[PATCH v2] tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`
The messages for assertions using hexadecimal numbers will be
easier to understand with `g_assert_cmphex`.
Cases changed : "cmpuint.*0x", "cmpuint.*<<"
Signed-off-by: Inès Varhol
---
tests/qtest/aspeed_fsi-test.c | 20 ++--
tests/qtest/cmsdk-apb-dualtimer-test.c | 2 +-
tests/qtest/cmsdk-apb-watchdog-test.c | 2 +-
tests/qtest/erst-test.c| 2 +-
tests/qtest/ivshmem-test.c | 10 +-
tests/qtest/libqos/ahci.c | 4 +-
tests/qtest/microbit-test.c| 46 -
tests/qtest/sse-timer-test.c | 4 +-
tests/qtest/stm32l4x5_exti-test.c | 138 -
tests/qtest/stm32l4x5_syscfg-test.c| 74 ++---
10 files changed, 151 insertions(+), 151 deletions(-)
diff --git a/tests/qtest/aspeed_fsi-test.c b/tests/qtest/aspeed_fsi-test.c
index b3020dd821..f5ab269972 100644
--- a/tests/qtest/aspeed_fsi-test.c
+++ b/tests/qtest/aspeed_fsi-test.c
@@ -63,22 +63,22 @@ static void test_fsi_setup(QTestState *s, uint32_t
base_addr)
/* Unselect FSI1 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
-g_assert_cmpuint(curval, ==, 0x0);
+g_assert_cmphex(curval, ==, 0x0);
/* Select FSI0 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
-g_assert_cmpuint(curval, ==, 0x1);
+g_assert_cmphex(curval, ==, 0x1);
} else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) {
/* Unselect FSI0 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
-g_assert_cmpuint(curval, ==, 0x0);
+g_assert_cmphex(curval, ==, 0x0);
/* Select FSI1 */
aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
-g_assert_cmpuint(curval, ==, 0x1);
+g_assert_cmphex(curval, ==, 0x1);
} else {
g_assert_not_reached();
}
@@ -145,11 +145,11 @@ static void test_fsi0_getcfam_addr0(const void *data)
aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
-g_assert_cmpuint(curval, ==, 0x1);
+g_assert_cmphex(curval, ==, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_STATUS);
-g_assert_cmpuint(curval, ==, 0x0);
+g_assert_cmphex(curval, ==, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_READ_DATA);
-g_assert_cmpuint(curval, ==, 0x152d02c0);
+g_assert_cmphex(curval, ==, 0x152d02c0);
}
static void test_fsi1_getcfam_addr0(const void *data)
@@ -168,11 +168,11 @@ static void test_fsi1_getcfam_addr0(const void *data)
aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
-g_assert_cmpuint(curval, ==, 0x2);
+g_assert_cmphex(curval, ==, 0x2);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_STATUS);
-g_assert_cmpuint(curval, ==, 0x0);
+g_assert_cmphex(curval, ==, 0x0);
curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_READ_DATA);
-g_assert_cmpuint(curval, ==, 0x152d02c0);
+g_assert_cmphex(curval, ==, 0x152d02c0);
}
int main(int argc, char **argv)
diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c
b/tests/qtest/cmsdk-apb-dualtimer-test.c
index ad6a758289..3b89bed97d 100644
--- a/tests/qtest/cmsdk-apb-dualtimer-test.c
+++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
@@ -69,7 +69,7 @@ static void test_dualtimer(void)
* tick VALUE should have wrapped round to 0x.
*/
clock_step(40);
-g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0x);
+g_assert_cmphex(readl(TIMER_BASE + TIMER1VALUE), ==, 0x);
/* Check that any write to INTCLR clears interrupt */
writel(TIMER_BASE + TIMER1INTCLR, 1);
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c
b/tests/qtest/cmsdk-apb-watchdog-test.c
index 2710cb17b8..00b5dbbc81 100644
--- a/tests/qtest/cmsdk-apb-watchdog-test.c
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
@@ -88,7 +88,7 @@ static void test_clock_change(void)
/* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
rcc = readl(SSYS_BASE + RCC);
-g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
+g_assert_cmphex(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
writel(SSYS_BASE + RCC, rcc);
diff --git a/tests/qtest/erst-test.c b/tests/qtest/erst-test.c
index c45bee7f05..36bbe122ab 100644
--- a/tests/qtest/erst-test.c
+++ b/tests/qtest/erst-test.c
@@ -109,7 +109,7 @@ static void setup_vm_cmd(ERSTState *s, const char *cmd)
g_assert_cmpuint(s->reg_barsize, ==, 16);
s->mem_bar = qpci_iomap(s->dev, 1, >mem_barsize);
-
Re: [PATCH] m25p80: Add support for the GD25WQ32E flash
PING
Hi all, could you have a look at this small patch?
See also:
https://patchew.org/QEMU/20240330203520.64892-1-giacomo.parmeggi...@gmail.com/
BR,
Giacomo Parmeggiani
On Sat, Mar 30, 2024 at 9:36 PM Giacomo Parmeggiani <
giacomo.parmeggi...@gmail.com> wrote:
> This introduces the GigaDevice GD25WQ32E flash, including the SFDP table
>
> Signed-off-by: Giacomo Parmeggiani
> ---
> hw/block/m25p80.c | 2 ++
> hw/block/m25p80_sfdp.c | 40
> hw/block/m25p80_sfdp.h | 2 ++
> 3 files changed, 44 insertions(+)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 8dec134832..6cc05b63e5 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -205,6 +205,8 @@ static const FlashPartInfo known_devices[] = {
> /* GigaDevice */
> { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
> { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
> +{ INFO("gd25wq32e", 0xc86516, 0, 64 << 10, 64, ER_4K),
> + .sfdp_read = m25p80_sfdp_gd25wq32e },
>
> /* Intel/Numonyx -- xxxs33b */
> { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
> diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
> index 6ee2cfaf11..cb0963328d 100644
> --- a/hw/block/m25p80_sfdp.c
> +++ b/hw/block/m25p80_sfdp.c
> @@ -406,3 +406,43 @@ static const uint8_t sfdp_is25wp256[] = {
> 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> };
> define_sfdp_read(is25wp256);
> +
> +/*
> + * GigaDevice
> + */
> +
> +static const uint8_t sfdp_gd25wq32e[] = {
> +0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
> +0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
> +0xc8, 0x00, 0x01, 0x03, 0x90, 0x00, 0x00, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xe5, 0x20, 0xf1, 0xff, 0xff, 0xff, 0xff, 0x01,
> +0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
> +0xee, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
> +0xff, 0xff, 0x00, 0xff, 0x0c, 0x20, 0x0f, 0x52,
> +0x10, 0xd8, 0x00, 0xff, 0x63, 0x92, 0xfd, 0xfe,
> +0x83, 0x2f, 0x26, 0x46, 0xec, 0x82, 0x18, 0x44,
> +0x7a, 0x75, 0x7a, 0x75, 0x04, 0xbd, 0xd5, 0x5c,
> +0x00, 0x06, 0x64, 0x00, 0x08, 0x10, 0x00, 0x00,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0x00, 0x36, 0x50, 0x16, 0x9e, 0xf9, 0x77, 0x64,
> +0xfc, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
> +};
> +define_sfdp_read(gd25wq32e);
> diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
> index 1733b56950..7d1f60f2ee 100644
> --- a/hw/block/m25p80_sfdp.h
> +++ b/hw/block/m25p80_sfdp.h
> @@ -29,4 +29,6 @@ uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
>
> uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
>
> +uint8_t m25p80_sfdp_gd25wq32e(uint32_t addr);
> +
> #endif
> --
> 2.32.1 (Apple Git-133)
>
>
--
*Giacomo Parmeggiani*
