Re: [Qemu-devel] qemu/pc-bios ppc_rom.bin
On 10/5/07, Natalia Portillo [EMAIL PROTECTED] wrote: It is desiderable for QEMU, no way, IT IS A MUST FOR QEMU, to be able to boot real firmware that boots in the real hardware QEMU is emulating. (That is, if QEMU emulates a PIIX4 with Pentium II, it must support booting a BIOS for P2+PIIX4, but must not support booting a BIOS for a Athlon+nForce) And, extrapolate what I say to PowerPC, MIPS, ARM, Alpha, Sparc, so on! Please send your patches to fix the bugs in this area to the list. ;-)
Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions
On Wed, Sep 26, 2007 at 11:23:30AM +0200, Aurelien Jarno wrote:
Hi,
As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
sdl and sdr instructions are not correctly implemented. In case of
exception the BadVAddr register gets the aligned address instead of the
unaligned original address.
In addition to that, the store instructions are generating the wrong
exception, AdEl instead of AdEs, because the current implementation
first do a load.
The patch below fixes that by accessing the bytes one by one, starting
by the unaligned original address.
The patch doesn't apply anymore to the current CVS. Please find below an
updated version.
Index: Makefile.target
===
RCS file: /sources/qemu/qemu/Makefile.target,v
retrieving revision 1.204
diff -u -d -p -r1.204 Makefile.target
--- Makefile.target 4 Oct 2007 21:53:54 - 1.204
+++ Makefile.target 6 Oct 2007 10:52:41 -
@@ -641,7 +641,7 @@ endif
ifeq ($(TARGET_BASE_ARCH), mips)
helper.o: cpu.h exec-all.h
op.o: op_template.c fop_template.c op_mem.c exec.h cpu.h
-op_helper.o: op_helper_mem.c exec.h softmmu_template.h cpu.h
+op_helper.o: exec.h softmmu_template.h cpu.h
translate.o: translate_init.c exec-all.h disas.h
endif
Index: target-mips/exec.h
===
RCS file: /sources/qemu/qemu/target-mips/exec.h,v
retrieving revision 1.36
diff -u -d -p -r1.36 exec.h
--- target-mips/exec.h 30 Sep 2007 01:58:33 - 1.36
+++ target-mips/exec.h 6 Oct 2007 10:52:42 -
@@ -100,36 +100,6 @@ void fpu_dump_state(CPUState *env, FILE
int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
int flags);
void dump_sc (void);
-void do_lwl_raw (uint32_t);
-void do_lwr_raw (uint32_t);
-uint32_t do_swl_raw (uint32_t);
-uint32_t do_swr_raw (uint32_t);
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
-void do_ldl_raw (uint64_t);
-void do_ldr_raw (uint64_t);
-uint64_t do_sdl_raw (uint64_t);
-uint64_t do_sdr_raw (uint64_t);
-#endif
-#if !defined(CONFIG_USER_ONLY)
-void do_lwl_user (uint32_t);
-void do_lwl_kernel (uint32_t);
-void do_lwr_user (uint32_t);
-void do_lwr_kernel (uint32_t);
-uint32_t do_swl_user (uint32_t);
-uint32_t do_swl_kernel (uint32_t);
-uint32_t do_swr_user (uint32_t);
-uint32_t do_swr_kernel (uint32_t);
-#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
-void do_ldl_user (uint64_t);
-void do_ldl_kernel (uint64_t);
-void do_ldr_user (uint64_t);
-void do_ldr_kernel (uint64_t);
-uint64_t do_sdl_user (uint64_t);
-uint64_t do_sdl_kernel (uint64_t);
-uint64_t do_sdr_user (uint64_t);
-uint64_t do_sdr_kernel (uint64_t);
-#endif
-#endif
void do_pmon (int function);
void dump_sc (void);
Index: target-mips/op_helper.c
===
RCS file: /sources/qemu/qemu/target-mips/op_helper.c,v
retrieving revision 1.63
diff -u -d -p -r1.63 op_helper.c
--- target-mips/op_helper.c 30 Sep 2007 01:58:33 - 1.63
+++ target-mips/op_helper.c 6 Oct 2007 10:52:42 -
@@ -62,18 +62,6 @@ void do_raise_exception_direct (uint32_t
do_raise_exception_direct_err (exception, 0);
}
-#define MEMSUFFIX _raw
-#include op_helper_mem.c
-#undef MEMSUFFIX
-#if !defined(CONFIG_USER_ONLY)
-#define MEMSUFFIX _user
-#include op_helper_mem.c
-#undef MEMSUFFIX
-#define MEMSUFFIX _kernel
-#include op_helper_mem.c
-#undef MEMSUFFIX
-#endif
-
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
#if TARGET_LONG_BITS HOST_LONG_BITS
/* Those might call libgcc functions. */
Index: target-mips/op_helper_mem.c
===
RCS file: target-mips/op_helper_mem.c
diff -N target-mips/op_helper_mem.c
--- target-mips/op_helper_mem.c 30 Sep 2007 01:58:33 - 1.9
+++ /dev/null 1 Jan 1970 00:00:00 -
@@ -1,301 +0,0 @@
-#undef DEBUG_OP
-
-#ifdef TARGET_WORDS_BIGENDIAN
-#define GET_LMASK(v) ((v) 3)
-#else
-#define GET_LMASK(v) (((v) 3) ^ 3)
-#endif
-
-void glue(do_lwl, MEMSUFFIX) (uint32_t tmp)
-{
-#if defined (DEBUG_OP)
-target_ulong sav = T0;
-#endif
-
-switch (GET_LMASK(T0)) {
-case 0:
-T0 = (int32_t)tmp;
-break;
-case 1:
-T0 = (int32_t)((tmp 8) | (T1 0x00FF));
-break;
-case 2:
-T0 = (int32_t)((tmp 16) | (T1 0x));
-break;
-case 3:
-T0 = (int32_t)((tmp 24) | (T1 0x00FF));
-break;
-}
-#if defined (DEBUG_OP)
-if (logfile) {
-fprintf(logfile, %s: TARGET_FMT_lx - %08x TARGET_FMT_lx =
TARGET_FMT_lx \n,
-__func__, sav, tmp, T1, T0);
-}
-#endif
-RETURN();
-}
-
-void glue(do_lwr, MEMSUFFIX) (uint32_t tmp)
-{
-#if defined (DEBUG_OP)
-target_ulong sav = T0;
-#endif
-
-switch (GET_LMASK(T0)) {
-case 0:
-T0 = (int32_t)((tmp 24) | (T1 0xFF00));
-break;
-case 1:
-T0 =
[Qemu-devel] qemu/hw sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/10/06 11:24:18 Modified files: hw : sun4m.c Log message: Support for loading a real BIOS image (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemur1=1.52r2=1.53
[Qemu-devel] qemu vl.h hw/slavio_timer.c hw/sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/10/06 11:25:43 Modified files: . : vl.h hw : slavio_timer.c sun4m.c Log message: Implement user mode for timers CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.274r2=1.275 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_timer.c?cvsroot=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemur1=1.53r2=1.54
[Qemu-devel] qemu sparc-dis.c sparc.ld sparc64.ld hw/apb_pci...
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl blueswir1 07/10/06 11:28:21 Modified files: . : sparc-dis.c sparc.ld sparc64.ld hw : apb_pci.c cs4231.c esp.c iommu.c slavio_intctl.c slavio_misc.c slavio_serial.c slavio_timer.c sun4m.c sun4u.c tcx.c Log message: More detabification CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/sparc-dis.c?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/sparc.ld?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/sparc64.ld?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/apb_pci.c?cvsroot=qemur1=1.7r2=1.8 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/cs4231.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/esp.c?cvsroot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/iommu.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl.c?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_misc.c?cvsroot=qemur1=1.9r2=1.10 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_serial.c?cvsroot=qemur1=1.24r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_timer.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemur1=1.54r2=1.55 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4u.c?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/tcx.c?cvsroot=qemur1=1.23r2=1.24
[Qemu-devel] [PATCH] sparc32 slaveio_timer user timer fixes
Some more user timer fixes.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.17
diff -p -u -r1.17 slavio_timer.c
--- hw/slavio_timer.c 6 Oct 2007 11:28:21 - 1.17
+++ hw/slavio_timer.c 6 Oct 2007 12:28:53 -
@@ -54,16 +54,24 @@ typedef struct SLAVIO_TIMERState {
ptimer_state *timer;
uint32_t count, counthigh, reached;
uint64_t limit;
-int stopped;
-int mode; // 0 = processor, 1 = user, 2 = system
+// processor only
+int running;
+struct SLAVIO_TIMERState *master;
+int slave_index;
+// system only
struct SLAVIO_TIMERState *slave[MAX_CPUS];
uint32_t slave_mode;
} SLAVIO_TIMERState;
#define TIMER_MAXADDR 0x1f
-#define TIMER_SIZE (TIMER_MAXADDR + 1)
+#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10
+static int slavio_timer_is_user(SLAVIO_TIMERState *s)
+{
+return s-master (s-master-slave_mode (1 s-slave_index));
+}
+
// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
@@ -84,9 +92,10 @@ static void slavio_timer_irq(void *opaqu
slavio_timer_get_out(s);
DPRINTF(callback: count %x%08x\n, s-counthigh, s-count);
-s-reached = 0x8000;
-if (s-mode != 1)
+if (!slavio_timer_is_user(s)) {
+s-reached = 0x8000;
qemu_irq_raise(s-irq);
+}
}
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
@@ -99,35 +108,39 @@ static uint32_t slavio_timer_mem_readl(v
case 0:
// read limit (system counter mode) or read most signifying
// part of counter (user mode)
-if (s-mode != 1) {
+if (slavio_timer_is_user(s)) {
+// read user timer MSW
+slavio_timer_get_out(s);
+ret = s-counthigh;
+} else {
+// read limit
// clear irq
qemu_irq_lower(s-irq);
s-reached = 0;
ret = s-limit 0x7fff;
}
-else {
-slavio_timer_get_out(s);
-ret = s-counthigh 0x7fff;
-}
break;
case 1:
// read counter and reached bit (system mode) or read lsbits
// of counter (user mode)
slavio_timer_get_out(s);
-if (s-mode != 1)
-ret = (s-count 0x7fff) | s-reached;
-else
-ret = s-count;
+if (slavio_timer_is_user(s)) // read user timer LSW
+ret = s-count 0xffe00;
+else // read limit
+ret = (s-count 0x7e00) | s-reached;
break;
case 3:
+// only available in processor counter/timer
// read start/stop status
-ret = s-stopped;
+ret = s-running;
break;
case 4:
+// only available in system counter
// read user/system mode
ret = s-slave_mode;
break;
default:
+DPRINTF(invalid read address TARGET_FMT_plx \n, addr);
ret = 0;
break;
}
@@ -146,20 +159,31 @@ static void slavio_timer_mem_writel(void
saddr = (addr TIMER_MAXADDR) 2;
switch (saddr) {
case 0:
-if (s-mode == 1) {
-// set user counter limit MSW, reset counter
+if (slavio_timer_is_user(s)) {
+// set user counter MSW, reset counter
qemu_irq_lower(s-irq);
-s-limit = 0xfe00ULL;
-s-limit |= (uint64_t)val 32;
+s-limit = 0x7e00ULL;
+DPRINTF(processor %d user timer reset\n, s-slave_index);
+ptimer_set_limit(s-timer, s-limit 9, 1);
+} else {
+// set limit, reset counter
+qemu_irq_lower(s-irq);
+s-limit = val 0x7e00ULL;
if (!s-limit)
-s-limit = 0x7e00ULL;
+s-limit = 0x7e00ULL;
ptimer_set_limit(s-timer, s-limit 9, 1);
-break;
}
-// set limit, reset counter
-reload = 1;
-qemu_irq_lower(s-irq);
-// fall through
+break;
+case 1:
+if (slavio_timer_is_user(s)) {
+// set user counter LSW, reset counter
+qemu_irq_lower(s-irq);
+s-limit = 0x7e00ULL;
+DPRINTF(processor %d user timer reset\n, s-slave_index);
+ptimer_set_limit(s-timer, s-limit 9, 1);
+} else
+DPRINTF(not user timer\n);
+break;
case 2:
// set limit without resetting counter
s-limit = val 0x7e00ULL;
@@ -167,52 +191,42 @@ static void slavio_timer_mem_writel(void
s-limit = 0x7e00ULL;
ptimer_set_limit(s-timer, s-limit 9, reload);
break;
-case 1:
-// set user counter limit LSW, reset counter
-if (s-mode == 1) {
-
[Qemu-devel] strange graphics message
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 does anyone know what this screen means? ===| DirectFB 1.0.0 |=== (c) 2001-2007 The DirectFB Organization (directfb.org) (c) 2000-2004 Convergence (integrated media) GmbH (*) DirectFB/Core: Single Application Core. (2007-09-07 00:13) (*) Direct/Memcpy: Using Generic 64bit memcpy() ===| DirectFB 1.0.0 |=== (c) 2001-2007 The DirectFB Organization (directfb.org) (c) 2000-2004 Convergence (integrated media) GmbH The host os is running the NVidia proprietary driver on AMD64. A while ago (maybe a year or so) I ran this same OS install disk under qemu and it ran. But on my AMD64/NVidia box, I am getting this bizarre message and the console does not come back. I have to ctrl+c to escape out. What is the problem/solution here? - -- Cheers, Matt Young [EMAIL PROTECTED] GPG Public Key: http://youngdev.net/?page=gpg GPG Fingerprint: 980C 032B 272D 848D B2F7 ED85 38B3 EDCB 3C5D 7106 -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.7 (GNU/Linux) iD8DBQFHB7bTOLPtyzxdcQYRAqa9AKCKVJqmolcENmmkG57ksUg8v4ftogCgli42 Ci4FfuJ+D8buK0IW4Sjum5M= =vLYG -END PGP SIGNATURE-
[Qemu-devel] qemu-system-m68k and booting m68k images
Two questions: 1. Why does qemu-system-m68k require a kernel image? 2. Is support planned for booting m68k bootable images, e.g. floppy images, harddrive images? -- Ian Graeme Hilt
