Re: [Qemu-devel] [PATCH 06/21] vl: add a tmp pointer so that a handler can delete the entry to which it belongs.
2010/12/8 Isaku Yamahata yamah...@valinux.co.jp:
QLIST_FOREACH_SAFE?
Thanks! So, it should be,
QLIST_FOREACH_SAFE(e, vm_change_state_head, entries, ne) {
e-cb(e-opaque, running, reason);
}
I'll put it in the next spin.
Yoshi
On Thu, Nov 25, 2010 at 03:06:45PM +0900, Yoshiaki Tamura wrote:
By copying the next entry to a tmp pointer,
qemu_del_vm_change_state_handler() can be called in the handler.
Signed-off-by: Yoshiaki Tamura tamura.yoshi...@lab.ntt.co.jp
---
vl.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index 805e11f..6b6aec0 100644
--- a/vl.c
+++ b/vl.c
@@ -1073,11 +1073,12 @@ void
qemu_del_vm_change_state_handler(VMChangeStateEntry *e)
void vm_state_notify(int running, int reason)
{
- VMChangeStateEntry *e;
+ VMChangeStateEntry *e, *ne;
trace_vm_state_notify(running, reason);
- for (e = vm_change_state_head.lh_first; e; e = e-entries.le_next) {
+ for (e = vm_change_state_head.lh_first; e; e = ne) {
+ ne = e-entries.le_next;
e-cb(e-opaque, running, reason);
}
}
--
1.7.1.2
--
yamahata
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Re: [Qemu-devel] State of EHCI emulation for QEMU
Hi, - command line must look like this: ... -drive if=none,id=usbstick,file=/path/to/image \ -device usb-storage,bus=ehci.0,drive=usbstick ie. register driver device referencing it, and there was a typo id-if I'll fix. - long-term, -usb should become a shorthand for -device usb-uhci,id=uhci -device usb-ehci,id=ehci (at least for x86) Hmm, I'd tend to leave '-M pc' as-is and enable ehci by default in the upcoming q35 emulation, especially in case both make it into 0.15. Unfortunately, msd is not yet magically healed: non queue head request in async schedule processing error - resetting ehci HC Yea, I've seen a flaw in async handling. Just need to dig some more into the code to fix it properly, also the packet workflow (including async handling) is one of the spots where the qemu usb subsystem needs some work ... PS: Your tree lacks conversion of usb-musb.c. Huh? 'git diff kiszka/master kiszka/ehci hw/usb-musb.c' is empty. cheers, Gerd
Re: [Qemu-devel] State of EHCI emulation for QEMU
Am 08.12.2010 09:18, Gerd Hoffmann wrote: Hi, - command line must look like this: ... -drive if=none,id=usbstick,file=/path/to/image \ -device usb-storage,bus=ehci.0,drive=usbstick ie. register driver device referencing it, and there was a typo id-if I'll fix. - long-term, -usb should become a shorthand for -device usb-uhci,id=uhci -device usb-ehci,id=ehci (at least for x86) Hmm, I'd tend to leave '-M pc' as-is and enable ehci by default in the upcoming q35 emulation, especially in case both make it into 0.15. I'm was concerned about the semantic of -usb. If ehciuhci is going to be on by default in the future, we should obsolete and finally drop this switch. Unfortunately, msd is not yet magically healed: non queue head request in async schedule processing error - resetting ehci HC Yea, I've seen a flaw in async handling. Just need to dig some more into the code to fix it properly, also the packet workflow (including async handling) is one of the spots where the qemu usb subsystem needs some work ... PS: Your tree lacks conversion of usb-musb.c. Huh? 'git diff kiszka/master kiszka/ehci hw/usb-musb.c' is empty. The breakage comes from one of your patches. Just try to build an ARM target. Jan signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] State of EHCI emulation for QEMU
Hi, It appears that the import of the ehci code to spice has completely lost the development history and code contributions - from the original version by Mark Burkley through the work I've done on it. Would you mind pulling in the patch history instead of just the final code? I've first tried to rebase the ehci branch to latest master exactly to keep the history. Was quite messy with lots of conflicts though, so I gave up. For review upstream merge having the whole history isn't that helpful anyway. cheers, Gerd
Re: [Qemu-devel] State of EHCI emulation for QEMU
Am 08.12.2010 09:26, Gerd Hoffmann wrote: Hi, It appears that the import of the ehci code to spice has completely lost the development history and code contributions - from the original version by Mark Burkley through the work I've done on it. Would you mind pulling in the patch history instead of just the final code? I've first tried to rebase the ehci branch to latest master exactly to keep the history. Was quite messy with lots of conflicts though, so I gave up. For review upstream merge having the whole history isn't that helpful anyway. I'm was regularly merging master into ehci, and that worked quite well. For the development phase, it might be nice to keep the history if possible. But I agree that we need a clean series once upstream submission is in sight. Jan signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PATTCH v2 4/6] pci/aer: fix interrupt on config write
From: Michael S. Tsirkin m...@redhat.com
config write handling for aer seems broken:
For example, it won't clear a level interrupt
when command register is set to 0.
Make it match the spec: level should equal
the logical or of enabled bits, msi only
be sent when the logical or changes.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Isaku Yamahata yamah...@valinux.co.jp
---
- reorder
- abort() instead of assert(0)
---
hw/pcie_aer.c | 46 +-
1 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index bc98da0..389e9d5 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -762,43 +762,31 @@ void pcie_aer_root_reset(PCIDevice *dev)
*/
}
-static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status)
-{
-return
-((cmd PCI_ERR_ROOT_CMD_COR_EN) (status PCI_ERR_ROOT_COR_RCV)) ||
-((cmd PCI_ERR_ROOT_CMD_NONFATAL_EN)
- (status PCI_ERR_ROOT_NONFATAL_RCV)) ||
-((cmd PCI_ERR_ROOT_CMD_FATAL_EN)
- (status PCI_ERR_ROOT_FATAL_RCV));
-}
-
void pcie_aer_root_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len,
uint32_t root_cmd_prev)
{
uint8_t *aer_cap = dev-config + dev-exp.aer_cap;
-
-/* root command register */
+uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
+uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status);
uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
-if (root_cmd PCI_ERR_ROOT_CMD_EN_MASK) {
-/* 6.2.4.1.2 Interrupt Generation */
+/* 6.2.4.1.2 Interrupt Generation */
+if (!msix_enabled(dev) !msi_enabled(dev)) {
+qemu_set_irq(dev-irq[dev-exp.aer_intx], !!(root_cmd enabled_cmd));
+return;
+}
-/* 0 - 1 */
-uint32_t root_cmd_set = ~root_cmd_prev root_cmd;
-uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
-bool trigger = pcie_aer_root_does_trigger(root_cmd_set, root_status);
+if ((root_cmd_prev enabled_cmd) || !(root_cmd enabled_cmd)) {
+/* Send MSI on transition from false to true. */
+return;
+}
-if (msix_enabled(dev)) {
-if (trigger) {
-msix_notify(dev, pcie_aer_root_get_vector(dev));
-}
-} else if (msi_enabled(dev)) {
-if (trigger) {
-msi_notify(dev, pcie_aer_root_get_vector(dev));
-}
-} else {
-qemu_set_irq(dev-irq[dev-exp.aer_intx], trigger);
-}
+if (msix_enabled(dev)) {
+msix_notify(dev, pcie_aer_root_get_vector(dev));
+} else if (msi_enabled(dev)) {
+msi_notify(dev, pcie_aer_root_get_vector(dev));
+} else {
+abort();
}
}
--
1.7.1.1
[Qemu-devel] [PATTCH v2 2/6] Makefile: make msix/msi depend on CONFIG_PCI
From: Michael S. Tsirkin m...@redhat.com Possible now that pci is not depending on these. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- Makefile.objs |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/Makefile.objs b/Makefile.objs index 04625eb..d1e63ce 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -168,7 +168,8 @@ hw-obj-$(CONFIG_VIRTIO) += virtio.o virtio-console.o hw-obj-y += fw_cfg.o # FIXME: Core PCI code and its direct dependencies are required by the # QMP query-pci command. -hw-obj-y += pci.o pci_bridge.o msix.o msi.o +hw-obj-y += pci.o pci_bridge.o +hw-obj-$(CONFIG_PCI) += msix.o msi.o hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o hw-obj-y += watchdog.o -- 1.7.1.1
[Qemu-devel] [PATTCH v2 6/6] pci/aer: factor out common code
From: Michael S. Tsirkin m...@redhat.com
Same logic is used to assert interrupts
and send msix messages, so add a static functin for this.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/pcie_aer.c | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 0fb21ab..2ceb00a 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -273,6 +273,17 @@ static uint32_t pcie_aer_status_to_cmd(uint32_t status)
return cmd;
}
+static void pcie_aer_root_notify(PCIDevice *dev)
+{
+if (msix_enabled(dev)) {
+msix_notify(dev, pcie_aer_root_get_vector(dev));
+} else if (msi_enabled(dev)) {
+msi_notify(dev, pcie_aer_root_get_vector(dev));
+} else {
+qemu_set_irq(dev-irq[dev-exp.aer_intx], 1);
+}
+}
+
/*
* 6.2.6 Error Message Control
* Figure 6-3
@@ -344,13 +355,7 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
return;
}
-if (msix_enabled(dev)) {
-msix_notify(dev, pcie_aer_root_get_vector(dev));
-} else if (msi_enabled(dev)) {
-msi_notify(dev, pcie_aer_root_get_vector(dev));
-} else {
-qemu_set_irq(dev-irq[dev-exp.aer_intx], 1);
-}
+pcie_aer_root_notify(dev);
}
/*
@@ -760,13 +765,7 @@ void pcie_aer_root_write_config(PCIDevice *dev,
return;
}
-if (msix_enabled(dev)) {
-msix_notify(dev, pcie_aer_root_get_vector(dev));
-} else if (msi_enabled(dev)) {
-msi_notify(dev, pcie_aer_root_get_vector(dev));
-} else {
-abort();
-}
+pcie_aer_root_notify(dev);
}
static const VMStateDescription vmstate_pcie_aer_err = {
--
1.7.1.1
[Qemu-devel] [PATTCH v2 3/6] pci/aer: fix error injection
From: Michael S. Tsirkin m...@redhat.com
Fix the injection logic upon aer message to follow 6.2.4.1.2 more
closely: specifically only send an msi interrupt when the logical or of
the enabled bits changed, not when a bit which was previously clear
becomes set.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Isaku Yamahata yamah...@valinux.co.jp
---
Changes v1 - v2:
- reorder
---
hw/pcie_aer.c | 51 +++
1 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 80cc438..bc98da0 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -257,6 +257,22 @@ static unsigned int pcie_aer_root_get_vector(PCIDevice
*dev)
return (root_status PCI_ERR_ROOT_IRQ) PCI_ERR_ROOT_IRQ_SHIFT;
}
+/* Given a status register, get corresponding bits in the command register */
+static uint32_t pcie_aer_status_to_cmd(uint32_t status)
+{
+uint32_t cmd = 0;
+if (status PCI_ERR_ROOT_COR_RCV) {
+cmd |= PCI_ERR_ROOT_CMD_COR_EN;
+}
+if (status PCI_ERR_ROOT_NONFATAL_RCV) {
+cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN;
+}
+if (status PCI_ERR_ROOT_FATAL_RCV) {
+cmd |= PCI_ERR_ROOT_CMD_FATAL_EN;
+}
+return cmd;
+}
+
/*
* return value:
* true: error message is sent up
@@ -272,14 +288,14 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
uint16_t cmd;
uint8_t *aer_cap;
uint32_t root_cmd;
-uint32_t root_status;
+uint32_t root_status, prev_status;
bool msi_trigger;
msg_sent = false;
cmd = pci_get_word(dev-config + PCI_COMMAND);
aer_cap = dev-config + dev-exp.aer_cap;
root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
-root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
+prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
msi_trigger = false;
if (cmd PCI_COMMAND_SERR) {
@@ -337,20 +353,23 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
}
pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status);
-if (root_cmd msg-severity) {
-/* 6.2.4.1.2 Interrupt Generation */
-if (msix_enabled(dev)) {
-if (msi_trigger) {
-msix_notify(dev, pcie_aer_root_get_vector(dev));
-}
-} else if (msi_enabled(dev)) {
-if (msi_trigger) {
-msi_notify(dev, pcie_aer_root_get_vector(dev));
-}
-} else {
-qemu_set_irq(dev-irq[dev-exp.aer_intx], 1);
-}
-msg_sent = true;
+/* 6.2.4.1.2 Interrupt Generation */
+/* All the above did was set some bits in the status register.
+ * Specifically these that match message severity.
+ * The below code relies on this fact. */
+if (!(root_cmd msg-severity) ||
+(pcie_aer_status_to_cmd(prev_status) root_cmd)) {
+/* Condition is not being set or was already true so nothing to do. */
+return msg_sent;
+}
+
+msg_sent = true;
+if (msix_enabled(dev)) {
+msix_notify(dev, pcie_aer_root_get_vector(dev));
+} else if (msi_enabled(dev)) {
+msi_notify(dev, pcie_aer_root_get_vector(dev));
+} else {
+qemu_set_irq(dev-irq[dev-exp.aer_intx], 1);
}
return msg_sent;
}
--
1.7.1.1
[Qemu-devel] [PATTCH v2 0/6] pcie aer fixes
I respined the patch series by mst for bisectability. Changes v1 - v2: - reorder patches for bisectability - s/assert/trigger/ to avoid name conflict - abort() instead of assert(0) Original patch description: Here are a bunch of fixes and cleanups to aer interrupt injection. Compile tested only, issues were found by reading the code and spec. Michael S. Tsirkin (6): pci: untangle pci/msi dependency Makefile: make msix/msi depend on CONFIG_PCI pci/aer: fix error injection pci/aer: fix interrupt on config write pci/aer: remove dead code pci/aer: factor out common code Makefile.objs |3 +- hw/pci.c | 19 -- hw/pci.h |3 -- hw/pcie.c |8 +++-- hw/pcie_aer.c | 111 ++-- 5 files changed, 59 insertions(+), 85 deletions(-)
[Qemu-devel] [PATTCH v2 5/6] pci/aer: remove dead code
From: Michael S. Tsirkin m...@redhat.com
Remove some unused variables and return values.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Isaku Yamahata yamah...@valinux.co.jp
---
changes v1 - v2:
- reorder
---
hw/pcie_aer.c | 25 ++---
1 files changed, 2 insertions(+), 23 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 389e9d5..0fb21ab 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -274,29 +274,21 @@ static uint32_t pcie_aer_status_to_cmd(uint32_t status)
}
/*
- * return value:
- * true: error message is sent up
- * false: error message is masked
- *
* 6.2.6 Error Message Control
* Figure 6-3
* root port part
*/
-static bool pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
+static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
{
-bool msg_sent;
uint16_t cmd;
uint8_t *aer_cap;
uint32_t root_cmd;
uint32_t root_status, prev_status;
-bool msi_trigger;
-msg_sent = false;
cmd = pci_get_word(dev-config + PCI_COMMAND);
aer_cap = dev-config + dev-exp.aer_cap;
root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
-msi_trigger = false;
if (cmd PCI_COMMAND_SERR) {
/* System Error.
@@ -315,25 +307,14 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
if (root_status PCI_ERR_ROOT_COR_RCV) {
root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
} else {
-if (root_cmd PCI_ERR_ROOT_CMD_COR_EN) {
-msi_trigger = true;
-}
pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg-source_id);
}
root_status |= PCI_ERR_ROOT_COR_RCV;
break;
case PCI_ERR_ROOT_CMD_NONFATAL_EN:
-if (!(root_status PCI_ERR_ROOT_NONFATAL_RCV)
-root_cmd PCI_ERR_ROOT_CMD_NONFATAL_EN) {
-msi_trigger = true;
-}
root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
break;
case PCI_ERR_ROOT_CMD_FATAL_EN:
-if (!(root_status PCI_ERR_ROOT_FATAL_RCV)
-root_cmd PCI_ERR_ROOT_CMD_FATAL_EN) {
-msi_trigger = true;
-}
if (!(root_status PCI_ERR_ROOT_UNCOR_RCV)) {
root_status |= PCI_ERR_ROOT_FIRST_FATAL;
}
@@ -360,10 +341,9 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
if (!(root_cmd msg-severity) ||
(pcie_aer_status_to_cmd(prev_status) root_cmd)) {
/* Condition is not being set or was already true so nothing to do. */
-return msg_sent;
+return;
}
-msg_sent = true;
if (msix_enabled(dev)) {
msix_notify(dev, pcie_aer_root_get_vector(dev));
} else if (msi_enabled(dev)) {
@@ -371,7 +351,6 @@ static bool pcie_aer_msg_root_port(PCIDevice *dev, const
PCIEAERMsg *msg)
} else {
qemu_set_irq(dev-irq[dev-exp.aer_intx], 1);
}
-return msg_sent;
}
/*
--
1.7.1.1
Re: [Qemu-devel] [PATCH 1/1] qemu-img.c: Clean up handling of image size in img_create()
Am 07.12.2010 21:36, schrieb Stefan Hajnoczi:
On Tue, Dec 7, 2010 at 5:39 PM, jes.soren...@redhat.com wrote:
// The size for the image must always be specified, with one exception:
// If we are using a backing file, we can obtain the size from there
-if (get_option_parameter(param, BLOCK_OPT_SIZE)-value.n == -1) {
-
+if (get_option_parameter(param, BLOCK_OPT_SIZE)-value.n == 0) {
QEMUOptionParameter *backing_file =
get_option_parameter(param, BLOCK_OPT_BACKING_FILE);
QEMUOptionParameter *backing_fmt =
Today it is possible to create 0 byte sized images. Your patch will
change that:
If there is a backing file, then the size will be taken from the backing file.
If there is no backing file, then an error about missing size will be
printed, even though a size of 0 has been given.
I can think of one use case for it: You can store the VM state on a
zero-sized qcow2 image for internal snapshots.
Otherwise it's probably rather useless, but we have supported it for a
long time, so I wouldn't remove it. People have actually noticed in the
past when something was broken with it.
Kevin
Re: [Qemu-devel] [PATCH 1/6] [RFC] Emulation of GRLIB GPTimer as defined in GRLIB IP Core User's Manual.
On Tue, Dec 07, 2010 at 10:55:33AM +0100, Fabien Chouteau wrote:
On 12/06/2010 06:12 PM, Blue Swirl wrote:
On Mon, Dec 6, 2010 at 9:26 AM, Fabien Chouteauchout...@adacore.com
wrote:
Signed-off-by: Fabien Chouteauchout...@adacore.com
---
hw/grlib_gptimer.c | 448
1 files changed, 448 insertions(+), 0 deletions(-)
diff --git a/hw/grlib_gptimer.c b/hw/grlib_gptimer.c
new file mode 100644
index 000..41edbe4
--- /dev/null
+++ b/hw/grlib_gptimer.c
@@ -0,0 +1,448 @@
+/*
+ * QEMU GRLIB GPTimer Emulator
+ *
+ * Copyright (c) 2010 AdaCore
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
a copy
+ * of this software and associated documentation files (the Software),
to deal
+ * in the Software without restriction, including without limitation the
rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
IN
+ * THE SOFTWARE.
+ */
+
+#include sysbus.h
+#include qemu-timer.h
+
+#include grlib.h
+
+/* #define DEBUG_TIMER */
The usual convention is
//#define DEBUG_TIMER
for easy editing.
Actually, it's easier for me with the /* */, but OK.
However, very often the much more powerful tracepoints can replace
debug statements.
+
+#ifdef DEBUG_TIMER
+#define DPRINTF(fmt, ...) \
+do { printf(GPTIMER: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+#define UNIT_REG_SIZE16 /* Size of memory mapped regs for the
unit */
+#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a
GPTimer */
+
+#define GPTIMER_MAX_TIMERS 8
+
+/* GPTimer Config register fields */
+#define GPTIMER_ENABLE (1 0)
+#define GPTIMER_RESTART (1 1)
+#define GPTIMER_LOAD(1 2)
+#define GPTIMER_INT_ENABLE (1 3)
+#define GPTIMER_INT_PENDING (1 4)
+#define GPTIMER_CHAIN (1 5) /* Not supported */
+#define GPTIMER_DEBUG_HALT (1 6) /* Not supported */
+
+/* Memory mapped register offsets */
+#define SCALER_OFFSET 0x00
+#define SCALER_RELOAD_OFFSET 0x04
+#define CONFIG_OFFSET 0x08
+#define COUNTER_OFFSET0x00
+#define COUNTER_RELOAD_OFFSET 0x04
+#define TIMER_BASE0x10
+
+typedef struct GPTimer GPTimer;
+typedef struct GPTimerUnit GPTimerUnit;
+
+struct GPTimer
+{
+QEMUBH *bh;
+struct ptimer_state *ptimer;
+
+qemu_irq irq;
+int id;
+GPTimerUnit *unit;
+
+/* registers */
+uint32_t counter;
+uint32_t reload;
+uint32_t config;
+};
+
+struct GPTimerUnit
+{
+SysBusDevice busdev;
+
+uint32_t nr_timers; /* Number of timers available */
+uint32_t freq_hz; /* System frequency */
+uint32_t irq_line; /* Base irq line */
+
+GPTimer *timers;
+
+/* registers */
+uint32_t scaler;
+uint32_t reload;
+uint32_t config;
+};
+
+DeviceState *grlib_gptimer_create(target_phys_addr_t base,
+ uint32_tnr_timers,
+ uint32_tfreq,
+ qemu_irq *cpu_irqs,
+ int base_irq)
This function belongs to leon3.c.
I don't see why. GPTimer is a peripheral and you may want to use it in
an other system.
This might depend a bit on taste, but I agree with Blue that we shouldn't
clutter the device models with this kind of instantiator helper calls.
IMO it's better to put them higher up (e.g board code or similar).
+{
+DeviceState *dev;
+int i;
+_ir
+dev = qdev_create(NULL, grlib,gptimer);
+qdev_prop_set_uint32(dev, nr-timers, nr_timers);
+qdev_prop_set_uint32(dev, frequency, freq);
+qdev_prop_set_uint32(dev, irq-line, base_irq);
Base irq is not device property, but part of board configuration. Thus
leon3.c should just passcpu_irqs[base_irq] to this function.
I need this
[Qemu-devel] [PATCH v2 1/1] qemu-img.c: Clean up handling of image size in img_create()
From: Jes Sorensen jes.soren...@redhat.com
This cleans up the handling of image size in img_create() by parsing
the value early, and then only setting it once if a value has been
added as the last argument to the command line.
Signed-off-by: Jes Sorensen jes.soren...@redhat.com
---
qemu-img.c | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/qemu-img.c b/qemu-img.c
index d146d8c..9986004 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -282,6 +282,7 @@ static int add_old_style_options(const char *fmt,
QEMUOptionParameter *list,
static int img_create(int argc, char **argv)
{
int c, ret = 0;
+uint64_t img_size = -1;
const char *fmt = raw;
const char *base_fmt = NULL;
const char *filename;
@@ -329,6 +330,11 @@ static int img_create(int argc, char **argv)
}
filename = argv[optind++];
+/* Get image size, if specified */
+if (optind argc) {
+img_size = strtosz(argv[optind++], NULL);
+}
+
if (options !strcmp(options, ?)) {
ret = print_block_option_help(filename, fmt);
goto out;
@@ -356,7 +362,8 @@ static int img_create(int argc, char **argv)
/* Create parameter list with default values */
param = parse_option_parameters(, create_options, param);
-set_option_parameter_int(param, BLOCK_OPT_SIZE, -1);
+
+set_option_parameter_int(param, BLOCK_OPT_SIZE, img_size);
/* Parse -o options */
if (options) {
@@ -368,11 +375,6 @@ static int img_create(int argc, char **argv)
}
}
-/* Add size to parameters */
-if (optind argc) {
-set_option_parameter(param, BLOCK_OPT_SIZE, argv[optind++]);
-}
-
/* Add old-style options to parameters */
ret = add_old_style_options(fmt, param, base_filename, base_fmt);
if (ret 0) {
--
1.7.3.2
Re: [Qemu-devel] [PATCH 1/1] qemu-img.c: Clean up handling of image size in img_create()
On 12/08/10 09:54, Kevin Wolf wrote: Am 07.12.2010 21:36, schrieb Stefan Hajnoczi: Today it is possible to create 0 byte sized images. Your patch will change that: If there is a backing file, then the size will be taken from the backing file. If there is no backing file, then an error about missing size will be printed, even though a size of 0 has been given. I can think of one use case for it: You can store the VM state on a zero-sized qcow2 image for internal snapshots. Otherwise it's probably rather useless, but we have supported it for a long time, so I wouldn't remove it. People have actually noticed in the past when something was broken with it. Ok that is fair, I have just posted an updated version which should do the right thing. Shows up it made the patch even simpler :) Cheers, Jes
Re: [Qemu-devel] Re: [RFC][PATCH v5 01/21] Move code related to fd handlers into utility functions
On 12/08/10 10:15, Stefan Hajnoczi wrote: On Tue, Dec 07, 2010 at 04:02:03PM +0100, Jes Sorensen wrote: Anything to avoid qemu_set_fd_handler17() at some point. I think using __qemu_set_fd_handler() encourages people to modify that code rather than copy it. I agree that qemu_set_fd_handler3() could be named something more meaningful. Unfortunately we can't use __qemu_set_fd_handler() because the C language standard reserves identifiers that start with double underscore for the standard library. The Linux kernel gets away with it because the code is freestanding but that doesn't apply to QEMU. Hmmm you sure that is actually a rule, rather than a convention? Either way, we can use 3 underscores, or leave the function static, in which case the C library names are a non issue. Cheers, Jes
Re: [Qemu-devel] Re: [RFC][PATCH v5 01/21] Move code related to fd handlers into utility functions
On Wed, Dec 08, 2010 at 10:17:50AM +0100, Jes Sorensen wrote: On 12/08/10 10:15, Stefan Hajnoczi wrote: On Tue, Dec 07, 2010 at 04:02:03PM +0100, Jes Sorensen wrote: Anything to avoid qemu_set_fd_handler17() at some point. I think using __qemu_set_fd_handler() encourages people to modify that code rather than copy it. I agree that qemu_set_fd_handler3() could be named something more meaningful. Unfortunately we can't use __qemu_set_fd_handler() because the C language standard reserves identifiers that start with double underscore for the standard library. The Linux kernel gets away with it because the code is freestanding but that doesn't apply to QEMU. Hmmm you sure that is actually a rule, rather than a convention? Either way, we can use 3 underscores, or leave the function static, in which case the C library names are a non issue. From 7.1.3 Reserved identifiers: All identifiers that begin with an underscore and either an uppercase letter or another underscore are always reserved for any use. and All identifiers that begin with an underscore are always reserved for use as identifiers with file scope in both the ordinary and tag name spaces. That includes three or more underscores too. Stefan
Re: [Qemu-devel] Re: [RFC][PATCH v5 01/21] Move code related to fd handlers into utility functions
On 12/08/10 10:23, Stefan Hajnoczi wrote: From 7.1.3 Reserved identifiers: All identifiers that begin with an underscore and either an uppercase letter or another underscore are always reserved for any use. and All identifiers that begin with an underscore are always reserved for use as identifiers with file scope in both the ordinary and tag name spaces. That includes three or more underscores too. Ok, I never hit problems with this, but ok we can name it do_qemu_set_fd_handler() instead. That would go with the existing naming conventions used in many places throughout the code. Cheers, Jes
[Qemu-devel] Re: [PATCH 0/4] qemu-img: Fail creation if backing format is invalid
Am 07.12.2010 10:35, schrieb Stefan Hajnoczi: This patch series adds a check to validate the backing format before creating an image file. This ensures we provide a clear error message as early as possible when an unsupported format is used. The first three patches clean up code on the way and the last patch makes the actual backing format validation change. Thanks, applied all to the block branch. Kevin
Re: [Qemu-devel] [PATCH 1/6] [RFC] Emulation of GRLIB GPTimer as defined in GRLIB IP Core User's Manual.
On 12/08/2010 09:30 AM, Edgar E. Iglesias wrote:
On Tue, Dec 07, 2010 at 10:55:33AM +0100, Fabien Chouteau wrote:
On 12/06/2010 06:12 PM, Blue Swirl wrote:
On Mon, Dec 6, 2010 at 9:26 AM, Fabien Chouteauchout...@adacore.com wrote:
Signed-off-by: Fabien Chouteauchout...@adacore.com
---
hw/grlib_gptimer.c | 448
1 files changed, 448 insertions(+), 0 deletions(-)
diff --git a/hw/grlib_gptimer.c b/hw/grlib_gptimer.c
new file mode 100644
index 000..41edbe4
--- /dev/null
+++ b/hw/grlib_gptimer.c
@@ -0,0 +1,448 @@
+/*
+ * QEMU GRLIB GPTimer Emulator
+ *
+ * Copyright (c) 2010 AdaCore
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include sysbus.h
+#include qemu-timer.h
+
+#include grlib.h
+
+/* #define DEBUG_TIMER */
The usual convention is
//#define DEBUG_TIMER
for easy editing.
Actually, it's easier for me with the /* */, but OK.
However, very often the much more powerful tracepoints can replace
debug statements.
+
+#ifdef DEBUG_TIMER
+#define DPRINTF(fmt, ...) \
+do { printf(GPTIMER: fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+#define UNIT_REG_SIZE16 /* Size of memory mapped regs for the unit */
+#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
+
+#define GPTIMER_MAX_TIMERS 8
+
+/* GPTimer Config register fields */
+#define GPTIMER_ENABLE (1 0)
+#define GPTIMER_RESTART (1 1)
+#define GPTIMER_LOAD(1 2)
+#define GPTIMER_INT_ENABLE (1 3)
+#define GPTIMER_INT_PENDING (1 4)
+#define GPTIMER_CHAIN (1 5) /* Not supported */
+#define GPTIMER_DEBUG_HALT (1 6) /* Not supported */
+
+/* Memory mapped register offsets */
+#define SCALER_OFFSET 0x00
+#define SCALER_RELOAD_OFFSET 0x04
+#define CONFIG_OFFSET 0x08
+#define COUNTER_OFFSET0x00
+#define COUNTER_RELOAD_OFFSET 0x04
+#define TIMER_BASE0x10
+
+typedef struct GPTimer GPTimer;
+typedef struct GPTimerUnit GPTimerUnit;
+
+struct GPTimer
+{
+QEMUBH *bh;
+struct ptimer_state *ptimer;
+
+qemu_irq irq;
+int id;
+GPTimerUnit *unit;
+
+/* registers */
+uint32_t counter;
+uint32_t reload;
+uint32_t config;
+};
+
+struct GPTimerUnit
+{
+SysBusDevice busdev;
+
+uint32_t nr_timers; /* Number of timers available */
+uint32_t freq_hz; /* System frequency */
+uint32_t irq_line; /* Base irq line */
+
+GPTimer *timers;
+
+/* registers */
+uint32_t scaler;
+uint32_t reload;
+uint32_t config;
+};
+
+DeviceState *grlib_gptimer_create(target_phys_addr_t base,
+ uint32_tnr_timers,
+ uint32_tfreq,
+ qemu_irq *cpu_irqs,
+ int base_irq)
This function belongs to leon3.c.
I don't see why. GPTimer is a peripheral and you may want to use it in
an other system.
This might depend a bit on taste, but I agree with Blue that we shouldn't
clutter the device models with this kind of instantiator helper calls.
IMO it's better to put them higher up (e.g board code or similar).
Do you mean like Xilinx devices where the instantiators are in-lined
functions in hw/xilinx.h?
--
Fabien Chouteau
Re: [Qemu-devel] [RFC][PATCH v5 00/21] virtagent: host/guest RPC communication agent
On Fri, Dec 3, 2010 at 6:03 PM, Michael Roth mdr...@linux.vnet.ibm.com wrote: These patches apply to master, and can also be obtained from: git://repo.or.cz/qemu/mdroth.git virtagent_v5 Why XML-RPC and not QMP? When I skim through the patch series it seems like much of the work being done is very similar to QMP. What concrete use-cases are there? * Reboot support on x86. A QMP command can invoke guest-initiated reboot via virtagent. * ? Will virtagent be extensible by host administrators or end-users? For example, can I drop in a custom command to collect statistics and invoke it across VMs on my hosts? Do I need to recompile QEMU and/or the virtagent daemon? Stefan
[Qemu-devel] Re: [PATCH] ceph/rbd block driver for qemu-kvm (v9)
Am 06.12.2010 20:53, schrieb Christian Brunner: This is a new version of the rbd driver. The only difference from v8 is a check for a recent librados version in configure. If the librados version is too old, rbd support will be disabled. RBD is an block driver for the distributed file system Ceph (http://ceph.newdream.net/). This driver uses librados (which is part of the Ceph server) for direct access to the Ceph object store and is running entirely in userspace (Yehuda also wrote a driver for the linux kernel, that can be used to access rbd volumes as a block device). Regards, Christian Signed-off-by: Yehuda Sadeh yeh...@hq.newdream.net Signed-off-by: Christian Brunner c...@muc.de Thanks. I still haven't managed to actually test it, but I've applied this to the block branch now based on your testing and Stefan's review (and the fact that it doesn't break my build any more). Kevin
Re: [Qemu-devel] [PATCH] ppc: kvm: fix signedness warning
ping?
On 25.11.2010, at 08:20, Alexander Graf wrote:
I get a warning on a signed comparison with an unsigned variable, so
let's make the variable signed and be happy.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/kvm.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 5cacef7..5caa07c 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -132,7 +132,7 @@ int kvm_arch_get_registers(CPUState *env)
{
struct kvm_regs regs;
struct kvm_sregs sregs;
-uint32_t i, ret;
+int i, ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, regs);
if (ret 0)
--
1.6.0.2
[Qemu-devel] [PATCH 04/15] dbdma: Make little endian
The device is only used on big endian systems, but always byte swaps. That's a very good indicator that it's actually a little endian device ;-). Signed-off-by: Alexander Graf ag...@suse.de --- hw/mac_dbdma.c |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c index f449a59..5680fa9 100644 --- a/hw/mac_dbdma.c +++ b/hw/mac_dbdma.c @@ -707,8 +707,6 @@ static void dbdma_writel (void *opaque, DBDMA_DPRINTF(channel 0x%x reg 0x%x\n, (uint32_t)addr DBDMA_CHANNEL_SHIFT, reg); -value = bswap32(value); - /* cmdptr cannot be modified if channel is RUN or ACTIVE */ if (reg == DBDMA_CMDPTR_LO @@ -788,7 +786,6 @@ static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) break; } -value = bswap32(value); return value; } @@ -845,7 +842,7 @@ void* DBDMA_init (int *dbdma_mem_index) s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS); *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); register_savevm(NULL, dbdma, -1, 1, dbdma_save, dbdma_load, s); qemu_register_reset(dbdma_reset, s); -- 1.6.0.2
[Qemu-devel] [PATCH 11/15] openpic: Replace explicit byte swap with endian hints
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/openpic.c | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 9e2500a..6d2cf99 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -242,19 +242,10 @@ typedef struct openpic_t {
int max_irq;
int irq_ipi0;
int irq_tim0;
-int need_swap;
void (*reset) (void *);
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
-static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
-{
-if (opp-need_swap)
-return bswap32(val);
-
-return val;
-}
-
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q-queue, n_IRQ);
@@ -599,7 +590,6 @@ static void openpic_gbl_write (void *opaque,
target_phys_addr_t addr, uint32_t v
DPRINTF(%s: addr TARGET_FMT_plx = %08x\n, __func__, addr, val);
if (addr 0xF)
return;
-val = openpic_swap32(opp, val);
addr = 0xFF;
switch (addr) {
case 0x00: /* FREP */
@@ -693,7 +683,6 @@ static uint32_t openpic_gbl_read (void *opaque,
target_phys_addr_t addr)
break;
}
DPRINTF(%s: = %08x\n, __func__, retval);
-retval = openpic_swap32(opp, retval);
return retval;
}
@@ -706,7 +695,6 @@ static void openpic_timer_write (void *opaque, uint32_t
addr, uint32_t val)
DPRINTF(%s: addr %08x = %08x\n, __func__, addr, val);
if (addr 0xF)
return;
-val = openpic_swap32(opp, val);
addr -= 0x1100;
addr = 0x;
idx = (addr 0xFFF0) 6;
@@ -759,7 +747,6 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t
addr)
break;
}
DPRINTF(%s: = %08x\n, __func__, retval);
-retval = openpic_swap32(opp, retval);
return retval;
}
@@ -772,7 +759,6 @@ static void openpic_src_write (void *opaque, uint32_t addr,
uint32_t val)
DPRINTF(%s: addr %08x = %08x\n, __func__, addr, val);
if (addr 0xF)
return;
-val = openpic_swap32(opp, val);
addr = addr 0xFFF0;
idx = addr 5;
if (addr 0x10) {
@@ -804,7 +790,6 @@ static uint32_t openpic_src_read (void *opaque, uint32_t
addr)
retval = read_IRQreg(opp, idx, IRQ_IPVP);
}
DPRINTF(%s: = %08x\n, __func__, retval);
-retval = openpic_swap32(opp, retval);
return retval;
}
@@ -819,7 +804,6 @@ static void openpic_cpu_write (void *opaque,
target_phys_addr_t addr, uint32_t v
DPRINTF(%s: addr TARGET_FMT_plx = %08x\n, __func__, addr, val);
if (addr 0xF)
return;
-val = openpic_swap32(opp, val);
addr = 0x1FFF0;
idx = addr / 0x1000;
dst = opp-dst[idx];
@@ -937,7 +921,6 @@ static uint32_t openpic_cpu_read (void *opaque,
target_phys_addr_t addr)
break;
}
DPRINTF(%s: = %08x\n, __func__, retval);
-retval = openpic_swap32(opp, retval);
return retval;
}
@@ -1204,7 +1187,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int
nb_cpus,
opp = qemu_mallocz(sizeof(openpic_t));
}
opp-mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
-DEVICE_NATIVE_ENDIAN);
+DEVICE_LITTLE_ENDIAN);
//isu_base = 0xFFFC;
opp-nb_cpus = nb_cpus;
@@ -1232,7 +1215,6 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int
nb_cpus,
for (i = 0; i nb_cpus; i++)
opp-dst[i].irqs = irqs[i];
opp-irq_out = irq_out;
-opp-need_swap = 1;
register_savevm(opp-pci_dev.qdev, openpic, 0, 2,
openpic_save, openpic_load, opp);
@@ -1673,7 +1655,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
int mem_index;
mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_BIG_ENDIAN);
if (mem_index 0) {
goto free;
}
@@ -1689,7 +1671,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
for (i = 0; i nb_cpus; i++)
mpp-dst[i].irqs = irqs[i];
mpp-irq_out = irq_out;
-mpp-need_swap = 0;/* MPIC has the same endian as target */
mpp-irq_raise = mpic_irq_raise;
mpp-reset = mpic_reset;
--
1.6.0.2
[Qemu-devel] [PATCH 03/15] Make simple io mem handler endian aware
As an alternative to the 3 individual handlers, there is also a simplified
io mem hook function. To be consistent, let's add an endianness parameter
there too.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/apb_pci.c |3 ++-
hw/pci_host.c | 12
hw/unin_pci.c |6 --
rwhandler.c |4 ++--
rwhandler.h |2 +-
5 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index bf00c71..84e9af7 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -418,7 +418,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
/* PCI configuration space */
s-pci_config_handler.read = apb_pci_config_read;
s-pci_config_handler.write = apb_pci_config_write;
-pci_config = cpu_register_io_memory_simple(s-pci_config_handler);
+pci_config = cpu_register_io_memory_simple(s-pci_config_handler,
+ DEVICE_NATIVE_ENDIAN);
assert(pci_config = 0);
/* at region 1 */
sysbus_init_mmio(dev, 0x100ULL, pci_config);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index bc5b771..a6e39c9 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -187,9 +187,11 @@ int pci_host_conf_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
-return cpu_register_io_memory_simple(s-conf_handler);
+return cpu_register_io_memory_simple(s-conf_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
-return cpu_register_io_memory_simple(s-conf_noswap_handler);
+return cpu_register_io_memory_simple(s-conf_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
@@ -203,9 +205,11 @@ int pci_host_data_register_mmio(PCIHostState *s, int swap)
{
pci_host_init(s);
if (swap) {
-return cpu_register_io_memory_simple(s-data_handler);
+return cpu_register_io_memory_simple(s-data_handler,
+ DEVICE_NATIVE_ENDIAN);
} else {
-return cpu_register_io_memory_simple(s-data_noswap_handler);
+return cpu_register_io_memory_simple(s-data_noswap_handler,
+ DEVICE_NATIVE_ENDIAN);
}
}
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 1310211..53791dd 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -154,7 +154,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(s-host_state, 1);
s-data_handler.read = unin_data_read;
s-data_handler.write = unin_data_write;
-pci_mem_data = cpu_register_io_memory_simple(s-data_handler);
+pci_mem_data = cpu_register_io_memory_simple(s-data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
@@ -175,7 +176,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
pci_mem_config = pci_host_conf_register_mmio(s-host_state, 1);
s-data_handler.read = unin_data_read;
s-data_handler.write = unin_data_write;
-pci_mem_data = cpu_register_io_memory_simple(s-data_handler);
+pci_mem_data = cpu_register_io_memory_simple(s-data_handler,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/rwhandler.c b/rwhandler.c
index 88dfcc5..bb2238f 100644
--- a/rwhandler.c
+++ b/rwhandler.c
@@ -35,14 +35,14 @@ static CPUReadMemoryFunc * const
cpu_io_memory_simple_read[] = {
cpu_io_memory_simple_readl,
};
-int cpu_register_io_memory_simple(struct ReadWriteHandler *handler)
+int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler-read || !handler-write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
- handler, DEVICE_NATIVE_ENDIAN);
+ handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
diff --git a/rwhandler.h b/rwhandler.h
index bc11849..b2a5790 100644
--- a/rwhandler.h
+++ b/rwhandler.h
@@ -19,7 +19,7 @@ struct ReadWriteHandler {
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
-int cpu_register_io_memory_simple(ReadWriteHandler *);
+int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);
--
1.6.0.2
[Qemu-devel] [PATCH 06/15] uninorth: Get rid of bswap
There's no need to bswap once we correctly set the mmio to be little endian.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/unin_pci.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f2e440e..5f15058 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -121,7 +121,6 @@ static void unin_data_write(ReadWriteHandler *handler,
pcibus_t addr, uint32_t val, int len)
{
UNINState *s = container_of(handler, UNINState, data_handler);
-val = qemu_bswap_len(val, len);
UNIN_DPRINTF(write addr % FMT_PCIBUS len %d val %x\n, addr, len, val);
pci_data_write(s-host_state.bus,
unin_get_config_reg(s-host_state.config_reg, addr),
@@ -138,7 +137,6 @@ static uint32_t unin_data_read(ReadWriteHandler *handler,
unin_get_config_reg(s-host_state.config_reg, addr),
len);
UNIN_DPRINTF(read addr % FMT_PCIBUS len %d val %x\n, addr, len, val);
-val = qemu_bswap_len(val, len);
return val;
}
@@ -156,7 +154,7 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
s-data_handler.read = unin_data_read;
s-data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(s-data_handler,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
@@ -179,7 +177,7 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
s-data_handler.read = unin_data_read;
s-data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(s-data_handler,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
--
1.6.0.2
[Qemu-devel] [PATCH 01/15] exec: introduce endianness swapped mmio
The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of). Some
are big endian (special system devices) and a very little fraction is
target native endian (fw_cfg).
So instead of assuming every device to be native endianness, let's move
to a model where the device tells us which endianness it's in.
That way we can compile the devices only once and get rid of all the ugly
swap will be done by the underlying layer.
For the same of readability, this patch only introduces the helper framework
but doesn't allow the registering code to set its endianness yet.
Signed-off-by: Alexander Graf ag...@suse.de
---
v0 - v1:
- don't restrict to big endian targets
- move constants to enum
---
cpu-common.h |8 +++-
exec.c | 123 +-
2 files changed, 128 insertions(+), 3 deletions(-)
diff --git a/cpu-common.h b/cpu-common.h
index bb6b137..6d4a898 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -20,6 +20,12 @@
#if !defined(CONFIG_USER_ONLY)
+enum device_endian {
+DEVICE_NATIVE_ENDIAN,
+DEVICE_BIG_ENDIAN,
+DEVICE_LITTLE_ENDIAN,
+};
+
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
@@ -55,7 +61,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
- void *opaque);
+ void *opaque, enum device_endian endian);
void cpu_unregister_io_memory(int table_address);
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
diff --git a/exec.c b/exec.c
index 42a35e0..af1e89d 100644
--- a/exec.c
+++ b/exec.c
@@ -3355,6 +3355,106 @@ static int get_free_io_mem_idx(void)
return -1;
}
+/*
+ * Usually, devices operate in little endian mode. There are devices out
+ * there that operate in big endian too. Each device gets byte swapped
+ * mmio if plugged onto a CPU that does the other endianness.
+ *
+ * CPU Device swap?
+ *
+ * little little no
+ * little big yes
+ * big little yes
+ * big big no
+ */
+
+typedef struct SwapEndianContainer {
+CPUReadMemoryFunc *read[3];
+CPUWriteMemoryFunc *write[3];
+void *opaque;
+} SwapEndianContainer;
+
+static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr)
+{
+uint32_t val;
+SwapEndianContainer *c = opaque;
+val = c-read[0](c-opaque, addr);
+return val;
+}
+
+static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr)
+{
+uint32_t val;
+SwapEndianContainer *c = opaque;
+val = bswap16(c-read[1](c-opaque, addr));
+return val;
+}
+
+static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr)
+{
+uint32_t val;
+SwapEndianContainer *c = opaque;
+val = bswap32(c-read[2](c-opaque, addr));
+return val;
+}
+
+static CPUReadMemoryFunc * const swapendian_readfn[3]={
+swapendian_mem_readb,
+swapendian_mem_readw,
+swapendian_mem_readl
+};
+
+static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+SwapEndianContainer *c = opaque;
+c-write[0](c-opaque, addr, val);
+}
+
+static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+SwapEndianContainer *c = opaque;
+c-write[1](c-opaque, addr, bswap16(val));
+}
+
+static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+SwapEndianContainer *c = opaque;
+c-write[2](c-opaque, addr, bswap32(val));
+}
+
+static CPUWriteMemoryFunc * const swapendian_writefn[3]={
+swapendian_mem_writeb,
+swapendian_mem_writew,
+swapendian_mem_writel
+};
+
+static void swapendian_init(int io_index)
+{
+SwapEndianContainer *c = qemu_malloc(sizeof(SwapEndianContainer));
+int i;
+
+/* Swap mmio for big endian targets */
+c-opaque = io_mem_opaque[io_index];
+for (i = 0; i 3; i++) {
+c-read[i] = io_mem_read[io_index][i];
+c-write[i] = io_mem_write[io_index][i];
+
+io_mem_read[io_index][i] = swapendian_readfn[i];
+io_mem_write[io_index][i] = swapendian_writefn[i];
+}
+io_mem_opaque[io_index] = c;
+}
+
+static void swapendian_del(int io_index)
+{
+if (io_mem_read[io_index][0] == swapendian_readfn[0]) {
+qemu_free(io_mem_opaque[io_index]);
+}
+}
+
/* mem_read and mem_write are arrays of functions containing the
function to access byte (index 0), word (index 1) and dword (index
2). Functions can be omitted with a NULL function pointer.
@@ -3365,9 +3465,10 @@ static int
[Qemu-devel] [PATCH 00/15] MMIO endianness cleanup v2
The way mmio endianness is currently implemented is horrifying. In the real world, CPUs have an endianness and write out data to the memory bus. Instead of RAM, a receiving side here can be a device. This device gets a byte stream again and needs to make sense of it. Since big endian systems write big endian numbers into memory while little endian systems write little endian numbers there, the device and software on the CPU need to be aware of this. In practice, most devices these days (ISA, PCI) assume that the data is little endian. So to communicate with such a device from the CPU's side, the OS byte swaps all MMIO. In qemu however, we simply pass the register value we find on to the device. So any byte mangling the guest does to compensate for the transfer screw us up by exposing byte swapped MMIO on the device's side. The way this has been fixed historically is by constructs like this one: #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif With the move to get device code only compiled once, this has become harder and harder to justify though, since we don't know the target endianness during compile time. It's especially bad since it doesn't make any sense at all to clutter all the device code with endianness workarounds, aside from the fact that about 80% of the device code currently does the wrong thing :). So my solution to the issue is to make every device define if it's a little, big or native (target) endianness device. This basically tells the layers below what endianness the device expects mmio to occur in. Little endian devices on little endian hosts don't swap. On big endian hosts they do. Same the other way around. The only reason I added native endianness is that we have some PV devices like the fw_cfg that expect qemu's broken behavior. These devices are the minority though. In the long run I'd expect to see most code be committed with either of the two endianness choices. The patch set also includes a bunch of conversions for devices that were already aware of endianness. For easy testing or pulling, please use this repo: git://repo.or.cz/qemu/agraf.git qemu-endian-fix-v2 v0-v1: - make LE targets compile - add one missing conversion - make endian choice be an enum v1 - v2: - rebase (this thing bitrots _fast_!) Alexander Graf (15): exec: introduce endianness swapped mmio Add endianness as io mem parameter Make simple io mem handler endian aware dbdma: Make little endian pci-host: Delegate bswap to mmio layer uninorth: Get rid of bswap e1000: Make little endian prep: Declare as little endian versatile_pci: Declare as little endian ppc4xx_pci: Declare as little endian openpic: Replace explicit byte swap with endian hints rtl8139: Declare as little endian heathrow_pic: Declare as little endian isa_mmio: Always use little endian usb_ohci: Always use little endian Makefile.objs |3 + Makefile.target|7 -- cpu-common.h |8 ++- exec.c | 142 +--- hw/apb_pci.c |9 ++- hw/apic.c |3 +- hw/arm_gic.c |3 +- hw/arm_sysctl.c|3 +- hw/arm_timer.c |5 +- hw/armv7m.c|2 +- hw/axis_dev88.c|6 +- hw/bonito.c| 19 -- hw/cirrus_vga.c| 12 +++- hw/cs4231.c|3 +- hw/cuda.c |3 +- hw/dec_pci.c |6 +- hw/dp8393x.c |3 +- hw/ds1225y.c |6 +- hw/e1000.c | 11 +--- hw/eccmemctl.c |6 +- hw/eepro100.c |3 +- hw/empty_slot.c|3 +- hw/escc.c |3 +- hw/esp.c |3 +- hw/etraxfs_dma.c |2 +- hw/etraxfs_eth.c |3 +- hw/etraxfs_pic.c |3 +- hw/etraxfs_ser.c |3 +- hw/etraxfs_timer.c |3 +- hw/fdc.c |6 +- hw/fw_cfg.c|6 +- hw/g364fb.c|3 +- hw/grackle_pci.c |6 +- hw/gt64xxx.c |9 +-- hw/heathrow_pic.c |5 +- hw/hpet.c |3 +- hw/ide/macio.c |3 +- hw/ide/mmio.c |6 +- hw/integratorcp.c |9 ++- hw/intel-hda.c |3 +- hw/ioapic.c|3 +- hw/isa.h |2 +- hw/isa_mmio.c | 100 ++- hw/ivshmem.c |2 +- hw/jazz_led.c |3 +- hw/lan9118.c |3 +- hw/lance.c |3 +- hw/lsi53c895a.c|6 +- hw/m48t59.c|3 +- hw/mac_dbdma.c |6 +- hw/mac_nvram.c |3 +- hw/marvell_88w8618_audio.c |3 +- hw/mcf5206.c |3 +-
[Qemu-devel] [PATCH 09/15] versatile_pci: Declare as little endian
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/versatile_pci.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 3baad96..cc8f9f8 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -32,18 +32,12 @@ static void pci_vpb_config_writeb (void *opaque,
target_phys_addr_t addr,
static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap16(val);
-#endif
pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
}
static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
}
@@ -58,9 +52,6 @@ static uint32_t pci_vpb_config_readw (void *opaque,
target_phys_addr_t addr)
{
uint32_t val;
val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap16(val);
-#endif
return val;
}
@@ -68,9 +59,6 @@ static uint32_t pci_vpb_config_readl (void *opaque,
target_phys_addr_t addr)
{
uint32_t val;
val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
return val;
}
@@ -133,7 +121,7 @@ static int pci_vpb_init(SysBusDevice *dev)
s-mem_config = cpu_register_io_memory(pci_vpb_config_read,
pci_vpb_config_write, bus,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x0400, pci_vpb_map);
pci_create_simple(bus, -1, versatile_pci_host);
--
1.6.0.2
[Qemu-devel] [PATCH 08/15] prep: Declare as little endian
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc_prep.c | 38 +++---
1 files changed, 3 insertions(+), 35 deletions(-)
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 80f5db6..1492266 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -145,20 +145,12 @@ static uint32_t PPC_intack_readb (void *opaque,
target_phys_addr_t addr)
static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-return bswap16(_PPC_intack_read(addr));
-#else
return _PPC_intack_read(addr);
-#endif
}
static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-return bswap32(_PPC_intack_read(addr));
-#else
return _PPC_intack_read(addr);
-#endif
}
static CPUWriteMemoryFunc * const PPC_intack_write[] = {
@@ -210,9 +202,6 @@ static void PPC_XCSR_writeb (void *opaque,
static void PPC_XCSR_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap16(value);
-#endif
printf(%s: 0x TARGET_FMT_plx = 0x%08 PRIx32 \n, __func__, addr,
value);
}
@@ -220,9 +209,6 @@ static void PPC_XCSR_writew (void *opaque,
static void PPC_XCSR_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap32(value);
-#endif
printf(%s: 0x TARGET_FMT_plx = 0x%08 PRIx32 \n, __func__, addr,
value);
}
@@ -243,9 +229,6 @@ static uint32_t PPC_XCSR_readw (void *opaque,
target_phys_addr_t addr)
printf(%s: 0x TARGET_FMT_plx = %08 PRIx32 \n, __func__, addr,
retval);
-#ifdef TARGET_WORDS_BIGENDIAN
-retval = bswap16(retval);
-#endif
return retval;
}
@@ -256,9 +239,6 @@ static uint32_t PPC_XCSR_readl (void *opaque,
target_phys_addr_t addr)
printf(%s: 0x TARGET_FMT_plx = %08 PRIx32 \n, __func__, addr,
retval);
-#ifdef TARGET_WORDS_BIGENDIAN
-retval = bswap32(retval);
-#endif
return retval;
}
@@ -484,9 +464,6 @@ static void PPC_prep_io_writew (void *opaque,
target_phys_addr_t addr,
sysctrl_t *sysctrl = opaque;
addr = prep_IO_address(sysctrl, addr);
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap16(value);
-#endif
PPC_IO_DPRINTF(0x TARGET_FMT_plx = 0x%08 PRIx32 \n, addr, value);
cpu_outw(addr, value);
}
@@ -498,9 +475,6 @@ static uint32_t PPC_prep_io_readw (void *opaque,
target_phys_addr_t addr)
addr = prep_IO_address(sysctrl, addr);
ret = cpu_inw(addr);
-#ifdef TARGET_WORDS_BIGENDIAN
-ret = bswap16(ret);
-#endif
PPC_IO_DPRINTF(0x TARGET_FMT_plx = 0x%08 PRIx32 \n, addr, ret);
return ret;
@@ -512,9 +486,6 @@ static void PPC_prep_io_writel (void *opaque,
target_phys_addr_t addr,
sysctrl_t *sysctrl = opaque;
addr = prep_IO_address(sysctrl, addr);
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap32(value);
-#endif
PPC_IO_DPRINTF(0x TARGET_FMT_plx = 0x%08 PRIx32 \n, addr, value);
cpu_outl(addr, value);
}
@@ -526,9 +497,6 @@ static uint32_t PPC_prep_io_readl (void *opaque,
target_phys_addr_t addr)
addr = prep_IO_address(sysctrl, addr);
ret = cpu_inl(addr);
-#ifdef TARGET_WORDS_BIGENDIAN
-ret = bswap32(ret);
-#endif
PPC_IO_DPRINTF(0x TARGET_FMT_plx = 0x%08 PRIx32 \n, addr, ret);
return ret;
@@ -691,7 +659,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
PPC_prep_io_write, sysctrl,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
cpu_register_physical_memory(0x8000, 0x0080, PPC_io_memory);
/* init basic PC hardware */
@@ -757,12 +725,12 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* PCI intack location */
PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
PPC_intack_write, NULL,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
cpu_register_physical_memory(0xBFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
- NULL, DEVICE_NATIVE_ENDIAN);
+ NULL, DEVICE_LITTLE_ENDIAN);
cpu_register_physical_memory(0xFEFF, 0x1000, PPC_io_memory);
#endif
--
1.6.0.2
[Qemu-devel] [PATCH 14/15] isa_mmio: Always use little endian
This patch converts the ISA MMIO bridge code to always use little endian mmio.
All bswap code that existed was only there to convert from native cpu
endianness to little endian ISA devices.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/bonito.c|4 +-
hw/gt64xxx.c |6 +--
hw/isa.h |2 +-
hw/isa_mmio.c | 102 +--
hw/mips_jazz.c |7 +---
hw/mips_mipssim.c |6 +--
hw/mips_r4k.c |6 +--
hw/ppc440.c|2 +-
hw/ppc_newworld.c |2 +-
hw/ppc_oldworld.c |2 +-
hw/ppce500_mpc8544ds.c |2 +-
hw/sh_pci.c|4 +-
hw/sun4u.c |4 +-
hw/versatile_pci.c |6 +--
14 files changed, 36 insertions(+), 119 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index fd90527..65a4a63 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -743,12 +743,12 @@ static int bonito_initfn(PCIDevice *dev)
s-bonito_pciio_start = BONITO_PCIIO_BASE;
s-bonito_pciio_length = BONITO_PCIIO_SIZE;
isa_mem_base = s-bonito_pciio_start;
-isa_mmio_init(s-bonito_pciio_start, s-bonito_pciio_length, 0);
+isa_mmio_init(s-bonito_pciio_start, s-bonito_pciio_length);
/* add pci local io mapping */
s-bonito_localio_start = BONITO_DEV_BASE;
s-bonito_localio_length = BONITO_DEV_SIZE;
-isa_mmio_init(s-bonito_localio_start, s-bonito_localio_length, 0);
+isa_mmio_init(s-bonito_localio_start, s-bonito_localio_length);
/* set the default value of north bridge pci config */
pci_set_word(dev-config + PCI_COMMAND, 0x);
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 51e4db0..14c6ad3 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -297,11 +297,7 @@ static void gt64120_pci_mapping(GT64120State *s)
s-PCI0IO_start = s-regs[GT_PCI0IOLD] 21;
s-PCI0IO_length = ((s-regs[GT_PCI0IOHD] + 1) - (s-regs[GT_PCI0IOLD]
0x7f)) 21;
isa_mem_base = s-PCI0IO_start;
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(s-PCI0IO_start, s-PCI0IO_length, 1);
-#else
- isa_mmio_init(s-PCI0IO_start, s-PCI0IO_length, 0);
-#endif
+ isa_mmio_init(s-PCI0IO_start, s-PCI0IO_length);
}
}
diff --git a/hw/isa.h b/hw/isa.h
index aaf0272..e6848e4 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -32,7 +32,7 @@ ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 46458f4..ca957fb 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -31,27 +31,13 @@ static void isa_mmio_writeb (void *opaque,
target_phys_addr_t addr,
cpu_outb(addr IOPORTS_MASK, val);
}
-static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
-val = bswap16(val);
cpu_outw(addr IOPORTS_MASK, val);
}
-static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-cpu_outw(addr IOPORTS_MASK, val);
-}
-
-static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-val = bswap32(val);
-cpu_outl(addr IOPORTS_MASK, val);
-}
-
-static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr IOPORTS_MASK, val);
@@ -59,86 +45,38 @@ static void isa_mmio_writel_le(void *opaque,
target_phys_addr_t addr,
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
{
-uint32_t val;
-
-val = cpu_inb(addr IOPORTS_MASK);
-return val;
+return cpu_inb(addr IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
{
-uint32_t val;
-
-val = cpu_inw(addr IOPORTS_MASK);
-val = bswap16(val);
-return val;
+return cpu_inw(addr IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
{
-uint32_t val;
-
-val = cpu_inw(addr IOPORTS_MASK);
-return val;
+return cpu_inl(addr IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)
-{
-uint32_t val;
-
-val = cpu_inl(addr IOPORTS_MASK);
-val = bswap32(val);
-return val;
-}
-
-static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)
-{
-uint32_t val;
-
-val = cpu_inl(addr IOPORTS_MASK);
-return val;
-}
-
-static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
-
[Qemu-devel] [PATCH 07/15] e1000: Make little endian
The e1000 has compatibility code to handle big endianness which makes it
mandatory to be recompiled on different targets.
With the generic mmio endianness solution, there's no need for that anymore.
We just declare all mmio to be little endian and call it a day.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |1 -
hw/e1000.c | 11 ++-
3 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 04625eb..29b1ede 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -224,6 +224,7 @@ hw-obj-$(CONFIG_NE2000_PCI) += ne2000.o
hw-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o
hw-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
hw-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
+hw-obj-$(CONFIG_E1000_PCI) += e1000.o
hw-obj-$(CONFIG_SMC91C111) += smc91c111.o
hw-obj-$(CONFIG_LAN9118) += lan9118.o
diff --git a/Makefile.target b/Makefile.target
index 5784844..39d8df9 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -211,7 +211,6 @@ obj-$(CONFIG_USB_OHCI) += usb-ohci.o
# PCI network cards
obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
-obj-$(CONFIG_E1000_PCI) += e1000.o
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
diff --git a/hw/e1000.c b/hw/e1000.c
index bf3f2d3..a697abd 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -857,9 +857,6 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
E1000State *s = opaque;
unsigned int index = (addr 0x1) 2;
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
if (index NWRITEOPS macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index NREADOPS macreg_readops[index]) {
@@ -894,11 +891,7 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
if (index NREADOPS macreg_readops[index])
{
-uint32_t val = macreg_readops[index](s, index);
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
-return val;
+return macreg_readops[index](s, index);
}
DBGOUT(UNKNOWN, MMIO unknown read addr=0x%08x\n, index2);
return 0;
@@ -1131,7 +1124,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d-mmio_index = cpu_register_io_memory(e1000_mmio_read,
-e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
+e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
pci_register_bar(d-dev, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
--
1.6.0.2
[Qemu-devel] [PATCH 05/15] pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that
most pci host devices are little endian. The ppc e500 is the only
odd one here, being big endian.
So let's directly pass the endianness down to the mmio layer and not
worry about it on the pci host layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index aa07ab7..bf88f2a 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -96,8 +96,10 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(DECState, dev);
-pci_mem_config = pci_host_conf_register_mmio(s-host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(s-host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(s-host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(s-host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 91c755f..bd3d6b0 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(GrackleState, dev);
-pci_mem_config = pci_host_conf_register_mmio(s-host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(s-host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(s-host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(s-host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index a6e39c9..eebff7a 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,64 +78,39 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF(%s addr % FMT_PCIBUS %d val %PRIx32\n,
__func__, addr, len, val);
-val = qemu_bswap_len(val, len);
s-config_reg = val;
}
-static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s-config_reg;
-val = qemu_bswap_len(val, len);
PCI_DPRINTF(%s addr % FMT_PCIBUS len %d val %PRIx32\n,
__func__, addr, len, val);
return val;
}
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
-PCI_DPRINTF(%s addr % FMT_PCIBUS %d val %PRIx32\n,
-__func__, addr, len, val);
-s-config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-uint32_t val = s-config_reg;
-
-PCI_DPRINTF(%s addr % FMT_PCIBUS len %d val %PRIx32\n,
-__func__, addr, len, val);
-return val;
-}
-
-static void pci_host_data_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(ReadWriteHandler *handler,
+pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-
-val = qemu_bswap_len(val, len);
PCI_DPRINTF(write addr % FMT_PCIBUS len %d val %x\n,
addr, len, val);
if (s-config_reg (1u 31))
pci_data_write(s-bus, s-config_reg | (addr 3), val, len);
}
-static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
+static uint32_t pci_host_data_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
[Qemu-devel] [PATCH 3/3] target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com --- target-arm/helper.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 7cd6a4e..1522022 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -76,6 +76,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) memcpy(env-cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env-cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); env-cp15.c0_cachetype = 0x1dd20d2; +env-cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: set_feature(env, ARM_FEATURE_V6); @@ -131,6 +132,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env-cp15.c0_clid = (1 27) | (1 24) | 3; env-cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env-cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ +env-cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: set_feature(env, ARM_FEATURE_V6); -- 1.7.3.1
[Qemu-devel] [PATCH 15/15] usb_ohci: Always use little endian
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw/usb-ohci.c |9 +
3 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 2b93598..cebb945 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -188,6 +188,7 @@ hw-obj-$(CONFIG_I8254) += i8254.o
hw-obj-$(CONFIG_PCSPK) += pcspk.o
hw-obj-$(CONFIG_PCKBD) += pckbd.o
hw-obj-$(CONFIG_USB_UHCI) += usb-uhci.o
+hw-obj-$(CONFIG_USB_OHCI) += usb-ohci.o
hw-obj-$(CONFIG_FDC) += fdc.o
hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o
hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o
diff --git a/Makefile.target b/Makefile.target
index 8bef8e3..d08f5dd 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -206,9 +206,6 @@ QEMU_CFLAGS += $(VNC_PNG_CFLAGS)
# xen backend driver support
obj-$(CONFIG_XEN) += xen_machine_pv.o xen_domainbuild.o
-# USB layer
-obj-$(CONFIG_USB_OHCI) += usb-ohci.o
-
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index ba1ebbc..8eb4a1e 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1530,9 +1530,6 @@ static uint32_t ohci_mem_read(void *ptr,
target_phys_addr_t addr)
}
}
-#ifdef TARGET_WORDS_BIGENDIAN
-retval = bswap32(retval);
-#endif
return retval;
}
@@ -1542,10 +1539,6 @@ static void ohci_mem_write(void *ptr, target_phys_addr_t
addr, uint32_t val)
addr = 0xff;
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
-
/* Only aligned reads are allowed on OHCI */
if (addr 3) {
fprintf(stderr, usb-ohci: Mis-aligned write\n);
@@ -1698,7 +1691,7 @@ static void usb_ohci_init(OHCIState *ohci, DeviceState
*dev,
}
ohci-mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
ohci-localmem_base = localmem_base;
ohci-name = dev-info-name;
--
1.6.0.2
[Qemu-devel] [PATCH 12/15] rtl8139: Declare as little endian
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf ag...@suse.de
---
Makefile.objs |1 +
Makefile.target |3 ---
hw/rtl8139.c| 14 +-
3 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 29b1ede..2b93598 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -225,6 +225,7 @@ hw-obj-$(CONFIG_EEPRO100_PCI) += eepro100.o
hw-obj-$(CONFIG_PCNET_PCI) += pcnet-pci.o
hw-obj-$(CONFIG_PCNET_COMMON) += pcnet.o
hw-obj-$(CONFIG_E1000_PCI) += e1000.o
+hw-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
hw-obj-$(CONFIG_SMC91C111) += smc91c111.o
hw-obj-$(CONFIG_LAN9118) += lan9118.o
diff --git a/Makefile.target b/Makefile.target
index 39d8df9..8bef8e3 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -209,9 +209,6 @@ obj-$(CONFIG_XEN) += xen_machine_pv.o xen_domainbuild.o
# USB layer
obj-$(CONFIG_USB_OHCI) += usb-ohci.o
-# PCI network cards
-obj-$(CONFIG_RTL8139_PCI) += rtl8139.o
-
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 30a3960..4a73f6f 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3125,17 +3125,11 @@ static void rtl8139_mmio_writeb(void *opaque,
target_phys_addr_t addr, uint32_t
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap16(val);
-#endif
rtl8139_io_writew(opaque, addr 0xFF, val);
}
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
rtl8139_io_writel(opaque, addr 0xFF, val);
}
@@ -3147,18 +3141,12 @@ static uint32_t rtl8139_mmio_readb(void *opaque,
target_phys_addr_t addr)
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap16(val);
-#endif
return val;
}
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
-val = bswap32(val);
-#endif
return val;
}
@@ -3367,7 +3355,7 @@ static int pci_rtl8139_init(PCIDevice *dev)
/* I/O handler for memory-mapped I/O */
s-rtl8139_mmio_io_addr =
cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
pci_register_bar(s-dev, 0, 0x100,
PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
--
1.6.0.2
[Qemu-devel] [PATCH 13/15] heathrow_pic: Declare as little endian
This patch replaces explicit bswaps with endianness hints to the mmio layer. Signed-off-by: Alexander Graf ag...@suse.de --- hw/heathrow_pic.c |4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c index 390b63c..b19b754 100644 --- a/hw/heathrow_pic.c +++ b/hw/heathrow_pic.c @@ -68,7 +68,6 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) HeathrowPIC *pic; unsigned int n; -value = bswap32(value); n = ((addr 0xfff) - 0x10) 4; PIC_DPRINTF(writel: TARGET_FMT_plx %u: %08x\n, addr, n, value); if (n = 2) @@ -118,7 +117,6 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) } } PIC_DPRINTF(readl: TARGET_FMT_plx %u: %08x\n, addr, n, value); -value = bswap32(value); return value; } @@ -223,7 +221,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index, /* only 1 CPU */ s-irqs = irqs[0]; *pmem_index = cpu_register_io_memory(pic_read, pic_write, s, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); register_savevm(NULL, heathrow_pic, -1, 1, heathrow_pic_save, heathrow_pic_load, s); -- 1.6.0.2
[Qemu-devel] [PATCH 10/15] ppc4xx_pci: Declare as little endian
This patch replaces explicit bswaps with endianness hints to the
mmio layer.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc4xx_pci.c | 17 ++---
1 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index f2ecece..f62f1f9 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -24,7 +24,6 @@
#include ppc4xx.h
#include pci.h
#include pci_host.h
-#include bswap.h
#undef DEBUG
#ifdef DEBUG
@@ -102,10 +101,6 @@ static void pci4xx_cfgaddr_writel(void *opaque,
target_phys_addr_t addr,
{
PPC4xxPCIState *ppc4xx_pci = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap32(value);
-#endif
-
ppc4xx_pci-pci_state.config_reg = value ~0x3;
}
@@ -120,10 +115,6 @@ static void ppc4xx_pci_reg_write4(void *opaque,
target_phys_addr_t offset,
{
struct PPC4xxPCIState *pci = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap32(value);
-#endif
-
/* We ignore all target attempts at PCI configuration, effectively
* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
@@ -251,10 +242,6 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque,
target_phys_addr_t offset)
value = 0;
}
-#ifdef TARGET_WORDS_BIGENDIAN
-value = bswap32(value);
-#endif
-
return value;
}
@@ -373,7 +360,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
/* CFGADDR */
index = cpu_register_io_memory(pci4xx_cfgaddr_read,
pci4xx_cfgaddr_write, controller,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
if (index 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
@@ -386,7 +373,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
/* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
- DEVICE_NATIVE_ENDIAN);
+ DEVICE_LITTLE_ENDIAN);
if (index 0)
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
--
1.6.0.2
[Qemu-devel] Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves
Avi, Marcello, can you please commit this simple fix? (turning 40 to 80?) Without it QEMU crashes reliably on our new CPUs (they return 46 leaves) and causes pain in our testing, because we have to manually apply this patch on each tree. Thanks! Andre. Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/include/asm/kvm_host.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) Hi, I found that either KVM or QEMU (possibly both) are broken in respect to handling more CPUID entries than the limit dictates. KVM will return -E2BIG, which is the same error as if the user hasn't provided enough space to hold all entries. Now QEMU will continue to enlarge the allocated memory until it gets into an out-of-memory condition. I have tried to fix this with teaching KVM how to deal with a capped number of entries (there are some bugs in the current code), but this will limit the number of CPUID entries KVM handles, which will surely cut of the lastly appended PV leaves. A proper fix would be to make this allocation dynamic. Is this a feasible way or will this lead to issues or side-effects? Regards, Andre. diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 54e42c8..3cc80c4 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -79,7 +79,7 @@ #define KVM_NUM_MMU_PAGES (1 KVM_MMU_HASH_SHIFT) #define KVM_MIN_FREE_MMU_PAGES 5 #define KVM_REFILL_PAGES 25 -#define KVM_MAX_CPUID_ENTRIES 40 +#define KVM_MAX_CPUID_ENTRIES 80 #define KVM_NR_FIXED_MTRR_REGION 88 #define KVM_NR_VAR_MTRR 8
[Qemu-devel] [PATCH 0/3] target-arm: fix mmu access protection emulation
The ARM VMSAv6 emulation does not correctly ignore access protection checks for manager domain translation table descriptors. This causes ARM Linux kernel to hang during initialization for ARMv7 CPUs. However that has so far been hidden by another emulation bug where the cp15 c1 system control register has an invalid reset value for the emulated ARMv6 and ARMv7 processors indicating an earlier processor revision instead and thus making QEMU run the MMU emulation in ARMv5 mode. This patch series fixes the access protection emulation in the ARM MMU emulation (1) and introduces correct cp15 c1 system control register values for the ARM1136, Cortex-A8 and Cortex-A9 cores (2,3). Juha Riihimäki (2): target-arm: fix vmsav6 access control target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9 Mattias Holm (1): target-arm: correct cp15 c1_sys reset value for cortex-a8 target-arm/helper.c | 37 ++--- 1 files changed, 22 insertions(+), 15 deletions(-) -- 1.7.3.1
[Qemu-devel] [PATCH 1/3] target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translation
table descriptors assigned to manager domains.
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com
---
target-arm/helper.c | 34 +++---
1 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 996d40d..5bcfcf7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1078,22 +1078,26 @@ static int get_phys_addr_v6(CPUState *env, uint32_t
address, int access_type,
}
code = 15;
}
-if (xn access_type == 2)
-goto do_fault;
+if (domain == 3) {
+*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+} else {
+if (xn access_type == 2)
+goto do_fault;
-/* The simplified model uses AP[0] as an access control bit. */
-if ((env-cp15.c1_sys (1 29)) (ap 1) == 0) {
-/* Access flag fault. */
-code = (code == 15) ? 6 : 3;
-goto do_fault;
-}
-*prot = check_ap(env, ap, domain, access_type, is_user);
-if (!*prot) {
-/* Access permission fault. */
-goto do_fault;
-}
-if (!xn) {
-*prot |= PAGE_EXEC;
+/* The simplified model uses AP[0] as an access control bit. */
+if ((env-cp15.c1_sys (1 29)) (ap 1) == 0) {
+/* Access flag fault. */
+code = (code == 15) ? 6 : 3;
+goto do_fault;
+}
+*prot = check_ap(env, ap, domain, access_type, is_user);
+if (!*prot) {
+/* Access permission fault. */
+goto do_fault;
+}
+if (!xn) {
+*prot |= PAGE_EXEC;
+}
}
*phys_ptr = phys_addr;
return 0;
--
1.7.3.1
[Qemu-devel] [PATCH 2/3] target-arm: correct cp15 c1_sys reset value for cortex-a8
From: Mattias Holm h...@liacs.nl Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com --- target-arm/helper.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5bcfcf7..7cd6a4e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -109,6 +109,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env-cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env-cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ env-cp15.c0_ccsid[2] = 0xf000; /* No L2 icache. */ +env-cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: set_feature(env, ARM_FEATURE_V6); -- 1.7.3.1
[Qemu-devel] [PATCHv8 02/16] Introduce new BusInfo callback get_fw_dev_path.
New get_fw_dev_path callback will be used for build device path usable
by firmware in contrast to qdev qemu internal device path.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/qdev.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/qdev.h b/hw/qdev.h
index bc71110..f72fbde 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -49,6 +49,12 @@ struct DeviceState {
typedef void (*bus_dev_printfn)(Monitor *mon, DeviceState *dev, int indent);
typedef char *(*bus_get_dev_path)(DeviceState *dev);
+/*
+ * This callback is used to create Open Firmware device path in accordance with
+ * OF spec http://forthworks.com/standards/of1275.pdf. Indicidual bus bindings
+ * can be found here http://playground.sun.com/1275/bindings/.
+ */
+typedef char *(*bus_get_fw_dev_path)(DeviceState *dev);
typedef int (qbus_resetfn)(BusState *bus);
struct BusInfo {
@@ -56,6 +62,7 @@ struct BusInfo {
size_t size;
bus_dev_printfn print_dev;
bus_get_dev_path get_dev_path;
+bus_get_fw_dev_path get_fw_dev_path;
qbus_resetfn *reset;
Property *props;
};
--
1.7.2.3
[Qemu-devel] [PATCHv8 07/16] Add get_fw_dev_path callback for system bus.
Prints out mmio or pio used to access child device.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/pci_host.c |2 ++
hw/sysbus.c | 30 ++
hw/sysbus.h |4
3 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/hw/pci_host.c b/hw/pci_host.c
index bc5b771..28d45bf 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -197,6 +197,7 @@ void pci_host_conf_register_ioport(pio_addr_t ioport,
PCIHostState *s)
{
pci_host_init(s);
register_ioport_simple(s-conf_noswap_handler, ioport, 4, 4);
+sysbus_init_ioports(s-busdev, ioport, 4);
}
int pci_host_data_register_mmio(PCIHostState *s, int swap)
@@ -215,4 +216,5 @@ void pci_host_data_register_ioport(pio_addr_t ioport,
PCIHostState *s)
register_ioport_simple(s-data_noswap_handler, ioport, 4, 1);
register_ioport_simple(s-data_noswap_handler, ioport, 4, 2);
register_ioport_simple(s-data_noswap_handler, ioport, 4, 4);
+sysbus_init_ioports(s-busdev, ioport, 4);
}
diff --git a/hw/sysbus.c b/hw/sysbus.c
index d817721..1583bd8 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -22,11 +22,13 @@
#include monitor.h
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent);
+static char *sysbus_get_fw_dev_path(DeviceState *dev);
struct BusInfo system_bus_info = {
.name = System,
.size = sizeof(BusState),
.print_dev = sysbus_dev_print,
+.get_fw_dev_path = sysbus_get_fw_dev_path,
};
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq)
@@ -106,6 +108,16 @@ void sysbus_init_mmio_cb(SysBusDevice *dev,
target_phys_addr_t size,
dev-mmio[n].cb = cb;
}
+void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size)
+{
+pio_addr_t i;
+
+for (i = 0; i size; i++) {
+assert(dev-num_pio QDEV_MAX_PIO);
+dev-pio[dev-num_pio++] = ioport++;
+}
+}
+
static int sysbus_device_init(DeviceState *dev, DeviceInfo *base)
{
SysBusDeviceInfo *info = container_of(base, SysBusDeviceInfo, qdev);
@@ -171,3 +183,21 @@ static void sysbus_dev_print(Monitor *mon, DeviceState
*dev, int indent)
indent, , s-mmio[i].addr, s-mmio[i].size);
}
}
+
+static char *sysbus_get_fw_dev_path(DeviceState *dev)
+{
+SysBusDevice *s = sysbus_from_qdev(dev);
+char path[40];
+int off;
+
+off = snprintf(path, sizeof(path), %s, qdev_fw_name(dev));
+
+if (s-num_mmio) {
+snprintf(path + off, sizeof(path) - off, @TARGET_FMT_plx,
+ s-mmio[0].addr);
+} else if (s-num_pio) {
+snprintf(path + off, sizeof(path) - off, @i%04x, s-pio[0]);
+}
+
+return strdup(path);
+}
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 5980901..e9eb618 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -6,6 +6,7 @@
#include qdev.h
#define QDEV_MAX_MMIO 32
+#define QDEV_MAX_PIO 32
#define QDEV_MAX_IRQ 256
typedef struct SysBusDevice SysBusDevice;
@@ -23,6 +24,8 @@ struct SysBusDevice {
mmio_mapfunc cb;
ram_addr_t iofunc;
} mmio[QDEV_MAX_MMIO];
+int num_pio;
+pio_addr_t pio[QDEV_MAX_PIO];
};
typedef int (*sysbus_initfn)(SysBusDevice *dev);
@@ -45,6 +48,7 @@ void sysbus_init_mmio_cb(SysBusDevice *dev,
target_phys_addr_t size,
mmio_mapfunc cb);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
+void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t
size);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
--
1.7.2.3
[Qemu-devel] [PATCHv8 16/16] Pass boot device list to firmware.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/fw_cfg.c | 14 ++
sysemu.h|1 +
vl.c| 48
3 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index 7b9434f..20a816f 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -53,6 +53,7 @@ struct FWCfgState {
FWCfgFiles *files;
uint16_t cur_entry;
uint32_t cur_offset;
+Notifier machine_ready;
};
static void fw_cfg_write(FWCfgState *s, uint8_t value)
@@ -315,6 +316,15 @@ int fw_cfg_add_file(FWCfgState *s, const char *filename,
uint8_t *data,
return 1;
}
+static void fw_cfg_machine_ready(struct Notifier* n)
+{
+uint32_t len;
+FWCfgState *s = container_of(n, FWCfgState, machine_ready);
+char *bootindex = get_boot_devices_list(len);
+
+fw_cfg_add_file(s, bootorder, (uint8_t*)bootindex, len);
+}
+
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t ctl_addr, target_phys_addr_t
data_addr)
{
@@ -343,6 +353,10 @@ FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t
data_port,
fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
+
+s-machine_ready.notify = fw_cfg_machine_ready;
+qemu_add_machine_init_done_notifier(s-machine_ready);
+
return s;
}
diff --git a/sysemu.h b/sysemu.h
index c42f33a..38a20a3 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -196,4 +196,5 @@ void register_devices(void);
void add_boot_device_path(int32_t bootindex, DeviceState *dev,
const char *suffix);
+char *get_boot_devices_list(uint32_t *size);
#endif
diff --git a/vl.c b/vl.c
index 0d20d26..c4d3fc0 100644
--- a/vl.c
+++ b/vl.c
@@ -736,6 +736,54 @@ void add_boot_device_path(int32_t bootindex, DeviceState
*dev,
QTAILQ_INSERT_TAIL(fw_boot_order, node, link);
}
+/*
+ * This function returns null terminated string that consist of new line
+ * separated device pathes.
+ *
+ * memory pointed by size is assigned total length of the array in bytes
+ *
+ */
+char *get_boot_devices_list(uint32_t *size)
+{
+FWBootEntry *i;
+uint32_t total = 0;
+char *list = NULL;
+
+QTAILQ_FOREACH(i, fw_boot_order, link) {
+char *devpath = NULL, *bootpath;
+int len;
+
+if (i-dev) {
+devpath = qdev_get_fw_dev_path(i-dev);
+assert(devpath);
+}
+
+if (i-suffix devpath) {
+bootpath = qemu_malloc(strlen(devpath) + strlen(i-suffix) + 1);
+sprintf(bootpath, %s%s, devpath, i-suffix);
+qemu_free(devpath);
+} else if (devpath) {
+bootpath = devpath;
+} else {
+bootpath = strdup(i-suffix);
+assert(bootpath);
+}
+
+if (total) {
+list[total-1] = '\n';
+}
+len = strlen(bootpath) + 1;
+list = qemu_realloc(list, total + len);
+memcpy(list[total], bootpath, len);
+total += len;
+qemu_free(bootpath);
+}
+
+*size = total;
+
+return list;
+}
+
static void numa_add(const char *optarg)
{
char option[128];
--
1.7.2.3
[Qemu-devel] [PATCHv8 04/16] Add get_fw_dev_path callback to ISA bus in qdev.
Use device ioports to create unique device path.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/isa-bus.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index c0ac7e9..c423c1b 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -31,11 +31,13 @@ static ISABus *isabus;
target_phys_addr_t isa_mem_base = 0;
static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
+static char *isabus_get_fw_dev_path(DeviceState *dev);
static struct BusInfo isa_bus_info = {
.name = ISA,
.size = sizeof(ISABus),
.print_dev = isabus_dev_print,
+.get_fw_dev_path = isabus_get_fw_dev_path,
};
ISABus *isa_bus_new(DeviceState *dev)
@@ -188,4 +190,18 @@ static void isabus_register_devices(void)
sysbus_register_withprop(isabus_bridge_info);
}
+static char *isabus_get_fw_dev_path(DeviceState *dev)
+{
+ISADevice *d = (ISADevice*)dev;
+char path[40];
+int off;
+
+off = snprintf(path, sizeof(path), %s, qdev_fw_name(dev));
+if (d-nioports) {
+snprintf(path + off, sizeof(path) - off, @%04x, d-ioports[0]);
+}
+
+return strdup(path);
+}
+
device_init(isabus_register_devices)
--
1.7.2.3
[Qemu-devel] [PATCHv8 01/16] Introduce fw_name field to DeviceInfo structure.
Add fw_name to DeviceInfo to use in device path building. In
contrast to name fw_name should refer to functionality device
provides instead of particular device model like name does.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/fdc.c|1 +
hw/ide/isa.c|1 +
hw/ide/qdev.c |1 +
hw/isa-bus.c|1 +
hw/lance.c |1 +
hw/piix_pci.c |1 +
hw/qdev.h |6 ++
hw/scsi-disk.c |1 +
hw/usb-hub.c|1 +
hw/usb-net.c|1 +
hw/virtio-pci.c |1 +
11 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/hw/fdc.c b/hw/fdc.c
index c159dcb..a467c4b 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -2040,6 +2040,7 @@ static const VMStateDescription vmstate_isa_fdc ={
static ISADeviceInfo isa_fdc_info = {
.init = isabus_fdc_init1,
.qdev.name = isa-fdc,
+.qdev.fw_name = fdc,
.qdev.size = sizeof(FDCtrlISABus),
.qdev.no_user = 1,
.qdev.vmsd = vmstate_isa_fdc,
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
index 6b57e0d..9856435 100644
--- a/hw/ide/isa.c
+++ b/hw/ide/isa.c
@@ -98,6 +98,7 @@ ISADevice *isa_ide_init(int iobase, int iobase2, int isairq,
static ISADeviceInfo isa_ide_info = {
.qdev.name = isa-ide,
+.qdev.fw_name = ide,
.qdev.size = sizeof(ISAIDEState),
.init = isa_ide_initfn,
.qdev.reset = isa_ide_reset,
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 0808760..6d27b60 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -134,6 +134,7 @@ static int ide_drive_initfn(IDEDevice *dev)
static IDEDeviceInfo ide_drive_info = {
.qdev.name = ide-drive,
+.qdev.fw_name = drive,
.qdev.size = sizeof(IDEDrive),
.init = ide_drive_initfn,
.qdev.props = (Property[]) {
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 4e306de..26036e0 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -153,6 +153,7 @@ static int isabus_bridge_init(SysBusDevice *dev)
static SysBusDeviceInfo isabus_bridge_info = {
.init = isabus_bridge_init,
.qdev.name = isabus-bridge,
+.qdev.fw_name = isa,
.qdev.size = sizeof(SysBusDevice),
.qdev.no_user = 1,
};
diff --git a/hw/lance.c b/hw/lance.c
index dc12144..1a3bb1a 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -141,6 +141,7 @@ static void lance_reset(DeviceState *dev)
static SysBusDeviceInfo lance_info = {
.init = lance_init,
.qdev.name = lance,
+.qdev.fw_name = ethernet,
.qdev.size = sizeof(SysBusPCNetState),
.qdev.reset = lance_reset,
.qdev.vmsd = vmstate_lance,
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index b5589b9..38f9d9e 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -365,6 +365,7 @@ static PCIDeviceInfo i440fx_info[] = {
static SysBusDeviceInfo i440fx_pcihost_info = {
.init = i440fx_pcihost_initfn,
.qdev.name= i440FX-pcihost,
+.qdev.fw_name = pci,
.qdev.size= sizeof(I440FXState),
.qdev.no_user = 1,
};
diff --git a/hw/qdev.h b/hw/qdev.h
index 3fac364..bc71110 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -141,6 +141,7 @@ typedef void (*qdev_resetfn)(DeviceState *dev);
struct DeviceInfo {
const char *name;
+const char *fw_name;
const char *alias;
const char *desc;
size_t size;
@@ -306,6 +307,11 @@ void qdev_prop_set_defaults(DeviceState *dev, Property
*props);
void qdev_prop_register_global_list(GlobalProperty *props);
void qdev_prop_set_globals(DeviceState *dev);
+static inline const char *qdev_fw_name(DeviceState *dev)
+{
+return dev-info-fw_name ? : dev-info-alias ? : dev-info-name;
+}
+
/* This is a nasty hack to allow passing a NULL bus to qdev_create. */
extern struct BusInfo system_bus_info;
diff --git a/hw/scsi-disk.c b/hw/scsi-disk.c
index 6e49404..851046f 100644
--- a/hw/scsi-disk.c
+++ b/hw/scsi-disk.c
@@ -1230,6 +1230,7 @@ static int scsi_disk_initfn(SCSIDevice *dev)
static SCSIDeviceInfo scsi_disk_info = {
.qdev.name= scsi-disk,
+.qdev.fw_name = disk,
.qdev.desc= virtual scsi disk or cdrom,
.qdev.size= sizeof(SCSIDiskState),
.qdev.reset = scsi_disk_reset,
diff --git a/hw/usb-hub.c b/hw/usb-hub.c
index 2a1edfc..8e3a96b 100644
--- a/hw/usb-hub.c
+++ b/hw/usb-hub.c
@@ -545,6 +545,7 @@ static int usb_hub_initfn(USBDevice *dev)
static struct USBDeviceInfo hub_info = {
.product_desc = QEMU USB Hub,
.qdev.name = usb-hub,
+.qdev.fw_name= hub,
.qdev.size = sizeof(USBHubState),
.init = usb_hub_initfn,
.handle_packet = usb_hub_handle_packet,
diff --git a/hw/usb-net.c b/hw/usb-net.c
index 58c672f..f6bed21 100644
--- a/hw/usb-net.c
+++ b/hw/usb-net.c
@@ -1496,6 +1496,7 @@ static USBDevice *usb_net_init(const char *cmdline)
static struct USBDeviceInfo net_info = {
.product_desc = QEMU USB Network Interface,
.qdev.name = usb-net,
+.qdev.fw_name= network,
.qdev.size = sizeof(USBNetState),
.init = usb_net_initfn,
.handle_packet =
[Qemu-devel] [PATCHv8 15/16] Add notifier that will be called when machine is fully created.
Action that depends on fully initialized device model should register
with this notifier chain.
Signed-off-by: Gleb Natapov g...@redhat.com
---
sysemu.h |2 ++
vl.c | 15 +++
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/sysemu.h b/sysemu.h
index 48f8eee..c42f33a 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -60,6 +60,8 @@ void qemu_system_reset(void);
void qemu_add_exit_notifier(Notifier *notify);
void qemu_remove_exit_notifier(Notifier *notify);
+void qemu_add_machine_init_done_notifier(Notifier *notify);
+
void do_savevm(Monitor *mon, const QDict *qdict);
int load_vmstate(const char *name);
void do_delvm(Monitor *mon, const QDict *qdict);
diff --git a/vl.c b/vl.c
index 844d6a5..0d20d26 100644
--- a/vl.c
+++ b/vl.c
@@ -254,6 +254,9 @@ static void *boot_set_opaque;
static NotifierList exit_notifiers =
NOTIFIER_LIST_INITIALIZER(exit_notifiers);
+static NotifierList machine_init_done_notifiers =
+NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
+
int kvm_allowed = 0;
uint32_t xen_domid;
enum xen_mode xen_mode = XEN_EMULATE;
@@ -1782,6 +1785,16 @@ static void qemu_run_exit_notifiers(void)
notifier_list_notify(exit_notifiers);
}
+void qemu_add_machine_init_done_notifier(Notifier *notify)
+{
+notifier_list_add(machine_init_done_notifiers, notify);
+}
+
+static void qemu_run_machine_init_done_notifiers(void)
+{
+notifier_list_notify(machine_init_done_notifiers);
+}
+
static const QEMUOption *lookup_opt(int argc, char **argv,
const char **poptarg, int *poptind)
{
@@ -3028,6 +3041,8 @@ int main(int argc, char **argv, char **envp)
}
qemu_register_reset((void *)qbus_reset_all, sysbus_get_default());
+qemu_run_machine_init_done_notifiers();
+
qemu_system_reset();
if (loadvm) {
if (load_vmstate(loadvm) 0) {
--
1.7.2.3
[Qemu-devel] [PATCHv8 03/16] Keep track of ISA ports ISA device is using in qdev.
Store all io ports used by device in ISADevice structure.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/cs4231a.c |1 +
hw/fdc.c |3 +++
hw/gus.c |4
hw/ide/isa.c |2 ++
hw/isa-bus.c | 25 +
hw/isa.h |4
hw/m48t59.c |1 +
hw/mc146818rtc.c |1 +
hw/ne2000-isa.c |3 +++
hw/parallel.c|5 +
hw/pckbd.c |3 +++
hw/sb16.c|4
hw/serial.c |1 +
13 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index 4d5ce5c..598f032 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -645,6 +645,7 @@ static int cs4231a_initfn (ISADevice *dev)
isa_init_irq (dev, s-pic, s-irq);
for (i = 0; i 4; i++) {
+isa_init_ioport(dev, i);
register_ioport_write (s-port + i, 1, 1, cs_write, s);
register_ioport_read (s-port + i, 1, 1, cs_read, s);
}
diff --git a/hw/fdc.c b/hw/fdc.c
index a467c4b..22fb64a 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -1983,6 +1983,9 @@ static int isabus_fdc_init1(ISADevice *dev)
fdctrl_write_port, fdctrl);
register_ioport_write(iobase + 0x07, 1, 1,
fdctrl_write_port, fdctrl);
+isa_init_ioport_range(dev, iobase, 6);
+isa_init_ioport(dev, iobase + 7);
+
isa_init_irq(isa-busdev, fdctrl-irq, isairq);
fdctrl-dma_chann = dma_chann;
diff --git a/hw/gus.c b/hw/gus.c
index e9016d8..ff9e7c7 100644
--- a/hw/gus.c
+++ b/hw/gus.c
@@ -264,20 +264,24 @@ static int gus_initfn (ISADevice *dev)
register_ioport_write (s-port, 1, 1, gus_writeb, s);
register_ioport_write (s-port, 1, 2, gus_writew, s);
+isa_init_ioport_range(dev, s-port, 2);
register_ioport_read ((s-port + 0x100) 0xf00, 1, 1, gus_readb, s);
register_ioport_read ((s-port + 0x100) 0xf00, 1, 2, gus_readw, s);
+isa_init_ioport_range(dev, (s-port + 0x100) 0xf00, 2);
register_ioport_write (s-port + 6, 10, 1, gus_writeb, s);
register_ioport_write (s-port + 6, 10, 2, gus_writew, s);
register_ioport_read (s-port + 6, 10, 1, gus_readb, s);
register_ioport_read (s-port + 6, 10, 2, gus_readw, s);
+isa_init_ioport_range(dev, s-port + 6, 10);
register_ioport_write (s-port + 0x100, 8, 1, gus_writeb, s);
register_ioport_write (s-port + 0x100, 8, 2, gus_writew, s);
register_ioport_read (s-port + 0x100, 8, 1, gus_readb, s);
register_ioport_read (s-port + 0x100, 8, 2, gus_readw, s);
+isa_init_ioport_range(dev, s-port + 0x100, 8);
DMA_register_channel (s-emu.gusdma, GUS_read_DMA, s);
s-emu.himemaddr = s-himem;
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
index 9856435..4206afd 100644
--- a/hw/ide/isa.c
+++ b/hw/ide/isa.c
@@ -70,6 +70,8 @@ static int isa_ide_initfn(ISADevice *dev)
ide_bus_new(s-bus, s-dev.qdev);
ide_init_ioport(s-bus, s-iobase, s-iobase2);
isa_init_irq(dev, s-irq, s-isairq);
+isa_init_ioport_range(dev, s-iobase, 8);
+isa_init_ioport(dev, s-iobase2);
ide_init2(s-bus, s-irq);
vmstate_register(dev-qdev, 0, vmstate_ide_isa, s);
return 0;
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 26036e0..c0ac7e9 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -92,6 +92,31 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq)
dev-nirqs++;
}
+static void isa_init_ioport_one(ISADevice *dev, uint16_t ioport)
+{
+assert(dev-nioports ARRAY_SIZE(dev-ioports));
+dev-ioports[dev-nioports++] = ioport;
+}
+
+static int isa_cmp_ports(const void *p1, const void *p2)
+{
+return *(uint16_t*)p1 - *(uint16_t*)p2;
+}
+
+void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length)
+{
+int i;
+for (i = start; i start + length; i++) {
+isa_init_ioport_one(dev, i);
+}
+qsort(dev-ioports, dev-nioports, sizeof(dev-ioports[0]), isa_cmp_ports);
+}
+
+void isa_init_ioport(ISADevice *dev, uint16_t ioport)
+{
+isa_init_ioport_range(dev, ioport, 1);
+}
+
static int isa_qdev_init(DeviceState *qdev, DeviceInfo *base)
{
ISADevice *dev = DO_UPCAST(ISADevice, qdev, qdev);
diff --git a/hw/isa.h b/hw/isa.h
index aaf0272..4794b76 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -14,6 +14,8 @@ struct ISADevice {
DeviceState qdev;
uint32_t isairq[2];
int nirqs;
+uint16_t ioports[32];
+int nioports;
};
typedef int (*isa_qdev_initfn)(ISADevice *dev);
@@ -26,6 +28,8 @@ ISABus *isa_bus_new(DeviceState *dev);
void isa_bus_irqs(qemu_irq *irqs);
qemu_irq isa_reserve_irq(int isairq);
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
+void isa_init_ioport(ISADevice *dev, uint16_t ioport);
+void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
ISADevice *isa_create(const char *name);
ISADevice *isa_create_simple(const char *name);
diff --git a/hw/m48t59.c b/hw/m48t59.c
index c7492a6..75a94e1 100644
---
[Qemu-devel] [PATCHv8 14/16] Add bootindex for option roms.
Extend -option-rom command to have additional parameter ,bootindex=.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/loader.c| 16 +++-
hw/loader.h|8
hw/multiboot.c |3 ++-
hw/ne2000.c|2 +-
hw/nseries.c |4 ++--
hw/palm.c |6 +++---
hw/pc.c|7 ---
hw/pci.c |2 +-
hw/pcnet-pci.c |2 +-
qemu-config.c | 17 +
sysemu.h |6 +-
vl.c | 11 +--
12 files changed, 60 insertions(+), 24 deletions(-)
diff --git a/hw/loader.c b/hw/loader.c
index 1e98326..eb198f6 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -107,7 +107,7 @@ int load_image_targphys(const char *filename,
size = get_image_size(filename);
if (size 0)
-rom_add_file_fixed(filename, addr);
+rom_add_file_fixed(filename, addr, -1);
return size;
}
@@ -557,10 +557,11 @@ static void rom_insert(Rom *rom)
}
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr)
+ target_phys_addr_t addr, int32_t bootindex)
{
Rom *rom;
int rc, fd = -1;
+char devpath[100];
rom = qemu_mallocz(sizeof(*rom));
rom-name = qemu_strdup(file);
@@ -605,7 +606,12 @@ int rom_add_file(const char *file, const char *fw_dir,
snprintf(fw_file_name, sizeof(fw_file_name), %s/%s, rom-fw_dir,
basename);
fw_cfg_add_file(fw_cfg, fw_file_name, rom-data, rom-romsize);
+snprintf(devpath, sizeof(devpath), /r...@%s, fw_file_name);
+} else {
+snprintf(devpath, sizeof(devpath), /rom@ TARGET_FMT_plx, addr);
}
+
+add_boot_device_path(bootindex, NULL, devpath);
return 0;
err:
@@ -635,12 +641,12 @@ int rom_add_blob(const char *name, const void *blob,
size_t len,
int rom_add_vga(const char *file)
{
-return rom_add_file(file, vgaroms, 0);
+return rom_add_file(file, vgaroms, 0, -1);
}
-int rom_add_option(const char *file)
+int rom_add_option(const char *file, int32_t bootindex)
{
-return rom_add_file(file, genroms, 0);
+return rom_add_file(file, genroms, 0, bootindex);
}
static void rom_reset(void *unused)
diff --git a/hw/loader.h b/hw/loader.h
index 1f82fc5..fc6bdff 100644
--- a/hw/loader.h
+++ b/hw/loader.h
@@ -22,7 +22,7 @@ void pstrcpy_targphys(const char *name,
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr);
+ target_phys_addr_t addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
target_phys_addr_t addr);
int rom_load_all(void);
@@ -31,8 +31,8 @@ int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t
size);
void *rom_ptr(target_phys_addr_t addr);
void do_info_roms(Monitor *mon);
-#define rom_add_file_fixed(_f, _a) \
-rom_add_file(_f, NULL, _a)
+#define rom_add_file_fixed(_f, _a, _i) \
+rom_add_file(_f, NULL, _a, _i)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
rom_add_blob(_f, _b, _l, _a)
@@ -43,6 +43,6 @@ void do_info_roms(Monitor *mon);
#define PC_ROM_SIZE(PC_ROM_MAX - PC_ROM_MIN_VGA)
int rom_add_vga(const char *file);
-int rom_add_option(const char *file);
+int rom_add_option(const char *file, int32_t bootindex);
#endif
diff --git a/hw/multiboot.c b/hw/multiboot.c
index e710bbb..7cc3055 100644
--- a/hw/multiboot.c
+++ b/hw/multiboot.c
@@ -331,7 +331,8 @@ int load_multiboot(void *fw_cfg,
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, mb_bootinfo_data,
sizeof(bootinfo));
-option_rom[nb_option_roms] = multiboot.bin;
+option_rom[nb_option_roms].name = multiboot.bin;
+option_rom[nb_option_roms].bootindex = 0;
nb_option_roms++;
return 1; /* yes, we are multiboot */
diff --git a/hw/ne2000.c b/hw/ne2000.c
index a030106..5966359 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -742,7 +742,7 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
if (!pci_dev-qdev.hotplugged) {
static int loaded = 0;
if (!loaded) {
-rom_add_option(pxe-ne2k_pci.bin);
+rom_add_option(pxe-ne2k_pci.bin, -1);
loaded = 1;
}
}
diff --git a/hw/nseries.c b/hw/nseries.c
index 04a028d..2f6f473 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -1326,7 +1326,7 @@ static void n8x0_init(ram_addr_t ram_size, const char
*boot_device,
qemu_register_reset(n8x0_boot_init, s);
}
-if (option_rom[0] (boot_device[0] == 'n' || !kernel_filename)) {
+if (option_rom[0].name (boot_device[0] == 'n' || !kernel_filename)) {
int rom_size;
uint8_t nolo_tags[0x1];
/* No, wait, better start at the ROM. */
@@ -1341,7 +1341,7 @@ static void n8x0_init(ram_addr_t ram_size, const char
*boot_device,
*
* The code above is for loading the `zImage' file from Nokia
* images. */
-rom_size =
[Qemu-devel] [PATCHv8 00/16] boot order specification
Forget to save a couple of buffers before sending version 7 :( Anthony, Blue can this be applied now? Gleb Natapov (16): Introduce fw_name field to DeviceInfo structure. Introduce new BusInfo callback get_fw_dev_path. Keep track of ISA ports ISA device is using in qdev. Add get_fw_dev_path callback to ISA bus in qdev. Store IDE bus id in IDEBus structure for easy access. Add get_fw_dev_path callback to IDE bus. Add get_fw_dev_path callback for system bus. Add get_fw_dev_path callback for pci bus. Record which USBDevice USBPort belongs too. Add get_fw_dev_path callback for usb bus. Add get_fw_dev_path callback to scsi bus. Add bootindex parameter to net/block/fd device Change fw_cfg_add_file() to get full file path as a parameter. Add bootindex for option roms. Add notifier that will be called when machine is fully created. Pass boot device list to firmware. block_int.h |4 +- hw/cs4231a.c |1 + hw/e1000.c|4 ++ hw/eepro100.c |3 + hw/fdc.c | 12 ++ hw/fw_cfg.c | 30 -- hw/fw_cfg.h |4 +- hw/gus.c |4 ++ hw/ide/cmd646.c |4 +- hw/ide/internal.h |3 +- hw/ide/isa.c |5 ++- hw/ide/piix.c |4 +- hw/ide/qdev.c | 22 ++- hw/ide/via.c |4 +- hw/isa-bus.c | 42 +++ hw/isa.h |4 ++ hw/lance.c|1 + hw/loader.c | 32 --- hw/loader.h |8 ++-- hw/m48t59.c |1 + hw/mc146818rtc.c |1 + hw/multiboot.c|3 +- hw/ne2000-isa.c |3 + hw/ne2000.c |5 ++- hw/nseries.c |4 +- hw/palm.c |6 +- hw/parallel.c |5 ++ hw/pc.c |7 ++- hw/pci.c | 110 --- hw/pci_host.c |2 + hw/pckbd.c|3 + hw/pcnet-pci.c|2 +- hw/pcnet.c|4 ++ hw/piix_pci.c |1 + hw/qdev.c | 32 +++ hw/qdev.h | 14 ++ hw/rtl8139.c |4 ++ hw/sb16.c |4 ++ hw/scsi-bus.c | 23 +++ hw/scsi-disk.c|2 + hw/serial.c |1 + hw/sysbus.c | 30 ++ hw/sysbus.h |4 ++ hw/usb-bus.c | 45 - hw/usb-hub.c |3 +- hw/usb-musb.c |2 +- hw/usb-net.c |3 + hw/usb-ohci.c |2 +- hw/usb-uhci.c |2 +- hw/usb.h |3 +- hw/virtio-blk.c |2 + hw/virtio-net.c |2 + hw/virtio-pci.c |1 + net.h |4 +- qemu-config.c | 17 sysemu.h | 11 +- vl.c | 114 - 57 files changed, 593 insertions(+), 80 deletions(-) -- 1.7.2.3
[Qemu-devel] [PATCHv8 09/16] Record which USBDevice USBPort belongs too.
Ports on root hub will have NULL here. This is needed to reconstruct
path from device to its root hub to build device path.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/usb-bus.c |3 ++-
hw/usb-hub.c |2 +-
hw/usb-musb.c |2 +-
hw/usb-ohci.c |2 +-
hw/usb-uhci.c |2 +-
hw/usb.h |3 ++-
6 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/usb-bus.c b/hw/usb-bus.c
index b692503..256b881 100644
--- a/hw/usb-bus.c
+++ b/hw/usb-bus.c
@@ -110,11 +110,12 @@ USBDevice *usb_create_simple(USBBus *bus, const char
*name)
}
void usb_register_port(USBBus *bus, USBPort *port, void *opaque, int index,
- usb_attachfn attach)
+ USBDevice *pdev, usb_attachfn attach)
{
port-opaque = opaque;
port-index = index;
port-attach = attach;
+port-pdev = pdev;
QTAILQ_INSERT_TAIL(bus-free, port, next);
bus-nfree++;
}
diff --git a/hw/usb-hub.c b/hw/usb-hub.c
index 8e3a96b..8a3f829 100644
--- a/hw/usb-hub.c
+++ b/hw/usb-hub.c
@@ -535,7 +535,7 @@ static int usb_hub_initfn(USBDevice *dev)
for (i = 0; i s-nb_ports; i++) {
port = s-ports[i];
usb_register_port(usb_bus_from_device(dev),
- port-port, s, i, usb_hub_attach);
+ port-port, s, i, s-dev, usb_hub_attach);
port-wPortStatus = PORT_STAT_POWER;
port-wPortChange = 0;
}
diff --git a/hw/usb-musb.c b/hw/usb-musb.c
index 7f15842..9efe7a6 100644
--- a/hw/usb-musb.c
+++ b/hw/usb-musb.c
@@ -343,7 +343,7 @@ struct MUSBState {
}
usb_bus_new(s-bus, NULL /* FIXME */);
-usb_register_port(s-bus, s-port, s, 0, musb_attach);
+usb_register_port(s-bus, s-port, s, 0, NULL, musb_attach);
return s;
}
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index 8fb2f83..1247295 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1705,7 +1705,7 @@ static void usb_ohci_init(OHCIState *ohci, DeviceState
*dev,
usb_bus_new(ohci-bus, dev);
ohci-num_ports = num_ports;
for (i = 0; i num_ports; i++) {
-usb_register_port(ohci-bus, ohci-rhport[i].port, ohci, i,
ohci_attach);
+usb_register_port(ohci-bus, ohci-rhport[i].port, ohci, i, NULL,
ohci_attach);
}
ohci-async_td = 0;
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index 1d83400..b9b822f 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1115,7 +1115,7 @@ static int usb_uhci_common_initfn(UHCIState *s)
usb_bus_new(s-bus, s-dev.qdev);
for(i = 0; i NB_PORTS; i++) {
-usb_register_port(s-bus, s-ports[i].port, s, i, uhci_attach);
+usb_register_port(s-bus, s-ports[i].port, s, i, NULL, uhci_attach);
}
s-frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s);
s-expire_time = qemu_get_clock(vm_clock) +
diff --git a/hw/usb.h b/hw/usb.h
index 00d2802..0b32d77 100644
--- a/hw/usb.h
+++ b/hw/usb.h
@@ -203,6 +203,7 @@ struct USBPort {
USBDevice *dev;
usb_attachfn attach;
void *opaque;
+USBDevice *pdev;
int index; /* internal port index, may be used with the opaque */
QTAILQ_ENTRY(USBPort) next;
};
@@ -312,7 +313,7 @@ USBDevice *usb_create(USBBus *bus, const char *name);
USBDevice *usb_create_simple(USBBus *bus, const char *name);
USBDevice *usbdevice_create(const char *cmdline);
void usb_register_port(USBBus *bus, USBPort *port, void *opaque, int index,
- usb_attachfn attach);
+ USBDevice *pdev, usb_attachfn attach);
void usb_unregister_port(USBBus *bus, USBPort *port);
int usb_device_attach(USBDevice *dev);
int usb_device_detach(USBDevice *dev);
--
1.7.2.3
[Qemu-devel] [PATCHv8 11/16] Add get_fw_dev_path callback to scsi bus.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/scsi-bus.c | 23 +++
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/hw/scsi-bus.c b/hw/scsi-bus.c
index 93f0e9a..7febb86 100644
--- a/hw/scsi-bus.c
+++ b/hw/scsi-bus.c
@@ -5,9 +5,12 @@
#include qdev.h
#include blockdev.h
+static char *scsibus_get_fw_dev_path(DeviceState *dev);
+
static struct BusInfo scsi_bus_info = {
.name = SCSI,
.size = sizeof(SCSIBus),
+.get_fw_dev_path = scsibus_get_fw_dev_path,
.props = (Property[]) {
DEFINE_PROP_UINT32(scsi-id, SCSIDevice, id, -1),
DEFINE_PROP_END_OF_LIST(),
@@ -518,3 +521,23 @@ void scsi_req_complete(SCSIRequest *req)
req-tag,
req-status);
}
+
+static char *scsibus_get_fw_dev_path(DeviceState *dev)
+{
+SCSIDevice *d = (SCSIDevice*)dev;
+SCSIBus *bus = scsi_bus_from_device(d);
+char path[100];
+int i;
+
+for (i = 0; i bus-ndev; i++) {
+if (bus-devs[i] == d) {
+break;
+}
+}
+
+assert(i != bus-ndev);
+
+snprintf(path, sizeof(path), %...@%x, qdev_fw_name(dev), i);
+
+return strdup(path);
+}
--
1.7.2.3
[Qemu-devel] [PATCHv8 08/16] Add get_fw_dev_path callback for pci bus.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/pci.c | 108 -
1 files changed, 85 insertions(+), 23 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 0c15b13..e7ea907 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -43,6 +43,7 @@
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *pcibus_get_dev_path(DeviceState *dev);
+static char *pcibus_get_fw_dev_path(DeviceState *dev);
static int pcibus_reset(BusState *qbus);
struct BusInfo pci_bus_info = {
@@ -50,6 +51,7 @@ struct BusInfo pci_bus_info = {
.size = sizeof(PCIBus),
.print_dev = pcibus_dev_print,
.get_dev_path = pcibus_get_dev_path,
+.get_fw_dev_path = pcibus_get_fw_dev_path,
.reset = pcibus_reset,
.props = (Property[]) {
DEFINE_PROP_PCI_DEVFN(addr, PCIDevice, devfn, -1),
@@ -1117,45 +1119,63 @@ void pci_msi_notify(PCIDevice *dev, unsigned int vector)
typedef struct {
uint16_t class;
const char *desc;
+const char *fw_name;
+uint16_t fw_ign_bits;
} pci_class_desc;
static const pci_class_desc pci_class_descriptions[] =
{
-{ 0x0100, SCSI controller},
-{ 0x0101, IDE controller},
-{ 0x0102, Floppy controller},
-{ 0x0103, IPI controller},
-{ 0x0104, RAID controller},
+{ 0x0001, VGA controller, display},
+{ 0x0100, SCSI controller, scsi},
+{ 0x0101, IDE controller, ide},
+{ 0x0102, Floppy controller, fdc},
+{ 0x0103, IPI controller, ipi},
+{ 0x0104, RAID controller, raid},
{ 0x0106, SATA controller},
{ 0x0107, SAS controller},
{ 0x0180, Storage controller},
-{ 0x0200, Ethernet controller},
-{ 0x0201, Token Ring controller},
-{ 0x0202, FDDI controller},
-{ 0x0203, ATM controller},
+{ 0x0200, Ethernet controller, ethernet},
+{ 0x0201, Token Ring controller, token-ring},
+{ 0x0202, FDDI controller, fddi},
+{ 0x0203, ATM controller, atm},
{ 0x0280, Network controller},
-{ 0x0300, VGA controller},
+{ 0x0300, VGA controller, display, 0x00ff},
{ 0x0301, XGA controller},
{ 0x0302, 3D controller},
{ 0x0380, Display controller},
-{ 0x0400, Video controller},
-{ 0x0401, Audio controller},
+{ 0x0400, Video controller, video},
+{ 0x0401, Audio controller, sound},
{ 0x0402, Phone},
{ 0x0480, Multimedia controller},
-{ 0x0500, RAM controller},
-{ 0x0501, Flash controller},
+{ 0x0500, RAM controller, memory},
+{ 0x0501, Flash controller, flash},
{ 0x0580, Memory controller},
-{ 0x0600, Host bridge},
-{ 0x0601, ISA bridge},
-{ 0x0602, EISA bridge},
-{ 0x0603, MC bridge},
-{ 0x0604, PCI bridge},
-{ 0x0605, PCMCIA bridge},
-{ 0x0606, NUBUS bridge},
-{ 0x0607, CARDBUS bridge},
+{ 0x0600, Host bridge, host},
+{ 0x0601, ISA bridge, isa},
+{ 0x0602, EISA bridge, eisa},
+{ 0x0603, MC bridge, mca},
+{ 0x0604, PCI bridge, pci},
+{ 0x0605, PCMCIA bridge, pcmcia},
+{ 0x0606, NUBUS bridge, nubus},
+{ 0x0607, CARDBUS bridge, cardbus},
{ 0x0608, RACEWAY bridge},
{ 0x0680, Bridge},
-{ 0x0c03, USB controller},
+{ 0x0700, Serial port, serial},
+{ 0x0701, Parallel port, parallel},
+{ 0x0800, Interrupt controller, interrupt-controller},
+{ 0x0801, DMA controller, dma-controller},
+{ 0x0802, Timer, timer},
+{ 0x0803, RTC, rtc},
+{ 0x0900, Keyboard, keyboard},
+{ 0x0901, Pen, pen},
+{ 0x0902, Mouse, mouse},
+{ 0x0A00, Dock station, dock, 0x00ff},
+{ 0x0B00, i386 cpu, cpu, 0x00ff},
+{ 0x0c00, Fireware contorller, fireware},
+{ 0x0c01, Access bus controller, access-bus},
+{ 0x0c02, SSA controller, ssa},
+{ 0x0c03, USB controller, usb},
+{ 0x0c04, Fibre channel controller, fibre-channel},
{ 0, NULL}
};
@@ -1960,6 +1980,48 @@ static void pcibus_dev_print(Monitor *mon, DeviceState
*dev, int indent)
}
}
+static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
+{
+PCIDevice *d = (PCIDevice *)dev;
+const char *name = NULL;
+const pci_class_desc *desc = pci_class_descriptions;
+int class = pci_get_word(d-config + PCI_CLASS_DEVICE);
+
+while (desc-desc
+ (class ~desc-fw_ign_bits) !=
+ (desc-class ~desc-fw_ign_bits)) {
+desc++;
+}
+
+if (desc-desc) {
+name = desc-fw_name;
+}
+
+if (name) {
+pstrcpy(buf, len, name);
+} else {
+snprintf(buf, len, pci%04x,%04x,
+ pci_get_word(d-config + PCI_VENDOR_ID),
+ pci_get_word(d-config + PCI_DEVICE_ID));
+}
+
+return buf;
+}
+
+static char *pcibus_get_fw_dev_path(DeviceState *dev)
+{
+PCIDevice *d = (PCIDevice *)dev;
+char path[50], name[33];
+int off;
+
+off = snprintf(path, sizeof(path), %...@%x,
+ pci_dev_fw_name(dev, name, sizeof name),
+ PCI_SLOT(d-devfn));
+if
[Qemu-devel] [PATCHv8 05/16] Store IDE bus id in IDEBus structure for easy access.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/ide/cmd646.c |4 ++--
hw/ide/internal.h |3 ++-
hw/ide/isa.c |2 +-
hw/ide/piix.c |4 ++--
hw/ide/qdev.c |3 ++-
hw/ide/via.c |4 ++--
6 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index dfe6091..ea5d2dc 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -253,8 +253,8 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
-ide_bus_new(d-bus[0], d-dev.qdev);
-ide_bus_new(d-bus[1], d-dev.qdev);
+ide_bus_new(d-bus[0], d-dev.qdev, 0);
+ide_bus_new(d-bus[1], d-dev.qdev, 1);
ide_init2(d-bus[0], irq[0]);
ide_init2(d-bus[1], irq[1]);
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 85f4a16..71af66f 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -449,6 +449,7 @@ struct IDEBus {
IDEDevice *slave;
BMDMAState *bmdma;
IDEState ifs[2];
+int bus_id;
uint8_t unit;
uint8_t cmd;
qemu_irq irq;
@@ -567,7 +568,7 @@ void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo
*hd0,
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
/* hw/ide/qdev.c */
-void ide_bus_new(IDEBus *idebus, DeviceState *dev);
+void ide_bus_new(IDEBus *idebus, DeviceState *dev, int bus_id);
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
#endif /* HW_IDE_INTERNAL_H */
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
index 4206afd..8c59c5a 100644
--- a/hw/ide/isa.c
+++ b/hw/ide/isa.c
@@ -67,7 +67,7 @@ static int isa_ide_initfn(ISADevice *dev)
{
ISAIDEState *s = DO_UPCAST(ISAIDEState, dev, dev);
-ide_bus_new(s-bus, s-dev.qdev);
+ide_bus_new(s-bus, s-dev.qdev, 0);
ide_init_ioport(s-bus, s-iobase, s-iobase2);
isa_init_irq(dev, s-irq, s-isairq);
isa_init_ioport_range(dev, s-iobase, 8);
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index e02b89a..1c0cb0c 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -125,8 +125,8 @@ static int pci_piix_ide_initfn(PCIIDEState *d)
vmstate_register(d-dev.qdev, 0, vmstate_ide_pci, d);
-ide_bus_new(d-bus[0], d-dev.qdev);
-ide_bus_new(d-bus[1], d-dev.qdev);
+ide_bus_new(d-bus[0], d-dev.qdev, 0);
+ide_bus_new(d-bus[1], d-dev.qdev, 1);
ide_init_ioport(d-bus[0], 0x1f0, 0x3f6);
ide_init_ioport(d-bus[1], 0x170, 0x376);
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 6d27b60..88ff657 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -29,9 +29,10 @@ static struct BusInfo ide_bus_info = {
.size = sizeof(IDEBus),
};
-void ide_bus_new(IDEBus *idebus, DeviceState *dev)
+void ide_bus_new(IDEBus *idebus, DeviceState *dev, int bus_id)
{
qbus_create_inplace(idebus-qbus, ide_bus_info, dev, NULL);
+idebus-bus_id = bus_id;
}
static int ide_qdev_init(DeviceState *qdev, DeviceInfo *base)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 66be0c4..78857e8 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -154,8 +154,8 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
vmstate_register(dev-qdev, 0, vmstate_ide_pci, d);
-ide_bus_new(d-bus[0], d-dev.qdev);
-ide_bus_new(d-bus[1], d-dev.qdev);
+ide_bus_new(d-bus[0], d-dev.qdev, 0);
+ide_bus_new(d-bus[1], d-dev.qdev, 1);
ide_init2(d-bus[0], isa_reserve_irq(14));
ide_init2(d-bus[1], isa_reserve_irq(15));
ide_init_ioport(d-bus[0], 0x1f0, 0x3f6);
--
1.7.2.3
[Qemu-devel] [PATCHv8 06/16] Add get_fw_dev_path callback to IDE bus.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/ide/qdev.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 88ff657..01a181b 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -24,9 +24,12 @@
/* - */
+static char *idebus_get_fw_dev_path(DeviceState *dev);
+
static struct BusInfo ide_bus_info = {
.name = IDE,
.size = sizeof(IDEBus),
+.get_fw_dev_path = idebus_get_fw_dev_path,
};
void ide_bus_new(IDEBus *idebus, DeviceState *dev, int bus_id)
@@ -35,6 +38,16 @@ void ide_bus_new(IDEBus *idebus, DeviceState *dev, int
bus_id)
idebus-bus_id = bus_id;
}
+static char *idebus_get_fw_dev_path(DeviceState *dev)
+{
+char path[30];
+
+snprintf(path, sizeof(path), %...@%d, qdev_fw_name(dev),
+ ((IDEBus*)dev-parent_bus)-bus_id);
+
+return strdup(path);
+}
+
static int ide_qdev_init(DeviceState *qdev, DeviceInfo *base)
{
IDEDevice *dev = DO_UPCAST(IDEDevice, qdev, qdev);
--
1.7.2.3
[Qemu-devel] [PATCHv8 12/16] Add bootindex parameter to net/block/fd device
If bootindex is specified on command line a string that describes device
in firmware readable way is added into sorted list. Later this list will
be passed into firmware to control boot order.
Signed-off-by: Gleb Natapov g...@redhat.com
---
block_int.h |4 +++-
hw/e1000.c |4
hw/eepro100.c |3 +++
hw/fdc.c|8
hw/ide/qdev.c |5 +
hw/ne2000.c |3 +++
hw/pcnet.c |4
hw/qdev.c | 32
hw/qdev.h |1 +
hw/rtl8139.c|4
hw/scsi-disk.c |1 +
hw/usb-net.c|2 ++
hw/virtio-blk.c |2 ++
hw/virtio-net.c |2 ++
net.h |4 +++-
sysemu.h|2 ++
vl.c| 40
17 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/block_int.h b/block_int.h
index 3c3adb5..0a0e47d 100644
--- a/block_int.h
+++ b/block_int.h
@@ -227,6 +227,7 @@ typedef struct BlockConf {
uint16_t logical_block_size;
uint16_t min_io_size;
uint32_t opt_io_size;
+int32_t bootindex;
} BlockConf;
static inline unsigned int get_physical_block_exp(BlockConf *conf)
@@ -249,6 +250,7 @@ static inline unsigned int get_physical_block_exp(BlockConf
*conf)
DEFINE_PROP_UINT16(physical_block_size, _state, \
_conf.physical_block_size, 512), \
DEFINE_PROP_UINT16(min_io_size, _state, _conf.min_io_size, 0), \
-DEFINE_PROP_UINT32(opt_io_size, _state, _conf.opt_io_size, 0)
+DEFINE_PROP_UINT32(opt_io_size, _state, _conf.opt_io_size, 0),\
+DEFINE_PROP_INT32(bootindex, _state, _conf.bootindex, -1) \
#endif /* BLOCK_INT_H */
diff --git a/hw/e1000.c b/hw/e1000.c
index 57d08cf..e411b03 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -30,6 +30,7 @@
#include net.h
#include net/checksum.h
#include loader.h
+#include sysemu.h
#include e1000_hw.h
@@ -1154,6 +1155,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)
d-dev.qdev.info-name, d-dev.qdev.id, d);
qemu_format_nic_info_str(d-nic-nc, macaddr);
+
+add_boot_device_path(d-conf.bootindex, pci_dev-qdev, /ethernet-...@0);
+
return 0;
}
diff --git a/hw/eepro100.c b/hw/eepro100.c
index f8a700a..a464e9b 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -46,6 +46,7 @@
#include pci.h
#include net.h
#include eeprom93xx.h
+#include sysemu.h
#define KiB 1024
@@ -1907,6 +1908,8 @@ static int e100_nic_init(PCIDevice *pci_dev)
s-vmstate-name = s-nic-nc.model;
vmstate_register(pci_dev-qdev, -1, s-vmstate, s);
+add_boot_device_path(s-conf.bootindex, pci_dev-qdev, /ethernet-...@0);
+
return 0;
}
diff --git a/hw/fdc.c b/hw/fdc.c
index 22fb64a..a7c7c17 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -35,6 +35,7 @@
#include sysbus.h
#include qdev-addr.h
#include blockdev.h
+#include sysemu.h
//
/* debug Floppy devices */
@@ -523,6 +524,8 @@ typedef struct FDCtrlSysBus {
typedef struct FDCtrlISABus {
ISADevice busdev;
struct FDCtrl state;
+int32_t bootindexA;
+int32_t bootindexB;
} FDCtrlISABus;
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
@@ -1992,6 +1995,9 @@ static int isabus_fdc_init1(ISADevice *dev)
qdev_set_legacy_instance_id(dev-qdev, iobase, 2);
ret = fdctrl_init_common(fdctrl);
+add_boot_device_path(isa-bootindexA, dev-qdev, /flo...@0);
+add_boot_device_path(isa-bootindexB, dev-qdev, /flo...@1);
+
return ret;
}
@@ -2051,6 +2057,8 @@ static ISADeviceInfo isa_fdc_info = {
.qdev.props = (Property[]) {
DEFINE_PROP_DRIVE(driveA, FDCtrlISABus, state.drives[0].bs),
DEFINE_PROP_DRIVE(driveB, FDCtrlISABus, state.drives[1].bs),
+DEFINE_PROP_INT32(bootindexA, FDCtrlISABus, bootindexA, -1),
+DEFINE_PROP_INT32(bootindexB, FDCtrlISABus, bootindexB, -1),
DEFINE_PROP_END_OF_LIST(),
},
};
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 01a181b..2bb5c27 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -21,6 +21,7 @@
#include qemu-error.h
#include hw/ide/internal.h
#include blockdev.h
+#include sysemu.h
/* - */
@@ -143,6 +144,10 @@ static int ide_drive_initfn(IDEDevice *dev)
if (!dev-serial) {
dev-serial = qemu_strdup(s-drive_serial_str);
}
+
+add_boot_device_path(dev-conf.bootindex, dev-qdev,
+ dev-unit ? /d...@1 : /d...@0);
+
return 0;
}
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 126e7cf..a030106 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -26,6 +26,7 @@
#include net.h
#include ne2000.h
#include loader.h
+#include sysemu.h
/* debug NE2000 card */
//#define DEBUG_NE2000
@@ -746,6 +747,8 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
}
}
+add_boot_device_path(s-c.bootindex, pci_dev-qdev, /ethernet-...@0);
+
return 0;
}
Re: [Qemu-devel] [PATCH 1/8] ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
On 6 December 2010 17:07, Peter Maydell peter.mayd...@linaro.org wrote: (regarding my random-instruction-sequence testing tool) (I really must get round to writing the README and sticking it in a public git repo.) The curious can find it here: http://git.linaro.org/gitweb?p=people/pmaydell/risu.git;a=summary -- PMM
[Qemu-devel] [PATCHv8 13/16] Change fw_cfg_add_file() to get full file path as a parameter.
Change fw_cfg_add_file() to get full file path as a parameter instead
of building one internally. Two reasons for that. First caller may need
to know how file is named. Second this moves policy of file naming out
from fw_cfg. Platform may want to use more then two levels of
directories for instance.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/fw_cfg.c | 16
hw/fw_cfg.h |4 ++--
hw/loader.c | 16 ++--
3 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index 72866ae..7b9434f 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -277,10 +277,9 @@ int fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
return 1;
}
-int fw_cfg_add_file(FWCfgState *s, const char *dir, const char *filename,
-uint8_t *data, uint32_t len)
+int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
+uint32_t len)
{
-const char *basename;
int i, index;
if (!s-files) {
@@ -297,15 +296,8 @@ int fw_cfg_add_file(FWCfgState *s, const char *dir, const
char *filename,
fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len);
-basename = strrchr(filename, '/');
-if (basename) {
-basename++;
-} else {
-basename = filename;
-}
-
-snprintf(s-files-f[index].name, sizeof(s-files-f[index].name),
- %s/%s, dir, basename);
+pstrcpy(s-files-f[index].name, sizeof(s-files-f[index].name),
+filename);
for (i = 0; i index; i++) {
if (strcmp(s-files-f[index].name, s-files-f[i].name) == 0) {
FW_CFG_DPRINTF(%s: skip duplicate: %s\n, __FUNCTION__,
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index 4d13a4f..856bf91 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -60,8 +60,8 @@ int fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t
value);
int fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value);
int fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
-int fw_cfg_add_file(FWCfgState *s, const char *dir, const char *filename,
-uint8_t *data, uint32_t len);
+int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
+uint32_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t crl_addr, target_phys_addr_t
data_addr);
diff --git a/hw/loader.c b/hw/loader.c
index 49ac1fa..1e98326 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -592,8 +592,20 @@ int rom_add_file(const char *file, const char *fw_dir,
}
close(fd);
rom_insert(rom);
-if (rom-fw_file fw_cfg)
-fw_cfg_add_file(fw_cfg, rom-fw_dir, rom-fw_file, rom-data,
rom-romsize);
+if (rom-fw_file fw_cfg) {
+const char *basename;
+char fw_file_name[56];
+
+basename = strrchr(rom-fw_file, '/');
+if (basename) {
+basename++;
+} else {
+basename = rom-fw_file;
+}
+snprintf(fw_file_name, sizeof(fw_file_name), %s/%s, rom-fw_dir,
+ basename);
+fw_cfg_add_file(fw_cfg, fw_file_name, rom-data, rom-romsize);
+}
return 0;
err:
--
1.7.2.3
[Qemu-devel] [PATCHv8 10/16] Add get_fw_dev_path callback for usb bus.
Signed-off-by: Gleb Natapov g...@redhat.com
---
hw/usb-bus.c | 42 ++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/hw/usb-bus.c b/hw/usb-bus.c
index 256b881..8b4583c 100644
--- a/hw/usb-bus.c
+++ b/hw/usb-bus.c
@@ -5,11 +5,13 @@
#include monitor.h
static void usb_bus_dev_print(Monitor *mon, DeviceState *qdev, int indent);
+static char *usbbus_get_fw_dev_path(DeviceState *dev);
static struct BusInfo usb_bus_info = {
.name = USB,
.size = sizeof(USBBus),
.print_dev = usb_bus_dev_print,
+.get_fw_dev_path = usbbus_get_fw_dev_path,
};
static int next_usb_bus = 0;
static QTAILQ_HEAD(, USBBus) busses = QTAILQ_HEAD_INITIALIZER(busses);
@@ -307,3 +309,43 @@ USBDevice *usbdevice_create(const char *cmdline)
}
return usb-usbdevice_init(params);
}
+
+static int usbbus_get_fw_dev_path_helper(USBDevice *d, USBBus *bus, char *p,
+ int len)
+{
+int l = 0;
+USBPort *port;
+
+QTAILQ_FOREACH(port, bus-used, next) {
+if (port-dev == d) {
+if (port-pdev) {
+l = usbbus_get_fw_dev_path_helper(port-pdev, bus, p, len);
+}
+l += snprintf(p + l, len - l, %...@%x/, qdev_fw_name(d-qdev),
+ port-index);
+break;
+}
+}
+
+return l;
+}
+
+static char *usbbus_get_fw_dev_path(DeviceState *dev)
+{
+USBDevice *d = (USBDevice*)dev;
+USBBus *bus = usb_bus_from_device(d);
+char path[100];
+int l;
+
+assert(d-attached != 0);
+
+l = usbbus_get_fw_dev_path_helper(d, bus, path, sizeof(path));
+
+if (l == 0) {
+abort();
+}
+
+path[l-1] = '\0';
+
+return strdup(path);
+}
--
1.7.2.3
[Qemu-devel] [PATCH 08/13] pci: add ich7 pci id
We need a PCI ID for our new AHCI adapter. I just picked an ICH-7M because that's the one built into the first Macbooks. This patch adds a PCI ID define for an ICH-7 AHCI adapter. Signed-off-by: Alexander Graf ag...@suse.de --- v3 - v4: - add ICH7 instead of ICH7M (herbszt) v4 - v5: - rename to ICH7_AHCI_RAID (herbszt) v6 - v7: - use non-raid ich7 ahci (herbszt) --- hw/pci.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/pci.h b/hw/pci.h index 89f7b76..0dce2b0 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -62,6 +62,7 @@ /* Intel (0x8086) */ #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 #define PCI_DEVICE_ID_INTEL_825570x1229 +#define PCI_DEVICE_ID_INTEL_ICH7_AHCI0x27c1 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ #define PCI_VENDOR_ID_REDHAT_QUMRANET0x1af4 -- 1.6.0.2
[Qemu-devel] [PATCH 11/13] config: add ahci for pci capable machines
This patch enables AHCI for all machines supporting PCI. Signed-off-by: Alexander Graf ag...@suse.de --- default-configs/pci.mak |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/default-configs/pci.mak b/default-configs/pci.mak index d700b3c..0471efb 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -13,3 +13,4 @@ CONFIG_E1000_PCI=y CONFIG_IDE_CORE=y CONFIG_IDE_QDEV=y CONFIG_IDE_PCI=y +CONFIG_AHCI=y -- 1.6.0.2
[Qemu-devel] [PATCH 06/13] ide: add ncq identify data for ahci sata drives
From: Roland Elek elek.rol...@gmail.com
I modified ide_identify() to include the zero-based queue length
value in word 75, and set bit 8 in word 76 to signal NCQ support
in the identify data for AHCI SATA drives.
Signed-off-by: Roland Elek elek.rol...@gmail.com
---
hw/ide/core.c |7 +++
hw/ide/internal.h |2 ++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 6284539..a3f8104 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -140,6 +140,13 @@ static void ide_identify(IDEState *s)
put_le16(p + 66, 120);
put_le16(p + 67, 120);
put_le16(p + 68, 120);
+
+if (s-ncq_queues) {
+put_le16(p + 75, s-ncq_queues - 1);
+/* NCQ supported */
+put_le16(p + 76, (1 8));
+}
+
put_le16(p + 80, 0xf0); /* ata3 - ata6 supported */
put_le16(p + 81, 0x16); /* conforms to ata5 */
/* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 7e2ba1a..414adf5 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -453,6 +453,8 @@ struct IDEState {
int smart_errors;
uint8_t smart_selftest_count;
uint8_t *smart_selftest_data;
+/* AHCI */
+int ncq_queues;
};
struct IDEDMAOps {
--
1.6.0.2
[Qemu-devel] [PATCH 12/13] ahci: set SATA Mode Select
From: Sebastian Herbszt herb...@gmx.de Set SATA Mode Select to AHCI in the Address Map Register. Signed-off-by: Sebastian Herbszt herb...@gmx.de --- hw/ide/ahci.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 7e7aa89..2ef03ed 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1328,6 +1328,9 @@ static int pci_ahci_init(PCIDevice *dev) d-card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ pci_config_set_interrupt_pin(d-card.config, 1); +/* XXX Software should program this register */ +d-card.config[0x90] = 1 6; /* Address Map Register - AHCI mode */ + qemu_register_reset(ahci_reset, d); /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ -- 1.6.0.2
[Qemu-devel] [PATCH 13/13] ahci: set pci revision id
From: Sebastian Herbszt herb...@gmx.de Set pci revision id to 0x01. Signed-off-by: Sebastian Herbszt herb...@gmx.de --- hw/ide/ahci.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 2ef03ed..fdfc011 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1322,6 +1322,7 @@ static int pci_ahci_init(PCIDevice *dev) PCI_DEVICE_ID_INTEL_ICH7_AHCI); pci_config_set_class(d-card.config, PCI_CLASS_STORAGE_SATA); +pci_config_set_revision(d-card.config, 0x01); pci_config_set_prog_interface(d-card.config, AHCI_PROGMODE_MAJOR_REV_1); d-card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ -- 1.6.0.2
[Qemu-devel] Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves
On 12/08/2010 01:13 PM, Andre Przywara wrote: Avi, Marcello, can you please commit this simple fix? (turning 40 to 80?) Without it QEMU crashes reliably on our new CPUs (they return 46 leaves) and causes pain in our testing, because we have to manually apply this patch on each tree. Sorry about that, applied now. -- error compiling committee.c: too many arguments to function
[Qemu-devel] [PATCH 04/13] bmdma: split out irq setting
The IDE core doesn't care about BMDMA blocking IRQs from getting submitted,
so let's reflect that in the code and make IRQ blocking fully transparent.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c |6 --
hw/ide/internal.h |4 ++--
hw/ide/pci.c | 44 +++-
3 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index fce994f..6284539 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2586,18 +2586,12 @@ static void ide_init1(IDEBus *bus, int unit)
ide_sector_write_timer_cb, s);
}
-static int ide_nop_start_irq(void *opaque)
-{
-return 1;
-}
-
static int ide_nop(void *opaque)
{
return 0;
}
static const IDEDMAOps ide_dma_nop = {
-.start_irq = ide_nop_start_irq,
.start_dma = (void*)ide_nop,
.start_transfer = (void*)ide_nop,
.prepare_buf= (void*)ide_nop,
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 15ab119..af7e741 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -457,7 +457,6 @@ struct IDEState {
};
struct IDEDMAOps {
-DMAFunc *start_irq;
DMAStartFunc *start_dma;
DMAFunc *start_transfer;
DMAIntFunc *prepare_buf;
@@ -530,6 +529,7 @@ struct BMDMAState {
uint32_t nsector;
IORange addr_ioport;
QEMUBH *bh;
+qemu_irq irq;
};
static inline IDEState *idebus_active_if(IDEBus *bus)
@@ -545,7 +545,7 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
static inline void ide_set_irq(IDEBus *bus)
{
-if (bus-dma.ops-start_irq(bus-dma.opaque)) {
+if (!(bus-cmd IDE_CMD_DISABLE_IRQ)) {
qemu_irq_raise(bus-irq);
}
}
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 2506cc5..270c13a 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -35,22 +35,6 @@
#define BMDMA_PAGE_SIZE 4096
-static int bmdma_start_irq(void *opaque)
-{
-BMDMAState *bm = opaque;
-IDEBus *bus = bm-bus;
-
-if (!(bus-cmd IDE_CMD_DISABLE_IRQ)) {
-if (bm) {
-bm-status |= BM_STATUS_INT;
-}
-return 1;
-}
-
-/* IRQ forbidden */
-return 0;
-}
-
static void bmdma_start_dma(void *opaque, IDEState *s,
BlockDriverCompletionFunc *dma_cb)
{
@@ -286,6 +270,24 @@ static int bmdma_start_transfer(void *opaque)
return 0;
}
+static void bmdma_irq(void *opaque, int n, int level)
+{
+BMDMAState *bm = opaque;
+
+if (!level) {
+/* pass through lower */
+qemu_set_irq(bm-irq, level);
+return;
+}
+
+if (bm) {
+bm-status |= BM_STATUS_INT;
+}
+
+/* trigger the real irq */
+qemu_set_irq(bm-irq, level);
+}
+
void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
{
BMDMAState *bm = opaque;
@@ -453,7 +455,6 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo
**hd_table)
}
static const struct IDEDMAOps bmdma_ops = {
-.start_irq = bmdma_start_irq,
.start_dma = bmdma_start_dma,
.start_transfer = bmdma_start_transfer,
.prepare_buf = bmdma_prepare_buf,
@@ -467,6 +468,15 @@ static const struct IDEDMAOps bmdma_ops = {
void bmdma_init(IDEBus *bus, BMDMAState *bm)
{
+qemu_irq *irq;
+
+if (bus-dma.ops == bmdma_ops) {
+return;
+}
+
bus-dma.ops = bmdma_ops;
bus-dma.opaque = bm;
+bm-irq = bus-irq;
+irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
+bus-irq = *irq;
}
--
1.6.0.2
[Qemu-devel] [PATCH 10/13] config: move ide core and pci to pci.mak
Every device that can do PCI should also be able to do IDE. So let's move the IDE definitions over to pci.mak. Signed-off-by: Alexander Graf ag...@suse.de --- default-configs/arm-softmmu.mak |1 - default-configs/i386-softmmu.mak |3 --- default-configs/mips-softmmu.mak |3 --- default-configs/mips64-softmmu.mak |3 --- default-configs/mips64el-softmmu.mak |3 --- default-configs/mipsel-softmmu.mak |3 --- default-configs/pci.mak |3 +++ default-configs/ppc-softmmu.mak |3 --- default-configs/ppc64-softmmu.mak|3 --- default-configs/ppcemb-softmmu.mak |3 --- default-configs/sh4-softmmu.mak |1 - default-configs/sh4eb-softmmu.mak|1 - default-configs/sparc64-softmmu.mak |3 --- default-configs/x86_64-softmmu.mak |3 --- 14 files changed, 3 insertions(+), 33 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index ac48dc1..8d1174f 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -8,7 +8,6 @@ CONFIG_ECC=y CONFIG_SERIAL=y CONFIG_PTIMER=y CONFIG_SD=y -CONFIG_IDE_CORE=y CONFIG_MAX7310=y CONFIG_WM8750=y CONFIG_TWL92230=y diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak index ce905d2..323fafb 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -13,9 +13,6 @@ CONFIG_FDC=y CONFIG_ACPI=y CONFIG_APM=y CONFIG_DMA=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_PIIX=y CONFIG_NE2000_ISA=y diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak index 565e611..f524971 100644 --- a/default-configs/mips-softmmu.mak +++ b/default-configs/mips-softmmu.mak @@ -17,9 +17,6 @@ CONFIG_ACPI=y CONFIG_APM=y CONFIG_DMA=y CONFIG_PIIX4=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_PIIX=y CONFIG_NE2000_ISA=y diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak index 03bd8eb..aeab6b2 100644 --- a/default-configs/mips64-softmmu.mak +++ b/default-configs/mips64-softmmu.mak @@ -17,9 +17,6 @@ CONFIG_ACPI=y CONFIG_APM=y CONFIG_DMA=y CONFIG_PIIX4=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_PIIX=y CONFIG_NE2000_ISA=y diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak index 4661617..8e6511c 100644 --- a/default-configs/mips64el-softmmu.mak +++ b/default-configs/mips64el-softmmu.mak @@ -17,9 +17,6 @@ CONFIG_ACPI=y CONFIG_APM=y CONFIG_DMA=y CONFIG_PIIX4=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_PIIX=y CONFIG_IDE_VIA=y diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak index 92fc473..a05ac25 100644 --- a/default-configs/mipsel-softmmu.mak +++ b/default-configs/mipsel-softmmu.mak @@ -17,9 +17,6 @@ CONFIG_ACPI=y CONFIG_APM=y CONFIG_DMA=y CONFIG_PIIX4=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_PIIX=y CONFIG_NE2000_ISA=y diff --git a/default-configs/pci.mak b/default-configs/pci.mak index c74a99f..d700b3c 100644 --- a/default-configs/pci.mak +++ b/default-configs/pci.mak @@ -10,3 +10,6 @@ CONFIG_PCNET_COMMON=y CONFIG_LSI_SCSI_PCI=y CONFIG_RTL8139_PCI=y CONFIG_E1000_PCI=y +CONFIG_IDE_CORE=y +CONFIG_IDE_QDEV=y +CONFIG_IDE_PCI=y diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index f1cb99e..4563742 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -23,9 +23,6 @@ CONFIG_GRACKLE_PCI=y CONFIG_UNIN_PCI=y CONFIG_DEC_PCI=y CONFIG_PPCE500_PCI=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_CMD646=y CONFIG_IDE_MACIO=y diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak index 83cbe97..d5073b3 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -23,9 +23,6 @@ CONFIG_GRACKLE_PCI=y CONFIG_UNIN_PCI=y CONFIG_DEC_PCI=y CONFIG_PPCE500_PCI=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_CMD646=y CONFIG_IDE_MACIO=y diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak index 2b52d4a..9f0730c 100644 --- a/default-configs/ppcemb-softmmu.mak +++ b/default-configs/ppcemb-softmmu.mak @@ -23,9 +23,6 @@ CONFIG_GRACKLE_PCI=y CONFIG_UNIN_PCI=y CONFIG_DEC_PCI=y CONFIG_PPCE500_PCI=y -CONFIG_IDE_CORE=y -CONFIG_IDE_QDEV=y -CONFIG_IDE_PCI=y CONFIG_IDE_ISA=y CONFIG_IDE_CMD646=y CONFIG_IDE_MACIO=y diff --git a/default-configs/sh4-softmmu.mak b/default-configs/sh4-softmmu.mak index 87247a4..5c69acc 100644 --- a/default-configs/sh4-softmmu.mak +++ b/default-configs/sh4-softmmu.mak @@ -3,6 +3,5 @@ include pci.mak CONFIG_SERIAL=y CONFIG_PTIMER=y -CONFIG_IDE_CORE=y CONFIG_PFLASH_CFI02=y CONFIG_ISA_MMIO=y
[Qemu-devel] [PATCH 05/13] bmdma: move header definitions out
The bmdma header definitions currently reside in generic code, but only PCI
specific code should know about BMDMA internals. So let's move the definitions
and everything using them out to pci.h.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/internal.h | 27 ---
hw/ide/pci.h | 28
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index af7e741..7e2ba1a 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -20,7 +20,6 @@ typedef struct IDEBus IDEBus;
typedef struct IDEDevice IDEDevice;
typedef struct IDEDeviceInfo IDEDeviceInfo;
typedef struct IDEState IDEState;
-typedef struct BMDMAState BMDMAState;
typedef struct IDEDMA IDEDMA;
typedef struct IDEDMAOps IDEDMAOps;
@@ -512,37 +511,11 @@ struct IDEDeviceInfo {
#define BM_CMD_START 0x01
#define BM_CMD_READ 0x08
-struct BMDMAState {
-uint8_t cmd;
-uint8_t status;
-uint32_t addr;
-
-IDEBus *bus;
-/* current transfer state */
-uint32_t cur_addr;
-uint32_t cur_prd_last;
-uint32_t cur_prd_addr;
-uint32_t cur_prd_len;
-uint8_t unit;
-BlockDriverCompletionFunc *dma_cb;
-int64_t sector_num;
-uint32_t nsector;
-IORange addr_ioport;
-QEMUBH *bh;
-qemu_irq irq;
-};
-
static inline IDEState *idebus_active_if(IDEBus *bus)
{
return bus-ifs + bus-unit;
}
-static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
-{
-assert(bmdma-unit != (uint8_t)-1);
-return bmdma-bus-ifs + bmdma-unit;
-}
-
static inline void ide_set_irq(IDEBus *bus)
{
if (!(bus-cmd IDE_CMD_DISABLE_IRQ)) {
diff --git a/hw/ide/pci.h b/hw/ide/pci.h
index 1cd7b06..0f96297 100644
--- a/hw/ide/pci.h
+++ b/hw/ide/pci.h
@@ -3,6 +3,26 @@
#include hw/ide/internal.h
+typedef struct BMDMAState {
+uint8_t cmd;
+uint8_t status;
+uint32_t addr;
+
+IDEBus *bus;
+/* current transfer state */
+uint32_t cur_addr;
+uint32_t cur_prd_last;
+uint32_t cur_prd_addr;
+uint32_t cur_prd_len;
+uint8_t unit;
+BlockDriverCompletionFunc *dma_cb;
+int64_t sector_num;
+uint32_t nsector;
+IORange addr_ioport;
+QEMUBH *bh;
+qemu_irq irq;
+} BMDMAState;
+
typedef struct PCIIDEState {
PCIDevice dev;
IDEBus bus[2];
@@ -10,6 +30,14 @@ typedef struct PCIIDEState {
uint32_t secondary; /* used only for cmd646 */
} PCIIDEState;
+
+static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
+{
+assert(bmdma-unit != (uint8_t)-1);
+return bmdma-bus-ifs + bmdma-unit;
+}
+
+
void bmdma_init(IDEBus *bus, BMDMAState *bm);
void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val);
extern const IORangeOps bmdma_addr_ioport_ops;
--
1.6.0.2
[Qemu-devel] [PATCH 01/13] ide: split ide command interpretation off
The ATA command interpretation code can be used for PATA and SATA
interfaces alike. So let's split it out into a separate function.
Signed-off-by: Alexander Graf ag...@suse.de
---
v6 - v7:
- use bus instead of opaque (stefanha)
---
hw/ide/core.c | 20 ++--
hw/ide/internal.h |2 ++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 430350f..ac4ee71 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -1791,9 +1791,6 @@ static void ide_clear_hob(IDEBus *bus)
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
-IDEState *s;
-int n;
-int lba48 = 0;
#ifdef DEBUG_IDE
printf(IDE: write addr=0x%x val=0x%02x\n, addr, val);
@@ -1854,17 +1851,29 @@ void ide_ioport_write(void *opaque, uint32_t addr,
uint32_t val)
default:
case 7:
/* command */
+ide_exec_cmd(bus, val);
+break;
+}
+}
+
+
+void ide_exec_cmd(IDEBus *bus, uint32_t val)
+{
+IDEState *s;
+int n;
+int lba48 = 0;
+
#if defined(DEBUG_IDE)
printf(ide: CMD=%02x\n, val);
#endif
s = idebus_active_if(bus);
/* ignore commands to non existant slave */
if (s != bus-ifs !s-bs)
-break;
+return;
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
if ((s-status (BUSY_STAT|DRQ_STAT)) val != WIN_DEVICE_RESET)
-break;
+return;
switch(val) {
case WIN_IDENTIFY:
@@ -2355,7 +2364,6 @@ void ide_ioport_write(void *opaque, uint32_t addr,
uint32_t val)
ide_set_irq(s-bus);
break;
}
-}
}
uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 85f4a16..8617b87 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -566,6 +566,8 @@ void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo
*hd0,
DriveInfo *hd1, qemu_irq irq);
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
+void ide_exec_cmd(IDEBus *bus, uint32_t val);
+
/* hw/ide/qdev.c */
void ide_bus_new(IDEBus *idebus, DeviceState *dev);
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
--
1.6.0.2
[Qemu-devel] [PATCH 00/13] AHCI emulation support v8
This patch adds support for AHCI emulation. I have tested and verified it works in Linux, OpenBSD, Windows Vista and Windows 7. This AHCI emulation supports NCQ, so multiple read or write requests can be outstanding at the same time. The code is however not fully optimized yet. I'm fairly sure that there are low hanging performance fruits to be found still :). In my simple benchmarks I achieved about 2/3rd of virtio performance. Also, this AHCI emulation layer does not support legacy mode. So if you're using a disk with this emulation, you do not get it exposed using the legacy IDE interfaces. Another nitpick is CD-ROM support in Windows. Somehow it doesn't detect a CD-ROM drive attached to AHCI. At least it doesn't list it. To attach an AHCI disk to your VM, please use -drive id=disk,file=...,if=none -device ahci,id=ahci \ -device ide-drive,drive=disk,bus=ahci.0 Big endian hosts are still broken due to qemu shortcomings in mmio handing. With the mmio endianness patch set, ahci works there too. This patch set is based on work done during the Google Summer of Code. I was mentoring a student, Roland Elek, who wrote most of the AHCI emulation code based on a patch from Chong Qiao. A bunch of other people were also involved, so everybody who I didn't mention - thanks a lot! git://repo.or.cz/qemu/ahci.git ahci v1 - v2: - rename IDEExtender to IDEBusOps and make a pointer (kraxel) - make dma hooks explicit by putting them into ops struct (stefanha) - use qdev buses (kraxel) - minor cleanups - dprintf overhaul - add reset function v2 - v3: - add msi support (kraxel) - use MIN macro (kraxel) - add msi support (kraxel) - fix ncq with multiple ports - zap qdev properties (kraxel) - redesign legacy IF_SATA hooks (kraxel) - don't build ahci as part of target - move to ide/ (kwolf) v3 - v4: - prepare for endianness safety - add lspci dump (herbszt) - use ich7 instead of ich7m (herbszt) - fix lst+fis mapping (kraxel) - coding style (blue swirl) - explicit mmio setters/getters (blue swirl) - split pata code out to pata.c (kwolf) - only include config-devices.h in machine description (blue swirl) v4 - v5: - s/H2dNcqFis/NCQFrame/g (blue swirl) - redo -drive magic (blue swirl) - bump BAR to 4k - rename ICH7_AHCI to ICH7_AHCI_RAID (herbszt) - drop device config header (blue swirl) v5 - v6: - PCI config space fixes (isaku) - remove CONFIG_AHCI from x86 default configs (paul brook) - use snprintf (blue swirl) - add generic PCI config file (paul brook) - build ahci on all PCI platforms (paul brook) v6 - v7: - use bus instead of opaque (stefanha) - change naming in IDEBusOps (stefanha, kwolf) - rename IDEBusOps (stefanha) - improve interrupt injection - combine tfdata code paths - update tfdata more often - reset port registers on port reset - improve debug output - add feature variable from fis for some extended commands - always set feature to DMA for atapi - osx 10.5.0 works as of this version - use non-raid ich7 ahci (herbszt) - reflect normal ich7 in pci dump - stick to new IDEBusOps (stefanha, kwolf) - stefan's ahci comments v7 - v8: - rewrite ops as DMA offsplit framework - split bmdma stuff out to pci.c - generate tfdata on the fly - reimplement immediate dma rw - add safety net for busy engine - adjust ahci code for new DMA framework - move ide core+pci to pci.mak - add sebastian's config space patches Alexander Graf (10): ide: split ide command interpretation off ide: fix whitespace gap in ide_exec_cmd ide: Split out BMDMA code from ATA core bmdma: split out irq setting bmdma: move header definitions out pci: add storage class for sata pci: add ich7 pci id ahci: add ahci emulation config: move ide core and pci to pci.mak config: add ahci for pci capable machines Roland Elek (1): ide: add ncq identify data for ahci sata drives Sebastian Herbszt (2): ahci: set SATA Mode Select ahci: set pci revision id Makefile.objs|1 + default-configs/arm-softmmu.mak |1 - default-configs/i386-softmmu.mak |3 - default-configs/mips-softmmu.mak |3 - default-configs/mips64-softmmu.mak |3 - default-configs/mips64el-softmmu.mak |3 - default-configs/mipsel-softmmu.mak |3 - default-configs/pci.mak |4 + default-configs/ppc-softmmu.mak |3 - default-configs/ppc64-softmmu.mak|3 - default-configs/ppcemb-softmmu.mak |3 - default-configs/sh4-softmmu.mak |1 - default-configs/sh4eb-softmmu.mak|1 - default-configs/sparc64-softmmu.mak |3 - default-configs/x86_64-softmmu.mak |3 - hw/ide/ahci.c| 1378 ++ hw/ide/cmd646.c |6 +- hw/ide/core.c| 1071 +++--- hw/ide/internal.h| 80 ++- hw/ide/pci.c
[Qemu-devel] Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves
On 12/01/2010 02:55 PM, Andre Przywara wrote: Avi Kivity wrote: On 12/01/2010 01:17 PM, Andre Przywara wrote: Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywaraandre.przyw...@amd.com --- arch/x86/include/asm/kvm_host.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) Hi, I found that either KVM or QEMU (possibly both) are broken in respect to handling more CPUID entries than the limit dictates. KVM will return -E2BIG, which is the same error as if the user hasn't provided enough space to hold all entries. Now QEMU will continue to enlarge the allocated memory until it gets into an out-of-memory condition. I have tried to fix this with teaching KVM how to deal with a capped number of entries (there are some bugs in the current code), but this will limit the number of CPUID entries KVM handles, which will surely cut of the lastly appended PV leaves. A proper fix would be to make this allocation dynamic. Is this a feasible way or will this lead to issues or side-effects? Well, there has to be some limit, or userspace can allocate unbounded kernel memory. But this limit should not be a compile-time constant, but a runtime one. The needed size depends on the host CPU (plus the KVM PV leaves) and thus could be determined once for all VMs and vCPUs at module load-time. But then we cannot use the static array allocation we currently have in struct kvm_vcpu_arch: struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; So we would use a kind-of dynamic allocation bounded by the host CPU's need. But for the code is does not make much difference to a real dynamic allocation. Also we could implement kvm_dev_ioctl_get_supported_cpuid without the vmalloc, if we don't care about some dozens of copy_to_user() calls in this function. Then we would not need this limit in GET_SUPPORTED_CPUID at all, but it will strike us again at KVM_SET_CPUID[2], where we may not fulfill the promises we gave earlier. Having said this, what about that: kvm_dev_ioctl_get_supported_cpuid is invariant to the VM or vCPU (as it is used by a system ioctl), so it could be run once at initialization, which would limit the ioctl implementation to a plain bounded copy. Would you want such a patch (removing the vmalloc and maybe even the limit)? Making GET_SUPPORTED_CPUID data static would be an improvement, yes. -- error compiling committee.c: too many arguments to function
[Qemu-devel] [PATCH 07/13] pci: add storage class for sata
This patch adds the storage sata class id. Signed-off-by: Alexander Graf ag...@suse.de --- hw/pci_ids.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/pci_ids.h b/hw/pci_ids.h index 82cba7e..ea3418c 100644 --- a/hw/pci_ids.h +++ b/hw/pci_ids.h @@ -15,6 +15,7 @@ #define PCI_CLASS_STORAGE_SCSI 0x0100 #define PCI_CLASS_STORAGE_IDE0x0101 +#define PCI_CLASS_STORAGE_SATA 0x0106 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_CLASS_NETWORK_ETHERNET 0x0200 -- 1.6.0.2
[Qemu-devel] [PATCH 02/13] ide: fix whitespace gap in ide_exec_cmd
Now that we have the function split out, we have to reindent it.
In order to increase the readability of the actual functional change,
this is split out.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/core.c | 734
1 files changed, 367 insertions(+), 367 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index ac4ee71..5e2fcbd 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -1864,423 +1864,423 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
int lba48 = 0;
#if defined(DEBUG_IDE)
-printf(ide: CMD=%02x\n, val);
+printf(ide: CMD=%02x\n, val);
#endif
-s = idebus_active_if(bus);
-/* ignore commands to non existant slave */
-if (s != bus-ifs !s-bs)
-return;
+s = idebus_active_if(bus);
+/* ignore commands to non existant slave */
+if (s != bus-ifs !s-bs)
+return;
-/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
-if ((s-status (BUSY_STAT|DRQ_STAT)) val != WIN_DEVICE_RESET)
-return;
+/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
+if ((s-status (BUSY_STAT|DRQ_STAT)) val != WIN_DEVICE_RESET)
+return;
-switch(val) {
-case WIN_IDENTIFY:
-if (s-bs s-drive_kind != IDE_CD) {
-if (s-drive_kind != IDE_CFATA)
-ide_identify(s);
-else
-ide_cfata_identify(s);
-s-status = READY_STAT | SEEK_STAT;
-ide_transfer_start(s, s-io_buffer, 512, ide_transfer_stop);
-} else {
-if (s-drive_kind == IDE_CD) {
-ide_set_signature(s);
-}
-ide_abort_command(s);
-}
-ide_set_irq(s-bus);
-break;
-case WIN_SPECIFY:
-case WIN_RECAL:
-s-error = 0;
+switch(val) {
+case WIN_IDENTIFY:
+if (s-bs s-drive_kind != IDE_CD) {
+if (s-drive_kind != IDE_CFATA)
+ide_identify(s);
+else
+ide_cfata_identify(s);
s-status = READY_STAT | SEEK_STAT;
-ide_set_irq(s-bus);
-break;
-case WIN_SETMULT:
-if (s-drive_kind == IDE_CFATA s-nsector == 0) {
-/* Disable Read and Write Multiple */
-s-mult_sectors = 0;
-s-status = READY_STAT | SEEK_STAT;
-} else if ((s-nsector 0xff) != 0
-((s-nsector 0xff) MAX_MULT_SECTORS ||
- (s-nsector (s-nsector - 1)) != 0)) {
-ide_abort_command(s);
-} else {
-s-mult_sectors = s-nsector 0xff;
-s-status = READY_STAT | SEEK_STAT;
+ide_transfer_start(s, s-io_buffer, 512, ide_transfer_stop);
+} else {
+if (s-drive_kind == IDE_CD) {
+ide_set_signature(s);
}
-ide_set_irq(s-bus);
-break;
-case WIN_VERIFY_EXT:
- lba48 = 1;
-case WIN_VERIFY:
-case WIN_VERIFY_ONCE:
-/* do sector number check ? */
- ide_cmd_lba48_transform(s, lba48);
+ide_abort_command(s);
+}
+ide_set_irq(s-bus);
+break;
+case WIN_SPECIFY:
+case WIN_RECAL:
+s-error = 0;
+s-status = READY_STAT | SEEK_STAT;
+ide_set_irq(s-bus);
+break;
+case WIN_SETMULT:
+if (s-drive_kind == IDE_CFATA s-nsector == 0) {
+/* Disable Read and Write Multiple */
+s-mult_sectors = 0;
s-status = READY_STAT | SEEK_STAT;
-ide_set_irq(s-bus);
-break;
+} else if ((s-nsector 0xff) != 0
+((s-nsector 0xff) MAX_MULT_SECTORS ||
+ (s-nsector (s-nsector - 1)) != 0)) {
+ide_abort_command(s);
+} else {
+s-mult_sectors = s-nsector 0xff;
+s-status = READY_STAT | SEEK_STAT;
+}
+ide_set_irq(s-bus);
+break;
+case WIN_VERIFY_EXT:
+ lba48 = 1;
+case WIN_VERIFY:
+case WIN_VERIFY_ONCE:
+/* do sector number check ? */
+ ide_cmd_lba48_transform(s, lba48);
+s-status = READY_STAT | SEEK_STAT;
+ide_set_irq(s-bus);
+break;
case WIN_READ_EXT:
- lba48 = 1;
-case WIN_READ:
-case WIN_READ_ONCE:
-if (!s-bs)
-goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
-s-req_nb_sectors = 1;
-ide_sector_read(s);
-break;
+ lba48 = 1;
+case WIN_READ:
+case WIN_READ_ONCE:
+if (!s-bs)
+goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+s-req_nb_sectors = 1;
+ide_sector_read(s);
+break;
case WIN_WRITE_EXT:
- lba48 = 1;
-case
[Qemu-devel] [PATCH 03/13] ide: Split out BMDMA code from ATA core
The ATA core is currently heavily intertwined with BMDMA code. Let's loosen
that a bit, so we can happily replace the DMA backend with different
implementations.
Signed-off-by: Alexander Graf ag...@suse.de
---
v7 - v8:
- rewrite as DMA ops
---
hw/ide/cmd646.c |6 +-
hw/ide/core.c | 322 -
hw/ide/internal.h | 53 +++--
hw/ide/pci.c | 278 +-
hw/ide/pci.h |1 +
hw/ide/piix.c |6 +-
hw/ide/via.c |6 +-
7 files changed, 399 insertions(+), 273 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index dfe6091..ecfa4d6 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -167,9 +167,9 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
for(i = 0;i 2; i++) {
BMDMAState *bm = d-bmdma[i];
-d-bus[i].bmdma = bm;
+bmdma_init(d-bus[i], bm);
bm-bus = d-bus+i;
-qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
+qemu_add_vm_change_state_handler(d-bus[i].dma.ops-restart_cb, bm);
if (i == 0) {
register_ioport_write(addr, 4, 1, bmdma_writeb_0, d);
@@ -218,7 +218,7 @@ static void cmd646_reset(void *opaque)
for (i = 0; i 2; i++) {
ide_bus_reset(d-bus[i]);
-ide_dma_reset(d-bmdma[i]);
+d-bus[i].dma.ops-reset(d-bmdma[i]);
}
}
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 5e2fcbd..fce994f 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -34,8 +34,6 @@
#include hw/ide/internal.h
-#define IDE_PAGE_SIZE 4096
-
static const int smart_attributes[][5] = {
/* id, flags, val, wrst, thrsh */
{ 0x01, 0x03, 0x64, 0x64, 0x06}, /* raw read */
@@ -61,11 +59,8 @@ static inline int media_is_cd(IDEState *s)
return (media_present(s) s-nb_sectors = CD_MAX_SECTORS);
}
-static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
-static void ide_dma_restart(IDEState *s, int is_read);
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
static int ide_handle_rw_error(IDEState *s, int error, int op);
-static void ide_flush_cache(IDEState *s);
static void padstr(char *str, const char *src, int len)
{
@@ -314,11 +309,11 @@ static inline void ide_abort_command(IDEState *s)
}
static inline void ide_dma_submit_check(IDEState *s,
- BlockDriverCompletionFunc *dma_cb, BMDMAState *bm)
+ BlockDriverCompletionFunc *dma_cb)
{
-if (bm-aiocb)
+if (s-bus-dma.aiocb)
return;
-dma_cb(bm, -1);
+dma_cb(s, -1);
}
/* prepare data transfer and tell what to do after */
@@ -328,8 +323,10 @@ static void ide_transfer_start(IDEState *s, uint8_t *buf,
int size,
s-end_transfer_func = end_transfer_func;
s-data_ptr = buf;
s-data_end = buf + size;
-if (!(s-status ERR_STAT))
+if (!(s-status ERR_STAT)) {
s-status |= DRQ_STAT;
+}
+s-bus-dma.ops-start_transfer(s-bus-dma.opaque);
}
static void ide_transfer_stop(IDEState *s)
@@ -394,7 +391,7 @@ static void ide_rw_error(IDEState *s) {
ide_set_irq(s-bus);
}
-static void ide_sector_read(IDEState *s)
+void ide_sector_read(IDEState *s)
{
int64_t sector_num;
int ret, n;
@@ -427,58 +424,15 @@ static void ide_sector_read(IDEState *s)
}
}
-
-/* return 0 if buffer completed */
-static int dma_buf_prepare(BMDMAState *bm, int is_write)
-{
-IDEState *s = bmdma_active_if(bm);
-struct {
-uint32_t addr;
-uint32_t size;
-} prd;
-int l, len;
-
-qemu_sglist_init(s-sg, s-nsector / (IDE_PAGE_SIZE / 512) + 1);
-s-io_buffer_size = 0;
-for(;;) {
-if (bm-cur_prd_len == 0) {
-/* end of table (with a fail safe of one page) */
-if (bm-cur_prd_last ||
-(bm-cur_addr - bm-addr) = IDE_PAGE_SIZE)
-return s-io_buffer_size != 0;
-cpu_physical_memory_read(bm-cur_addr, (uint8_t *)prd, 8);
-bm-cur_addr += 8;
-prd.addr = le32_to_cpu(prd.addr);
-prd.size = le32_to_cpu(prd.size);
-len = prd.size 0xfffe;
-if (len == 0)
-len = 0x1;
-bm-cur_prd_len = len;
-bm-cur_prd_addr = prd.addr;
-bm-cur_prd_last = (prd.size 0x8000);
-}
-l = bm-cur_prd_len;
-if (l 0) {
-qemu_sglist_add(s-sg, bm-cur_prd_addr, l);
-bm-cur_prd_addr += l;
-bm-cur_prd_len -= l;
-s-io_buffer_size += l;
-}
-}
-return 1;
-}
-
static void dma_buf_commit(IDEState *s, int is_write)
{
qemu_sglist_destroy(s-sg);
}
-static void ide_dma_set_inactive(BMDMAState *bm)
+static void ide_set_inactive(IDEState *s)
{
-bm-status = ~BM_STATUS_DMAING;
-bm-dma_cb = NULL;
-bm-unit = -1;
-bm-aiocb = NULL;
+s-bus-dma.aiocb = NULL;
+s-bus-dma.ops-set_inactive(s-bus-dma.opaque);
}
void
[Qemu-devel] [PATCH 09/13] ahci: add ahci emulation
This patch adds an emulation layer for an ICH-7M AHCI controller. For now this controller does not do IDE legacy emulation. It is a pure AHCI controller. Signed-off-by: Alexander Graf ag...@suse.de --- v1 - v2: - rename IDEExtender to IDEBusOps and make a pointer (kraxel) - make dma hooks explicit by putting them into ops struct (stefanha) - use qdev buses (kraxel) - minor cleanups - dprintf overhaul - add reset function v2 - v3: - add msi support (kraxel) - use MIN macro (kraxel) - add msi support (kraxel) - fix ncq with multiple ports - zap qdev properties (kraxel) - redesign legacy IF_SATA hooks (kraxel) - don't build ahci as part of target - move to ide/ (kwolf) v3 - v4: - prepare for endianness safety - add lspci dump (herbszt) - use ich7 instead of ich7m (herbszt) - fix lst+fis mapping (kraxel) - coding style (blue swirl) - explicit mmio setters/getters (blue swirl) v4 - v5: - s/H2dNcqFis/NCQFrame/g (blue swirl) - redo -drive magic (blue swirl) - bump BAR to 4k - ahci.c: rename to ICH7_AHCI_RAID (herbszt) v5 - v6: - PCI config space fixes (isaku) - remove CONFIG_AHCI from default configs v6 - v7: - improve interrupt injection - combine tfdata code paths - update tfdata more often - reset port registers on port reset - improve debug output - add feature variable from fis for some extended commands - always set feature to DMA for atapi - osx 10.5.0 works as of this version - use non-raid ich7 ahci (herbszt) - reflect normal ich7 in pci dump - stick to new IDEBusOps (stefanha, kwolf) - ahci: stefan's ahci comments v7 - v8: - generate tfdata on the fly - reimplement immediate dma rw - add safety net for busy engine - adjust for new DMA interface --- Makefile.objs |1 + hw/ide/ahci.c | 1374 + 2 files changed, 1375 insertions(+), 0 deletions(-) create mode 100644 hw/ide/ahci.c diff --git a/Makefile.objs b/Makefile.objs index 04625eb..4f692e4 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -238,6 +238,7 @@ hw-obj-$(CONFIG_IDE_PIIX) += ide/piix.o hw-obj-$(CONFIG_IDE_CMD646) += ide/cmd646.o hw-obj-$(CONFIG_IDE_MACIO) += ide/macio.o hw-obj-$(CONFIG_IDE_VIA) += ide/via.o +hw-obj-$(CONFIG_AHCI) += ide/ahci.o # SCSI layer hw-obj-$(CONFIG_LSI_SCSI_PCI) += lsi53c895a.o diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c new file mode 100644 index 000..7e7aa89 --- /dev/null +++ b/hw/ide/ahci.c @@ -0,0 +1,1374 @@ +/* + * QEMU AHCI Emulation + * + * Copyright (c) 2010 qiaoch...@loongson.cn + * Copyright (c) 2010 Roland Elek elek.rol...@gmail.com + * Copyright (c) 2010 Sebastian Herbszt herb...@gmx.de + * Copyright (c) 2010 Alexander Graf ag...@suse.de + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see http://www.gnu.org/licenses/. + * + * + * lspci dump of a real device: + * + * 00:1f.2 SATA controller: Intel Corporation 82801GR/GH (ICH7 Family) SATA AHCI Controller (rev 01) (prog-if 01 [AHCI 1.0]) + *Subsystem: Intel Corporation 82801GR/GH (ICH7 Family) SATA AHCI Controller + *Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + *Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium TAbort- TAbort- MAbort- SERR- PERR- INTx- + *Latency: 0 + *Interrupt: pin B routed to IRQ 221 + *Region 0: I/O ports at e880 [size=8] + *Region 1: I/O ports at e800 [size=4] + *Region 2: I/O ports at e480 [size=8] + *Region 3: I/O ports at e400 [size=4] + *Region 4: I/O ports at e080 [size=16] + *Region 5: Memory at ffa3fc00 (32-bit, non-prefetchable) [size=1K] + *Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ + *Address: fee0100c Data: 41d9 + *Capabilities: [70] Power Management version 2 + *Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) + *Status: D0 PME-Enable- DSel=0 DScale=0 PME- + *Kernel driver in use: ahci + *Kernel modules: ahci + * + * 00:1f.2 0106: 8086:27c1 (rev 01) + * + */ + +#include hw/hw.h +#include hw/msi.h +#include hw/pc.h +#include hw/pci.h + +#include monitor.h +#include dma.h +#include cpu-common.h +#include blockdev.h +#include internal.h +#include hw/ide/pci.h + +/* #define
[Qemu-devel] [PATCH] fix qruncom compilation problems
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
I had this patch lying around but I don't think I ever got
qruncom to work completely.
Makefile.target |3 ++
tests/Makefile |7 ++--
tests/qruncom.c | 93 +++---
3 files changed, 67 insertions(+), 36 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index 5784844..4ac8f6f 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -339,6 +339,9 @@ obj-y += $(addprefix ../libdis/, $(libdis-y))
obj-y += $(libobj-y)
obj-y += $(addprefix $(HWDIR)/, $(hw-obj-y))
+else # !CONFIG_SOFTMMU
+libqemu.a: $(addprefix ../, $(common-obj-y)) $(libobj-y) $(addprefix
../libdis/, $(libdis-y))
+ ar rc $@ $^
endif # CONFIG_SOFTMMU
obj-y += $(addprefix ../, $(trace-obj-y))
diff --git a/tests/Makefile b/tests/Makefile
index e43ec70..6dbeb6f 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -116,9 +116,10 @@ speed: sha1 sha1-i386
# broken test
# NOTE: -fomit-frame-pointer is currently needed : this is a bug in libqemu
-qruncom: qruncom.c ../ioport-user.c ../i386-user/libqemu.a
- $(CC) $(CFLAGS) -fomit-frame-pointer $(LDFLAGS) -I../target-i386 -I..
-I../i386-user -I../fpu \
- -o $@ $(filter %.c, $^) -L../i386-user -lqemu -lm
+qruncom: qruncom.c
+ #$(MAKE) -C ../i386-linux-user libqemu.a
+ $(CC) $(CFLAGS) -fomit-frame-pointer $(LDFLAGS) -I../target-i386 -I..
-I../linux-user -I../i386-linux-user -I../fpu \
+ -o $@ $(filter %.c, $^) -L../i386-linux-user -lqemu -lm
# arm test
hello-arm: hello-arm.o
diff --git a/tests/qruncom.c b/tests/qruncom.c
index 079f7a2..66fc223 100644
--- a/tests/qruncom.c
+++ b/tests/qruncom.c
@@ -12,10 +12,68 @@
#include signal.h
#include malloc.h
+#define NEED_CPU_H 1
#include cpu.h
//#define SIGTEST
+unsigned long guest_base = 0;
+int have_guest_base = 0;
+int singlestep = 0;
+unsigned long last_brk = 0;
+
+void cpu_outb(uint32_t addr, uint8_t val)
+{
+fprintf(stderr, outb: port=0x%04PRIx32, data=%02PRIx8\n,
+addr, val);
+}
+
+void cpu_outw(uint32_t addr, uint16_t val)
+{
+fprintf(stderr, outw: port=0x%04PRIx32, data=%04PRIx16\n,
+addr, val);
+}
+
+void cpu_outl(uint32_t addr, uint32_t val)
+{
+fprintf(stderr, outl: port=0x%04PRIx32, data=%08PRIx32\n,
+addr, val);
+}
+
+uint8_t cpu_inb(uint32_t addr)
+{
+fprintf(stderr, inb: port=0x%04PRIx32\n, addr);
+return 0;
+}
+
+uint16_t cpu_inw(uint32_t addr)
+{
+fprintf(stderr, inw: port=0x%04PRIx32\n, addr);
+return 0;
+}
+
+uint32_t cpu_inl(uint32_t addr)
+{
+fprintf(stderr, inl: port=0x%04PRIx32\n, addr);
+return 0;
+}
+
+void cpu_list_lock(void)
+{
+}
+
+void cpu_list_unlock(void)
+{
+}
+
+void mmap_lock(void)
+{
+}
+
+void mmap_unlock(void)
+{
+}
+
int cpu_get_pic_interrupt(CPUState *env)
{
return -1;
@@ -44,26 +102,6 @@ static void set_idt(int n, unsigned int dpl)
set_gate(idt_table + n, 0, dpl, 0, 0);
}
-void qemu_free(void *ptr)
-{
-free(ptr);
-}
-
-void *qemu_malloc(size_t size)
-{
-return malloc(size);
-}
-
-void *qemu_mallocz(size_t size)
-{
-void *ptr;
-ptr = qemu_malloc(size);
-if (!ptr)
-return NULL;
-memset(ptr, 0, size);
-return ptr;
-}
-
void *qemu_vmalloc(size_t size)
{
return memalign(4096, size);
@@ -74,17 +112,6 @@ void qemu_vfree(void *ptr)
free(ptr);
}
-void qemu_printf(const char *fmt, ...)
-{
-va_list ap;
-va_start(ap, fmt);
-vprintf(fmt, ap);
-va_end(ap);
-}
-
-/* XXX: this is a bug in helper2.c */
-int errno;
-
/**/
#define COM_BASE_ADDR0x10100
@@ -99,7 +126,7 @@ static void usage(void)
static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg)
{
-return (uint8_t *)((seg 4) + (reg 0x));
+return (uint8_t *)(uintptr_t) ((seg 4) + (reg 0x));
}
static inline void pushw(CPUState *env, int val)
@@ -241,7 +268,7 @@ int main(int argc, char **argv)
case EXCP0D_GPF:
{
int int_num, ah;
-int_num = *(uint8_t *)(env-segs[R_CS].base + env-eip + 1);
+int_num = *(uint8_t *)(uintptr_t) (env-segs[R_CS].base +
env-eip + 1);
if (int_num != 0x21)
goto unknown_int;
ah = (env-regs[R_EAX] 8) 0xff;
--
1.7.3.2
Re: [Qemu-devel] [PATCH v8 7/7] virtio-console: Enable port throttling when chardev is slow to consume data
Sure. My proposal is for qemu_chr_write() to succeed all the time. If the backend can block, and the caller can handle it, it can get a -EAGAIN (or WSAEWOULDBLOCK) return. When the backend becomes writable, the chardev can call the -writes_unblocked() callback for that caller. Individual callers need not bother about re-submitting partial writes, since the buffering can be done in common code in one place (qemu-char.c). That's only OK if you assume it's OK to buffer all but one byte of the transmit request. Is that a fair assumption to make? No. See below. But that's entirely in guest memory, so it's limited to the amount of RAM that has been allocated to the guest. Exactly. The guest can cause ram_size * nr_ports of additional host memory to be allocated. Not acceptable. OK -- so this is how it adds up: - guest vq - virtio-serial-bus converts iov to buf This is an unbelievably lame piece of code. There's absolutely no reason to copy the data into a linear buffer. You should just be iterating over the elements of the sglist. - qemu-char stores the buf in case it wasn't able to send but then, since it's all async, we have: - virtio-serial-bus frees the buf - guest deletes the buf and removes it from the vq So what's left is only the data in qemu-char's buf. Now this can be (buf_size - 1) * nr_ports in the worst case. Add at least another buf_size because you have to allocate the qemu-char buffer before you free the virtio-serial buffer. We can expect that buf_size ~= guest ram size [1], so for practical purposes it may as well be unbounded. Worst case the guest could submit a buffer consisting of many large overlapping regions, giving a buf_size many times greater then guest ram size. Technically such code isn't even doing anything wrong. We're only reading from guest RAM, so in principle the same memory can be submitted multiple times without causing a race condition. The alternative would be to keep using the guest buffer till all's done, Yes. but then that depends on qemu getting async support - separating out the qemu_chr_write() into a separate thread and allowing vcpu and chr io operations to be run simultaneously. You don't need any special async char API or threads. Normal unix write semantics (i.e. short writes and EAGAIN) plus the unblock hook are sufficient. As mentioned above, the virtio-serial code should be iterating over the sglist. If the host won't accept all the data immediately then just remember how much has been sent, and resume iteration when the unblock hook is called. Paul [1] This kind of insanity does actually happen in the real world. e.g. loading a 700Mb ramdisk image via the fw_cfg device, or a kernel panic handler that dumps the contents of RAM to a debug channel (i.e. serial port).
[Qemu-devel] Re: [PATCH 01/13] ide: split ide command interpretation off
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote: The ATA command interpretation code can be used for PATA and SATA interfaces alike. So let's split it out into a separate function. Signed-off-by: Alexander Graf ag...@suse.de --- v6 - v7: - use bus instead of opaque (stefanha) --- hw/ide/core.c | 20 ++-- hw/ide/internal.h | 2 ++ 2 files changed, 16 insertions(+), 6 deletions(-) Reviewed-by: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
[Qemu-devel] Re: [PATCH 02/13] ide: fix whitespace gap in ide_exec_cmd
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote: Now that we have the function split out, we have to reindent it. In order to increase the readability of the actual functional change, this is split out. Signed-off-by: Alexander Graf ag...@suse.de --- hw/ide/core.c | 734 1 files changed, 367 insertions(+), 367 deletions(-) Reviewed-by: Stefan Hajnoczi stefa...@linux.vnet.ibm.com
Re: [Qemu-devel] [PATCH 06/21] vl: add a tmp pointer so that a handler can delete the entry to which it belongs.
On 12/08/2010 02:11 AM, Yoshiaki Tamura wrote:
2010/12/8 Isaku Yamahatayamah...@valinux.co.jp:
QLIST_FOREACH_SAFE?
Thanks! So, it should be,
QLIST_FOREACH_SAFE(e,vm_change_state_head, entries, ne) {
e-cb(e-opaque, running, reason);
}
I'll put it in the next spin.
This is still brittle though because it only allows the current handler
to delete itself. A better approach is to borrow the technique we use
with file descriptors (using a deleted flag) as that is robust against
deletion of any elements in a handler.
Regards,
Anthony Liguori
Yoshi
On Thu, Nov 25, 2010 at 03:06:45PM +0900, Yoshiaki Tamura wrote:
By copying the next entry to a tmp pointer,
qemu_del_vm_change_state_handler() can be called in the handler.
Signed-off-by: Yoshiaki Tamuratamura.yoshi...@lab.ntt.co.jp
---
vl.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/vl.c b/vl.c
index 805e11f..6b6aec0 100644
--- a/vl.c
+++ b/vl.c
@@ -1073,11 +1073,12 @@ void
qemu_del_vm_change_state_handler(VMChangeStateEntry *e)
void vm_state_notify(int running, int reason)
{
-VMChangeStateEntry *e;
+VMChangeStateEntry *e, *ne;
trace_vm_state_notify(running, reason);
-for (e = vm_change_state_head.lh_first; e; e = e-entries.le_next) {
+for (e = vm_change_state_head.lh_first; e; e = ne) {
+ne = e-entries.le_next;
e-cb(e-opaque, running, reason);
}
}
--
1.7.1.2
--
yamahata
--
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[Qemu-devel] Booting from VirtIO disk
Hi list I got confused after observing that there is no support for VirtIO block devices in Seabios supplied with Qemu-0.12.3. But still it can accept a VirtIO disk as a bootable device and perfectly boots from it. Then How it's done? But I can see the VirtIO block device code in Seabios source supplied with Qemu-0.13.0. Any pointer or explanation will help. Thanks Regards -- Anuj Aggarwal .''`. : :Ⓐ : # apt-get install hakuna-matata `. `'` `-
Re: [Qemu-devel] [PATCH v8 7/7] virtio-console: Enable port throttling when chardev is slow to consume data
On (Wed) Dec 08 2010 [12:56:33], Paul Brook wrote: Sure. My proposal is for qemu_chr_write() to succeed all the time. If the backend can block, and the caller can handle it, it can get a -EAGAIN (or WSAEWOULDBLOCK) return. When the backend becomes writable, the chardev can call the -writes_unblocked() callback for that caller. Individual callers need not bother about re-submitting partial writes, since the buffering can be done in common code in one place (qemu-char.c). That's only OK if you assume it's OK to buffer all but one byte of the transmit request. Is that a fair assumption to make? No. See below. But that's entirely in guest memory, so it's limited to the amount of RAM that has been allocated to the guest. Exactly. The guest can cause ram_size * nr_ports of additional host memory to be allocated. Not acceptable. OK -- so this is how it adds up: - guest vq - virtio-serial-bus converts iov to buf This is an unbelievably lame piece of code. I doubt it's 'unbelievably lame' just because of the copy. Care to expand? There's absolutely no reason to copy the data into a linear buffer. You should just be iterating over the elements of the sglist. OK, but that can be done in a separate patch series. - qemu-char stores the buf in case it wasn't able to send but then, since it's all async, we have: - virtio-serial-bus frees the buf - guest deletes the buf and removes it from the vq So what's left is only the data in qemu-char's buf. Now this can be (buf_size - 1) * nr_ports in the worst case. Add at least another buf_size because you have to allocate the qemu-char buffer before you free the virtio-serial buffer. We can expect that buf_size ~= guest ram size [1], so for practical purposes it may as well be unbounded. Now this only happens when the host chardev is slow or isn't being read from. So it's not really a guest causing a host DoS, but a guest causing itself some harm. You're right that the allocations happen one after the other, and the freeing happens later, so there is a time when 2 or 3 times the buf_size is needed. However, once qemu_chr_write() returns, there could be just one copy lying around, things are freed elsewhere. Worst case the guest could submit a buffer consisting of many large overlapping regions, giving a buf_size many times greater then guest ram size. Technically such code isn't even doing anything wrong. We're only reading from guest RAM, so in principle the same memory can be submitted multiple times without causing a race condition. Interesting. The alternative would be to keep using the guest buffer till all's done, Yes. but then that depends on qemu getting async support - separating out the qemu_chr_write() into a separate thread and allowing vcpu and chr io operations to be run simultaneously. You don't need any special async char API or threads. Normal unix write semantics (i.e. short writes and EAGAIN) plus the unblock hook are sufficient. As mentioned above, the virtio-serial code should be iterating over the sglist. If the host won't accept all the data immediately then just remember how much has been sent, and resume iteration when the unblock hook is called. Yes I've been thinking about this as well. But the problem is some kernel versions spin in the guest code till the buffer is placed back in the vq (signalling it's done using it). This is a problem for the virtio-console (hvc) that does writes with spinlocks held, so allocating new buffers, etc., isn't really -- possible easily. Amit
Re: [Qemu-devel] Re: [RFC][PATCH v5 01/21] Move code related to fd handlers into utility functions
On 12/08/2010 03:15 AM, Stefan Hajnoczi wrote: On Tue, Dec 07, 2010 at 04:02:03PM +0100, Jes Sorensen wrote: On 12/07/10 15:48, Michael Roth wrote: On 12/07/2010 07:31 AM, Jes Sorensen wrote: On 12/03/10 19:03, Michael Roth wrote: I am not happy with this addition of numbers to these functions, it doesn't tell us why we have a 3 and how it differs from 2. If 3 is really the backend for implementing 2, maybe it would be better to name it __qemu_set_fd_handler2() and then have macros/wrappers calling into it. That was the initial plan, but qemu_set_fd_handler2() is a back-end of sorts for qemu_set_fd_handler(), so I was just trying to be consistent with the naming. Personally I don't have any objections one way or the other. Anything to avoid qemu_set_fd_handler17() at some point. I think using __qemu_set_fd_handler() encourages people to modify that code rather than copy it. I agree that qemu_set_fd_handler3() could be named something more meaningful. Unfortunately we can't use __qemu_set_fd_handler() because the C language standard reserves identifiers that start with double underscore for the standard library. The Linux kernel gets away with it because the code is freestanding but that doesn't apply to QEMU. fdset_set_handler() or: iohandler_set_handler() Take whatever the structure is that represents the global state, convert it's name to lower case, and use that as the prefix. If this were C++, the namespacing would be obvious because you wouldn't have a choice about how to design the namespace ;-) /me ducks Regards, Anthony Liguori Stefan
[Qemu-devel] Re: [PATCH 03/13] ide: Split out BMDMA code from ATA core
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote:
@@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s)
ide_transfer_stop(s);
s-error = ABRT_ERR;
s-status = READY_STAT | ERR_STAT;
- ide_dma_set_inactive(s-bus-bmdma);
- s-bus-bmdma-status |= BM_STATUS_INT;
+ ide_set_inactive(s);
+ s-bus-dma.ops-set_status(s-bus-dma.opaque, BM_STATUS_INT);
Is BM_STATUS_INT constant naming appropriate for a general DMA
abstraction? Perhaps DMA_STATUS_INT.
@@ -2717,6 +2586,29 @@ static void ide_init1(IDEBus *bus, int unit)
ide_sector_write_timer_cb, s);
}
+static int ide_nop_start_irq(void *opaque)
+{
+ return 1;
+}
+
+static int ide_nop(void *opaque)
+{
+ return 0;
+}
+
+static const IDEDMAOps ide_dma_nop = {
+ .start_irq = ide_nop_start_irq,
+ .start_dma = (void*)ide_nop,
+ .start_transfer = (void*)ide_nop,
+ .prepare_buf = (void*)ide_nop,
+ .rw_buf = (void*)ide_nop,
+ .set_unit = (void*)ide_nop,
+ .set_status = (void*)ide_nop,
+ .set_inactive = (void*)ide_nop,
+ .restart_cb = (void*)ide_nop,
+ .reset = (void*)ide_nop,
Creative use of void* :). This looks unportable.
ppc and other architectures use function descriptors. There, a
function pointer is not sizeof(void*) so the (void*) cast is
questionable.
Also, casting to a function with a different signature is unportable.
You're relying on the calling convention to make this work.
Instead of fleshing out these functions, how about initializing
dma.ops to NULL? The program crashes should anyone try to do DMA
before setting a real IDEDMAOps pointer. That's not as robust as
limping along with non-working IDE, but should be straightforward to
debug if it ever happens. It also requires less code.
Stefan
Re: [Qemu-devel] Booting from VirtIO disk
2010/12/8 अनुज anu...@gmail.com: Hi list I got confused after observing that there is no support for VirtIO block devices in Seabios supplied with Qemu-0.12.3. But still it can accept a VirtIO disk as a bootable device and perfectly boots from it. Then How it's done? But I can see the VirtIO block device code in Seabios source supplied with Qemu-0.13.0. Before SeaBIOS had native support for virtio-blk there was the extboot option ROM which could boot from virtio-blk devices by reading a special I/O port (it does not speak virtio-blk, see qemu-kvm.git hw/extboot.c). Stefan
[Qemu-devel] Re: [PATCH 03/13] ide: Split out BMDMA code from ATA core
On 08.12.2010, at 15:26, Stefan Hajnoczi wrote:
On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote:
@@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s)
ide_transfer_stop(s);
s-error = ABRT_ERR;
s-status = READY_STAT | ERR_STAT;
-ide_dma_set_inactive(s-bus-bmdma);
-s-bus-bmdma-status |= BM_STATUS_INT;
+ide_set_inactive(s);
+s-bus-dma.ops-set_status(s-bus-dma.opaque, BM_STATUS_INT);
Is BM_STATUS_INT constant naming appropriate for a general DMA
abstraction? Perhaps DMA_STATUS_INT.
I was thinking of that too, but then again, why bother? Let's just declare
BMDMA status bits the standard and be good sounded the easiest :). Less
conversions are good, no? And so far, no other user really needs those bits.
@@ -2717,6 +2586,29 @@ static void ide_init1(IDEBus *bus, int unit)
ide_sector_write_timer_cb, s);
}
+static int ide_nop_start_irq(void *opaque)
+{
+return 1;
+}
+
+static int ide_nop(void *opaque)
+{
+return 0;
+}
+
+static const IDEDMAOps ide_dma_nop = {
+.start_irq = ide_nop_start_irq,
+.start_dma = (void*)ide_nop,
+.start_transfer = (void*)ide_nop,
+.prepare_buf= (void*)ide_nop,
+.rw_buf = (void*)ide_nop,
+.set_unit = (void*)ide_nop,
+.set_status = (void*)ide_nop,
+.set_inactive = (void*)ide_nop,
+.restart_cb = (void*)ide_nop,
+.reset = (void*)ide_nop,
Creative use of void* :). This looks unportable.
ppc and other architectures use function descriptors. There, a
function pointer is not sizeof(void*) so the (void*) cast is
questionable.
Also, casting to a function with a different signature is unportable.
You're relying on the calling convention to make this work.
Hrm, interesting. Maybe I should create one entry for each function type then.
Instead of fleshing out these functions, how about initializing
dma.ops to NULL? The program crashes should anyone try to do DMA
before setting a real IDEDMAOps pointer. That's not as robust as
limping along with non-working IDE, but should be straightforward to
debug if it ever happens. It also requires less code.
Unfortunately, at least reset gets called before the DMA init :(.
Alex
[Qemu-devel] Re: [PATCH 03/13] ide: Split out BMDMA code from ATA core
Am 08.12.2010 15:26, schrieb Stefan Hajnoczi: On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote: @@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s) ide_transfer_stop(s); s-error = ABRT_ERR; s-status = READY_STAT | ERR_STAT; -ide_dma_set_inactive(s-bus-bmdma); -s-bus-bmdma-status |= BM_STATUS_INT; +ide_set_inactive(s); +s-bus-dma.ops-set_status(s-bus-dma.opaque, BM_STATUS_INT); Is BM_STATUS_INT constant naming appropriate for a general DMA abstraction? Perhaps DMA_STATUS_INT. BM_STATUS_INT is a bit in the status register of busmaster IDE. So in theory it shouldn't appear in generic ATA code, but I'm not sure how much of this we can fix at this point. Instead of fleshing out these functions, how about initializing dma.ops to NULL? The program crashes should anyone try to do DMA before setting a real IDEDMAOps pointer. That's not as robust as limping along with non-working IDE, but should be straightforward to debug if it ever happens. It also requires less code. Allowing the guest to crash qemu is not an option. We'd have to check for NULL in all commands that initiate a DMA transfer. Kevin
[Qemu-devel] Re: [PATCH 03/13] ide: Split out BMDMA code from ATA core
On Wed, Dec 8, 2010 at 2:35 PM, Kevin Wolf kw...@redhat.com wrote: Am 08.12.2010 15:26, schrieb Stefan Hajnoczi: On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote: @@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s) ide_transfer_stop(s); s-error = ABRT_ERR; s-status = READY_STAT | ERR_STAT; - ide_dma_set_inactive(s-bus-bmdma); - s-bus-bmdma-status |= BM_STATUS_INT; + ide_set_inactive(s); + s-bus-dma.ops-set_status(s-bus-dma.opaque, BM_STATUS_INT); Is BM_STATUS_INT constant naming appropriate for a general DMA abstraction? Perhaps DMA_STATUS_INT. BM_STATUS_INT is a bit in the status register of busmaster IDE. So in theory it shouldn't appear in generic ATA code, but I'm not sure how much of this we can fix at this point. Instead of fleshing out these functions, how about initializing dma.ops to NULL? The program crashes should anyone try to do DMA before setting a real IDEDMAOps pointer. That's not as robust as limping along with non-working IDE, but should be straightforward to debug if it ever happens. It also requires less code. Allowing the guest to crash qemu is not an option. We'd have to check for NULL in all commands that initiate a DMA transfer. You're right, I wasn't aware that the ops gets a chance to execute before we initialize them to BMDMA. Stefan
[Qemu-devel] Re: [PATCH 03/13] ide: Split out BMDMA code from ATA core
Am 08.12.2010 15:40, schrieb Stefan Hajnoczi: On Wed, Dec 8, 2010 at 2:35 PM, Kevin Wolf kw...@redhat.com wrote: Am 08.12.2010 15:26, schrieb Stefan Hajnoczi: On Wed, Dec 8, 2010 at 12:13 PM, Alexander Graf ag...@suse.de wrote: @@ -486,8 +440,8 @@ void ide_dma_error(IDEState *s) ide_transfer_stop(s); s-error = ABRT_ERR; s-status = READY_STAT | ERR_STAT; -ide_dma_set_inactive(s-bus-bmdma); -s-bus-bmdma-status |= BM_STATUS_INT; +ide_set_inactive(s); +s-bus-dma.ops-set_status(s-bus-dma.opaque, BM_STATUS_INT); Is BM_STATUS_INT constant naming appropriate for a general DMA abstraction? Perhaps DMA_STATUS_INT. BM_STATUS_INT is a bit in the status register of busmaster IDE. So in theory it shouldn't appear in generic ATA code, but I'm not sure how much of this we can fix at this point. Instead of fleshing out these functions, how about initializing dma.ops to NULL? The program crashes should anyone try to do DMA before setting a real IDEDMAOps pointer. That's not as robust as limping along with non-working IDE, but should be straightforward to debug if it ever happens. It also requires less code. Allowing the guest to crash qemu is not an option. We'd have to check for NULL in all commands that initiate a DMA transfer. You're right, I wasn't aware that the ops gets a chance to execute before we initialize them to BMDMA. For example with ISA we never intialize it at all. Kevin
[Qemu-devel] Re: [PATCH 02/13] ide: fix whitespace gap in ide_exec_cmd
Am 08.12.2010 13:13, schrieb Alexander Graf: Now that we have the function split out, we have to reindent it. In order to increase the readability of the actual functional change, this is split out. Signed-off-by: Alexander Graf ag...@suse.de This patch adds some trailing whitespace. Can you take the chance to remove it? Kevin
Re: [Qemu-devel] Booting from VirtIO disk
2010/12/8 अनुज anu...@gmail.com: Hi thanks for your quick response. Please see the comments inline. 2010/12/8 Stefan Hajnoczi stefa...@gmail.com: 2010/12/8 अनुज anu...@gmail.com: Hi list I got confused after observing that there is no support for VirtIO block devices in Seabios supplied with Qemu-0.12.3. But still it can accept a VirtIO disk as a bootable device and perfectly boots from it. Then How it's done? But I can see the VirtIO block device code in Seabios source supplied with Qemu-0.13.0. Before SeaBIOS had native support for virtio-blk there was the extboot option ROM which could boot from virtio-blk devices by reading a special I/O port (it does not speak virtio-blk, see qemu-kvm.git hw/extboot.c). I couldn't find this file in qemu versions 0.12.3 and 0.13.0. And my same doubt is also for SCSI disks. Please keep qemu-devel@nongnu.org CCed so others can follow the conversation and help too. You probably looked at QEMU source code (from qemu.git). The extboot code is in qemu-kvm.git (which is shipped as the kvm or qemu-kvm package on distros). Are you sure you tested virtio-blk boot in qemu.git-based code? Stefan
Re: [Qemu-devel] User mode restart execution
Hi... On Tue, Dec 7, 2010 at 18:43, John Vele jve...@gmail.com wrote: Grettings, I am using user mode qemu for running stand-alone i386 binaries in linux. What I want to do is this: I want to run a binary until it ends, but I don't want qemu-i386 to exit (that is what it does normally) but restart the execution of the same binary from the beginning without exiting. Not sure why you wanna do such thing, but an idea crossed my mind: quite likely, a program exit with exit() C function. This is related to close() syscall AFAIK. Thus, how about modifying close() syscall handler in qemu user mode and make it jump again to load ELF from scratch? -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com
Re: [Qemu-devel] Booting from VirtIO disk
2010/12/8 Stefan Hajnoczi stefa...@gmail.com: 2010/12/8 अनुज anu...@gmail.com: Hi thanks for your quick response. Please see the comments inline. 2010/12/8 Stefan Hajnoczi stefa...@gmail.com: 2010/12/8 अनुज anu...@gmail.com: Hi list I got confused after observing that there is no support for VirtIO block devices in Seabios supplied with Qemu-0.12.3. But still it can accept a VirtIO disk as a bootable device and perfectly boots from it. Then How it's done? But I can see the VirtIO block device code in Seabios source supplied with Qemu-0.13.0. Before SeaBIOS had native support for virtio-blk there was the extboot option ROM which could boot from virtio-blk devices by reading a special I/O port (it does not speak virtio-blk, see qemu-kvm.git hw/extboot.c). I couldn't find this file in qemu versions 0.12.3 and 0.13.0. And my same doubt is also for SCSI disks. Please keep qemu-devel@nongnu.org CCed so others can follow the conversation and help too. You probably looked at QEMU source code (from qemu.git). The extboot code is in qemu-kvm.git (which is shipped as the kvm or qemu-kvm package on distros). Yes I was looking in qemu.git-based code by mistake. I found files in qemu-kvm.git-based code. Are you sure you tested virtio-blk boot in qemu.git-based code? No I have tested that boot only using qemu-kvm.git-based code. Stefan Thanks for your help. Regards -- Anuj Aggarwal .''`. : :Ⓐ : # apt-get install hakuna-matata `. `'` `-
