[Qemu-devel] Inject Interrupt, Using VMCS during qemu live migration.

[李 ヨンジュン]

Hello, I am trying to inject interrupt, in final phase of Live migration.

I use vmcs_write32 function to inject interrupt. This function is called
by qemu, with ioctl.

This is Code.

(KVM)

void vmcs_write32_provider(unsigned long field, u32 value)
{
vmcs_write32(field, value);
}


long kvm_arch_vcpu_ioctl(struct file *filp,
unsigned int ioctl, unsigned long arg)
{
//
case KVM_TEST_IOCTL: {
r=0;
//printk("Test IOCTL!!!\n");
int type = 0;
int trap=58;
u32 intr_fields= (0x8000 | (type<<8) | trap);
vmcs_write32_provider(0x4016,intr_fields);
printk("vmcs_write Success!!!\n");

goto out;
}


This code works perfectly when called by hypercall.(When call this
function in kvm_emulate_hypercall function by guest VM.)

But, when I trying to call this function by qemu(ioctl), This error
message is occurred.

KVM: entry failed, hardware error 0x8021

If you're running a guest on an Intel machine without unrestricted mode 
support, the failure can be most likely due to the guest entering an invalid 
state for Intel VT. For example, the guest maybe running in big real mode which 
is not supported on less recent Intel processors.


Register's Information's~~
RAX=1


 I need help. Thank you.

[Qemu-devel] Inject Interrupt, Using VMCS during qemu live migration.

[李 ヨンジュン]

Hello, I am trying to inject interrupt, in final phase of Live migration.

I use vmcs_write32 function to inject interrupt. This function is called
by qemu, with ioctl.

This is Code.

(KVM)

void vmcs_write32_provider(unsigned long field, u32 value)
{
vmcs_write32(field, value);
}


long kvm_arch_vcpu_ioctl(struct file *filp,
unsigned int ioctl, unsigned long arg)
{
//
case KVM_TEST_IOCTL: {
r=0;
//printk("Test IOCTL!!!\n");
int type = 0;
int trap=58;
u32 intr_fields= (0x8000 | (type<<8) | trap);
vmcs_write32_provider(0x4016,intr_fields);
printk("vmcs_write Success!!!\n");

goto out;
}


This code works perfectly when called by hypercall.(When call this
function in kvm_emulate_hypercall function by guest VM.)

But, when I trying to call this function by qemu(ioctl), This error
message is occurred.

http://pds23.egloos.com/pds/201209/09/86/f0062286_504c07a4bc3c7.png

I need help. Thank you.

[Qemu-devel] [PATCH 8/9] target-xtensa: implement FP1 group

[Max Filippov]

These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov 
---
 target-xtensa/helper.h|8 
 target-xtensa/op_helper.c |   47 ++
 target-xtensa/translate.c |   81 -
 3 files changed, 135 insertions(+), 1 deletions(-)

diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
index 9557347..4cc0088 100644
--- a/target-xtensa/helper.h
+++ b/target-xtensa/helper.h
@@ -49,4 +49,12 @@ DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, 
i32, f32, i32, i32)
 DEF_HELPER_3(itof, f32, env, i32, i32)
 DEF_HELPER_3(uitof, f32, env, i32, i32)
 
+DEF_HELPER_4(un_s, void, env, i32, f32, f32)
+DEF_HELPER_4(oeq_s, void, env, i32, f32, f32)
+DEF_HELPER_4(ueq_s, void, env, i32, f32, f32)
+DEF_HELPER_4(olt_s, void, env, i32, f32, f32)
+DEF_HELPER_4(ult_s, void, env, i32, f32, f32)
+DEF_HELPER_4(ole_s, void, env, i32, f32, f32)
+DEF_HELPER_4(ule_s, void, env, i32, f32, f32)
+
 #include "def-helper.h"
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index d85f9d0..cbaf3c7 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -864,3 +864,50 @@ float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, 
uint32_t scale)
 uint32_to_float32(scale, &env->fp_status),
 &env->fp_status);
 }
+
+static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
+{
+if (v) {
+env->sregs[BR] |= br;
+} else {
+env->sregs[BR] &= ~br;
+}
+}
+
+void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
+}
+
+void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
+}
+
+void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+int v = float32_compare_quiet(a, b, &env->fp_status);
+set_br(env, v == float_relation_equal || v == float_relation_unordered, 
br);
+}
+
+void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
+}
+
+void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+int v = float32_compare_quiet(a, b, &env->fp_status);
+set_br(env, v == float_relation_less || v == float_relation_unordered, br);
+}
+
+void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
+}
+
+void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
+{
+int v = float32_compare_quiet(a, b, &env->fp_status);
+set_br(env, v != float_relation_greater, br);
+}
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index a6ab18a..d361f7f 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2001,7 +2001,86 @@ static void disas_xtensa_insn(DisasContext *dc)
 
 case 11: /*FP1*/
 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
-TBD();
+
+#define gen_compare(rel, br, a, b) \
+do { \
+TCGv_i32 bit = tcg_const_i32(1 << br); \
+\
+gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
+tcg_temp_free(bit); \
+} while (0)
+
+switch (OP2) {
+case 1: /*UN.Sf*/
+gen_compare(un_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 2: /*OEQ.Sf*/
+gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 3: /*UEQ.Sf*/
+gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 4: /*OLT.Sf*/
+gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 5: /*ULT.Sf*/
+gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 6: /*OLE.Sf*/
+gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
+break;
+
+case 7: /*ULE.Sf*/
+gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
+break;
+
+#undef gen_compare
+
+case 8: /*MOVEQZ.Sf*/
+case 9: /*MOVNEZ.Sf*/
+case 10: /*MOVLTZ.Sf*/
+case 11: /*MOVGEZ.Sf*/
+gen_window_check1(dc, RRR_T);
+{
+static const TCGCond cond[] = {
+TCG_COND_NE,
+TCG_COND_EQ,
+TCG_COND_GE,
+TCG_COND_LT
+};
+int label = gen_new_label();
+tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
+tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
+gen_set_label(label);
+}
+break;
+
+case 12: /*MOVF.Sf*/
+case

[Qemu-devel] [PATCH 9/9] target-xtensa: implement coprocessor context option

[Max Filippov]

In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.

See ISA, 4.4.5 for more details.

FP is coprocessor 0.

Signed-off-by: Max Filippov 
---
 target-xtensa/cpu.h   |5 +
 target-xtensa/translate.c |   37 +
 2 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index b456283..7348277 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -468,6 +468,8 @@ static inline int cpu_mmu_index(CPUXtensaState *env)
 #define XTENSA_TBFLAG_LITBASE 0x8
 #define XTENSA_TBFLAG_DEBUG 0x10
 #define XTENSA_TBFLAG_ICOUNT 0x20
+#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
+#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 
 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 target_ulong *cs_base, int *flags)
@@ -491,6 +493,9 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState 
*env, target_ulong *pc,
 *flags |= XTENSA_TBFLAG_ICOUNT;
 }
 }
+if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+}
 }
 
 #include "cpu-all.h"
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index d361f7f..5172194 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -65,6 +65,8 @@ typedef struct DisasContext {
 bool debug;
 bool icount;
 TCGv_i32 next_icount;
+
+unsigned cpenable;
 } DisasContext;
 
 static TCGv_ptr cpu_env;
@@ -331,6 +333,15 @@ static void gen_check_privilege(DisasContext *dc)
 }
 }
 
+static void gen_check_cpenable(DisasContext *dc, unsigned cp)
+{
+if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
+!(dc->cpenable & (1 << cp))) {
+gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
+dc->is_jmp = DISAS_UPDATE;
+}
+}
+
 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
 {
 tcg_gen_mov_i32(cpu_pc, dest);
@@ -579,6 +590,12 @@ static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, 
TCGv_i32 v)
 }
 }
 
+static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
+gen_jumpi_check_loop_end(dc, 0);
+}
+
 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 {
 tcg_gen_andi_i32(cpu_SR[sr], v,
@@ -681,6 +698,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 
s)
 [DBREAKA + 1] = gen_wsr_dbreaka,
 [DBREAKC] = gen_wsr_dbreakc,
 [DBREAKC + 1] = gen_wsr_dbreakc,
+[CPENABLE] = gen_wsr_cpenable,
 [INTSET] = gen_wsr_intset,
 [INTCLEAR] = gen_wsr_intclear,
 [INTENABLE] = gen_wsr_intenable,
@@ -1832,6 +1850,7 @@ static void disas_xtensa_insn(DisasContext *dc)
 case 5: /*SSXUf*/
 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
 gen_window_check2(dc, RRR_S, RRR_T);
+gen_check_cpenable(dc, 0);
 {
 TCGv_i32 addr = tcg_temp_new_i32();
 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
@@ -1891,26 +1910,31 @@ static void disas_xtensa_insn(DisasContext *dc)
 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
 switch (OP2) {
 case 0: /*ADD.S*/
+gen_check_cpenable(dc, 0);
 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
 cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
 
 case 1: /*SUB.S*/
+gen_check_cpenable(dc, 0);
 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
 cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
 
 case 2: /*MUL.S*/
+gen_check_cpenable(dc, 0);
 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
 cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
 
 case 4: /*MADD.S*/
+gen_check_cpenable(dc, 0);
 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
 
 case 5: /*MSUB.S*/
+gen_check_cpenable(dc, 0);
 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
@@ -1921,6 +1945,7 @@ static void disas_xtensa_insn(DisasContext *dc)
 case 11: /*CEIL.Sf*/
 case 14: /*UTRUNC.Sf*/
 gen_window_check1(dc, RRR_R);
+gen_check_cpenable(dc, 0);
 {
 static const unsigned rounding_mode_const[] = {
 float_round_nearest_even,
@@ -1949,6 +1974,7 @@ static void disas_xtensa_insn(DisasContext *dc)
 case 12: /*FLOAT.Sf*/
 cas

[Qemu-devel] [PATCH 7/9] target-xtensa: implement FP0 conversions

[Max Filippov]

These are FP to integer and integer to FP conversion opcodes.
See ISA, 4.3.10 for more details.

Note that utrunc.s implementation follows ISS behaviour, not ISA.

Signed-off-by: Max Filippov 
---
 target-xtensa/helper.h|4 +++
 target-xtensa/op_helper.c |   43 
 target-xtensa/translate.c |   48 +
 3 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
index 4e6e417..9557347 100644
--- a/target-xtensa/helper.h
+++ b/target-xtensa/helper.h
@@ -44,5 +44,9 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32)
 DEF_HELPER_3(mul_s, f32, env, f32, f32)
 DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
 DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
+DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32)
+DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32)
+DEF_HELPER_3(itof, f32, env, i32, i32)
+DEF_HELPER_3(uitof, f32, env, i32, i32)
 
 #include "def-helper.h"
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index ba935a8..d85f9d0 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -821,3 +821,46 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, 
float32 b, float32 c)
 return float32_muladd(b, c, a, float_muladd_negate_product,
 &env->fp_status);
 }
+
+uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
+{
+float_status fp_status = {0};
+
+set_float_rounding_mode(rounding_mode, &fp_status);
+return float32_to_int32(
+float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status),
+&fp_status);
+}
+
+uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
+{
+float_status fp_status = {0};
+float32 zero = {0};
+float32 res;
+
+set_float_rounding_mode(rounding_mode, &fp_status);
+
+res = float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status);
+
+if (float32_compare_quiet(v, zero, &fp_status) == float_relation_less) {
+return float32_to_int32(res, &fp_status);
+} else {
+return float32_to_uint32(res, &fp_status);
+}
+}
+
+float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
+{
+return float32_div(
+int32_to_float32(v, &env->fp_status),
+uint32_to_float32(scale, &env->fp_status),
+&env->fp_status);
+}
+
+float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
+{
+return float32_div(
+uint32_to_float32(v, &env->fp_status),
+uint32_to_float32(scale, &env->fp_status),
+&env->fp_status);
+}
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index ec22f60..a6ab18a 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1915,6 +1915,54 @@ static void disas_xtensa_insn(DisasContext *dc)
 cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
 break;
 
+case 8: /*ROUND.Sf*/
+case 9: /*TRUNC.Sf*/
+case 10: /*FLOOR.Sf*/
+case 11: /*CEIL.Sf*/
+case 14: /*UTRUNC.Sf*/
+gen_window_check1(dc, RRR_R);
+{
+static const unsigned rounding_mode_const[] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_down,
+float_round_up,
+[6] = float_round_to_zero,
+};
+TCGv_i32 rounding_mode = tcg_const_i32(
+rounding_mode_const[OP2 & 7]);
+TCGv_i32 scale = tcg_const_i32(1 << RRR_T);
+
+if (OP2 == 14) {
+gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
+rounding_mode, scale);
+} else {
+gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
+rounding_mode, scale);
+}
+
+tcg_temp_free(rounding_mode);
+tcg_temp_free(scale);
+}
+break;
+
+case 12: /*FLOAT.Sf*/
+case 13: /*UFLOAT.Sf*/
+gen_window_check1(dc, RRR_S);
+{
+TCGv_i32 scale = tcg_const_i32(1 << RRR_T);
+
+if (OP2 == 13) {
+gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
+cpu_R[RRR_S], scale);
+} else {
+gen_helper_itof(cpu_FR[RRR_R], cpu_env,
+cpu_R[RRR_S], scale);
+}
+tcg_temp_free(scale);
+}
+break;
+
 case 15: /*FP1OP*/
 switch (RRR_T) {
  

[Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic

[Max Filippov]

These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov 
---
 target-xtensa/helper.h|7 +
 target-xtensa/op_helper.c |   37 +++
 target-xtensa/translate.c |   61 -
 3 files changed, 104 insertions(+), 1 deletions(-)

diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
index 1662552..4e6e417 100644
--- a/target-xtensa/helper.h
+++ b/target-xtensa/helper.h
@@ -37,5 +37,12 @@ DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32)
 DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32)
 
 DEF_HELPER_2(wur_fcr, void, env, i32)
+DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
+DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
+DEF_HELPER_3(add_s, f32, env, f32, f32)
+DEF_HELPER_3(sub_s, f32, env, f32, f32)
+DEF_HELPER_3(mul_s, f32, env, f32, f32)
+DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
+DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
 
 #include "def-helper.h"
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 3bf7339..ba935a8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -784,3 +784,40 @@ void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
 env->uregs[FCR] = v & 0xf07f;
 set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
 }
+
+float32 HELPER(abs_s)(float32 v)
+{
+return float32_abs(v);
+}
+
+float32 HELPER(neg_s)(float32 v)
+{
+return float32_chs(v);
+}
+
+float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
+{
+return float32_add(a, b, &env->fp_status);
+}
+
+float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
+{
+return float32_sub(a, b, &env->fp_status);
+}
+
+float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
+{
+return float32_mul(a, b, &env->fp_status);
+}
+
+float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
+{
+return float32_muladd(b, c, a, 0,
+&env->fp_status);
+}
+
+float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
+{
+return float32_muladd(b, c, a, float_muladd_negate_product,
+&env->fp_status);
+}
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index d167e9d..ec22f60 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1889,7 +1889,66 @@ static void disas_xtensa_insn(DisasContext *dc)
 
 case 10: /*FP0*/
 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
-TBD();
+switch (OP2) {
+case 0: /*ADD.S*/
+gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
+cpu_FR[RRR_S], cpu_FR[RRR_T]);
+break;
+
+case 1: /*SUB.S*/
+gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
+cpu_FR[RRR_S], cpu_FR[RRR_T]);
+break;
+
+case 2: /*MUL.S*/
+gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
+cpu_FR[RRR_S], cpu_FR[RRR_T]);
+break;
+
+case 4: /*MADD.S*/
+gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
+cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
+break;
+
+case 5: /*MSUB.S*/
+gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
+cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
+break;
+
+case 15: /*FP1OP*/
+switch (RRR_T) {
+case 0: /*MOV.Sf*/
+tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
+break;
+
+case 1: /*ABS.Sf*/
+gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
+break;
+
+case 4: /*RFRf*/
+gen_window_check1(dc, RRR_R);
+tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
+break;
+
+case 5: /*WFRf*/
+gen_window_check1(dc, RRR_S);
+tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
+break;
+
+case 6: /*NEG.Sf*/
+gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
+break;
+
+default: /*reserved*/
+RESERVED();
+break;
+}
+break;
+
+default: /*reserved*/
+RESERVED();
+break;
+}
 break;
 
 case 11: /*FP1*/
-- 
1.7.7.6

[Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups

[Max Filippov]

These are load/store instructions for FP registers with immediate or
register index and optional base post-update.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov 
---
 target-xtensa/translate.c |   58 +---
 1 files changed, 54 insertions(+), 4 deletions(-)

diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 97c388a..d167e9d 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1825,8 +1825,33 @@ static void disas_xtensa_insn(DisasContext *dc)
 break;
 
 case 8: /*LSCXp*/
-HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
-TBD();
+switch (OP2) {
+case 0: /*LSXf*/
+case 1: /*LSXUf*/
+case 4: /*SSXf*/
+case 5: /*SSXUf*/
+HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+gen_window_check2(dc, RRR_S, RRR_T);
+{
+TCGv_i32 addr = tcg_temp_new_i32();
+tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
+gen_load_store_alignment(dc, 2, addr, false);
+if (OP2 & 0x4) {
+tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
+} else {
+tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
+}
+if (OP2 & 0x1) {
+tcg_gen_mov_i32(cpu_R[RRR_S], addr);
+}
+tcg_temp_free(addr);
+}
+break;
+
+default: /*reserved*/
+RESERVED();
+break;
+}
 break;
 
 case 9: /*LSC4*/
@@ -2100,8 +2125,33 @@ static void disas_xtensa_insn(DisasContext *dc)
 break;
 
 case 3: /*LSCIp*/
-HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
-TBD();
+switch (RRI8_R) {
+case 0: /*LSIf*/
+case 4: /*SSIf*/
+case 8: /*LSIUf*/
+case 12: /*SSIUf*/
+HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
+gen_window_check1(dc, RRI8_S);
+{
+TCGv_i32 addr = tcg_temp_new_i32();
+tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
+gen_load_store_alignment(dc, 2, addr, false);
+if (RRI8_R & 0x4) {
+tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
+} else {
+tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
+}
+if (RRI8_R & 0x8) {
+tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
+}
+tcg_temp_free(addr);
+}
+break;
+
+default: /*reserved*/
+RESERVED();
+break;
+}
 break;
 
 case 4: /*MAC16d*/
-- 
1.7.7.6

[Qemu-devel] [PATCH 4/9] target-xtensa: add FP registers

[Max Filippov]

There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).

See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov 
---
 gdbstub.c |8 +++
 target-xtensa/cpu.h   |3 ++
 target-xtensa/helper.h|2 +
 target-xtensa/op_helper.c |   13 +++
 target-xtensa/translate.c |   52 ++--
 5 files changed, 71 insertions(+), 7 deletions(-)

diff --git a/gdbstub.c b/gdbstub.c
index 5d37dd9..7aba79e 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1660,6 +1660,10 @@ static int cpu_gdb_read_register(CPUXtensaState *env, 
uint8_t *mem_buf, int n)
 GET_REG32(env->uregs[reg->targno & 0xff]);
 break;
 
+case 4: /*f*/
+GET_REG32(env->fregs[reg->targno & 0x0f]);
+break;
+
 case 8: /*a*/
 GET_REG32(env->regs[reg->targno & 0x0f]);
 break;
@@ -1700,6 +1704,10 @@ static int cpu_gdb_write_register(CPUXtensaState *env, 
uint8_t *mem_buf, int n)
 env->uregs[reg->targno & 0xff] = tmp;
 break;
 
+case 4: /*f*/
+env->fregs[reg->targno & 0x0f] = tmp;
+break;
+
 case 8: /*a*/
 env->regs[reg->targno & 0x0f] = tmp;
 break;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 177094a..b456283 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -36,6 +36,7 @@
 #include "config.h"
 #include "qemu-common.h"
 #include "cpu-defs.h"
+#include "fpu/softfloat.h"
 
 #define TARGET_HAS_ICE 1
 
@@ -325,6 +326,8 @@ typedef struct CPUXtensaState {
 uint32_t sregs[256];
 uint32_t uregs[256];
 uint32_t phys_regs[MAX_NAREG];
+float32 fregs[16];
+float_status fp_status;
 
 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h
index 152fec0..1662552 100644
--- a/target-xtensa/helper.h
+++ b/target-xtensa/helper.h
@@ -36,4 +36,6 @@ DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32)
 DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32)
 DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32)
 
+DEF_HELPER_2(wur_fcr, void, env, i32)
+
 #include "def-helper.h"
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 2659c0e..3bf7339 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -771,3 +771,16 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, 
uint32_t v)
 }
 env->sregs[DBREAKC + i] = v;
 }
+
+void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
+{
+static const int rounding_mode[] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down,
+};
+
+env->uregs[FCR] = v & 0xf07f;
+set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
+}
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 1900bd5..97c388a 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -70,6 +70,7 @@ typedef struct DisasContext {
 static TCGv_ptr cpu_env;
 static TCGv_i32 cpu_pc;
 static TCGv_i32 cpu_R[16];
+static TCGv_i32 cpu_FR[16];
 static TCGv_i32 cpu_SR[256];
 static TCGv_i32 cpu_UR[256];
 
@@ -155,6 +156,12 @@ void xtensa_translate_init(void)
 "ar8", "ar9", "ar10", "ar11",
 "ar12", "ar13", "ar14", "ar15",
 };
+static const char * const fregnames[] = {
+"f0", "f1", "f2", "f3",
+"f4", "f5", "f6", "f7",
+"f8", "f9", "f10", "f11",
+"f12", "f13", "f14", "f15",
+};
 int i;
 
 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
@@ -167,6 +174,12 @@ void xtensa_translate_init(void)
 regnames[i]);
 }
 
+for (i = 0; i < 16; i++) {
+cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
+offsetof(CPUXtensaState, fregs[i]),
+fregnames[i]);
+}
+
 for (i = 0; i < 256; ++i) {
 if (sregnames[i]) {
 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
@@ -692,6 +705,23 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, 
TCGv_i32 s)
 }
 }
 
+static void gen_wur(uint32_t ur, TCGv_i32 s)
+{
+switch (ur) {
+case FCR:
+gen_helper_wur_fcr(cpu_env, s);
+break;
+
+case FSR:
+tcg_gen_andi_i32(cpu_UR[ur], s, 0xff80);
+break;
+
+default:
+tcg_gen_mov_i32(cpu_UR[ur], s);
+break;
+}
+}
+
 static void gen_load_store_alignment(DisasContext *dc, int shift,
 TCGv_i32 addr, bool no_hw_alignment)
 {
@@ -1761,13 +1791,11 @@ static void disas_xtensa_insn(DisasContext *dc)
 
 case 15: /*WUR*/
 gen_window_check1(dc, RRR_T);
-{
-if (uregnames[RSR_SR]) {
-tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
-} else {
-qemu_log("WUR %d not implemented, ", RSR_SR);
-TBD();
-}
+if (uregn

[Qemu-devel] [PATCH 3/9] target-xtensa: specialize softfloat NaN rules

[Max Filippov]

NaN propagation rule: leftmost NaN in the expression gets propagated to
the result.

Signed-off-by: Max Filippov 
---
 fpu/softfloat-specialize.h |9 +++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 4902450..9d78f41 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -57,7 +57,8 @@ const float16 float16_default_nan = const_float16(0xFE00);
 **/
 #if defined(TARGET_SPARC)
 const float32 float32_default_nan = const_float32(0x7FFF);
-#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
+  defined(TARGET_XTENSA)
 const float32 float32_default_nan = const_float32(0x7FC0);
 #elif SNAN_BIT_IS_ONE
 const float32 float32_default_nan = const_float32(0x7FBF);
@@ -262,9 +263,13 @@ float32 float32_maybe_silence_nan( float32 a_ )
 #error Rules for silencing a signaling NaN are target-specific
 #  endif
 #else
+#  if defined(TARGET_XTENSA)
+return a_;
+#  else
 uint32_t a = float32_val(a_);
 a |= (1 << 22);
 return make_float32(a);
+#  endif
 #endif
 }
 return a_;
@@ -372,7 +377,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag 
bIsQNaN, flag bIsSNaN,
 return 1;
 }
 }
-#elif defined(TARGET_PPC)
+#elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
 {
-- 
1.7.7.6

[Qemu-devel] [PATCH 2/9] target-xtensa: handle boolean option in overlays

[Max Filippov]

Signed-off-by: Max Filippov 
---
 target-xtensa/overlay_tool.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index a3a5650..e395053 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -58,6 +58,7 @@
 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
+XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
-- 
1.7.7.6

[Qemu-devel] [PATCH 1/9] softfloat: make float_muladd_negate_* flags independent

[Max Filippov]

Flags passed into float{32,64}_muladd are treated as bits; assign
independent bits to float_muladd_negate_* to allow precise control over
what gets negated in float{32,64}_muladd.

Signed-off-by: Max Filippov 
---
 fpu/softfloat.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index feec3a1..2860ca0 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -219,7 +219,7 @@ void float_raise( int8 flags STATUS_PARAM);
 enum {
 float_muladd_negate_c = 1,
 float_muladd_negate_product = 2,
-float_muladd_negate_result = 3,
+float_muladd_negate_result = 4,
 };
 
 /*
-- 
1.7.7.6

[Qemu-devel] [PATCH 0/9] target-xtensa: implement FP coprocessor option

[Max Filippov]

This series implements floating point coprocessor and coprocessor context
options for xtensa and fixes a couple of bugs to make it work.

Max Filippov (9):
  softfloat: make float_muladd_negate_* flags independent
  target-xtensa: handle boolean option in overlays
  target-xtensa: specialize softfloat NaN rules
  target-xtensa: add FP registers
  target-xtensa: implement LSCX and LSCI groups
  target-xtensa: implement FP0 arithmetic
  target-xtensa: implement FP0 conversions
  target-xtensa: implement FP1 group
  target-xtensa: implement coprocessor context option

 fpu/softfloat-specialize.h   |9 +-
 fpu/softfloat.h  |2 +-
 gdbstub.c|8 +
 target-xtensa/cpu.h  |8 +
 target-xtensa/helper.h   |   21 +++
 target-xtensa/op_helper.c|  140 +
 target-xtensa/overlay_tool.h |1 +
 target-xtensa/translate.c|  337 --
 8 files changed, 510 insertions(+), 16 deletions(-)

-- 
1.7.7.6

Re: [Qemu-devel] [PATCH 5/5] target-ppc: get rid of the HANDLE_NAN{1, 2, 3} macros

[Peter Maydell]

On 8 September 2012 22:12, Aurelien Jarno  wrote:
> We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros.

This is nice. I feel like it justifies my adding all that stuff
to fpu/ for ARM :-)

-- PMM

Re: [Qemu-devel] [PATCH 4/5] virtio-scsi: Add start/stop functionality for vhost-scsi

[Michael S. Tsirkin]

On Fri, Sep 07, 2012 at 06:00:50PM +0200, Paolo Bonzini wrote:
> Il 07/09/2012 08:48, Nicholas A. Bellinger ha scritto:
> > Cc: Stefan Hajnoczi 
> > Cc: Zhi Yong Wu 
> > Cc: Michael S. Tsirkin 
> > Cc: Paolo Bonzini 
> > Signed-off-by: Nicholas Bellinger 
> > ---
> >  hw/virtio-pci.c  |2 ++
> >  hw/virtio-scsi.c |   49 +
> >  hw/virtio-scsi.h |1 +
> >  3 files changed, 52 insertions(+), 0 deletions(-)
> 
> Please create a completely separate device vhost-scsi-pci instead (or
> virtio-scsi-tcm-pci, or something like that).  It is used completely
> differently from virtio-scsi-pci, it does not make sense to conflate the
> two.
> 
> Paolo

Ideally the name would say how it is different, not what backend it
uses. Any good suggestions?

-- 
MST

Re: [Qemu-devel] [PATCH 1/5] softfloat: fix float{32, 64}_muladd options

[Peter Maydell]

On 8 September 2012 22:40, Max Filippov  wrote:
> On Sun, Sep 9, 2012 at 1:12 AM, Aurelien Jarno  wrote:
>> float{32,64}_muladd takes an enum as a parameter, and not flags. It
>> means the parameter should be checked with == test instead of &.
>
> I've also stumbled upon this bug, have a patch for it in the xtensa tree.
> I guess that the interface was designed to allow combining these flags, why
> don't just make them independent:

Yes, the intent is that all these negations can be controlled
separately so that you can have operations which do more than
one of them. ARM doesn't use the negation options so this isn't
a "live" bug, but IIRC I did check various other architectures
and those do require various combinations of these negate flags.
So I think Max's patch is the correct one.

-- PMM

Re: [Qemu-devel] [PATCH 1/5] softfloat: fix float{32, 64}_muladd options

[Max Filippov]

On Sun, Sep 9, 2012 at 1:12 AM, Aurelien Jarno  wrote:
> float{32,64}_muladd takes an enum as a parameter, and not flags. It
> means the parameter should be checked with == test instead of &.
>
> Cc: Peter Maydell 
> Signed-off-by: Aurelien Jarno 
> ---

Hi Aurelien,

I've also stumbled upon this bug, have a patch for it in the xtensa tree.
I guess that the interface was designed to allow combining these flags, why
don't just make them independent:

diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index feec3a1..2860ca0 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -219,7 +219,7 @@ void float_raise( int8 flags STATUS_PARAM);
 enum {
 float_muladd_negate_c = 1,
 float_muladd_negate_product = 2,
-float_muladd_negate_result = 3,
+float_muladd_negate_result = 4,
 };

 /*

-- 
Thanks.
-- Max

[Qemu-devel] [PATCH 2/5] target-ppc: simplify NaN propagation for vector functions

[Aurelien Jarno]

Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN()
function for PowerPC, implementing the correct NaN propagation rules.
Therefore there is no need to test the operands manually, we can rely
on the softfloat code to do that.

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/int_helper.c |   26 +++---
 1 file changed, 7 insertions(+), 19 deletions(-)

diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index f638b2a..5b2a3c8 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -409,9 +409,7 @@ VARITH(uwm, u32)
 int i;  \
 \
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {\
-HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {\
-r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
-}   \
+r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
 }   \
 }
 VARITHFP(addfp, float32_add)
@@ -1039,9 +1037,7 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, 
ppc_avr_t *b)
 int i;
 
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN1(r->f[i], b->f[i]) {
-r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
-}
+r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
 }
 }
 
@@ -1054,9 +1050,7 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, 
ppc_avr_t *b)
 \
 set_float_rounding_mode(rounding, &s);  \
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {\
-HANDLE_NAN1(r->f[i], b->f[i]) { \
-r->f[i] = float32_round_to_int (b->f[i], &s);   \
-}   \
+r->f[i] = float32_round_to_int (b->f[i], &s);   \
 }   \
 }
 VRFI(n, float_round_nearest_even)
@@ -1089,11 +1083,9 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, 
ppc_avr_t *b)
 int i;
 
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN1(r->f[i], b->f[i]) {
-float32 t = float32_sqrt(b->f[i], &env->vec_status);
+float32 t = float32_sqrt(b->f[i], &env->vec_status);
 
-r->f[i] = float32_div(float32_one, t, &env->vec_status);
-}
+r->f[i] = float32_div(float32_one, t, &env->vec_status);
 }
 }
 
@@ -1109,9 +1101,7 @@ void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, 
ppc_avr_t *b)
 int i;
 
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN1(r->f[i], b->f[i]) {
-r->f[i] = float32_exp2(b->f[i], &env->vec_status);
-}
+r->f[i] = float32_exp2(b->f[i], &env->vec_status);
 }
 }
 
@@ -1120,9 +1110,7 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, 
ppc_avr_t *b)
 int i;
 
 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN1(r->f[i], b->f[i]) {
-r->f[i] = float32_log2(b->f[i], &env->vec_status);
-}
+r->f[i] = float32_log2(b->f[i], &env->vec_status);
 }
 }
 
-- 
1.7.10.4

[Qemu-devel] [PATCH 1/5] softfloat: fix float{32, 64}_muladd options

[Aurelien Jarno]

float{32,64}_muladd takes an enum as a parameter, and not flags. It
means the parameter should be checked with == test instead of &.

Cc: Peter Maydell 
Signed-off-by: Aurelien Jarno 
---
 fpu/softfloat.c |   12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index b29256a..518e45b 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2171,15 +2171,15 @@ float32 float32_muladd(float32 a, float32 b, float32 c, 
int flags STATUS_PARAM)
 return float32_default_nan;
 }
 
-if (flags & float_muladd_negate_c) {
+if (flags == float_muladd_negate_c) {
 cSign ^= 1;
 }
 
-signflip = (flags & float_muladd_negate_result) ? 1 : 0;
+signflip = (flags == float_muladd_negate_result) ? 1 : 0;
 
 /* Work out the sign and type of the product */
 pSign = aSign ^ bSign;
-if (flags & float_muladd_negate_product) {
+if (flags == float_muladd_negate_product) {
 pSign ^= 1;
 }
 pInf = (aExp == 0xff) || (bExp == 0xff);
@@ -3724,15 +3724,15 @@ float64 float64_muladd(float64 a, float64 b, float64 c, 
int flags STATUS_PARAM)
 return float64_default_nan;
 }
 
-if (flags & float_muladd_negate_c) {
+if (flags == float_muladd_negate_c) {
 cSign ^= 1;
 }
 
-signflip = (flags & float_muladd_negate_result) ? 1 : 0;
+signflip = (flags == float_muladd_negate_result) ? 1 : 0;
 
 /* Work out the sign and type of the product */
 pSign = aSign ^ bSign;
-if (flags & float_muladd_negate_product) {
+if (flags == float_muladd_negate_product) {
 pSign ^= 1;
 }
 pInf = (aExp == 0x7ff) || (bExp == 0x7ff);
-- 
1.7.10.4

[Qemu-devel] [PATCH 3/5] target-ppc: use the softfloat min/max functions

[Aurelien Jarno]

Use the new softfloat float32_min() and float32_max() to implement the
vminfp and vmaxfp instructions. As a bonus we can get rid of the call to
the HANDLE_NAN2 macro, as the NaN handling is directly done at the
softfloat level.

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/int_helper.c |   23 ++-
 1 file changed, 2 insertions(+), 21 deletions(-)

diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 5b2a3c8..6141243 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -414,6 +414,8 @@ VARITH(uwm, u32)
 }
 VARITHFP(addfp, float32_add)
 VARITHFP(subfp, float32_sub)
+VARITHFP(minfp, float32_min)
+VARITHFP(maxfp, float32_max)
 #undef VARITHFP
 
 #define VARITHSAT_CASE(type, op, cvt, element)  \
@@ -728,27 +730,6 @@ VMINMAX(uw, u32)
 #undef VMINMAX_DO
 #undef VMINMAX
 
-#define VMINMAXFP(suffix, rT, rF)   \
-void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
-  ppc_avr_t *b) \
-{   \
-int i;  \
-\
-for (i = 0; i < ARRAY_SIZE(r->f); i++) {\
-HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {\
-if (float32_lt_quiet(a->f[i], b->f[i],  \
- &env->vec_status)) {   \
-r->f[i] = rT->f[i]; \
-} else {\
-r->f[i] = rF->f[i]; \
-}   \
-}   \
-}   \
-}
-VMINMAXFP(minfp, a, b)
-VMINMAXFP(maxfp, b, a)
-#undef VMINMAXFP
-
 void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
 {
 int i;
-- 
1.7.10.4

[Qemu-devel] [PATCH 4/5] target-ppc: use the softfloat float32_muladd function

[Aurelien Jarno]

Use the new softfloat float32_muladd() function to implement the vmaddfp
and vnmsubfp instructions. As a bonus we can get rid of the call to the
HANDLE_NAN3 macro, as the NaN handling is directly done at the softfloat
level.

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/int_helper.c |   57 ---
 1 file changed, 14 insertions(+), 43 deletions(-)

diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 6141243..51cb97c 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -418,6 +418,20 @@ VARITHFP(minfp, float32_min)
 VARITHFP(maxfp, float32_max)
 #undef VARITHFP
 
+#define VARITHFPFMA(suffix, type)   \
+void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
+   ppc_avr_t *b, ppc_avr_t *c)  \
+{   \
+int i;  \
+for (i = 0; i < ARRAY_SIZE(r->f); i++) {\
+r->f[i] = float32_muladd(a->f[i], c->f[i], b->f[i], \
+ type, &env->vec_status);   \
+}   \
+}
+VARITHFPFMA(maddfp, 0);
+VARITHFPFMA(nmsubfp, float_muladd_negate_result);
+#undef VARITHFPFMA
+
 #define VARITHSAT_CASE(type, op, cvt, element)  \
 {   \
 type result = (type)a->element[i] op (type)b->element[i];   \
@@ -649,27 +663,6 @@ VCT(uxs, cvtsduw, u32)
 VCT(sxs, cvtsdsw, s32)
 #undef VCT
 
-void helper_vmaddfp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
-ppc_avr_t *c)
-{
-int i;
-
-for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
-/* Need to do the computation in higher precision and round
- * once at the end.  */
-float64 af, bf, cf, t;
-
-af = float32_to_float64(a->f[i], &env->vec_status);
-bf = float32_to_float64(b->f[i], &env->vec_status);
-cf = float32_to_float64(c->f[i], &env->vec_status);
-t = float64_mul(af, cf, &env->vec_status);
-t = float64_add(t, bf, &env->vec_status);
-r->f[i] = float64_to_float32(t, &env->vec_status);
-}
-}
-}
-
 void helper_vmhaddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
   ppc_avr_t *b, ppc_avr_t *c)
 {
@@ -909,28 +902,6 @@ VMUL(uh, u16, u32)
 #undef VMUL_DO
 #undef VMUL
 
-void helper_vnmsubfp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
- ppc_avr_t *b, ppc_avr_t *c)
-{
-int i;
-
-for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
-/* Need to do the computation is higher precision and round
- * once at the end.  */
-float64 af, bf, cf, t;
-
-af = float32_to_float64(a->f[i], &env->vec_status);
-bf = float32_to_float64(b->f[i], &env->vec_status);
-cf = float32_to_float64(c->f[i], &env->vec_status);
-t = float64_mul(af, cf, &env->vec_status);
-t = float64_sub(t, bf, &env->vec_status);
-t = float64_chs(t);
-r->f[i] = float64_to_float32(t, &env->vec_status);
-}
-}
-}
-
 void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
   ppc_avr_t *c)
 {
-- 
1.7.10.4

[Qemu-devel] [PATCH 5/5] target-ppc: get rid of the HANDLE_NAN{1, 2, 3} macros

[Aurelien Jarno]

We can finally get rid of the ugly HANDLE_NAN{1,2,3} macros.

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 target-ppc/int_helper.c |   21 -
 1 file changed, 21 deletions(-)

diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 51cb97c..6d8bf4d 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -287,23 +287,6 @@ target_ulong helper_602_mfrom(target_ulong arg)
 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
 #endif
 
-/* If X is a NaN, store the corresponding QNaN into RESULT.  Otherwise,
- * execute the following block.  */
-#define DO_HANDLE_NAN(result, x)\
-if (float32_is_any_nan(x)) {\
-CPU_FloatU __f; \
-__f.f = x;  \
-__f.l = __f.l | (1 << 22);  /* Set QNaN bit. */ \
-result = __f.f; \
-} else
-
-#define HANDLE_NAN1(result, x)  \
-DO_HANDLE_NAN(result, x)
-#define HANDLE_NAN2(result, x, y)   \
-DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y)
-#define HANDLE_NAN3(result, x, y, z)\
-DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y) DO_HANDLE_NAN(result, z)
-
 /* Saturating arithmetic helpers.  */
 #define SATCVT(from, to, from_type, to_type, min, max)  \
 static inline to_type cvt##from##to(from_type x, int *sat)  \
@@ -1413,10 +1396,6 @@ VUPK(lsh, s32, s16, UPKLO)
 #undef UPKHI
 #undef UPKLO
 
-#undef DO_HANDLE_NAN
-#undef HANDLE_NAN1
-#undef HANDLE_NAN2
-#undef HANDLE_NAN3
 #undef VECTOR_FOR_INORDER_I
 #undef HI_IDX
 #undef LO_IDX
-- 
1.7.10.4

Re: [Qemu-devel] QEMU (no kvm) Win7 (64bit) boot error

[Clemens Kolbitsch]

On Fri, Sep 7, 2012 at 9:26 PM, Stefan Weil  wrote:
> Am 08.09.2012 02:48, schrieb Clemens Kolbitsch:
>>
>> Hi guys,
>>
>> I need to run Win7 64bit in Qemu without KVM support. I found a few
>> messages concerning the "unsupported architecture" problem (Windows
>> shows a BSOD with "STOP 0x005D ..." on boot), for example
>>
>> http://lists.gnu.org/archive/html/qemu-devel/2011-03/msg01623.html
>> or
>> http://permalink.gmane.org/gmane.comp.emulators.qemu/92457
>>
>> but I don't think there was ever a solution to the problem - at least
>> what is proposed does not work (I've tried stable and GIT versions).
>>
>> Since I have a decent background of modifying the Qemu internals, I'm
>> more than happy to contribute to solving this issue, but I'm not sure
>> if anyone is currently working on it (i.e., I don't want to start at 0
>> in case someone is about to release a patch).
>>
>> Please let me know if there is already a know solution/workaround or
>> whoever might be working on it, please ping me so we can sync.
>>
>> BTW, in case this is necessary, here are the details of what I
>> need/what is not working:
>>
>> Qemu: current git-trunk,
>>
>> x86_64-softmmu$ ./qemu-system-x86_64 --version
>> QEMU emulator version 1.2.50, Copyright (c) 2003-2008 Fabrice Bellard
>>
>> host: 64bit, Ubuntu LTS12.04
>>
>> guest: 64bit Windows 7, no KVM possible
>>
>> Thanks!
>> -Clemens
>
>
> Hi Clemens,
>
> AFAIK, nobody is working on this issue which exists for a long time now.
> It would be great if you could find a solution to make QEMU without KVM
> work with Windows guests.

Hi Stefan,

thanks for the info. I'll work on it then - hopefully I can come back
with a patch soon!

> PS: It's QEMU, not Qemu. I modified the subject in my reply :-)

hehe, old habbit :) I'll try to remember - but why is the ML then
called "Qemu-devel" ? ;)

-Clemens

Re: [Qemu-devel] [PATCH 05/12] alpha: use the new pci_vga_init() function

[Alexander Graf]

On 08.09.2012, at 17:00, Alexander Graf  wrote:

> 
> 
> On 08.09.2012, at 16:57, Aurelien Jarno  wrote:
> 
>> On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
>>> 
>>> 
>>> On 08.09.2012, at 13:26, Aurelien Jarno  wrote:
>>> 
 This remove the fallback to std-vga in case, as availability of the
 requested vga device is now tested in vl.c, and returns an error message
 to the user.
 
 Cc: Richard Henderson 
 Signed-off-by: Aurelien Jarno 
 ---
 hw/alpha_dp264.c |2 +-
 hw/alpha_pci.c   |   24 
 hw/alpha_sys.h   |2 --
 3 files changed, 1 insertion(+), 27 deletions(-)
 
 diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
 index 9eb939f..5ea04c7 100644
 --- a/hw/alpha_dp264.c
 +++ b/hw/alpha_dp264.c
 @@ -77,7 +77,7 @@ static void clipper_init(ram_addr_t ram_size,
   isa_create_simple(isa_bus, "i8042");
 
   /* VGA setup.  Don't bother loading the bios.  */
 -alpha_pci_vga_setup(pci_bus);
 +pci_vga_init(pci_bus);
 
   /* Serial code setup.  */
   for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
 diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
 index 0352e72..8079a46 100644
 --- a/hw/alpha_pci.c
 +++ b/hw/alpha_pci.c
 @@ -10,8 +10,6 @@
 #include "alpha_sys.h"
 #include "qemu-log.h"
 #include "sysemu.h"
 -#include "vmware_vga.h"
 -#include "vga-pci.h"
 
 
 /* PCI IO reads/writes, to byte-word addressable memory.  */
 @@ -109,25 +107,3 @@ const MemoryRegionOps alpha_pci_iack_ops = {
   .max_access_size = 4,
   },
 };
 -
 -void alpha_pci_vga_setup(PCIBus *pci_bus)
 -{
 -switch (vga_interface_type) {
 -#ifdef CONFIG_SPICE
 -case VGA_QXL:
 -pci_create_simple(pci_bus, -1, "qxl-vga");
 -return;
 -#endif
 -case VGA_CIRRUS:
 -pci_cirrus_vga_init(pci_bus);
 -return;
 -case VGA_VMWARE:
 -pci_vmsvga_init(pci_bus);
 -return;
 -}
 -/* If VGA is enabled at all, and one of the above didn't work, then
 -   fallback to Standard VGA.  */
 -if (vga_interface_type != VGA_NONE) {
 -pci_std_vga_init(pci_bus);
 -}
>>> 
>>> You're removing the fallback logic here, no?
>>> 
>> 
>> Yes, because the availability of the other type is now checked in vl.c
>> so that pci_vga_init() is able to create the requested card. That way
>> the users get an error message instead of having a card different to what
>> they request.
> 
> But this is alpha and you're calling pci_vga_init, not pc_vga_init :).

Ah, I misread the code. It's creating a pci std vga adapter as fallback. Then 
it's all fine :)

Alex

> 
> Alex
> 
>> 
>> -- 
>> Aurelien Jarno  GPG: 1024D/F1BCDB73
>> aurel...@aurel32.net http://www.aurel32.net
> 

Re: [Qemu-devel] [PATCH 05/12] alpha: use the new pci_vga_init() function

[Alexander Graf]

On 08.09.2012, at 16:57, Aurelien Jarno  wrote:

> On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
>> 
>> 
>> On 08.09.2012, at 13:26, Aurelien Jarno  wrote:
>> 
>>> This remove the fallback to std-vga in case, as availability of the
>>> requested vga device is now tested in vl.c, and returns an error message
>>> to the user.
>>> 
>>> Cc: Richard Henderson 
>>> Signed-off-by: Aurelien Jarno 
>>> ---
>>> hw/alpha_dp264.c |2 +-
>>> hw/alpha_pci.c   |   24 
>>> hw/alpha_sys.h   |2 --
>>> 3 files changed, 1 insertion(+), 27 deletions(-)
>>> 
>>> diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
>>> index 9eb939f..5ea04c7 100644
>>> --- a/hw/alpha_dp264.c
>>> +++ b/hw/alpha_dp264.c
>>> @@ -77,7 +77,7 @@ static void clipper_init(ram_addr_t ram_size,
>>>isa_create_simple(isa_bus, "i8042");
>>> 
>>>/* VGA setup.  Don't bother loading the bios.  */
>>> -alpha_pci_vga_setup(pci_bus);
>>> +pci_vga_init(pci_bus);
>>> 
>>>/* Serial code setup.  */
>>>for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
>>> diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
>>> index 0352e72..8079a46 100644
>>> --- a/hw/alpha_pci.c
>>> +++ b/hw/alpha_pci.c
>>> @@ -10,8 +10,6 @@
>>> #include "alpha_sys.h"
>>> #include "qemu-log.h"
>>> #include "sysemu.h"
>>> -#include "vmware_vga.h"
>>> -#include "vga-pci.h"
>>> 
>>> 
>>> /* PCI IO reads/writes, to byte-word addressable memory.  */
>>> @@ -109,25 +107,3 @@ const MemoryRegionOps alpha_pci_iack_ops = {
>>>.max_access_size = 4,
>>>},
>>> };
>>> -
>>> -void alpha_pci_vga_setup(PCIBus *pci_bus)
>>> -{
>>> -switch (vga_interface_type) {
>>> -#ifdef CONFIG_SPICE
>>> -case VGA_QXL:
>>> -pci_create_simple(pci_bus, -1, "qxl-vga");
>>> -return;
>>> -#endif
>>> -case VGA_CIRRUS:
>>> -pci_cirrus_vga_init(pci_bus);
>>> -return;
>>> -case VGA_VMWARE:
>>> -pci_vmsvga_init(pci_bus);
>>> -return;
>>> -}
>>> -/* If VGA is enabled at all, and one of the above didn't work, then
>>> -   fallback to Standard VGA.  */
>>> -if (vga_interface_type != VGA_NONE) {
>>> -pci_std_vga_init(pci_bus);
>>> -}
>> 
>> You're removing the fallback logic here, no?
>> 
> 
> Yes, because the availability of the other type is now checked in vl.c
> so that pci_vga_init() is able to create the requested card. That way
> the users get an error message instead of having a card different to what
> they request.

But this is alpha and you're calling pci_vga_init, not pc_vga_init :).

Alex

> 
> -- 
> Aurelien Jarno  GPG: 1024D/F1BCDB73
> aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Alexander Graf]

On 08.09.2012, at 14:30, Blue Swirl  wrote:

> On Sat, Sep 8, 2012 at 12:13 PM, Alexander Graf  wrote:
>> 
>> 
>> On 08.09.2012, at 12:16, Blue Swirl  wrote:
>> 
>>> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf  wrote:
 
 
 On 08.09.2012, at 10:06, Blue Swirl  wrote:
 
> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
>> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>> 
>>> Reinventing a disassembler for ever growing x86 assembly is
>>> no fun.
>> 
>> We can try linking to a disassembler library.  I use udis86 to
>> disassemble instructions in kvm tracepoints
>> (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
>> it's maintained but not heavily so.
> 
> I think commonality with KVM would be preferred. The library looks
> neat and based on changelog, more actively developed than BSD DDB.
> 
>> 
>> Of course for non-x86 we'd need to continue using binutils; this is
>> about copying code vs. libraries, not about licensing.
> 
> For most architectures, pre-GPLv3 binutils is good enough since the
> instruction set does not change anymore. Maybe only PPC and Sparc64
> still change besides x86. New CPUs types more recent than 2007 will
> have problems.
 
 Alternatively we could try to run the disassembler in a different process, 
 right?
>>> 
>>> For qemu.log this would be doable and even improve performance since
>>> only binary data would be transferred.
>>> 
>>> But for monitor disassembly command x/i it may be too clumsy.
>> 
>> Why would it be clumsy? We'd have to make sure we are communicating 
>> synchronously with the daemon, but apart from that it shouldn't be too 
>> different from the log, no?
> 
> The log file should be written as binary which the disassembly tool
> could read.

The log file contains a lot more information than just the diassembly. You get 
cpu state dumps, tcg op dumps, and above all there are a very big amount of log 
writing bits throughout the code for debug purposes that write plain ascii.

Do you think it's worth creating a 2-step process out of this? I was more 
thinking along the lines of a second process that qemu would spawn when log 
file is active / on monitor command which then would get binary opcodes voa a 
pipe and returns ascii disassembly that qemu cam use again.

That second program could even be built as part of our build process, right? We 
would then be able to pull in gplv3 code from binutils into that program, but 
keep it out of the main project.


Alex

Re: [Qemu-devel] [PATCH 05/12] alpha: use the new pci_vga_init() function

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 04:47:43PM +0200, Alexander Graf wrote:
> 
> 
> On 08.09.2012, at 13:26, Aurelien Jarno  wrote:
> 
> > This remove the fallback to std-vga in case, as availability of the
> > requested vga device is now tested in vl.c, and returns an error message
> > to the user.
> > 
> > Cc: Richard Henderson 
> > Signed-off-by: Aurelien Jarno 
> > ---
> > hw/alpha_dp264.c |2 +-
> > hw/alpha_pci.c   |   24 
> > hw/alpha_sys.h   |2 --
> > 3 files changed, 1 insertion(+), 27 deletions(-)
> > 
> > diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
> > index 9eb939f..5ea04c7 100644
> > --- a/hw/alpha_dp264.c
> > +++ b/hw/alpha_dp264.c
> > @@ -77,7 +77,7 @@ static void clipper_init(ram_addr_t ram_size,
> > isa_create_simple(isa_bus, "i8042");
> > 
> > /* VGA setup.  Don't bother loading the bios.  */
> > -alpha_pci_vga_setup(pci_bus);
> > +pci_vga_init(pci_bus);
> > 
> > /* Serial code setup.  */
> > for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
> > diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
> > index 0352e72..8079a46 100644
> > --- a/hw/alpha_pci.c
> > +++ b/hw/alpha_pci.c
> > @@ -10,8 +10,6 @@
> > #include "alpha_sys.h"
> > #include "qemu-log.h"
> > #include "sysemu.h"
> > -#include "vmware_vga.h"
> > -#include "vga-pci.h"
> > 
> > 
> > /* PCI IO reads/writes, to byte-word addressable memory.  */
> > @@ -109,25 +107,3 @@ const MemoryRegionOps alpha_pci_iack_ops = {
> > .max_access_size = 4,
> > },
> > };
> > -
> > -void alpha_pci_vga_setup(PCIBus *pci_bus)
> > -{
> > -switch (vga_interface_type) {
> > -#ifdef CONFIG_SPICE
> > -case VGA_QXL:
> > -pci_create_simple(pci_bus, -1, "qxl-vga");
> > -return;
> > -#endif
> > -case VGA_CIRRUS:
> > -pci_cirrus_vga_init(pci_bus);
> > -return;
> > -case VGA_VMWARE:
> > -pci_vmsvga_init(pci_bus);
> > -return;
> > -}
> > -/* If VGA is enabled at all, and one of the above didn't work, then
> > -   fallback to Standard VGA.  */
> > -if (vga_interface_type != VGA_NONE) {
> > -pci_std_vga_init(pci_bus);
> > -}
> 
> You're removing the fallback logic here, no?
> 

Yes, because the availability of the other type is now checked in vl.c
so that pci_vga_init() is able to create the requested card. That way
the users get an error message instead of having a card different to what
they request.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH 00/12] Rework PCI video card initialization

[Alexander Graf]

On 08.09.2012, at 13:26, Aurelien Jarno  wrote:

> This patch series is technically a new version of the "add a video
> card only when requested" series I sent yesterday. It uses a different
> approach though.
> 
> It creates a new pci_vga_init() function that takes care of initializing
> the requested PCI video card. This way there is no need to duplicate
> code in the various machines QEMU supports, and has the advantage that
> the newly added PCI video cards are available to all machines without
> having to touch machine specific code.
> 
> Cc: Alexander Graf 
> Cc: Andreas Färber 
> Cc: Anthony Liguori 
> Cc: Blue Swirl 
> Cc: David Gibson 
> Cc: Gerd Hoffmann 
> Cc: Richard Henderson 

Apart from my comment and the bits already mentioned, the series looks very 
good. It's certainly a trenendous cleanup + simplification of the vga code.

Alex

> 
> Aurelien Jarno (12):
>  vga: rename pci_vga_init() into pci_std_vga_init()
>  vl.c: check for qxl availability
>  pci: add a pci_vga_init() function
>  mips/malta: use the new pci_vga_init() function
>  alpha: use the new pci_vga_init() function
>  ppc/newworld: use the new pci_vga_init() function
>  ppc/oldworld: use the new pci_vga_init() function
>  ppc/prep: use the new pci_vga_init() function
>  ppc/pSeries: use the new pci_vga_init() function
>  sun/sun4u: use the new pci_vga_init() function
>  pc: use the new pci_vga_init() function
>  vga: cleanup after pci_vga_init() conversion
> 
> hw/alpha_dp264.c  |2 +-
> hw/alpha_pci.c|   24 
> hw/alpha_sys.h|2 --
> hw/cirrus_vga.c   |6 --
> hw/mips_malta.c   |   10 +-
> hw/pc.c   |   41 +++--
> hw/pci.c  |   18 ++
> hw/pci.h  |3 +++
> hw/ppc_newworld.c |1 -
> hw/ppc_oldworld.c |1 -
> hw/ppc_prep.c |1 -
> hw/spapr.c|7 ++-
> hw/sun4u.c|1 -
> hw/vga-pci.c  |   10 ++
> hw/vga-pci.h  |   12 
> hw/vmware_vga.c   |1 -
> hw/vmware_vga.h   |   15 ---
> sysemu.h  |4 
> vl.c  |   12 +++-
> 19 files changed, 53 insertions(+), 118 deletions(-)
> delete mode 100644 hw/vga-pci.h
> delete mode 100644 hw/vmware_vga.h
> 
> -- 
> 1.7.10.4
> 
> 

Re: [Qemu-devel] [PATCH 05/12] alpha: use the new pci_vga_init() function

[Alexander Graf]

On 08.09.2012, at 13:26, Aurelien Jarno  wrote:

> This remove the fallback to std-vga in case, as availability of the
> requested vga device is now tested in vl.c, and returns an error message
> to the user.
> 
> Cc: Richard Henderson 
> Signed-off-by: Aurelien Jarno 
> ---
> hw/alpha_dp264.c |2 +-
> hw/alpha_pci.c   |   24 
> hw/alpha_sys.h   |2 --
> 3 files changed, 1 insertion(+), 27 deletions(-)
> 
> diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
> index 9eb939f..5ea04c7 100644
> --- a/hw/alpha_dp264.c
> +++ b/hw/alpha_dp264.c
> @@ -77,7 +77,7 @@ static void clipper_init(ram_addr_t ram_size,
> isa_create_simple(isa_bus, "i8042");
> 
> /* VGA setup.  Don't bother loading the bios.  */
> -alpha_pci_vga_setup(pci_bus);
> +pci_vga_init(pci_bus);
> 
> /* Serial code setup.  */
> for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
> diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
> index 0352e72..8079a46 100644
> --- a/hw/alpha_pci.c
> +++ b/hw/alpha_pci.c
> @@ -10,8 +10,6 @@
> #include "alpha_sys.h"
> #include "qemu-log.h"
> #include "sysemu.h"
> -#include "vmware_vga.h"
> -#include "vga-pci.h"
> 
> 
> /* PCI IO reads/writes, to byte-word addressable memory.  */
> @@ -109,25 +107,3 @@ const MemoryRegionOps alpha_pci_iack_ops = {
> .max_access_size = 4,
> },
> };
> -
> -void alpha_pci_vga_setup(PCIBus *pci_bus)
> -{
> -switch (vga_interface_type) {
> -#ifdef CONFIG_SPICE
> -case VGA_QXL:
> -pci_create_simple(pci_bus, -1, "qxl-vga");
> -return;
> -#endif
> -case VGA_CIRRUS:
> -pci_cirrus_vga_init(pci_bus);
> -return;
> -case VGA_VMWARE:
> -pci_vmsvga_init(pci_bus);
> -return;
> -}
> -/* If VGA is enabled at all, and one of the above didn't work, then
> -   fallback to Standard VGA.  */
> -if (vga_interface_type != VGA_NONE) {
> -pci_std_vga_init(pci_bus);
> -}

You're removing the fallback logic here, no?

Alex

> -}
> diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
> index de40f8b..7604d09 100644
> --- a/hw/alpha_sys.h
> +++ b/hw/alpha_sys.h
> @@ -19,6 +19,4 @@ extern const MemoryRegionOps alpha_pci_bw_io_ops;
> extern const MemoryRegionOps alpha_pci_conf1_ops;
> extern const MemoryRegionOps alpha_pci_iack_ops;
> 
> -void alpha_pci_vga_setup(PCIBus *pci_bus);
> -
> #endif
> -- 
> 1.7.10.4
> 
> 

Re: [Qemu-devel] [PATCH v6 2/2] block: Support GlusterFS as a QEMU block backend

[Bharata B Rao]

On Fri, Sep 07, 2012 at 05:11:33PM +0200, Paolo Bonzini wrote:
> This is a bug that has to be fixed anyway.  There are provisions in
> aio.c, but they are broken apparently.  Can you try this:
> 
> diff --git a/aio.c b/aio.c
> index 0a9eb10..99b8b72 100644
> --- a/aio.c
> +++ b/aio.c
> @@ -119,7 +119,7 @@ bool qemu_aio_wait(void)
>  return true;
>  }
> 
> -walking_handlers = 1;
> +walking_handlers++;
> 
>  FD_ZERO(&rdfds);
>  FD_ZERO(&wrfds);
> @@ -147,7 +147,7 @@ bool qemu_aio_wait(void)
>  }
>  }
> 
> -walking_handlers = 0;
> +walking_handlers--;
> 
>  /* No AIO operations?  Get us out of here */
>  if (!busy) {
> @@ -159,7 +159,7 @@ bool qemu_aio_wait(void)
> 
>  /* if we have any readable fds, dispatch event */
>  if (ret > 0) {
> -walking_handlers = 1;
> +walking_handlers++;
> 
>  /* we have to walk very carefully in case
>   * qemu_aio_set_fd_handler is called while we're walking */
> @@ -187,7 +187,7 @@ bool qemu_aio_wait(void)
>  }
>  }
> 
> -walking_handlers = 0;
> +walking_handlers--;
>  }
> 
>  return true;
> 

This works. I am able to create qcow2 files on gluster backend with this fix.

Regards,
Bharata.

[Qemu-devel] [PATCH] tci: Support deposit operations

[Stefan Weil]

The operations for INDEX_op_deposit_i32 and INDEX_op_deposit_i64
are now supported and enabled by default.

Signed-off-by: Stefan Weil 
---
 tcg/tci/tcg-target.c |   24 
 tcg/tci/tcg-target.h |4 ++--
 tci.c|   22 ++
 3 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
index ef8580f..7124b15 100644
--- a/tcg/tci/tcg-target.c
+++ b/tcg/tci/tcg-target.c
@@ -123,6 +123,9 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
 { INDEX_op_rotl_i32, { R, RI, RI } },
 { INDEX_op_rotr_i32, { R, RI, RI } },
 #endif
+#if TCG_TARGET_HAS_deposit_i32
+{ INDEX_op_deposit_i32, { R, "0", R } },
+#endif
 
 { INDEX_op_brcond_i32, { R, RI } },
 
@@ -201,6 +204,9 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
 { INDEX_op_rotl_i64, { R, RI, RI } },
 { INDEX_op_rotr_i64, { R, RI, RI } },
 #endif
+#if TCG_TARGET_HAS_deposit_i64
+{ INDEX_op_deposit_i64, { R, "0", R } },
+#endif
 { INDEX_op_brcond_i64, { R, RI } },
 
 #if TCG_TARGET_HAS_ext8s_i64
@@ -655,6 +661,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const 
TCGArg *args,
 tcg_out_ri32(s, const_args[1], args[1]);
 tcg_out_ri32(s, const_args[2], args[2]);
 break;
+case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
+tcg_out_r(s, args[0]);
+tcg_out_r(s, args[1]);
+tcg_out_r(s, args[2]);
+assert(args[3] <= UINT8_MAX);
+tcg_out8(s, args[3]);
+assert(args[4] <= UINT8_MAX);
+tcg_out8(s, args[4]);
+break;
 
 #if TCG_TARGET_REG_BITS == 64
 case INDEX_op_mov_i64:
@@ -682,6 +697,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const 
TCGArg *args,
 tcg_out_ri64(s, const_args[1], args[1]);
 tcg_out_ri64(s, const_args[2], args[2]);
 break;
+case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
+tcg_out_r(s, args[0]);
+tcg_out_r(s, args[1]);
+tcg_out_r(s, args[2]);
+assert(args[3] <= UINT8_MAX);
+tcg_out8(s, args[3]);
+assert(args[4] <= UINT8_MAX);
+tcg_out8(s, args[4]);
+break;
 case INDEX_op_div_i64:  /* Optional (TCG_TARGET_HAS_div_i64). */
 case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
 case INDEX_op_rem_i64:  /* Optional (TCG_TARGET_HAS_div_i64). */
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 30a0f21..f7ca8be 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -67,7 +67,7 @@
 #define TCG_TARGET_HAS_ext8u_i321
 #define TCG_TARGET_HAS_ext16u_i32   1
 #define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_deposit_i32  0
+#define TCG_TARGET_HAS_deposit_i32  1
 #define TCG_TARGET_HAS_eqv_i32  0
 #define TCG_TARGET_HAS_nand_i32 0
 #define TCG_TARGET_HAS_nor_i32  0
@@ -80,7 +80,7 @@
 #define TCG_TARGET_HAS_bswap16_i64  1
 #define TCG_TARGET_HAS_bswap32_i64  1
 #define TCG_TARGET_HAS_bswap64_i64  1
-#define TCG_TARGET_HAS_deposit_i64  0
+#define TCG_TARGET_HAS_deposit_i64  1
 /* Not more than one of the next two defines must be 1. */
 #define TCG_TARGET_HAS_div_i64  0
 #define TCG_TARGET_HAS_div2_i64 0
diff --git a/tci.c b/tci.c
index c79350d..01d365a 100644
--- a/tci.c
+++ b/tci.c
@@ -697,6 +697,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, 
uint8_t *tb_ptr)
 tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2)));
 break;
 #endif
+#if TCG_TARGET_HAS_deposit_i32
+case INDEX_op_deposit_i32:
+t0 = *tb_ptr++;
+t1 = tci_read_r32(&tb_ptr);
+t2 = tci_read_r32(&tb_ptr);
+tmp16 = *tb_ptr++;
+tmp8 = *tb_ptr++;
+tmp32 = (((1 << tmp8) - 1) << tmp16);
+tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
+break;
+#endif
 case INDEX_op_brcond_i32:
 t0 = tci_read_r32(&tb_ptr);
 t1 = tci_read_ri32(&tb_ptr);
@@ -944,6 +955,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, 
uint8_t *tb_ptr)
 TODO();
 break;
 #endif
+#if TCG_TARGET_HAS_deposit_i64
+case INDEX_op_deposit_i64:
+t0 = *tb_ptr++;
+t1 = tci_read_r64(&tb_ptr);
+t2 = tci_read_r64(&tb_ptr);
+tmp16 = *tb_ptr++;
+tmp8 = *tb_ptr++;
+tmp64 = (((1ULL << tmp8) - 1) << tmp16);
+tci_write_reg32(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
+break;
+#endif
 case INDEX_op_brcond_i64:
 t0 = tci_read_r64(&tb_ptr);
 t1 = tci_read_ri64(&tb_ptr);
-- 
1.7.10

Re: [Qemu-devel] [PATCH v2 12/14] target-sh4: switch to AREG0 free mode

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 11:50:04AM +, Blue Swirl wrote:
> Add an explicit CPUState parameter instead of relying on AREG0
> and switch to AREG0 free mode.
> 
> Signed-off-by: Blue Swirl 
> ---
>  configure|2 +-
>  target-sh4/Makefile.objs |2 -
>  target-sh4/helper.h  |   84 +++---
>  target-sh4/op_helper.c   |  182 ++---
>  target-sh4/translate.c   |  114 -
>  5 files changed, 195 insertions(+), 189 deletions(-)
> 
> diff --git a/configure b/configure
> index d760e07..d69e43e 100755
> --- a/configure
> +++ b/configure
> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
> "$target_dir/Makefile"
>  
>  
>  case "$target_arch2" in
> -  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
> sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> +  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
> sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>  echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>;;
>  esac
> diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
> index 2e0e093..ca20f21 100644
> --- a/target-sh4/Makefile.objs
> +++ b/target-sh4/Makefile.objs
> @@ -1,4 +1,2 @@
>  obj-y += translate.o op_helper.o helper.o cpu.o
>  obj-$(CONFIG_SOFTMMU) += machine.o
> -
> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> diff --git a/target-sh4/helper.h b/target-sh4/helper.h
> index 95e3c7c..6e4f108 100644
> --- a/target-sh4/helper.h
> +++ b/target-sh4/helper.h
> @@ -1,54 +1,54 @@
>  #include "def-helper.h"
>  
> -DEF_HELPER_0(ldtlb, void)
> -DEF_HELPER_0(raise_illegal_instruction, void)
> -DEF_HELPER_0(raise_slot_illegal_instruction, void)
> -DEF_HELPER_0(raise_fpu_disable, void)
> -DEF_HELPER_0(raise_slot_fpu_disable, void)
> -DEF_HELPER_0(debug, void)
> -DEF_HELPER_1(sleep, void, i32)
> -DEF_HELPER_1(trapa, void, i32)
> +DEF_HELPER_1(ldtlb, void, env)
> +DEF_HELPER_1(raise_illegal_instruction, void, env)
> +DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
> +DEF_HELPER_1(raise_fpu_disable, void, env)
> +DEF_HELPER_1(raise_slot_fpu_disable, void, env)
> +DEF_HELPER_1(debug, void, env)
> +DEF_HELPER_2(sleep, void, env, i32)
> +DEF_HELPER_2(trapa, void, env, i32)
>  
> -DEF_HELPER_2(movcal, void, i32, i32)
> -DEF_HELPER_0(discard_movcal_backup, void)
> -DEF_HELPER_1(ocbi, void, i32)
> +DEF_HELPER_3(movcal, void, env, i32, i32)
> +DEF_HELPER_1(discard_movcal_backup, void, env)
> +DEF_HELPER_2(ocbi, void, env, i32)
>  
> -DEF_HELPER_2(addv, i32, i32, i32)
> -DEF_HELPER_2(addc, i32, i32, i32)
> -DEF_HELPER_2(subv, i32, i32, i32)
> -DEF_HELPER_2(subc, i32, i32, i32)
> -DEF_HELPER_2(div1, i32, i32, i32)
> -DEF_HELPER_2(macl, void, i32, i32)
> -DEF_HELPER_2(macw, void, i32, i32)
> +DEF_HELPER_3(addv, i32, env, i32, i32)
> +DEF_HELPER_3(addc, i32, env, i32, i32)
> +DEF_HELPER_3(subv, i32, env, i32, i32)
> +DEF_HELPER_3(subc, i32, env, i32, i32)
> +DEF_HELPER_3(div1, i32, env, i32, i32)
> +DEF_HELPER_3(macl, void, env, i32, i32)
> +DEF_HELPER_3(macw, void, env, i32, i32)
>  
> -DEF_HELPER_1(ld_fpscr, void, i32)
> +DEF_HELPER_2(ld_fpscr, void, env, i32)
>  
>  DEF_HELPER_1(fabs_FT, f32, f32)
>  DEF_HELPER_1(fabs_DT, f64, f64)
> -DEF_HELPER_2(fadd_FT, f32, f32, f32)
> -DEF_HELPER_2(fadd_DT, f64, f64, f64)
> -DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
> -DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
> +DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
> +DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
> +DEF_HELPER_2(fcnvds_DT_FT, f32, env, f64)
>  
> -DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
> -DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
> -DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
> -DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
> -DEF_HELPER_2(fdiv_FT, f32, f32, f32)
> -DEF_HELPER_2(fdiv_DT, f64, f64, f64)
> -DEF_HELPER_1(float_FT, f32, i32)
> -DEF_HELPER_1(float_DT, f64, i32)
> -DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
> -DEF_HELPER_2(fmul_FT, f32, f32, f32)
> -DEF_HELPER_2(fmul_DT, f64, f64, f64)
> +DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
> +DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
> +DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
> +DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
> +DEF_HELPER_3(fdiv_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fdiv_DT, f64, env, f64, f64)
> +DEF_HELPER_2(float_FT, f32, env, i32)
> +DEF_HELPER_2(float_DT, f64, env, i32)
> +DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
> +DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
>  DEF_HELPER_1(fneg_T, f32, f32)
> -DEF_HELPER_2(fsub_FT, f32, f32, f32)
> -DEF_HELPER_2(fsub_DT, f64, f64, f64)
> -DEF_HELPER_1(fsqrt_FT, f32, f32)
> -DEF_HELPER_1(fsqrt_DT, f64, f64)
> -DEF_HELPER_1(ftrc_FT, i32, f32)
> -DEF_HELPER_1(ftrc_DT, i32, f64)
> -DEF_HELPER_2(fipr, void, i32, i32)
> -DEF_HELPER_1(ftrv, void, i32)
> +DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
> +DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
> +DEF_

[Qemu-devel] [PATCH] tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0

[Aurelien Jarno]

The load/store slow path has been broken in e141ab52d:
- We need to move 4 registers for store functions and 3 registers for
  load functions and not the reverse.
- According to the s390x calling convention the arguments of a function
  should be zero extended. This means that the register shift should be
  done with TCG_TYPE_I64 to ensure the higher word is correctly zero
  extended when needed.

I am aware that CONFIG_TCG_PASS_AREG0 is being removed and thus that
this patch can be improved, but doing so means it can also be applied to
the 1.1 and 1.2 stable branches.

Cc: qemu-sta...@nongnu.org
Cc: Alexander Graf 
Cc: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 tcg/s390/tcg-target.c |   14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 04662c1..99b5339 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -1509,11 +1509,13 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg 
data_reg,
 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
 #ifdef CONFIG_TCG_PASS_AREG0
 /* XXX/FIXME: suboptimal */
-tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
+tcg_target_call_iarg_regs[2]);
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
 tcg_target_call_iarg_regs[1]);
-tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
 tcg_target_call_iarg_regs[0]);
-tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
 TCG_AREG0);
 #endif
 tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
@@ -1521,13 +1523,11 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg 
data_reg,
 tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
 #ifdef CONFIG_TCG_PASS_AREG0
 /* XXX/FIXME: suboptimal */
-tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
-tcg_target_call_iarg_regs[2]);
 tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
 tcg_target_call_iarg_regs[1]);
-tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1],
 tcg_target_call_iarg_regs[0]);
-tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
+tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
 TCG_AREG0);
 #endif
 tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
-- 
1.7.10.4

[Qemu-devel] [PATCH 10/12] sun/sun4u: use the new pci_vga_init() function

[Aurelien Jarno]

As a bonus it allows new vga card types (including none).

Cc: Blue Swirl 
Signed-off-by: Aurelien Jarno 
---
 hw/sun4u.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/sun4u.c b/hw/sun4u.c
index cca090f..137a7c6 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -39,7 +39,6 @@
 #include "elf.h"
 #include "blockdev.h"
 #include "exec-memory.h"
-#include "vga-pci.h"
 
 //#define DEBUG_IRQ
 //#define DEBUG_EBUS
@@ -821,7 +820,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, 
&pci_bus2,
&pci_bus3, &pbm_irqs);
-pci_std_vga_init(pci_bus);
+pci_vga_init(pci_bus);
 
 // XXX Should be pci_bus3
 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 08/12] ppc/prep: use the new pci_vga_init() function

[Andreas Färber]

Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> As a bonus it allows new vga card types (including none).
> 
> Cc: Andreas Färber 
> Signed-off-by: Aurelien Jarno 

Acked-by: Andreas Färber 

/-F

[Qemu-devel] [PATCH v2 10/14] target-cris: Avoid AREG0 for helpers

[Blue Swirl]

From: Aurelien Jarno 

Add an explicit CPUCRISState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl 
Signed-off-by: Aurelien Jarno 
---
 target-cris/helper.h|   37 +++-
 target-cris/op_helper.c |   80 +++
 target-cris/translate.c |   44 ---
 target-cris/translate_v10.c |4 +-
 4 files changed, 88 insertions(+), 77 deletions(-)

diff --git a/target-cris/helper.h b/target-cris/helper.h
index 093063a..99fb326 100644
--- a/target-cris/helper.h
+++ b/target-cris/helper.h
@@ -1,26 +1,29 @@
 #include "def-helper.h"
 
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_1(tlb_flush_pid, void, i32)
-DEF_HELPER_1(spc_write, void, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_2(tlb_flush_pid, void, env, i32)
+DEF_HELPER_2(spc_write, void, env, i32)
 DEF_HELPER_3(dump, void, i32, i32, i32)
-DEF_HELPER_0(rfe, void);
-DEF_HELPER_0(rfn, void);
+DEF_HELPER_1(rfe, void, env);
+DEF_HELPER_1(rfn, void, env);
 
-DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
-DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
+DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
+DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
 
 DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
-DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
+DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
 
-DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, 
i32)
-DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, 
i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
-DEF_HELPER_0(evaluate_flags, void)
-DEF_HELPER_0(top_evaluate_flags, void)
+DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env,
+  i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env,
+i32, i32, i32, i32)
+DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env,
+i32, i32, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
+DEF_HELPER_1(evaluate_flags, void, env)
+DEF_HELPER_1(top_evaluate_flags, void, env)
 
 #include "def-helper.h"
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index ac7c98c..5ca85a0 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -79,7 +79,7 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 cpu_restore_state(tb, env, retaddr);
 
/* Evaluate flags after retranslation.  */
-helper_top_evaluate_flags();
+helper_top_evaluate_flags(env);
 }
 }
 cpu_loop_exit(env);
@@ -89,13 +89,13 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 
 #endif
 
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPUCRISState *env, uint32_t index)
 {
env->exception_index = index;
 cpu_loop_exit(env);
 }
 
-void helper_tlb_flush_pid(uint32_t pid)
+void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
 {
 #if !defined(CONFIG_USER_ONLY)
pid &= 0xff;
@@ -104,7 +104,7 @@ void helper_tlb_flush_pid(uint32_t pid)
 #endif
 }
 
-void helper_spc_write(uint32_t new_spc)
+void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
 {
 #if !defined(CONFIG_USER_ONLY)
tlb_flush_page(env, env->pregs[PR_SPC]);
@@ -121,7 +121,7 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
 #define EXTRACT_FIELD(src, start, end) \
(((src) >> start) & ((1 << (end - start + 1)) - 1))
 
-void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
+void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
 {
uint32_t srs;
srs = env->pregs[PR_SRS];
@@ -171,7 +171,7 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
 #endif
 }
 
-void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
+void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
 {
uint32_t srs;
env->pregs[PR_SRS] &= 3;
@@ -216,7 +216,7 @@ static void cris_ccs_rshift(CPUCRISState *env)
env->pregs[PR_CCS] = ccs;
 }
 
-void helper_rfe(void)
+void helper_rfe(CPUCRISState *env)
 {
int rflag = env->pregs[PR_CCS] & R_FLAG;
 
@@ -232,

[Qemu-devel] [PATCH 04/12] mips/malta: use the new pci_vga_init() function

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno 
---
 hw/mips_malta.c |   10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index c39dee5..632b466 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -33,7 +33,6 @@
 #include "mips.h"
 #include "mips_cpudevs.h"
 #include "pci.h"
-#include "vmware_vga.h"
 #include "qemu-char.h"
 #include "sysemu.h"
 #include "arch_init.h"
@@ -48,7 +47,6 @@
 #include "blockdev.h"
 #include "exec-memory.h"
 #include "sysbus.h" /* SysBusDevice */
-#include "vga-pci.h"
 
 //#define DEBUG_BOARD_INIT
 
@@ -987,13 +985,7 @@ void mips_malta_init (ram_addr_t ram_size,
 network_init();
 
 /* Optional PCI video card */
-if (cirrus_vga_enabled) {
-pci_cirrus_vga_init(pci_bus);
-} else if (vmsvga_enabled) {
-pci_vmsvga_init(pci_bus);
-} else if (std_vga_enabled) {
-pci_std_vga_init(pci_bus);
-}
+pci_vga_init(pci_bus);
 }
 
 static int mips_malta_sysbus_device_init(SysBusDevice *sysbusdev)
-- 
1.7.10.4

[Qemu-devel] [PATCH 12/12] vga: cleanup after pci_vga_init() conversion

[Aurelien Jarno]

Now that all machines call pci_vga_init(), some unused code can be
removed.

Cc: Anthony Liguori 
Signed-off-by: Aurelien Jarno 
---
 hw/cirrus_vga.c |6 --
 hw/vga-pci.c|6 --
 hw/vga-pci.h|   12 
 hw/vmware_vga.c |1 -
 hw/vmware_vga.h |   15 ---
 sysemu.h|4 
 6 files changed, 44 deletions(-)
 delete mode 100644 hw/vga-pci.h
 delete mode 100644 hw/vmware_vga.h

diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index e8dcc6b..5d1d42f 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -28,7 +28,6 @@
  */
 #include "hw.h"
 #include "pci.h"
-#include "vga-pci.h"
 #include "console.h"
 #include "vga_int.h"
 #include "loader.h"
@@ -2963,11 +2962,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
  return 0;
 }
 
-DeviceState *pci_cirrus_vga_init(PCIBus *bus)
-{
-return &pci_create_simple(bus, -1, "cirrus-vga")->qdev;
-}
-
 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 992ffd9..996d47f 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -24,7 +24,6 @@
 #include "hw.h"
 #include "console.h"
 #include "pci.h"
-#include "vga-pci.h"
 #include "vga_int.h"
 #include "pixel_ops.h"
 #include "qemu-timer.h"
@@ -70,11 +69,6 @@ static int pci_std_vga_initfn(PCIDevice *dev)
  return 0;
 }
 
-DeviceState *pci_std_vga_init(PCIBus *bus)
-{
-return &pci_create_simple(bus, -1, "VGA")->qdev;
-}
-
 static Property vga_pci_properties[] = {
 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/vga-pci.h b/hw/vga-pci.h
deleted file mode 100644
index d111cdc..000
--- a/hw/vga-pci.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef VGA_PCI_H
-#define VGA_PCI_H
-
-#include "qemu-common.h"
-
-/* vga-pci.c */
-DeviceState *pci_std_vga_init(PCIBus *bus);
-
-/* cirrus_vga.c */
-DeviceState *pci_cirrus_vga_init(PCIBus *bus);
-
-#endif
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index f5e4f44..5796d89 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -25,7 +25,6 @@
 #include "loader.h"
 #include "console.h"
 #include "pci.h"
-#include "vmware_vga.h"
 
 #undef VERBOSE
 #define HW_RECT_ACCEL
diff --git a/hw/vmware_vga.h b/hw/vmware_vga.h
deleted file mode 100644
index 000fbdd..000
--- a/hw/vmware_vga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef QEMU_VMWARE_VGA_H
-#define QEMU_VMWARE_VGA_H
-
-#include "qemu-common.h"
-
-/* vmware_vga.c */
-static inline DeviceState *pci_vmsvga_init(PCIBus *bus)
-{
-PCIDevice *dev;
-
-dev = pci_create_simple(bus, -1, "vmware-svga");
-return &dev->qdev;
-}
-
-#endif
diff --git a/sysemu.h b/sysemu.h
index 65552ac..0587b38 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -105,11 +105,7 @@ typedef enum {
 } VGAInterfaceType;
 
 extern int vga_interface_type;
-#define cirrus_vga_enabled (vga_interface_type == VGA_CIRRUS)
-#define std_vga_enabled (vga_interface_type == VGA_STD)
 #define xenfb_enabled (vga_interface_type == VGA_XENFB)
-#define vmsvga_enabled (vga_interface_type == VGA_VMWARE)
-#define qxl_enabled (vga_interface_type == VGA_QXL)
 
 extern int graphic_width;
 extern int graphic_height;
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 11/14] target-cris: Switch to AREG0 free mode

[Blue Swirl]

From: Aurelien Jarno 

Add an explicit CPUCRISState parameter instead of relying on AREG0, and
use cpu_ld* in translation and interrupt handling. Remove AREG0 swapping
in tlb_fill(). Switch to AREG0 free mode

Signed-off-by: Blue Swirl 
Signed-off-by: Aurelien Jarno 
---
 configure   |2 +-
 target-cris/Makefile.objs   |2 -
 target-cris/helper.c|4 +-
 target-cris/op_helper.c |9 +--
 target-cris/translate.c |  256 +-
 target-cris/translate_v10.c |   95 
 6 files changed, 181 insertions(+), 187 deletions(-)

diff --git a/configure b/configure
index e464d2f..d760e07 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | 
unicore32 | x86_64 | xtensa* | ppc*)
+  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
sparc* | unicore32 | x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
index 4b09e8c..afb87bc 100644
--- a/target-cris/Makefile.objs
+++ b/target-cris/Makefile.objs
@@ -1,4 +1,2 @@
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index bfbc29e..1bdb7e2 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
}
 
/* Now that we are in kernel mode, load the handlers address.  */
-   env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
env->locked_irq = 1;
env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 
@@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
/* Now that we are in kernel mode, load the handlers address.
   This load may not fault, real hw leaves that behaviour as
   undefined.  */
-   env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 
/* Clear the excption_index to avoid spurios hw_aborts for recursive
   bus faults.  */
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 5ca85a0..a7468d4 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -19,7 +19,6 @@
  */
 
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "mmu.h"
 #include "helper.h"
 #include "host-utils.h"
@@ -55,17 +54,12 @@
 /* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
   uintptr_t retaddr)
 {
 TranslationBlock *tb;
-CPUCRISState *saved_env;
 int ret;
 
-saved_env = env;
-env = env1;
-
 D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
   env->pc, env->debug1, (void *)retaddr);
 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
@@ -84,7 +78,6 @@ void tlb_fill(CPUCRISState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 }
 cpu_loop_exit(env);
 }
-env = saved_env;
 }
 
 #endif
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 283dd98..19144b5 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -78,7 +78,7 @@ typedef struct DisasContext {
target_ulong pc, ppc;
 
/* Decoder.  */
-   unsigned int (*decoder)(struct DisasContext *dc);
+unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
uint32_t ir;
uint32_t opcode;
unsigned int op1;
@@ -233,7 +233,7 @@ static int sign_extend(unsigned int val, unsigned int width)
return sval;
 }
 
-static int cris_fetch(DisasContext *dc, uint32_t addr,
+static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
  unsigned int size, unsigned int sign)
 {
int r;
@@ -241,24 +241,24 @@ static int cris_fetch(DisasContext *dc, uint32_t addr,
switch (size) {
case 4:
{
-   r = ldl_code(addr);
+r = cpu_ldl_code(env, addr);
break;
}
case 2:
{
if (sign) {
-   r = ldsw_code(addr);
+r = cpu_ldsw_code(env, addr);
} else {
-   r = lduw_code(addr);
+   

Re: [Qemu-devel] [PATCH 02/12] vl.c: check for qxl availability

[Andreas Färber]

Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> Check for qxl availability in vl.c. This will allow to remove #ifdef
> CONFIG_SPICE .. #endif later in this series
> 
> Cc: Anthony Liguori 
> Cc: Gerd Hoffmann 
> Signed-off-by: Aurelien Jarno 
> ---
>  vl.c |   12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/vl.c b/vl.c
> index 7c577fa..6363915 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -1703,6 +1703,11 @@ static bool vmware_vga_available(void)
>  return qdev_exists("vmware-svga");
>  }
>  
> +static bool qxl_vga_available(void)
> +{
> +return qdev_exists("qxl-vga");

I'd suggest to use the QOM equivalent:

object_class_by_name("qxl-vga")

Andreas

> +}
> +
>  static void select_vgahw (const char *p)
>  {
>  const char *opts;
> @@ -1732,7 +1737,12 @@ static void select_vgahw (const char *p)
>  } else if (strstart(p, "xenfb", &opts)) {
>  vga_interface_type = VGA_XENFB;
>  } else if (strstart(p, "qxl", &opts)) {
> -vga_interface_type = VGA_QXL;
> +if (qxl_vga_available()) {
> +vga_interface_type = VGA_QXL;
> +} else {
> +fprintf(stderr, "Error: QXL VGA not available\n");
> +exit(0);
> +}
>  } else if (!strstart(p, "none", &opts)) {
>  invalid_vga:
>  fprintf(stderr, "Unknown vga type: %s\n", p);
> 


-- 
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GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

[Qemu-devel] [PATCH v2 05/14] target-unicore32: switch to AREG0 free mode

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Tested-by: Guan Xuetao 
Signed-off-by: Blue Swirl 
---
 configure  |2 +-
 target-unicore32/Makefile.objs |2 -
 target-unicore32/helper.h  |   26 
 target-unicore32/op_helper.c   |   65 +++
 target-unicore32/translate.c   |   38 +++---
 5 files changed, 58 insertions(+), 75 deletions(-)

diff --git a/configure b/configure
index 350b47c..4fd3b7f 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+  alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | 
xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 777f01f..8e143da 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -2,5 +2,3 @@ obj-y += translate.o op_helper.o helper.o cpu.o
 obj-y += ucf64_helper.o
 
 obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
index 305318a..a4b8149 100644
--- a/target-unicore32/helper.h
+++ b/target-unicore32/helper.h
@@ -17,26 +17,26 @@ DEF_HELPER_1(cp1_putc, void, i32)
 DEF_HELPER_1(clz, i32, i32)
 DEF_HELPER_1(clo, i32, i32)
 
-DEF_HELPER_1(exception, void, i32)
+DEF_HELPER_2(exception, void, env, i32)
 
-DEF_HELPER_2(asr_write, void, i32, i32)
-DEF_HELPER_0(asr_read, i32)
+DEF_HELPER_3(asr_write, void, env, i32, i32)
+DEF_HELPER_1(asr_read, i32, env)
 
-DEF_HELPER_1(get_user_reg, i32, i32)
-DEF_HELPER_2(set_user_reg, void, i32, i32)
+DEF_HELPER_2(get_user_reg, i32, env, i32)
+DEF_HELPER_3(set_user_reg, void, env, i32, i32)
 
-DEF_HELPER_2(add_cc, i32, i32, i32)
-DEF_HELPER_2(adc_cc, i32, i32, i32)
-DEF_HELPER_2(sub_cc, i32, i32, i32)
-DEF_HELPER_2(sbc_cc, i32, i32, i32)
+DEF_HELPER_3(add_cc, i32, env, i32, i32)
+DEF_HELPER_3(adc_cc, i32, env, i32, i32)
+DEF_HELPER_3(sub_cc, i32, env, i32, i32)
+DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
 
 DEF_HELPER_2(shl, i32, i32, i32)
 DEF_HELPER_2(shr, i32, i32, i32)
 DEF_HELPER_2(sar, i32, i32, i32)
-DEF_HELPER_2(shl_cc, i32, i32, i32)
-DEF_HELPER_2(shr_cc, i32, i32, i32)
-DEF_HELPER_2(sar_cc, i32, i32, i32)
-DEF_HELPER_2(ror_cc, i32, i32, i32)
+DEF_HELPER_3(shl_cc, i32, env, i32, i32)
+DEF_HELPER_3(shr_cc, i32, env, i32, i32)
+DEF_HELPER_3(sar_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror_cc, i32, env, i32, i32)
 
 DEF_HELPER_1(ucf64_get_fpscr, i32, env)
 DEF_HELPER_2(ucf64_set_fpscr, void, env, i32)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index c63789d..f474d1b 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -9,19 +9,18 @@
  * later version. See the COPYING file in the top-level directory.
  */
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helper.h"
 
 #define SIGNBIT (uint32_t)0x8000
 #define SIGNBIT64 ((uint64_t)1 << 63)
 
-void HELPER(exception)(uint32_t excp)
+void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
 {
 env->exception_index = excp;
 cpu_loop_exit(env);
 }
 
-static target_ulong asr_read(void)
+static target_ulong asr_read(CPUUniCore32State *env)
 {
 int ZF;
 ZF = (env->ZF == 0);
@@ -29,24 +28,18 @@ static target_ulong asr_read(void)
 (env->CF << 29) | ((env->VF & 0x8000) >> 3);
 }
 
-target_ulong cpu_asr_read(CPUUniCore32State *env1)
+target_ulong cpu_asr_read(CPUUniCore32State *env)
 {
-CPUUniCore32State *saved_env;
-target_ulong ret;
-
-saved_env = env;
-env = env1;
-ret = asr_read();
-env = saved_env;
-return ret;
+return asr_read(env);
 }
 
-target_ulong HELPER(asr_read)(void)
+target_ulong HELPER(asr_read)(CPUUniCore32State *env)
 {
-return asr_read();
+return asr_read(env);
 }
 
-static void asr_write(target_ulong val, target_ulong mask)
+static void asr_write(CPUUniCore32State *env, target_ulong val,
+  target_ulong mask)
 {
 if (mask & ASR_NZCV) {
 env->ZF = (~val) & ASR_Z;
@@ -62,23 +55,19 @@ static void asr_write(target_ulong val, target_ulong mask)
 env->uncached_asr = (env->uncached_asr & ~mask) | (val & mask);
 }
 
-void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong 
mask)
+void cpu_asr_write(CPUUniCore32State *env, target_ulong val, target_ulong mask)
 {
-CPUUniCore32State *saved_env;
-
-saved_env = env;
-env = env1;
-asr_write(val, mask);
-env = saved_env;
+asr_write(env, val, mask);
 }
 
-void HELPER(asr_write)(target_ulong val, target_ulong mask)
+void HELPER(asr_write)(CPUUniCore32State *env, target_ulong val,
+   target_ulong mask)
 {
-asr_wri

[Qemu-devel] [PATCH v2 04/14] target-m68k: avoid using cpu_single_env

[Blue Swirl]

Pass around CPUState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
---
 target-m68k/translate.c |  270 ---
 1 files changed, 140 insertions(+), 130 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 10bb303..fb707f2 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -150,18 +150,24 @@ static void *gen_throws_exception;
 #define OS_SINGLE 4
 #define OS_DOUBLE 5
 
-typedef void (*disas_proc)(DisasContext *, uint16_t);
+typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
 
 #ifdef DEBUG_DISPATCH
-#define DISAS_INSN(name) \
-  static void real_disas_##name (DisasContext *s, uint16_t insn); \
-  static void disas_##name (DisasContext *s, uint16_t insn) { \
-qemu_log("Dispatch " #name "\n"); \
-real_disas_##name(s, insn); } \
-  static void real_disas_##name (DisasContext *s, uint16_t insn)
+#define DISAS_INSN(name)\
+static void real_disas_##name(CPUM68KState *env, DisasContext *s,   \
+  uint16_t insn);   \
+static void disas_##name(CPUM68KState *env, DisasContext *s,\
+ uint16_t insn) \
+{   \
+qemu_log("Dispatch " #name "\n");   \
+real_disas_##name(s, env, insn);\
+}   \
+static void real_disas_##name(CPUM68KState *env, DisasContext *s,   \
+  uint16_t insn)
 #else
-#define DISAS_INSN(name) \
-  static void disas_##name (DisasContext *s, uint16_t insn)
+#define DISAS_INSN(name)\
+static void disas_##name(CPUM68KState *env, DisasContext *s,\
+ uint16_t insn)
 #endif
 
 /* Generate a load from the specified address.  Narrow values are
@@ -257,12 +263,12 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv 
addr, TCGv val,
 }
 
 /* Read a 32-bit immediate constant.  */
-static inline uint32_t read_im32(DisasContext *s)
+static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
 {
 uint32_t im;
-im = ((uint32_t)cpu_lduw_code(cpu_single_env, s->pc)) << 16;
+im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
 s->pc += 2;
-im |= cpu_lduw_code(cpu_single_env, s->pc);
+im |= cpu_lduw_code(env, s->pc);
 s->pc += 2;
 return im;
 }
@@ -288,7 +294,8 @@ static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
 
 /* Handle a base + index + displacement effective addresss.
A NULL_QREG base means pc-relative.  */
-static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
+static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
+TCGv base)
 {
 uint32_t offset;
 uint16_t ext;
@@ -297,7 +304,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, 
TCGv base)
 uint32_t bd, od;
 
 offset = s->pc;
-ext = cpu_lduw_code(cpu_single_env, s->pc);
+ext = cpu_lduw_code(env, s->pc);
 s->pc += 2;
 
 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
@@ -311,10 +318,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, 
TCGv base)
 if ((ext & 0x30) > 0x10) {
 /* base displacement */
 if ((ext & 0x30) == 0x20) {
-bd = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
+bd = (int16_t)cpu_lduw_code(env, s->pc);
 s->pc += 2;
 } else {
-bd = read_im32(s);
+bd = read_im32(env, s);
 }
 } else {
 bd = 0;
@@ -360,10 +367,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, 
TCGv base)
 if ((ext & 3) > 1) {
 /* outer displacement */
 if ((ext & 3) == 2) {
-od = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
+od = (int16_t)cpu_lduw_code(env, s->pc);
 s->pc += 2;
 } else {
-od = read_im32(s);
+od = read_im32(env, s);
 }
 } else {
 od = 0;
@@ -492,7 +499,8 @@ static inline TCGv gen_extend(TCGv val, int opsize, int 
sign)
 
 /* Generate code for an "effective address".  Does not adjust the base
register for autoincrement addressing modes.  */
-static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
+static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
+int opsize)
 {
 TCGv reg;
 TCGv tmp;
@@ -514,29 +522,29 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int 
opsize)
 case 5: /* Indirect displacement.  */

[Qemu-devel] [PATCH 09/12] ppc/pSeries: use the new pci_vga_init() function

[Aurelien Jarno]

Keep the case to prevent some vga card to be selected.

Cc: Alexander Graf 
Cc: David Gibson 
Signed-off-by: Aurelien Jarno 
---
 hw/spapr.c |7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/spapr.c b/hw/spapr.c
index 80735d6..8b0c390 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -46,7 +46,6 @@
 #include "kvm.h"
 #include "kvm_ppc.h"
 #include "pci.h"
-#include "vga-pci.h"
 
 #include "exec-memory.h"
 #include "hw/usb.h"
@@ -589,11 +588,9 @@ static void spapr_cpu_reset(void *opaque)
 static int spapr_vga_init(PCIBus *pci_bus)
 {
 switch (vga_interface_type) {
-case VGA_STD:
-pci_std_vga_init(pci_bus);
-return 1;
 case VGA_NONE:
-return 0;
+case VGA_STD:
+return pci_vga_init(pci_bus) != NULL;
 default:
 fprintf(stderr, "This vga model is not supported,"
 "currently it only supports -vga std\n");
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 11/12] pc: use the new pci_vga_init() function

[Blue Swirl]

On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno  wrote:
> The CONFIG_SPICE is now tested in vl.c and thus not needed anymore. The
> various tests are still needed for the ISA cases.
>
> Cc: Anthony Liguori 
> Signed-off-by: Aurelien Jarno 
> ---
>  hw/pc.c |   41 +++--
>  1 file changed, 15 insertions(+), 26 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 8736a30..8cdbd9e 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -27,7 +27,6 @@
>  #include "fdc.h"
>  #include "ide.h"
>  #include "pci.h"
> -#include "vmware_vga.h"
>  #include "monitor.h"
>  #include "fw_cfg.h"
>  #include "hpet_emul.h"
> @@ -51,7 +50,6 @@
>  #include "exec-memory.h"
>  #include "arch_init.h"
>  #include "bitmap.h"
> -#include "vga-pci.h"
>
>  /* output Bochs bios info messages */
>  //#define DEBUG_BIOS
> @@ -1019,34 +1017,25 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus 
> *pci_bus)
>  {
>  DeviceState *dev = NULL;
>
> -if (cirrus_vga_enabled) {
> -if (pci_bus) {
> -dev = pci_cirrus_vga_init(pci_bus);
> -} else {
> +if (pci_bus) {
> +PCIDevice *pcidev = pci_vga_init(pci_bus);
> +dev = pcidev ? &pcidev->qdev : NULL;
> +} else {
> +switch (vga_interface_type) {
> +case VGA_CIRRUS:
>  dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
> -}
> -} else if (vmsvga_enabled) {
> -if (pci_bus) {
> -dev = pci_vmsvga_init(pci_bus);
> -} else {
> -fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
> -}
> -#ifdef CONFIG_SPICE
> -} else if (qxl_enabled) {
> -if (pci_bus) {
> -dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
> -} else {
> -fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
> -}
> -#endif
> -} else if (std_vga_enabled) {
> -if (pci_bus) {
> -dev = pci_std_vga_init(pci_bus);
> -} else {
> +break;
> +case VGA_QXL:
> +fprintf(stderr, "%s: qxl: no PCI bus\n", __func__);
> +break;
> +case VGA_STD:
>  dev = isa_vga_init(isa_bus);
> +break;
> +case VGA_VMWARE:
> +fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __func__);
> +break;

Please move this to isa.[ch] (like PCI case), so other ISA bus users
(actually just MIPS r4k) benefit also.

>  }
>  }
> -
>  return dev;
>  }
>
> --
> 1.7.10.4
>
>

Re: [Qemu-devel] [PATCH 01/12] vga: rename pci_vga_init() into pci_std_vga_init()

[Andreas Färber]

Am 08.09.2012 13:26, schrieb Aurelien Jarno:
> This better explains what is this function about. Adjust all callers.
> 
> Cc: Richard Henderson 
> Cc: Alexander Graf 
> Cc: Andreas Färber 
> Cc: David Gibson 
> Cc: Blue Swirl 
> Cc: Anthony Liguori 
> Signed-off-by: Aurelien Jarno 

Looks fine,

Acked-by: Andreas Färber 

Andreas

Re: [Qemu-devel] [PATCH 01/12] vga: rename pci_vga_init() into pci_std_vga_init()

[Blue Swirl]

On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno  wrote:
> This better explains what is this function about. Adjust all callers.
>
> Cc: Richard Henderson 
> Cc: Alexander Graf 
> Cc: Andreas Färber 
> Cc: David Gibson 
> Cc: Blue Swirl 

Acked-by: Blue Swirl 

> Cc: Anthony Liguori 
> Signed-off-by: Aurelien Jarno 
> ---
>  hw/alpha_pci.c|2 +-
>  hw/mips_malta.c   |2 +-
>  hw/pc.c   |2 +-
>  hw/ppc_newworld.c |2 +-
>  hw/ppc_oldworld.c |2 +-
>  hw/ppc_prep.c |2 +-
>  hw/spapr.c|2 +-
>  hw/sun4u.c|2 +-
>  hw/vga-pci.c  |6 +++---
>  hw/vga-pci.h  |2 +-
>  10 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
> index ea546f8..0352e72 100644
> --- a/hw/alpha_pci.c
> +++ b/hw/alpha_pci.c
> @@ -128,6 +128,6 @@ void alpha_pci_vga_setup(PCIBus *pci_bus)
>  /* If VGA is enabled at all, and one of the above didn't work, then
> fallback to Standard VGA.  */
>  if (vga_interface_type != VGA_NONE) {
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>  }
>  }
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index ad23f26..c39dee5 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -992,7 +992,7 @@ void mips_malta_init (ram_addr_t ram_size,
>  } else if (vmsvga_enabled) {
>  pci_vmsvga_init(pci_bus);
>  } else if (std_vga_enabled) {
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>  }
>  }
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 112739a..8736a30 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1041,7 +1041,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus 
> *pci_bus)
>  #endif
>  } else if (std_vga_enabled) {
>  if (pci_bus) {
> -dev = pci_vga_init(pci_bus);
> +dev = pci_std_vga_init(pci_bus);
>  } else {
>  dev = isa_vga_init(isa_bus);
>  }
> diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
> index e95cfe8..84af948 100644
> --- a/hw/ppc_newworld.c
> +++ b/hw/ppc_newworld.c
> @@ -330,7 +330,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
>  machine_arch = ARCH_MAC99;
>  }
>  /* init basic PC hardware */
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>
>  escc_mem = escc_init(0, pic[0x25], pic[0x24],
>   serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
> diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
> index 1dcd8a6..8267eb4 100644
> --- a/hw/ppc_oldworld.c
> +++ b/hw/ppc_oldworld.c
> @@ -250,7 +250,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
>  pci_bus = pci_grackle_init(0xfec0, pic,
> get_system_memory(),
> get_system_io());
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>
>  escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
> serial_hds[1], ESCC_CLOCK, 4);
> diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
> index 592b7b2..1fa7609 100644
> --- a/hw/ppc_prep.c
> +++ b/hw/ppc_prep.c
> @@ -611,7 +611,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
>  memory_region_add_subregion(sysmem, 0x8000, PPC_io_memory);
>
>  /* init basic PC hardware */
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>
>  if (serial_hds[0])
>  serial_isa_init(isa_bus, 0, serial_hds[0]);
> diff --git a/hw/spapr.c b/hw/spapr.c
> index c34b767..80735d6 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -590,7 +590,7 @@ static int spapr_vga_init(PCIBus *pci_bus)
>  {
>  switch (vga_interface_type) {
>  case VGA_STD:
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>  return 1;
>  case VGA_NONE:
>  return 0;
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index 07cd042..cca090f 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -821,7 +821,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>  ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
>  pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, 
> &pci_bus2,
> &pci_bus3, &pbm_irqs);
> -pci_vga_init(pci_bus);
> +pci_std_vga_init(pci_bus);
>
>  // XXX Should be pci_bus3
>  isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
> diff --git a/hw/vga-pci.c b/hw/vga-pci.c
> index 9abbada..992ffd9 100644
> --- a/hw/vga-pci.c
> +++ b/hw/vga-pci.c
> @@ -47,7 +47,7 @@ static const VMStateDescription vmstate_vga_pci = {
>  }
>  };
>
> -static int pci_vga_initfn(PCIDevice *dev)
> +static int pci_std_vga_initfn(PCIDevice *dev)
>  {
>   PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
>   VGACommonState *s = &d->vga;
> @@ -70,7 +70,7 @@ static int pci_vga_initfn(PCIDevice *dev)
>   return 0;
>  }
>
> -DeviceState *pci_vga_init(PCIBus *bus)
> +DeviceState *pci_std_vga_init(PCIBus *bus)
>  {
>  return &pci_create_simple(bus, -1, "VG

Re: [Qemu-devel] [PATCH 10/12] sun/sun4u: use the new pci_vga_init() function

[Blue Swirl]

On Sat, Sep 8, 2012 at 11:26 AM, Aurelien Jarno  wrote:
> As a bonus it allows new vga card types (including none).
>
> Cc: Blue Swirl 

Acked-by: Blue Swirl 

> Signed-off-by: Aurelien Jarno 
> ---
>  hw/sun4u.c |3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index cca090f..137a7c6 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -39,7 +39,6 @@
>  #include "elf.h"
>  #include "blockdev.h"
>  #include "exec-memory.h"
> -#include "vga-pci.h"
>
>  //#define DEBUG_IRQ
>  //#define DEBUG_EBUS
> @@ -821,7 +820,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
>  ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
>  pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, 
> &pci_bus2,
> &pci_bus3, &pbm_irqs);
> -pci_std_vga_init(pci_bus);
> +pci_vga_init(pci_bus);
>
>  // XXX Should be pci_bus3
>  isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
> --
> 1.7.10.4
>

[Qemu-devel] [PATCH v2 03/14] target-m68k: switch to AREG0 free mode

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl 
---
 configure |2 +-
 target-m68k/Makefile.objs |2 -
 target-m68k/helpers.h |2 +-
 target-m68k/op_helper.c   |   68 
 target-m68k/translate.c   |   76 +++--
 5 files changed, 68 insertions(+), 82 deletions(-)

diff --git a/configure b/configure
index 9261f68..350b47c 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | i386 | lm32 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+  alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-m68k/Makefile.objs b/target-m68k/Makefile.objs
index cda6015..7eccfab 100644
--- a/target-m68k/Makefile.objs
+++ b/target-m68k/Makefile.objs
@@ -1,5 +1,3 @@
 obj-y += m68k-semi.o
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index cb8a0c7..8112b44 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -49,6 +49,6 @@ DEF_HELPER_3(set_mac_exts, void, env, i32, i32)
 DEF_HELPER_3(set_mac_extu, void, env, i32, i32)
 
 DEF_HELPER_2(flush_flags, void, env, i32)
-DEF_HELPER_1(raise_exception, void, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
 
 #include "def-helper.h"
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 1971a57..3116287 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -17,17 +17,16 @@
  * License along with this library; if not, see .
  */
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helpers.h"
 
 #if defined(CONFIG_USER_ONLY)
 
-void do_interrupt(CPUM68KState *env1)
+void do_interrupt(CPUM68KState *env)
 {
-env1->exception_index = -1;
+env->exception_index = -1;
 }
 
-void do_interrupt_m68k_hardirq(CPUM68KState *env1)
+void do_interrupt_m68k_hardirq(CPUM68KState *env)
 {
 }
 
@@ -54,16 +53,12 @@ extern int semihosting_enabled;
 /* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUM68KState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
   uintptr_t retaddr)
 {
 TranslationBlock *tb;
-CPUM68KState *saved_env;
 int ret;
 
-saved_env = env;
-env = env1;
 ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
 if (unlikely(ret)) {
 if (retaddr) {
@@ -77,24 +72,23 @@ void tlb_fill(CPUM68KState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 }
 cpu_loop_exit(env);
 }
-env = saved_env;
 }
 
-static void do_rte(void)
+static void do_rte(CPUM68KState *env)
 {
 uint32_t sp;
 uint32_t fmt;
 
 sp = env->aregs[7];
-fmt = ldl_kernel(sp);
-env->pc = ldl_kernel(sp + 4);
+fmt = cpu_ldl_kernel(env, sp);
+env->pc = cpu_ldl_kernel(env, sp + 4);
 sp |= (fmt >> 28) & 3;
 env->sr = fmt & 0x;
 m68k_switch_sp(env);
 env->aregs[7] = sp + 8;
 }
 
-static void do_interrupt_all(int is_hw)
+static void do_interrupt_all(CPUM68KState *env, int is_hw)
 {
 uint32_t sp;
 uint32_t fmt;
@@ -108,14 +102,14 @@ static void do_interrupt_all(int is_hw)
 switch (env->exception_index) {
 case EXCP_RTE:
 /* Return from an exception.  */
-do_rte();
+do_rte(env);
 return;
 case EXCP_HALT_INSN:
 if (semihosting_enabled
 && (env->sr & SR_S) != 0
 && (env->pc & 3) == 0
-&& lduw_code(env->pc - 4) == 0x4e71
-&& ldl_code(env->pc) == 0x4e7bf000) {
+&& cpu_lduw_code(env, env->pc - 4) == 0x4e71
+&& cpu_ldl_code(env, env->pc) == 0x4e7bf000) {
 env->pc += 4;
 do_m68k_semihosting(env, env->dregs[0]);
 return;
@@ -151,44 +145,34 @@ static void do_interrupt_all(int is_hw)
 /* ??? This could cause MMU faults.  */
 sp &= ~3;
 sp -= 4;
-stl_kernel(sp, retaddr);
+cpu_stl_kernel(env, sp, retaddr);
 sp -= 4;
-stl_kernel(sp, fmt);
+cpu_stl_kernel(env, sp, fmt);
 env->aregs[7] = sp;
 /* Jump to vector.  */
-env->pc = ldl_kernel(env->vbr + vector);
+env->pc = cpu_ldl_kernel(env, env->vbr + vector);
 }
 
-void do_interrupt(CPUM68KState *env1)
+void do_interrupt(CPUM68KState *env)
 {
-CPUM68KState *saved_env;
-
-sav

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Blue Swirl]

On Sat, Sep 8, 2012 at 12:13 PM, Alexander Graf  wrote:
>
>
> On 08.09.2012, at 12:16, Blue Swirl  wrote:
>
>> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf  wrote:
>>>
>>>
>>> On 08.09.2012, at 10:06, Blue Swirl  wrote:
>>>
 On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>
>> Reinventing a disassembler for ever growing x86 assembly is
>> no fun.
>
> We can try linking to a disassembler library.  I use udis86 to
> disassemble instructions in kvm tracepoints
> (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
> it's maintained but not heavily so.

 I think commonality with KVM would be preferred. The library looks
 neat and based on changelog, more actively developed than BSD DDB.

>
> Of course for non-x86 we'd need to continue using binutils; this is
> about copying code vs. libraries, not about licensing.

 For most architectures, pre-GPLv3 binutils is good enough since the
 instruction set does not change anymore. Maybe only PPC and Sparc64
 still change besides x86. New CPUs types more recent than 2007 will
 have problems.
>>>
>>> Alternatively we could try to run the disassembler in a different process, 
>>> right?
>>
>> For qemu.log this would be doable and even improve performance since
>> only binary data would be transferred.
>>
>> But for monitor disassembly command x/i it may be too clumsy.
>
> Why would it be clumsy? We'd have to make sure we are communicating 
> synchronously with the daemon, but apart from that it shouldn't be too 
> different from the log, no?

The log file should be written as binary which the disassembly tool
could read. The daemon would probably slow down execution back to
original speed since it would be writing ASCII, though this mode could
be supported too.

>
>> There's
>> some overlap with GDB support, so maybe we could deprecate monitor
>> disassembly.
>
> I really like the way the monitor goes through special v->p lookup, as it's a 
> lot easier to debug...

GDB could be taught new tricks, but that would not help users with old dogs.

>
> Alex
>
>>
>>>
>>> Alex
>>>

>
>
> --
> error compiling committee.c: too many arguments to function

[Qemu-devel] [PATCH v2 07/14] target-arm: convert remaining helpers

[Blue Swirl]

Convert remaining helpers to AREG0 free mode: add an explicit
CPUState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl 
Reviewed-by: Peter Maydell 
---
 target-arm/helper.h|   52 +-
 target-arm/op_helper.c |   64 +++---
 target-arm/translate.c |  134 
 3 files changed, 125 insertions(+), 125 deletions(-)

diff --git a/target-arm/helper.h b/target-arm/helper.h
index 106aacd..afdb2b5 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
 DEF_HELPER_1(sxtb16, i32, i32)
 DEF_HELPER_1(uxtb16, i32, i32)
 
-DEF_HELPER_2(add_setq, i32, i32, i32)
-DEF_HELPER_2(add_saturate, i32, i32, i32)
-DEF_HELPER_2(sub_saturate, i32, i32, i32)
-DEF_HELPER_2(add_usaturate, i32, i32, i32)
-DEF_HELPER_2(sub_usaturate, i32, i32, i32)
-DEF_HELPER_1(double_saturate, i32, s32)
+DEF_HELPER_3(add_setq, i32, env, i32, i32)
+DEF_HELPER_3(add_saturate, i32, env, i32, i32)
+DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
+DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
+DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
+DEF_HELPER_2(double_saturate, i32, env, s32)
 DEF_HELPER_2(sdiv, s32, s32, s32)
 DEF_HELPER_2(udiv, i32, i32, i32)
 DEF_HELPER_1(rbit, i32, i32)
@@ -40,10 +40,10 @@ PAS_OP(uq)
 PAS_OP(uh)
 #undef PAS_OP
 
-DEF_HELPER_2(ssat, i32, i32, i32)
-DEF_HELPER_2(usat, i32, i32, i32)
-DEF_HELPER_2(ssat16, i32, i32, i32)
-DEF_HELPER_2(usat16, i32, i32, i32)
+DEF_HELPER_3(ssat, i32, env, i32, i32)
+DEF_HELPER_3(usat, i32, env, i32, i32)
+DEF_HELPER_3(ssat16, i32, env, i32, i32)
+DEF_HELPER_3(usat16, i32, env, i32, i32)
 
 DEF_HELPER_2(usad8, i32, i32, i32)
 
@@ -54,7 +54,7 @@ DEF_HELPER_2(exception, void, env, i32)
 DEF_HELPER_1(wfi, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
-DEF_HELPER_0(cpsr_read, i32)
+DEF_HELPER_1(cpsr_read, i32, env)
 
 DEF_HELPER_3(v7m_msr, void, env, i32, i32)
 DEF_HELPER_2(v7m_mrs, i32, env, i32)
@@ -67,7 +67,7 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
 DEF_HELPER_2(get_r13_banked, i32, env, i32)
 DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
 
-DEF_HELPER_1(get_user_reg, i32, i32)
+DEF_HELPER_2(get_user_reg, i32, env, i32)
 DEF_HELPER_3(set_user_reg, void, env, i32, i32)
 
 DEF_HELPER_1(vfp_get_fpscr, i32, env)
@@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
 DEF_HELPER_2(rsqrte_f32, f32, f32, env)
 DEF_HELPER_2(recpe_u32, i32, i32, env)
 DEF_HELPER_2(rsqrte_u32, i32, i32, env)
-DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
-
-DEF_HELPER_2(add_cc, i32, i32, i32)
-DEF_HELPER_2(adc_cc, i32, i32, i32)
-DEF_HELPER_2(sub_cc, i32, i32, i32)
-DEF_HELPER_2(sbc_cc, i32, i32, i32)
-
-DEF_HELPER_2(shl, i32, i32, i32)
-DEF_HELPER_2(shr, i32, i32, i32)
-DEF_HELPER_2(sar, i32, i32, i32)
-DEF_HELPER_2(shl_cc, i32, i32, i32)
-DEF_HELPER_2(shr_cc, i32, i32, i32)
-DEF_HELPER_2(sar_cc, i32, i32, i32)
-DEF_HELPER_2(ror_cc, i32, i32, i32)
+DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
+
+DEF_HELPER_3(add_cc, i32, env, i32, i32)
+DEF_HELPER_3(adc_cc, i32, env, i32, i32)
+DEF_HELPER_3(sub_cc, i32, env, i32, i32)
+DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
+
+DEF_HELPER_3(shl, i32, env, i32, i32)
+DEF_HELPER_3(shr, i32, env, i32, i32)
+DEF_HELPER_3(sar, i32, env, i32, i32)
+DEF_HELPER_3(shl_cc, i32, env, i32, i32)
+DEF_HELPER_3(shr_cc, i32, env, i32, i32)
+DEF_HELPER_3(sar_cc, i32, env, i32, i32)
+DEF_HELPER_3(ror_cc, i32, env, i32, i32)
 
 /* neon_helper.c */
 DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index b1adce3..5b868bf 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -29,7 +29,7 @@ static void raise_exception(CPUARMState *env, int tt)
 cpu_loop_exit(env);
 }
 
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
+uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
   uint32_t rn, uint32_t maxindex)
 {
 uint32_t val;
@@ -101,7 +101,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 
 /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
instructions into helper.c  */
-uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 {
 uint32_t res = a + b;
 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
@@ -109,7 +109,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
 return res;
 }
 
-uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 {
 uint32_t res = a + b;
 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
@@ -119,7 +119,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
 return res;
 }
 
-uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
+uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 {
 uint32_t res = a - b;
 if (((res ^ a)

[Qemu-devel] [PATCH 06/12] ppc/newworld: use the new pci_vga_init() function

[Aurelien Jarno]

As a bonus it allows new vga card types (including none).

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 hw/ppc_newworld.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 84af948..b8d3c9c 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -67,7 +67,6 @@
 #include "hw/usb.h"
 #include "blockdev.h"
 #include "exec-memory.h"
-#include "vga-pci.h"
 
 #define MAX_IDE_BUS 2
 #define CFG_ADDR 0xf510
@@ -330,7 +329,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
 machine_arch = ARCH_MAC99;
 }
 /* init basic PC hardware */
-pci_std_vga_init(pci_bus);
+pci_vga_init(pci_bus);
 
 escc_mem = escc_init(0, pic[0x25], pic[0x24],
  serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 08/14] target-arm: final conversion to AREG0 free mode

[Blue Swirl]

Convert code load functions and switch to AREG0 free mode.

Signed-off-by: Blue Swirl 
Reviewed-by: Peter Maydell 
---
 configure|2 +-
 target-arm/Makefile.objs |2 --
 target-arm/cpu.h |   10 ++
 target-arm/helper.c  |9 +
 target-arm/op_helper.c   |8 +---
 target-arm/translate.c   |6 +++---
 6 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/configure b/configure
index 4fd3b7f..efb5014 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | 
xtensa* | ppc*)
+  alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | 
x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index f447c4f..b6f1a9e 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -2,5 +2,3 @@ obj-y += arm-semi.o
 obj-$(CONFIG_SOFTMMU) += machine.o
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-y += neon_helper.o iwmmxt_helper.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d7f93d9..7fac94f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env, 
TranslationBlock *tb)
 }
 
 /* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
+static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
+bool do_swap)
 {
-uint32_t insn = ldl_code(addr);
+uint32_t insn = cpu_ldl_code(env, addr);
 if (do_swap) {
 return bswap32(insn);
 }
@@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool 
do_swap)
 }
 
 /* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
+static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
+ bool do_swap)
 {
-uint16_t insn = lduw_code(addr);
+uint16_t insn = cpu_lduw_code(env, addr);
 if (do_swap) {
 return bswap16(insn);
 }
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dceaa95..1300d59 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
 case EXCP_BKPT:
 if (semihosting_enabled) {
 int nr;
-nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
+nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
 if (nr == 0xab) {
 env->regs[15] += 2;
 env->regs[0] = do_arm_semihosting(env);
@@ -1828,9 +1828,10 @@ void do_interrupt(CPUARMState *env)
 if (semihosting_enabled) {
 /* Check for semihosting interrupt.  */
 if (env->thumb) {
-mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 
0xff;
+mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
+& 0xff;
 } else {
-mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
+mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
 & 0xff;
 }
 /* Only intercept calls from privileged modes, to provide some
@@ -1851,7 +1852,7 @@ void do_interrupt(CPUARMState *env)
 case EXCP_BKPT:
 /* See if this is a semihosting syscall.  */
 if (env->thumb && semihosting_enabled) {
-mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
+mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
 if (mask == 0xab
   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
 env->regs[15] += 2;
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 5b868bf..f13fc3a 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -17,7 +17,6 @@
  * License along with this library; if not, see .
  */
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helper.h"
 
 #define SIGNBIT (uint32_t)0x8000
@@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, 
uint32_t def,
 /* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
   uintptr_t retaddr)
 {
 TranslationBlock *tb;
-CPUARMState *s

[Qemu-devel] [PATCH v2 12/14] target-sh4: switch to AREG0 free mode

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl 
---
 configure|2 +-
 target-sh4/Makefile.objs |2 -
 target-sh4/helper.h  |   84 +++---
 target-sh4/op_helper.c   |  182 ++---
 target-sh4/translate.c   |  114 -
 5 files changed, 195 insertions(+), 189 deletions(-)

diff --git a/configure b/configure
index d760e07..d69e43e 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
sparc* | unicore32 | x86_64 | xtensa* | ppc*)
+  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | sh4* 
| sparc* | unicore32 | x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-sh4/Makefile.objs b/target-sh4/Makefile.objs
index 2e0e093..ca20f21 100644
--- a/target-sh4/Makefile.objs
+++ b/target-sh4/Makefile.objs
@@ -1,4 +1,2 @@
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 95e3c7c..6e4f108 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -1,54 +1,54 @@
 #include "def-helper.h"
 
-DEF_HELPER_0(ldtlb, void)
-DEF_HELPER_0(raise_illegal_instruction, void)
-DEF_HELPER_0(raise_slot_illegal_instruction, void)
-DEF_HELPER_0(raise_fpu_disable, void)
-DEF_HELPER_0(raise_slot_fpu_disable, void)
-DEF_HELPER_0(debug, void)
-DEF_HELPER_1(sleep, void, i32)
-DEF_HELPER_1(trapa, void, i32)
+DEF_HELPER_1(ldtlb, void, env)
+DEF_HELPER_1(raise_illegal_instruction, void, env)
+DEF_HELPER_1(raise_slot_illegal_instruction, void, env)
+DEF_HELPER_1(raise_fpu_disable, void, env)
+DEF_HELPER_1(raise_slot_fpu_disable, void, env)
+DEF_HELPER_1(debug, void, env)
+DEF_HELPER_2(sleep, void, env, i32)
+DEF_HELPER_2(trapa, void, env, i32)
 
-DEF_HELPER_2(movcal, void, i32, i32)
-DEF_HELPER_0(discard_movcal_backup, void)
-DEF_HELPER_1(ocbi, void, i32)
+DEF_HELPER_3(movcal, void, env, i32, i32)
+DEF_HELPER_1(discard_movcal_backup, void, env)
+DEF_HELPER_2(ocbi, void, env, i32)
 
-DEF_HELPER_2(addv, i32, i32, i32)
-DEF_HELPER_2(addc, i32, i32, i32)
-DEF_HELPER_2(subv, i32, i32, i32)
-DEF_HELPER_2(subc, i32, i32, i32)
-DEF_HELPER_2(div1, i32, i32, i32)
-DEF_HELPER_2(macl, void, i32, i32)
-DEF_HELPER_2(macw, void, i32, i32)
+DEF_HELPER_3(addv, i32, env, i32, i32)
+DEF_HELPER_3(addc, i32, env, i32, i32)
+DEF_HELPER_3(subv, i32, env, i32, i32)
+DEF_HELPER_3(subc, i32, env, i32, i32)
+DEF_HELPER_3(div1, i32, env, i32, i32)
+DEF_HELPER_3(macl, void, env, i32, i32)
+DEF_HELPER_3(macw, void, env, i32, i32)
 
-DEF_HELPER_1(ld_fpscr, void, i32)
+DEF_HELPER_2(ld_fpscr, void, env, i32)
 
 DEF_HELPER_1(fabs_FT, f32, f32)
 DEF_HELPER_1(fabs_DT, f64, f64)
-DEF_HELPER_2(fadd_FT, f32, f32, f32)
-DEF_HELPER_2(fadd_DT, f64, f64, f64)
-DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
-DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
+DEF_HELPER_3(fadd_FT, f32, env, f32, f32)
+DEF_HELPER_3(fadd_DT, f64, env, f64, f64)
+DEF_HELPER_2(fcnvsd_FT_DT, f64, env, f32)
+DEF_HELPER_2(fcnvds_DT_FT, f32, env, f64)
 
-DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
-DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
-DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
-DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
-DEF_HELPER_2(fdiv_FT, f32, f32, f32)
-DEF_HELPER_2(fdiv_DT, f64, f64, f64)
-DEF_HELPER_1(float_FT, f32, i32)
-DEF_HELPER_1(float_DT, f64, i32)
-DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
-DEF_HELPER_2(fmul_FT, f32, f32, f32)
-DEF_HELPER_2(fmul_DT, f64, f64, f64)
+DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
+DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
+DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
+DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
+DEF_HELPER_3(fdiv_FT, f32, env, f32, f32)
+DEF_HELPER_3(fdiv_DT, f64, env, f64, f64)
+DEF_HELPER_2(float_FT, f32, env, i32)
+DEF_HELPER_2(float_DT, f64, env, i32)
+DEF_HELPER_4(fmac_FT, f32, env, f32, f32, f32)
+DEF_HELPER_3(fmul_FT, f32, env, f32, f32)
+DEF_HELPER_3(fmul_DT, f64, env, f64, f64)
 DEF_HELPER_1(fneg_T, f32, f32)
-DEF_HELPER_2(fsub_FT, f32, f32, f32)
-DEF_HELPER_2(fsub_DT, f64, f64, f64)
-DEF_HELPER_1(fsqrt_FT, f32, f32)
-DEF_HELPER_1(fsqrt_DT, f64, f64)
-DEF_HELPER_1(ftrc_FT, i32, f32)
-DEF_HELPER_1(ftrc_DT, i32, f64)
-DEF_HELPER_2(fipr, void, i32, i32)
-DEF_HELPER_1(ftrv, void, i32)
+DEF_HELPER_3(fsub_FT, f32, env, f32, f32)
+DEF_HELPER_3(fsub_DT, f64, env, f64, f64)
+DEF_HELPER_2(fsqrt_FT, f32, env, f32)
+DEF_HELPER_2(fsqrt_DT, f64, env, f64)
+DEF_HELPER_2(ftrc_FT, i32, env, f32)
+DEF_HELPER_2(ftrc_DT, i32, env, f64)
+DEF_HELPER_3(fipr, void, env, i32, i32)
+DEF_HELPER_2(ftrv, void, env, i32)
 
 #include "def-helper.h"
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 40

[Qemu-devel] [PATCH 03/12] pci: add a pci_vga_init() function

[Aurelien Jarno]

This function create a PCI VGA device according to the value of
vga_interface_type. It returns a PCIDevice (and not a DeviceState).

Cc: Anthony Liguori 
Signed-off-by: Aurelien Jarno 
---
 hw/pci.c |   18 ++
 hw/pci.h |3 +++
 2 files changed, 21 insertions(+)

diff --git a/hw/pci.c b/hw/pci.c
index 4d95984..1b775b6 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1474,6 +1474,24 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char 
*default_model,
 return res;
 }
 
+PCIDevice *pci_vga_init(PCIBus *bus)
+{
+switch (vga_interface_type) {
+case VGA_CIRRUS:
+return pci_create_simple(bus, -1, "cirrus-vga");
+case VGA_QXL:
+return pci_create_simple(bus, -1, "qxl-vga");
+case VGA_STD:
+return pci_create_simple(bus, -1, "VGA");
+case VGA_VMWARE:
+return pci_create_simple(bus, -1, "vmware-svga");
+case VGA_NONE:
+default: /* Other non-PCI types. Checking for unsupported types is already
+done in vl.c. */
+return NULL;
+}
+}
+
 /* Whether a given bus number is in range of the secondary
  * bus of the given bridge device. */
 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
diff --git a/hw/pci.h b/hw/pci.h
index 4b6ab3d..84b43b2 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -334,6 +334,9 @@ PCIDevice *pci_nic_init(NICInfo *nd, const char 
*default_model,
 const char *default_devaddr);
 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
const char *default_devaddr);
+
+PCIDevice *pci_vga_init(PCIBus *bus);
+
 int pci_bus_num(PCIBus *s);
 void pci_for_each_device(PCIBus *bus, int bus_num,
  void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
-- 
1.7.10.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Alexander Graf]

On 08.09.2012, at 12:16, Blue Swirl  wrote:

> On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf  wrote:
>> 
>> 
>> On 08.09.2012, at 10:06, Blue Swirl  wrote:
>> 
>>> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
 On 09/05/2012 10:04 PM, Blue Swirl wrote:
> 
> Reinventing a disassembler for ever growing x86 assembly is
> no fun.
 
 We can try linking to a disassembler library.  I use udis86 to
 disassemble instructions in kvm tracepoints
 (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
 it's maintained but not heavily so.
>>> 
>>> I think commonality with KVM would be preferred. The library looks
>>> neat and based on changelog, more actively developed than BSD DDB.
>>> 
 
 Of course for non-x86 we'd need to continue using binutils; this is
 about copying code vs. libraries, not about licensing.
>>> 
>>> For most architectures, pre-GPLv3 binutils is good enough since the
>>> instruction set does not change anymore. Maybe only PPC and Sparc64
>>> still change besides x86. New CPUs types more recent than 2007 will
>>> have problems.
>> 
>> Alternatively we could try to run the disassembler in a different process, 
>> right?
> 
> For qemu.log this would be doable and even improve performance since
> only binary data would be transferred.
> 
> But for monitor disassembly command x/i it may be too clumsy.

Why would it be clumsy? We'd have to make sure we are communicating 
synchronously with the daemon, but apart from that it shouldn't be too 
different from the log, no?

> There's
> some overlap with GDB support, so maybe we could deprecate monitor
> disassembly.

I really like the way the monitor goes through special v->p lookup, as it's a 
lot easier to debug...

Alex

> 
>> 
>> Alex
>> 
>>> 
 
 
 --
 error compiling committee.c: too many arguments to function
>>> 

[Qemu-devel] [PATCH v2 06/14] target-arm: convert void helpers

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0.

For easier review, convert only op helpers which don't return any value.

Signed-off-by: Blue Swirl 
Reviewed-by: Peter Maydell 
---
 target-arm/helper.h|8 
 target-arm/op_helper.c |   20 ++--
 target-arm/translate.c |8 
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/target-arm/helper.h b/target-arm/helper.h
index 21e9cfe..106aacd 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -50,10 +50,10 @@ DEF_HELPER_2(usad8, i32, i32, i32)
 DEF_HELPER_1(logicq_cc, i32, i64)
 
 DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
-DEF_HELPER_1(exception, void, i32)
-DEF_HELPER_0(wfi, void)
+DEF_HELPER_2(exception, void, env, i32)
+DEF_HELPER_1(wfi, void, env)
 
-DEF_HELPER_2(cpsr_write, void, i32, i32)
+DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_0(cpsr_read, i32)
 
 DEF_HELPER_3(v7m_msr, void, env, i32, i32)
@@ -68,7 +68,7 @@ DEF_HELPER_2(get_r13_banked, i32, env, i32)
 DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
 
 DEF_HELPER_1(get_user_reg, i32, i32)
-DEF_HELPER_2(set_user_reg, void, i32, i32)
+DEF_HELPER_3(set_user_reg, void, env, i32, i32)
 
 DEF_HELPER_1(vfp_get_fpscr, i32, env)
 DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index d77bfab..b1adce3 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -23,7 +23,7 @@
 #define SIGNBIT (uint32_t)0x8000
 #define SIGNBIT64 ((uint64_t)1 << 63)
 
-static void raise_exception(int tt)
+static void raise_exception(CPUARMState *env, int tt)
 {
 env->exception_index = tt;
 cpu_loop_exit(env);
@@ -93,7 +93,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 cpu_restore_state(tb, env, retaddr);
 }
 }
-raise_exception(env->exception_index);
+raise_exception(env, env->exception_index);
 }
 env = saved_env;
 }
@@ -230,14 +230,14 @@ uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
 return res;
 }
 
-void HELPER(wfi)(void)
+void HELPER(wfi)(CPUARMState *env)
 {
 env->exception_index = EXCP_HLT;
 env->halted = 1;
 cpu_loop_exit(env);
 }
 
-void HELPER(exception)(uint32_t excp)
+void HELPER(exception)(CPUARMState *env, uint32_t excp)
 {
 env->exception_index = excp;
 cpu_loop_exit(env);
@@ -248,7 +248,7 @@ uint32_t HELPER(cpsr_read)(void)
 return cpsr_read(env) & ~CPSR_EXEC;
 }
 
-void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
+void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 {
 cpsr_write(env, val, mask);
 }
@@ -271,7 +271,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
 return val;
 }
 
-void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
+void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 {
 if (regno == 13) {
 env->banked_r13[0] = val;
@@ -290,7 +290,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, 
uint32_t value)
 const ARMCPRegInfo *ri = rip;
 int excp = ri->writefn(env, ri, value);
 if (excp) {
-raise_exception(excp);
+raise_exception(env, excp);
 }
 }
 
@@ -300,7 +300,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 uint64_t value;
 int excp = ri->readfn(env, ri, &value);
 if (excp) {
-raise_exception(excp);
+raise_exception(env, excp);
 }
 return value;
 }
@@ -310,7 +310,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, 
uint64_t value)
 const ARMCPRegInfo *ri = rip;
 int excp = ri->writefn(env, ri, value);
 if (excp) {
-raise_exception(excp);
+raise_exception(env, excp);
 }
 }
 
@@ -320,7 +320,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 uint64_t value;
 int excp = ri->readfn(env, ri, &value);
 if (excp) {
-raise_exception(excp);
+raise_exception(env, excp);
 }
 return value;
 }
diff --git a/target-arm/translate.c b/target-arm/translate.c
index edef79a..6f651d9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
 {
 TCGv tmp_mask = tcg_const_i32(mask);
-gen_helper_cpsr_write(var, tmp_mask);
+gen_helper_cpsr_write(cpu_env, var, tmp_mask);
 tcg_temp_free_i32(tmp_mask);
 }
 /* Set NZCV flags from the high 4 bits of var.  */
@@ -209,7 +209,7 @@ static void gen_exception(int excp)
 {
 TCGv tmp = tcg_temp_new_i32();
 tcg_gen_movi_i32(tmp, excp);
-gen_helper_exception(tmp);
+gen_helper_exception(cpu_env, tmp);
 tcg_temp_free_i32(tmp);
 }
 
@@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, 
DisasContext *s)
 tmp = gen_ld32(addr, IS_USER(s));
 if (user) {
 tmp2 = tcg_const_i32

[Qemu-devel] [PATCH 02/12] vl.c: check for qxl availability

[Aurelien Jarno]

Check for qxl availability in vl.c. This will allow to remove #ifdef
CONFIG_SPICE .. #endif later in this series

Cc: Anthony Liguori 
Cc: Gerd Hoffmann 
Signed-off-by: Aurelien Jarno 
---
 vl.c |   12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/vl.c b/vl.c
index 7c577fa..6363915 100644
--- a/vl.c
+++ b/vl.c
@@ -1703,6 +1703,11 @@ static bool vmware_vga_available(void)
 return qdev_exists("vmware-svga");
 }
 
+static bool qxl_vga_available(void)
+{
+return qdev_exists("qxl-vga");
+}
+
 static void select_vgahw (const char *p)
 {
 const char *opts;
@@ -1732,7 +1737,12 @@ static void select_vgahw (const char *p)
 } else if (strstart(p, "xenfb", &opts)) {
 vga_interface_type = VGA_XENFB;
 } else if (strstart(p, "qxl", &opts)) {
-vga_interface_type = VGA_QXL;
+if (qxl_vga_available()) {
+vga_interface_type = VGA_QXL;
+} else {
+fprintf(stderr, "Error: QXL VGA not available\n");
+exit(0);
+}
 } else if (!strstart(p, "none", &opts)) {
 invalid_vga:
 fprintf(stderr, "Unknown vga type: %s\n", p);
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH v7 12/14] target-mips-ase-dsp: Add MIPS DSP processors

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 08:01:30PM +0800, Jia Liu wrote:
> Hi Aurelien,
> 
> On Thu, Sep 6, 2012 at 5:11 PM, Aurelien Jarno  wrote:
> > On Tue, Aug 28, 2012 at 02:36:23PM +0800, Jia Liu wrote:
> >> Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model for test.
> >>
> >> Signed-off-by: Jia Liu 
> >> ---
> >>  target-mips/translate_init.c |   55 
> >> ++
> >>  1 file changed, 55 insertions(+)
> >>
> >> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> >> index c39138f..65ba547 100644
> >> --- a/target-mips/translate_init.c
> >> +++ b/target-mips/translate_init.c
> >> @@ -311,6 +311,32 @@ static const mips_def_t mips_defs[] =
> >>  .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
> >>  .mmu_type = MMU_TYPE_R4000,
> >>  },
> >> +{
> >> +/* A generic CPU providing MIPS32 ASE DSP Release 2 features.
> >> +   FIXME: Eventually this should be replaced by a real CPU model. 
> >> */
> >
> > Is it something that could be fixed now? I guess MIPS produces core with
> > this instruction set.
> >
> 
> I'll make it 74kf. Is it OK?
> 

Yes, it looks fine to me.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH v7 12/14] target-mips-ase-dsp: Add MIPS DSP processors

[Jia Liu]

Hi Aurelien,

On Thu, Sep 6, 2012 at 5:11 PM, Aurelien Jarno  wrote:
> On Tue, Aug 28, 2012 at 02:36:23PM +0800, Jia Liu wrote:
>> Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model for test.
>>
>> Signed-off-by: Jia Liu 
>> ---
>>  target-mips/translate_init.c |   55 
>> ++
>>  1 file changed, 55 insertions(+)
>>
>> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
>> index c39138f..65ba547 100644
>> --- a/target-mips/translate_init.c
>> +++ b/target-mips/translate_init.c
>> @@ -311,6 +311,32 @@ static const mips_def_t mips_defs[] =
>>  .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
>>  .mmu_type = MMU_TYPE_R4000,
>>  },
>> +{
>> +/* A generic CPU providing MIPS32 ASE DSP Release 2 features.
>> +   FIXME: Eventually this should be replaced by a real CPU model. */
>
> Is it something that could be fixed now? I guess MIPS produces core with
> this instruction set.
>

I'll make it 74kf. Is it OK?

>> +.name = "mips32dspr2",
>> +.CP0_PRid = 0x00019300,
>> +.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
>> +(MMU_TYPE_R4000 << CP0C0_MT),
>> +.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
>> +   (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
>> +   (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>> +   (1 << CP0C1_CA),
>> +.CP0_Config2 = MIPS_CONFIG2,
>> +.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
>> +.CP0_LLAddr_rw_bitmask = 0,
>> +.CP0_LLAddr_shift = 4,
>> +.SYNCI_Step = 32,
>> +.CCRes = 2,
>> +/* No DSP implemented. */
>> +.CP0_Status_rw_bitmask = 0x3778FF1F,
>> +.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>> +(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
>> +.SEGBITS = 32,
>> +.PABITS = 32,
>> +.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
>> +.mmu_type = MMU_TYPE_R4000,
>> +},
>>  #if defined(TARGET_MIPS64)
>>  {
>>  .name = "R4000",
>> @@ -484,6 +510,35 @@ static const mips_def_t mips_defs[] =
>>.insn_flags = CPU_LOONGSON2F,
>>.mmu_type = MMU_TYPE_R4000,
>>  },
>> +{
>> +/* A generic CPU providing MIPS64 ASE DSP Release 2 features.
>> +   FIXME: Eventually this should be replaced by a real CPU model. */
>> +.name = "mips64dspr2",
>> +/* We emulate a later version of the 20Kc, earlier ones had a broken
>> +   WAIT instruction. */
>> +.CP0_PRid = 0x000182a0,
>> +.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
>> +(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
>> +.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
>> +   (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
>> +   (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>> +   (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>> +.CP0_Config2 = MIPS_CONFIG2,
>> +.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP),
>> +.CP0_LLAddr_rw_bitmask = 0,
>> +.CP0_LLAddr_shift = 0,
>> +.SYNCI_Step = 32,
>> +.CCRes = 1,
>> +.CP0_Status_rw_bitmask = 0x37FB,
>> +/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
>> +.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
>> +(1 << FCR0_D) | (1 << FCR0_S) |
>> +(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
>> +.SEGBITS = 40,
>> +.PABITS = 36,
>> +.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
>> +.mmu_type = MMU_TYPE_R4000,
>> +},
>>
>>  #endif
>>  };
>> --
>> 1.7.9.5
>>
>>
>
> --
> Aurelien Jarno  GPG: 1024D/F1BCDB73
> aurel...@aurel32.net http://www.aurel32.net

Regards,
Jia

[Qemu-devel] [PATCH 08/12] ppc/prep: use the new pci_vga_init() function

[Aurelien Jarno]

As a bonus it allows new vga card types (including none).

Cc: Andreas Färber 
Signed-off-by: Aurelien Jarno 
---
 hw/ppc_prep.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 1fa7609..1544430 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -39,7 +39,6 @@
 #include "blockdev.h"
 #include "arch_init.h"
 #include "exec-memory.h"
-#include "vga-pci.h"
 
 //#define HARD_DEBUG_PPC_IO
 //#define DEBUG_PPC_IO
@@ -611,7 +610,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
 memory_region_add_subregion(sysmem, 0x8000, PPC_io_memory);
 
 /* init basic PC hardware */
-pci_std_vga_init(pci_bus);
+pci_vga_init(pci_bus);
 
 if (serial_hds[0])
 serial_isa_init(isa_bus, 0, serial_hds[0]);
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 01/14] target-s390x: avoid cpu_single_env

[Blue Swirl]

Pass around CPUState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
---
 target-s390x/translate.c |  356 --
 1 files changed, 183 insertions(+), 173 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 66119cd..3214783 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -274,21 +274,21 @@ static inline void potential_page_fault(DisasContext *s)
 #endif
 }
 
-static inline uint64_t ld_code2(uint64_t pc)
+static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
 {
-return (uint64_t)cpu_lduw_code(cpu_single_env, pc);
+return (uint64_t)cpu_lduw_code(env, pc);
 }
 
-static inline uint64_t ld_code4(uint64_t pc)
+static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
 {
-return (uint64_t)cpu_ldl_code(cpu_single_env, pc);
+return (uint64_t)cpu_ldl_code(env, pc);
 }
 
-static inline uint64_t ld_code6(uint64_t pc)
+static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)
 {
 uint64_t opc;
-opc = (uint64_t)cpu_lduw_code(cpu_single_env, pc) << 32;
-opc |= (uint64_t)(uint32_t)cpu_ldl_code(cpu_single_env, pc + 2);
+opc = (uint64_t)cpu_lduw_code(env, pc) << 32;
+opc |= (uint64_t)(uint32_t)cpu_ldl_code(env, pc + 2);
 return opc;
 }
 
@@ -319,7 +319,7 @@ static inline void gen_debug(DisasContext *s)
 
 #ifdef CONFIG_USER_ONLY
 
-static void gen_illegal_opcode(DisasContext *s, int ilc)
+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)
 {
 TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
 update_psw_addr(s);
@@ -331,20 +331,20 @@ static void gen_illegal_opcode(DisasContext *s, int ilc)
 
 #else /* CONFIG_USER_ONLY */
 
-static void debug_print_inst(DisasContext *s, int ilc)
+static void debug_print_inst(CPUS390XState *env, DisasContext *s, int ilc)
 {
 #ifdef DEBUG_ILLEGAL_INSTRUCTIONS
 uint64_t inst = 0;
 
 switch (ilc & 3) {
 case 1:
-inst = ld_code2(s->pc);
+inst = ld_code2(env, s->pc);
 break;
 case 2:
-inst = ld_code4(s->pc);
+inst = ld_code4(env, s->pc);
 break;
 case 3:
-inst = ld_code6(s->pc);
+inst = ld_code6(env, s->pc);
 break;
 }
 
@@ -353,11 +353,12 @@ static void debug_print_inst(DisasContext *s, int ilc)
 #endif
 }
 
-static void gen_program_exception(DisasContext *s, int ilc, int code)
+static void gen_program_exception(CPUS390XState *env, DisasContext *s, int ilc,
+  int code)
 {
 TCGv_i32 tmp;
 
-debug_print_inst(s, ilc);
+debug_print_inst(env, s, ilc);
 
 /* remember what pgm exeption this was */
 tmp = tcg_const_i32(code);
@@ -385,20 +386,21 @@ static void gen_program_exception(DisasContext *s, int 
ilc, int code)
 }
 
 
-static void gen_illegal_opcode(DisasContext *s, int ilc)
+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)
 {
-gen_program_exception(s, ilc, PGM_SPECIFICATION);
+gen_program_exception(env, s, ilc, PGM_SPECIFICATION);
 }
 
-static void gen_privileged_exception(DisasContext *s, int ilc)
+static void gen_privileged_exception(CPUS390XState *env, DisasContext *s,
+ int ilc)
 {
-gen_program_exception(s, ilc, PGM_PRIVILEGED);
+gen_program_exception(env, s, ilc, PGM_PRIVILEGED);
 }
 
-static void check_privileged(DisasContext *s, int ilc)
+static void check_privileged(CPUS390XState *env, DisasContext *s, int ilc)
 {
 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
-gen_privileged_exception(s, ilc);
+gen_privileged_exception(env, s, ilc);
 }
 }
 
@@ -1460,7 +1462,8 @@ static void gen_op_clc(DisasContext *s, int l, TCGv_i64 
s1, TCGv_i64 s2)
 set_cc_static(s);
 }
 
-static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
+static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,
+ int x2, int b2, int d2)
 {
 TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
 TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
@@ -1925,14 +1928,14 @@ static void disas_e3(DisasContext* s, int op, int r1, 
int x2, int b2, int d2)
 break;
 default:
 LOG_DISAS("illegal e3 operation 0x%x\n", op);
-gen_illegal_opcode(s, 3);
+gen_illegal_opcode(env, s, 3);
 break;
 }
 tcg_temp_free_i64(addr);
 }
 
 #ifndef CONFIG_USER_ONLY
-static void disas_e5(DisasContext* s, uint64_t insn)
+static void disas_e5(CPUS390XState *env, DisasContext* s, uint64_t insn)
 {
 TCGv_i64 tmp, tmp2;
 int op = (insn >> 32) & 0xff;
@@ -1950,7 +1953,7 @@ static void disas_e5(DisasContext* s, uint64_t insn)
 break;
 default:
 LOG_DISAS("illegal e5 operation 0x%x\n", op);
-gen_illegal_opcode(s, 3);
+gen_illegal_opcode(env, s, 3);
 break;
 }
 
@@ -1959,7 +1962,8 @@ static void disas_e5(DisasContext* s, uint64_t insn)
 }
 #endif
 
-static void disas_eb(Disa

[Qemu-devel] [PATCH 01/12] vga: rename pci_vga_init() into pci_std_vga_init()

[Aurelien Jarno]

This better explains what is this function about. Adjust all callers.

Cc: Richard Henderson 
Cc: Alexander Graf 
Cc: Andreas Färber 
Cc: David Gibson 
Cc: Blue Swirl 
Cc: Anthony Liguori 
Signed-off-by: Aurelien Jarno 
---
 hw/alpha_pci.c|2 +-
 hw/mips_malta.c   |2 +-
 hw/pc.c   |2 +-
 hw/ppc_newworld.c |2 +-
 hw/ppc_oldworld.c |2 +-
 hw/ppc_prep.c |2 +-
 hw/spapr.c|2 +-
 hw/sun4u.c|2 +-
 hw/vga-pci.c  |6 +++---
 hw/vga-pci.h  |2 +-
 10 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
index ea546f8..0352e72 100644
--- a/hw/alpha_pci.c
+++ b/hw/alpha_pci.c
@@ -128,6 +128,6 @@ void alpha_pci_vga_setup(PCIBus *pci_bus)
 /* If VGA is enabled at all, and one of the above didn't work, then
fallback to Standard VGA.  */
 if (vga_interface_type != VGA_NONE) {
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 }
 }
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index ad23f26..c39dee5 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -992,7 +992,7 @@ void mips_malta_init (ram_addr_t ram_size,
 } else if (vmsvga_enabled) {
 pci_vmsvga_init(pci_bus);
 } else if (std_vga_enabled) {
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 }
 }
 
diff --git a/hw/pc.c b/hw/pc.c
index 112739a..8736a30 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1041,7 +1041,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 #endif
 } else if (std_vga_enabled) {
 if (pci_bus) {
-dev = pci_vga_init(pci_bus);
+dev = pci_std_vga_init(pci_bus);
 } else {
 dev = isa_vga_init(isa_bus);
 }
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index e95cfe8..84af948 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -330,7 +330,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
 machine_arch = ARCH_MAC99;
 }
 /* init basic PC hardware */
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 
 escc_mem = escc_init(0, pic[0x25], pic[0x24],
  serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 1dcd8a6..8267eb4 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -250,7 +250,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
 pci_bus = pci_grackle_init(0xfec0, pic,
get_system_memory(),
get_system_io());
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 
 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
serial_hds[1], ESCC_CLOCK, 4);
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 592b7b2..1fa7609 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -611,7 +611,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
 memory_region_add_subregion(sysmem, 0x8000, PPC_io_memory);
 
 /* init basic PC hardware */
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 
 if (serial_hds[0])
 serial_isa_init(isa_bus, 0, serial_hds[0]);
diff --git a/hw/spapr.c b/hw/spapr.c
index c34b767..80735d6 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -590,7 +590,7 @@ static int spapr_vga_init(PCIBus *pci_bus)
 {
 switch (vga_interface_type) {
 case VGA_STD:
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 return 1;
 case VGA_NONE:
 return 0;
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 07cd042..cca090f 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -821,7 +821,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, 
&pci_bus2,
&pci_bus3, &pbm_irqs);
-pci_vga_init(pci_bus);
+pci_std_vga_init(pci_bus);
 
 // XXX Should be pci_bus3
 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 9abbada..992ffd9 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -47,7 +47,7 @@ static const VMStateDescription vmstate_vga_pci = {
 }
 };
 
-static int pci_vga_initfn(PCIDevice *dev)
+static int pci_std_vga_initfn(PCIDevice *dev)
 {
  PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
  VGACommonState *s = &d->vga;
@@ -70,7 +70,7 @@ static int pci_vga_initfn(PCIDevice *dev)
  return 0;
 }
 
-DeviceState *pci_vga_init(PCIBus *bus)
+DeviceState *pci_std_vga_init(PCIBus *bus)
 {
 return &pci_create_simple(bus, -1, "VGA")->qdev;
 }
@@ -86,7 +86,7 @@ static void vga_class_init(ObjectClass *klass, void *data)
 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 
 k->no_hotplug = 1;
-k->init = pci_vga_initfn;
+k->init = pci_std_vga_initfn;
 k->romfile = "vgabios-stdvga.bin";
 k->vendor_id = PCI_VENDOR_ID_QEMU;
 k->device_id = PCI_DEVICE_ID_QEMU_VGA;
di

[Qemu-devel] [PATCH v2 09/14] target-microblaze: switch to AREG0 free mode

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl 
---
 configure   |2 +-
 target-microblaze/Makefile.objs |2 -
 target-microblaze/helper.h  |   48 
 target-microblaze/op_helper.c   |  115 ++-
 target-microblaze/translate.c   |   61 +++--
 5 files changed, 110 insertions(+), 118 deletions(-)

diff --git a/configure b/configure
index efb5014..e464d2f 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | 
x86_64 | xtensa* | ppc*)
+  alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | 
unicore32 | x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-microblaze/Makefile.objs b/target-microblaze/Makefile.objs
index 4b09e8c..afb87bc 100644
--- a/target-microblaze/Makefile.objs
+++ b/target-microblaze/Makefile.objs
@@ -1,4 +1,2 @@
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
index 9dcfb0f..a1a732c 100644
--- a/target-microblaze/helper.h
+++ b/target-microblaze/helper.h
@@ -1,39 +1,39 @@
 #include "def-helper.h"
 
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_0(debug, void)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_1(debug, void, env)
 DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, i32)
 DEF_HELPER_2(cmp, i32, i32, i32)
 DEF_HELPER_2(cmpu, i32, i32, i32)
 DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
 
-DEF_HELPER_2(divs, i32, i32, i32)
-DEF_HELPER_2(divu, i32, i32, i32)
-
-DEF_HELPER_2(fadd, i32, i32, i32)
-DEF_HELPER_2(frsub, i32, i32, i32)
-DEF_HELPER_2(fmul, i32, i32, i32)
-DEF_HELPER_2(fdiv, i32, i32, i32)
-DEF_HELPER_1(flt, i32, i32)
-DEF_HELPER_1(fint, i32, i32)
-DEF_HELPER_1(fsqrt, i32, i32)
-
-DEF_HELPER_2(fcmp_un, i32, i32, i32)
-DEF_HELPER_2(fcmp_lt, i32, i32, i32)
-DEF_HELPER_2(fcmp_eq, i32, i32, i32)
-DEF_HELPER_2(fcmp_le, i32, i32, i32)
-DEF_HELPER_2(fcmp_gt, i32, i32, i32)
-DEF_HELPER_2(fcmp_ne, i32, i32, i32)
-DEF_HELPER_2(fcmp_ge, i32, i32, i32)
+DEF_HELPER_3(divs, i32, env, i32, i32)
+DEF_HELPER_3(divu, i32, env, i32, i32)
+
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(frsub, i32, env, i32, i32)
+DEF_HELPER_3(fmul, i32, env, i32, i32)
+DEF_HELPER_3(fdiv, i32, env, i32, i32)
+DEF_HELPER_2(flt, i32, env, i32)
+DEF_HELPER_2(fint, i32, env, i32)
+DEF_HELPER_2(fsqrt, i32, env, i32)
+
+DEF_HELPER_3(fcmp_un, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_lt, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_eq, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_le, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_gt, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_ne, i32, env, i32, i32)
+DEF_HELPER_3(fcmp_ge, i32, env, i32, i32)
 
 DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32)
 #if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_1(mmu_read, i32, i32)
-DEF_HELPER_2(mmu_write, void, i32, i32)
+DEF_HELPER_2(mmu_read, i32, env, i32)
+DEF_HELPER_3(mmu_write, void, env, i32, i32)
 #endif
 
-DEF_HELPER_4(memalign, void, i32, i32, i32, i32)
-DEF_HELPER_1(stackprot, void, i32)
+DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32)
+DEF_HELPER_2(stackprot, void, env, i32)
 
 DEF_HELPER_2(get, i32, i32, i32)
 DEF_HELPER_3(put, void, i32, i32, i32)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 3b1f072..c9789f4 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -20,7 +20,6 @@
 
 #include 
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helper.h"
 #include "host-utils.h"
 
@@ -42,17 +41,12 @@
 /* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
   uintptr_t retaddr)
 {
 TranslationBlock *tb;
-CPUMBState *saved_env;
 int ret;
 
-saved_env = env;
-env = env1;
-
 ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
 if (unlikely(ret)) {
 if (retaddr) {
@@ -66,7 +60,6 @@ void tlb_fill(CPUMBState *env1, target_ulong addr, int 
is_write, int mmu_idx,
 }
 cpu_loop_exit(env);
 }
-env = saved_env;
 }
 #endif
 
@@ -105,13 +98,13 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
 return 0xdead | id;
 }
 
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPUMBState *env, uint32_t ind

[Qemu-devel] [PATCH 07/12] ppc/oldworld: use the new pci_vga_init() function

[Aurelien Jarno]

As a bonus it allows new vga card types (including none).

Cc: Alexander Graf 
Signed-off-by: Aurelien Jarno 
---
 hw/ppc_oldworld.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 8267eb4..2c4a478 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -43,7 +43,6 @@
 #include "kvm_ppc.h"
 #include "blockdev.h"
 #include "exec-memory.h"
-#include "vga-pci.h"
 
 #define MAX_IDE_BUS 2
 #define CFG_ADDR 0xf510
@@ -250,7 +249,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
 pci_bus = pci_grackle_init(0xfec0, pic,
get_system_memory(),
get_system_io());
-pci_std_vga_init(pci_bus);
+pci_vga_init(pci_bus);
 
 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
serial_hds[1], ESCC_CLOCK, 4);
-- 
1.7.10.4

[Qemu-devel] [PATCH v2 02/14] target-lm32: switch to AREG0 free mode

[Blue Swirl]

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl 
---
 configure |2 +-
 target-lm32/Makefile.objs |2 --
 target-lm32/helper.h  |   20 ++--
 target-lm32/op_helper.c   |   29 +++--
 target-lm32/translate.c   |   28 +---
 5 files changed, 35 insertions(+), 46 deletions(-)

diff --git a/configure b/configure
index a88a465..9261f68 100755
--- a/configure
+++ b/configure
@@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | i386 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
+  alpha | i386 | lm32 | or32 | s390x | sparc* | x86_64 | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
diff --git a/target-lm32/Makefile.objs b/target-lm32/Makefile.objs
index 2e0e093..ca20f21 100644
--- a/target-lm32/Makefile.objs
+++ b/target-lm32/Makefile.objs
@@ -1,4 +1,2 @@
 obj-y += translate.o op_helper.o helper.o cpu.o
 obj-$(CONFIG_SOFTMMU) += machine.o
-
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-lm32/helper.h b/target-lm32/helper.h
index 9d335ef..07f5670 100644
--- a/target-lm32/helper.h
+++ b/target-lm32/helper.h
@@ -1,14 +1,14 @@
 #include "def-helper.h"
 
-DEF_HELPER_1(raise_exception, void, i32)
-DEF_HELPER_0(hlt, void)
-DEF_HELPER_1(wcsr_im, void, i32)
-DEF_HELPER_1(wcsr_ip, void, i32)
-DEF_HELPER_1(wcsr_jtx, void, i32)
-DEF_HELPER_1(wcsr_jrx, void, i32)
-DEF_HELPER_0(rcsr_im, i32)
-DEF_HELPER_0(rcsr_ip, i32)
-DEF_HELPER_0(rcsr_jtx, i32)
-DEF_HELPER_0(rcsr_jrx, i32)
+DEF_HELPER_2(raise_exception, void, env, i32)
+DEF_HELPER_1(hlt, void, env)
+DEF_HELPER_2(wcsr_im, void, env, i32)
+DEF_HELPER_2(wcsr_ip, void, env, i32)
+DEF_HELPER_2(wcsr_jtx, void, env, i32)
+DEF_HELPER_2(wcsr_jrx, void, env, i32)
+DEF_HELPER_1(rcsr_im, i32, env)
+DEF_HELPER_1(rcsr_ip, i32, env)
+DEF_HELPER_1(rcsr_jtx, i32, env)
+DEF_HELPER_1(rcsr_jrx, i32, env)
 
 #include "def-helper.h"
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 51edc1a..7b91d8c 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -1,6 +1,5 @@
 #include 
 #include "cpu.h"
-#include "dyngen-exec.h"
 #include "helper.h"
 #include "host-utils.h"
 
@@ -18,55 +17,55 @@
 #define SHIFT 3
 #include "softmmu_template.h"
 
-void helper_raise_exception(uint32_t index)
+void helper_raise_exception(CPULM32State *env, uint32_t index)
 {
 env->exception_index = index;
 cpu_loop_exit(env);
 }
 
-void helper_hlt(void)
+void helper_hlt(CPULM32State *env)
 {
 env->halted = 1;
 env->exception_index = EXCP_HLT;
 cpu_loop_exit(env);
 }
 
-void helper_wcsr_im(uint32_t im)
+void helper_wcsr_im(CPULM32State *env, uint32_t im)
 {
 lm32_pic_set_im(env->pic_state, im);
 }
 
-void helper_wcsr_ip(uint32_t im)
+void helper_wcsr_ip(CPULM32State *env, uint32_t im)
 {
 lm32_pic_set_ip(env->pic_state, im);
 }
 
-void helper_wcsr_jtx(uint32_t jtx)
+void helper_wcsr_jtx(CPULM32State *env, uint32_t jtx)
 {
 lm32_juart_set_jtx(env->juart_state, jtx);
 }
 
-void helper_wcsr_jrx(uint32_t jrx)
+void helper_wcsr_jrx(CPULM32State *env, uint32_t jrx)
 {
 lm32_juart_set_jrx(env->juart_state, jrx);
 }
 
-uint32_t helper_rcsr_im(void)
+uint32_t helper_rcsr_im(CPULM32State *env)
 {
 return lm32_pic_get_im(env->pic_state);
 }
 
-uint32_t helper_rcsr_ip(void)
+uint32_t helper_rcsr_ip(CPULM32State *env)
 {
 return lm32_pic_get_ip(env->pic_state);
 }
 
-uint32_t helper_rcsr_jtx(void)
+uint32_t helper_rcsr_jtx(CPULM32State *env)
 {
 return lm32_juart_get_jtx(env->juart_state);
 }
 
-uint32_t helper_rcsr_jrx(void)
+uint32_t helper_rcsr_jrx(CPULM32State *env)
 {
 return lm32_juart_get_jrx(env->juart_state);
 }
@@ -74,17 +73,12 @@ uint32_t helper_rcsr_jrx(void)
 /* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPULM32State *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
   uintptr_t retaddr)
 {
 TranslationBlock *tb;
-CPULM32State *saved_env;
 int ret;
 
-saved_env = env;
-env = env1;
-
 ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
 if (unlikely(ret)) {
 if (retaddr) {
@@ -98,7 +92,6 @@ void tlb_fill(CPULM32State *env1, target_ulong addr, int 
is_write, int mmu_idx,
 }
 cpu_loop_exit(env);
 }
-env = saved_env;
 }
 #endif
 
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 872a2ba..5f6dcba 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -116,7 +116,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, 
uint32_t index)
 {
 TCGv_i32 tmp 

[Qemu-devel] [PATCH v2 00/14] AREG0 patches, final round

[Blue Swirl]

Convert remaining targets to AREG0 free mode.

Avoid also cpu_single_env in translation code.

If there are no objections and the s390x queue gets pulled in,
I'll apply the series next weekend.

v2:
  drop queued s390x patches
  avoid also cpu_single_env

Aurelien Jarno (2):
  target-cris: Avoid AREG0 for helpers
  target-cris: Switch to AREG0 free mode

Blue Swirl (12):
  target-s390x: avoid cpu_single_env
  target-lm32: switch to AREG0 free mode
  target-m68k: switch to AREG0 free mode
  target-m68k: avoid using cpu_single_env
  target-unicore32: switch to AREG0 free mode
  target-arm: convert void helpers
  target-arm: convert remaining helpers
  target-arm: final conversion to AREG0 free mode
  target-microblaze: switch to AREG0 free mode
  target-sh4: switch to AREG0 free mode
  target-mips: switch to AREG0 free mode
  Remove unused CONFIG_TCG_PASS_AREG0 and dead code

 Makefile.target |8 -
 configure   |   11 -
 cpu-all.h   |   11 -
 cputlb.c|5 -
 dyngen-exec.h   |   70 ---
 exec-all.h  |4 -
 hw/spapr_hcall.c|1 -
 softmmu_defs.h  |   21 -
 softmmu_header.h|   63 +--
 softmmu_template.h  |   72 +--
 target-arm/Makefile.objs|2 -
 target-arm/cpu.h|   10 +-
 target-arm/helper.c |9 +-
 target-arm/helper.h |   60 ++--
 target-arm/op_helper.c  |   92 ++--
 target-arm/translate.c  |  148 +++---
 target-cris/Makefile.objs   |2 -
 target-cris/helper.c|4 +-
 target-cris/helper.h|   37 +-
 target-cris/op_helper.c |   89 ++--
 target-cris/translate.c |  300 ++--
 target-cris/translate_v10.c |   99 ++--
 target-lm32/Makefile.objs   |2 -
 target-lm32/helper.h|   20 +-
 target-lm32/op_helper.c |   29 +-
 target-lm32/translate.c |   28 +-
 target-m68k/Makefile.objs   |2 -
 target-m68k/helpers.h   |2 +-
 target-m68k/op_helper.c |   71 +--
 target-m68k/translate.c |  284 ++-
 target-microblaze/Makefile.objs |2 -
 target-microblaze/helper.h  |   48 +-
 target-microblaze/op_helper.c   |  115 ++---
 target-microblaze/translate.c   |   61 ++-
 target-mips/Makefile.objs   |2 -
 target-mips/cpu.h   |   16 +-
 target-mips/helper.h|  410 
 target-mips/op_helper.c | 1065 ---
 target-mips/translate.c |  754 ++--
 target-s390x/translate.c|  356 +++---
 target-sh4/Makefile.objs|2 -
 target-sh4/helper.h |   84 ++--
 target-sh4/op_helper.c  |  182 
 target-sh4/translate.c  |  114 +++--
 target-sparc/Makefile.objs  |2 -
 target-unicore32/Makefile.objs  |2 -
 target-unicore32/helper.h   |   26 +-
 target-unicore32/op_helper.c|   65 +--
 target-unicore32/translate.c|   38 +-
 tcg/arm/tcg-target.c|   31 +-
 tcg/arm/tcg-target.h|1 -
 tcg/hppa/tcg-target.c   |   24 -
 tcg/hppa/tcg-target.h   |1 -
 tcg/i386/tcg-target.c   |   30 --
 tcg/i386/tcg-target.h   |1 -
 tcg/ia64/tcg-target.c   |   34 --
 tcg/ia64/tcg-target.h   |1 -
 tcg/mips/tcg-target.c   |   31 +-
 tcg/mips/tcg-target.h   |1 -
 tcg/ppc/tcg-target.c|   38 --
 tcg/ppc64/tcg-target.c  |   28 -
 tcg/s390/tcg-target.c   |   24 -
 tcg/s390/tcg-target.h   |1 -
 tcg/sparc/tcg-target.c  |   30 --
 tcg/sparc/tcg-target.h  |1 -
 tcg/tci/tcg-target.c|4 -
 tci.c   |   12 -
 user-exec.c |   14 -
 68 files changed, 2394 insertions(+), 2813 deletions(-)
 delete mode 100644 dyngen-exec.h

-- 
1.7.2.5

[Qemu-devel] [PATCH 00/12] Rework PCI video card initialization

[Aurelien Jarno]

This patch series is technically a new version of the "add a video
card only when requested" series I sent yesterday. It uses a different
approach though.

It creates a new pci_vga_init() function that takes care of initializing
the requested PCI video card. This way there is no need to duplicate
code in the various machines QEMU supports, and has the advantage that
the newly added PCI video cards are available to all machines without
having to touch machine specific code.

Cc: Alexander Graf 
Cc: Andreas Färber 
Cc: Anthony Liguori 
Cc: Blue Swirl 
Cc: David Gibson 
Cc: Gerd Hoffmann 
Cc: Richard Henderson 

Aurelien Jarno (12):
  vga: rename pci_vga_init() into pci_std_vga_init()
  vl.c: check for qxl availability
  pci: add a pci_vga_init() function
  mips/malta: use the new pci_vga_init() function
  alpha: use the new pci_vga_init() function
  ppc/newworld: use the new pci_vga_init() function
  ppc/oldworld: use the new pci_vga_init() function
  ppc/prep: use the new pci_vga_init() function
  ppc/pSeries: use the new pci_vga_init() function
  sun/sun4u: use the new pci_vga_init() function
  pc: use the new pci_vga_init() function
  vga: cleanup after pci_vga_init() conversion

 hw/alpha_dp264.c  |2 +-
 hw/alpha_pci.c|   24 
 hw/alpha_sys.h|2 --
 hw/cirrus_vga.c   |6 --
 hw/mips_malta.c   |   10 +-
 hw/pc.c   |   41 +++--
 hw/pci.c  |   18 ++
 hw/pci.h  |3 +++
 hw/ppc_newworld.c |1 -
 hw/ppc_oldworld.c |1 -
 hw/ppc_prep.c |1 -
 hw/spapr.c|7 ++-
 hw/sun4u.c|1 -
 hw/vga-pci.c  |   10 ++
 hw/vga-pci.h  |   12 
 hw/vmware_vga.c   |1 -
 hw/vmware_vga.h   |   15 ---
 sysemu.h  |4 
 vl.c  |   12 +++-
 19 files changed, 53 insertions(+), 118 deletions(-)
 delete mode 100644 hw/vga-pci.h
 delete mode 100644 hw/vmware_vga.h

-- 
1.7.10.4

[Qemu-devel] [PATCH 11/12] pc: use the new pci_vga_init() function

[Aurelien Jarno]

The CONFIG_SPICE is now tested in vl.c and thus not needed anymore. The
various tests are still needed for the ISA cases.

Cc: Anthony Liguori 
Signed-off-by: Aurelien Jarno 
---
 hw/pc.c |   41 +++--
 1 file changed, 15 insertions(+), 26 deletions(-)

diff --git a/hw/pc.c b/hw/pc.c
index 8736a30..8cdbd9e 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -27,7 +27,6 @@
 #include "fdc.h"
 #include "ide.h"
 #include "pci.h"
-#include "vmware_vga.h"
 #include "monitor.h"
 #include "fw_cfg.h"
 #include "hpet_emul.h"
@@ -51,7 +50,6 @@
 #include "exec-memory.h"
 #include "arch_init.h"
 #include "bitmap.h"
-#include "vga-pci.h"
 
 /* output Bochs bios info messages */
 //#define DEBUG_BIOS
@@ -1019,34 +1017,25 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus 
*pci_bus)
 {
 DeviceState *dev = NULL;
 
-if (cirrus_vga_enabled) {
-if (pci_bus) {
-dev = pci_cirrus_vga_init(pci_bus);
-} else {
+if (pci_bus) {
+PCIDevice *pcidev = pci_vga_init(pci_bus);
+dev = pcidev ? &pcidev->qdev : NULL;
+} else {
+switch (vga_interface_type) {
+case VGA_CIRRUS:
 dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
-}
-} else if (vmsvga_enabled) {
-if (pci_bus) {
-dev = pci_vmsvga_init(pci_bus);
-} else {
-fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
-}
-#ifdef CONFIG_SPICE
-} else if (qxl_enabled) {
-if (pci_bus) {
-dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
-} else {
-fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
-}
-#endif
-} else if (std_vga_enabled) {
-if (pci_bus) {
-dev = pci_std_vga_init(pci_bus);
-} else {
+break;
+case VGA_QXL:
+fprintf(stderr, "%s: qxl: no PCI bus\n", __func__);
+break;
+case VGA_STD:
 dev = isa_vga_init(isa_bus);
+break;
+case VGA_VMWARE:
+fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __func__);
+break;
 }
 }
-
 return dev;
 }
 
-- 
1.7.10.4

[Qemu-devel] [PATCH 05/12] alpha: use the new pci_vga_init() function

[Aurelien Jarno]

This remove the fallback to std-vga in case, as availability of the
requested vga device is now tested in vl.c, and returns an error message
to the user.

Cc: Richard Henderson 
Signed-off-by: Aurelien Jarno 
---
 hw/alpha_dp264.c |2 +-
 hw/alpha_pci.c   |   24 
 hw/alpha_sys.h   |2 --
 3 files changed, 1 insertion(+), 27 deletions(-)

diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
index 9eb939f..5ea04c7 100644
--- a/hw/alpha_dp264.c
+++ b/hw/alpha_dp264.c
@@ -77,7 +77,7 @@ static void clipper_init(ram_addr_t ram_size,
 isa_create_simple(isa_bus, "i8042");
 
 /* VGA setup.  Don't bother loading the bios.  */
-alpha_pci_vga_setup(pci_bus);
+pci_vga_init(pci_bus);
 
 /* Serial code setup.  */
 for (i = 0; i < MAX_SERIAL_PORTS; ++i) {
diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
index 0352e72..8079a46 100644
--- a/hw/alpha_pci.c
+++ b/hw/alpha_pci.c
@@ -10,8 +10,6 @@
 #include "alpha_sys.h"
 #include "qemu-log.h"
 #include "sysemu.h"
-#include "vmware_vga.h"
-#include "vga-pci.h"
 
 
 /* PCI IO reads/writes, to byte-word addressable memory.  */
@@ -109,25 +107,3 @@ const MemoryRegionOps alpha_pci_iack_ops = {
 .max_access_size = 4,
 },
 };
-
-void alpha_pci_vga_setup(PCIBus *pci_bus)
-{
-switch (vga_interface_type) {
-#ifdef CONFIG_SPICE
-case VGA_QXL:
-pci_create_simple(pci_bus, -1, "qxl-vga");
-return;
-#endif
-case VGA_CIRRUS:
-pci_cirrus_vga_init(pci_bus);
-return;
-case VGA_VMWARE:
-pci_vmsvga_init(pci_bus);
-return;
-}
-/* If VGA is enabled at all, and one of the above didn't work, then
-   fallback to Standard VGA.  */
-if (vga_interface_type != VGA_NONE) {
-pci_std_vga_init(pci_bus);
-}
-}
diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
index de40f8b..7604d09 100644
--- a/hw/alpha_sys.h
+++ b/hw/alpha_sys.h
@@ -19,6 +19,4 @@ extern const MemoryRegionOps alpha_pci_bw_io_ops;
 extern const MemoryRegionOps alpha_pci_conf1_ops;
 extern const MemoryRegionOps alpha_pci_iack_ops;
 
-void alpha_pci_vga_setup(PCIBus *pci_bus);
-
 #endif
-- 
1.7.10.4

Re: [Qemu-devel] Linux KVM, Windows 7 guest choppy sound

[Jan Kiszka]

On 2012-09-07 18:09, Erik Lotspeich wrote:
> Hi,
> 
> I apologize if this isn't the right venue for this message, but this
> mailing list seems a bit more active than qemu-discuss.
> 
> Background:
> I am running OpenSUSE 12.1. I fixed audio issues in VM guests by setting
> the following in qemu.conf:
> 
> vnc_allow_host_audio = 1
> 
> I also set user= and group= to allow qemu-kvm to run as the same user as
> I am logged in as. This allowed qemu-kvm to send audio to pulseaudio.
> 
> My issue:
> I am using the ICH6 virtual audio driver in my VMs. In my Linux VMs, the
> sound works perfectly without any issues. In my Windows 7 VM, the sound
> works with the exception of static and choppiness in the audio. Has
> anyone else seen this or have any ideas for a fix?

Known issue, likely unfixable in QEMU due to hard-coded constraints of
the driver Windows uses (too small playback buffers).

I gave up on hda, I'm happily using a passed-through USB headset now.
Another known-to-work alternative is PCI passthrough of the host sound
hardware. However, both approaches are no option when the host is out of
reach.

What seems to work better - but is lacking input support - is usb-audio.
Maybe worth a try when you don't need a microphone.

Jan



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Re: [Qemu-devel] [PATCH] iSCSI: We dont need to explicitely call qemu_notify_event() any more

[Paolo Bonzini]

Il 08/09/2012 01:22, ronnie sahlberg ha scritto:
> Ping?

Both are already in scsi-next, thanks!

Paolo

> On Thu, Aug 30, 2012 at 4:56 PM, Ronnie Sahlberg
>  wrote:
>> We no longer need to explicitely call qemu_notify_event() any more since 
>> this is now done automatically any time the filehandles we listen to change.
>>
>> Signed-off-by: Ronnie Sahlberg 
>> ---
>>  block/iscsi.c |6 --
>>  1 files changed, 0 insertions(+), 6 deletions(-)
>>
>> diff --git a/block/iscsi.c b/block/iscsi.c
>> index 0b96165..355ce65 100644
>> --- a/block/iscsi.c
>> +++ b/block/iscsi.c
>> @@ -167,12 +167,6 @@ iscsi_set_events(IscsiLun *iscsilun)
>>
>>  }
>>
>> -/* If we just added an event, the callback might be delayed
>> - * unless we call qemu_notify_event().
>> - */
>> -if (ev & ~iscsilun->events) {
>> -qemu_notify_event();
>> -}
>>  iscsilun->events = ev;
>>  }
>>
>> --
>> 1.7.3.1
>>
> 
> 

Re: [Qemu-devel] [PATCH 3/4] wakeup: make serial configurable

[Paolo Bonzini]

Il 08/09/2012 09:15, Blue Swirl ha scritto:
>> Preferably some which don't
>> > break on 'qemu -nodefault -device isa-serial,chardev=foo'.
> Add a qdev property? The base address check can't be correct, the
> serial device could be the only one in the board and wired to wakeup
> but still use a different iobase.

Could work, but the default value for the property would still be
"depending on the iobase".

> One way could be to check if chr == serial_hds[0] or rather, pass the
> wakeup reason code from board level based on this check.

That doesn't work for -device.

Paolo

Re: [Qemu-devel] [PATCH v2a] musicpal: Fix flash mapping

[Blue Swirl]

Thanks, applied.

On Sat, Sep 8, 2012 at 9:52 AM, Jan Kiszka  wrote:
> The old arithmetic assumed 32 physical address bits which is no longer
> true for ARM since 3cc0cd61f4.
>
> Signed-off-by: Jan Kiszka 
> ---
>
> Changes in v2a:
> - mark large constant ULL
>
>  hw/musicpal.c |4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/musicpal.c b/hw/musicpal.c
> index ad725b5..f305e21 100644
> --- a/hw/musicpal.c
> +++ b/hw/musicpal.c
> @@ -1583,7 +1583,7 @@ static void musicpal_init(ram_addr_t ram_size,
>   * image is smaller than 32 MB.
>   */
>  #ifdef TARGET_WORDS_BIGENDIAN
> -pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
> +pflash_cfi02_register(0x1ULL-MP_FLASH_SIZE_MAX, NULL,
>"musicpal.flash", flash_size,
>dinfo->bdrv, 0x1,
>(flash_size + 0x) >> 16,
> @@ -1591,7 +1591,7 @@ static void musicpal_init(ram_addr_t ram_size,
>2, 0x00BF, 0x236D, 0x, 0x,
>0x, 0x2AAA, 1);
>  #else
> -pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
> +pflash_cfi02_register(0x1ULL-MP_FLASH_SIZE_MAX, NULL,
>"musicpal.flash", flash_size,
>dinfo->bdrv, 0x1,
>(flash_size + 0x) >> 16,
> --
> 1.7.3.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Blue Swirl]

On Sat, Sep 8, 2012 at 9:28 AM, Alexander Graf  wrote:
>
>
> On 08.09.2012, at 10:06, Blue Swirl  wrote:
>
>> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
>>> On 09/05/2012 10:04 PM, Blue Swirl wrote:

 Reinventing a disassembler for ever growing x86 assembly is
 no fun.
>>>
>>> We can try linking to a disassembler library.  I use udis86 to
>>> disassemble instructions in kvm tracepoints
>>> (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
>>> it's maintained but not heavily so.
>>
>> I think commonality with KVM would be preferred. The library looks
>> neat and based on changelog, more actively developed than BSD DDB.
>>
>>>
>>> Of course for non-x86 we'd need to continue using binutils; this is
>>> about copying code vs. libraries, not about licensing.
>>
>> For most architectures, pre-GPLv3 binutils is good enough since the
>> instruction set does not change anymore. Maybe only PPC and Sparc64
>> still change besides x86. New CPUs types more recent than 2007 will
>> have problems.
>
> Alternatively we could try to run the disassembler in a different process, 
> right?

For qemu.log this would be doable and even improve performance since
only binary data would be transferred.

But for monitor disassembly command x/i it may be too clumsy. There's
some overlap with GDB support, so maybe we could deprecate monitor
disassembly.

>
> Alex
>
>>
>>>
>>>
>>> --
>>> error compiling committee.c: too many arguments to function
>>

[Qemu-devel] [PATCH v2a] musicpal: Fix flash mapping

[Jan Kiszka]

The old arithmetic assumed 32 physical address bits which is no longer
true for ARM since 3cc0cd61f4.

Signed-off-by: Jan Kiszka 
---

Changes in v2a:
- mark large constant ULL

 hw/musicpal.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/musicpal.c b/hw/musicpal.c
index ad725b5..f305e21 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -1583,7 +1583,7 @@ static void musicpal_init(ram_addr_t ram_size,
  * image is smaller than 32 MB.
  */
 #ifdef TARGET_WORDS_BIGENDIAN
-pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
+pflash_cfi02_register(0x1ULL-MP_FLASH_SIZE_MAX, NULL,
   "musicpal.flash", flash_size,
   dinfo->bdrv, 0x1,
   (flash_size + 0x) >> 16,
@@ -1591,7 +1591,7 @@ static void musicpal_init(ram_addr_t ram_size,
   2, 0x00BF, 0x236D, 0x, 0x,
   0x, 0x2AAA, 1);
 #else
-pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
+pflash_cfi02_register(0x1ULL-MP_FLASH_SIZE_MAX, NULL,
   "musicpal.flash", flash_size,
   dinfo->bdrv, 0x1,
   (flash_size + 0x) >> 16,
-- 
1.7.3.4

Re: [Qemu-devel] [PATCH v2] musicpal: Fix flash mapping

[Jan Kiszka]

On 2012-09-08 11:50, Peter Maydell wrote:
> On 8 September 2012 10:48, Jan Kiszka  wrote:
>> The old arithmetic assumed 32 physical address bits which is no longer
>> true for ARM since 3cc0cd61f4.
>>
>> Signed-off-by: Jan Kiszka 
>> ---
>>
>> Changes in v2:
>> - mark large constant ULL
>>
>>  #ifdef TARGET_WORDS_BIGENDIAN
>> -pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
>> +pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
>>"musicpal.flash", flash_size,
> 
> ...wrong version of patch sent?

Grrr...



signature.asc
Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH v2] musicpal: Fix flash mapping

[Peter Maydell]

On 8 September 2012 10:48, Jan Kiszka  wrote:
> The old arithmetic assumed 32 physical address bits which is no longer
> true for ARM since 3cc0cd61f4.
>
> Signed-off-by: Jan Kiszka 
> ---
>
> Changes in v2:
> - mark large constant ULL
>
>  #ifdef TARGET_WORDS_BIGENDIAN
> -pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
> +pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
>"musicpal.flash", flash_size,

...wrong version of patch sent?

-- PMM

[Qemu-devel] [PATCH v2] musicpal: Fix flash mapping

[Jan Kiszka]

The old arithmetic assumed 32 physical address bits which is no longer
true for ARM since 3cc0cd61f4.

Signed-off-by: Jan Kiszka 
---

Changes in v2:
- mark large constant ULL

 hw/musicpal.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/musicpal.c b/hw/musicpal.c
index ad725b5..10c2c16 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -1583,7 +1583,7 @@ static void musicpal_init(ram_addr_t ram_size,
  * image is smaller than 32 MB.
  */
 #ifdef TARGET_WORDS_BIGENDIAN
-pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
+pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
   "musicpal.flash", flash_size,
   dinfo->bdrv, 0x1,
   (flash_size + 0x) >> 16,
@@ -1591,7 +1591,7 @@ static void musicpal_init(ram_addr_t ram_size,
   2, 0x00BF, 0x236D, 0x, 0x,
   0x, 0x2AAA, 1);
 #else
-pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
+pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
   "musicpal.flash", flash_size,
   dinfo->bdrv, 0x1,
   (flash_size + 0x) >> 16,
-- 
1.7.3.4

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 09:29:59AM +, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 9:12 AM, Aurelien Jarno  wrote:
> > On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
> >> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno  
> >> wrote:
> >> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
> >> >> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  
> >> >> wrote:
> >> >> > This patch series improves the TCG optimizer, based on patterns found
> >> >> > while executing various guest. The brcond ad setcond constant folding
> >> >> > are useful especially useful when they are used to avoid some argument
> >> >> > values (e.g. division by 0), and thus can be optimized when this 
> >> >> > argument
> >> >> > is a constant.
> >> >> >
> >> >> > This bring around 0.5% improvement on openssl like benchmarks.
> >> >> >
> >> >> >
> >> >> > Modifications between V1 and V2 following feedback I got:
> >> >> >  - In the first patch, account for the liveness analysis time and
> >> >> >optimizing pass time separately
> >> >> >  - Fixed swith/break in patch 7 to correctly throw an error
> >> >> >  - Added patch 9 to make the code more readable
> >> >> > Other patches are unmodified.
> >> >> >
> >> >> >
> >> >> > Aurelien Jarno (9):
> >> >> >   tcg: improve profiler
> >> >> >   tcg/optimize: split expression simplification
> >> >> >   tcg/optimize: simplify or/xor r, a, 0 cases
> >> >> >   tcg/optimize: simplify and r, a, 0 cases
> >> >> >   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
> >> >>
> >> >> Aren't the above or/and/shift/rot simplifications (and also for
> >> >> example OR with 0xf and XOR register by itself) already
> >> >> handled by tcg/tcg-op.h?
> >> >
> >> > They are handled there when the values are known at decode time. It is
> >> > not the case when the value are propagated in the TB.
> >> >
> >> > For example, this is optimized in tcg/tcg-op.h:
> >> >   ori t0, t1, 0
> >> >
> >> > This is not optimized in tcg/tcg-op.h:
> >> >   movi t2, 0
> >> >   or t0, t1, t2
> >>
> >> I see. Does the optimizer pass then make the tcg/tcg-op.h optimization
> >> redundant, could we do the optimizations only in optimizer?
> >
> > Technically yes. In practice it's a good idea to keep simple
> > optimizations in tcg/tcg-op.h, as they cost less in CPU time than when
> > done later.
> 
> OK. Could there be further optimizations based on tcg/tcg-op.h, for
> example case OR reg, 0x -> mov reg, 0x could be
> rechecked?
> 

Yes this is something we can add. That said I based this patch series on
instructions I have found while running a few targets (arm, ppc, mips,
x86_64) and looking at qemu.log. I haven't seen this one.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Blue Swirl]

On Sat, Sep 8, 2012 at 9:12 AM, Aurelien Jarno  wrote:
> On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
>> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno  wrote:
>> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
>> >> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  
>> >> wrote:
>> >> > This patch series improves the TCG optimizer, based on patterns found
>> >> > while executing various guest. The brcond ad setcond constant folding
>> >> > are useful especially useful when they are used to avoid some argument
>> >> > values (e.g. division by 0), and thus can be optimized when this 
>> >> > argument
>> >> > is a constant.
>> >> >
>> >> > This bring around 0.5% improvement on openssl like benchmarks.
>> >> >
>> >> >
>> >> > Modifications between V1 and V2 following feedback I got:
>> >> >  - In the first patch, account for the liveness analysis time and
>> >> >optimizing pass time separately
>> >> >  - Fixed swith/break in patch 7 to correctly throw an error
>> >> >  - Added patch 9 to make the code more readable
>> >> > Other patches are unmodified.
>> >> >
>> >> >
>> >> > Aurelien Jarno (9):
>> >> >   tcg: improve profiler
>> >> >   tcg/optimize: split expression simplification
>> >> >   tcg/optimize: simplify or/xor r, a, 0 cases
>> >> >   tcg/optimize: simplify and r, a, 0 cases
>> >> >   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
>> >>
>> >> Aren't the above or/and/shift/rot simplifications (and also for
>> >> example OR with 0xf and XOR register by itself) already
>> >> handled by tcg/tcg-op.h?
>> >
>> > They are handled there when the values are known at decode time. It is
>> > not the case when the value are propagated in the TB.
>> >
>> > For example, this is optimized in tcg/tcg-op.h:
>> >   ori t0, t1, 0
>> >
>> > This is not optimized in tcg/tcg-op.h:
>> >   movi t2, 0
>> >   or t0, t1, t2
>>
>> I see. Does the optimizer pass then make the tcg/tcg-op.h optimization
>> redundant, could we do the optimizations only in optimizer?
>
> Technically yes. In practice it's a good idea to keep simple
> optimizations in tcg/tcg-op.h, as they cost less in CPU time than when
> done later.

OK. Could there be further optimizations based on tcg/tcg-op.h, for
example case OR reg, 0x -> mov reg, 0x could be
rechecked?

>
> On the other hand, we can remove such optimizations done in some
> TCG backends as they won't see this kind of ops anymore.
>
>> >
>> >> >   tcg/optimize: swap brcond/setcond arguments when possible
>> >> >   tcg/optimize: add constant folding for setcond
>> >> >   tcg/optimize: add constant folding for brcond
>> >> >   tcg/optimize: fix if/else/break coding style
>> >>
>> >> Otherwise a very nice series.
>> >>
>> >> >
>> >> >  tcg/optimize.c |  179 
>> >> > +++-
>> >> >  tcg/tcg.c  |   12 +++-
>> >> >  tcg/tcg.h  |1 +
>> >> >  3 files changed, 175 insertions(+), 17 deletions(-)
>> >> >
>> >> > --
>> >> > 1.7.10.4
>> >> >
>> >> >
>> >>
>> >>
>> >
>> > --
>> > Aurelien Jarno  GPG: 1024D/F1BCDB73
>> > aurel...@aurel32.net http://www.aurel32.net
>>
>
> --
> Aurelien Jarno  GPG: 1024D/F1BCDB73
> aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Alexander Graf]

On 08.09.2012, at 10:06, Blue Swirl  wrote:

> On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
>> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>> 
>>> Reinventing a disassembler for ever growing x86 assembly is
>>> no fun.
>> 
>> We can try linking to a disassembler library.  I use udis86 to
>> disassemble instructions in kvm tracepoints
>> (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
>> it's maintained but not heavily so.
> 
> I think commonality with KVM would be preferred. The library looks
> neat and based on changelog, more actively developed than BSD DDB.
> 
>> 
>> Of course for non-x86 we'd need to continue using binutils; this is
>> about copying code vs. libraries, not about licensing.
> 
> For most architectures, pre-GPLv3 binutils is good enough since the
> instruction set does not change anymore. Maybe only PPC and Sparc64
> still change besides x86. New CPUs types more recent than 2007 will
> have problems.

Alternatively we could try to run the disassembler in a different process, 
right?

Alex

> 
>> 
>> 
>> --
>> error compiling committee.c: too many arguments to function
> 

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 09:06:52AM +, Blue Swirl wrote:
> On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno  wrote:
> > On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
> >> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  
> >> wrote:
> >> > This patch series improves the TCG optimizer, based on patterns found
> >> > while executing various guest. The brcond ad setcond constant folding
> >> > are useful especially useful when they are used to avoid some argument
> >> > values (e.g. division by 0), and thus can be optimized when this argument
> >> > is a constant.
> >> >
> >> > This bring around 0.5% improvement on openssl like benchmarks.
> >> >
> >> >
> >> > Modifications between V1 and V2 following feedback I got:
> >> >  - In the first patch, account for the liveness analysis time and
> >> >optimizing pass time separately
> >> >  - Fixed swith/break in patch 7 to correctly throw an error
> >> >  - Added patch 9 to make the code more readable
> >> > Other patches are unmodified.
> >> >
> >> >
> >> > Aurelien Jarno (9):
> >> >   tcg: improve profiler
> >> >   tcg/optimize: split expression simplification
> >> >   tcg/optimize: simplify or/xor r, a, 0 cases
> >> >   tcg/optimize: simplify and r, a, 0 cases
> >> >   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
> >>
> >> Aren't the above or/and/shift/rot simplifications (and also for
> >> example OR with 0xf and XOR register by itself) already
> >> handled by tcg/tcg-op.h?
> >
> > They are handled there when the values are known at decode time. It is
> > not the case when the value are propagated in the TB.
> >
> > For example, this is optimized in tcg/tcg-op.h:
> >   ori t0, t1, 0
> >
> > This is not optimized in tcg/tcg-op.h:
> >   movi t2, 0
> >   or t0, t1, t2
> 
> I see. Does the optimizer pass then make the tcg/tcg-op.h optimization
> redundant, could we do the optimizations only in optimizer?

Technically yes. In practice it's a good idea to keep simple
optimizations in tcg/tcg-op.h, as they cost less in CPU time than when
done later.

On the other hand, we can remove such optimizations done in some
TCG backends as they won't see this kind of ops anymore.

> >
> >> >   tcg/optimize: swap brcond/setcond arguments when possible
> >> >   tcg/optimize: add constant folding for setcond
> >> >   tcg/optimize: add constant folding for brcond
> >> >   tcg/optimize: fix if/else/break coding style
> >>
> >> Otherwise a very nice series.
> >>
> >> >
> >> >  tcg/optimize.c |  179 
> >> > +++-
> >> >  tcg/tcg.c  |   12 +++-
> >> >  tcg/tcg.h  |1 +
> >> >  3 files changed, 175 insertions(+), 17 deletions(-)
> >> >
> >> > --
> >> > 1.7.10.4
> >> >
> >> >
> >>
> >>
> >
> > --
> > Aurelien Jarno  GPG: 1024D/F1BCDB73
> > aurel...@aurel32.net http://www.aurel32.net
> 

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH] Add MAINTAINERS entry for leon3

[Blue Swirl]

Thanks, applied.

On Tue, May 22, 2012 at 8:14 AM, Fabien Chouteau  wrote:
>
> Signed-off-by: Fabien Chouteau 
> ---
>  MAINTAINERS |6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b45f075..3d773d3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -387,6 +387,12 @@ M: Blue Swirl 
>  S: Maintained
>  F: hw/sun4u.c
>
> +Leon3
> +M: Fabien Chouteau 
> +S: Maintained
> +F: hw/leon3.c
> +F: hw/grlib*
> +
>  S390 Machines
>  -
>  S390 Virtio
> --
> 1.7.9.5
>

Re: [Qemu-devel] [PATCH] target-sparc: fix fcmp{s, d, q} instructions wrt exception

[Blue Swirl]

Thanks, applied.

On Fri, Sep 7, 2012 at 3:13 PM, Aurelien Jarno  wrote:
> fcmp{s,d,q} instructions are supposed to ignore quiet NaN (contrary to
> the fcmpe{s,d,q} instructions), but the current code is wrongly setting
> the NV exception in that case. Moreover the current code is duplicated:
> first the arguments are checked for NaN to generate an exception, and
> later in case the comparison is unordered (which can only happens if one
> of the argument is a NaN), the same check is done to generate an
> exception.
>
> Fix that by calling clear_float_exceptions() followed by
> check_ieee_exceptions() as for the other floating point instructions.
> Use the _compare_quiet functions for fcmp{s,d,q} and the _compare ones
> for fcmpe{s,d,q}. Simplify the flag setting by not clearing a flag that
> is set the line just below.
>
> This fix allows the math glibc testsuite to pass.
>
> Cc: Blue Swirl 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-sparc/fop_helper.c |   67 
> ++---
>  1 file changed, 27 insertions(+), 40 deletions(-)
>
> diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c
> index 9c64ef8..f4b62a5 100644
> --- a/target-sparc/fop_helper.c
> +++ b/target-sparc/fop_helper.c
> @@ -334,34 +334,28 @@ void helper_fsqrtq(CPUSPARCState *env)
>  }
>
>  #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
> -void glue(helper_, name) (CPUSPARCState *env)
> \
> +void glue(helper_, name) (CPUSPARCState *env)   \
>  {   \
> -env->fsr &= FSR_FTT_NMASK;  \
> -if (E && (glue(size, _is_any_nan)(reg1) ||  \
> -  glue(size, _is_any_nan)(reg2)) && \
> -(env->fsr & FSR_NVM)) { \
> -env->fsr |= FSR_NVC;\
> -env->fsr |= FSR_FTT_IEEE_EXCP;  \
> -helper_raise_exception(env, TT_FP_EXCP);\
> +int ret;\
> +clear_float_exceptions(env);\
> +if (E) {\
> +ret = glue(size, _compare)(reg1, reg2, &env->fp_status);\
> +} else {\
> +ret = glue(size, _compare_quiet)(reg1, reg2,\
> + &env->fp_status);  \
>  }   \
> -switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
> +check_ieee_exceptions(env); \
> +switch (ret) {  \
>  case float_relation_unordered:  \
> -if ((env->fsr & FSR_NVM)) { \
> -env->fsr |= FSR_NVC;\
> -env->fsr |= FSR_FTT_IEEE_EXCP;  \
> -helper_raise_exception(env, TT_FP_EXCP);\
> -} else {\
> -env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
> -env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;\
> -env->fsr |= FSR_NVA;\
> -}   \
> +env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS;\
> +env->fsr |= FSR_NVA;\
>  break;  \
>  case float_relation_less:   \
> -env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
> +env->fsr &= ~(FSR_FCC1) << FS;  \
>  env->fsr |= FSR_FCC0 << FS; \
>  break;  \
>  case float_relation_greater:\
> -env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
> +env->fsr &= ~(FSR_FCC0) << FS;  \
>  env->fsr |= FSR_FCC1 << FS; \
>  break;  \
>  default:\
> @@ -370,34 +364,27 @@ void helper_fsqrtq(CPUSPARCState *env)
>  }   

Re: [Qemu-devel] [PATCH] target-xtensa: fix missing errno codes for mingw32

[Blue Swirl]

Thanks, applied.

On Thu, Sep 6, 2012 at 12:36 AM, Max Filippov  wrote:
> Put the following errno value mappings under #ifdef:
>
> xtensa-semi.c: In function 'errno_h2g':
> xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function)
> xtensa-semi.c:113: error: (Each undeclared identifier is reported only once
> xtensa-semi.c:113: error: for each function it appears in.)
> xtensa-semi.c:113: error: array index in initializer not of integer type
> xtensa-semi.c:113: error: (near initialization for 'guest_errno')
> xtensa-semi.c:124: error: 'ETXTBSY' undeclared (first use in this function)
> xtensa-semi.c:124: error: array index in initializer not of integer type
> xtensa-semi.c:124: error: (near initialization for 'guest_errno')
> xtensa-semi.c:134: error: 'ELOOP' undeclared (first use in this function)
> xtensa-semi.c:134: error: array index in initializer not of integer type
> xtensa-semi.c:134: error: (near initialization for 'guest_errno')
>
> Signed-off-by: Max Filippov 
> ---
>  target-xtensa/xtensa-semi.c |6 ++
>  1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
> index e745bef..52be07a 100644
> --- a/target-xtensa/xtensa-semi.c
> +++ b/target-xtensa/xtensa-semi.c
> @@ -110,7 +110,9 @@ static uint32_t errno_h2g(int host_errno)
>  [ENOMEM]= TARGET_ENOMEM,
>  [EACCES]= TARGET_EACCES,
>  [EFAULT]= TARGET_EFAULT,
> +#ifdef ENOTBLK
>  [ENOTBLK]   = TARGET_ENOTBLK,
> +#endif
>  [EBUSY] = TARGET_EBUSY,
>  [EEXIST]= TARGET_EEXIST,
>  [EXDEV] = TARGET_EXDEV,
> @@ -121,7 +123,9 @@ static uint32_t errno_h2g(int host_errno)
>  [ENFILE]= TARGET_ENFILE,
>  [EMFILE]= TARGET_EMFILE,
>  [ENOTTY]= TARGET_ENOTTY,
> +#ifdef ETXTBSY
>  [ETXTBSY]   = TARGET_ETXTBSY,
> +#endif
>  [EFBIG] = TARGET_EFBIG,
>  [ENOSPC]= TARGET_ENOSPC,
>  [ESPIPE]= TARGET_ESPIPE,
> @@ -131,7 +135,9 @@ static uint32_t errno_h2g(int host_errno)
>  [EDOM]  = TARGET_EDOM,
>  [ERANGE]= TARGET_ERANGE,
>  [ENOSYS]= TARGET_ENOSYS,
> +#ifdef ELOOP
>  [ELOOP] = TARGET_ELOOP,
> +#endif
>  };
>
>  if (host_errno == 0) {
> --
> 1.7.7.6
>

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Blue Swirl]

On Sat, Sep 8, 2012 at 9:01 AM, Aurelien Jarno  wrote:
> On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
>> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  wrote:
>> > This patch series improves the TCG optimizer, based on patterns found
>> > while executing various guest. The brcond ad setcond constant folding
>> > are useful especially useful when they are used to avoid some argument
>> > values (e.g. division by 0), and thus can be optimized when this argument
>> > is a constant.
>> >
>> > This bring around 0.5% improvement on openssl like benchmarks.
>> >
>> >
>> > Modifications between V1 and V2 following feedback I got:
>> >  - In the first patch, account for the liveness analysis time and
>> >optimizing pass time separately
>> >  - Fixed swith/break in patch 7 to correctly throw an error
>> >  - Added patch 9 to make the code more readable
>> > Other patches are unmodified.
>> >
>> >
>> > Aurelien Jarno (9):
>> >   tcg: improve profiler
>> >   tcg/optimize: split expression simplification
>> >   tcg/optimize: simplify or/xor r, a, 0 cases
>> >   tcg/optimize: simplify and r, a, 0 cases
>> >   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
>>
>> Aren't the above or/and/shift/rot simplifications (and also for
>> example OR with 0xf and XOR register by itself) already
>> handled by tcg/tcg-op.h?
>
> They are handled there when the values are known at decode time. It is
> not the case when the value are propagated in the TB.
>
> For example, this is optimized in tcg/tcg-op.h:
>   ori t0, t1, 0
>
> This is not optimized in tcg/tcg-op.h:
>   movi t2, 0
>   or t0, t1, t2

I see. Does the optimizer pass then make the tcg/tcg-op.h optimization
redundant, could we do the optimizations only in optimizer?

>
>> >   tcg/optimize: swap brcond/setcond arguments when possible
>> >   tcg/optimize: add constant folding for setcond
>> >   tcg/optimize: add constant folding for brcond
>> >   tcg/optimize: fix if/else/break coding style
>>
>> Otherwise a very nice series.
>>
>> >
>> >  tcg/optimize.c |  179 
>> > +++-
>> >  tcg/tcg.c  |   12 +++-
>> >  tcg/tcg.h  |1 +
>> >  3 files changed, 175 insertions(+), 17 deletions(-)
>> >
>> > --
>> > 1.7.10.4
>> >
>> >
>>
>>
>
> --
> Aurelien Jarno  GPG: 1024D/F1BCDB73
> aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 08:35:18AM +, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno  wrote:
> > On Sun, Sep 02, 2012 at 05:33:47PM +, Blue Swirl wrote:
> >> Add an explicit CPUState parameter instead of relying on AREG0
> >> and switch to AREG0 free mode.
> >>
> >> Signed-off-by: Blue Swirl 
> >> ---
> >>  configure   |2 +-
> >>  target-cris/Makefile.objs   |2 -
> >>  target-cris/helper.c|4 +-
> >>  target-cris/helper.h|   34 
> >>  target-cris/op_helper.c |   89 
> >> +--
> >>  target-cris/translate.c |   50 ---
> >>  target-cris/translate_v10.c |   22 +-
> >>  7 files changed, 101 insertions(+), 102 deletions(-)
> >>
> >> diff --git a/configure b/configure
> >> index e464d2f..d760e07 100755
> >> --- a/configure
> >> +++ b/configure
> >> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
> >> "$target_dir/Makefile"
> >>
> >>
> >>  case "$target_arch2" in
> >> -  alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* 
> >> | unicore32 | x86_64 | xtensa* | ppc*)
> >> +  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
> >> sparc* | unicore32 | x86_64 | xtensa* | ppc*)
> >>  echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
> >>;;
> >>  esac
> >> diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
> >> index 4b09e8c..afb87bc 100644
> >> --- a/target-cris/Makefile.objs
> >> +++ b/target-cris/Makefile.objs
> >> @@ -1,4 +1,2 @@
> >>  obj-y += translate.o op_helper.o helper.o cpu.o
> >>  obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
> >> -
> >> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
> >> diff --git a/target-cris/helper.c b/target-cris/helper.c
> >> index bfbc29e..1bdb7e2 100644
> >> --- a/target-cris/helper.c
> >> +++ b/target-cris/helper.c
> >> @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
> >>   }
> >>
> >>   /* Now that we are in kernel mode, load the handlers address.  */
> >> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> >> +env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> >>   env->locked_irq = 1;
> >>   env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
> >>
> >> @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
> >>   /* Now that we are in kernel mode, load the handlers address.
> >>  This load may not fault, real hw leaves that behaviour as
> >>  undefined.  */
> >> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
> >> +env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
> >>
> >>   /* Clear the excption_index to avoid spurios hw_aborts for recursive
> >>  bus faults.  */
> >> diff --git a/target-cris/helper.h b/target-cris/helper.h
> >> index 093063a..b575524 100644
> >> --- a/target-cris/helper.h
> >> +++ b/target-cris/helper.h
> >> @@ -1,26 +1,26 @@
> >>  #include "def-helper.h"
> >>
> >> -DEF_HELPER_1(raise_exception, void, i32)
> >> -DEF_HELPER_1(tlb_flush_pid, void, i32)
> >> -DEF_HELPER_1(spc_write, void, i32)
> >> +DEF_HELPER_2(raise_exception, void, env, i32)
> >> +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
> >> +DEF_HELPER_2(spc_write, void, env, i32)
> >>  DEF_HELPER_3(dump, void, i32, i32, i32)
> >> -DEF_HELPER_0(rfe, void);
> >> -DEF_HELPER_0(rfn, void);
> >> +DEF_HELPER_1(rfe, void, env);
> >> +DEF_HELPER_1(rfn, void, env);
> >>
> >> -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
> >> -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
> >> +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
> >> +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
> >>
> >>  DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
> >> -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
> >> +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
> >>
> >> -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, 
> >> i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, 
> >> i32, i32)
> >> -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, 
> >> i32, i32)
> >> -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
> >> -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
> >> -DEF_HELPER_0(evaluate_flags, void)
> >> -DEF_HELPER_0(top_evaluate_flags, void)
> >> +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, 
> >> i32, i32)
> >> +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, 
> >> i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, 
> >> i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, 
> >> i32, i32, i32)
> >> +DEF_HELPER_FLAGS_5(evaluat

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Aurelien Jarno]

On Sat, Sep 08, 2012 at 08:18:50AM +, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  wrote:
> > This patch series improves the TCG optimizer, based on patterns found
> > while executing various guest. The brcond ad setcond constant folding
> > are useful especially useful when they are used to avoid some argument
> > values (e.g. division by 0), and thus can be optimized when this argument
> > is a constant.
> >
> > This bring around 0.5% improvement on openssl like benchmarks.
> >
> >
> > Modifications between V1 and V2 following feedback I got:
> >  - In the first patch, account for the liveness analysis time and
> >optimizing pass time separately
> >  - Fixed swith/break in patch 7 to correctly throw an error
> >  - Added patch 9 to make the code more readable
> > Other patches are unmodified.
> >
> >
> > Aurelien Jarno (9):
> >   tcg: improve profiler
> >   tcg/optimize: split expression simplification
> >   tcg/optimize: simplify or/xor r, a, 0 cases
> >   tcg/optimize: simplify and r, a, 0 cases
> >   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
> 
> Aren't the above or/and/shift/rot simplifications (and also for
> example OR with 0xf and XOR register by itself) already
> handled by tcg/tcg-op.h?

They are handled there when the values are known at decode time. It is
not the case when the value are propagated in the TB.

For example, this is optimized in tcg/tcg-op.h:
  ori t0, t1, 0 

This is not optimized in tcg/tcg-op.h:
  movi t2, 0
  or t0, t1, t2

> >   tcg/optimize: swap brcond/setcond arguments when possible
> >   tcg/optimize: add constant folding for setcond
> >   tcg/optimize: add constant folding for brcond
> >   tcg/optimize: fix if/else/break coding style
> 
> Otherwise a very nice series.
> 
> >
> >  tcg/optimize.c |  179 
> > +++-
> >  tcg/tcg.c  |   12 +++-
> >  tcg/tcg.h  |1 +
> >  3 files changed, 175 insertions(+), 17 deletions(-)
> >
> > --
> > 1.7.10.4
> >
> >
> 
> 

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

Re: [Qemu-devel] [PATCH] musicpal: Fix flash mapping

[Jan Kiszka]

On 2012-09-08 10:44, Blue Swirl wrote:
> On Fri, Sep 7, 2012 at 3:25 PM, Peter Maydell  
> wrote:
>> On 7 September 2012 15:53, Jan Kiszka  wrote:
>>> On 2012-09-07 16:41, Peter Maydell wrote:
 On 7 September 2012 00:03, Jan Kiszka  wrote:
> +pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,

 I don't think this will compile on a 32 bit system, will it?
 You probably want an ULL suffix.
>>>
>>> It does as the result always fits in 32 bits. But I can add that if you
>>> prefer.
>>
>> I think I had a misconception of this bit of the C standard.
>> C will pick a type big enough to fit the constant value (which
>> will in this case be a 64 bit type of some kind), even without
>> an ULL suffix. So you're right, it's OK.
> 
> GCC disagrees:
> $ cat u64.c
> unsigned int i = 0x1 - 1;
> $ gcc -m32 -Wall -c u64.c
> u64.c:1: warning: integer constant is too large for 'long' type

Obviously depends on the compiler version or configuration, mine (4.5
still) does not. I'll send v2 to make them all happy.

Jan




signature.asc
Description: OpenPGP digital signature

Re: [Qemu-devel] [PATCH] musicpal: Fix flash mapping

[Blue Swirl]

On Fri, Sep 7, 2012 at 3:25 PM, Peter Maydell  wrote:
> On 7 September 2012 15:53, Jan Kiszka  wrote:
>> On 2012-09-07 16:41, Peter Maydell wrote:
>>> On 7 September 2012 00:03, Jan Kiszka  wrote:
 +pflash_cfi02_register(0x1-MP_FLASH_SIZE_MAX, NULL,
>>>
>>> I don't think this will compile on a 32 bit system, will it?
>>> You probably want an ULL suffix.
>>
>> It does as the result always fits in 32 bits. But I can add that if you
>> prefer.
>
> I think I had a misconception of this bit of the C standard.
> C will pick a type big enough to fit the constant value (which
> will in this case be a 64 bit type of some kind), even without
> an ULL suffix. So you're right, it's OK.

GCC disagrees:
$ cat u64.c
unsigned int i = 0x1 - 1;
$ gcc -m32 -Wall -c u64.c
u64.c:1: warning: integer constant is too large for 'long' type

Clang doesn't care even with --all-warnings:
$ clang -m32 -Wall --all-warnings -c u64.c

>
> Reviewed-by: Peter Maydell 
>
> -- PMM
>

Re: [Qemu-devel] [PATCH 18/21] target-cris: switch to AREG0 free mode

[Blue Swirl]

On Fri, Sep 7, 2012 at 2:18 PM, Aurelien Jarno  wrote:
> On Sun, Sep 02, 2012 at 05:33:47PM +, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl 
>> ---
>>  configure   |2 +-
>>  target-cris/Makefile.objs   |2 -
>>  target-cris/helper.c|4 +-
>>  target-cris/helper.h|   34 
>>  target-cris/op_helper.c |   89 
>> +--
>>  target-cris/translate.c |   50 ---
>>  target-cris/translate_v10.c |   22 +-
>>  7 files changed, 101 insertions(+), 102 deletions(-)
>>
>> diff --git a/configure b/configure
>> index e464d2f..d760e07 100755
>> --- a/configure
>> +++ b/configure
>> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
>> "$target_dir/Makefile"
>>
>>
>>  case "$target_arch2" in
>> -  alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | 
>> unicore32 | x86_64 | xtensa* | ppc*)
>> +  alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | or32 | s390x | 
>> sparc* | unicore32 | x86_64 | xtensa* | ppc*)
>>  echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>>;;
>>  esac
>> diff --git a/target-cris/Makefile.objs b/target-cris/Makefile.objs
>> index 4b09e8c..afb87bc 100644
>> --- a/target-cris/Makefile.objs
>> +++ b/target-cris/Makefile.objs
>> @@ -1,4 +1,2 @@
>>  obj-y += translate.o op_helper.o helper.o cpu.o
>>  obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/target-cris/helper.c b/target-cris/helper.c
>> index bfbc29e..1bdb7e2 100644
>> --- a/target-cris/helper.c
>> +++ b/target-cris/helper.c
>> @@ -151,7 +151,7 @@ static void do_interruptv10(CPUCRISState *env)
>>   }
>>
>>   /* Now that we are in kernel mode, load the handlers address.  */
>> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
>> +env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>>   env->locked_irq = 1;
>>   env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
>>
>> @@ -233,7 +233,7 @@ void do_interrupt(CPUCRISState *env)
>>   /* Now that we are in kernel mode, load the handlers address.
>>  This load may not fault, real hw leaves that behaviour as
>>  undefined.  */
>> - env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
>> +env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
>>
>>   /* Clear the excption_index to avoid spurios hw_aborts for recursive
>>  bus faults.  */
>> diff --git a/target-cris/helper.h b/target-cris/helper.h
>> index 093063a..b575524 100644
>> --- a/target-cris/helper.h
>> +++ b/target-cris/helper.h
>> @@ -1,26 +1,26 @@
>>  #include "def-helper.h"
>>
>> -DEF_HELPER_1(raise_exception, void, i32)
>> -DEF_HELPER_1(tlb_flush_pid, void, i32)
>> -DEF_HELPER_1(spc_write, void, i32)
>> +DEF_HELPER_2(raise_exception, void, env, i32)
>> +DEF_HELPER_2(tlb_flush_pid, void, env, i32)
>> +DEF_HELPER_2(spc_write, void, env, i32)
>>  DEF_HELPER_3(dump, void, i32, i32, i32)
>> -DEF_HELPER_0(rfe, void);
>> -DEF_HELPER_0(rfn, void);
>> +DEF_HELPER_1(rfe, void, env);
>> +DEF_HELPER_1(rfn, void, env);
>>
>> -DEF_HELPER_2(movl_sreg_reg, void, i32, i32)
>> -DEF_HELPER_2(movl_reg_sreg, void, i32, i32)
>> +DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32)
>> +DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32)
>>
>>  DEF_HELPER_FLAGS_1(lz, TCG_CALL_PURE, i32, i32);
>> -DEF_HELPER_FLAGS_3(btst, TCG_CALL_PURE, i32, i32, i32, i32);
>> +DEF_HELPER_FLAGS_4(btst, TCG_CALL_PURE, i32, env, i32, i32, i32);
>>
>> -DEF_HELPER_FLAGS_3(evaluate_flags_muls, TCG_CALL_PURE, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_3(evaluate_flags_mulu, TCG_CALL_PURE, i32, i32, i32, i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_mcp, TCG_CALL_PURE, i32, i32, i32, i32, 
>> i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_alu_4, TCG_CALL_PURE, i32, i32, i32, i32, 
>> i32)
>> -DEF_HELPER_FLAGS_4(evaluate_flags_sub_4, TCG_CALL_PURE, i32, i32, i32, i32, 
>> i32)
>> -DEF_HELPER_FLAGS_2(evaluate_flags_move_4, TCG_CALL_PURE, i32, i32, i32)
>> -DEF_HELPER_FLAGS_2(evaluate_flags_move_2, TCG_CALL_PURE, i32, i32, i32)
>> -DEF_HELPER_0(evaluate_flags, void)
>> -DEF_HELPER_0(top_evaluate_flags, void)
>> +DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_PURE, i32, env, i32, i32, 
>> i32)
>> +DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_PURE, i32, env, i32, i32, 
>> i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_mcp, TCG_CALL_PURE, i32, env, i32, i32, 
>> i32, i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_alu_4, TCG_CALL_PURE, i32, env, i32, i32, 
>> i32, i32)
>> +DEF_HELPER_FLAGS_5(evaluate_flags_sub_4, TCG_CALL_PURE, i32, env, i32, i32, 
>> i32, i32)
>> +DEF_HELPER_FLAGS_3(evaluate_flags_move_4, TCG_CALL_PURE, i32, env, i32, i32)
>> +DEF_HELPER_FLAGS_3(evaluate_flags_move_2, TCG_CALL_PURE, i32, env, i32, i32)
>> +DEF_HELPER_1(evaluate_flags, void, env)
>> +DEF_HELPER_1

Re: [Qemu-devel] [PATCH v2 0/9] Improve TCG optimizer

[Blue Swirl]

On Fri, Sep 7, 2012 at 1:16 PM, Aurelien Jarno  wrote:
> This patch series improves the TCG optimizer, based on patterns found
> while executing various guest. The brcond ad setcond constant folding
> are useful especially useful when they are used to avoid some argument
> values (e.g. division by 0), and thus can be optimized when this argument
> is a constant.
>
> This bring around 0.5% improvement on openssl like benchmarks.
>
>
> Modifications between V1 and V2 following feedback I got:
>  - In the first patch, account for the liveness analysis time and
>optimizing pass time separately
>  - Fixed swith/break in patch 7 to correctly throw an error
>  - Added patch 9 to make the code more readable
> Other patches are unmodified.
>
>
> Aurelien Jarno (9):
>   tcg: improve profiler
>   tcg/optimize: split expression simplification
>   tcg/optimize: simplify or/xor r, a, 0 cases
>   tcg/optimize: simplify and r, a, 0 cases
>   tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases

Aren't the above or/and/shift/rot simplifications (and also for
example OR with 0xf and XOR register by itself) already
handled by tcg/tcg-op.h?

>   tcg/optimize: swap brcond/setcond arguments when possible
>   tcg/optimize: add constant folding for setcond
>   tcg/optimize: add constant folding for brcond
>   tcg/optimize: fix if/else/break coding style

Otherwise a very nice series.

>
>  tcg/optimize.c |  179 
> +++-
>  tcg/tcg.c  |   12 +++-
>  tcg/tcg.h  |1 +
>  3 files changed, 175 insertions(+), 17 deletions(-)
>
> --
> 1.7.10.4
>
>

Re: [Qemu-devel] [PATCH 1/3] target-arm: convert void helpers

[Blue Swirl]

On Thu, Sep 6, 2012 at 7:00 PM, Peter Maydell  wrote:
> On 4 September 2012 21:48, Peter Maydell  wrote:
>> On 4 September 2012 21:37, Blue Swirl  wrote:
>>> Add an explicit CPUState parameter instead of relying on AREG0.
>>>
>>> For easier review, convert only op helpers which don't return any value.
>>>
>>> Signed-off-by: Blue Swirl 
>>
>> Reviewed-by: Peter Maydell 
>>
>> Thanks for splitting these up, it helped a lot.
>
> Forgot to ask, are you planning to apply these directly?
> I'm happy to take them via the target-arm tree but I imagine
> there'll be merge conflicts on that line in configure if we
> do that for every target...

That was my original plan (which I didn't spell out, mea culpa), but
since Alex already took the s390x patches via his tree, we'll see what
will happen with the commit order.

>
> thanks
> -- PMM

Re: [Qemu-devel] [PATCH 01/21] target-s390x: fix style

[Blue Swirl]

On Thu, Sep 6, 2012 at 6:33 PM, Alexander Graf  wrote:
>
> On 02.09.2012, at 13:33, Blue Swirl wrote:
>
>> Before splitting op_helper.c and helper.c in the next patches,
>> fix style issues. No functional changes.
>>
>> Replace also GCC specific __FUNCTION__ with
>> standard __func__.
>>
>> Don't init static variable (cpu_s390x_init:inited) with 0.
>>
>> Signed-off-by: Blue Swirl 
>
> Thanks, applied [01-12] to s390-next.

Please send a pull request soon, as the first set in the series it is
blocking the rest.

>
>
> Alex
>

Re: [Qemu-devel] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Blue Swirl]

On Thu, Sep 6, 2012 at 8:44 AM, Avi Kivity  wrote:
> On 09/05/2012 10:04 PM, Blue Swirl wrote:
>>
>> Reinventing a disassembler for ever growing x86 assembly is
>> no fun.
>
> We can try linking to a disassembler library.  I use udis86 to
> disassemble instructions in kvm tracepoints
> (http://udis86.git.sourceforge.net/git/gitweb.cgi?p=udis86/udis86;a=shortlog),
> it's maintained but not heavily so.

I think commonality with KVM would be preferred. The library looks
neat and based on changelog, more actively developed than BSD DDB.

>
> Of course for non-x86 we'd need to continue using binutils; this is
> about copying code vs. libraries, not about licensing.

For most architectures, pre-GPLv3 binutils is good enough since the
instruction set does not change anymore. Maybe only PPC and Sparc64
still change besides x86. New CPUs types more recent than 2007 will
have problems.

>
>
> --
> error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH v3 4/4] kvm: i386: Add classic PCI device assignment

[Blue Swirl]

On Thu, Sep 6, 2012 at 4:06 PM, Andreas Färber  wrote:
> Am 06.09.2012 10:44, schrieb Jan Kiszka:
>> On 2012-08-30 20:30, Jan Kiszka wrote:
>>> This adds PCI device assignment for i386 targets using the classic KVM
>>> interfaces. This version is 100% identical to what is being maintained
>>> in qemu-kvm for several years and is supported by libvirt as well. It is
>>> expected to remain relevant for another couple of years until kernels
>>> without full-features and performance-wise equivalent VFIO support are
>>> obsolete.
>>>
>>> A refactoring to-do that should be done in-tree is to model MSI and
>>> MSI-X support via the generic PCI layer, similar to what VFIO is already
>>> doing for MSI-X. This should improve the correctness and clean up the
>>> code from duplicate logic.
>>>
>>> Signed-off-by: Jan Kiszka 
>>> ---
>>>
>>> Changes in v3:
>>>  - addressed comment by Peter (changed device name to kvm-pci-assign +
>>>alias)
>>>  - addressed (most) comments by Michael
>>>  - fixed INT pin regression
>>
>> Does someone _disagree_ that there are no open (and reasonably solvable)
>> issues and that this can now be merged through uq/master?
>
> My implicit suggestion was to add a notice that new patch contributions
> to the file from date -mm-dd on would be declared GPLv2+, as Paolo
> has done elsewhere. That would limit the amount of people to ask for a
> potential relicensing attempt.

+1

>
> For the record, Anthony explained on IRC that the code originated from
> Xen originally and thus qemu-kvm.git does not contain the full history
> anyway and that pulling in the Mercurial file history and replaying the
> KVM history on top was too difficult, therefore this patch with a single
> SoB by Jan.
>
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/4] kvm: i386: Add classic PCI device assignment

[Blue Swirl]

On Thu, Sep 6, 2012 at 3:42 AM, Alexander Graf  wrote:
>
> On 05.09.2012, at 15:38, Blue Swirl wrote:
>
>> On Wed, Sep 5, 2012 at 7:22 PM, Anthony Liguori  
>> wrote:
>>> Blue Swirl  writes:
>>>
 On Wed, Sep 5, 2012 at 3:41 PM, Anthony Liguori  
 wrote:
> Avi Kivity  writes:
>
>> On 09/05/2012 12:00 AM, Anthony Liguori wrote:

 Why? The way this is being submitted I don't see why we should treat
 Jan's patch any different from a patch by IBM or Samsung where we've
 asked folks to fix the license to comply with what I thought was our 
 new
 policy (it does not even contain a from-x-on-GPLv2+ notice).
>>>
>>> Asking is one thing.  Requiring is another.
>>>
>>> I would prefer that people submitted GPLv2+, but I don't think it should
>>> be a hard requirement.  It means, among other things, that we cannot
>>> accept most code that originates from the Linux kernel.
>>
>> We could extend this to "require unless there is a reason to grant an
>> exception" if we wanted to (not saying I know whether we want to or
>> not).
>
> I don't want QEMU to be GPLv3.  I don't like the terms of the GPLv3.
>
> I don't mind GPLv2+, if people want to share code from QEMU in GPLv3
> projects, GPLv2+ enables that.

 The advantage of 100% GPLv2+ (or other GPLv3 compatible) would be that
 QEMU could share code from GPLv3 projects, specifically latest
 binutils. Reinventing a disassembler for ever growing x86 assembly is
 no fun.
>>>
>>> But we can't share code with Linux (like for virtio).
>>
>> It's a tradeoff between reimplementing disassembler without using
>> binutils vs. reimplementing virtio without using Linux. Both have
>> their problems and both are growing areas. Disassembler is a bit
>> smaller and the basic function does not ever change.
>>
>>>
>>> Yes, the GPLv3 sucks and FSF screwed up massively not making it v2
>>> compatible.
>>
>> I sort of agree. They had their reasons, of course. Too bad binutils
>> licensing is fully controlled by FSF, for us it would be enough if
>> they had some sort of dual licensing scheme (GPLv3 + BSD for example)
>> in place.
>
> What do the BSD guys do here? They want to have a disassembler too that works 
> across all different sorts of architectures, no?

There's at least GDB and DDD. The DDB kernel debugger contains a
disassembler for several architectures:
http://fxr.watson.org/fxr/ident?v=NETBSD&i=db_disasm

At least cris, lm32, microblaze, unicore32 and s390x are still missing
and I don't know if sh3 equals sh4. For some of those, maybe current
code from old binutils will be good enough forever.

It looks like the most recent change for x86 is from 2009 and there's
no support for even MMX so it does not look very potential way to
handle the x86 instruction set growth.

>
>
> Alex
>

Re: [Qemu-devel] [PATCH 17/21] target-microblaze: switch to AREG0 free mode

[Blue Swirl]

On Thu, Sep 6, 2012 at 3:38 PM, Aurelien Jarno  wrote:
> On Sun, Sep 02, 2012 at 05:33:46PM +, Blue Swirl wrote:
>> Add an explicit CPUState parameter instead of relying on AREG0
>> and switch to AREG0 free mode.
>>
>> Signed-off-by: Blue Swirl 
>> ---
>>  configure   |2 +-
>>  target-microblaze/Makefile.objs |2 -
>>  target-microblaze/helper.h  |   48 
>>  target-microblaze/op_helper.c   |  115 
>> ++-
>>  target-microblaze/translate.c   |   56 +++-
>>  5 files changed, 108 insertions(+), 115 deletions(-)
>>
>> diff --git a/configure b/configure
>> index efb5014..e464d2f 100755
>> --- a/configure
>> +++ b/configure
>> @@ -3829,7 +3829,7 @@ symlink "$source_path/Makefile.target" 
>> "$target_dir/Makefile"
>>
>>
>>  case "$target_arch2" in
>> -  alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | 
>> x86_64 | xtensa* | ppc*)
>> +  alpha | arm* | i386 | lm32 | m68k | microblaze* | or32 | s390x | sparc* | 
>> unicore32 | x86_64 | xtensa* | ppc*)
>>  echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
>>;;
>>  esac
>> diff --git a/target-microblaze/Makefile.objs 
>> b/target-microblaze/Makefile.objs
>> index 4b09e8c..afb87bc 100644
>> --- a/target-microblaze/Makefile.objs
>> +++ b/target-microblaze/Makefile.objs
>> @@ -1,4 +1,2 @@
>>  obj-y += translate.o op_helper.o helper.o cpu.o
>>  obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
>> -
>> -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
>> diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
>> index 9dcfb0f..a1a732c 100644
>> --- a/target-microblaze/helper.h
>> +++ b/target-microblaze/helper.h
>> @@ -1,39 +1,39 @@
>>  #include "def-helper.h"
>>
>> -DEF_HELPER_1(raise_exception, void, i32)
>> -DEF_HELPER_0(debug, void)
>> +DEF_HELPER_2(raise_exception, void, env, i32)
>> +DEF_HELPER_1(debug, void, env)
>>  DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, 
>> i32)
>>  DEF_HELPER_2(cmp, i32, i32, i32)
>>  DEF_HELPER_2(cmpu, i32, i32, i32)
>>  DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
>>
>> -DEF_HELPER_2(divs, i32, i32, i32)
>> -DEF_HELPER_2(divu, i32, i32, i32)
>> -
>> -DEF_HELPER_2(fadd, i32, i32, i32)
>> -DEF_HELPER_2(frsub, i32, i32, i32)
>> -DEF_HELPER_2(fmul, i32, i32, i32)
>> -DEF_HELPER_2(fdiv, i32, i32, i32)
>> -DEF_HELPER_1(flt, i32, i32)
>> -DEF_HELPER_1(fint, i32, i32)
>> -DEF_HELPER_1(fsqrt, i32, i32)
>> -
>> -DEF_HELPER_2(fcmp_un, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_lt, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_eq, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_le, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_gt, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_ne, i32, i32, i32)
>> -DEF_HELPER_2(fcmp_ge, i32, i32, i32)
>> +DEF_HELPER_3(divs, i32, env, i32, i32)
>> +DEF_HELPER_3(divu, i32, env, i32, i32)
>> +
>> +DEF_HELPER_3(fadd, i32, env, i32, i32)
>> +DEF_HELPER_3(frsub, i32, env, i32, i32)
>> +DEF_HELPER_3(fmul, i32, env, i32, i32)
>> +DEF_HELPER_3(fdiv, i32, env, i32, i32)
>> +DEF_HELPER_2(flt, i32, env, i32)
>> +DEF_HELPER_2(fint, i32, env, i32)
>> +DEF_HELPER_2(fsqrt, i32, env, i32)
>> +
>> +DEF_HELPER_3(fcmp_un, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_lt, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_eq, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_le, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_gt, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_ne, i32, env, i32, i32)
>> +DEF_HELPER_3(fcmp_ge, i32, env, i32, i32)
>>
>>  DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32)
>>  #if !defined(CONFIG_USER_ONLY)
>> -DEF_HELPER_1(mmu_read, i32, i32)
>> -DEF_HELPER_2(mmu_write, void, i32, i32)
>> +DEF_HELPER_2(mmu_read, i32, env, i32)
>> +DEF_HELPER_3(mmu_write, void, env, i32, i32)
>>  #endif
>>
>> -DEF_HELPER_4(memalign, void, i32, i32, i32, i32)
>> -DEF_HELPER_1(stackprot, void, i32)
>> +DEF_HELPER_5(memalign, void, env, i32, i32, i32, i32)
>> +DEF_HELPER_2(stackprot, void, env, i32)
>>
>>  DEF_HELPER_2(get, i32, i32, i32)
>>  DEF_HELPER_3(put, void, i32, i32, i32)
>> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
>> index 3b1f072..c9789f4 100644
>> --- a/target-microblaze/op_helper.c
>> +++ b/target-microblaze/op_helper.c
>> @@ -20,7 +20,6 @@
>>
>>  #include 
>>  #include "cpu.h"
>> -#include "dyngen-exec.h"
>>  #include "helper.h"
>>  #include "host-utils.h"
>>
>> @@ -42,17 +41,12 @@
>>  /* Try to fill the TLB and return an exception if error. If retaddr is
>> NULL, it means that the function was called in C code (i.e. not
>> from generated code or from helper.c) */
>> -/* XXX: fix it to restore all registers */
>> -void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int 
>> mmu_idx,
>> +void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
>>uintptr_t retaddr)
>>  {
>>  TranslationBlock *tb;
>> -CPUMBState *saved_env;
>>  int ret;
>>
>> -saved_env = env;
>> -env = env

Re: [Qemu-devel] [PATCH] CHECKPATCH

[Blue Swirl]

On Thu, Sep 6, 2012 at 3:32 PM, Avi Kivity  wrote:
> On 09/02/2012 01:51 PM, Blue Swirl wrote:
>> I've used the following snippet to check what happens with the last 100 
>> commits:
>> for i in '' 1 2 3 4 5 6 7 8 9; do for j in 0 1 2 3 4 5 6 7 8 9; do
>> echo $i$j; git show HEAD~$i$j >/tmp/a; clear;head -20 /tmp/a;
>> ./scripts/checkpatch.pl --root=. /tmp/a; read foo; done; done
>>
>> Sadly, it also shows how much stuff gets committed without checking,
>> and on the other hand, the amount of false alarms.
>
> Maintainers should add a checkpatch invocation as a git hook (advisory
> only), this could reduce the amount of violations getting into the tree.

I'd agree. But it looks like we have a few maintainers who actively
oppose CODING_STYLE and HACKING and don't reject patches with
violations or even inform the submitters about problems. The next
level is that we have committers who commit pulls without checking,
but I think the  responsibility for checking patches for all possible
aspects (especially since there are real, deep, technical and
architectural issues to consider besides minor issues like style)
should not be duplicated at every level.

>
>
> --
> error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH 3/4] wakeup: make serial configurable

[Blue Swirl]

On Thu, Sep 6, 2012 at 10:47 AM, Gerd Hoffmann  wrote:
> On 09/06/12 09:48, Peter Maydell wrote:
>> On 6 September 2012 08:42, Gerd Hoffmann  wrote:
>>> @@ -789,6 +790,13 @@ static int serial_isa_initfn(ISADevice *dev)
>>>  isa->isairq = isa_serial_irq[isa->index];
>>>  index++;
>>>
>>> +if (isa->iobase == 0x3f8) {
>>> +s->reason = QEMU_WAKEUP_REASON_GPE_a;
>>> +s->wakeup = 1;
>>> +} else {
>>> +s->reason = QEMU_WAKEUP_REASON_OTHER;
>>> +}
>>> +
>>
>> It seems a bit odd that this is done in the ISA serial model
>> itself and not by the next level up wiring up some output
>> of the ISA serial device to some appropriate input...
>
> Suggestions how to do that are welcome.  Preferably some which don't
> break on 'qemu -nodefault -device isa-serial,chardev=foo'.

Add a qdev property? The base address check can't be correct, the
serial device could be the only one in the board and wired to wakeup
but still use a different iobase.

One way could be to check if chr == serial_hds[0] or rather, pass the
wakeup reason code from board level based on this check.

>
> cheers,
>   Gerd
>
>

Re: [Qemu-devel] [PATCH v2 0/4] CHECKPATCH: Add warning for single else statement.

[Blue Swirl]

On Thu, Sep 6, 2012 at 10:32 AM, Andreas Färber  wrote:
> Am 05.09.2012 21:46, schrieb Blue Swirl:
>> Thanks, applied all.
>
> Question: Are additions to checkpatch.pl supposed to be in QEMU Coding
> Style as done here? Do you plan to convert it consistently then?
> checkpatch.pl uses tabs consistently, making checkpatch.pl complain. ;)
> The alternative would be to stick to upstream formatting and exempt
> checkpatch.pl from its own checks.

I'd suppose checkpatch.pl can't check Perl,  Python or sh syntax so we
could try to limit some of the checks to C files only. For example
tabs are mandatory as the initial character for Makefile rules, we
could in theory demand spaces otherwise but I guess nobody cares
enough to add checks for this.

>
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg