Re: [Qemu-devel] [PATCH] Versatile Express: add modelling of NOR flash
On 09/05/2012 09:07 PM, Francesco Lavra wrote: Hi, On 09/05/2012 10:47 AM, Peter Maydell wrote: On 5 September 2012 06:16, Stefan Weil s...@weilnetz.de wrote: Am 04.09.2012 19:08, schrieb Francesco Lavra: /* VE_NORFLASH0ALIAS: not modelled */ What about that alias? It's not difficult to add it, too. Just look for memory_region_init_alias in the code to see how it is done (hw/mips_malta.c has an alias region for flash). It's painful because you might also have to add the logic for letting the guest map and unmap the alias (which implies implementing a whole section of the A15 board we don't currently bother with, the SCC registers). I'd need to check the board documentation more carefully to see if we can get away with always mapping that area as the flash alias. Documentation at http://infocenter.arm.com/help/topic/com.arm.doc.ddi0503c/CHDEFDJF.html says that the entire first 512 MB can be mapped to either SMC (which is the default) or AXI, so if AXI is selected neither of the 2 flash banks is visible. Also, the same doc says that it's possible to map either NOR0 (default) or NOR1 to the address 0x. This implies that in the A Series memory map VE_NORFLASH0 should be at 0x0800 and VE_NORFLASH0ALIAS at 0x, not the other way around (by the way, this is also how U-Boot defines the memory for the A5 CoreTile). Maybe worth a patch? If we can get way with always aliasing to flash 0, the actual implementation of the alias is made difficult by the fact that memory_region_init_alias() needs the MemoryRegion of the aliased memory, and the daughterboard-specific initialization is done in a function which doesn't have access to that MemoryRegion. So we can either: 1. move initialization of common flash modelling before daughterboard-specific initialization and pass the relevant MemoryRegion to the daughterboard-specific init function 2. add another field to VEDBoardInfo which tells if the alias capability is implemented, and use this info in vexpress_common_init() to define the alias if appropriate Or we can simply deem this alias not worth the trouble, which is what I thought before sending the patch... Let me know your thoughts. (Also we'd need to fix the current problem with the motherboard address map arrays that there's no way to distinguish peripheral not present on this board from peripheral at address 0, since the A9 board doesn't have the flash alias.) More to the point, this is the third attempt at doing this. Previously Liming Wang sent a patch: http://patchwork.ozlabs.org/patch/147905/ and Jagan sent a two-patch set: http://patchwork.ozlabs.org/patch/171812/ http://patchwork.ozlabs.org/patch/171814/ both of which failed in the code review stage. Francesco, can you check that you haven't fallen into any of the same problems they did, please? I read the reviews of previous attempts, and in fact there is a fix which can be easily done, i.e. replacing the calls to drive_get() with drive_get_next(). Will do that in v2, but first the above points need to be addressed. Thanks, Francesco Ping? http://thread.gmane.org/gmane.comp.emulators.qemu/168461
Re: [Qemu-devel] [PATCH] Basic support for ARM A15 architectured (cp15) timers
Thanks for the feedback!
I should probably point out (as I wrote in my initial mail) that this is just a
prototype - a quick n dirty hack to get Linux up and running with the arch
timers. It is very true that I'm not following the QEMU coding standard (I must
admit that haven't even read it).
The background is that I wanted to run QEMU and the A15 CoreTile side by side
with as similar configuration as possible. And the missing A15 timers was kind
of stopping me, so I had to work around that. (For that reason, I tried to keep
most of my additions in a single file and not to clutter the entire source
tree). At the same time I saw that someone asked for these timers on the
mailing list some month ago. So I thought that I could as well share my results.
That said, I'm very grateful that you still took the time to actually review
the code, and I will try to improve it. I have fixed some minor issues that
prevented me to run multicore so far. (My eventual goal is to run as close as
possible to the real 2xA15+3xA7 CoreTile that I try to mimic).
However, being a QEMU newbie I have a couple of questions related to the right
way of implementing this:
1) What is considered to be part of the core and what is considered to be a
device external to the core? To me, it looks like co-processor functionality in
general is considered to be part of the core (implemented in
target-arm/helper.c or similar), whereas timer devices in general are kept in
hw/arm_* (c.f. arm_timer.c and arm_mptimer.c). But in this case I have a timer
that is implemented as a coprocessor - where should that go? Or should it be
split in two places?
2) Where should a device like this save its own internal state? Some other
devices seems to save its state as an extension of the SysBusDevice structure,
but coprocessor state in general rather seems to be part of CPUARMState or
similar. What is the right way in this particular case?
br,
/D
-Original Message-
From: Blue Swirl [mailto:blauwir...@gmail.com]
Sent: den 14 september 2012 19:26
To: Daniel Forsgren
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] Basic support for ARM A15 architectured
(cp15) timers
On Wed, Sep 12, 2012 at 11:49 AM, Daniel Forsgren
daniel.forsg...@enea.com wrote:
This patch adds basic support for the architected timers (i.e. cp15)
found in A15. It's enough to allow Linux to boot, using arch_timer for
the tick. However - it is not a complete model of the timer block at
large, it is not that well structured, and it is currently tested with
qemu-linaro-1.1.50-2012.07 (not latest and greatest). It's simply a
prototype.
However, if anyone wants to play with the architectured (cp15) timers
instead of sp804, then please feel free to try it out. It has been
tested with linux-linaro-3.6-rc2-2012.08, and you can easily verify
the existence of these timers under /proc/interrupts:
root@linaro-developer:~# cat /proc/interrupts
cat /proc/interrupts
CPU0
29: 7424 GIC arch_timer
30: 0 GIC arch_timer
Please note that this also requires some minor fixes that are not part
of qemu-linaro-1.1.50-2012.07:
http://patches.linaro.org/9833/
Signed-off-by: Daniel Forsgren daniel.forsg...@enea.com
---
diff -Nupr qemu-linaro-1.1.50-2012.07/hw/a15mpcore.c qemu-linaro-1.1.50-
2012.07-modified/hw/a15mpcore.c
--- qemu-linaro-1.1.50-2012.07/hw/a15mpcore.c 2012-07-05
16:48:28.0 +0200
+++ qemu-linaro-1.1.50-2012.07-modified/hw/a15mpcore.c 2012-09-12
+++ 11:24:25.844237405 +0200
@@ -28,6 +28,7 @@ typedef struct A15MPPrivState {
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
+DeviceState *archtimer;
DeviceState *gic;
} A15MPPrivState;
@@ -40,7 +41,8 @@ static void a15mp_priv_set_irq(void *opa static int
a15mp_priv_init(SysBusDevice *dev) {
A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
-SysBusDevice *busdev;
+SysBusDevice *busdev, *timerbusdev;
+int i;
if (kvm_irqchip_in_kernel()) {
s-gic = qdev_create(NULL, kvm-arm_gic); @@ -60,6 +62,11 @@
static int a15mp_priv_init(SysBusDevice
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(s-busdev.qdev, a15mp_priv_set_irq, s-num_irq
- 32);
+s-archtimer = qdev_create(NULL, arm_archtimer);
+//qdev_prop_set_uint32(s-archtimer, num-cpu, s-num_cpu);
Please don't introduce dead code.
+qdev_init_nofail(s-archtimer);
+timerbusdev = sysbus_from_qdev(s-archtimer);
+
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x-0x0fff -- reserved
* 0x1000-0x1fff -- GIC Distributor @@ -75,6 +82,16 @@ static
int a15mp_priv_init(SysBusDevice
sysbus_mmio_get_region(busdev, 1));
sysbus_init_mmio(dev, s-container);
+
+
+for (i = 0; i
Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
Il 15/09/2012 02:24, Isaku Yamahata ha scritto: ok, yes pcie hotplug seems to work :) I guess I got confused b/c I thought devices would show up on the host bus. So the host bus in q35 simply doesn't support hotplug? No, it doesn't. I think it makes sense then to keep ACPI hotplug on the host bus, for backwards compatibility with PIIX4 guests, especially if the code is written. Paolo
[Qemu-devel] [RFC V2] QEMU wiki remix
Hello list, Here is the new version of the QEMU wiki remix using the QEMU logo. http://files.nodalink.com/qemu/Main_Page since v1: fluid layout minimalist design Best regards Benoît
Re: [Qemu-devel] [PATCH 1/9] NiosII: Add support for the Altera NiosII soft-core CPU.
Am 10.09.2012 02:19, schrieb crwu...@gmail.com: From: Chris Wulff crwu...@gmail.com Signed-off-by: Chris Wulff crwu...@gmail.com --- target-nios2/Makefile.objs |5 + target-nios2/altera_iic.c | 100 +++ target-nios2/cpu-qom.h | 69 +++ target-nios2/cpu.c | 83 +++ target-nios2/cpu.h | 259 target-nios2/exec.h| 60 ++ target-nios2/helper.c | 291 + target-nios2/helper.h | 45 ++ target-nios2/instruction.c | 1463 target-nios2/instruction.h | 290 + target-nios2/machine.c | 33 + target-nios2/mmu.c | 273 + target-nios2/mmu.h | 49 ++ target-nios2/op_helper.c | 125 target-nios2/translate.c | 252 15 files changed, 3397 insertions(+) Some general comments: You're introducing a new target here, so if you design your API cleanly (using Nios2CPU where possible) you don't really need a separate cpu-qom.h file in addition to cpu.h, cf. target-or32. Please prefer passing Nios2CPU as opaque rather than CPUNios2State (e.g., 3/9; cf. target-arm). Reason is that fields are being moved from CPUxxxState to CPUState and this will simplify the migration. Thanks, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 3/9] Altera: Add support for Altera devices required to boot linux on NiosII.
Am 11.09.2012 21:53, schrieb Blue Swirl:
On Mon, Sep 10, 2012 at 12:20 AM, crwu...@gmail.com wrote:
diff --git a/hw/nios2_pic_cpu.c b/hw/nios2_pic_cpu.c
new file mode 100644
index 000..c89b4ae
--- /dev/null
+++ b/hw/nios2_pic_cpu.c
@@ -0,0 +1,48 @@
+/*
+ * QEMU Altera Nios II CPU interrupt wrapper logic.
+ *
+ * Copyright (c) 2012 Chris Wulff crwu...@gmail.com
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include hw.h
+#include pc.h
Why?
+#include nios2.h
+
+void pic_info(Monitor *mon)
+{
+}
+
+void irq_info(Monitor *mon)
+{
+}
Thought these stubs were no longer necessary...
+
+static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
+{
+CPUNios2State *env = (CPUNios2State *)opaque;
Useless cast in C.
Please use Nios2CPU so that we can more easily make cpu_interrupt() and
cpu_reset_interrupt() take a CPUState argument in the future.
Please also split this patch up per device and always cc the appropriate
maintainers to facilitate review (e.g.,
--cc-cmd=scripts/get_maintainer.pl --nogit-fallback).
Regards,
Andreas
+int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
+
+if (level) {
+cpu_interrupt(env, type);
+} else {
+cpu_reset_interrupt(env, type);
+}
+}
+
+qemu_irq *nios2_pic_init_cpu(CPUNios2State *env)
+{
+return qemu_allocate_irqs(nios2_pic_cpu_handler, env, 2);
+}
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [libvirt] [PATCH v2 1/4] config: Introduce migration for SPICE graphics
On Fri, Sep 14, 2012 at 05:23:16PM -0600, Eric Blake wrote: [adding qemu] On 09/14/2012 11:47 AM, Daniel P. Berrange wrote: On Fri, Sep 14, 2012 at 07:34:50PM +0200, Michal Privoznik wrote: With this element users will control how SPICE server behaves upon migration. For now, there's just one attribute 'seamless' turning seamless migration on/off/default. Ewww, no. This information is a related to a API operation, not the VM configuration. It should be either auto-detected by libvirt to the best compatible setting, or passed as a flag to the virDomainMigrate API call if auto-detection is not possible. But with the current qemu implementation, there's no way to know if the destination supports this until after you've started the source, and the current implementation in qemu is that you must declare the semantics at the time you start qemu, not at the time you send the 'migrate' monitor command. For libvirt autodetection to work without polluting the domain XML, we'd need to be able to auto-detect at the time we start migration. This sounds like we need to enhance the 'migrate-set-capabilities' command to enable or disable this feature on the fly, according to what libvirt detects from the remote end, rather than hard-coding it to the startup state of qemu on the source side. Hmm, my understanding of the QEMU flag was different. Based on the commit message: spice: adding seamless-migration option to the command line The seamless-migration flag is required in order to identify whether libvirt supports the new QEVENT_SPICE_MIGRATE_COMPLETED or not (by default the flag is off). New libvirt versions that wait for QEVENT_SPICE_MIGRATE_COMPLETED should turn on this flag. When this flag is off, spice fallbacks to its old migration method, which can result in data loss. This says to me that any libvirt which knows about the new SPICE_MIGRATE_COMPLETED event, should set the seamless-migration flag unconditionally, to indicate that it can handle the event and thus the new migration method. It says nothing about only setting this flag if the destination QEMU also supports it. As such, IMHO, we can should set this flag unconditonally on all QEMUs we run which support it. If it turns out that this flag does indeed require that the destination QEMU also has the same setting, then IMHO this flag is a fatally flawed design. At time of starting any QEMU instance, we can't know whether the destination QEMU we want to migrate to will have the support or not. Compatibility checks of this kind can only be decided at time the migrate command is actually issued. Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM.
Am 13.09.2012 22:12, schrieb Jason Baron: Let's use PCIExpressHost with QOM. Signed-off-by: Jason Baron jba...@redhat.com Acked-by: Andreas Färber afaer...@suse.de Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 1/9] NiosII: Add support for the Altera NiosII soft-core CPU.
On Tue, Sep 11, 2012 at 5:34 PM, Aurelien Jarno aurel...@aurel32.netwrote: On Sun, Sep 09, 2012 at 08:19:59PM -0400, crwu...@gmail.com wrote: From: Chris Wulff crwu...@gmail.com Signed-off-by: Chris Wulff crwu...@gmail.com +tcg_gen_movi_tl(dc-cpu_R[R_RA], dc-pc + 4); +tcg_gen_movi_tl(dc-cpu_R[R_PC], +(dc-pc 0xF000) | (instr-imm26 * 4)); + +dc-is_jmp = DISAS_JUMP; +} + You probably want to add some tcg_gen_goto_tb() for static jumps, so that TB linking is possible. It greatly improves the speed of the emulation. Doing this actually made quite a big difference. The reported bogomips from linux went up 15x and the observable speed by about 2x. The rest of your suggested changes didn't have much noticeable effect but were at least good things to clean up anyway. -- Chris Wulff
[Qemu-devel] [PATCH] usb-redir: Allow to attach USB 2.0 devices to 1.1 host controller
From: Jan Kiszka jan.kis...@siemens.com
This follows the logic of host-linux: If a 2.0 device has no ISO
endpoint and no interrupt endpoint with a packet size 64, we can
attach it also to an 1.1 host controller. In case the redir server does
not report endpoint sizes, play safe and remove the 1.1 compatibility as
well.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
hw/usb/redirect.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
index 5301a69..bc36e53 100644
--- a/hw/usb/redirect.c
+++ b/hw/usb/redirect.c
@@ -1098,6 +1098,9 @@ static void usbredir_device_connect(void *priv,
}
dev-dev.speedmask = (1 dev-dev.speed);
+if (dev-dev.speed == USB_SPEED_HIGH) {
+dev-dev.speedmask |= USB_SPEED_MASK_FULL;
+}
dev-device_info = *device_connect;
if (usbredir_check_filter(dev)) {
@@ -1172,7 +1175,14 @@ static void usbredir_ep_info(void *priv,
case usb_redir_type_invalid:
break;
case usb_redir_type_iso:
+dev-dev.speedmask = ~USB_SPEED_MASK_FULL;
+/* Fall through */
case usb_redir_type_interrupt:
+if (!usbredirparser_peer_has_cap(dev-parser,
+ usb_redir_cap_ep_info_max_packet_size) ||
+ep_info-max_packet_size[i] 64) {
+dev-dev.speedmask = ~USB_SPEED_MASK_FULL;
+}
if (dev-endpoint[i].interval == 0) {
ERROR(Received 0 interval for isoc or irq endpoint\n);
usbredir_device_disconnect(dev);
--
1.7.3.4
Re: [Qemu-devel] [PATCH] Basic support for ARM A15 architectured (cp15) timers
On Sat, Sep 15, 2012 at 8:57 AM, Daniel Forsgren
daniel.forsg...@enea.com wrote:
Thanks for the feedback!
I should probably point out (as I wrote in my initial mail) that this is just
a prototype - a quick n dirty hack to get Linux up and running with the arch
timers. It is very true that I'm not following the QEMU coding standard (I
must admit that haven't even read it).
The background is that I wanted to run QEMU and the A15 CoreTile side by side
with as similar configuration as possible. And the missing A15 timers was
kind of stopping me, so I had to work around that. (For that reason, I tried
to keep most of my additions in a single file and not to clutter the entire
source tree). At the same time I saw that someone asked for these timers on
the mailing list some month ago. So I thought that I could as well share my
results.
That said, I'm very grateful that you still took the time to actually review
the code, and I will try to improve it. I have fixed some minor issues that
prevented me to run multicore so far. (My eventual goal is to run as close as
possible to the real 2xA15+3xA7 CoreTile that I try to mimic).
However, being a QEMU newbie I have a couple of questions related to the
right way of implementing this:
1) What is considered to be part of the core and what is considered to be a
device external to the core? To me, it looks like co-processor functionality
in general is considered to be part of the core (implemented in
target-arm/helper.c or similar), whereas timer devices in general are kept in
hw/arm_* (c.f. arm_timer.c and arm_mptimer.c). But in this case I have a
timer that is implemented as a coprocessor - where should that go? Or should
it be split in two places?
SoC devices attached to the CPU is a bit grey area. In this case, I
think coprocessor should be part of the CPU. Peter?
2) Where should a device like this save its own internal state? Some other
devices seems to save its state as an extension of the SysBusDevice
structure, but coprocessor state in general rather seems to be part of
CPUARMState or similar. What is the right way in this particular case?
Currently the divisive line seems to be that devices which are only
accessible via MMIO or generic IO instructions should be external to
CPU. But it could be possible to introduce generic methods to register
other classes, for example for the ARM coprocessors, x86 model
specific registers, PPC SPRs and Sparc ASIs. The memory API should
support adding more address spaces. Maybe this could be a nice
approach.
But I'd vote for CPUARMState for now.
br,
/D
-Original Message-
From: Blue Swirl [mailto:blauwir...@gmail.com]
Sent: den 14 september 2012 19:26
To: Daniel Forsgren
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] Basic support for ARM A15 architectured
(cp15) timers
On Wed, Sep 12, 2012 at 11:49 AM, Daniel Forsgren
daniel.forsg...@enea.com wrote:
This patch adds basic support for the architected timers (i.e. cp15)
found in A15. It's enough to allow Linux to boot, using arch_timer for
the tick. However - it is not a complete model of the timer block at
large, it is not that well structured, and it is currently tested with
qemu-linaro-1.1.50-2012.07 (not latest and greatest). It's simply a
prototype.
However, if anyone wants to play with the architectured (cp15) timers
instead of sp804, then please feel free to try it out. It has been
tested with linux-linaro-3.6-rc2-2012.08, and you can easily verify
the existence of these timers under /proc/interrupts:
root@linaro-developer:~# cat /proc/interrupts
cat /proc/interrupts
CPU0
29: 7424 GIC arch_timer
30: 0 GIC arch_timer
Please note that this also requires some minor fixes that are not part
of qemu-linaro-1.1.50-2012.07:
http://patches.linaro.org/9833/
Signed-off-by: Daniel Forsgren daniel.forsg...@enea.com
---
diff -Nupr qemu-linaro-1.1.50-2012.07/hw/a15mpcore.c qemu-linaro-1.1.50-
2012.07-modified/hw/a15mpcore.c
--- qemu-linaro-1.1.50-2012.07/hw/a15mpcore.c 2012-07-05
16:48:28.0 +0200
+++ qemu-linaro-1.1.50-2012.07-modified/hw/a15mpcore.c 2012-09-12
+++ 11:24:25.844237405 +0200
@@ -28,6 +28,7 @@ typedef struct A15MPPrivState {
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
+DeviceState *archtimer;
DeviceState *gic;
} A15MPPrivState;
@@ -40,7 +41,8 @@ static void a15mp_priv_set_irq(void *opa static int
a15mp_priv_init(SysBusDevice *dev) {
A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
-SysBusDevice *busdev;
+SysBusDevice *busdev, *timerbusdev;
+int i;
if (kvm_irqchip_in_kernel()) {
s-gic = qdev_create(NULL, kvm-arm_gic); @@ -60,6 +62,11 @@
static int a15mp_priv_init(SysBusDevice
/* Pass through inbound GPIO lines to the GIC */
Re: [Qemu-devel] [PATCH v5] configure: properly check if -lrt and -lm is needed
Thanks, applied.
On Wed, Sep 12, 2012 at 9:06 AM, Natanael Copa natanael.c...@gmail.com wrote:
Fixes build against uClibc.
uClibc provides 2 versions of clock_gettime(), one with realtime
support and one without (this is so you can avoid linking in -lrt
unless actually needed). This means that the clock_gettime() don't
need -lrt. We still need it for timer_create() so we check for this
function in addition.
We also need check if -lm is needed for isnan().
Both -lm and -lrt are needed for libs_qga.
Signed-off-by: Natanael Copa nc...@alpinelinux.org
---
Changes v4-v5:
- Do not exit with error if librt fails.
Apparently, mingw32 does not use those functions at all so we
should not exit with error.
This is how it originally worked.
configure | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index edf9da4..c1ed856 100755
--- a/configure
+++ b/configure
@@ -2624,17 +2624,44 @@ fi
##
+# Do we need libm
+cat $TMPC EOF
+#include math.h
+int main(void) { return isnan(sin(0.0)); }
+EOF
+if compile_prog ; then
+ :
+elif compile_prog -lm ; then
+ LIBS=-lm $LIBS
+ libs_qga=-lm $libs_qga
+else
+ echo
+ echo Error: libm check failed
+ echo
+ exit 1
+fi
+
+##
# Do we need librt
+# uClibc provides 2 versions of clock_gettime(), one with realtime
+# support and one without. This means that the clock_gettime() don't
+# need -lrt. We still need it for timer_create() so we check for this
+# function in addition.
cat $TMPC EOF
#include signal.h
#include time.h
-int main(void) { return clock_gettime(CLOCK_REALTIME, NULL); }
+int main(void) {
+ timer_create(CLOCK_REALTIME, NULL, NULL);
+ return clock_gettime(CLOCK_REALTIME, NULL);
+}
EOF
if compile_prog ; then
:
-elif compile_prog -lrt ; then
+# we need pthread for static linking. use previous pthread test result
+elif compile_prog -lrt $pthread_lib ; then
LIBS=-lrt $LIBS
+ libs_qga=-lrt $libs_qga
fi
if test $darwin != yes -a $mingw32 != yes -a $solaris != yes -a \
--
1.7.12
Re: [Qemu-devel] [PATCH] tcg: Fix MAX_OPC_PARAM_IARGS
Thanks, applied. On Wed, Sep 12, 2012 at 5:18 PM, Stefan Weil s...@weilnetz.de wrote: DEF_HELPER_FLAGS_5 was added some time ago without adjusting MAX_OPC_PARAM_IARGS. Fixing the definition becomes more important as QEMU is using an increasing number of helper functions called with 5 arguments. Add also a comment to avoid future problems when DEF_HELPER_FLAGS_6 will be added. Signed-off-by: Stefan Weil s...@weilnetz.de --- Hi, I think this patch should be added to the latest stable versions, too. Please note that this patch breaks compilation with --enable-tcg-interpreter. TCI code is designed for up to 4 arguments and needs modifications. The current TCI binaries crash at runtime, so the patch just makes it obvious that TCI needs to be fixed. Regards, Stefan Weil def-helper.h |2 ++ exec-all.h |2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/def-helper.h b/def-helper.h index b98ff69..022a9ce 100644 --- a/def-helper.h +++ b/def-helper.h @@ -128,6 +128,8 @@ #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \ DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) +/* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */ + #endif /* DEF_HELPER_H */ #ifndef GEN_HELPER diff --git a/exec-all.h b/exec-all.h index ac19c02..8977729 100644 --- a/exec-all.h +++ b/exec-all.h @@ -51,7 +51,7 @@ typedef struct TranslationBlock TranslationBlock; #else #define MAX_OPC_PARAM_PER_ARG 1 #endif -#define MAX_OPC_PARAM_IARGS 4 +#define MAX_OPC_PARAM_IARGS 5 #define MAX_OPC_PARAM_OARGS 1 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) -- 1.7.10
Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
On Sat, Sep 15, 2012 at 01:33:04PM +0200, Paolo Bonzini wrote: Il 15/09/2012 02:24, Isaku Yamahata ha scritto: ok, yes pcie hotplug seems to work :) I guess I got confused b/c I thought devices would show up on the host bus. So the host bus in q35 simply doesn't support hotplug? No, it doesn't. I think it makes sense then to keep ACPI hotplug on the host bus, for backwards compatibility with PIIX4 guests, especially if the code is written. Paolo I agree. I think ACPI hotplug support is a spec requirement anyway: if you look at ACPI spec you will see that native hotplug support for guest is optional. -- MST
Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
On Fri, Sep 14, 2012 at 03:01:55PM -0400, Jason Baron wrote: On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote: On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote: On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote: On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote: 2) hotplug I've added piix acpi style hotplug to ich9. What's the point of this? Its design is ad-hoc and shpc/pcie hotplug are available. The point was to get to feature parity with piix. I'm not sure how hard pcie hotplug is to implement really. I was thinking that we could replace the piix hotplug style with pcie hotplug, once that was implemented... shpc/pcie hotplug emulators are already available in qemu. hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c. thanks, -- yamahata ok, yes pcie hotplug seems to work :) I guess I got confused b/c I thought devices would show up on the host bus. So the host bus in q35 simply doesn't support hotplug? Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param. Without the 'bus=pcie.n' param, i get: Bus 'pcie.0' does not support hotplugging We probably then need to enhance 'device_add' to find a reasonable default bus for the device on hotplug? Thanks, -Jason Maybe though I am not too worried: hotplug is an advanced enough feature. We will also still need a PCI bus in the system so that legacy PCI devices such as virtio can be added. And that bus needs ACPI for hotplug. -- MST
Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
On Sat, Sep 15, 2012 at 09:24:51AM +0900, Isaku Yamahata wrote: On Fri, Sep 14, 2012 at 03:01:55PM -0400, Jason Baron wrote: On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote: On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote: On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote: On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote: 2) hotplug I've added piix acpi style hotplug to ich9. What's the point of this? Its design is ad-hoc and shpc/pcie hotplug are available. The point was to get to feature parity with piix. I'm not sure how hard pcie hotplug is to implement really. I was thinking that we could replace the piix hotplug style with pcie hotplug, once that was implemented... shpc/pcie hotplug emulators are already available in qemu. hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c. thanks, -- yamahata ok, yes pcie hotplug seems to work :) I guess I got confused b/c I thought devices would show up on the host bus. So the host bus in q35 simply doesn't support hotplug? No, it doesn't. Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param. Without the 'bus=pcie.n' param, i get: Bus 'pcie.0' does not support hotplugging We probably then need to enhance 'device_add' to find a reasonable default bus for the device on hotplug? Yes. By the way I would tread carefully before switching on native hotplug support unconditionally in the BIOS. For example, it has an annoying two-second delay after device is added and before it is used built into the spec that might interfere with some uses. As a minimum we might want to give users the ability to disable BIOS native hotplug support. -- yamahata
Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote: On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote: 2) hotplug I've added piix acpi style hotplug to ich9. What's the point of this? Its design is ad-hoc and shpc/pcie hotplug are available. We have a pci bridge with shpc support, but not host support. In any case, windows guests do not support shpc for PCI, and we need ability to mix in PCI buses with hotplug support so we can use PCI devices. -- yamahata
Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
On Thu, Sep 13, 2012 at 04:12:42PM -0400, Jason Baron wrote:
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 000..4f75d97
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,378 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the
rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2009, 2010
+ * Isaku Yamahata yamahata at valinux co jp
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
http://www.gnu.org/licenses/
+ */
+#include hw.h
+#include arch_init.h
+#include pc.h
+#include fdc.h
+#include pci.h
+#include pci_bridge.h
+#include pci_p2pbr.h
+#include ioh3420.h
+#include xio3130_upstream.h
+#include xio3130_downstream.h
+#include block.h
+#include blockdev.h
+#include sysemu.h
+#include audio/audio.h
+#include net.h
+#include smbus.h
+#include boards.h
+#include monitor.h
+#include fw_cfg.h
+#include hpet_emul.h
+#include watchdog.h
+#include smbios.h
+#include ide.h
+#include usb-uhci.h
+
+#include q35.h
+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS 6
+
+#define I21154_REV0x05
+#define I21154_PI 0x00
+
+static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
+{
+const PCIP2PBridgeInit init = {
+.bus = bus,
+.devfn = devfn,
+.multifunction = multifunction,
+
+.bus_name = bus_name,
+.map_irq = pci_swizzle_map_irq_fn,
+};
+const PCIP2PBridgeProp prop = {
+.vendor_id = PCI_VENDOR_ID_DEC,
+.device_id = PCI_DEVICE_ID_DEC_21154,
+.revision_id = I21154_REV,
+.prog_interface = I21154_PI,
+};
+return pci_p2pbr_create_simple(init, prop);
+}
+
+static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
+{
+uint8_t dev;
+uint8_t sec_bus;
+uint8_t port = 0;
+uint8_t chassis = 0;
+uint16_t slot = 0;
+uint8_t upstream_port;
+PCIESlot *s;
+uint8_t fn;
+PCIESlot *root_port;
+PCIBus *root_port_bus;
+char buf[16];
+
+/* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
+ of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
+#define Q35_P2P_BRDIGE_DEV_BASE 28
+#define Q35_P2P_BRDIGE_DEV_MAX 32
+#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
+for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev Q35_P2P_BRDIGE_DEV_MAX; dev++)
{
+PCIBridge *br;
+sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
+
+snprintf(buf, sizeof(buf), pci.%d, sec_bus);
+br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+}
+
+/* PCIe root port b0:d1:f0 in GMCH.
+ * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
+ */
+sec_bus = 32;
+snprintf(buf, sizeof(buf), pcie.%d, sec_bus);
+s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC),
true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+
+
+/* more slots. ICH9
[Qemu-devel] [PATCH 0/6] linux-user improvements
These patches are available at git://repo.or.cz/qemu/rth.git axp-next and fix several problems detected by the glibc testsuite. r~ Richard Henderson (6): linux-user: Perform more checks on iovec lists linux-user: Implement gethostname alpha-linux-user: Fix sigaltstack structure definition alpha-linux-user: Fix sigaction target-alpha: Fix cpu_alpha_init linux-user: Fix siginfo handling linux-user/alpha/target_signal.h | 7 +- linux-user/qemu.h| 3 + linux-user/signal.c | 81 ++ linux-user/syscall.c | 177 +-- linux-user/syscall_defs.h| 2 +- target-alpha/translate.c | 7 +- 6 files changed, 178 insertions(+), 99 deletions(-) -- 1.7.11.4
[Qemu-devel] [PATCH 4/6] alpha-linux-user: Fix sigaction
Unconditional bswap replaced by __get_user/__put_user.
Signed-off-by: Richard Henderson r...@twiddle.net
---
linux-user/signal.c | 22 --
linux-user/syscall_defs.h | 2 +-
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 7869147..bf2dfb8 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -586,28 +586,22 @@ int do_sigaction(int sig, const struct target_sigaction
*act,
sig, act, oact);
#endif
if (oact) {
-oact-_sa_handler = tswapal(k-_sa_handler);
-#if defined(TARGET_MIPS) || defined (TARGET_ALPHA)
-oact-sa_flags = bswap32(k-sa_flags);
-#else
-oact-sa_flags = tswapal(k-sa_flags);
-#endif
+__put_user(k-_sa_handler, oact-_sa_handler);
+__put_user(k-sa_flags, oact-sa_flags);
#if !defined(TARGET_MIPS)
-oact-sa_restorer = tswapal(k-sa_restorer);
+__put_user(k-sa_restorer, oact-sa_restorer);
#endif
+/* Not swapped. */
oact-sa_mask = k-sa_mask;
}
if (act) {
/* FIXME: This is not threadsafe. */
-k-_sa_handler = tswapal(act-_sa_handler);
-#if defined(TARGET_MIPS) || defined (TARGET_ALPHA)
-k-sa_flags = bswap32(act-sa_flags);
-#else
-k-sa_flags = tswapal(act-sa_flags);
-#endif
+__get_user(k-_sa_handler, act-_sa_handler);
+__get_user(k-sa_flags, act-sa_flags);
#if !defined(TARGET_MIPS)
-k-sa_restorer = tswapal(act-sa_restorer);
+__get_user(k-sa_restorer, act-sa_restorer);
#endif
+/* To be swapped in target_to_host_sigset. */
k-sa_mask = act-sa_mask;
/* we update the host linux signal state */
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index a98cbf7..8ca70b9 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -540,7 +540,7 @@ int do_sigaction(int sig, const struct target_sigaction
*act,
struct target_old_sigaction {
abi_ulong _sa_handler;
abi_ulong sa_mask;
-abi_ulong sa_flags;
+int32_t sa_flags;
};
struct target_rt_sigaction {
--
1.7.11.4
[Qemu-devel] [PATCH 2/6] linux-user: Implement gethostname
Signed-off-by: Richard Henderson r...@twiddle.net
---
linux-user/syscall.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ceca04c..925e579 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8866,6 +8866,19 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
break;
}
#endif
+#ifdef TARGET_NR_gethostname
+case TARGET_NR_gethostname:
+{
+char *name = lock_user(VERIFY_WRITE, arg1, arg2, 0);
+if (name) {
+ret = get_errno(gethostname(name, arg2));
+unlock_user(name, arg1, arg2);
+} else {
+ret = -TARGET_EFAULT;
+}
+break;
+}
+#endif
default:
unimplemented:
gemu_log(qemu: Unsupported syscall: %d\n, num);
--
1.7.11.4
[Qemu-devel] [PATCH 5/6] target-alpha: Fix cpu_alpha_init
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-alpha/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 12de6a3..f998f75 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3525,6 +3525,7 @@ static const struct cpu_def_t cpu_defs[] = {
CPUAlphaState * cpu_alpha_init (const char *cpu_model)
{
+static bool inited;
AlphaCPU *cpu;
CPUAlphaState *env;
int implver, amask, i, max;
@@ -3532,7 +3533,10 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
cpu = ALPHA_CPU(object_new(TYPE_ALPHA_CPU));
env = cpu-env;
-alpha_translate_init();
+if (!inited) {
+inited = true;
+alpha_translate_init();
+}
/* Default to ev67; no reason not to emulate insns by default. */
implver = IMPLVER_21264;
@@ -3549,6 +3553,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
}
env-implver = implver;
env-amask = amask;
+env-cpu_model_str = cpu_model;
qemu_init_vcpu(env);
return env;
--
1.7.11.4
[Qemu-devel] [PATCH 1/6] linux-user: Perform more checks on iovec lists
Validate count between 0 and IOV_MAX. Limit total length of
operation in the same way the kernel does.
Signed-off-by: Richard Henderson r...@twiddle.net
---
linux-user/syscall.c | 162 ---
1 file changed, 102 insertions(+), 60 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 6257a04..ceca04c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -1744,55 +1744,96 @@ static abi_long do_getsockopt(int sockfd, int level,
int optname,
return ret;
}
-/* FIXME
- * lock_iovec()/unlock_iovec() have a return code of 0 for success where
- * other lock functions have a return code of 0 for failure.
- */
-static abi_long lock_iovec(int type, struct iovec *vec, abi_ulong target_addr,
- int count, int copy)
+static struct iovec *lock_iovec(int type, abi_ulong target_addr,
+int count, int copy)
{
struct target_iovec *target_vec;
-abi_ulong base;
+struct iovec *vec;
+abi_ulong total_len, max_len;
int i;
-target_vec = lock_user(VERIFY_READ, target_addr, count * sizeof(struct
target_iovec), 1);
-if (!target_vec)
-return -TARGET_EFAULT;
-for(i = 0;i count; i++) {
-base = tswapal(target_vec[i].iov_base);
-vec[i].iov_len = tswapal(target_vec[i].iov_len);
-if (vec[i].iov_len != 0) {
-vec[i].iov_base = lock_user(type, base, vec[i].iov_len, copy);
-/* Don't check lock_user return value. We must call writev even
- if a element has invalid base address. */
+if (count == 0) {
+errno = 0;
+return NULL;
+}
+if (count IOV_MAX) {
+errno = EINVAL;
+return NULL;
+}
+
+vec = calloc(count, sizeof(struct iovec));
+if (vec == NULL) {
+errno = ENOMEM;
+return NULL;
+}
+
+target_vec = lock_user(VERIFY_READ, target_addr,
+ count * sizeof(struct target_iovec), 1);
+if (target_vec == NULL) {
+errno = EFAULT;
+goto fail2;
+}
+
+/* ??? If host page size target page size, this will result in a
+ value larger than what we can actually support. */
+max_len = 0x7fff TARGET_PAGE_MASK;
+total_len = 0;
+
+for (i = 0; i count; i++) {
+abi_ulong base = tswapal(target_vec[i].iov_base);
+abi_long len = tswapal(target_vec[i].iov_len);
+
+if (len 0) {
+errno = EINVAL;
+goto fail;
+} else if (len == 0) {
+/* Zero length pointer is ignored. */
+vec[i].iov_base = 0;
} else {
-/* zero length pointer is ignored */
-vec[i].iov_base = NULL;
+vec[i].iov_base = lock_user(type, base, len, copy);
+if (!vec[i].iov_base) {
+errno = EFAULT;
+goto fail;
+}
+if (len max_len - total_len) {
+len = max_len - total_len;
+}
}
+vec[i].iov_len = len;
+total_len += len;
}
-unlock_user (target_vec, target_addr, 0);
-return 0;
+
+unlock_user(target_vec, target_addr, 0);
+return vec;
+
+ fail:
+free(vec);
+ fail2:
+unlock_user(target_vec, target_addr, 0);
+return NULL;
}
-static abi_long unlock_iovec(struct iovec *vec, abi_ulong target_addr,
- int count, int copy)
+static void unlock_iovec(struct iovec *vec, abi_ulong target_addr,
+ int count, int copy)
{
struct target_iovec *target_vec;
-abi_ulong base;
int i;
-target_vec = lock_user(VERIFY_READ, target_addr, count * sizeof(struct
target_iovec), 1);
-if (!target_vec)
-return -TARGET_EFAULT;
-for(i = 0;i count; i++) {
-if (target_vec[i].iov_base) {
-base = tswapal(target_vec[i].iov_base);
+target_vec = lock_user(VERIFY_READ, target_addr,
+ count * sizeof(struct target_iovec), 1);
+if (target_vec) {
+for (i = 0; i count; i++) {
+abi_ulong base = tswapal(target_vec[i].iov_base);
+abi_long len = tswapal(target_vec[i].iov_base);
+if (len 0) {
+break;
+}
unlock_user(vec[i].iov_base, base, copy ? vec[i].iov_len : 0);
}
+unlock_user(target_vec, target_addr, 0);
}
-unlock_user (target_vec, target_addr, 0);
-return 0;
+free(vec);
}
/* do_socket() Must return target values and target errnos. */
@@ -1888,8 +1929,7 @@ static abi_long do_sendrecvmsg(int fd, abi_ulong
target_msg,
ret = target_to_host_sockaddr(msg.msg_name, tswapal(msgp-msg_name),
msg.msg_namelen);
if (ret) {
-unlock_user_struct(msgp, target_msg, send ? 0 : 1);
-return ret;
+goto out2;
}
} else {
msg.msg_name =
[Qemu-devel] [PATCH 3/6] alpha-linux-user: Fix sigaltstack structure definition
Signed-off-by: Richard Henderson r...@twiddle.net
---
linux-user/alpha/target_signal.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/linux-user/alpha/target_signal.h b/linux-user/alpha/target_signal.h
index 94f15f6..d3822da 100644
--- a/linux-user/alpha/target_signal.h
+++ b/linux-user/alpha/target_signal.h
@@ -6,9 +6,10 @@
/* this struct defines a stack used during syscall handling */
typedef struct target_sigaltstack {
- abi_ulong ss_sp;
- abi_long ss_flags;
- abi_ulong ss_size;
+abi_ulong ss_sp;
+int32_t ss_flags;
+int32_t dummy;
+abi_ulong ss_size;
} target_stack_t;
--
1.7.11.4
[Qemu-devel] [PATCH 6/6] linux-user: Fix siginfo handling
Compare signal numbers in the proper domain.
Convert all of the fields for SIGIO and SIGCHLD.
Signed-off-by: Richard Henderson r...@twiddle.net
---
linux-user/qemu.h| 3 +++
linux-user/signal.c | 59 +++-
linux-user/syscall.c | 2 +-
3 files changed, 44 insertions(+), 20 deletions(-)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 69b27d7..8f871eb 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -219,6 +219,9 @@ unsigned long init_guest_space(unsigned long host_start,
#include qemu-log.h
+/* syscall.c */
+int host_to_target_waitstatus(int status);
+
/* strace.c */
void print_syscall(int num,
abi_long arg1, abi_long arg2, abi_long arg3,
diff --git a/linux-user/signal.c b/linux-user/signal.c
index bf2dfb8..9842ba6 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -202,46 +202,67 @@ void target_to_host_old_sigset(sigset_t *sigset,
static inline void host_to_target_siginfo_noswap(target_siginfo_t *tinfo,
const siginfo_t *info)
{
-int sig;
-sig = host_to_target_signal(info-si_signo);
+int sig = host_to_target_signal(info-si_signo);
tinfo-si_signo = sig;
tinfo-si_errno = 0;
tinfo-si_code = info-si_code;
-if (sig == SIGILL || sig == SIGFPE || sig == SIGSEGV ||
-sig == SIGBUS || sig == SIGTRAP) {
-/* should never come here, but who knows. The information for
- the target is irrelevant */
+
+if (sig == TARGET_SIGILL || sig == TARGET_SIGFPE || sig == TARGET_SIGSEGV
+|| sig == TARGET_SIGBUS || sig == TARGET_SIGTRAP) {
+/* Should never come here, but who knows. The information for
+ the target is irrelevant. */
tinfo-_sifields._sigfault._addr = 0;
-} else if (sig == SIGIO) {
+} else if (sig == TARGET_SIGIO) {
+tinfo-_sifields._sigpoll._band = info-si_band;
tinfo-_sifields._sigpoll._fd = info-si_fd;
+} else if (sig == TARGET_SIGCHLD) {
+tinfo-_sifields._sigchld._pid = info-si_pid;
+tinfo-_sifields._sigchld._uid = info-si_uid;
+tinfo-_sifields._sigchld._status
+= host_to_target_waitstatus(info-si_status);
+tinfo-_sifields._sigchld._utime = info-si_utime;
+tinfo-_sifields._sigchld._stime = info-si_stime;
} else if (sig = TARGET_SIGRTMIN) {
tinfo-_sifields._rt._pid = info-si_pid;
tinfo-_sifields._rt._uid = info-si_uid;
/* XXX: potential problem if 64 bit */
-tinfo-_sifields._rt._sigval.sival_ptr =
-(abi_ulong)(unsigned long)info-si_value.sival_ptr;
+tinfo-_sifields._rt._sigval.sival_ptr
+= (abi_ulong)(unsigned long)info-si_value.sival_ptr;
}
}
static void tswap_siginfo(target_siginfo_t *tinfo,
const target_siginfo_t *info)
{
-int sig;
-sig = info-si_signo;
+int sig = info-si_signo;
tinfo-si_signo = tswap32(sig);
tinfo-si_errno = tswap32(info-si_errno);
tinfo-si_code = tswap32(info-si_code);
-if (sig == SIGILL || sig == SIGFPE || sig == SIGSEGV ||
-sig == SIGBUS || sig == SIGTRAP) {
-tinfo-_sifields._sigfault._addr =
-tswapal(info-_sifields._sigfault._addr);
-} else if (sig == SIGIO) {
- tinfo-_sifields._sigpoll._fd = tswap32(info-_sifields._sigpoll._fd);
+
+if (sig == TARGET_SIGILL || sig == TARGET_SIGFPE || sig == TARGET_SIGSEGV
+|| sig == TARGET_SIGBUS || sig == TARGET_SIGTRAP) {
+tinfo-_sifields._sigfault._addr
+= tswapal(info-_sifields._sigfault._addr);
+} else if (sig == TARGET_SIGIO) {
+tinfo-_sifields._sigpoll._band
+= tswap32(info-_sifields._sigpoll._band);
+tinfo-_sifields._sigpoll._fd = tswap32(info-_sifields._sigpoll._fd);
+} else if (sig == TARGET_SIGCHLD) {
+tinfo-_sifields._sigchld._pid
+= tswap32(info-_sifields._sigchld._pid);
+tinfo-_sifields._sigchld._uid
+= tswap32(info-_sifields._sigchld._uid);
+tinfo-_sifields._sigchld._status
+= tswap32(info-_sifields._sigchld._status);
+tinfo-_sifields._sigchld._utime
+= tswapal(info-_sifields._sigchld._utime);
+tinfo-_sifields._sigchld._stime
+= tswapal(info-_sifields._sigchld._stime);
} else if (sig = TARGET_SIGRTMIN) {
tinfo-_sifields._rt._pid = tswap32(info-_sifields._rt._pid);
tinfo-_sifields._rt._uid = tswap32(info-_sifields._rt._uid);
-tinfo-_sifields._rt._sigval.sival_ptr =
-tswapal(info-_sifields._rt._sigval.sival_ptr);
+tinfo-_sifields._rt._sigval.sival_ptr
+= tswapal(info-_sifields._rt._sigval.sival_ptr);
}
}
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 925e579..3676c72 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4920,7 +4920,7 @@ static int do_futex(target_ulong uaddr,
[Qemu-devel] [PATCH] fix gcc warnings when RESERVED_VA is 0
The current code, while correct, triggers a bunch of gcc warnings when
RESERVED_VA is 0 like so:
linux-user/syscall.c: In function 'do_shmat':
linux-user/syscall.c:3058: warning: comparison of unsigned expression 0 is
always false
linux-user/syscall.c: In function 'open_self_maps':
linux-user/syscall.c:4960: warning: comparison of unsigned expression 0 is
always false
linux-user/syscall.c:4960: warning: comparison of unsigned expression 0 is
always false
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
cpu-all.h |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/cpu-all.h b/cpu-all.h
index 5e07d28..0e5dcf0 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -202,10 +202,16 @@ extern unsigned long reserved_va;
#if HOST_LONG_BITS = TARGET_VIRT_ADDR_SPACE_BITS
#define h2g_valid(x) 1
#else
+/* Gcc likes to warn about comparing unsigned longs to 0, so cpp it away. */
+# if RESERVED_VA
+# define _h2g_reserved_va(x) ((x) RESERVED_VA)
+# else
+# define _h2g_reserved_va(x) 1
+# endif
#define h2g_valid(x) ({ \
unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
(__guest (1ul TARGET_VIRT_ADDR_SPACE_BITS)) \
-(!RESERVED_VA || (__guest RESERVED_VA)); \
+_h2g_reserved_va(__guest); \
})
#endif
--
1.7.9.7
[Qemu-devel] [PATCH] fix warnings from printf target addresses
Current code triggers:
memory.c: In function 'invalid_read':
memory.c:1001: warning: format '%#x' expects type 'unsigned int',
but argument 4 has type 'target_phys_addr_t'
memory.c: In function 'invalid_write':
memory.c:1013: warning: format '%#x' expects type 'unsigned int',
but argument 4 has type 'target_phys_addr_t'
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
memory.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/memory.c b/memory.c
index 58a242d..7d5f4a3 100644
--- a/memory.c
+++ b/memory.c
@@ -998,7 +998,8 @@ static uint64_t invalid_read(void *opaque,
target_phys_addr_t addr,
MemoryRegion *mr = opaque;
if (!mr-warning_printed) {
-fprintf(stderr, Invalid read from memory region %s at offset %#x\n,
mr-name, addr);
+fprintf(stderr, Invalid read from memory region %s at offset %#llx\n,
+mr-name, (unsigned long long)addr);
mr-warning_printed = true;
}
return -1U;
@@ -1010,7 +1011,8 @@ static void invalid_write(void *opaque,
target_phys_addr_t addr, uint64_t data,
MemoryRegion *mr = opaque;
if (!mr-warning_printed) {
-fprintf(stderr, Invalid write to memory region %s at offset %#x\n,
mr-name, addr);
+fprintf(stderr, Invalid write to memory region %s at offset %#llx\n,
+mr-name, (unsigned long long)addr);
mr-warning_printed = true;
}
}
--
1.7.9.7
[Qemu-devel] [PATCH] allow make {dist,}clean work w/out configure
There's no reason to require configure to run before running a clean target, so check MAKECMDGOALS before. Signed-off-by: Mike Frysinger vap...@gentoo.org --- Makefile |4 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index 1cd5bc8..e75740c 100644 --- a/Makefile +++ b/Makefile @@ -14,9 +14,11 @@ config-host.mak: $(SRC_PATH)/configure @sed -n /.*Configured with/s/[^:]*: //p $@ | sh else config-host.mak: +ifeq ($(findstring clean,$(MAKECMDGOALS)),) @echo Please call configure before running make! @exit 1 endif +endif GENERATED_HEADERS = config-host.h trace.h qemu-options.def ifeq ($(TRACE_BACKEND),dtrace) @@ -398,7 +400,9 @@ qemu-doc.dvi qemu-doc.html qemu-doc.info qemu-doc.pdf: \ # Add a dependency on the generated files, so that they are always # rebuilt before other object files +ifeq ($(findstring clean,$(MAKECMDGOALS)),) Makefile: $(GENERATED_HEADERS) +endif # Include automatically generated dependency files # Dependencies in Makefile.objs files come from our recursive subdir rules -- 1.7.9.7
