Re: [Qemu-devel] [PATCH 08/32] kvm/openpic: in-kernel mpic support
Am 30.06.2013 03:44, schrieb Alexander Graf: From: Scott Wood scottw...@freescale.com Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood scottw...@freescale.com [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build] Signed-off-by: Alexander Graf ag...@suse.de --- default-configs/ppc-softmmu.mak | 1 + default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/openpic_kvm.c | 252 ++ hw/ppc/e500.c | 79 +++- include/hw/ppc/openpic.h | 2 +- target-ppc/kvm-stub.c | 6 + 7 files changed, 336 insertions(+), 6 deletions(-) create mode 100644 hw/intc/openpic_kvm.c I had objected to the subject, and this patch is not bisectable since you didn't squash my ppcemb-softmmu build fix. Please do. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [Bug 1196145] [NEW] usb-host: hostaddr=0XX is parsed as octal number
Public bug reported: when doing device_add usb-host,hostaddr=010 taking 010 in the format of both lsusb or udev, qemu parses an octal number and assumes hostaddr=8. (i used a 2.0 device on the ehci.0 bus) at least to me that is confusing. also: when adding a non-existent usb device (bogus hostaddr), the following is created according to 'usb info': Device 1.0, Port 1, Speed 1.5 Mb/s, Product USB Host Device in usb_qdev_init(): usb_claim_port is called but usb_device_init does not report an error and thus usb_release_port is not called. ** Affects: qemu Importance: Undecided Status: New ** Tags: usb -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1196145 Title: usb-host: hostaddr=0XX is parsed as octal number Status in QEMU: New Bug description: when doing device_add usb-host,hostaddr=010 taking 010 in the format of both lsusb or udev, qemu parses an octal number and assumes hostaddr=8. (i used a 2.0 device on the ehci.0 bus) at least to me that is confusing. also: when adding a non-existent usb device (bogus hostaddr), the following is created according to 'usb info': Device 1.0, Port 1, Speed 1.5 Mb/s, Product USB Host Device in usb_qdev_init(): usb_claim_port is called but usb_device_init does not report an error and thus usb_release_port is not called. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1196145/+subscriptions
[Qemu-devel] [Bug 1196145] Re: usb-host: hostaddr=0XX is parsed as octal number
ps: when using host-libusb.c and tested on 1.5.1.tgz -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1196145 Title: usb-host: hostaddr=0XX is parsed as octal number Status in QEMU: New Bug description: when doing device_add usb-host,hostaddr=010 taking 010 in the format of both lsusb or udev, qemu parses an octal number and assumes hostaddr=8. (i used a 2.0 device on the ehci.0 bus) at least to me that is confusing. also: when adding a non-existent usb device (bogus hostaddr), the following is created according to 'usb info': Device 1.0, Port 1, Speed 1.5 Mb/s, Product USB Host Device in usb_qdev_init(): usb_claim_port is called but usb_device_init does not report an error and thus usb_release_port is not called. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1196145/+subscriptions
Re: [Qemu-devel] [PATCH 27/32] PPC: Introduce an alias cache for faster lookups
Am 30.06.2013 03:45, schrieb Alexander Graf:
When running QEMU with -cpu ? we walk through every alias for every
target CPU we know about. This takes several seconds on my very fast
host system.
Let's introduce a class object cache in the alias table. Using that we
don't have to go through the tedious work of finding our target class.
Instead, we can just go directly from the alias name to the target class
pointer.
This patch brings -cpu ? to reasonable times again.
Before:
real0m4.716s
After:
real0m0.025s
Signed-off-by: Alexander Graf ag...@suse.de
I had objected to this patch being not the right solution to the problem.
---
target-ppc/cpu-models.c | 2 +-
target-ppc/cpu-models.h | 3 ++-
target-ppc/translate_init.c | 32 +++-
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 17f56b7..9bb68c8 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1227,7 +1227,7 @@
/***/
/* PowerPC CPU aliases */
-const PowerPCCPUAlias ppc_cpu_aliases[] = {
+PowerPCCPUAlias ppc_cpu_aliases[] = {
{ 403, 403GC },
{ 405, 405D4 },
{ 405CR, 405CRc },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index a94f835..262ca47 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -31,9 +31,10 @@
typedef struct PowerPCCPUAlias {
const char *alias;
const char *model;
+ObjectClass *klass;
And please don't spread this deliberate misspelling. When I did, I was
flamed and the solution was to use oc for ObjectClass, cc for CPUClass,
etc. Your patch still keeps traversing the class list with O(n).
} PowerPCCPUAlias;
-extern const PowerPCCPUAlias ppc_cpu_aliases[];
+extern PowerPCCPUAlias ppc_cpu_aliases[];
/*/
/* PVR definitions for most known PowerPC
*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f01e9e7..45b4053 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7934,6 +7934,28 @@ static gint ppc_cpu_compare_class_name(gconstpointer
a, gconstpointer b)
#include ctype.h
+static ObjectClass *ppc_cpu_class_by_name(const char *name);
+
+static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
+{
+ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
+
+/* Cache target class lookups in the alias table */
+if (!alias-klass) {
+alias-klass = ppc_cpu_class_by_name(alias-model);
+if (!alias-klass) {
+/* Fast check for non-existing aliases */
+alias-klass = invalid_class;
+}
+}
+
+if (alias-klass == invalid_class) {
+return NULL;
+} else {
+return alias-klass;
+}
+}
Instead of saving bogus values with meaning no class we should drop
the ifdef'fery and make all types available. Our plan was to add one or
more flags to PowerPCCPUClass.
Andreas
+
static ObjectClass *ppc_cpu_class_by_name(const char *name)
{
GSList *list, *item;
@@ -7961,7 +7983,7 @@ static ObjectClass *ppc_cpu_class_by_name(const char
*name)
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
-return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
+return ppc_cpu_class_by_alias(ppc_cpu_aliases[i]);
}
}
@@ -8051,8 +8073,8 @@ static void ppc_cpu_list_entry(gpointer data, gpointer
user_data)
(*s-cpu_fprintf)(s-file, PowerPC %-16s PVR %08x\n,
name, pcc-pvr);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
-const PowerPCCPUAlias *alias = ppc_cpu_aliases[i];
-ObjectClass *alias_oc = ppc_cpu_class_by_name(alias-model);
+PowerPCCPUAlias *alias = ppc_cpu_aliases[i];
+ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
if (alias_oc != oc) {
continue;
@@ -8119,12 +8141,12 @@ CpuDefinitionInfoList
*arch_query_cpu_definitions(Error **errp)
g_slist_free(list);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
-const PowerPCCPUAlias *alias = ppc_cpu_aliases[i];
+PowerPCCPUAlias *alias = ppc_cpu_aliases[i];
ObjectClass *oc;
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
-oc = ppc_cpu_class_by_name(alias-model);
+oc = ppc_cpu_class_by_alias(alias);
if (oc == NULL) {
continue;
}
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [Qemu-ppc] [PATCH] RFCv3 kvm irqfd: support msimessage to irq translation in PHB
On Sun, 2013-06-30 at 10:59 +1000, Alexey Kardashevskiy wrote: 1) A PCI bus function to do the MSI - virq mapping 2) On x86 (and e500), this is implemented by calling kvm_irqchip_add_msi_route() 3) On pseries, this just returns msi-data Perhaps (2) can just be the default PCI bus implementation to simplify things. hw/pci/pci.c does not have any kvm code yet and I would like not to be the first person who tries adding this there :) But ok, I'll do it. Unless I'm confused (which is very possible) I seem to remember that there was duplication of that MSI / KVM mapping between virtio-pci and vfio as well, so it makes sense to move it to the PCI code. Cheers, Ben.
Re: [Qemu-devel] [PATCH 02/15] PPC: g3beige: Move secondary IDE bus to mac-io
Am 30.06.2013 03:26, schrieb Alexander Graf:
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- fix IRQ mapping
---
hw/ide/macio.c| 2 +-
hw/misc/macio/macio.c | 95
+--
hw/ppc/mac_oldworld.c | 17 +
3 files changed, 64 insertions(+), 50 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a1952b0..7a1c573 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -363,7 +363,7 @@ static void macio_ide_register_types(void)
type_register_static(macio_ide_type_info);
}
-/* hd_table must contain 4 block drivers */
+/* hd_table must contain 2 block drivers */
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
{
int i;
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index fd4c8e5..d9971e2 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -51,11 +51,9 @@ typedef struct OldWorldMacIOState {
/* private */
MacIOState parent_obj;
/* public */
-
-qemu_irq irqs[3];
-
+qemu_irq irqs[5];
MacIONVRAMState nvram;
-MACIOIDEState ide;
+MACIOIDEState ide[2];
} OldWorldMacIOState;
I had asked you to please keep my spacing: It separates parent field,
local fields (IRQs) and child fields.
#define NEWWORLD_MACIO(obj) \
@@ -147,18 +145,32 @@ static int macio_common_initfn(PCIDevice *d)
return 0;
}
+static int macio_initfn_ide(MacIOState *s, MACIOIDEState *ide, qemu_irq irq0,
+qemu_irq irq1, int dmaid)
macio_realize_ide would be a better name since PCIDevices still use
their legacy initfn.
Otherwise looks good.
Andreas
+{
+SysBusDevice *sysbus_dev;
+
+sysbus_dev = SYS_BUS_DEVICE(ide);
+sysbus_connect_irq(sysbus_dev, 0, irq0);
+sysbus_connect_irq(sysbus_dev, 1, irq1);
+macio_ide_register_dma(ide, s-dbdma, dmaid);
+return qdev_init(DEVICE(ide));
+}
+
static int macio_oldworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+int i;
+int cur_irq = 0;
int ret = macio_common_initfn(d);
if (ret 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(s-cuda);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[0]);
+sysbus_connect_irq(sysbus_dev, 0, os-irqs[cur_irq++]);
ret = qdev_init(DEVICE(os-nvram));
if (ret 0) {
@@ -174,23 +186,39 @@ static int macio_oldworld_initfn(PCIDevice *d)
memory_region_add_subregion(s-bar, 0x0, s-pic_mem);
}
-sysbus_dev = SYS_BUS_DEVICE(os-ide);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[1]);
-sysbus_connect_irq(sysbus_dev, 1, os-irqs[2]);
-macio_ide_register_dma(os-ide, s-dbdma, 0x16);
-ret = qdev_init(DEVICE(os-ide));
-if (ret 0) {
-return ret;
+/* IDE buses */
+for (i = 0; i ARRAY_SIZE(os-ide); i++) {
+qemu_irq irq0 = os-irqs[cur_irq++];
+qemu_irq irq1 = os-irqs[cur_irq++];
+
+ret = macio_initfn_ide(s, os-ide[i], irq0, irq1, 0x16 + (i * 4));
+if (ret 0) {
+return ret;
+}
}
return 0;
}
+static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
+{
+gchar *name;
+
+object_initialize(ide, TYPE_MACIO_IDE);
+qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
+memory_region_add_subregion(s-bar, 0x1f000 + ((index + 1) * 0x1000),
+ide-mem);
+name = g_strdup_printf(ide[%i], index);
+object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
+g_free(name);
+}
+
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
+int i;
qdev_init_gpio_out(DEVICE(obj), os-irqs, ARRAY_SIZE(os-irqs));
@@ -199,10 +227,9 @@ static void macio_oldworld_init(Object *obj)
qdev_prop_set_uint32(dev, size, 0x2000);
qdev_prop_set_uint32(dev, it_shift, 4);
-object_initialize(os-ide, TYPE_MACIO_IDE);
-qdev_set_parent_bus(DEVICE(os-ide), sysbus_get_default());
-memory_region_add_subregion(s-bar, 0x1f000 + (1 * 0x1000),
os-ide.mem);
-object_property_add_child(obj, ide, OBJECT(os-ide), NULL);
+for (i = 0; i 2; i++) {
+macio_init_ide(s, os-ide[i], i);
+}
}
static int macio_newworld_initfn(PCIDevice *d)
@@ -210,35 +237,30 @@ static int macio_newworld_initfn(PCIDevice *d)
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+int i;
+int cur_irq = 0;
int ret = macio_common_initfn(d);
Re: [Qemu-devel] [PATCH 04/15] PPC: dbdma: Replace tabs with spaces
Am 30.06.2013 03:26, schrieb Alexander Graf:
s/^I//g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 102
+++---
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 2fc7f87..ab174f5 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -85,75 +85,75 @@
/* Bits in control and status registers */
-#define RUN 0x8000
-#define PAUSE0x4000
-#define FLUSH0x2000
-#define WAKE 0x1000
-#define DEAD 0x0800
-#define ACTIVE 0x0400
-#define BT 0x0100
-#define DEVSTAT 0x00ff
+#define RUN0x8000
+#define PAUSE 0x4000
+#define FLUSH 0x2000
+#define WAKE 0x1000
+#define DEAD 0x0800
+#define ACTIVE 0x0400
+#define BT 0x0100
+#define DEVSTAT0x00ff
/*
* DBDMA command structure. These fields are all little-endian!
*/
typedef struct dbdma_cmd {
-uint16_t req_count;/* requested byte transfer count */
-uint16_t command; /* command word (has bit-fields) */
-uint32_t phy_addr; /* physical data address */
-uint32_t cmd_dep; /* command-dependent field */
-uint16_t res_count;/* residual count after completion */
-uint16_t xfer_status; /* transfer status */
+uint16_t req_count; /* requested byte transfer count */
+uint16_t command;/* command word (has bit-fields) */
+uint32_t phy_addr; /* physical data address */
+uint32_t cmd_dep;/* command-dependent field */
+uint16_t res_count; /* residual count after completion */
+uint16_t xfer_status;/* transfer status */
} dbdma_cmd;
/* DBDMA command values in command field */
#define COMMAND_MASK0xf000
-#define OUTPUT_MORE 0x /* transfer memory data to stream */
-#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
-#define INPUT_MORE 0x2000 /* transfer stream data to memory */
-#define INPUT_LAST 0x3000 /* ditto, expect end marker */
-#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
-#define LOAD_WORD0x5000 /* read word (4 bytes) from device reg */
-#define DBDMA_NOP0x6000 /* do nothing */
-#define DBDMA_STOP 0x7000 /* suspend processing */
+#define OUTPUT_MORE 0x/* transfer memory data to stream */
+#define OUTPUT_LAST 0x1000/* ditto followed by end marker */
+#define INPUT_MORE 0x2000/* transfer stream data to memory */
+#define INPUT_LAST 0x3000/* ditto, expect end marker */
+#define STORE_WORD 0x4000/* write word (4 bytes) to device reg
*/
+#define LOAD_WORD 0x5000/* read word (4 bytes) from device reg
*/
+#define DBDMA_NOP 0x6000/* do nothing */
+#define DBDMA_STOP 0x7000/* suspend processing */
/* Key values in command field */
#define KEY_MASK0x0700
-#define KEY_STREAM0 0x /* usual data stream */
-#define KEY_STREAM1 0x0100 /* control/status stream */
-#define KEY_STREAM2 0x0200 /* device-dependent stream */
-#define KEY_STREAM3 0x0300 /* device-dependent stream */
-#define KEY_STREAM4 0x0400 /* reserved */
-#define KEY_REGS 0x0500 /* device register space */
-#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
-#define KEY_DEVICE 0x0700 /* device memory-mapped space */
+#define KEY_STREAM0 0x/* usual data stream */
+#define KEY_STREAM1 0x0100/* control/status stream */
+#define KEY_STREAM2 0x0200/* device-dependent stream */
+#define KEY_STREAM3 0x0300/* device-dependent stream */
+#define KEY_STREAM4 0x0400/* reserved */
+#define KEY_REGS0x0500/* device register space */
+#define KEY_SYSTEM 0x0600/* system memory-mapped space */
+#define KEY_DEVICE 0x0700/* device memory-mapped space */
/* Interrupt control values in command field */
#define INTR_MASK 0x0030
-#define INTR_NEVER 0x /* don't interrupt */
-#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
-#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
-#define INTR_ALWAYS 0x0030 /* always interrupt */
+#define INTR_NEVER 0x/* don't interrupt */
+#define INTR_IFSET 0x0010/* intr if condition bit is 1 */
+#define INTR_IFCLR 0x0020/* intr if condition bit is 0 */
+#define INTR_ALWAYS 0x0030/* always interrupt */
/* Branch control values in command field */
#define BR_MASK 0x000c
-#define BR_NEVER 0x /* don't branch */
-#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
-#define BR_IFCLR 0x0008 /* branch if
Re: [Qemu-devel] [PATCH 05/15] PPC: Mac: Add debug prints in macio and dbdma code
Am 30.06.2013 03:26, schrieb Alexander Graf:
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disabled by default of course.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/macio.c| 39 ++-
hw/misc/macio/mac_dbdma.c | 12 ++--
2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 82409dc..5cbc923 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -30,6 +30,17 @@
#include hw/ide/internal.h
+/* debug MACIO */
+// #define DEBUG_MACIO
+
+#ifdef DEBUG_MACIO
+#define MACIO_DPRINTF(fmt, ...) \
+do { printf(MACIO: %s: fmt , __func__, ## __VA_ARGS__); } while (0)
+#else
+#define MACIO_DPRINTF(fmt, ...)
+#endif
Please use the pattern you suggested yourself of having an if
(DEBUG_MACIO_ENABLED) {...} inside the macro rather than a second
MACIO_DPRINTF(), so that the newly added debug output doesn'T bitrot.
Andreas
+
+
/***/
/* MacIO based PowerPC IDE */
@@ -48,6 +59,8 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
goto done;
}
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
+
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -59,15 +72,22 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
s-io_buffer_index = 0x7ff;
}
-if (s-packet_transfer_size = 0)
+/* end of transfer ? */
+if (s-packet_transfer_size = 0) {
+MACIO_DPRINTF(end of transfer\n);
ide_atapi_cmd_ok(s);
+}
+/* end of DMA ? */
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
Both comments duplicate your debug output module question mark. :)
/* launch next transfer */
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
s-io_buffer_size = io-len;
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
@@ -76,12 +96,17 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=%d size=%d, cmd_cmd=%d\n,
+ (s-lba 2) + (s-io_buffer_index 9),
+ s-packet_transfer_size, s-dma_cmd);
+
m-aiocb = dma_bdrv_read(s-bs, s-sg,
(int64_t)(s-lba 2) + (s-io_buffer_index
9),
pmac_ide_atapi_transfer_cb, io);
return;
done:
+MACIO_DPRINTF(done DMA\n);
bdrv_acct_done(s-bs, s-acct);
io-dma_end(opaque);
}
@@ -95,6 +120,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
int64_t sector_num;
if (ret 0) {
+MACIO_DPRINTF(DMA error\n);
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
ide_dma_error(s);
@@ -102,6 +128,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
}
sector_num = ide_get_sector(s);
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -113,12 +140,14 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
/* end of transfer ? */
if (s-nsector == 0) {
+MACIO_DPRINTF(end of transfer\n);
s-status = READY_STAT | SEEK_STAT;
ide_set_irq(s-bus);
}
/* end of DMA ? */
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
@@ -127,12 +156,18 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
s-io_buffer_index = 0;
s-io_buffer_size = io-len;
+
Intentionally two white lines?
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
address_space_memory);
qemu_sglist_add(s-sg, io-addr, io-len);
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=% PRId64 n=%d, nsector=%d, cmd_cmd=%d\n,
+ sector_num, n, s-nsector, s-dma_cmd);
+
switch (s-dma_cmd) {
case IDE_DMA_READ:
m-aiocb = dma_bdrv_read(s-bs, s-sg, sector_num,
@@ -162,6 +197,8 @@ static void pmac_ide_transfer(DBDMA_io *io)
MACIOIDEState *m = io-opaque;
IDEState *s = idebus_active_if(m-bus);
+MACIO_DPRINTF(\n, __LINE__);
The argument is unused.
+
s-io_buffer_size = 0;
if (s-drive_kind == IDE_CD) {
bdrv_acct_start(s-bs, s-acct, io-len, BDRV_ACCT_READ);
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index ab174f5..903604d 100644
---
Re: [Qemu-devel] [PATCH 12/15] PPC: dbdma: Move processing to io
Am 30.06.2013 03:27, schrieb Alexander Graf:
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 10 ++
include/hw/ppc/mac_dbdma.h | 3 ++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 324ac54..91b9eaf 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -275,7 +275,9 @@ static void dbdma_end(DBDMA_io *io)
conditional_branch(ch);
wait:
-ch-processing = 0;
+/* Indicate that we're ready for a new DMA round */
+ch-io.processing = 0;
+
if ((ch-regs[DBDMA_STATUS] RUN)
(ch-regs[DBDMA_STATUS] ACTIVE))
channel_run(ch);
@@ -301,7 +303,7 @@ static void start_output(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 1;
-ch-processing = 1;
+ch-io.processing = 1;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -327,7 +329,7 @@ static void start_input(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 0;
-ch-processing = 1;
+ch-io.processing = 1;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -525,7 +527,7 @@ static void DBDMA_run(DBDMAState *s)
for (channel = 0; channel DBDMA_CHANNELS; channel++) {
DBDMA_channel *ch = s-channels[channel];
uint32_t status = ch-regs[DBDMA_STATUS];
-if (!ch-processing (status RUN) (status ACTIVE)) {
+if (!ch-io.processing (status RUN) (status ACTIVE)) {
channel_run(ch);
}
}
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index eb8e0f0..8ad1b6e 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -37,6 +37,8 @@ struct DBDMA_io {
int is_last;
int is_dma_out;
DBDMA_end dma_end;
+/* DMA is in progress, don't start another one */
+int processing;
Can it be changed to bool (its users to true/false) while at it?
Andreas
};
/*
@@ -148,7 +150,6 @@ typedef struct DBDMA_channel {
DBDMA_rw rw;
DBDMA_flush flush;
dbdma_cmd current;
-int processing;
} DBDMA_channel;
typedef struct {
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [Qemu-ppc] [PATCH] RFCv3 kvm irqfd: support msimessage to irq translation in PHB
On 06/30/2013 04:32 PM, Benjamin Herrenschmidt wrote: On Sun, 2013-06-30 at 10:59 +1000, Alexey Kardashevskiy wrote: 1) A PCI bus function to do the MSI - virq mapping 2) On x86 (and e500), this is implemented by calling kvm_irqchip_add_msi_route() 3) On pseries, this just returns msi-data Perhaps (2) can just be the default PCI bus implementation to simplify things. hw/pci/pci.c does not have any kvm code yet and I would like not to be the first person who tries adding this there :) But ok, I'll do it. Unless I'm confused (which is very possible) I seem to remember that there was duplication of that MSI / KVM mapping between virtio-pci and vfio as well, so it makes sense to move it to the PCI code. No, you are right and this is what Anthony is telling me to do. -- Alexey
Re: [Qemu-devel] [PATCH] Avoid use of QOM type name macros in VMStateDescriptions
Am 27.06.2013 13:03, schrieb Peter Maydell:
The name field in a VMStateDescription is part of the migration state
versioning, so changing it will break migration. It's therefore a
bad idea to use a QOM typename macro to initialize it, because in
general we're free to rename QOM types as part of code refactoring
and cleanup. For the handful of devices that were doing this by
mistake, replace the QOM typenames with the corresponding literal
strings.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
As per recent discussion. There are also a few devices which use
the typename in memory_region_init_io(). Since that is suboptimal
but not a problem in the way that possible migration breaks would
be, I haven't fixed those since they'd just clash with Paolo's
memory-region-owner patches.
The one I didn't touch was hw/usb/host-linux.c, since that changes
the QOM typename and the VMStateDescription name depending on
whether QEMU was built with CONFIG_USB_LIBUSB defined or not.
That seems a bit fishy to me but I've left it alone.
hw/i2c/exynos4210_i2c.c |2 +-
hw/scsi/vmw_pvscsi.c |2 +-
hw/timer/imx_epit.c |2 +-
hw/timer/imx_gpt.c|2 +-
hw/usb/ccid-card-passthru.c |2 +-
hw/usb/dev-smartcard-reader.c |2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/i2c/exynos4210_i2c.c b/hw/i2c/exynos4210_i2c.c
index 196f889..a75abef 100644
--- a/hw/i2c/exynos4210_i2c.c
+++ b/hw/i2c/exynos4210_i2c.c
@@ -271,7 +271,7 @@ static const MemoryRegionOps exynos4210_i2c_ops = {
};
static const VMStateDescription exynos4210_i2c_vmstate = {
-.name = TYPE_EXYNOS4_I2C,
+.name = exynos4210.i2c,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 7cf4044..f2f0c00 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -1136,7 +1136,7 @@ pvscsi_post_load(void *opaque, int version_id)
}
static const VMStateDescription vmstate_pvscsi = {
-.name = TYPE_PVSCSI,
+.name = pvscsi,
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
Apparently someone confused TypeInfo and VMStateDescription here, the
TypeInfo .name is by contrast not using the constant - fixing up.
Rest is verified to match constants.
Applied to my new qom-next staging tree:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7cdb006..8cefd74a 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -370,7 +370,7 @@ static const MemoryRegionOps imx_epit_ops = {
};
static const VMStateDescription vmstate_imx_timer_epit = {
-.name = TYPE_IMX_EPIT,
+.name = imx.epit,
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index de53b13..eebd2b7 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -142,7 +142,7 @@ typedef struct {
} IMXGPTState;
static const VMStateDescription vmstate_imx_timer_gpt = {
-.name = TYPE_IMX_GPT,
+.name = imx.gpt,
.version_id = 3,
.minimum_version_id = 3,
.minimum_version_id_old = 3,
diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c
index 01c7e6f..5f01ff1 100644
--- a/hw/usb/ccid-card-passthru.c
+++ b/hw/usb/ccid-card-passthru.c
@@ -364,7 +364,7 @@ static int passthru_exitfn(CCIDCardState *base)
}
static VMStateDescription passthru_vmstate = {
-.name = PASSTHRU_DEV_NAME,
+.name = ccid-card-passthru,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
index 125cc2c..b33eb25 100644
--- a/hw/usb/dev-smartcard-reader.c
+++ b/hw/usb/dev-smartcard-reader.c
@@ -1397,7 +1397,7 @@ static VMStateDescription usb_device_vmstate = {
};
static VMStateDescription ccid_vmstate = {
-.name = CCID_DEV_NAME,
+.name = usb-ccid,
.version_id = 1,
.minimum_version_id = 1,
.post_load = ccid_post_load,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 03/30] net/pcnet-pci: QOM Upcast Sweep
Am 24.06.2013 08:52, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/net/pcnet-pci.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index 9df2b87..b1afbf4 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -43,6 +43,10 @@
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH
+#define TYPE_PCI_PC_NET pcnet
I'm wondering whether we should rename this PCNET rather than PC_NET,
but I'm queuing it as is. Thanks,
Andreas
+
+#define PCI_PC_NET(obj) \
+ OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PC_NET)
typedef struct {
PCIDevice pci_dev;
@@ -273,7 +277,7 @@ static void pci_pcnet_cleanup(NetClientState *nc)
static void pci_pcnet_uninit(PCIDevice *dev)
{
-PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
+PCIPCNetState *d = PCI_PC_NET(dev);
memory_region_destroy(d-state.mmio);
memory_region_destroy(d-io_bar);
@@ -293,7 +297,7 @@ static NetClientInfo net_pci_pcnet_info = {
static int pci_pcnet_init(PCIDevice *pci_dev)
{
-PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
+PCIPCNetState *d = PCI_PC_NET(pci_dev);
PCNetState *s = d-state;
uint8_t *pci_conf;
@@ -329,12 +333,12 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
s-phys_mem_write = pci_physical_memory_write;
s-dma_opaque = pci_dev;
-return pcnet_common_init(pci_dev-qdev, s, net_pci_pcnet_info);
+return pcnet_common_init(DEVICE(pci_dev), s, net_pci_pcnet_info);
}
static void pci_reset(DeviceState *dev)
{
-PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
+PCIPCNetState *d = PCI_PC_NET(dev);
pcnet_h_reset(d-state);
}
@@ -362,7 +366,7 @@ static void pcnet_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo pcnet_info = {
-.name = pcnet,
+.name = TYPE_PCI_PC_NET,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIPCNetState),
.class_init= pcnet_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] RFCv3 kvm irqfd: support msimessage to irq translation in PHB
On 06/30/2013 12:28 AM, Anthony Liguori wrote: On Sat, Jun 29, 2013 at 8:45 AM, Alexey Kardashevskiy a...@ozlabs.ru wrote: On PPC64 systems MSI Messages are translated to system IRQ in a PCI host bridge. This is already supported for emulated MSI/MSIX but not for irqfd where the current QEMU allocates IRQ numbers from irqchip and maps MSIMessages to those IRQ in the host kernel. The patch extends irqfd support in order to avoid unnecessary mapping and reuse the one which already exists in a PCI host bridge. Specifically, a map_msi callback is added to PCIBus and pci_bus_map_msi() to PCI API. The latter returns -1 if a specific PHB does not provide with any trsnslation so the existing code will work. I think there's a bit of confusion here. The kernel needs a virq number to create an eventfd. virq is just a KVM concept, it doesn't correspond to anything useful in hardware. On pseries, there is a 1-1 mapping between XICS IRQs and VIRQs and MSI can be trivially mapped to a virq. On x86, we need to call a special kernel function which essentially creates an apic message-virq mapping such that we can deliver the irqfd. So what this should look like is: 1) A PCI bus function to do the MSI - virq mapping 2) On x86 (and e500), this is implemented by calling kvm_irqchip_add_msi_route() 3) On pseries, this just returns msi-data Perhaps (2) can just be the default PCI bus implementation to simplify things. Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru --- Looks like we agreed that in general PHB is the right place for this, not KVM, so I am trying again. Probably something should be done to kvm_irqchip_update_msi_route() as well but I do not really understand what exactly. Any suggestions? Ah. Everybody ignored, I'll try asking again :) kvm_irqchip_update_msi_route() - where should it go? What is it for? virtio-pci and pci device assignment use it but vfio does not - is it a bug of vfio? Thanks. -- Alexey
Re: [Qemu-devel] [PATCH v2 04/30] usb/hcd-xhci: QOM Upcast Sweep
Am 24.06.2013 08:52, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/usb/hcd-xhci.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 91633ed..0146711 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -482,6 +482,11 @@ struct XHCIState {
XHCIRing cmd_ring;
};
+#define TYPE_XHCI nec-usb-xhci
+
+#define XHCI(obj) \
+OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
+
typedef struct XHCIEvRingSeg {
uint32_t addr_low;
uint32_t addr_high;
@@ -2681,7 +2686,7 @@ static void xhci_port_reset(XHCIPort *port)
static void xhci_reset(DeviceState *dev)
{
-XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
+XHCIState *xhci = XHCI(dev);
int i;
trace_usb_xhci_reset();
@@ -2926,6 +2931,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
+DeviceState *d = DEVICE(ptr);
trace_usb_xhci_oper_write(reg, val);
@@ -2939,7 +2945,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
xhci-usbcmd = val 0xc0f;
xhci_mfwrap_update(xhci);
if (val USBCMD_HCRST) {
-xhci_reset(xhci-pci_dev.qdev);
+xhci_reset(d);
}
xhci_intx_update(xhci);
break;
@@ -3267,6 +3273,7 @@ static USBBusOps xhci_bus_ops = {
static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
{
+DeviceState *d = DEVICE(xhci);
This is duplicating the dev argument. I'll drop that and rename your
variable to dev instead:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Thanks,
Andreas
XHCIPort *port;
int i, usbports, speedmask;
@@ -3281,7 +3288,7 @@ static void usb_xhci_init(XHCIState *xhci, DeviceState
*dev)
usbports = MAX(xhci-numports_2, xhci-numports_3);
xhci-numports = xhci-numports_2 + xhci-numports_3;
-usb_bus_new(xhci-bus, xhci_bus_ops, xhci-pci_dev.qdev);
+usb_bus_new(xhci-bus, xhci_bus_ops, d);
for (i = 0; i usbports; i++) {
speedmask = 0;
@@ -3313,14 +3320,14 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
{
int i, ret;
-XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
+XHCIState *xhci = XHCI(dev);
xhci-pci_dev.config[PCI_CLASS_PROG] = 0x30;/* xHCI */
xhci-pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
xhci-pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
xhci-pci_dev.config[0x60] = 0x30; /* release number */
-usb_xhci_init(xhci, dev-qdev);
+usb_xhci_init(xhci, DEVICE(dev));
if (xhci-numintrs MAXINTRS) {
xhci-numintrs = MAXINTRS;
@@ -3581,7 +3588,7 @@ static void xhci_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo xhci_info = {
-.name = nec-usb-xhci,
+.name = TYPE_XHCI,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(XHCIState),
.class_init= xhci_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 05/30] scsi/lsi53c895a: QOM Upcast Sweep
Am 24.06.2013 08:53, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/scsi/lsi53c895a.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index 22b8e98..d488c5c 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -275,6 +275,11 @@ typedef struct {
uint32_t script_ram[2048];
} LSIState;
+#define TYPE_LSI53C895A lsi53c895a
+
+#define LSI53C895A(obj) \
+OBJECT_CHECK(LSIState, (obj), TYPE_LSI53C895A)
+
static inline int lsi_irq_on_rsl(LSIState *s)
{
return (s-sien0 LSI_SIST0_RSL) (s-scid LSI_SCID_RRE);
@@ -653,7 +658,7 @@ static void lsi_request_free(LSIState *s, lsi_request *p)
static void lsi_request_cancelled(SCSIRequest *req)
{
-LSIState *s = DO_UPCAST(LSIState, dev.qdev, req-bus-qbus.parent);
+LSIState *s = LSI53C895A(req-bus-qbus.parent);
We should be using BUS() in place of -qbus, but since you're pretty
cleanly separating things in your series, we can do that as a follow-up.
Thanks, queued on qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
lsi_request *p = req-hba_private;
req-hba_private = NULL;
@@ -692,7 +697,7 @@ static int lsi_queue_req(LSIState *s, SCSIRequest *req,
uint32_t len)
/* Callback to indicate that the SCSI layer has completed a command. */
static void lsi_command_complete(SCSIRequest *req, uint32_t status, size_t
resid)
{
-LSIState *s = DO_UPCAST(LSIState, dev.qdev, req-bus-qbus.parent);
+LSIState *s = LSI53C895A(req-bus-qbus.parent);
int out;
out = (s-sstat1 PHASE_MASK) == PHASE_DO;
@@ -717,7 +722,7 @@ static void lsi_command_complete(SCSIRequest *req,
uint32_t status, size_t resid
/* Callback to indicate that the SCSI layer has completed a transfer. */
static void lsi_transfer_data(SCSIRequest *req, uint32_t len)
{
-LSIState *s = DO_UPCAST(LSIState, dev.qdev, req-bus-qbus.parent);
+LSIState *s = LSI53C895A(req-bus-qbus.parent);
int out;
assert(req-hba_private);
@@ -1726,7 +1731,7 @@ static void lsi_reg_writeb(LSIState *s, int offset,
uint8_t val)
lsi_execute_script(s);
}
if (val LSI_ISTAT0_SRST) {
-qdev_reset_all(s-dev.qdev);
+qdev_reset_all(DEVICE(s));
}
break;
case 0x16: /* MBOX0 */
@@ -1960,7 +1965,7 @@ static const MemoryRegionOps lsi_io_ops = {
static void lsi_scsi_reset(DeviceState *dev)
{
-LSIState *s = DO_UPCAST(LSIState, dev.qdev, dev);
+LSIState *s = LSI53C895A(dev);
lsi_soft_reset(s);
}
@@ -2061,7 +2066,7 @@ static const VMStateDescription vmstate_lsi_scsi = {
static void lsi_scsi_uninit(PCIDevice *d)
{
-LSIState *s = DO_UPCAST(LSIState, dev, d);
+LSIState *s = LSI53C895A(d);
memory_region_destroy(s-mmio_io);
memory_region_destroy(s-ram_io);
@@ -2080,7 +2085,8 @@ static const struct SCSIBusInfo lsi_scsi_info = {
static int lsi_scsi_init(PCIDevice *dev)
{
-LSIState *s = DO_UPCAST(LSIState, dev, dev);
+LSIState *s = LSI53C895A(dev);
+DeviceState *d = DEVICE(dev);
uint8_t *pci_conf;
pci_conf = s-dev.config;
@@ -2099,8 +2105,8 @@ static int lsi_scsi_init(PCIDevice *dev)
pci_register_bar(s-dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, s-ram_io);
QTAILQ_INIT(s-queue);
-scsi_bus_new(s-bus, dev-qdev, lsi_scsi_info, NULL);
-if (!dev-qdev.hotplugged) {
+scsi_bus_new(s-bus, d, lsi_scsi_info, NULL);
+if (!d-hotplugged) {
return scsi_bus_legacy_handle_cmdline(s-bus);
}
return 0;
@@ -2122,7 +2128,7 @@ static void lsi_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo lsi_info = {
-.name = lsi53c895a,
+.name = TYPE_LSI53C895A,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(LSIState),
.class_init= lsi_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 16/30] pci/*: QOM casting sweep
Am 24.06.2013 09:01, schrieb peter.crosthwa...@xilinx.com:
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index d35c2ee..aa45e77 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -252,9 +252,9 @@ static void shpc_free_devices_in_slot(SHPCDevice *shpc,
int slot)
for (devfn = PCI_DEVFN(pci_slot, 0);
devfn = PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
++devfn) {
-PCIDevice *affected_dev = shpc-sec_bus-devices[devfn];
+DeviceState *affected_dev = DEVICE(shpc-sec_bus-devices[devfn]);
if (affected_dev) {
Did you verify this works as expected? Or might we need
object_dynamic_cast() here? I remember we had issues with assertions in
the past, not sure if all are resolved...
Andreas
-qdev_free(affected_dev-qdev);
+qdev_free(affected_dev);
}
}
}
[snip]
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 08/30] ide/ich: QOM Upcast Sweep
Am 24.06.2013 08:55, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/ide/ahci.h | 5 +
hw/ide/ich.c | 10 +-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 341a571..916bef0 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -305,6 +305,11 @@ typedef struct AHCIPCIState {
AHCIState ahci;
} AHCIPCIState;
+#define TYPE_ICH_AHCI ich9-ahci
Let's be as precise as for the LSI SCSI HBA and name this ICH9. :)
+
+#define ICH_AHCI(obj) \
+OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH_AHCI)
Wondering if this is specific to ICH(9)? Alex?
Leaving it as is for now, renaming is an easy follow-up.
+
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 6c0c0c2..c3cbf2a 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -92,7 +92,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
static void pci_ich9_reset(DeviceState *dev)
{
-struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
+struct AHCIPCIState *d = ICH_AHCI(dev);
Let's drop the struct while touching the line.
Thanks, applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
ahci_reset(d-ahci);
}
@@ -102,9 +102,9 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
int sata_cap_offset;
uint8_t *sata_cap;
-d = DO_UPCAST(struct AHCIPCIState, card, dev);
+d = ICH_AHCI(dev);
-ahci_init(d-ahci, dev-qdev, pci_get_address_space(dev), 6);
+ahci_init(d-ahci, DEVICE(dev), pci_get_address_space(dev), 6);
pci_config_set_prog_interface(d-card.config, AHCI_PROGMODE_MAJOR_REV_1);
@@ -141,7 +141,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
static void pci_ich9_uninit(PCIDevice *dev)
{
struct AHCIPCIState *d;
-d = DO_UPCAST(struct AHCIPCIState, card, dev);
+d = ICH_AHCI(dev);
msi_uninit(dev);
ahci_uninit(d-ahci);
@@ -163,7 +163,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo ich_ahci_info = {
-.name = ich9-ahci,
+.name = TYPE_ICH_AHCI,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(AHCIPCIState),
.class_init= ich_ahci_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 09/30] ide/piix: QOM casting sweep
Am 24.06.2013 08:56, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Use standard QOM cast macro. Remove usage of DO_UPCAST and
direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/ide/piix.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index bf2856f..d0fdea3 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -135,7 +135,7 @@ static void pci_piix_init_ports(PCIIDEState *d) {
int i;
for (i = 0; i 2; i++) {
-ide_bus_new(d-bus[i], d-dev.qdev, i, 2);
+ide_bus_new(d-bus[i], DEVICE(d), i, 2);
ide_init_ioport(d-bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
ide_init2(d-bus[i], isa_get_irq(NULL, port_info[i].isairq));
@@ -159,7 +159,7 @@ static int pci_piix_ide_initfn(PCIDevice *dev)
bmdma_setup_bar(d);
pci_register_bar(d-dev, 4, PCI_BASE_ADDRESS_SPACE_IO, d-bmdma_bar);
-vmstate_register(d-dev.qdev, 0, vmstate_ide_pci, d);
+vmstate_register(DEVICE(dev), 0, vmstate_ide_pci, d);
pci_piix_init_ports(d);
@@ -173,7 +173,7 @@ static int pci_piix3_xen_ide_unplug(DeviceState *dev)
DriveInfo *di;
int i = 0;
-pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
+pci_dev = PCI_DEVICE(dev);
pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
This misses the actual type. Any reason for that?
Andreas
for (; i 3; i++) {
@@ -188,7 +188,7 @@ static int pci_piix3_xen_ide_unplug(DeviceState *dev)
drive_put_ref(di);
}
}
-qdev_reset_all((pci_ide-dev.qdev));
+qdev_reset_all(DEVICE(dev));
return 0;
}
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 12/30] virtio/vmware_vga: QOM casting sweep
display/vmware_vga: ... obviously.
Am 24.06.2013 08:58, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST and
direct - style casting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/display/vmware_vga.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index fd3569d..0e2aa3f 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -81,6 +81,11 @@ struct vmsvga_state_s {
int redraw_fifo_first, redraw_fifo_last;
};
+#define TYPE_VM_SVGA vmware-svga
+
+#define VM_SVGA(obj) \
+OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VM_SVGA)
Let's use VMWARE_VGA for uniqueness. Thanks, applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
+
struct pci_vmsvga_state_s {
PCIDevice card;
struct vmsvga_state_s chip;
@@ -1092,8 +1097,7 @@ static void vmsvga_update_display(void *opaque)
static void vmsvga_reset(DeviceState *dev)
{
-struct pci_vmsvga_state_s *pci =
-DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
+struct pci_vmsvga_state_s *pci = VM_SVGA(dev);
struct vmsvga_state_s *s = pci-chip;
s-index = 0;
@@ -1246,8 +1250,7 @@ static const MemoryRegionOps vmsvga_io_ops = {
static int pci_vmsvga_initfn(PCIDevice *dev)
{
-struct pci_vmsvga_state_s *s =
-DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
+struct pci_vmsvga_state_s *s = VM_SVGA(dev);
s-card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
s-card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
@@ -1299,7 +1302,7 @@ static void vmsvga_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo vmsvga_info = {
-.name = vmware-svga,
+.name = TYPE_VM_SVGA,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(struct pci_vmsvga_state_s),
.class_init= vmsvga_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 13/30] misc/ivshmem: QOM Upcast Sweep
Am 24.06.2013 08:59, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/misc/ivshmem.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 5658f73..fd40caf 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -48,6 +48,10 @@
#define IVSHMEM_DPRINTF(fmt, ...)
#endif
+#define TYPE_IVSHMEM ivshmem
+#define IVSHMEM(obj) \
+OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
+
typedef struct Peer {
int nb_eventfds;
EventNotifier *eventfds;
@@ -341,7 +345,7 @@ static void create_shared_memory_BAR(IVShmemState *s, int
fd) {
memory_region_init_ram_ptr(s-ivshmem, ivshmem.bar2,
s-ivshmem_size, ptr);
-vmstate_register_ram(s-ivshmem, s-dev.qdev);
+vmstate_register_ram(s-ivshmem, DEVICE(s-dev));
DEVICE(s)
memory_region_add_subregion(s-bar, 0, s-ivshmem);
/* region for shared memory */
@@ -469,7 +473,7 @@ static void ivshmem_read(void *opaque, const uint8_t *
buf, int flags)
incoming_fd, 0);
memory_region_init_ram_ptr(s-ivshmem,
ivshmem.bar2, s-ivshmem_size, map_ptr);
-vmstate_register_ram(s-ivshmem, s-dev.qdev);
+vmstate_register_ram(s-ivshmem, DEVICE(s-dev));
DEVICE(s)
Renaming the parent field showed that there are still some s-dev
accesses missed in this patch. Applying anyway to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
IMO such casting cleanup patches make the most sense when they are
complete in removing all accesses to the parent field and proving that
by renaming the parent field with the only remaining usage being in
VMSTATE_PCI(). We won't be able to drop DO_UPCAST() since it's being
used outside QOM in the block layer for instance. I'm hoping we can
squash a fixup so that we don't need to touch each device twice.
Regards,
Andreas
IVSHMEM_DPRINTF(guest h/w addr = % PRIu64 , size = % PRIu64 \n,
s-ivshmem_offset, s-ivshmem_size);
@@ -534,7 +538,7 @@ static void ivshmem_use_msix(IVShmemState * s)
static void ivshmem_reset(DeviceState *d)
{
-IVShmemState *s = DO_UPCAST(IVShmemState, dev.qdev, d);
+IVShmemState *s = IVSHMEM(d);
s-intrstatus = 0;
ivshmem_use_msix(s);
@@ -648,7 +652,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
s-ivshmem_size = ivshmem_get_size(s);
}
-register_savevm(s-dev.qdev, ivshmem, 0, 0, ivshmem_save,
ivshmem_load,
+register_savevm(DEVICE(dev), ivshmem, 0, 0, ivshmem_save, ivshmem_load,
dev);
/* IRQFD requires MSI */
@@ -780,10 +784,10 @@ static void pci_ivshmem_uninit(PCIDevice *dev)
memory_region_destroy(s-ivshmem_mmio);
memory_region_del_subregion(s-bar, s-ivshmem);
-vmstate_unregister_ram(s-ivshmem, s-dev.qdev);
+vmstate_unregister_ram(s-ivshmem, DEVICE(dev));
memory_region_destroy(s-ivshmem);
memory_region_destroy(s-bar);
-unregister_savevm(dev-qdev, ivshmem, s);
+unregister_savevm(DEVICE(dev), ivshmem, s);
}
static Property ivshmem_properties[] = {
@@ -813,7 +817,7 @@ static void ivshmem_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo ivshmem_info = {
-.name = ivshmem,
+.name = TYPE_IVSHMEM,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(IVShmemState),
.class_init= ivshmem_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 14/30] xen/xen_platform: QOM casting sweep
Am 24.06.2013 09:00, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/xen/xen_platform.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/hw/xen/xen_platform.c b/hw/xen/xen_platform.c
index b6c6793..f119c44 100644
--- a/hw/xen/xen_platform.c
+++ b/hw/xen/xen_platform.c
@@ -62,6 +62,10 @@ typedef struct PCIXenPlatformState {
int log_buffer_off;
} PCIXenPlatformState;
+#define TYPE_XEN_PLATFORM xen-platform
+#define XEN_PLATFORM(obj) \
+OBJECT_CHECK(PCIXenPlatformState, (obj), TYPE_XEN_PLATFORM)
+
#define XEN_PLATFORM_IOPORT 0x10
/* Send bytes to syslog */
@@ -88,7 +92,7 @@ static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
if (pci_get_word(d-config + PCI_CLASS_DEVICE) ==
PCI_CLASS_NETWORK_ETHERNET
strcmp(d-name, xen-pci-passthrough) != 0) {
-qdev_free(d-qdev);
+qdev_free(DEVICE(d));
}
}
@@ -103,7 +107,7 @@ static void unplug_disks(PCIBus *b, PCIDevice *d, void *o)
if (pci_get_word(d-config + PCI_CLASS_DEVICE) ==
PCI_CLASS_STORAGE_IDE
strcmp(d-name, xen-pci-passthrough) != 0) {
-qdev_unplug((d-qdev), NULL);
+qdev_unplug(DEVICE(d), NULL);
}
}
@@ -114,7 +118,7 @@ static void pci_unplug_disks(PCIBus *bus)
static void platform_fixed_ioport_writew(void *opaque, uint32_t addr,
uint32_t val)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
These are superfluous since PCIXenPlatformState is passed for both
MemoryRegionOps. Dropping these hunks.
Some usages of the parent field are still left behind.
Thanks, applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
switch (addr) {
case 0:
@@ -164,7 +168,7 @@ static void platform_fixed_ioport_writel(void *opaque,
uint32_t addr,
static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr,
uint32_t val)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
switch (addr) {
case 0: /* Platform flags */ {
@@ -187,7 +191,7 @@ static void platform_fixed_ioport_writeb(void *opaque,
uint32_t addr, uint32_t v
static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
switch (addr) {
case 0:
@@ -206,7 +210,7 @@ static uint32_t platform_fixed_ioport_readw(void *opaque,
uint32_t addr)
static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
switch (addr) {
case 0:
@@ -222,7 +226,7 @@ static uint32_t platform_fixed_ioport_readb(void *opaque,
uint32_t addr)
static void platform_fixed_ioport_reset(void *opaque)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
platform_fixed_ioport_writeb(s, 0, 0);
}
@@ -292,7 +296,7 @@ static uint64_t xen_platform_ioport_readb(void *opaque,
hwaddr addr,
static void xen_platform_ioport_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
switch (addr) {
case 0: /* Platform flags */
@@ -349,7 +353,7 @@ static void platform_mmio_setup(PCIXenPlatformState *d)
static int xen_platform_post_load(void *opaque, int version_id)
{
-PCIXenPlatformState *s = opaque;
+PCIXenPlatformState *s = XEN_PLATFORM(opaque);
platform_fixed_ioport_writeb(s, 0, s-flags);
@@ -371,7 +375,7 @@ static const VMStateDescription vmstate_xen_platform = {
static int xen_platform_initfn(PCIDevice *dev)
{
-PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
+PCIXenPlatformState *d = XEN_PLATFORM(dev);
uint8_t *pci_conf;
pci_conf = d-pci_dev.config;
@@ -397,7 +401,7 @@ static int xen_platform_initfn(PCIDevice *dev)
static void platform_reset(DeviceState *dev)
{
-PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev,
dev);
+PCIXenPlatformState *s = XEN_PLATFORM(dev);
platform_fixed_ioport_reset(s);
}
@@ -420,7 +424,7 @@ static void xen_platform_class_init(ObjectClass *klass,
void *data)
}
static const TypeInfo xen_platform_info = {
-.name = xen-platform,
+.name = TYPE_XEN_PLATFORM,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIXenPlatformState),
.class_init= xen_platform_class_init,
--
Re: [Qemu-devel] [PATCH v2 00/30] PCI: Cleanup legacy casts in device land -- ANN: qom-next revived
Hi Peter, Am 24.06.2013 08:49, schrieb peter.crosthwa...@xilinx.com: From: Peter Crosthwaite peter.crosthwa...@xilinx.com There are a number of different cast implementations from various stages of QEMU development out in device model land. This series cleans up the ones involving TYPE_PCI_DEVICE to consistently use proper QOM casts for both up and down casts. Some were easy, some needed QOM cast macros which are added as appropriate. Following the recent discussion RE performance consequences of QOM casts, im interested in any reports of possible performance regressions here, although I am hoping that Anthony current efforts to improve QOM casting efficiency make this a non-issue. While I did not run extensive benchmarks, state of the discussion between Paolo, Anthony and me, I believe, was that it can be considered okay to use QOM casts everywhere consistently now, but we should not use casts where they are unnecessary (i.e., only where we change type). E.g., http://patchwork.ozlabs.org/patch/255367/ I have therefore dropped some opaque casts where the type on both sides of void* matched (for an up-/downcast I do prefer the cast for safety). Anyway, if we get this merged early, then there is still time for more benchmarking/optimizations during Soft Freeze IMO. Maybe our staging tree will facilitate testing, too. ;) Changed since V1: Removed hunks which macroified VMSD names Dropped virtio/virtio.pci patch Rebased Peter Crosthwaite (30): net/e1000: QOM Upcast Sweep net/rtl8139: QOM Upcast Sweep net/pcnet-pci: QOM Upcast Sweep usb/hcd-xhci: QOM Upcast Sweep scsi/lsi53c895a: QOM Upcast Sweep scsi/megasas: QOM Upcast Sweep scsi/esp-pci: QOM Upcast Sweep ide/ich: QOM Upcast Sweep ide/piix: QOM casting sweep acpi/piix4: QOM Upcast Sweep misc/pci-testdev: QOM Upcast Sweep virtio/vmware_vga: QOM casting sweep misc/ivshmem: QOM Upcast Sweep xen/xen_platform: QOM casting sweep As requested, I've started picking up QOM type/cast/realize patches on: git://github.com/afaerber/qemu-cpu.git qom-next https://github.com/afaerber/qemu-cpu/commits/qom-next (Not to be confused with my qom-cpu / qom-cpu-next CPU trees.) If anyone wishes to contribute patches against that tree, please indicate so with --subject-prefix=PATCH qom-next As a matter of personal taste and consistency, I've used the gtk-doc notation DO_UPCAST() wherever I stumbled over it in commit messages. I've queued all patches above except for ide/piix (09/30) and had comments and/or minor changes for some of them. Noticing some incompleteness, I will reiterate over them. Whether I send a pull when we're all happy with it or whether we let submaintainers pick/pull by subsystem at some point doesn't matter to me, as long as we can join efforts to make QOM realize reality soon. :) isa/*: QOM casting sweep pci/*: QOM casting sweep pci-bridge/pci_bridge_dev: Don't use DO_UPCAST pci-bridge/*: substitute -qdev casts with DEVICE() pci/pci_bridge: substitute -qdev casts with DEVICE() misc/vfio: substitute -qdev casts with DEVICE() net/eepro100: substitute -qdev casts with DEVICE() net/ne2000: substitute -qdev casts with DEVICE() usb/*: substitute -qdev casts with DEVICE() watchdog/wdt_i6300esb: substitute -qdev casts with DEVICE() scsi/vmw_pvscsi: substitute -qdev casts with DEVICE() i2c/smbus_ich9: substitute -qdev casts with DEVICE() ide/cmd646: substitute -qdev casts with DEVICE() ide/via: substitute -qdev casts with DEVICE() pci-host/*: substitute -qdev casts with DEVICE() i386/*: substitute -qdev casts with DEVICE() These patches seem more sloppy while not reaching a clear goal such as dropping a macro or renaming PCIDevice::qdev, so I'd prefer to get open issues sorted out before rushing ahead with half-done conversions. Functionally everything I've seen so far looked fine though. But maybe I'm missing something? What exactly was the motivation behind the series? Do you have a follow-up? Regards, Andreas hw/acpi/piix4.c| 31 +-- hw/display/vmware_vga.c| 13 - hw/i2c/smbus_ich9.c| 2 +- hw/i386/kvm/pci-assign.c | 21 - hw/i386/pc.c | 3 ++- hw/i386/pc_piix.c | 4 ++-- hw/i386/pc_q35.c | 4 ++-- hw/ide/ahci.h | 5 + hw/ide/cmd646.c| 8 hw/ide/ich.c | 10 +- hw/ide/piix.c | 8 hw/ide/via.c | 4 ++-- hw/isa/i82378.c| 8 hw/isa/lpc_ich9.c | 6 +++--- hw/misc/ivshmem.c | 18 +++--- hw/misc/pci-testdev.c | 11 --- hw/misc/vfio.c | 4 ++-- hw/net/e1000.c | 18
[Qemu-devel] [PATCH qom-next] net/e1000: QOM parent field cleanup
Rename to parent_obj and fix any remaining fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/net/e1000.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 27c4221..f3838ed 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -85,7 +85,10 @@ enum {
};
typedef struct E1000State_st {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
NICState *nic;
NICConf conf;
MemoryRegion mmio;
@@ -245,6 +248,8 @@ static const uint32_t mac_reg_init[] = {
static void
set_interrupt_cause(E1000State *s, int index, uint32_t val)
{
+PCIDevice *d = PCI_DEVICE(s);
+
if (val (E1000_DEVID = E1000_DEV_ID_82547EI_MOBILE)) {
/* Only for 8257x */
val |= E1000_ICR_INT_ASSERTED;
@@ -261,7 +266,7 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
*/
s-mac_reg[ICS] = val;
-qemu_set_irq(s-dev.irq[0], (s-mac_reg[IMS] s-mac_reg[ICR]) != 0);
+qemu_set_irq(d-irq[0], (s-mac_reg[IMS] s-mac_reg[ICR]) != 0);
}
static void
@@ -558,6 +563,7 @@ xmit_seg(E1000State *s)
static void
process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
{
+PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_lower = le32_to_cpu(dp-lower.data);
uint32_t dtype = txd_lower (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
unsigned int split_size = txd_lower 0x, bytes, sz, op;
@@ -616,7 +622,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
bytes = msh - tp-size;
bytes = MIN(sizeof(tp-data) - tp-size, bytes);
-pci_dma_read(s-dev, addr, tp-data + tp-size, bytes);
+pci_dma_read(d, addr, tp-data + tp-size, bytes);
if ((sz = tp-size + bytes) = hdr tp-size hdr)
memmove(tp-header, tp-data, hdr);
tp-size = sz;
@@ -632,7 +638,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
DBGOUT(TXERR, TCP segmentation error\n);
} else {
split_size = MIN(sizeof(tp-data) - tp-size, split_size);
-pci_dma_read(s-dev, addr, tp-data + tp-size, split_size);
+pci_dma_read(d, addr, tp-data + tp-size, split_size);
tp-size += split_size;
}
@@ -650,6 +656,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
static uint32_t
txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
{
+PCIDevice *d = PCI_DEVICE(s);
uint32_t txd_upper, txd_lower = le32_to_cpu(dp-lower.data);
if (!(txd_lower (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
@@ -657,7 +664,7 @@ txdesc_writeback(E1000State *s, dma_addr_t base, struct
e1000_tx_desc *dp)
txd_upper = (le32_to_cpu(dp-upper.data) | E1000_TXD_STAT_DD)
~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
dp-upper.data = cpu_to_le32(txd_upper);
-pci_dma_write(s-dev, base + ((char *)dp-upper - (char *)dp),
+pci_dma_write(d, base + ((char *)dp-upper - (char *)dp),
dp-upper, sizeof(dp-upper));
return E1000_ICR_TXDW;
}
@@ -673,6 +680,7 @@ static uint64_t tx_desc_base(E1000State *s)
static void
start_xmit(E1000State *s)
{
+PCIDevice *d = PCI_DEVICE(s);
dma_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s-mac_reg[TDH], cause = E1000_ICS_TXQE;
@@ -685,7 +693,7 @@ start_xmit(E1000State *s)
while (s-mac_reg[TDH] != s-mac_reg[TDT]) {
base = tx_desc_base(s) +
sizeof(struct e1000_tx_desc) * s-mac_reg[TDH];
-pci_dma_read(s-dev, base, desc, sizeof(desc));
+pci_dma_read(d, base, desc, sizeof(desc));
DBGOUT(TX, index %d: %p : %x %x\n, s-mac_reg[TDH],
(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
@@ -818,6 +826,7 @@ static ssize_t
e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
E1000State *s = qemu_get_nic_opaque(nc);
+PCIDevice *d = PCI_DEVICE(s);
struct e1000_rx_desc desc;
dma_addr_t base;
unsigned int n, rdt;
@@ -877,7 +886,7 @@ e1000_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
desc_size = s-rxbuf_size;
}
base = rx_desc_base(s) + sizeof(desc) * s-mac_reg[RDH];
-pci_dma_read(s-dev, base, desc, sizeof(desc));
+pci_dma_read(d, base, desc, sizeof(desc));
desc.special = vlan_special;
desc.status |= (vlan_status | E1000_RXD_STAT_DD);
if (desc.buffer_addr) {
@@ -886,7 +895,7 @@ e1000_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
if (copy_size s-rxbuf_size) {
copy_size = s-rxbuf_size;
}
-pci_dma_write(s-dev, le64_to_cpu(desc.buffer_addr),
+pci_dma_write(d, le64_to_cpu(desc.buffer_addr),
buf + desc_offset + vlan_offset, copy_size);
}
desc_offset += desc_size;
@@
[Qemu-devel] [PATCH qom-next] net/rtl8139: QOM parent field cleanup
Rename to parent_obj and fix any remaining fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/net/rtl8139.c | 88 +++-
1 file changed, 49 insertions(+), 39 deletions(-)
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index 955d35e..0c81c83 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139.c
@@ -433,7 +433,10 @@ typedef struct RTL8139TallyCounters
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
typedef struct RTL8139State {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
uint8_t phys[8]; /* mac address */
uint8_t mult[8]; /* multicast mask array */
@@ -706,13 +709,14 @@ static void prom9346_set_wire(RTL8139State *s, int eecs,
int eesk, int eedi)
static void rtl8139_update_irq(RTL8139State *s)
{
+PCIDevice *d = PCI_DEVICE(s);
int isr;
isr = (s-IntrStatus s-IntrMask) 0x;
DPRINTF(Set IRQ to %d (%04x %04x)\n, isr ? 1 : 0, s-IntrStatus,
s-IntrMask);
-qemu_set_irq(s-dev.irq[0], (isr != 0));
+qemu_set_irq(d-irq[0], (isr != 0));
}
static int rtl8139_RxWrap(RTL8139State *s)
@@ -743,6 +747,8 @@ static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
{
+PCIDevice *d = PCI_DEVICE(s);
+
if (s-RxBufAddr + size s-RxBufferSize)
{
int wrapped = MOD2(s-RxBufAddr + size, s-RxBufferSize);
@@ -754,14 +760,14 @@ static void rtl8139_write_buffer(RTL8139State *s, const
void *buf, int size)
if (size wrapped)
{
-pci_dma_write(s-dev, s-RxBuf + s-RxBufAddr,
+pci_dma_write(d, s-RxBuf + s-RxBufAddr,
buf, size-wrapped);
}
/* reset buffer pointer */
s-RxBufAddr = 0;
-pci_dma_write(s-dev, s-RxBuf + s-RxBufAddr,
+pci_dma_write(d, s-RxBuf + s-RxBufAddr,
buf + (size-wrapped), wrapped);
s-RxBufAddr = wrapped;
@@ -771,7 +777,7 @@ static void rtl8139_write_buffer(RTL8139State *s, const
void *buf, int size)
}
/* non-wrapping path or overwrapping enabled */
-pci_dma_write(s-dev, s-RxBuf + s-RxBufAddr, buf, size);
+pci_dma_write(d, s-RxBuf + s-RxBufAddr, buf, size);
s-RxBufAddr += size;
}
@@ -814,6 +820,7 @@ static int rtl8139_can_receive(NetClientState *nc)
static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf,
size_t size_, int do_interrupt)
{
RTL8139State *s = qemu_get_nic_opaque(nc);
+PCIDevice *d = PCI_DEVICE(s);
/* size is the length of the buffer passed to the driver */
int size = size_;
const uint8_t *dot1q_buf = NULL;
@@ -978,13 +985,13 @@ static ssize_t rtl8139_do_receive(NetClientState *nc,
const uint8_t *buf, size_t
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
-pci_dma_read(s-dev, cplus_rx_ring_desc, val, 4);
+pci_dma_read(d, cplus_rx_ring_desc, val, 4);
rxdw0 = le32_to_cpu(val);
-pci_dma_read(s-dev, cplus_rx_ring_desc+4, val, 4);
+pci_dma_read(d, cplus_rx_ring_desc+4, val, 4);
rxdw1 = le32_to_cpu(val);
-pci_dma_read(s-dev, cplus_rx_ring_desc+8, val, 4);
+pci_dma_read(d, cplus_rx_ring_desc+8, val, 4);
rxbufLO = le32_to_cpu(val);
-pci_dma_read(s-dev, cplus_rx_ring_desc+12, val, 4);
+pci_dma_read(d, cplus_rx_ring_desc+12, val, 4);
rxbufHI = le32_to_cpu(val);
DPRINTF(+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n,
@@ -1052,12 +1059,12 @@ static ssize_t rtl8139_do_receive(NetClientState *nc,
const uint8_t *buf, size_t
/* receive/copy to target memory */
if (dot1q_buf) {
-pci_dma_write(s-dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
-pci_dma_write(s-dev, rx_addr + 2 * ETHER_ADDR_LEN,
+pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
+pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
size - 2 * ETHER_ADDR_LEN);
} else {
-pci_dma_write(s-dev, rx_addr, buf, size);
+pci_dma_write(d, rx_addr, buf, size);
}
if (s-CpCmd CPlusRxChkSum)
@@ -1067,7 +1074,7 @@ static ssize_t rtl8139_do_receive(NetClientState *nc,
const uint8_t *buf, size_t
/* write checksum */
val = cpu_to_le32(crc32(0, buf, size_));
-pci_dma_write(s-dev, rx_addr+size, (uint8_t *)val, 4);
+pci_dma_write(d, rx_addr+size, (uint8_t *)val, 4);
/* first segment of received packet flag */
#define CP_RX_STATUS_FS (129)
@@ -1113,9 +1120,9 @@ static ssize_t rtl8139_do_receive(NetClientState *nc,
const uint8_t *buf, size_t
/* update ring data */
val = cpu_to_le32(rxdw0);
-pci_dma_write(s-dev, cplus_rx_ring_desc, (uint8_t
Re: [Qemu-devel] [PATCH 04/15] PPC: dbdma: Replace tabs with spaces
Am 30.06.2013 um 08:35 schrieb Andreas Färber afaer...@suse.de:
Am 30.06.2013 03:26, schrieb Alexander Graf:
s/^I//g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 102
+++---
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 2fc7f87..ab174f5 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -85,75 +85,75 @@
/* Bits in control and status registers */
-#define RUN0x8000
-#define PAUSE0x4000
-#define FLUSH0x2000
-#define WAKE0x1000
-#define DEAD0x0800
-#define ACTIVE0x0400
-#define BT0x0100
-#define DEVSTAT0x00ff
+#define RUN0x8000
+#define PAUSE 0x4000
+#define FLUSH 0x2000
+#define WAKE 0x1000
+#define DEAD 0x0800
+#define ACTIVE 0x0400
+#define BT 0x0100
+#define DEVSTAT0x00ff
/*
* DBDMA command structure. These fields are all little-endian!
*/
typedef struct dbdma_cmd {
-uint16_t req_count; /* requested byte transfer count */
-uint16_t command; /* command word (has bit-fields) */
-uint32_t phy_addr; /* physical data address */
-uint32_t cmd_dep; /* command-dependent field */
-uint16_t res_count; /* residual count after completion */
-uint16_t xfer_status; /* transfer status */
+uint16_t req_count; /* requested byte transfer count */
+uint16_t command;/* command word (has bit-fields) */
+uint32_t phy_addr; /* physical data address */
+uint32_t cmd_dep;/* command-dependent field */
+uint16_t res_count; /* residual count after completion */
+uint16_t xfer_status;/* transfer status */
} dbdma_cmd;
/* DBDMA command values in command field */
#define COMMAND_MASK0xf000
-#define OUTPUT_MORE0x/* transfer memory data to stream */
-#define OUTPUT_LAST0x1000/* ditto followed by end marker */
-#define INPUT_MORE0x2000/* transfer stream data to memory */
-#define INPUT_LAST0x3000/* ditto, expect end marker */
-#define STORE_WORD0x4000/* write word (4 bytes) to device reg */
-#define LOAD_WORD0x5000/* read word (4 bytes) from device reg */
-#define DBDMA_NOP0x6000/* do nothing */
-#define DBDMA_STOP0x7000/* suspend processing */
+#define OUTPUT_MORE 0x/* transfer memory data to stream */
+#define OUTPUT_LAST 0x1000/* ditto followed by end marker */
+#define INPUT_MORE 0x2000/* transfer stream data to memory */
+#define INPUT_LAST 0x3000/* ditto, expect end marker */
+#define STORE_WORD 0x4000/* write word (4 bytes) to device reg
*/
+#define LOAD_WORD 0x5000/* read word (4 bytes) from device
reg */
+#define DBDMA_NOP 0x6000/* do nothing */
+#define DBDMA_STOP 0x7000/* suspend processing */
/* Key values in command field */
#define KEY_MASK0x0700
-#define KEY_STREAM00x/* usual data stream */
-#define KEY_STREAM10x0100/* control/status stream */
-#define KEY_STREAM20x0200/* device-dependent stream */
-#define KEY_STREAM30x0300/* device-dependent stream */
-#define KEY_STREAM40x0400/* reserved */
-#define KEY_REGS0x0500/* device register space */
-#define KEY_SYSTEM0x0600/* system memory-mapped space */
-#define KEY_DEVICE0x0700/* device memory-mapped space */
+#define KEY_STREAM0 0x/* usual data stream */
+#define KEY_STREAM1 0x0100/* control/status stream */
+#define KEY_STREAM2 0x0200/* device-dependent stream */
+#define KEY_STREAM3 0x0300/* device-dependent stream */
+#define KEY_STREAM4 0x0400/* reserved */
+#define KEY_REGS0x0500/* device register space */
+#define KEY_SYSTEM 0x0600/* system memory-mapped space */
+#define KEY_DEVICE 0x0700/* device memory-mapped space */
/* Interrupt control values in command field */
#define INTR_MASK 0x0030
-#define INTR_NEVER0x/* don't interrupt */
-#define INTR_IFSET0x0010/* intr if condition bit is 1 */
-#define INTR_IFCLR0x0020/* intr if condition bit is 0 */
-#define INTR_ALWAYS0x0030/* always interrupt */
+#define INTR_NEVER 0x/* don't interrupt */
+#define INTR_IFSET 0x0010/* intr if condition bit is 1 */
+#define INTR_IFCLR 0x0020/* intr if condition bit is 0 */
+#define INTR_ALWAYS 0x0030/* always interrupt */
/* Branch control values in command field */
#define BR_MASK 0x000c
-#define BR_NEVER0x/* don't branch */
-#define BR_IFSET
Re: [Qemu-devel] [PATCH v2 03/30] net/pcnet-pci: QOM Upcast Sweep
Am 30.06.2013 09:34, schrieb Andreas Färber:
Am 24.06.2013 08:52, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/net/pcnet-pci.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index 9df2b87..b1afbf4 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -43,6 +43,10 @@
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH
+#define TYPE_PCI_PC_NET pcnet
I'm wondering whether we should rename this PCNET rather than PC_NET,
but I'm queuing it as is. Thanks,
Squashing the following.
Andreas
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index b1afbf4..6ae27b4 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -49,7 +49,10 @@
OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PC_NET)
typedef struct {
-PCIDevice pci_dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
PCNetState state;
MemoryRegion io_bar;
} PCIPCNetState;
@@ -240,7 +243,7 @@ static const VMStateDescription vmstate_pci_pcnet = {
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField []) {
-VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
+VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
VMSTATE_END_OF_LIST()
}
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH qom-next] usb/hcd-xhci: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/usb/hcd-xhci.c | 83 ---
1 file changed, 48 insertions(+), 35 deletions(-)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index bdbca67..765ee0e 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -443,7 +443,10 @@ typedef struct XHCIInterrupter {
} XHCIInterrupter;
struct XHCIState {
-PCIDevice pci_dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
USBBus bus;
qemu_irq irq;
MemoryRegion mem;
@@ -659,7 +662,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci,
dma_addr_t addr,
assert((len % sizeof(uint32_t)) == 0);
-pci_dma_read(xhci-pci_dev, addr, buf, len);
+pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
for (i = 0; i (len / sizeof(uint32_t)); i++) {
buf[i] = le32_to_cpu(buf[i]);
@@ -677,7 +680,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci,
dma_addr_t addr,
for (i = 0; i (len / sizeof(uint32_t)); i++) {
tmp[i] = cpu_to_le32(buf[i]);
}
-pci_dma_write(xhci-pci_dev, addr, tmp, len);
+pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
}
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
@@ -704,10 +707,11 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct
USBPort *uport)
static void xhci_intx_update(XHCIState *xhci)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
int level = 0;
-if (msix_enabled(xhci-pci_dev) ||
-msi_enabled(xhci-pci_dev)) {
+if (msix_enabled(pci_dev) ||
+msi_enabled(pci_dev)) {
return;
}
@@ -723,9 +727,10 @@ static void xhci_intx_update(XHCIState *xhci)
static void xhci_msix_update(XHCIState *xhci, int v)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
bool enabled;
-if (!msix_enabled(xhci-pci_dev)) {
+if (!msix_enabled(pci_dev)) {
return;
}
@@ -736,17 +741,19 @@ static void xhci_msix_update(XHCIState *xhci, int v)
if (enabled) {
trace_usb_xhci_irq_msix_use(v);
-msix_vector_use(xhci-pci_dev, v);
+msix_vector_use(pci_dev, v);
xhci-intr[v].msix_used = true;
} else {
trace_usb_xhci_irq_msix_unuse(v);
-msix_vector_unuse(xhci-pci_dev, v);
+msix_vector_unuse(pci_dev, v);
xhci-intr[v].msix_used = false;
}
}
static void xhci_intr_raise(XHCIState *xhci, int v)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
+
xhci-intr[v].erdp_low |= ERDP_EHB;
xhci-intr[v].iman |= IMAN_IP;
xhci-usbsts |= USBSTS_EINT;
@@ -759,15 +766,15 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
return;
}
-if (msix_enabled(xhci-pci_dev)) {
+if (msix_enabled(pci_dev)) {
trace_usb_xhci_irq_msix(v);
-msix_notify(xhci-pci_dev, v);
+msix_notify(pci_dev, v);
return;
}
-if (msi_enabled(xhci-pci_dev)) {
+if (msi_enabled(pci_dev)) {
trace_usb_xhci_irq_msi(v);
-msi_notify(xhci-pci_dev, v);
+msi_notify(pci_dev, v);
return;
}
@@ -790,6 +797,7 @@ static void xhci_die(XHCIState *xhci)
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCIInterrupter *intr = xhci-intr[v];
XHCITRB ev_trb;
dma_addr_t addr;
@@ -808,7 +816,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent
*event, int v)
ev_trb.status, ev_trb.control);
addr = intr-er_start + TRB_SIZE*intr-er_ep_idx;
-pci_dma_write(xhci-pci_dev, addr, ev_trb, TRB_SIZE);
+pci_dma_write(pci_dev, addr, ev_trb, TRB_SIZE);
intr-er_ep_idx++;
if (intr-er_ep_idx = intr-er_size) {
@@ -955,9 +963,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
dma_addr_t *addr)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
+
while (1) {
TRBType type;
-pci_dma_read(xhci-pci_dev, ring-dequeue, trb, TRB_SIZE);
+pci_dma_read(pci_dev, ring-dequeue, trb, TRB_SIZE);
trb-addr = ring-dequeue;
trb-ccs = ring-ccs;
le64_to_cpus(trb-parameter);
@@ -990,6 +1000,7 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing
*ring, XHCITRB *trb,
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
{
+PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCITRB trb;
int length = 0;
dma_addr_t dequeue = ring-dequeue;
@@ -999,7 +1010,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const
XHCIRing *ring)
while (1) {
TRBType type;
-pci_dma_read(xhci-pci_dev, dequeue, trb, TRB_SIZE);
+pci_dma_read(pci_dev, dequeue, trb, TRB_SIZE);
le64_to_cpus(trb.parameter);
le32_to_cpus(trb.status);
[Qemu-devel] [PATCH qom-next] scsi/lsi53c895a: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/scsi/lsi53c895a.c | 46 +++---
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index d488c5c..d5d26f8 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -184,7 +184,10 @@ typedef struct lsi_request {
} lsi_request;
typedef struct {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
MemoryRegion mmio_io;
MemoryRegion ram_io;
MemoryRegion io_io;
@@ -387,7 +390,7 @@ static inline uint32_t read_dword(LSIState *s, uint32_t
addr)
{
uint32_t buf;
-pci_dma_read(s-dev, addr, buf, 4);
+pci_dma_read(PCI_DEVICE(s), addr, buf, 4);
return cpu_to_le32(buf);
}
@@ -398,6 +401,7 @@ static void lsi_stop_script(LSIState *s)
static void lsi_update_irq(LSIState *s)
{
+PCIDevice *d = PCI_DEVICE(s);
int level;
static int last_level;
lsi_request *p;
@@ -429,7 +433,7 @@ static void lsi_update_irq(LSIState *s)
level, s-dstat, s-sist1, s-sist0);
last_level = level;
}
-qemu_set_irq(s-dev.irq[0], level);
+qemu_set_irq(d-irq[0], level);
if (!level lsi_irq_on_rsl(s) !(s-scntl1 LSI_SCNTL1_CON)) {
DPRINTF(Handled IRQs disconnected, looking for pending
@@ -525,6 +529,7 @@ static void lsi_bad_selection(LSIState *s, uint32_t id)
/* Initiate a SCSI layer data transfer. */
static void lsi_do_dma(LSIState *s, int out)
{
+PCIDevice *pci_dev;
uint32_t count;
dma_addr_t addr;
SCSIDevice *dev;
@@ -536,6 +541,7 @@ static void lsi_do_dma(LSIState *s, int out)
return;
}
+pci_dev = PCI_DEVICE(s);
dev = s-current-req-dev;
assert(dev);
@@ -561,9 +567,9 @@ static void lsi_do_dma(LSIState *s, int out)
}
/* ??? Set SFBR to first data byte. */
if (out) {
-pci_dma_read(s-dev, addr, s-current-dma_buf, count);
+pci_dma_read(pci_dev, addr, s-current-dma_buf, count);
} else {
-pci_dma_write(s-dev, addr, s-current-dma_buf, count);
+pci_dma_write(pci_dev, addr, s-current-dma_buf, count);
}
s-current-dma_len -= count;
if (s-current-dma_len == 0) {
@@ -758,7 +764,7 @@ static void lsi_do_command(LSIState *s)
DPRINTF(Send command len=%d\n, s-dbc);
if (s-dbc 16)
s-dbc = 16;
-pci_dma_read(s-dev, s-dnad, buf, s-dbc);
+pci_dma_read(PCI_DEVICE(s), s-dnad, buf, s-dbc);
s-sfbr = buf[0];
s-command_complete = 0;
@@ -809,7 +815,7 @@ static void lsi_do_status(LSIState *s)
s-dbc = 1;
status = s-status;
s-sfbr = status;
-pci_dma_write(s-dev, s-dnad, status, 1);
+pci_dma_write(PCI_DEVICE(s), s-dnad, status, 1);
lsi_set_phase(s, PHASE_MI);
s-msg_action = 1;
lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
@@ -823,7 +829,7 @@ static void lsi_do_msgin(LSIState *s)
len = s-msg_len;
if (len s-dbc)
len = s-dbc;
-pci_dma_write(s-dev, s-dnad, s-msg, len);
+pci_dma_write(PCI_DEVICE(s), s-dnad, s-msg, len);
/* Linux drivers rely on the last byte being in the SIDL. */
s-sidl = s-msg[len - 1];
s-msg_len -= len;
@@ -855,7 +861,7 @@ static void lsi_do_msgin(LSIState *s)
static uint8_t lsi_get_msgbyte(LSIState *s)
{
uint8_t data;
-pci_dma_read(s-dev, s-dnad, data, 1);
+pci_dma_read(PCI_DEVICE(s), s-dnad, data, 1);
s-dnad++;
s-dbc--;
return data;
@@ -1001,14 +1007,15 @@ static inline int32_t sxt24(int32_t n)
#define LSI_BUF_SIZE 4096
static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
{
+PCIDevice *d = PCI_DEVICE(s);
int n;
uint8_t buf[LSI_BUF_SIZE];
DPRINTF(memcpy dest 0x%08x src 0x%08x count %d\n, dest, src, count);
while (count) {
n = (count LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
-pci_dma_read(s-dev, src, buf, n);
-pci_dma_write(s-dev, dest, buf, n);
+pci_dma_read(d, src, buf, n);
+pci_dma_write(d, dest, buf, n);
src += n;
dest += n;
count -= n;
@@ -1034,6 +1041,7 @@ static void lsi_wait_reselect(LSIState *s)
static void lsi_execute_script(LSIState *s)
{
+PCIDevice *pci_dev = PCI_DEVICE(s);
uint32_t insn;
uint32_t addr, addr_high;
int opcode;
@@ -1076,7 +1084,7 @@ again:
/* 32-bit Table indirect */
offset = sxt24(addr);
-pci_dma_read(s-dev, s-dsa + offset, buf, 8);
+pci_dma_read(pci_dev, s-dsa + offset, buf, 8);
/* byte count is stored in bits 0:23 only */
s-dbc = cpu_to_le32(buf[0]) 0xff;
s-rbc = s-dbc;
@@ -1435,7 +1443,7 @@ again:
n = (insn 7);
reg = (insn 16) 0xff;
if (insn (1 24)) {
-pci_dma_read(s-dev, addr, data, n);
+pci_dma_read(pci_dev, addr,
[Qemu-devel] [PATCH qom-next] scsi/megasas: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/scsi/megasas.c | 46 ++
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 49fcae4..d62129e 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -70,7 +70,10 @@ typedef struct MegasasCmd {
} MegasasCmd;
typedef struct MegasasState {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
MemoryRegion mmio_io;
MemoryRegion port_io;
MemoryRegion queue_io;
@@ -237,7 +240,7 @@ static int megasas_map_sgl(MegasasState *s, MegasasCmd
*cmd, union mfi_sgl *sgl)
MEGASAS_MAX_SGE);
return iov_count;
}
-pci_dma_sglist_init(cmd-qsg, s-dev, iov_count);
+pci_dma_sglist_init(cmd-qsg, PCI_DEVICE(s), iov_count);
for (i = 0; i iov_count; i++) {
dma_addr_t iov_pa, iov_size_p;
@@ -498,6 +501,7 @@ static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
static void megasas_complete_frame(MegasasState *s, uint64_t context)
{
+PCIDevice *pci_dev = PCI_DEVICE(s);
int tail, queue_offset;
/* Decrement busy count */
@@ -526,12 +530,12 @@ static void megasas_complete_frame(MegasasState *s,
uint64_t context)
/* Notify HBA */
s-doorbell++;
if (s-doorbell == 1) {
-if (msix_enabled(s-dev)) {
+if (msix_enabled(pci_dev)) {
trace_megasas_msix_raise(0);
-msix_notify(s-dev, 0);
+msix_notify(pci_dev, 0);
} else {
trace_megasas_irq_raise();
-qemu_irq_raise(s-dev.irq[0]);
+qemu_irq_raise(pci_dev-irq[0]);
}
}
} else {
@@ -633,7 +637,7 @@ static int megasas_map_dcmd(MegasasState *s, MegasasCmd
*cmd)
}
iov_pa = megasas_sgl_get_addr(cmd, cmd-frame-dcmd.sgl);
iov_size = megasas_sgl_get_len(cmd, cmd-frame-dcmd.sgl);
-pci_dma_sglist_init(cmd-qsg, s-dev, 1);
+pci_dma_sglist_init(cmd-qsg, PCI_DEVICE(s), 1);
qemu_sglist_add(cmd-qsg, iov_pa, iov_size);
cmd-iov_size = iov_size;
return cmd-iov_size;
@@ -660,6 +664,7 @@ static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t
iov_size)
static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
{
+PCIDevice *pci_dev = PCI_DEVICE(s);
struct mfi_ctrl_info info;
size_t dcmd_size = sizeof(info);
BusChild *kid;
@@ -710,11 +715,11 @@ static int megasas_ctrl_get_info(MegasasState *s,
MegasasCmd *cmd)
memcpy(info.image_component[0].build_date, __DATE__, 11);
memcpy(info.image_component[0].build_time, __TIME__, 8);
info.image_component_count = 1;
-if (s-dev.has_rom) {
+if (pci_dev-has_rom) {
uint8_t biosver[32];
uint8_t *ptr;
-ptr = memory_region_get_ram_ptr(s-dev.rom);
+ptr = memory_region_get_ram_ptr(pci_dev-rom);
memcpy(biosver, ptr + 0x41, 31);
memcpy(info.image_component[1].name, BIOS, 4);
memcpy(info.image_component[1].version, biosver,
@@ -1905,6 +1910,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MegasasState *s = opaque;
+PCIDevice *pci_dev = PCI_DEVICE(s);
uint64_t frame_addr;
uint32_t frame_count;
int i;
@@ -1928,9 +1934,9 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
break;
case MFI_OMSK:
s-intr_mask = val;
-if (!megasas_intr_enabled(s) !msix_enabled(s-dev)) {
+if (!megasas_intr_enabled(s) !msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
-qemu_irq_lower(s-dev.irq[0]);
+qemu_irq_lower(pci_dev-irq[0]);
}
if (megasas_intr_enabled(s)) {
trace_megasas_intr_enabled();
@@ -1944,9 +1950,9 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
/* Update reply queue pointer */
trace_megasas_qf_update(s-reply_queue_head, s-busy);
stl_le_phys(s-producer_pa, s-reply_queue_head);
-if (!msix_enabled(s-dev)) {
+if (!msix_enabled(pci_dev)) {
trace_megasas_irq_lower();
-qemu_irq_lower(s-dev.irq[0]);
+qemu_irq_lower(pci_dev-irq[0]);
}
}
break;
@@ -2055,7 +2061,7 @@ static const VMStateDescription vmstate_megasas = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(dev, MegasasState),
+VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
VMSTATE_INT32(fw_state, MegasasState),
VMSTATE_INT32(intr_mask, MegasasState),
@@ -2072,7 +2078,7 @@ static void megasas_scsi_uninit(PCIDevice *d)
MegasasState *s = MEGASAS(d);
#ifdef USE_MSIX
-msix_uninit(s-dev,
[Qemu-devel] [PATCH qom-next] scsi/esp-pci: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/scsi/esp-pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
index 2a72da6..8ad4dfa 100644
--- a/hw/scsi/esp-pci.c
+++ b/hw/scsi/esp-pci.c
@@ -60,7 +60,10 @@
#define SBAC_STATUS 0x1000
typedef struct PCIESPState {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
MemoryRegion io;
uint32_t dma_regs[8];
uint32_t sbac;
@@ -260,7 +263,7 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t
*buf, int len,
len = pci-dma_regs[DMA_WBC];
}
-pci_dma_rw(pci-dev, addr, buf, len, dir);
+pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
/* update status registers */
pci-dma_regs[DMA_WBC] -= len;
@@ -309,7 +312,7 @@ static const VMStateDescription vmstate_esp_pci_scsi = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(dev, PCIESPState),
+VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
VMSTATE_END_OF_LIST()
@@ -344,7 +347,7 @@ static int esp_pci_scsi_init(PCIDevice *dev)
ESPState *s = pci-esp;
uint8_t *pci_conf;
-pci_conf = pci-dev.config;
+pci_conf = dev-config;
/* Interrupt pin A */
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
@@ -355,8 +358,8 @@ static int esp_pci_scsi_init(PCIDevice *dev)
s-chip_id = TCHI_AM53C974;
memory_region_init_io(pci-io, esp_pci_io_ops, pci, esp-io, 0x80);
-pci_register_bar(pci-dev, 0, PCI_BASE_ADDRESS_SPACE_IO, pci-io);
-s-irq = pci-dev.irq[0];
+pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, pci-io);
+s-irq = dev-irq[0];
scsi_bus_new(s-bus, d, esp_pci_scsi_info, NULL);
if (!d-hotplugged) {
--
1.8.1.4
[Qemu-devel] [PATCH qom-next] ide/ich: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/ide/ahci.c | 11 ++-
hw/ide/ahci.h | 5 -
hw/ide/ich.c | 22 +++---
3 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 1adfa0b..3c86b3a 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -117,12 +117,13 @@ static uint32_t ahci_port_read(AHCIState *s, int port,
int offset)
static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
{
-struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
+AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
+PCIDevice *pci_dev = PCI_DEVICE(d);
DPRINTF(0, raise irq\n);
-if (msi_enabled(d-card)) {
-msi_notify(d-card, 0);
+if (msi_enabled(pci_dev)) {
+msi_notify(pci_dev, 0);
} else {
qemu_irq_raise(s-irq);
}
@@ -130,11 +131,11 @@ static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
{
-struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
+AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
DPRINTF(0, lower irq\n);
-if (!msi_enabled(d-card)) {
+if (!msi_enabled(PCI_DEVICE(d))) {
qemu_irq_lower(s-irq);
}
}
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index f997c67..20e412c 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -301,7 +301,10 @@ typedef struct AHCIState {
} AHCIState;
typedef struct AHCIPCIState {
-PCIDevice card;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
AHCIState ahci;
} AHCIPCIState;
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index a6f78dc..4eb5488 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -84,7 +84,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
.unmigratable = 1, /* Still buggy under I/O load */
.version_id = 1,
.fields = (VMStateField []) {
-VMSTATE_PCI_DEVICE(card, AHCIPCIState),
+VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
VMSTATE_AHCI(ahci, AHCIPCIState),
VMSTATE_END_OF_LIST()
},
@@ -106,30 +106,30 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
ahci_init(d-ahci, DEVICE(dev), pci_get_address_space(dev), 6);
-pci_config_set_prog_interface(d-card.config, AHCI_PROGMODE_MAJOR_REV_1);
+pci_config_set_prog_interface(dev-config, AHCI_PROGMODE_MAJOR_REV_1);
-d-card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
-d-card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
-pci_config_set_interrupt_pin(d-card.config, 1);
+dev-config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
+dev-config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
+pci_config_set_interrupt_pin(dev-config, 1);
/* XXX Software should program this register */
-d-card.config[0x90] = 1 6; /* Address Map Register - AHCI mode */
+dev-config[0x90] = 1 6; /* Address Map Register - AHCI mode */
msi_init(dev, 0x50, 1, true, false);
-d-ahci.irq = d-card.irq[0];
+d-ahci.irq = dev-irq[0];
-pci_register_bar(d-card, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
+pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
d-ahci.idp);
-pci_register_bar(d-card, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
+pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
d-ahci.mem);
-sata_cap_offset = pci_add_capability(d-card, PCI_CAP_ID_SATA,
+sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
if (sata_cap_offset 0) {
return sata_cap_offset;
}
-sata_cap = d-card.config + sata_cap_offset;
+sata_cap = dev-config + sata_cap_offset;
pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
pci_set_long(sata_cap + SATA_CAP_BAR,
(ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 4));
--
1.8.1.4
Re: [Qemu-devel] CAN device
Hi, Thanks, Andreas. It really help me a lot. When I man qemu, I found path specifies the name of the serial device to open. Does that mean I should have a real serial device or I cannot test it? Can I test it just in a virtual environment? When I try to open a /dev/ttyS0 through cat /dev/ttyS0, error Input/output error. I google it, and found many reasons can cause that error. How should I test it? Thanks, Jin Yang. 2013/6/28 Andreas Färber afaer...@suse.de Hi, Am 28.06.2013 14:19, schrieb Yang Jin: I try to develop a CAN device on QEMU. And I found pci-serial is similar to CAN. Untill now, I have some questions about how to use pci-serial on QEMU. Actually, QEMU use isa-serial as a default serial device. So I try to use isa-serial firstly. Some useful information we can get from docs/qdev-device-use.txt. I know that we should use -chardev argument to create a host part, and then use -device isa-serial,iobase=IOADDR,irq=IRQ,index=IDX to start a isa-serial. I get those arguments from the source file, the following can work. -device isa-serial,chardev=isa0,iobase=0x3f8,irq=4,index=0 However, when I try to create a host through -chardev serial,id=isa0,path=./, error chardev: opening backend serial failed occurs. When change it to -chardev serial,id=isa0,path=/dev/ttyS0, it works. Now, I donot know what path means? Does it have some relation to the host device? Or it's just a symbol means nothing. Searching man qemu for chardev serial should answer that question. :) There you will also find alternative chardev backends you can use. And some questions about pci bus. On docs/qdev-device-use.txt, we get Example: device i440FX-pcihost is on the root bus, and provides a PCI bus named pci.0. To put a FOO device into its slot 4, use -device FOO,bus=/i440FX-pcihost/pci.0,addr=4. The abbreviated form bus=pci.0 also works as long as the bus name is unique. So, how can we get the name of the root device which we use now? You can browse the QOM hierarchy using the ./QMP/qom-list script and an appropriate -qmp option (e.g. unix:./qmp-sock,server,nowait). But leaving out the bus= option should work fine just as well. Regards, Andreas I searched that for some days, but doesnot get some usefull information. Thanks, Jin yang. -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] CAN device
Hi, Am 30.06.2013 14:25, schrieb Yang Jin: Thanks, Andreas. It really help me a lot. When I man qemu, I found path specifies the name of the serial device to open. Does that mean I should have a real serial device or I cannot test it? Can I test it just in a virtual environment? When I try to open a /dev/ttyS0 through cat /dev/ttyS0, error Input/output error. -chardev serial is for a serial device. If you cannot or don't want to use one, just use a different -chardev parameter. The man page I pointed you to documents quite a few: null, file, pipe, stdio and many more. I cannot guess which one is best for what you are trying to do. ;) Regards, Andreas P.S. Please avoid top-posting on the mailing list. -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH qom-next] acpi/piix4: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/acpi/piix4.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index b0f7667..e4f3b03 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -64,7 +64,9 @@ typedef struct CPUStatus {
} CPUStatus;
typedef struct PIIX4PMState {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
MemoryRegion io;
MemoryRegion io_gpe;
@@ -135,11 +137,12 @@ static void pm_tmr_timer(ACPIREGS *ar)
static void apm_ctrl_changed(uint32_t val, void *arg)
{
PIIX4PMState *s = arg;
+PCIDevice *d = PCI_DEVICE(s);
/* ACPI specs 3.0, 4.7.2.5 */
acpi_pm1_cnt_update(s-ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
-if (s-dev.config[0x5b] (1 1)) {
+if (d-config[0x5b] (1 1)) {
if (s-smi_irq) {
qemu_irq_raise(s-smi_irq);
}
@@ -148,24 +151,27 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
static void pm_io_space_update(PIIX4PMState *s)
{
+PCIDevice *d = PCI_DEVICE(s);
uint32_t pm_io_base;
-pm_io_base = le32_to_cpu(*(uint32_t *)(s-dev.config + 0x40));
+pm_io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x40));
pm_io_base = 0xffc0;
memory_region_transaction_begin();
-memory_region_set_enabled(s-io, s-dev.config[0x80] 1);
+memory_region_set_enabled(s-io, d-config[0x80] 1);
memory_region_set_address(s-io, pm_io_base);
memory_region_transaction_commit();
}
static void smbus_io_space_update(PIIX4PMState *s)
{
-s-smb_io_base = le32_to_cpu(*(uint32_t *)(s-dev.config + 0x90));
+PCIDevice *d = PCI_DEVICE(s);
+
+s-smb_io_base = le32_to_cpu(*(uint32_t *)(d-config + 0x90));
s-smb_io_base = 0xffc0;
memory_region_transaction_begin();
-memory_region_set_enabled(s-smb.io, s-dev.config[0xd2] 1);
+memory_region_set_enabled(s-smb.io, d-config[0xd2] 1);
memory_region_set_address(s-smb.io, s-smb_io_base);
memory_region_transaction_commit();
}
@@ -244,7 +250,7 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int
version_id)
int ret, i;
uint16_t temp;
-ret = pci_device_load(s-dev, f);
+ret = pci_device_load(PCI_DEVICE(s), f);
if (ret 0) {
return ret;
}
@@ -288,7 +294,7 @@ static const VMStateDescription vmstate_acpi = {
.load_state_old = acpi_load_old,
.post_load = vmstate_acpi_post_load,
.fields = (VMStateField []) {
-VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
+VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
@@ -359,7 +365,8 @@ static void piix4_update_hotplug(PIIX4PMState *s)
static void piix4_reset(void *opaque)
{
PIIX4PMState *s = opaque;
-uint8_t *pci_conf = s-dev.config;
+PCIDevice *d = PCI_DEVICE(s);
+uint8_t *pci_conf = d-config;
pci_conf[0x58] = 0;
pci_conf[0x59] = 0;
@@ -387,9 +394,10 @@ static void piix4_pm_powerdown_req(Notifier *n, void
*opaque)
static void piix4_pm_machine_ready(Notifier *n, void *opaque)
{
PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
+PCIDevice *d = PCI_DEVICE(s);
uint8_t *pci_conf;
-pci_conf = s-dev.config;
+pci_conf = d-config;
pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
pci_conf[0x63] = 0x60;
pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
@@ -402,7 +410,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
PIIX4PMState *s = PIIX4_PM(dev);
uint8_t *pci_conf;
-pci_conf = s-dev.config;
+pci_conf = dev-config;
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
pci_conf[0x09] = 0x00;
--
1.8.1.4
Re: [Qemu-devel] [PATCH v2 11/30] misc/pci-testdev: QOM Upcast Sweep
Am 24.06.2013 08:58, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/misc/pci-testdev.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
Missed one DO_UPCAST(), fixing up.
Andreas
diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c
index add58b7..153603e 100644
--- a/hw/misc/pci-testdev.c
+++ b/hw/misc/pci-testdev.c
@@ -232,7 +232,7 @@ static const MemoryRegionOps pci_testdev_pio_ops = {
static int pci_testdev_init(PCIDevice *pci_dev)
{
-PCITestDevState *d = DO_UPCAST(PCITestDevState, dev, pci_dev);
+PCITestDevState *d = PCI_TEST_DEV(pci_dev);
uint8_t *pci_conf;
char *name;
int r, i;
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH qom-next] misc/pci-testdev: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/misc/pci-testdev.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c
index 153603e..087ec3b 100644
--- a/hw/misc/pci-testdev.c
+++ b/hw/misc/pci-testdev.c
@@ -76,7 +76,10 @@ enum {
#define IOTEST_ACCESS_WIDTH (sizeof(uint8_t))
typedef struct PCITestDevState {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
MemoryRegion mmio;
MemoryRegion portio;
IOTest *tests;
@@ -237,7 +240,7 @@ static int pci_testdev_init(PCIDevice *pci_dev)
char *name;
int r, i;
-pci_conf = d-dev.config;
+pci_conf = pci_dev-config;
pci_conf[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */
@@ -245,8 +248,8 @@ static int pci_testdev_init(PCIDevice *pci_dev)
pci-testdev-mmio, IOTEST_MEMSIZE * 2);
memory_region_init_io(d-portio, pci_testdev_pio_ops, d,
pci-testdev-portio, IOTEST_IOSIZE * 2);
-pci_register_bar(d-dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, d-mmio);
-pci_register_bar(d-dev, 1, PCI_BASE_ADDRESS_SPACE_IO, d-portio);
+pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, d-mmio);
+pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, d-portio);
d-current = -1;
d-tests = g_malloc0(IOTEST_MAX * sizeof *d-tests);
--
1.8.1.4
Re: [Qemu-devel] [PATCH RFC qom-cpu 00/41] QOM CPUState, part 11: GDB stub
On Sat, Jun 29, 2013 at 10:01:16PM +0200, Andreas Färber wrote: Hello, This series cleans up gdbstub by changing all its internal CPU state to CPUState and by moving most target-specific code into the target directories. It depends on part 10 and starts with a follow-up, consolidating reset logging. Support for m68k, moxie and unicore32 to set the PC via gdbstub is added. Lightweight subclasses for XtensaCPU are introduced, keeping the XtensaConfig mechanisms, to stop xtensa from deviating at gdbstub level wrt register count. I'm wondering whether there would be interest in adding a program-counter dynamic property to the CPU, given that a setter has been factored out here? Available for testing at: git://github.com/afaerber/qemu-cpu.git qom-cpu-11.v1 https://github.com/afaerber/qemu-cpu/commits/qom-cpu-11.v1 For all lm32 parts: Acked-by: Michael Walle mich...@walle.cc
[Qemu-devel] [PATCH qom-next] display/vmware_vga: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/display/vmware_vga.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index fcc8944..8624be9 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -87,7 +87,10 @@ struct vmsvga_state_s {
OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
struct pci_vmsvga_state_s {
-PCIDevice card;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
struct vmsvga_state_s chip;
MemoryRegion io_bar;
};
@@ -792,7 +795,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
case SVGA_REG_FB_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
-ret = pci_get_bar_addr(pci_vmsvga-card, 1);
+ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
break;
}
@@ -828,7 +831,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
case SVGA_REG_MEM_START: {
struct pci_vmsvga_state_s *pci_vmsvga
= container_of(s, struct pci_vmsvga_state_s, chip);
-ret = pci_get_bar_addr(pci_vmsvga-card, 2);
+ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
break;
}
@@ -1176,7 +1179,7 @@ static const VMStateDescription vmstate_vmware_vga = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
+VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
vmstate_vmware_vga_internal, struct vmsvga_state_s),
VMSTATE_END_OF_LIST()
@@ -1252,21 +1255,21 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
{
struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
-s-card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
-s-card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
-s-card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
+dev-config[PCI_CACHE_LINE_SIZE] = 0x08;
+dev-config[PCI_LATENCY_TIMER] = 0x40;
+dev-config[PCI_INTERRUPT_LINE] = 0xff; /* End */
memory_region_init_io(s-io_bar, vmsvga_io_ops, s-chip,
vmsvga-io, 0x10);
memory_region_set_flush_coalesced(s-io_bar);
-pci_register_bar(s-card, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io_bar);
+pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, s-io_bar);
vmsvga_init(DEVICE(dev), s-chip,
pci_address_space(dev), pci_address_space_io(dev));
-pci_register_bar(s-card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
+pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
s-chip.vga.vram);
-pci_register_bar(s-card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
+pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
s-chip.fifo_ram);
if (!dev-rom_bar) {
--
1.8.1.4
Re: [Qemu-devel] [PATCH v2 13/30] misc/ivshmem: QOM Upcast Sweep
Am 30.06.2013 11:18, schrieb Andreas Färber:
Am 24.06.2013 08:59, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/misc/ivshmem.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 5658f73..fd40caf 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -48,6 +48,10 @@
#define IVSHMEM_DPRINTF(fmt, ...)
#endif
+#define TYPE_IVSHMEM ivshmem
+#define IVSHMEM(obj) \
+OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
+
typedef struct Peer {
int nb_eventfds;
EventNotifier *eventfds;
@@ -341,7 +345,7 @@ static void create_shared_memory_BAR(IVShmemState *s,
int fd) {
memory_region_init_ram_ptr(s-ivshmem, ivshmem.bar2,
s-ivshmem_size, ptr);
-vmstate_register_ram(s-ivshmem, s-dev.qdev);
+vmstate_register_ram(s-ivshmem, DEVICE(s-dev));
DEVICE(s)
memory_region_add_subregion(s-bar, 0, s-ivshmem);
/* region for shared memory */
@@ -469,7 +473,7 @@ static void ivshmem_read(void *opaque, const uint8_t *
buf, int flags)
incoming_fd, 0);
memory_region_init_ram_ptr(s-ivshmem,
ivshmem.bar2, s-ivshmem_size,
map_ptr);
-vmstate_register_ram(s-ivshmem, s-dev.qdev);
+vmstate_register_ram(s-ivshmem, DEVICE(s-dev));
DEVICE(s)
Renaming the parent field showed that there are still some s-dev
accesses missed in this patch. Applying anyway to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Missed two DO_UPCAST()s, fixed up.
Andreas
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index dcf1402..1f5f059 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -643,7 +643,7 @@ static void ivshmem_write_config(PCIDevice *pci_dev,
uint32_t address,
static int pci_ivshmem_init(PCIDevice *dev)
{
-IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
+IVShmemState *s = IVSHMEM(dev);
uint8_t *pci_conf;
if (s-sizearg == NULL)
@@ -775,7 +775,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
static void pci_ivshmem_uninit(PCIDevice *dev)
{
-IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
+IVShmemState *s = IVSHMEM(dev);
if (s-migration_blocker) {
migrate_del_blocker(s-migration_blocker);
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH qom-next] misc/ivshmem: QOM parent field cleanup
Rename to parent_obj and fix any fallout.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/misc/ivshmem.c | 37 ++---
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 1f5f059..55def3a 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -63,7 +63,10 @@ typedef struct EventfdEntry {
} EventfdEntry;
typedef struct IVShmemState {
-PCIDevice dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
uint32_t intrmask;
uint32_t intrstatus;
uint32_t doorbell;
@@ -120,6 +123,7 @@ static inline bool is_power_of_two(uint64_t x) {
/* accessing registers - based on rtl8139 */
static void ivshmem_update_irq(IVShmemState *s, int val)
{
+PCIDevice *d = PCI_DEVICE(s);
int isr;
isr = (s-intrstatus s-intrmask) 0x;
@@ -129,7 +133,7 @@ static void ivshmem_update_irq(IVShmemState *s, int val)
isr ? 1 : 0, s-intrstatus, s-intrmask);
}
-qemu_set_irq(s-dev.irq[0], (isr != 0));
+qemu_set_irq(d-irq[0], (isr != 0));
}
static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
@@ -300,7 +304,7 @@ static CharDriverState* create_eventfd_chr_device(void *
opaque, EventNotifier *
/* if MSI is supported we need multiple interrupts */
if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
-s-eventfd_table[vector].pdev = s-dev;
+s-eventfd_table[vector].pdev = PCI_DEVICE(s);
s-eventfd_table[vector].vector = vector;
qemu_chr_add_handlers(chr, ivshmem_can_receive, fake_irqfd,
@@ -349,7 +353,7 @@ static void create_shared_memory_BAR(IVShmemState *s, int
fd) {
memory_region_add_subregion(s-bar, 0, s-ivshmem);
/* region for shared memory */
-pci_register_bar(s-dev, 2, s-ivshmem_attr, s-bar);
+pci_register_bar(PCI_DEVICE(s), 2, s-ivshmem_attr, s-bar);
}
static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
@@ -525,14 +529,15 @@ static void ivshmem_read(void *opaque, const uint8_t *
buf, int flags)
* we just enable all vectors on init and after reset. */
static void ivshmem_use_msix(IVShmemState * s)
{
+PCIDevice *d = PCI_DEVICE(s);
int i;
-if (!msix_present(s-dev)) {
+if (!msix_present(d)) {
return;
}
for (i = 0; i s-vectors; i++) {
-msix_vector_use(s-dev, i);
+msix_vector_use(d, i);
}
}
@@ -573,7 +578,7 @@ static uint64_t ivshmem_get_size(IVShmemState * s) {
static void ivshmem_setup_msi(IVShmemState * s)
{
-if (msix_init_exclusive_bar(s-dev, s-vectors, 1)) {
+if (msix_init_exclusive_bar(PCI_DEVICE(s), s-vectors, 1)) {
IVSHMEM_DPRINTF(msix initialization failed\n);
exit(1);
}
@@ -589,12 +594,13 @@ static void ivshmem_setup_msi(IVShmemState * s)
static void ivshmem_save(QEMUFile* f, void *opaque)
{
IVShmemState *proxy = opaque;
+PCIDevice *pci_dev = PCI_DEVICE(proxy);
IVSHMEM_DPRINTF(ivshmem_save\n);
-pci_device_save(proxy-dev, f);
+pci_device_save(pci_dev, f);
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
-msix_save(proxy-dev, f);
+msix_save(pci_dev, f);
} else {
qemu_put_be32(f, proxy-intrstatus);
qemu_put_be32(f, proxy-intrmask);
@@ -607,6 +613,7 @@ static int ivshmem_load(QEMUFile* f, void *opaque, int
version_id)
IVSHMEM_DPRINTF(ivshmem_load\n);
IVShmemState *proxy = opaque;
+PCIDevice *pci_dev = PCI_DEVICE(proxy);
int ret;
if (version_id 0) {
@@ -618,13 +625,13 @@ static int ivshmem_load(QEMUFile* f, void *opaque, int
version_id)
return -EINVAL;
}
-ret = pci_device_load(proxy-dev, f);
+ret = pci_device_load(pci_dev, f);
if (ret) {
return ret;
}
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
-msix_load(proxy-dev, f);
+msix_load(pci_dev, f);
ivshmem_use_msix(proxy);
} else {
proxy-intrstatus = qemu_get_be32(f);
@@ -682,7 +689,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
migrate_add_blocker(s-migration_blocker);
}
-pci_conf = s-dev.config;
+pci_conf = dev-config;
pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_config_set_interrupt_pin(pci_conf, 1);
@@ -693,7 +700,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
ivshmem-mmio, IVSHMEM_REG_BAR_SIZE);
/* region for registers*/
-pci_register_bar(s-dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
+pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
s-ivshmem_mmio);
memory_region_init(s-bar, ivshmem-bar2-container, s-ivshmem_size);
@@ -727,7 +734,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
/* allocate/initialize space for interrupt handling */
s-peers = g_malloc0(s-nb_peers * sizeof(Peer));
-pci_register_bar(s-dev, 2, s-ivshmem_attr, s-bar);
+pci_register_bar(dev, 2,
Re: [Qemu-devel] [PATCH v4 06/10] qemu-ga: Add Windows VSS provider to quiesce applications on fsfreeze
On 26/06/2013 01:31, Tomoki Sekiyama wrote: Also, is it needed to call VSSCheckOSVersion from the requestor? I would think that checking VSSAPI.DLL is stronger than checking the version, and indeed you do that check too. In Windows XP, VSSAPI.DLL exists but it has different functionality and interfaces from newer Windows. http://msdn.microsoft.com/en-us/library/windows/desktop/aa384627(v=vs.85).aspx It is checking the OS version because this patchset only supports Windows 2003 or later. So why don't you query for the interface you supports rather than checking the OS version? Thanks, Gal. Thanks, Tomoki Sekiyama
[Qemu-devel] [PATCH qom-next] xen/xen_platform: QOM parent field cleanup
Replace direct uses of PCIXenPlatformState::pci_dev field with QOM casts
and rename it to parent_obj.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/xen/xen_platform.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/xen/xen_platform.c b/hw/xen/xen_platform.c
index 24c2118..5138acb 100644
--- a/hw/xen/xen_platform.c
+++ b/hw/xen/xen_platform.c
@@ -49,7 +49,10 @@
#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
typedef struct PCIXenPlatformState {
-PCIDevice pci_dev;
+/* private */
+PCIDevice parent_obj;
+/* public */
+
MemoryRegion fixed_io;
MemoryRegion bar;
MemoryRegion mmio_bar;
@@ -121,7 +124,8 @@ static void platform_fixed_ioport_writew(void *opaque,
uint32_t addr, uint32_t v
PCIXenPlatformState *s = opaque;
switch (addr) {
-case 0:
+case 0: {
+PCIDevice *pci_dev = PCI_DEVICE(s);
/* Unplug devices. Value is a bitmask of which devices to
unplug, with bit 0 the IDE devices, bit 1 the network
devices, and bit 2 the non-primary-master IDE devices. */
@@ -129,16 +133,17 @@ static void platform_fixed_ioport_writew(void *opaque,
uint32_t addr, uint32_t v
DPRINTF(unplug disks\n);
bdrv_drain_all();
bdrv_flush_all();
-pci_unplug_disks(s-pci_dev.bus);
+pci_unplug_disks(pci_dev-bus);
}
if (val UNPLUG_ALL_NICS) {
DPRINTF(unplug nics\n);
-pci_unplug_nics(s-pci_dev.bus);
+pci_unplug_nics(pci_dev-bus);
}
if (val UNPLUG_AUX_IDE_DISKS) {
DPRINTF(unplug auxiliary disks not supported\n);
}
break;
+}
case 2:
switch (val) {
case 1:
@@ -367,7 +372,7 @@ static const VMStateDescription vmstate_xen_platform = {
.minimum_version_id_old = 4,
.post_load = xen_platform_post_load,
.fields = (VMStateField []) {
-VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
+VMSTATE_PCI_DEVICE(parent_obj, PCIXenPlatformState),
VMSTATE_UINT8(flags, PCIXenPlatformState),
VMSTATE_END_OF_LIST()
}
@@ -378,7 +383,7 @@ static int xen_platform_initfn(PCIDevice *dev)
PCIXenPlatformState *d = XEN_PLATFORM(dev);
uint8_t *pci_conf;
-pci_conf = d-pci_dev.config;
+pci_conf = dev-config;
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
@@ -387,11 +392,11 @@ static int xen_platform_initfn(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 1;
platform_ioport_bar_setup(d);
-pci_register_bar(d-pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, d-bar);
+pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, d-bar);
/* reserve 16MB mmio address for share memory*/
platform_mmio_setup(d);
-pci_register_bar(d-pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
+pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
d-mmio_bar);
platform_fixed_ioport_init(d);
--
1.8.1.4
Re: [Qemu-devel] [PATCH] RFCv3 kvm irqfd: support msimessage to irq translation in PHB
On Sun, Jun 30, 2013 at 2:37 AM, Alexey Kardashevskiy a...@ozlabs.ru wrote: On 06/30/2013 12:28 AM, Anthony Liguori wrote: Ah. Everybody ignored, I'll try asking again :) kvm_irqchip_update_msi_route() - where should it go? What is it for? virtio-pci and pci device assignment use it but vfio does not - is it a bug of vfio? Thanks. The data part of an MSI message contains information about how to deliver the interrupt. But when we add a virq, it has essentially a fixed data value. So if the guest sends a data message that contains anything but the fixed data value, we need to swizzle the routing table to use the new data value. Michael can probably describe why this is needed in practice and Alex why this isn't used in VFIO. Regards, Anthony Liguori -- Alexey
Re: [Qemu-devel] [PATCH] RFCv3 kvm irqfd: support msimessage to irq translation in PHB
On Sat, Jun 29, 2013 at 7:59 PM, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 06/30/2013 12:28 AM, Anthony Liguori wrote:
Perhaps (2) can just be the default PCI bus implementation to simplify
things.
hw/pci/pci.c does not have any kvm code yet and I would like not to be the
first person who tries adding this there :)
But ok, I'll do it.
More often than not, the PHB is part of the northbridge and has direct
interactions with the CPUs. Since KVM is really modeling the CPUs,
it makes sense that the PHB would need to have some knowledge of KVM.
It's a bit silly for a PCI device like virtio-pci to have direct
knowledge of KVM...
You don't need this function. You can do this overloading as part of
the PCI bus initialization in spapr_pci.c
pci_bus_set_route_irq_fn is there already and I tried to follow the
existing pattern (yeah, missed assert though). Or this is different?
Yeah, the existing pattern sucks. PCI is long overdue for a
significant refactoring.
Regards,
Anthony Liguori
Regards,
Anthony Liguori
+int pci_bus_map_msi(PCIBus *bus, MSIMessage msg)
+{
+if (bus-map_msi) {
+return bus-map_msi(bus, msg);
+}
+return -1;
+}
+
/*
* PCI-to-PCI bridge specification
* 9.1: Interrupt routing. Table 9-1
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 23dbc0e..bae4faf 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -486,6 +486,11 @@ static void spapr_msi_write(void *opaque, hwaddr addr,
qemu_irq_pulse(xics_get_qirq(spapr-icp, irq));
}
+static int spapr_msi_get_irq(PCIBus *bus, MSIMessage msg)
+{
+return msg.data;
+}
+
static const MemoryRegionOps spapr_msi_ops = {
/* There is no .read as the read result is undefined by PCI spec */
.read = NULL,
@@ -657,6 +662,7 @@ static int spapr_phb_init(SysBusDevice *s)
sphb-lsi_table[i].irq = irq;
}
+pci_bus_set_map_msi_fn(bus, spapr_msi_get_irq);
return 0;
}
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b070b64..06a4e13 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -481,7 +481,7 @@ static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy
*proxy,
int ret;
if (irqfd-users == 0) {
-ret = kvm_irqchip_add_msi_route(kvm_state, msg);
+ret = kvm_irqchip_add_msi_route(kvm_state, proxy-pci_dev.bus,
msg);
if (ret 0) {
return ret;
}
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 6ef1f97..8c1edd6 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -332,6 +332,7 @@ MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
+typedef int (*pci_map_msi_fn)(PCIBus *bus, MSIMessage msg);
typedef enum {
PCI_HOTPLUG_DISABLED,
@@ -375,6 +376,9 @@ bool pci_intx_route_changed(PCIINTxRoute *old,
PCIINTxRoute *new);
void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
PCIINTxRoutingNotifier notifier);
+void pci_bus_set_map_msi_fn(PCIBus *bus, pci_map_msi_fn map_msi_fn);
+int pci_bus_map_msi(PCIBus *bus, MSIMessage msg);
+
void pci_device_reset(PCIDevice *dev);
void pci_bus_reset(PCIBus *bus);
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 66762f6..81efd2b 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -16,6 +16,7 @@ struct PCIBus {
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
pci_route_irq_fn route_intx_to_irq;
+pci_map_msi_fn map_msi;
pci_hotplug_fn hotplug;
DeviceState *hotplug_qdev;
void *irq_opaque;
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index f404d16..1bf2abe 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -305,8 +305,8 @@ static inline void cpu_synchronize_post_init(CPUState
*cpu)
}
}
-int kvm_irqchip_add_msi_route(KVMState *s, MSIMessage msg);
int kvm_irqchip_update_msi_route(KVMState *s, int virq, MSIMessage msg);
+int kvm_irqchip_add_msi_route(KVMState *s, PCIBus *pbus, MSIMessage msg);
void kvm_irqchip_release_virq(KVMState *s, int virq);
int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n, int
virq);
diff --git a/kvm-all.c b/kvm-all.c
index 1f81cca..3b7710d 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1180,11 +1180,16 @@ int kvm_irqchip_send_msi(KVMState *s, MSIMessage
msg)
return kvm_set_irq(s, route-kroute.gsi, 1);
}
-int kvm_irqchip_add_msi_route(KVMState *s, MSIMessage msg)
+int kvm_irqchip_add_msi_route(KVMState *s, PCIBus *pbus, MSIMessage msg)
{
struct kvm_irq_routing_entry kroute;
int virq;
+virq = pci_bus_map_msi(pbus, msg);
+if (virq = 0) {
+
Re: [Qemu-devel] [PATCH 21/26] kvmclock: use realize for kvmclock
Am 25.06.2013 19:45, schrieb Eduardo Habkost: On Tue, Jun 25, 2013 at 10:20:08AM +0800, Hu Tao wrote: [...] Is TYPE_SYS_BUS_DEVICE guaranteed to never override -realize() itself? From DeviceClass documentation: * If a type derived directly from TYPE_DEVICE implements @realize, it does * not need to implement @init and therefore does not need to store and call * #DeviceClass' default @realize callback. * For other types consult the documentation and implementation of the * respective parent types. The problem is that there's no documentation about -realize() on SysBusDeviceClass. Can we please explicitly document SysBusDeviceClass expectations about -realize() first, before making those changes? If someone wants to add a paragraph to sysbus.h:SysBusDeviceClass documentation I would happily ack or pick that up. :) IIUC, subclass's overriding -realize should call parent's -realize at some point. Peter Crosthwaite has a patchset to access a object's parent class at http://lists.nongnu.org/archive/html/qemu-devel/2013-06/msg02982.html Regarding SysBusDevice::init and SysBusDevice::realize, I think it's the same as in the case of DeviceClass. If you agree I'll document it as in DeviceClass. I believe it is reasonable to document that SysBusDevice subclasses don't need to call the parent -realize() method, like on DeviceClass. This is exactly what this patch set does, after all, and I haven't seen anybody complaining about it yet. So the thing is that SysBusDevice's DeviceClass::init implementation, called by DeviceState's DeviceClass::realize implementation, just calls SysBusDeviceClass::init if non-NULL. When we introduce our own device's realizefn to replace our SysBusDeviceClass::init implementation, there is no point calling that effectively no-op DeviceClass::realize implementation. And if we tried to, ... * ... how would we decide whether to call the parent's implementation first or last? It's not yes or no, it's no or when. Changing between either is more than just moving one line, it affects error handling and with knowledge about parent implementation never failing we could so far save us some work. * ... with the current QOM method scheme we'd go insane introducing a FooClass per device to save SysBusDevice's DeviceClass::realize in FooClass::parent_realize. Still waiting for Anthony on whether and how we want to change our scheme. Long story short: If someone wants to mess with base classes they get to check derived classes for compatibility with their change. Ideally qtest would help automate that to some degree. I would be all in favor if someone wanted to add a dummy test case per non-default, non-KVM device converted so that we can see that we didn't screw up -device instantiation too badly. Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 26/26] ehci: use realize for ehci
Am 22.06.2013 12:38, schrieb Andreas Färber: Am 22.06.2013 10:50, schrieb Hu Tao: Cc: Gerd Hoffmann kra...@redhat.com Signed-off-by: Hu Tao hu...@cn.fujitsu.com --- hw/usb/hcd-ehci-sysbus.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) I had already done this iirc, it should be in Gerd's USB queue, [...] FTR it was merged earlier this week: http://git.qemu.org/?p=qemu.git;a=commit;h=89f204d2c60fbf3e0c5af1ff1681e57c9f057178 Thanks, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 25/26] isa bus: use realize for isa bus
The subject is a bit misleading, suggest:
isa-bus: Use QOM realize for ISA SysBus bridge
Am 22.06.2013 10:50, schrieb Hu Tao:
Cc: Andreas Färber afaer...@suse.de
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Anthony Liguori aligu...@us.ibm.com
Cc: Avi Kivity a...@redhat.com
This will bounce, please drop. ;)
Also, if you use git-send-email together with
scripts/get_maintainer.pl --nogit-fallback you only need to add any
CCs missing in MAINTAINERS file per commit.
Cc: Jim Meyering meyer...@redhat.com
Signed-off-by: Hu Tao hu...@cn.fujitsu.com
---
hw/isa/isa-bus.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 136d17e..287f941 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -192,18 +192,17 @@ static void isabus_dev_print(Monitor *mon, DeviceState
*dev, int indent)
}
}
-static int isabus_bridge_init(SysBusDevice *dev)
+static void isabus_bridge_realize(DeviceState *dev, Error **errp)
{
/* nothing */
-return 0;
+return;
Not needed.
}
static void isabus_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = isabus_bridge_init;
+dc-realize = isabus_bridge_realize;
dc-fw_name = isa;
dc-no_user = 1;
}
I would propose to simply drop the init function instead of turning it
into a realize function unless you see a future use case for it.
Historically it was not possible to omit a SysBusDevice init function:
http://git.qemu.org/?p=qemu.git;a=commit;h=4ce5dae88ecf2bafa0cd663de7e923728b1b3672
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 00/30] PCI: Cleanup legacy casts in device land
Am 30.06.2013 12:44, schrieb Andreas Färber: Peter Crosthwaite (30): net/e1000: QOM Upcast Sweep net/rtl8139: QOM Upcast Sweep net/pcnet-pci: QOM Upcast Sweep usb/hcd-xhci: QOM Upcast Sweep scsi/lsi53c895a: QOM Upcast Sweep scsi/megasas: QOM Upcast Sweep scsi/esp-pci: QOM Upcast Sweep ide/ich: QOM Upcast Sweep ide/piix: QOM casting sweep acpi/piix4: QOM Upcast Sweep misc/pci-testdev: QOM Upcast Sweep virtio/vmware_vga: QOM casting sweep misc/ivshmem: QOM Upcast Sweep xen/xen_platform: QOM casting sweep As requested, I've started picking up QOM type/cast/realize patches on: git://github.com/afaerber/qemu-cpu.git qom-next https://github.com/afaerber/qemu-cpu/commits/qom-next [...] I've queued all patches above except for ide/piix (09/30) and had comments and/or minor changes for some of them. Noticing some incompleteness, I will reiterate over them. I've posted and inserted patches accompanying these or squashed casts/parent_obj as indicated where trivial, so that these devices are QOM'ified modulo any remaining -qdev or -qbus accesses or realizefn. (My commit messages have been tidied à la xen-platform.) Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
[Rehashing a previous thread]
19.06.2013 20:58, Paolo Bonzini wrote:
Il 18/06/2013 19:34, Michael Tokarev ha scritto:
The following working patchset demonstrates a one step to plugins system:
it moves various dependent libraries and stuff out from libs_softmmu or
libs_tools to object-specific variables. When that object is linked
into final executable, corresponding libs are expanded and appended to
the linking command line.
I took block/curl.o as an example (in the last patch).
This is a working example which can be used as is as a starting point
to convert other similar cases.
I was thinking of this problem too while drafting the modules feature
page. My solution had some duplication:
libs-$(CONFIG_CURL) += $(CURL_LIBS)
$(obj)/curl.so: libs-$(CONFIG_CURL) += $(CURL_LIBS)
where the .so rule would use $(libs-y) $(libs-m).
There are a few questions still.
I'm not sure whenever this $(obj)foo.o syntax (instead of $(obj)/foo.o)
is okay, using the slash is more natural, but when you realize that
objects can be stored in current dir it may be okay. However, it is
easy to make mistakes here in new code -- probably trivially catchable.
The foo.cflags isn't really necessary, but when you specify one
thing one way (target-specific variable), and another thing completely
different way, resulting code does not look nice. In particular, the
two curl definitions in block/Makefile.objs look somewhat funky if
curl.cflags isn't used.
I like this solution, and I agree that consistency between cflags and
libs is good. However, it would be great if you could do it without
changing the meaning of $(obj). It is not clear to me (from reading the
patches) why you need that.
Also, for the inevitable bikeshedding, I would prefer
cflags-$(obj)/curl.o-y
libs-$(obj)/curl.o-y
There's no need to have -y or -n prefix here, at least for now,
because a) it does look ugly -- this is what we have to actually
specify in makefile, and b) we don't really need to have different
libs for static vs dynamic linking or flags. I think anyway.
Also, my version (which uses $(obj)/curl.{libs,cflags,mod}) is safer
because the names will not clash with each other.
It is quite a bit ugly to strip out ../ in the link line, but it is
also ugly to add that ../ in the first place. Maybe I should add a
comment in Makefile.target where it adds ../ to also refer to
rules.mak, and back, for clarity.
The ../ is ugly indeed. Perhaps we can instead use something like
common.o: $(patsubst %,../%, $(common-obj-y))
$(LD) -r -o $@ $^
and then link common.o into the QEMU target. Libtool can also be used
to abstract ld -r. Making libtool mandatory wouldn't be a problem IMO
(we'd need it anyway for modules) as long as you do not need libtool to
start QEMU or gdb from the build directory.
I think this will mean that whole common.o will have to be linked
into each executable which uses it, even if some executables are
only using just one function from whole lot of .o files.
And I think we don't really have a choice here BUT to actually build a
shared library with all this stuff, which will be loaded either by
qemu-system binary or by tools (or by qemu-user for that matter) --
it looks like the only sane way to get all required-for-plugins symbols
is to use a shared library.
The same mechanism can be used to build .a static library too, so there
will be no different rules for plugins-vs-non-plugins cases.
And if foo.so or foo.a library is built, all the foo.libs of all
objects/modules which are members of that library, can be combined
into ${fooo.libs} just as well.
Thanks,
/mjt
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
Am 18.06.2013 19:34, schrieb Michael Tokarev: The following working patchset demonstrates a one step to plugins system: it moves various dependent libraries and stuff out from libs_softmmu or libs_tools to object-specific variables. We did have a more elaborate Makefile variable system before, but Paolo stashed most of that into common-obj-y and obj-y for simplicity. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
30.06.2013 19:28, Andreas Färber wrote: Am 18.06.2013 19:34, schrieb Michael Tokarev: The following working patchset demonstrates a one step to plugins system: it moves various dependent libraries and stuff out from libs_softmmu or libs_tools to object-specific variables. We did have a more elaborate Makefile variable system before, but Paolo stashed most of that into common-obj-y and obj-y for simplicity. I don't understand. I for one like to see a plugins system used in qemu, and except of the build system everything else is easy (and even nice, there's even no need to load all plugins at startup as was initially suggested). But for this to work, we really need to separate libs used only by plugins from the main lot, -- or else there's just no reason to build plugins in the first place. So, are you saying we should abandom this whole idea? Or that maybe Paolo dislikes it (I think he expressed his interest here too)? Count me confused. Thanks, /mjt
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
On 30 June 2013 16:36, Michael Tokarev m...@tls.msk.ru wrote: I don't understand. I for one like to see a plugins system used in qemu, and except of the build system everything else is easy (and even nice, there's even no need to load all plugins at startup as was initially suggested). But for this to work, we really need to separate libs used only by plugins from the main lot, -- or else there's just no reason to build plugins in the first place. So, why do we want to build things as plugins? Neither of the cover letters to your two patch series nor Anthony's wiki page on modules actually give the rationale. I'd like to see the reasons why we want this feature clearly laid out, because it is a big load of extra faff and potential portability issues (surrounding dlopen, possible use of libtool, etc), as well as being really easy to misunderstand as some kind of promise of API/ABI stability or third-party extension functionality.[*] [*] by which I mean that although everybody here proposing patches is clear that that's out of scope, end users don't generally read patches and rationale emails, and we dlopen device models looks really really like a plugin ABI... thanks -- PMM
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
Am 30.06.2013 17:36, schrieb Michael Tokarev: 30.06.2013 19:28, Andreas Färber wrote: Am 18.06.2013 19:34, schrieb Michael Tokarev: The following working patchset demonstrates a one step to plugins system: it moves various dependent libraries and stuff out from libs_softmmu or libs_tools to object-specific variables. We did have a more elaborate Makefile variable system before, but Paolo stashed most of that into common-obj-y and obj-y for simplicity. I don't understand. I for one like to see a plugins system used in qemu, and except of the build system everything else is easy (and even nice, there's even no need to load all plugins at startup as was initially suggested). But for this to work, we really need to separate libs used only by plugins from the main lot, -- or else there's just no reason to build plugins in the first place. So, are you saying we should abandom this whole idea? Or that maybe Paolo dislikes it (I think he expressed his interest here too)? I haven't read the whole thread yet, so count me confused too, including that Paolo didn't reply to that part of the message at all. Whenever the question of a plugin system came up, it was mostly about desperate attempts to try to sneak GPL-incompatible code into QEMU. I doubt that is the case here, so I am not generally opposed. I assume your interest is rather reducing packaging dependencies for headless installs etc.? The only thing I was pointing out for now is that with regards to our build system our ship seems to have a slingering course, with objects originally being grouped by functionality/scope, then thrown into a big pot, now apparently being picked apart again. And implicitly I was hinting that there are people with out-of-tree patchsets that constantly need to rebase on these Makefile changes, me finding a whole Makefile.objs as conflict much more confusing to resolve than a new file not compiling due to some CPUState or QOM code changes. Not saying you shouldn't apply changes for cool features, please just coordinate with Paolo to avoid unnecessary back-and-forth in the build system. Cheers, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 00/26] use realizefn for SysBusDevice, part 1
Hi, Am 22.06.2013 10:50, schrieb Hu Tao: This series updates part of devices inheriting from SysbusDevice to use DeviceState::realize, and QOM'ify them. These devices are default to x86_64-softmmu. I'm planning to make patches in the same manner, that is, each series is for devices default to each target. After all devices are converted to realizefn, SysBusDevice::init can be removed. This series looks promising. As was requested by others, please rebase (possibly on qom-next if there's conflicts with Peter M.'s patch?) and reorder the patches so that QOM cast macros come before more functional changes (the former can be picked up more quickly). For ARM I am looking into a few devices surrounding cpu/a9mpcore.c. Paolo has announced a PULL for his MemoryRegion refactorings for beginning of the week, which is likely to conflict with realizefn work. As a reminder for realize series (we should definitely document this!): * QOM realize functions should not create new devices as that creates problems with recursive realized = true and will prohibit changing static device properties through QMP. (Therefore more review work.) * Care must be taken with bus creation since qbus_create[_inplace]() / qbus_realize() check for DeviceState::id, which is still NULL at instance_init time. (OHCI looked good for instance.) Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC PATCH 0/4] per-object libraries
30.06.2013 19:51, Peter Maydell wrote: On 30 June 2013 16:36, Michael Tokarev m...@tls.msk.ru wrote: I don't understand. I for one like to see a plugins system used in qemu, and except of the build system everything else is easy (and even nice, there's even no need to load all plugins at startup as was initially suggested). But for this to work, we really need to separate libs used only by plugins from the main lot, -- or else there's just no reason to build plugins in the first place. So, why do we want to build things as plugins? Neither of the cover letters to your two patch series nor Anthony's wiki page on modules actually give the rationale. I just updated the wiki page a bit (which is at http://wiki.qemu.org/Features/Modules btw). The main rationale so far is to allow separate packaging of separate features for downstreams, to reduce the need to install all dependent libraries/packages. I'd like to see the reasons why we want this feature clearly laid out, because it is a big load of extra faff and potential portability issues (surrounding dlopen, possible use of libtool, etc), as well as being really easy to misunderstand as some kind of promise of API/ABI stability or third-party extension functionality.[*] [*] by which I mean that although everybody here proposing patches is clear that that's out of scope, end users don't generally read patches and rationale emails, and we dlopen device models looks really really like a plugin ABI... This has been mentioned already, one of the easy ways to prevent this is to add some build id to all main symbols, so that only modules from the same build will be loadable. I mentioned this in the wiki page too. Thanks, /mjt
[Qemu-devel] [PATCH RFC 03/15] cpu/a9mpcore: Embed GICState
From: Andreas Färber andreas.faer...@web.de
Prepares for conversion to QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 63a4eb1..6340b0f 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -9,6 +9,7 @@
*/
#include hw/sysbus.h
+#include hw/intc/gic_internal.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -23,15 +24,17 @@ typedef struct A9MPPrivState {
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdt;
-DeviceState *gic;
DeviceState *scu;
uint32_t num_irq;
+
+GICState gic;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
A9MPPrivState *s = (A9MPPrivState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
static void a9mp_priv_initfn(Object *obj)
@@ -40,19 +43,23 @@ static void a9mp_priv_initfn(Object *obj)
memory_region_init(s-container, a9mp-priv-container, 0x2000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-container);
+
+object_initialize(s-gic, TYPE_ARM_GIC);
+qdev_set_parent_bus(DEVICE(s-gic), sysbus_get_default());
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
+DeviceState *gicdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
-s-gic = qdev_create(NULL, arm_gic);
-qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
-qdev_prop_set_uint32(s-gic, num-irq, s-num_irq);
-qdev_init_nofail(s-gic);
-gicbusdev = SYS_BUS_DEVICE(s-gic);
+gicdev = DEVICE(s-gic);
+qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
+qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
+qdev_init_nofail(gicdev);
+gicbusdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, gicbusdev);
@@ -107,9 +114,9 @@ static int a9mp_priv_init(SysBusDevice *dev)
for (i = 0; i s-num_cpu; i++) {
int ppibase = (s-num_irq - 32) + i * 32;
sysbus_connect_irq(timerbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 29));
+ qdev_get_gpio_in(gicdev, ppibase + 29));
sysbus_connect_irq(wdtbusdev, i,
- qdev_get_gpio_in(s-gic, ppibase + 30));
+ qdev_get_gpio_in(gicdev, ppibase + 30));
}
return 0;
}
--
1.8.1.4
[Qemu-devel] [PATCH RFC 04/15] misc/a9scu: QOM cleanups
From: Andreas Färber andreas.faer...@web.de
Rename A9SCUState::busdev field to parent_obj and turn realizefn into an
instance_init function to allow early MMIO mapping.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/misc/a9scu.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 05897c2..30f6fac 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -13,7 +13,10 @@
/* A9MP private memory region. */
typedef struct A9SCUState {
-SysBusDevice busdev;
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
MemoryRegion iomem;
uint32_t control;
uint32_t status;
@@ -114,10 +117,10 @@ static void a9_scu_reset(DeviceState *dev)
s-control = 0;
}
-static void a9_scu_realize(DeviceState *dev, Error ** errp)
+static void a9_scu_init(Object *obj)
{
-A9SCUState *s = A9_SCU(dev);
-SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+A9SCUState *s = A9_SCU(obj);
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(s-iomem, a9_scu_ops, s, a9-scu, 0x100);
sysbus_init_mmio(sbd, s-iomem);
@@ -143,7 +146,6 @@ static void a9_scu_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-dc-realize = a9_scu_realize;
dc-props = a9_scu_properties;
dc-vmsd = vmstate_a9_scu;
dc-reset = a9_scu_reset;
@@ -153,6 +155,7 @@ static const TypeInfo a9_scu_info = {
.name = TYPE_A9_SCU,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9SCUState),
+.instance_init = a9_scu_init,
.class_init= a9_scu_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH RFC 02/15] cpu/a9mpcore: Split off instance_init
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 36254e9..63a4eb1 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -34,6 +34,14 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int
level)
qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
}
+static void a9mp_priv_initfn(Object *obj)
+{
+A9MPPrivState *s = A9MPCORE_PRIV(obj);
+
+memory_region_init(s-container, a9mp-priv-container, 0x2000);
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-container);
+}
+
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
@@ -78,7 +86,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
*
* We should implement the global timer but don't currently do so.
*/
-memory_region_init(s-container, a9mp-priv-container, 0x2000);
memory_region_add_subregion(s-container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
@@ -94,8 +101,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
-sysbus_init_mmio(dev, s-container);
-
/* Wire up the interrupt from each watchdog and timer.
* For each core the timer is PPI 29 and the watchdog PPI 30.
*/
@@ -134,6 +139,7 @@ static const TypeInfo a9mp_priv_info = {
.name = TYPE_A9MPCORE_PRIV,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9MPPrivState),
+.instance_init = a9mp_priv_initfn,
.class_init= a9mp_priv_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH RFC 01/15] cpu/a9mpcore: QOM casting cleanup
From: Andreas Färber andreas.faer...@web.de
Introduce type constant and cast macro and enforce its use by
renaming A9MPPrivState::busdev field to parent_obj.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 0a1a10f..36254e9 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -10,8 +10,15 @@
#include hw/sysbus.h
+#define TYPE_A9MPCORE_PRIV a9mpcore_priv
+#define A9MPCORE_PRIV(obj) \
+OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
+
typedef struct A9MPPrivState {
-SysBusDevice busdev;
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
uint32_t num_cpu;
MemoryRegion container;
DeviceState *mptimer;
@@ -29,7 +36,7 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int
level)
static int a9mp_priv_init(SysBusDevice *dev)
{
-A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
+A9MPPrivState *s = A9MPCORE_PRIV(dev);
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
int i;
@@ -43,7 +50,7 @@ static int a9mp_priv_init(SysBusDevice *dev)
sysbus_pass_irq(dev, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(s-busdev.qdev, a9mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s-num_irq - 32);
s-scu = qdev_create(NULL, a9-scu);
qdev_prop_set_uint32(s-scu, num-cpu, s-num_cpu);
@@ -124,7 +131,7 @@ static void a9mp_priv_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo a9mp_priv_info = {
-.name = a9mpcore_priv,
+.name = TYPE_A9MPCORE_PRIV,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A9MPPrivState),
.class_init= a9mp_priv_class_init,
--
1.8.1.4
[Qemu-devel] [PATCH RFC 10/15] cpu/a9mpcore: Prepare for QOM embedding
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 24 +---
include/hw/cpu/a9mpcore.h | 37 +
2 files changed, 38 insertions(+), 23 deletions(-)
create mode 100644 include/hw/cpu/a9mpcore.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 67ecf5d..d70eae6 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -8,29 +8,7 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-#include hw/intc/gic_internal.h
-#include hw/misc/a9scu.h
-#include hw/timer/arm_mptimer.h
-
-#define TYPE_A9MPCORE_PRIV a9mpcore_priv
-#define A9MPCORE_PRIV(obj) \
-OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
-
-typedef struct A9MPPrivState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t num_cpu;
-MemoryRegion container;
-uint32_t num_irq;
-
-GICState gic;
-A9SCUState scu;
-ARMMPTimerState mptimer;
-ARMMPTimerState wdt;
-} A9MPPrivState;
+#include hw/cpu/a9mpcore.h
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
new file mode 100644
index 000..4a9ffc8
--- /dev/null
+++ b/include/hw/cpu/a9mpcore.h
@@ -0,0 +1,37 @@
+/*
+ * Cortex-A9MPCore internal peripheral emulation.
+ *
+ * Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2011 Linaro Limited.
+ * Written by Paul Brook, Peter Maydell.
+ *
+ * This code is licensed under the GPL.
+ */
+#ifndef HW_CPU_A9MPCORE_H
+#define HW_CPU_A9MPCORE_H
+
+#include hw/sysbus.h
+#include hw/intc/gic_internal.h
+#include hw/misc/a9scu.h
+#include hw/timer/arm_mptimer.h
+
+#define TYPE_A9MPCORE_PRIV a9mpcore_priv
+#define A9MPCORE_PRIV(obj) \
+OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
+
+typedef struct A9MPPrivState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+uint32_t num_cpu;
+MemoryRegion container;
+uint32_t num_irq;
+
+GICState gic;
+A9SCUState scu;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdt;
+} A9MPPrivState;
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH RFC 06/15] timer/arm_mptimer: QOM cast cleanup
From: Andreas Färber andreas.faer...@web.de
Introduce type constant and cast macro and rename
ARMMPTimerState::busdev to enforce its use.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/timer/arm_mptimer.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 317f5e4..588e34b 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -40,8 +40,15 @@ typedef struct {
MemoryRegion iomem;
} TimerBlock;
+#define TYPE_ARM_MP_TIMER arm_mptimer
+#define ARM_MP_TIMER(obj) \
+OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MP_TIMER)
+
typedef struct {
-SysBusDevice busdev;
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
uint32_t num_cpu;
TimerBlock timerblock[MAX_CPUS];
MemoryRegion iomem;
@@ -211,9 +218,9 @@ static void timerblock_reset(TimerBlock *tb)
static void arm_mptimer_reset(DeviceState *dev)
{
-ARMMPTimerState *s =
-FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
+ARMMPTimerState *s = ARM_MP_TIMER(dev);
int i;
+
for (i = 0; i ARRAY_SIZE(s-timerblock); i++) {
timerblock_reset(s-timerblock[i]);
}
@@ -221,8 +228,9 @@ static void arm_mptimer_reset(DeviceState *dev)
static int arm_mptimer_init(SysBusDevice *dev)
{
-ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
+ARMMPTimerState *s = ARM_MP_TIMER(dev);
int i;
+
if (s-num_cpu 1 || s-num_cpu MAX_CPUS) {
hw_error(%s: num-cpu must be between 1 and %d\n, __func__, MAX_CPUS);
}
@@ -295,7 +303,7 @@ static void arm_mptimer_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo arm_mptimer_info = {
-.name = arm_mptimer,
+.name = TYPE_ARM_MP_TIMER,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMMPTimerState),
.class_init= arm_mptimer_class_init,
--
1.8.1.4
[Qemu-devel] [PATCH RFC 00/15] arm: A9MPCore+A15MPCore QOM'ification
From: Andreas Färber andreas.faer...@web.de Hello Peter, This series fully QOM'ifies A9MPCore so that it can be embedded for Tegra2. It goes on to do the same for A15MPCore, which had previously been taken as template for Cortex-A57 by John Rigby. Separate headers are introduced to only expose device state to whom asks for it. Regards, Andreas Cc: Peter Maydell peter.mayd...@linaro.org Cc: Peter Crosthwaite peter.crosthwa...@xilinx.com Cc: Hu Tao hu...@cn.fujitsu.com Cc: Mian M. Hamayun m.hama...@virtualopensystems.com Cc: Claudio Fontana claudio.font...@huawei.com Cc: kvm...@lists.cs.columbia.edu Andreas Färber (15): cpu/a9mpcore: QOM casting cleanup cpu/a9mpcore: Split off instance_init cpu/a9mpcore: Embed GICState misc/a9scu: QOM cleanups cpu/a9mpcore: Embed A9SCUState timer/arm_mptimer: QOM cast cleanup timer/arm_mptimer: Convert to QOM realize cpu/a9mpcore: Embed ARMMPTimerState cpu/a9mpcore: Convert to QOM realize cpu/a9mpcore: Prepare for QOM embedding cpu/a15mpcore: QOM cast cleanup cpu/a15mpcore: Split off instance_init cpu/a15mpcore: Embed GICState cpu/a15mpcore: Convert to QOM realize cpu/a15mpcore: Prepare for QOM embedding hw/cpu/a15mpcore.c | 64 +++--- hw/cpu/a9mpcore.c | 118 +++-- hw/misc/a9scu.c| 23 ++-- hw/timer/arm_mptimer.c | 62 +- include/hw/cpu/a15mpcore.h | 44 +++ include/hw/cpu/a9mpcore.h | 37 + include/hw/misc/a9scu.h| 31 +++ include/hw/timer/arm_mptimer.h | 54 +++ 8 files changed, 294 insertions(+), 139 deletions(-) create mode 100644 include/hw/cpu/a15mpcore.h create mode 100644 include/hw/cpu/a9mpcore.h create mode 100644 include/hw/misc/a9scu.h create mode 100644 include/hw/timer/arm_mptimer.h -- 1.8.1.4
[Qemu-devel] [PATCH RFC 07/15] timer/arm_mptimer: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Split the SysBusDevice initfn into instance_init and realizefn.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/timer/arm_mptimer.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index 588e34b..a19ffa3 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -226,8 +226,18 @@ static void arm_mptimer_reset(DeviceState *dev)
}
}
-static int arm_mptimer_init(SysBusDevice *dev)
+static void arm_mptimer_init(Object *obj)
{
+ARMMPTimerState *s = ARM_MP_TIMER(obj);
+
+memory_region_init_io(s-iomem, arm_thistimer_ops, s,
+ arm_mptimer_timer, 0x20);
+sysbus_init_mmio(SYS_BUS_DEVICE(obj), s-iomem);
+}
+
+static void arm_mptimer_realize(DeviceState *dev, Error **errp)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ARMMPTimerState *s = ARM_MP_TIMER(dev);
int i;
@@ -244,19 +254,14 @@ static int arm_mptimer_init(SysBusDevice *dev)
* * timer for core 1
* and so on.
*/
-memory_region_init_io(s-iomem, arm_thistimer_ops, s,
- arm_mptimer_timer, 0x20);
-sysbus_init_mmio(dev, s-iomem);
for (i = 0; i s-num_cpu; i++) {
TimerBlock *tb = s-timerblock[i];
tb-timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
-sysbus_init_irq(dev, tb-irq);
+sysbus_init_irq(sbd, tb-irq);
memory_region_init_io(tb-iomem, timerblock_ops, tb,
arm_mptimer_timerblock, 0x20);
-sysbus_init_mmio(dev, tb-iomem);
+sysbus_init_mmio(sbd, tb-iomem);
}
-
-return 0;
}
static const VMStateDescription vmstate_timerblock = {
@@ -293,9 +298,8 @@ static Property arm_mptimer_properties[] = {
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
-sbc-init = arm_mptimer_init;
+dc-realize = arm_mptimer_realize;
dc-vmsd = vmstate_arm_mptimer;
dc-reset = arm_mptimer_reset;
dc-no_user = 1;
@@ -306,6 +310,7 @@ static const TypeInfo arm_mptimer_info = {
.name = TYPE_ARM_MP_TIMER,
.parent= TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMMPTimerState),
+.instance_init = arm_mptimer_init,
.class_init= arm_mptimer_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH RFC 08/15] cpu/a9mpcore: Embed ARMMPTimerState
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 46 +--
hw/timer/arm_mptimer.c | 35 ---
include/hw/timer/arm_mptimer.h | 54 ++
3 files changed, 86 insertions(+), 49 deletions(-)
create mode 100644 include/hw/timer/arm_mptimer.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index b7148fa..48f5897 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -11,6 +11,7 @@
#include hw/sysbus.h
#include hw/intc/gic_internal.h
#include hw/misc/a9scu.h
+#include hw/timer/arm_mptimer.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -23,12 +24,12 @@ typedef struct A9MPPrivState {
uint32_t num_cpu;
MemoryRegion container;
-DeviceState *mptimer;
-DeviceState *wdt;
uint32_t num_irq;
GICState gic;
A9SCUState scu;
+ARMMPTimerState mptimer;
+ARMMPTimerState wdt;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
@@ -54,12 +55,28 @@ static void a9mp_priv_initfn(Object *obj)
sbd = SYS_BUS_DEVICE(s-scu);
memory_region_add_subregion(s-container, 0,
sysbus_mmio_get_region(sbd, 0));
+
+object_initialize(s-mptimer, TYPE_ARM_MP_TIMER);
+qdev_set_parent_bus(DEVICE(s-mptimer), sysbus_get_default());
+
+object_initialize(s-wdt, TYPE_ARM_MP_TIMER);
+qdev_set_parent_bus(DEVICE(s-wdt), sysbus_get_default());
+
+/* Note that the A9 exposes only the timer/watchdog for this core
+ * memory region, not the timer/watchdog for core X ones 11MPcore has.
+ */
+sbd = SYS_BUS_DEVICE(s-mptimer);
+memory_region_add_subregion(s-container, 0x600,
+sysbus_mmio_get_region(sbd, 0));
+sbd = SYS_BUS_DEVICE(s-wdt);
+memory_region_add_subregion(s-container, 0x620,
+sysbus_mmio_get_region(sbd, 0));
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
-DeviceState *gicdev, *scudev;
+DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev;
int i;
@@ -79,15 +96,15 @@ static int a9mp_priv_init(SysBusDevice *dev)
qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
qdev_init_nofail(scudev);
-s-mptimer = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-mptimer, num-cpu, s-num_cpu);
-qdev_init_nofail(s-mptimer);
-timerbusdev = SYS_BUS_DEVICE(s-mptimer);
+mptimerdev = DEVICE(s-mptimer);
+qdev_prop_set_uint32(mptimerdev, num-cpu, s-num_cpu);
+qdev_init_nofail(mptimerdev);
+timerbusdev = SYS_BUS_DEVICE(s-mptimer);
-s-wdt = qdev_create(NULL, arm_mptimer);
-qdev_prop_set_uint32(s-wdt, num-cpu, s-num_cpu);
-qdev_init_nofail(s-wdt);
-wdtbusdev = SYS_BUS_DEVICE(s-wdt);
+wdtdev = DEVICE(s-wdt);
+qdev_prop_set_uint32(wdtdev, num-cpu, s-num_cpu);
+qdev_init_nofail(wdtdev);
+wdtbusdev = SYS_BUS_DEVICE(s-wdt);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x-0x00ff -- Snoop Control Unit
@@ -103,13 +120,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
/* GIC CPU interface */
memory_region_add_subregion(s-container, 0x100,
sysbus_mmio_get_region(gicbusdev, 1));
-/* Note that the A9 exposes only the timer/watchdog for this core
- * memory region, not the timer/watchdog for core X ones 11MPcore has.
- */
-memory_region_add_subregion(s-container, 0x600,
-sysbus_mmio_get_region(timerbusdev, 0));
-memory_region_add_subregion(s-container, 0x620,
-sysbus_mmio_get_region(wdtbusdev, 0));
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index a19ffa3..5558f40 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -19,41 +19,13 @@
* with this program; if not, see http://www.gnu.org/licenses/.
*/
-#include hw/sysbus.h
+#include hw/timer/arm_mptimer.h
#include qemu/timer.h
/* This device implements the per-cpu private timer and watchdog block
* which is used in both the ARM11MPCore and Cortex-A9MP.
*/
-#define MAX_CPUS 4
-
-/* State of a single timer or watchdog block */
-typedef struct {
-uint32_t count;
-uint32_t load;
-uint32_t control;
-uint32_t status;
-int64_t tick;
-QEMUTimer *timer;
-qemu_irq irq;
-MemoryRegion iomem;
-} TimerBlock;
-
-#define TYPE_ARM_MP_TIMER arm_mptimer
-#define ARM_MP_TIMER(obj) \
-OBJECT_CHECK(ARMMPTimerState, (obj), TYPE_ARM_MP_TIMER)
-
-typedef struct {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t
[Qemu-devel] [PATCH RFC 13/15] cpu/a15mpcore: Embed GICState
From: Andreas Färber andreas.faer...@web.de
This covers both emulated and KVM GIC.
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 1a15bf8..ee09b57 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -20,6 +20,7 @@
#include hw/sysbus.h
#include sysemu/kvm.h
+#include hw/intc/gic_internal.h
/* A15MP private memory region. */
@@ -35,40 +36,48 @@ typedef struct A15MPPrivState {
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
-DeviceState *gic;
+
+GICState gic;
} A15MPPrivState;
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
A15MPPrivState *s = (A15MPPrivState *)opaque;
-qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
+
+qemu_set_irq(qdev_get_gpio_in(DEVICE(s-gic), irq), level);
}
static void a15mp_priv_initfn(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
A15MPPrivState *s = A15MPCORE_PRIV(obj);
+DeviceState *gicdev;
+const char *gictype = arm_gic;
+
+if (kvm_irqchip_in_kernel()) {
+gictype = kvm-arm-gic;
+}
memory_region_init(s-container, a15mp-priv-container, 0x8000);
sysbus_init_mmio(sbd, s-container);
+
+object_initialize(s-gic, gictype);
+gicdev = DEVICE(s-gic);
+qdev_set_parent_bus(gicdev, sysbus_get_default());
+qdev_prop_set_uint32(gicdev, revision, 2);
}
static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = A15MPCORE_PRIV(dev);
+DeviceState *gicdev;
SysBusDevice *busdev;
-const char *gictype = arm_gic;
-
-if (kvm_irqchip_in_kernel()) {
-gictype = kvm-arm-gic;
-}
-s-gic = qdev_create(NULL, gictype);
-qdev_prop_set_uint32(s-gic, num-cpu, s-num_cpu);
-qdev_prop_set_uint32(s-gic, num-irq, s-num_irq);
-qdev_prop_set_uint32(s-gic, revision, 2);
-qdev_init_nofail(s-gic);
-busdev = SYS_BUS_DEVICE(s-gic);
+gicdev = DEVICE(s-gic);
+qdev_prop_set_uint32(gicdev, num-cpu, s-num_cpu);
+qdev_prop_set_uint32(gicdev, num-irq, s-num_irq);
+qdev_init_nofail(gicdev);
+busdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
sysbus_pass_irq(dev, busdev);
--
1.8.1.4
[Qemu-devel] [PATCH RFC 05/15] cpu/a9mpcore: Embed A9SCUState
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 23 ++-
hw/misc/a9scu.c | 18 +-
include/hw/misc/a9scu.h | 31 +++
3 files changed, 46 insertions(+), 26 deletions(-)
create mode 100644 include/hw/misc/a9scu.h
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 6340b0f..b7148fa 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -10,6 +10,7 @@
#include hw/sysbus.h
#include hw/intc/gic_internal.h
+#include hw/misc/a9scu.h
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -24,10 +25,10 @@ typedef struct A9MPPrivState {
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdt;
-DeviceState *scu;
uint32_t num_irq;
GICState gic;
+A9SCUState scu;
} A9MPPrivState;
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
@@ -39,6 +40,7 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int
level)
static void a9mp_priv_initfn(Object *obj)
{
+SysBusDevice *sbd;
A9MPPrivState *s = A9MPCORE_PRIV(obj);
memory_region_init(s-container, a9mp-priv-container, 0x2000);
@@ -46,13 +48,19 @@ static void a9mp_priv_initfn(Object *obj)
object_initialize(s-gic, TYPE_ARM_GIC);
qdev_set_parent_bus(DEVICE(s-gic), sysbus_get_default());
+
+object_initialize(s-scu, TYPE_A9_SCU);
+qdev_set_parent_bus(DEVICE(s-scu), sysbus_get_default());
+sbd = SYS_BUS_DEVICE(s-scu);
+memory_region_add_subregion(s-container, 0,
+sysbus_mmio_get_region(sbd, 0));
}
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = A9MPCORE_PRIV(dev);
-DeviceState *gicdev;
-SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
+DeviceState *gicdev, *scudev;
+SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev;
int i;
gicdev = DEVICE(s-gic);
@@ -67,10 +75,9 @@ static int a9mp_priv_init(SysBusDevice *dev)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s-num_irq - 32);
-s-scu = qdev_create(NULL, a9-scu);
-qdev_prop_set_uint32(s-scu, num-cpu, s-num_cpu);
-qdev_init_nofail(s-scu);
-scubusdev = SYS_BUS_DEVICE(s-scu);
+scudev = DEVICE(s-scu);
+qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
+qdev_init_nofail(scudev);
s-mptimer = qdev_create(NULL, arm_mptimer);
qdev_prop_set_uint32(s-mptimer, num-cpu, s-num_cpu);
@@ -93,8 +100,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
*
* We should implement the global timer but don't currently do so.
*/
-memory_region_add_subregion(s-container, 0,
-sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
memory_region_add_subregion(s-container, 0x100,
sysbus_mmio_get_region(gicbusdev, 1));
diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index 30f6fac..b5a6087 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -8,23 +8,7 @@
* This code is licensed under the GPL.
*/
-#include hw/sysbus.h
-
-/* A9MP private memory region. */
-
-typedef struct A9SCUState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-MemoryRegion iomem;
-uint32_t control;
-uint32_t status;
-uint32_t num_cpu;
-} A9SCUState;
-
-#define TYPE_A9_SCU a9-scu
-#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
+#include hw/misc/a9scu.h
static uint64_t a9_scu_read(void *opaque, hwaddr offset,
unsigned size)
diff --git a/include/hw/misc/a9scu.h b/include/hw/misc/a9scu.h
new file mode 100644
index 000..efb0c30
--- /dev/null
+++ b/include/hw/misc/a9scu.h
@@ -0,0 +1,31 @@
+/*
+ * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
+ *
+ * Copyright (c) 2009 CodeSourcery.
+ * Copyright (c) 2011 Linaro Limited.
+ * Written by Paul Brook, Peter Maydell.
+ *
+ * This code is licensed under the GPL.
+ */
+#ifndef HW_MISC_A9SCU_H
+#define HW_MISC_A9SCU_H
+
+#include hw/sysbus.h
+
+/* A9MP private memory region. */
+
+typedef struct A9SCUState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+MemoryRegion iomem;
+uint32_t control;
+uint32_t status;
+uint32_t num_cpu;
+} A9SCUState;
+
+#define TYPE_A9_SCU a9-scu
+#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU)
+
+#endif
--
1.8.1.4
[Qemu-devel] [PATCH RFC 12/15] cpu/a15mpcore: Split off instance_init
From: Andreas Färber andreas.faer...@web.de
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index b30fe0c..1a15bf8 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -44,6 +44,15 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int
level)
qemu_set_irq(qdev_get_gpio_in(s-gic, irq), level);
}
+static void a15mp_priv_initfn(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+A15MPPrivState *s = A15MPCORE_PRIV(obj);
+
+memory_region_init(s-container, a15mp-priv-container, 0x8000);
+sysbus_init_mmio(sbd, s-container);
+}
+
static int a15mp_priv_init(SysBusDevice *dev)
{
A15MPPrivState *s = A15MPCORE_PRIV(dev);
@@ -75,13 +84,11 @@ static int a15mp_priv_init(SysBusDevice *dev)
* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
*/
-memory_region_init(s-container, a15mp-priv-container, 0x8000);
memory_region_add_subregion(s-container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(s-container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
-sysbus_init_mmio(dev, s-container);
return 0;
}
@@ -110,6 +117,7 @@ static const TypeInfo a15mp_priv_info = {
.name = TYPE_A15MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A15MPPrivState),
+.instance_init = a15mp_priv_initfn,
.class_init = a15mp_priv_class_init,
};
--
1.8.1.4
[Qemu-devel] [PATCH RFC 11/15] cpu/a15mpcore: QOM cast cleanup
From: Andreas Färber andreas.faer...@web.de
Introduce type constant and cast macro and rename A15MPPrivState::busdev
field to parent_obj to enforce its use.
Prepares for QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 648656d..b30fe0c 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -23,8 +23,15 @@
/* A15MP private memory region. */
+#define TYPE_A15MPCORE_PRIV a15mpcore_priv
+#define A15MPCORE_PRIV(obj) \
+OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
+
typedef struct A15MPPrivState {
-SysBusDevice busdev;
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
uint32_t num_cpu;
uint32_t num_irq;
MemoryRegion container;
@@ -39,7 +46,7 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int
level)
static int a15mp_priv_init(SysBusDevice *dev)
{
-A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
+A15MPPrivState *s = A15MPCORE_PRIV(dev);
SysBusDevice *busdev;
const char *gictype = arm_gic;
@@ -58,7 +65,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
sysbus_pass_irq(dev, busdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(s-busdev.qdev, a15mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s-num_irq - 32);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x-0x0fff -- reserved
@@ -100,7 +107,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo a15mp_priv_info = {
-.name = a15mpcore_priv,
+.name = TYPE_A15MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(A15MPPrivState),
.class_init = a15mp_priv_class_init,
--
1.8.1.4
[Qemu-devel] [PATCH RFC 14/15] cpu/a15mpcore: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Turn SysBusDevice initfn into a QOM realizefn.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index ee09b57..7fd120f 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -67,8 +67,9 @@ static void a15mp_priv_initfn(Object *obj)
qdev_prop_set_uint32(gicdev, revision, 2);
}
-static int a15mp_priv_init(SysBusDevice *dev)
+static void a15mp_priv_realize(DeviceState *dev, Error **errp)
{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
DeviceState *gicdev;
SysBusDevice *busdev;
@@ -80,10 +81,10 @@ static int a15mp_priv_init(SysBusDevice *dev)
busdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
-sysbus_pass_irq(dev, busdev);
+sysbus_pass_irq(sbd, busdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(dev, a15mp_priv_set_irq, s-num_irq - 32);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x-0x0fff -- reserved
@@ -97,8 +98,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(s-container, 0x2000,
sysbus_mmio_get_region(busdev, 1));
-
-return 0;
}
static Property a15mp_priv_properties[] = {
@@ -116,8 +115,8 @@ static Property a15mp_priv_properties[] = {
static void a15mp_priv_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = a15mp_priv_init;
+
+dc-realize = a15mp_priv_realize;
dc-props = a15mp_priv_properties;
/* We currently have no savable state */
}
--
1.8.1.4
[Qemu-devel] [PATCH RFC 09/15] cpu/a9mpcore: Convert to QOM realize
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 48f5897..67ecf5d 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -73,8 +73,9 @@ static void a9mp_priv_initfn(Object *obj)
sysbus_mmio_get_region(sbd, 0));
}
-static int a9mp_priv_init(SysBusDevice *dev)
+static void a9mp_priv_realize(DeviceState *dev, Error **errp)
{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev;
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev;
@@ -87,10 +88,10 @@ static int a9mp_priv_init(SysBusDevice *dev)
gicbusdev = SYS_BUS_DEVICE(s-gic);
/* Pass through outbound IRQ lines from the GIC */
-sysbus_pass_irq(dev, gicbusdev);
+sysbus_pass_irq(sbd, gicbusdev);
/* Pass through inbound GPIO lines to the GIC */
-qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s-num_irq - 32);
+qdev_init_gpio_in(dev, a9mp_priv_set_irq, s-num_irq - 32);
scudev = DEVICE(s-scu);
qdev_prop_set_uint32(scudev, num-cpu, s-num_cpu);
@@ -133,7 +134,6 @@ static int a9mp_priv_init(SysBusDevice *dev)
sysbus_connect_irq(wdtbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 30));
}
-return 0;
}
static Property a9mp_priv_properties[] = {
@@ -151,9 +151,8 @@ static Property a9mp_priv_properties[] = {
static void a9mp_priv_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = a9mp_priv_init;
+dc-realize = a9mp_priv_realize;
dc-props = a9mp_priv_properties;
}
--
1.8.1.4
[Qemu-devel] [PATCH RFC 15/15] cpu/a15mpcore: Prepare for QOM embedding
From: Andreas Färber andreas.faer...@web.de
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a15mpcore.c | 21 +
include/hw/cpu/a15mpcore.h | 44
2 files changed, 45 insertions(+), 20 deletions(-)
create mode 100644 include/hw/cpu/a15mpcore.h
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 7fd120f..1b275b1 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -18,27 +18,8 @@
* with this program; if not, see http://www.gnu.org/licenses/.
*/
-#include hw/sysbus.h
+#include hw/cpu/a15mpcore.h
#include sysemu/kvm.h
-#include hw/intc/gic_internal.h
-
-/* A15MP private memory region. */
-
-#define TYPE_A15MPCORE_PRIV a15mpcore_priv
-#define A15MPCORE_PRIV(obj) \
-OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
-
-typedef struct A15MPPrivState {
-/* private */
-SysBusDevice parent_obj;
-/* public */
-
-uint32_t num_cpu;
-uint32_t num_irq;
-MemoryRegion container;
-
-GICState gic;
-} A15MPPrivState;
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
diff --git a/include/hw/cpu/a15mpcore.h b/include/hw/cpu/a15mpcore.h
new file mode 100644
index 000..e9e9d52
--- /dev/null
+++ b/include/hw/cpu/a15mpcore.h
@@ -0,0 +1,44 @@
+/*
+ * Cortex-A15MPCore internal peripheral emulation.
+ *
+ * Copyright (c) 2012 Linaro Limited.
+ * Written by Peter Maydell.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+#ifndef HW_CPU_A15MPCORE_H
+#define HW_CPU_A15MPCORE_H
+
+#include hw/sysbus.h
+#include hw/intc/gic_internal.h
+
+/* A15MP private memory region. */
+
+#define TYPE_A15MPCORE_PRIV a15mpcore_priv
+#define A15MPCORE_PRIV(obj) \
+OBJECT_CHECK(A15MPPrivState, (obj), TYPE_A15MPCORE_PRIV)
+
+typedef struct A15MPPrivState {
+/* private */
+SysBusDevice parent_obj;
+/* public */
+
+uint32_t num_cpu;
+uint32_t num_irq;
+MemoryRegion container;
+
+GICState gic;
+} A15MPPrivState;
+
+#endif
--
1.8.1.4
Re: [Qemu-devel] [PATCH RFC 03/15] cpu/a9mpcore: Embed GICState
On 30 June 2013 22:00, Andreas Färber afaer...@suse.de wrote:
From: Andreas Färber andreas.faer...@web.de
Prepares for conversion to QOM realize.
Signed-off-by: Andreas Färber andreas.faer...@web.de
---
hw/cpu/a9mpcore.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 63a4eb1..6340b0f 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -9,6 +9,7 @@
*/
#include hw/sysbus.h
+#include hw/intc/gic_internal.h
This doesn't look right -- the GIC internals are supposed
to be internal to the GIC implementation (and its subclasses).
They shouldn't be exposed to users. (That's why the header
is in hw/intc and not in include/.)
#define TYPE_A9MPCORE_PRIV a9mpcore_priv
#define A9MPCORE_PRIV(obj) \
@@ -23,15 +24,17 @@ typedef struct A9MPPrivState {
MemoryRegion container;
DeviceState *mptimer;
DeviceState *wdt;
-DeviceState *gic;
DeviceState *scu;
uint32_t num_irq;
+
+GICState gic;
} A9MPPrivState;
So we sort of had a discussion about this before, but I
still don't think we have a sensible way of doing
embedding of devices into container device structures
like this properly (ie without exposing implementation
internals that qdev doesn't require you to expose).
If we want to do struct-embedding then I think we should
come up with a standard way of writing that code (eg
a .h file under include/hw with type name macros and a
struct with only the public-facing bits and internal
members hidden behind a typedef somehow, and a .priv.h
in hw/whatever/ with the actual struct that the device
needs itself), and then start using that. Otherwise we
should just keep using pointers since they can happily
be opaque about the details of the struct they point to.
thanks
-- PMM
Re: [Qemu-devel] [PATCH 08/32] kvm/openpic: in-kernel mpic support
On 30.06.2013, at 08:13, Andreas Färber wrote: Am 30.06.2013 03:44, schrieb Alexander Graf: From: Scott Wood scottw...@freescale.com Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood scottw...@freescale.com [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build] Signed-off-by: Alexander Graf ag...@suse.de --- default-configs/ppc-softmmu.mak | 1 + default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/openpic_kvm.c | 252 ++ hw/ppc/e500.c | 79 +++- include/hw/ppc/openpic.h | 2 +- target-ppc/kvm-stub.c | 6 + 7 files changed, 336 insertions(+), 6 deletions(-) create mode 100644 hw/intc/openpic_kvm.c I had objected to the subject What's wrong with the subject? I don't find it misleading. I don't remember we ever had strong ruling on subject lines. In fact, I usually format mine completely differently. , and this patch is not bisectable since you didn't squash my ppcemb-softmmu build fix. Please do. Please send build fixes separately from QOM refactoring. The patch as a whole is way too big to get squashed into the original patch. I'll extract the build fix and pluck it up manually this time, but please keep things separate next time around. Alex
Re: [Qemu-devel] [PATCH 27/32] PPC: Introduce an alias cache for faster lookups
On 30.06.2013, at 08:25, Andreas Färber wrote:
Am 30.06.2013 03:45, schrieb Alexander Graf:
When running QEMU with -cpu ? we walk through every alias for every
target CPU we know about. This takes several seconds on my very fast
host system.
Let's introduce a class object cache in the alias table. Using that we
don't have to go through the tedious work of finding our target class.
Instead, we can just go directly from the alias name to the target class
pointer.
This patch brings -cpu ? to reasonable times again.
Before:
real0m4.716s
After:
real0m0.025s
Signed-off-by: Alexander Graf ag...@suse.de
I had objected to this patch being not the right solution to the problem.
Not on the mailing list FWIW. It's a real solution to a real problem. Just
revert it when the final all-surpassing solution comes along. Until then, at
least -cpu ? works fast.
---
target-ppc/cpu-models.c | 2 +-
target-ppc/cpu-models.h | 3 ++-
target-ppc/translate_init.c | 32 +++-
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 17f56b7..9bb68c8 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1227,7 +1227,7 @@
/***/
/* PowerPC CPU aliases */
-const PowerPCCPUAlias ppc_cpu_aliases[] = {
+PowerPCCPUAlias ppc_cpu_aliases[] = {
{ 403, 403GC },
{ 405, 405D4 },
{ 405CR, 405CRc },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index a94f835..262ca47 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -31,9 +31,10 @@
typedef struct PowerPCCPUAlias {
const char *alias;
const char *model;
+ObjectClass *klass;
And please don't spread this deliberate misspelling. When I did, I was
flamed and the solution was to use oc for ObjectClass, cc for CPUClass,
etc.
ok, s/klass/oc/g then.
Your patch still keeps traversing the class list with O(n).
So?
} PowerPCCPUAlias;
-extern const PowerPCCPUAlias ppc_cpu_aliases[];
+extern PowerPCCPUAlias ppc_cpu_aliases[];
/*/
/* PVR definitions for most known PowerPC
*/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f01e9e7..45b4053 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7934,6 +7934,28 @@ static gint ppc_cpu_compare_class_name(gconstpointer
a, gconstpointer b)
#include ctype.h
+static ObjectClass *ppc_cpu_class_by_name(const char *name);
+
+static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
+{
+ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
+
+/* Cache target class lookups in the alias table */
+if (!alias-klass) {
+alias-klass = ppc_cpu_class_by_name(alias-model);
+if (!alias-klass) {
+/* Fast check for non-existing aliases */
+alias-klass = invalid_class;
+}
+}
+
+if (alias-klass == invalid_class) {
+return NULL;
+} else {
+return alias-klass;
+}
+}
Instead of saving bogus values with meaning no class we should drop
the ifdef'fery and make all types available. Our plan was to add one or
more flags to PowerPCCPUClass.
I'm not sure I really want those types there already. There's some serious
further refactoring in the CPU initialization code needed to group common
registration between different CPUs together. Things are way too much
copypaste today still.
Alex
Re: [Qemu-devel] [Qemu-ppc] [PULL 00/32] ppc patch queue 2013-06-30
On 30.06.2013, at 03:44, Alexander Graf wrote: Hi Blue / Aurelien, This is my current patch queue for ppc. Please pull. I've squashed the build fix into the openpic-kvm patch and renamed the klass variable to oc. Both changes are active in the very same branch mentioned below. I don't want to spam the list by resending a full pull request again. Please just consider this email as a renewed request. Alex Alex The following changes since commit ffeec223b55ea696567ed544016824199cd7c7bc: Merge remote-tracking branch 'mjt/trivial-patches' into staging (2013-06-28 15:48:35 -0500) are available in the git repository at: git://github.com/agraf/qemu.git ppc-for-upstream for you to fetch changes up to 0b4f507cd58c554f3bd8c5f4d7ad34cd1d863532: PPC: Ignore writes to L2CR (2013-06-30 03:43:40 +0200) Alexander Graf (12): KVM: Don't assume that mpstate exists with in-kernel PIC always KVM: Export kvm_init_irq_routing KVM: MSI: Swap payload to native endianness KVM: PIC: Only commit irq routing when necessary PPC: Add non-kvm stub file Graphics: Switch to 800x600x32 as default mode PPC: Introduce an alias cache for faster lookups PPC: Add clock-frequency export for Mac machines PPC: Newworld: Add uninorth token register PPC: Newworld: Add second uninorth control register set mac-io: Add escc-legacy memory alias region PPC: Ignore writes to L2CR Alexey Kardashevskiy (1): target-ppc kvm: save cr register Andreas Färber (8): intc/openpic: QOM'ify intc/openpic: Convert to QOM realize intc/openpic_kvm: Fix QOM and build issues mpc8544_guts: Fix MemoryRegion name mpc8544_guts: QOM'ify mpc8544_guts: Turn qdev initfn into instance_init target-ppc: Drop redundant flags assignments from CPU families target-ppc: Introduce unrealizefn for PowerPCCPU Anthony Liguori (1): spapr-rtas: add CPU argument to RTAS calls Bharat Bhushan (1): booke_ppc: limit booke timer to max when timeout overflow David Gibson (2): target-ppc: Change default machine for 64-bit pseries: Update MAINTAINERS information Fabien Chouteau (2): PPC: Add dump_mmu() for 6xx PPC: Fix GDB read on code area for PPC6xx Hervé Poussineau (1): ppc: do not register IABR SPR twice for 603e Scott Wood (3): openpic: factor out some common defines into openpic.h PPC: e500: factor out mpic init code kvm/openpic: in-kernel mpic support Stefan Weil (1): pseries: Fix compiler warning (conversion of pointer to integral value) MAINTAINERS| 5 +- arch_init.c| 2 +- cpus.c | 2 +- default-configs/ppc-softmmu.mak| 1 + default-configs/ppc64-softmmu.mak | 1 + default-configs/ppcemb-softmmu.mak | 1 + hw/i386/kvm/ioapic.c | 1 + hw/intc/Makefile.objs | 1 + hw/intc/openpic.c | 89 +++-- hw/intc/openpic_kvm.c | 264 + hw/misc/macio/macio.c | 47 +++ hw/nvram/spapr_nvram.c | 4 +- hw/ppc/e500.c | 125 ++ hw/ppc/mac_newworld.c | 24 +++- hw/ppc/mac_oldworld.c | 2 + hw/ppc/mpc8544_guts.c | 32 ++--- hw/ppc/ppc_booke.c | 24 +++- hw/ppc/spapr.c | 3 +- hw/ppc/spapr_events.c | 2 +- hw/ppc/spapr_hcall.c | 2 +- hw/ppc/spapr_pci.c | 13 +- hw/ppc/spapr_rtas.c| 21 +-- hw/ppc/spapr_vio.c | 6 +- hw/ppc/xics.c | 12 +- include/hw/ppc/openpic.h | 14 ++ include/hw/ppc/ppc.h | 1 + include/hw/ppc/spapr.h | 5 +- include/sysemu/kvm.h | 12 ++ kvm-all.c | 22 ++-- kvm-stub.c | 4 + target-ppc/Makefile.objs | 1 + target-ppc/cpu-models.c| 2 +- target-ppc/cpu-models.h| 3 +- target-ppc/cpu.h | 4 +- target-ppc/kvm-stub.c | 18 +++ target-ppc/kvm.c | 5 + target-ppc/mmu_helper.c| 102 +- target-ppc/translate_init.c| 120 - 38 files changed, 792 insertions(+), 205 deletions(-) create mode 100644 hw/intc/openpic_kvm.c create mode 100644 target-ppc/kvm-stub.c
Re: [Qemu-devel] [PATCH 08/32] kvm/openpic: in-kernel mpic support
Am 01.07.2013 01:01, schrieb Alexander Graf: On 30.06.2013, at 08:13, Andreas Färber wrote: Am 30.06.2013 03:44, schrieb Alexander Graf: From: Scott Wood scottw...@freescale.com Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood scottw...@freescale.com [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build] Signed-off-by: Alexander Graf ag...@suse.de --- default-configs/ppc-softmmu.mak | 1 + default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/openpic_kvm.c | 252 ++ hw/ppc/e500.c | 79 +++- include/hw/ppc/openpic.h | 2 +- target-ppc/kvm-stub.c | 6 + 7 files changed, 336 insertions(+), 6 deletions(-) create mode 100644 hw/intc/openpic_kvm.c I had objected to the subject What's wrong with the subject? I don't find it misleading. I don't remember we ever had strong ruling on subject lines. In fact, I usually format mine completely differently. ...and I have complained about that often enough, which you are ignoring. , and this patch is not bisectable since you didn't squash my ppcemb-softmmu build fix. Please do. Please send build fixes separately from QOM refactoring. The patch as a whole is way too big to get squashed into the original patch. I'll extract the build fix and pluck it up manually this time, but please keep things separate next time around. No, this was not a refactoring of in-tree code, it was a fixup that Scott should have done. Next time review and test properly, then it wouldn't have made it into your tree in the first place and I wouldn't have needed to make my hands dirty with that crap. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH 02/15] PPC: g3beige: Move secondary IDE bus to mac-io
On 30.06.2013, at 08:33, Andreas Färber wrote:
Am 30.06.2013 03:26, schrieb Alexander Graf:
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- fix IRQ mapping
---
hw/ide/macio.c| 2 +-
hw/misc/macio/macio.c | 95
+--
hw/ppc/mac_oldworld.c | 17 +
3 files changed, 64 insertions(+), 50 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a1952b0..7a1c573 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -363,7 +363,7 @@ static void macio_ide_register_types(void)
type_register_static(macio_ide_type_info);
}
-/* hd_table must contain 4 block drivers */
+/* hd_table must contain 2 block drivers */
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
{
int i;
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index fd4c8e5..d9971e2 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -51,11 +51,9 @@ typedef struct OldWorldMacIOState {
/* private */
MacIOState parent_obj;
/* public */
-
-qemu_irq irqs[3];
-
+qemu_irq irqs[5];
MacIONVRAMState nvram;
-MACIOIDEState ide;
+MACIOIDEState ide[2];
} OldWorldMacIOState;
I had asked you to please keep my spacing: It separates parent field,
local fields (IRQs) and child fields.
Ok, fixed. If it's so dear to you, please send a follow-up patch fixing struct
NewWorldMacIOState then.
#define NEWWORLD_MACIO(obj) \
@@ -147,18 +145,32 @@ static int macio_common_initfn(PCIDevice *d)
return 0;
}
+static int macio_initfn_ide(MacIOState *s, MACIOIDEState *ide, qemu_irq
irq0,
+qemu_irq irq1, int dmaid)
macio_realize_ide would be a better name since PCIDevices still use
their legacy initfn.
I've tried to keep the naming consistent. macio_initfn_ide gets called from
macio_oldworld_initfn and macio_newworld_initfn. I'd find a sudden naming
switch to realize utterly confusing.
Alex
Otherwise looks good.
Andreas
+{
+SysBusDevice *sysbus_dev;
+
+sysbus_dev = SYS_BUS_DEVICE(ide);
+sysbus_connect_irq(sysbus_dev, 0, irq0);
+sysbus_connect_irq(sysbus_dev, 1, irq1);
+macio_ide_register_dma(ide, s-dbdma, dmaid);
+return qdev_init(DEVICE(ide));
+}
+
static int macio_oldworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+int i;
+int cur_irq = 0;
int ret = macio_common_initfn(d);
if (ret 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(s-cuda);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[0]);
+sysbus_connect_irq(sysbus_dev, 0, os-irqs[cur_irq++]);
ret = qdev_init(DEVICE(os-nvram));
if (ret 0) {
@@ -174,23 +186,39 @@ static int macio_oldworld_initfn(PCIDevice *d)
memory_region_add_subregion(s-bar, 0x0, s-pic_mem);
}
-sysbus_dev = SYS_BUS_DEVICE(os-ide);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[1]);
-sysbus_connect_irq(sysbus_dev, 1, os-irqs[2]);
-macio_ide_register_dma(os-ide, s-dbdma, 0x16);
-ret = qdev_init(DEVICE(os-ide));
-if (ret 0) {
-return ret;
+/* IDE buses */
+for (i = 0; i ARRAY_SIZE(os-ide); i++) {
+qemu_irq irq0 = os-irqs[cur_irq++];
+qemu_irq irq1 = os-irqs[cur_irq++];
+
+ret = macio_initfn_ide(s, os-ide[i], irq0, irq1, 0x16 + (i * 4));
+if (ret 0) {
+return ret;
+}
}
return 0;
}
+static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
+{
+gchar *name;
+
+object_initialize(ide, TYPE_MACIO_IDE);
+qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
+memory_region_add_subregion(s-bar, 0x1f000 + ((index + 1) * 0x1000),
+ide-mem);
+name = g_strdup_printf(ide[%i], index);
+object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
+g_free(name);
+}
+
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
+int i;
qdev_init_gpio_out(DEVICE(obj), os-irqs, ARRAY_SIZE(os-irqs));
@@ -199,10 +227,9 @@ static void macio_oldworld_init(Object *obj)
qdev_prop_set_uint32(dev, size, 0x2000);
qdev_prop_set_uint32(dev, it_shift, 4);
-object_initialize(os-ide, TYPE_MACIO_IDE);
-qdev_set_parent_bus(DEVICE(os-ide), sysbus_get_default());
-memory_region_add_subregion(s-bar, 0x1f000 + (1 * 0x1000),
os-ide.mem);
-object_property_add_child(obj, ide, OBJECT(os-ide), NULL);
+for (i = 0; i 2; i++) {
+macio_init_ide(s, os-ide[i], i);
+}
}
Re: [Qemu-devel] [PATCH 05/15] PPC: Mac: Add debug prints in macio and dbdma code
On 30.06.2013, at 08:42, Andreas Färber wrote:
Am 30.06.2013 03:26, schrieb Alexander Graf:
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disabled by default of course.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/macio.c| 39 ++-
hw/misc/macio/mac_dbdma.c | 12 ++--
2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 82409dc..5cbc923 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -30,6 +30,17 @@
#include hw/ide/internal.h
+/* debug MACIO */
+// #define DEBUG_MACIO
+
+#ifdef DEBUG_MACIO
+#define MACIO_DPRINTF(fmt, ...) \
+do { printf(MACIO: %s: fmt , __func__, ## __VA_ARGS__); } while (0)
+#else
+#define MACIO_DPRINTF(fmt, ...)
+#endif
Please use the pattern you suggested yourself of having an if
(DEBUG_MACIO_ENABLED) {...} inside the macro rather than a second
MACIO_DPRINTF(), so that the newly added debug output doesn'T bitrot.
Very good point. Thanks a lot!
+
+
/***/
/* MacIO based PowerPC IDE */
@@ -48,6 +59,8 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
goto done;
}
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
+
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -59,15 +72,22 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
s-io_buffer_index = 0x7ff;
}
-if (s-packet_transfer_size = 0)
+/* end of transfer ? */
+if (s-packet_transfer_size = 0) {
+MACIO_DPRINTF(end of transfer\n);
ide_atapi_cmd_ok(s);
+}
+/* end of DMA ? */
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
Both comments duplicate your debug output module question mark. :)
Yeah, I've just synced the comments between ATAPI and ATA here. But you're
right - I should just remove them altogether.
/* launch next transfer */
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
s-io_buffer_size = io-len;
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
@@ -76,12 +96,17 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=%d size=%d, cmd_cmd=%d\n,
+ (s-lba 2) + (s-io_buffer_index 9),
+ s-packet_transfer_size, s-dma_cmd);
+
m-aiocb = dma_bdrv_read(s-bs, s-sg,
(int64_t)(s-lba 2) + (s-io_buffer_index
9),
pmac_ide_atapi_transfer_cb, io);
return;
done:
+MACIO_DPRINTF(done DMA\n);
bdrv_acct_done(s-bs, s-acct);
io-dma_end(opaque);
}
@@ -95,6 +120,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
int64_t sector_num;
if (ret 0) {
+MACIO_DPRINTF(DMA error\n);
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
ide_dma_error(s);
@@ -102,6 +128,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
}
sector_num = ide_get_sector(s);
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -113,12 +140,14 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
/* end of transfer ? */
if (s-nsector == 0) {
+MACIO_DPRINTF(end of transfer\n);
s-status = READY_STAT | SEEK_STAT;
ide_set_irq(s-bus);
}
/* end of DMA ? */
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
@@ -127,12 +156,18 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
s-io_buffer_index = 0;
s-io_buffer_size = io-len;
+
Intentionally two white lines?
Nope, I'm sure that gets resolved somewhere later in the patch series. But I'll
fix it up here too ;).
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
address_space_memory);
qemu_sglist_add(s-sg, io-addr, io-len);
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=% PRId64 n=%d, nsector=%d, cmd_cmd=%d\n,
+ sector_num, n, s-nsector, s-dma_cmd);
+
switch (s-dma_cmd) {
case IDE_DMA_READ:
m-aiocb = dma_bdrv_read(s-bs, s-sg, sector_num,
@@ -162,6 +197,8 @@ static void pmac_ide_transfer(DBDMA_io *io)
MACIOIDEState *m = io-opaque;
IDEState *s = idebus_active_if(m-bus);
+MACIO_DPRINTF(\n, __LINE__);
The argument is unused.
which
Re: [Qemu-devel] [PATCH 12/15] PPC: dbdma: Move processing to io
On 30.06.2013, at 08:48, Andreas Färber wrote:
Am 30.06.2013 03:27, schrieb Alexander Graf:
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 10 ++
include/hw/ppc/mac_dbdma.h | 3 ++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 324ac54..91b9eaf 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -275,7 +275,9 @@ static void dbdma_end(DBDMA_io *io)
conditional_branch(ch);
wait:
-ch-processing = 0;
+/* Indicate that we're ready for a new DMA round */
+ch-io.processing = 0;
+
if ((ch-regs[DBDMA_STATUS] RUN)
(ch-regs[DBDMA_STATUS] ACTIVE))
channel_run(ch);
@@ -301,7 +303,7 @@ static void start_output(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 1;
-ch-processing = 1;
+ch-io.processing = 1;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -327,7 +329,7 @@ static void start_input(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 0;
-ch-processing = 1;
+ch-io.processing = 1;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -525,7 +527,7 @@ static void DBDMA_run(DBDMAState *s)
for (channel = 0; channel DBDMA_CHANNELS; channel++) {
DBDMA_channel *ch = s-channels[channel];
uint32_t status = ch-regs[DBDMA_STATUS];
-if (!ch-processing (status RUN) (status ACTIVE)) {
+if (!ch-io.processing (status RUN) (status ACTIVE)) {
channel_run(ch);
}
}
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index eb8e0f0..8ad1b6e 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -37,6 +37,8 @@ struct DBDMA_io {
int is_last;
int is_dma_out;
DBDMA_end dma_end;
+/* DMA is in progress, don't start another one */
+int processing;
Can it be changed to bool (its users to true/false) while at it?
Sure!
Alex
Re: [Qemu-devel] [PATCH v2 08/30] ide/ich: QOM Upcast Sweep
On 30.06.2013, at 10:21, Andreas Färber wrote:
Am 24.06.2013 08:55, schrieb peter.crosthwa...@xilinx.com:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define and use standard QOM cast macro. Remove usages of DO_UPCAST
and direct - style upcasting.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/ide/ahci.h | 5 +
hw/ide/ich.c | 10 +-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 341a571..916bef0 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -305,6 +305,11 @@ typedef struct AHCIPCIState {
AHCIState ahci;
} AHCIPCIState;
+#define TYPE_ICH_AHCI ich9-ahci
Let's be as precise as for the LSI SCSI HBA and name this ICH9. :)
No, please. ICH9 is a controller hub. This device really is only about the AHCI
part of it.
+
+#define ICH_AHCI(obj) \
+OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH_AHCI)
Wondering if this is specific to ICH(9)? Alex?
Leaving it as is for now, renaming is an easy follow-up.
This is not an ICH9 device. It's an ICH9-AHCI device. And for that the check
looks sane from what I can tell.
Alex
+
extern const VMStateDescription vmstate_ahci;
#define VMSTATE_AHCI(_field, _state) { \
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 6c0c0c2..c3cbf2a 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -92,7 +92,7 @@ static const VMStateDescription vmstate_ich9_ahci = {
static void pci_ich9_reset(DeviceState *dev)
{
-struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev);
+struct AHCIPCIState *d = ICH_AHCI(dev);
Let's drop the struct while touching the line.
Thanks, applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next
Andreas
ahci_reset(d-ahci);
}
@@ -102,9 +102,9 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
int sata_cap_offset;
uint8_t *sata_cap;
-d = DO_UPCAST(struct AHCIPCIState, card, dev);
+d = ICH_AHCI(dev);
-ahci_init(d-ahci, dev-qdev, pci_get_address_space(dev), 6);
+ahci_init(d-ahci, DEVICE(dev), pci_get_address_space(dev), 6);
pci_config_set_prog_interface(d-card.config, AHCI_PROGMODE_MAJOR_REV_1);
@@ -141,7 +141,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
static void pci_ich9_uninit(PCIDevice *dev)
{
struct AHCIPCIState *d;
-d = DO_UPCAST(struct AHCIPCIState, card, dev);
+d = ICH_AHCI(dev);
msi_uninit(dev);
ahci_uninit(d-ahci);
@@ -163,7 +163,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo ich_ahci_info = {
-.name = ich9-ahci,
+.name = TYPE_ICH_AHCI,
.parent= TYPE_PCI_DEVICE,
.instance_size = sizeof(AHCIPCIState),
.class_init= ich_ahci_class_init,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] target-mips: fix mipsdsp_trunc16_sat16_round
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson [r...@twiddle.net] Sent: Friday, June 28, 2013 7:40 PM To: Petar Jovanovic Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net Subject: Re: [Qemu-devel] [PATCH] target-mips: fix mipsdsp_trunc16_sat16_round On 06/27/2013 02:48 PM, Petar Jovanovic wrote: This doesn't look right either, as it doesn't properly check for overflow of negative values. What overflow of negative values? Can you please list the values for which the result would not be correct? Hmm, I suppose since we're always rounding to +INF, we can't overflow in the negative direction. The patch could use some commentary along those lines... r~ Ok, I will add comments in the code and resubmit the patch. Petar
[Qemu-devel] [PATCH v2] target-mips: fix mipsdsp_trunc16_sat16_round
From: Petar Jovanovic petar.jovano...@imgtec.com
This change corrects rounding and saturation of Q31 fractional value in
mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the
corner case for PRECRQ_RS.PH, and this test case is also part of the change.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
v2:
- added comments to the code
target-mips/dsp_helper.c | 16 +++-
tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c | 24
2 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 4116de9..85950b3 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -648,16 +648,22 @@ static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t
a, uint16_t b,
static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
CPUMIPSState *env)
{
-int64_t temp;
+uint16_t temp;
-temp = (int32_t)a + 0x8000;
-if (a (int)0x7fff8000) {
-temp = 0x7FFF;
+/*
+ * The value 0x8000 will be added to the input Q31 value, and the code
+ * needs to check if the addition causes an overflow. Since a positive
value
+ * is added, overflow can happen in one direction only.
+ */
+if (a 0x7FFF7FFF) {
+temp = 0x7FFF;
set_DSPControl_overflow_flag(1, 22, env);
+} else {
+temp = ((a + 0x8000) 16) 0x;
}
-return (temp 16) 0x;
+return temp;
}
static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
index 3535b37..da6845b 100644
--- a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
+++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
@@ -12,18 +12,34 @@ int main()
result = 0x12348765;
__asm
-(precrq_rs.ph.w %0, %1, %2\n\t
+(wrdsp $0\n\t
+ precrq_rs.ph.w %0, %1, %2\n\t
: =r(rd)
: r(rs), r(rt)
);
assert(result == rd);
-rs = 0x7fffC678;
+rs = 0x7FFFC678;
rt = 0x865432A0;
-result = 0x7fff8654;
+result = 0x7FFF8654;
__asm
-(precrq_rs.ph.w %0, %2, %3\n\t
+(wrdsp $0\n\t
+ precrq_rs.ph.w %0, %2, %3\n\t
+ rddsp %1\n\t
+ : =r(rd), =r(dsp)
+ : r(rs), r(rt)
+);
+assert(((dsp 22) 0x01) == 1);
+assert(result == rd);
+
+rs = 0xBEEFFEED;
+rt = 0x7FFF8000;
+result = 0xBEF07FFF;
+
+__asm
+(wrdsp $0\n\t
+ precrq_rs.ph.w %0, %2, %3\n\t
rddsp %1\n\t
: =r(rd), =r(dsp)
: r(rs), r(rt)
--
1.7.9.5
[Qemu-devel] [PATCH 06/17] PPC: dbdma: Fix debug print
There was a debug print that didn't compile for me because the format and the arguments weren't in sync. Fix it up. Signed-off-by: Alexander Graf ag...@suse.de --- hw/misc/macio/mac_dbdma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index 1963b47..908a123 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -720,7 +720,8 @@ static void dbdma_write(void *opaque, hwaddr addr, DBDMA_channel *ch = s-channels[channel]; int reg = (addr - (channel DBDMA_CHANNEL_SHIFT)) 2; -DBDMA_DPRINTF(writel 0x TARGET_FMT_plx = 0x%08x\n, addr, value); +DBDMA_DPRINTF(writel 0x TARGET_FMT_plx = 0x%08PRIx64\n, + addr, value); DBDMA_DPRINTF(channel 0x%x reg 0x%x\n, (uint32_t)addr DBDMA_CHANNEL_SHIFT, reg); -- 1.8.1.4
[Qemu-devel] [PATCH 01/17] PPC: Mac: Fix guest exported tbfreq values
We can tell the guest the frequency of its time base through fwcfg.
However, we tell it a different value from the speed tb actually runs
at. Let's fix it and make the tbfreq initialization and the fwcfg exposure
use the same values.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ppc/mac_newworld.c | 5 +++--
hw/ppc/mac_oldworld.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 3badfa3..253089a 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -71,6 +71,7 @@
#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf510
+#define TBFREQ (100UL * 1000UL * 1000UL)
/* debug UniNorth */
//#define DEBUG_UNIN
@@ -191,7 +192,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
env = cpu-env;
/* Set time-base frequency to 100 Mhz */
-cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_core99_reset, cpu);
}
@@ -460,7 +461,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
} else {
-fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
+fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ);
}
/* Mac OS X requires a known good clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 26600);
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 8faff30..2aab54c 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -45,6 +45,7 @@
#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf510
+#define TBFREQ 1660UL
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
@@ -114,7 +115,7 @@ static void ppc_heathrow_init(QEMUMachineInitArgs *args)
env = cpu-env;
/* Set time-base frequency to 16.6 Mhz */
-cpu_ppc_tb_init(env, 1660UL);
+cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_heathrow_reset, cpu);
}
@@ -331,7 +332,7 @@ static void ppc_heathrow_init(QEMUMachineInitArgs *args)
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
} else {
-fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
+fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ);
}
/* Mac OS X requires a known good clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 26600);
--
1.8.1.4
[Qemu-devel] [PATCH 00/17] PPC: Mac OS X guest bringup v2
Recently there has been a lot of progress on the OpenBIOS side to get Mac OS X to boot. For a while now it seemed there was only very little to make it a fully working guest os in QEMU. This patch set is the result of this. With this I can successfully boot Mac OS X 10.2 to 10.4 with the g3beige machine all the way to the GUI. I was not able to boot 10.0 or 10.1, both of which crashed in interrupt controller registration. 10.5 does not include drivers for g3beige anymore. Everything as of 10.6 is x86 only. The mac99 target doesn't look quite as good, but also very close. FWIW only minor issues in our NVRAM layout keep us from using that one. 10.4 already boots for me. Please don't try to run this with KVM yet. Mac OS X uses mixed mode (half real, half paged) extensively, which happens to break badly in KVM. For reference, here are a few pictures: https://dl.dropboxusercontent.com/u/8976842/Screen%20Shot%202013-06-29%20at%2021.25.38.png https://dl.dropboxusercontent.com/u/8976842/Screen%20Shot%202013-06-29%20at%2005.21.03.png If you want to try this out, please apply the patches on top of my ppc-next queue. Or just use this git repo: git://github.com/agraf/qemu.git macos-v2 Enjoy! Alex v1 - v2: - fix spaces - use non-bitrotting DPRINTF for macio - clean up - fix dprintf - make processing a bool Alexander Graf (17): PPC: Mac: Fix guest exported tbfreq values PPC: g3beige: Move secondary IDE bus to mac-io PPC: Macio: Replace tabs with spaces PPC: dbdma: Replace tabs with spaces PPC: Mac: Add debug prints in macio and dbdma code PPC: dbdma: Fix debug print PPC: dbdma: Allow new commands in RUN state PPC: dbdma: Move defines into header file PPC: dbdma: Introduce kick function PPC: dbdma: Move static bh variable to device struct PPC: dbdma: macio: Add DMA callback PPC: dbdma: Move processing to io PPC: dbdma: Wait for DMA until we have data PPC: dbdma: Support unaligned DMA access PPC: Add timer handler for newworld mac-io PPC: Update PPC OpenBIOS PPC: dbdma: Support more multi-issue DMA requests hw/ide/macio.c | 239 ++--- hw/misc/macio/mac_dbdma.c | 193 ++-- hw/misc/macio/macio.c | 125 +--- hw/ppc/mac.h | 3 + hw/ppc/mac_newworld.c | 5 +- hw/ppc/mac_oldworld.c | 22 ++--- include/hw/ppc/mac_dbdma.h | 124 +++ pc-bios/openbios-ppc | Bin 733972 - 1358022 bytes 8 files changed, 502 insertions(+), 209 deletions(-) -- 1.8.1.4
[Qemu-devel] [PATCH 02/17] PPC: g3beige: Move secondary IDE bus to mac-io
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- fix spaces
---
hw/ide/macio.c| 2 +-
hw/misc/macio/macio.c | 93 ++-
hw/ppc/mac_oldworld.c | 17 +-
3 files changed, 64 insertions(+), 48 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a1952b0..7a1c573 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -363,7 +363,7 @@ static void macio_ide_register_types(void)
type_register_static(macio_ide_type_info);
}
-/* hd_table must contain 4 block drivers */
+/* hd_table must contain 2 block drivers */
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
{
int i;
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index fd4c8e5..548fea6 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -52,10 +52,10 @@ typedef struct OldWorldMacIOState {
MacIOState parent_obj;
/* public */
-qemu_irq irqs[3];
+qemu_irq irqs[5];
MacIONVRAMState nvram;
-MACIOIDEState ide;
+MACIOIDEState ide[2];
} OldWorldMacIOState;
#define NEWWORLD_MACIO(obj) \
@@ -147,18 +147,32 @@ static int macio_common_initfn(PCIDevice *d)
return 0;
}
+static int macio_initfn_ide(MacIOState *s, MACIOIDEState *ide, qemu_irq irq0,
+qemu_irq irq1, int dmaid)
+{
+SysBusDevice *sysbus_dev;
+
+sysbus_dev = SYS_BUS_DEVICE(ide);
+sysbus_connect_irq(sysbus_dev, 0, irq0);
+sysbus_connect_irq(sysbus_dev, 1, irq1);
+macio_ide_register_dma(ide, s-dbdma, dmaid);
+return qdev_init(DEVICE(ide));
+}
+
static int macio_oldworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+int i;
+int cur_irq = 0;
int ret = macio_common_initfn(d);
if (ret 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(s-cuda);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[0]);
+sysbus_connect_irq(sysbus_dev, 0, os-irqs[cur_irq++]);
ret = qdev_init(DEVICE(os-nvram));
if (ret 0) {
@@ -174,23 +188,39 @@ static int macio_oldworld_initfn(PCIDevice *d)
memory_region_add_subregion(s-bar, 0x0, s-pic_mem);
}
-sysbus_dev = SYS_BUS_DEVICE(os-ide);
-sysbus_connect_irq(sysbus_dev, 0, os-irqs[1]);
-sysbus_connect_irq(sysbus_dev, 1, os-irqs[2]);
-macio_ide_register_dma(os-ide, s-dbdma, 0x16);
-ret = qdev_init(DEVICE(os-ide));
-if (ret 0) {
-return ret;
+/* IDE buses */
+for (i = 0; i ARRAY_SIZE(os-ide); i++) {
+qemu_irq irq0 = os-irqs[cur_irq++];
+qemu_irq irq1 = os-irqs[cur_irq++];
+
+ret = macio_initfn_ide(s, os-ide[i], irq0, irq1, 0x16 + (i * 4));
+if (ret 0) {
+return ret;
+}
}
return 0;
}
+static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
+{
+gchar *name;
+
+object_initialize(ide, TYPE_MACIO_IDE);
+qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
+memory_region_add_subregion(s-bar, 0x1f000 + ((index + 1) * 0x1000),
+ide-mem);
+name = g_strdup_printf(ide[%i], index);
+object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
+g_free(name);
+}
+
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
+int i;
qdev_init_gpio_out(DEVICE(obj), os-irqs, ARRAY_SIZE(os-irqs));
@@ -199,10 +229,9 @@ static void macio_oldworld_init(Object *obj)
qdev_prop_set_uint32(dev, size, 0x2000);
qdev_prop_set_uint32(dev, it_shift, 4);
-object_initialize(os-ide, TYPE_MACIO_IDE);
-qdev_set_parent_bus(DEVICE(os-ide), sysbus_get_default());
-memory_region_add_subregion(s-bar, 0x1f000 + (1 * 0x1000), os-ide.mem);
-object_property_add_child(obj, ide, OBJECT(os-ide), NULL);
+for (i = 0; i 2; i++) {
+macio_init_ide(s, os-ide[i], i);
+}
}
static int macio_newworld_initfn(PCIDevice *d)
@@ -210,35 +239,30 @@ static int macio_newworld_initfn(PCIDevice *d)
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+int i;
+int cur_irq = 0;
int ret = macio_common_initfn(d);
if (ret 0) {
return ret;
}
sysbus_dev = SYS_BUS_DEVICE(s-cuda);
-sysbus_connect_irq(sysbus_dev, 0, ns-irqs[0]);
+sysbus_connect_irq(sysbus_dev, 0, ns-irqs[cur_irq++]);
if (s-pic_mem) {
/* OpenPIC */
memory_region_add_subregion(s-bar, 0x4, s-pic_mem);
}
-sysbus_dev = SYS_BUS_DEVICE(ns-ide[0]);
-sysbus_connect_irq(sysbus_dev, 0, ns-irqs[1]);
-sysbus_connect_irq(sysbus_dev, 1,
[Qemu-devel] [PATCH 03/17] PPC: Macio: Replace tabs with spaces
s/^I//g on the file.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/macio.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 7a1c573..82409dc 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -55,7 +55,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
s-packet_transfer_size -= s-io_buffer_size;
s-io_buffer_index += s-io_buffer_size;
- s-lba += s-io_buffer_index 11;
+s-lba += s-io_buffer_index 11;
s-io_buffer_index = 0x7ff;
}
@@ -97,7 +97,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
if (ret 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
- ide_dma_error(s);
+ide_dma_error(s);
goto done;
}
@@ -136,11 +136,11 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
switch (s-dma_cmd) {
case IDE_DMA_READ:
m-aiocb = dma_bdrv_read(s-bs, s-sg, sector_num,
-pmac_ide_transfer_cb, io);
+ pmac_ide_transfer_cb, io);
break;
case IDE_DMA_WRITE:
m-aiocb = dma_bdrv_write(s-bs, s-sg, sector_num,
- pmac_ide_transfer_cb, io);
+ pmac_ide_transfer_cb, io);
break;
case IDE_DMA_TRIM:
m-aiocb = dma_bdrv_io(s-bs, s-sg, sector_num,
--
1.8.1.4
[Qemu-devel] [PATCH 07/17] PPC: dbdma: Allow new commands in RUN state
The DBDMA controller can not change its command stream while it's
actively streaming data, true. But the fact that it's in RUN state
doesn't actually indicate anything. It could just as well be in
WAIT while in RUN. And then it's legal to change commands.
This fixes a real world issue I've encountered with Mac OS X.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 908a123..ab32957 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -725,11 +725,11 @@ static void dbdma_write(void *opaque, hwaddr addr,
DBDMA_DPRINTF(channel 0x%x reg 0x%x\n,
(uint32_t)addr DBDMA_CHANNEL_SHIFT, reg);
-/* cmdptr cannot be modified if channel is RUN or ACTIVE */
+/* cmdptr cannot be modified if channel is ACTIVE */
-if (reg == DBDMA_CMDPTR_LO
-(ch-regs[DBDMA_STATUS] (RUN | ACTIVE)))
+if (reg == DBDMA_CMDPTR_LO (ch-regs[DBDMA_STATUS] ACTIVE)) {
return;
+}
ch-regs[reg] = value;
--
1.8.1.4
[Qemu-devel] [PATCH 05/17] PPC: Mac: Add debug prints in macio and dbdma code
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disabled by default of course.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- use non-bitrotting DPRINTF for macio
- clean up
---
hw/ide/macio.c| 43 ---
hw/misc/macio/mac_dbdma.c | 14 +++---
2 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 82409dc..fceadfe 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -30,6 +30,22 @@
#include hw/ide/internal.h
+/* debug MACIO */
+// #define DEBUG_MACIO
+
+#ifdef DEBUG_MACIO
+static const int debug_macio = 1;
+#else
+static const int debug_macio = 0;
+#endif
+
+#define MACIO_DPRINTF(fmt, ...) do { \
+if (debug_macio) { \
+printf(fmt , ## __VA_ARGS__); \
+} \
+} while (0)
+
+
/***/
/* MacIO based PowerPC IDE */
@@ -48,6 +64,8 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
goto done;
}
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
+
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -59,15 +77,20 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
s-io_buffer_index = 0x7ff;
}
-if (s-packet_transfer_size = 0)
+if (s-packet_transfer_size = 0) {
+MACIO_DPRINTF(end of transfer\n);
ide_atapi_cmd_ok(s);
+}
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
/* launch next transfer */
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
s-io_buffer_size = io-len;
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
@@ -76,12 +99,17 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=%d size=%d, cmd_cmd=%d\n,
+ (s-lba 2) + (s-io_buffer_index 9),
+ s-packet_transfer_size, s-dma_cmd);
+
m-aiocb = dma_bdrv_read(s-bs, s-sg,
(int64_t)(s-lba 2) + (s-io_buffer_index
9),
pmac_ide_atapi_transfer_cb, io);
return;
done:
+MACIO_DPRINTF(done DMA\n);
bdrv_acct_done(s-bs, s-acct);
io-dma_end(opaque);
}
@@ -95,6 +123,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
int64_t sector_num;
if (ret 0) {
+MACIO_DPRINTF(DMA error\n);
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
ide_dma_error(s);
@@ -102,6 +131,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
}
sector_num = ide_get_sector(s);
+MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
if (s-io_buffer_size 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
@@ -111,14 +141,14 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
s-nsector -= n;
}
-/* end of transfer ? */
if (s-nsector == 0) {
+MACIO_DPRINTF(end of transfer\n);
s-status = READY_STAT | SEEK_STAT;
ide_set_irq(s-bus);
}
-/* end of DMA ? */
if (io-len == 0) {
+MACIO_DPRINTF(end of DMA\n);
goto done;
}
@@ -127,12 +157,17 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
s-io_buffer_index = 0;
s-io_buffer_size = io-len;
+MACIO_DPRINTF(io-len = %#x\n, io-len);
+
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
address_space_memory);
qemu_sglist_add(s-sg, io-addr, io-len);
io-addr += io-len;
io-len = 0;
+MACIO_DPRINTF(sector_num=% PRId64 n=%d, nsector=%d, cmd_cmd=%d\n,
+ sector_num, n, s-nsector, s-dma_cmd);
+
switch (s-dma_cmd) {
case IDE_DMA_READ:
m-aiocb = dma_bdrv_read(s-bs, s-sg, sector_num,
@@ -162,6 +197,8 @@ static void pmac_ide_transfer(DBDMA_io *io)
MACIOIDEState *m = io-opaque;
IDEState *s = idebus_active_if(m-bus);
+MACIO_DPRINTF(\n);
+
s-io_buffer_size = 0;
if (s-drive_kind == IDE_CD) {
bdrv_acct_start(s-bs, s-acct, io-len, BDRV_ACCT_READ);
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index ab174f5..1963b47 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -224,7 +224,7 @@ static void conditional_interrupt(DBDMA_channel *ch)
uint32_t status;
int cond;
-DBDMA_DPRINTF(conditional_interrupt\n);
+DBDMA_DPRINTF(%s\n, __func__);
intr = le16_to_cpu(current-command) INTR_MASK;
@@ -233,6 +233,7 @@ static void conditional_interrupt(DBDMA_channel *ch)
return;
case INTR_ALWAYS: /* always interrupt */
[Qemu-devel] [PATCH 15/17] PPC: Add timer handler for newworld mac-io
Mac OS X accesses fancy timer registers inside of the mac-io on bootup.
These really should be ticking at the mac-io bus frequency, but I don't
see anyone upset when we just make them as fast as we want to.
With this patch on top of my previous patch queue and latest OpenBIOS
I am able to boot Mac OS X 10.4 with -M mac99.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/macio.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index 548fea6..4c872c9 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -234,11 +234,39 @@ static void macio_oldworld_init(Object *obj)
}
}
+static void timer_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+}
+
+static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
+{
+uint32_t value = 0;
+
+switch (addr) {
+case 0x38:
+value = qemu_get_clock_ns(vm_clock);
+break;
+case 0x3c:
+value = qemu_get_clock_ns(vm_clock) 32;
+break;
+}
+
+return value;
+}
+
+static const MemoryRegionOps timer_ops = {
+.read = timer_read,
+.write = timer_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static int macio_newworld_initfn(PCIDevice *d)
{
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
SysBusDevice *sysbus_dev;
+MemoryRegion *timer_memory = g_new(MemoryRegion, 1);
int i;
int cur_irq = 0;
int ret = macio_common_initfn(d);
@@ -265,6 +293,10 @@ static int macio_newworld_initfn(PCIDevice *d)
}
}
+/* Timer */
+memory_region_init_io(timer_memory, timer_ops, NULL, timer, 0x1000);
+memory_region_add_subregion(s-bar, 0x15000, timer_memory);
+
return 0;
}
--
1.8.1.4
[Qemu-devel] [PATCH 10/17] PPC: dbdma: Move static bh variable to device struct
The DBDMA controller has a bottom half to asynchronously process DMA
request queues.
This bh was stored as a gross static variable. Move it into the device
struct instead.
While at it, move all users of it to the new generic kick function.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 24 +++-
include/hw/ppc/mac_dbdma.h | 1 +
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 8434e90..95abbba 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -54,6 +54,11 @@
/*
*/
+static DBDMAState *dbdma_from_ch(DBDMA_channel *ch)
+{
+return container_of(ch, DBDMAState, channels[ch-channel]);
+}
+
#ifdef DEBUG_DBDMA
static void dump_dbdma_cmd(dbdma_cmd *cmd)
{
@@ -248,7 +253,6 @@ static void conditional_branch(DBDMA_channel *ch)
}
}
-static QEMUBH *dbdma_bh;
static void channel_run(DBDMA_channel *ch);
static void dbdma_end(DBDMA_io *io)
@@ -365,7 +369,7 @@ static void load_word(DBDMA_channel *ch, int key, uint32_t
addr,
next(ch);
wait:
-qemu_bh_schedule(dbdma_bh);
+DBDMA_kick(dbdma_from_ch(ch));
}
static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
@@ -403,7 +407,7 @@ static void store_word(DBDMA_channel *ch, int key, uint32_t
addr,
next(ch);
wait:
-qemu_bh_schedule(dbdma_bh);
+DBDMA_kick(dbdma_from_ch(ch));
}
static void nop(DBDMA_channel *ch)
@@ -420,7 +424,7 @@ static void nop(DBDMA_channel *ch)
conditional_branch(ch);
wait:
-qemu_bh_schedule(dbdma_bh);
+DBDMA_kick(dbdma_from_ch(ch));
}
static void stop(DBDMA_channel *ch)
@@ -538,7 +542,7 @@ static void DBDMA_run_bh(void *opaque)
void DBDMA_kick(DBDMAState *dbdma)
{
-qemu_bh_schedule(dbdma_bh);
+qemu_bh_schedule(dbdma-bh);
}
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
@@ -594,10 +598,12 @@ dbdma_control_write(DBDMA_channel *ch)
ch-regs[DBDMA_STATUS] = status;
-if (status ACTIVE)
-qemu_bh_schedule(dbdma_bh);
-if ((status FLUSH) ch-flush)
+if (status ACTIVE) {
+DBDMA_kick(dbdma_from_ch(ch));
+}
+if ((status FLUSH) ch-flush) {
ch-flush(ch-io);
+}
}
static void dbdma_write(void *opaque, hwaddr addr,
@@ -750,7 +756,7 @@ void* DBDMA_init (MemoryRegion **dbdma_mem)
vmstate_register(NULL, -1, vmstate_dbdma, s);
qemu_register_reset(dbdma_reset, s);
-dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
+s-bh = qemu_bh_new(DBDMA_run_bh, s);
return s;
}
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index aaeab10..eb8e0f0 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -154,6 +154,7 @@ typedef struct DBDMA_channel {
typedef struct {
MemoryRegion mem;
DBDMA_channel channels[DBDMA_CHANNELS];
+QEMUBH *bh;
} DBDMAState;
/* Externally callable functions */
--
1.8.1.4
[Qemu-devel] [PATCH 17/17] PPC: dbdma: Support more multi-issue DMA requests
A DMA request can happen for data that hasn't been completely been provided by the IDE core yet. For example - DBDMA request for 0x1000 bytes - IDE request for 1 sector - DBDMA wants to read 0x1000 bytes (8 sectors) from bdrv - breakage Instead, we should truncate our bdrv request to the maximum number of sectors we're allowed to read at that given time. Once that transfer is through, we will fall into our recently introduced waiting logic. - DBDMA requests for 0x1000 bytes - IDE request for 1 sector - DBDMA wants to read MIN(0x1000, 1 * 512) bytes - DBDMA finishes reading, indicates to IDE core that transfer is complete - IDE request for 7 sectors - DBDMA finishes the DMA Reported-by: Mark Cave-Ayland mark.cave-ayl...@ilande.co.uk Signed-off-by: Alexander Graf ag...@suse.de --- hw/ide/macio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 7ef089f..f9a7676 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -87,7 +87,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) s-io_buffer_index = 0x7ff; } -s-io_buffer_size = io-len; +s-io_buffer_size = MIN(io-len, s-packet_transfer_size); MACIO_DPRINTF(remainder: %d io-len: %d size: %d\n, io-remainder_len, io-len, s-packet_transfer_size); @@ -251,7 +251,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret) /* launch next transfer */ s-io_buffer_index = 0; -s-io_buffer_size = io-len; +s-io_buffer_size = MIN(io-len, s-nsector * 512); /* handle unaligned accesses first, get them over with and only do the remaining bulk transfer using our async DMA helpers */ -- 1.8.1.4
[Qemu-devel] [PATCH 11/17] PPC: dbdma: macio: Add DMA callback
We need to know when the IDE core starts a DMA transfer. Add a notifier
function so we have the chance to start transmitting data.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- fix dprintf
---
hw/ide/macio.c | 40
hw/ppc/mac.h | 2 ++
2 files changed, 42 insertions(+)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index fceadfe..2729c62 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -359,11 +359,50 @@ static void macio_ide_reset(DeviceState *dev)
ide_bus_reset(d-bus);
}
+static int ide_nop(IDEDMA *dma)
+{
+return 0;
+}
+
+static int ide_nop_int(IDEDMA *dma, int x)
+{
+return 0;
+}
+
+static void ide_nop_restart(void *opaque, int x, RunState y)
+{
+}
+
+static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
+BlockDriverCompletionFunc *cb)
+{
+MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
+
+MACIO_DPRINTF(\n);
+DBDMA_kick(m-dbdma);
+}
+
+static const IDEDMAOps dbdma_ops = {
+.start_dma = ide_dbdma_start,
+.start_transfer = ide_nop,
+.prepare_buf= ide_nop_int,
+.rw_buf = ide_nop_int,
+.set_unit = ide_nop_int,
+.add_status = ide_nop_int,
+.set_inactive = ide_nop,
+.restart_cb = ide_nop_restart,
+.reset = ide_nop,
+};
+
static void macio_ide_realizefn(DeviceState *dev, Error **errp)
{
MACIOIDEState *s = MACIO_IDE(dev);
ide_init2(s-bus, s-irq);
+
+/* Register DMA callbacks */
+s-dma.ops = dbdma_ops;
+s-bus.dma = s-dma;
}
static void macio_ide_initfn(Object *obj)
@@ -414,6 +453,7 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo
**hd_table)
void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
{
+s-dbdma = dbdma;
DBDMA_register_channel(dbdma, channel, s-dma_irq,
pmac_ide_transfer, pmac_ide_flush, s);
}
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 54efaed..27c4ca3 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -131,6 +131,8 @@ typedef struct MACIOIDEState {
MemoryRegion mem;
IDEBus bus;
BlockDriverAIOCB *aiocb;
+IDEDMA dma;
+void *dbdma;
} MACIOIDEState;
void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
--
1.8.1.4
[Qemu-devel] [PATCH 13/17] PPC: dbdma: Wait for DMA until we have data
We should only start processing DMA requests when we have data to process.
Hold off working through the DMA shuffling until the IDE core told us that
it's ready.
This is required because the guest can program the DMA engine or the IDE
transfer first. Both are legal.
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- move processing to bool
---
hw/ide/macio.c | 19 +++
hw/ppc/mac.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 2729c62..9e613a9 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -64,6 +64,14 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
goto done;
}
+if (!m-dma_active) {
+MACIO_DPRINTF(waiting for data (%#x - %#x - %x)\n,
+ s-nsector, io-len, s-status);
+/* data not ready yet, wait for the channel to get restarted */
+io-processing = false;
+return;
+}
+
MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
if (s-io_buffer_size 0) {
@@ -80,6 +88,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
if (s-packet_transfer_size = 0) {
MACIO_DPRINTF(end of transfer\n);
ide_atapi_cmd_ok(s);
+m-dma_active = false;
}
if (io-len == 0) {
@@ -130,6 +139,14 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
goto done;
}
+if (!m-dma_active) {
+MACIO_DPRINTF(waiting for data (%#x - %#x - %x)\n,
+ s-nsector, io-len, s-status);
+/* data not ready yet, wait for the channel to get restarted */
+io-processing = false;
+return;
+}
+
sector_num = ide_get_sector(s);
MACIO_DPRINTF(io_buffer_size = %#x\n, s-io_buffer_size);
if (s-io_buffer_size 0) {
@@ -145,6 +162,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
MACIO_DPRINTF(end of transfer\n);
s-status = READY_STAT | SEEK_STAT;
ide_set_irq(s-bus);
+m-dma_active = false;
}
if (io-len == 0) {
@@ -379,6 +397,7 @@ static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
MACIO_DPRINTF(\n);
+m-dma_active = true;
DBDMA_kick(m-dbdma);
}
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 27c4ca3..1e578dd 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -133,6 +133,7 @@ typedef struct MACIOIDEState {
BlockDriverAIOCB *aiocb;
IDEDMA dma;
void *dbdma;
+bool dma_active;
} MACIOIDEState;
void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
--
1.8.1.4
[Qemu-devel] [PATCH 14/17] PPC: dbdma: Support unaligned DMA access
The DBDMA engine really just reads bytes from a producing device (IDE
in our case) and shoves these bytes into memory. It doesn't care whether
any alignment takes place or not.
Our code today however assumes that block accesses always happen on
sector (512 byte) boundaries. This is a fair assumption for most cases.
However, Mac OS X really likes to do unaligned, incomplete accesses
that it finishes with the next DMA request.
So we need to read / write the unaligned bits independent of the actual
asynchronous request, because that one can only handle 512-byte-aligned
data. We also need to cache these unaligned sectors until the next DMA
request, at which point the data might be successfully flushed from the
pipe.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/ide/macio.c | 129 ++---
include/hw/ppc/mac_dbdma.h | 3 ++
2 files changed, 125 insertions(+), 7 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 9e613a9..7ef089f 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -56,11 +56,13 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
DBDMA_io *io = opaque;
MACIOIDEState *m = io-opaque;
IDEState *s = idebus_active_if(m-bus);
+int unaligned;
if (ret 0) {
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
ide_atapi_io_error(s, ret);
+io-remainder_len = 0;
goto done;
}
@@ -85,7 +87,29 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
s-io_buffer_index = 0x7ff;
}
-if (s-packet_transfer_size = 0) {
+s-io_buffer_size = io-len;
+
+MACIO_DPRINTF(remainder: %d io-len: %d size: %d\n, io-remainder_len,
+ io-len, s-packet_transfer_size);
+if (io-remainder_len io-len) {
+/* guest wants the rest of its previous transfer */
+int remainder_len = MIN(io-remainder_len, io-len);
+
+MACIO_DPRINTF(copying remainder %d bytes\n, remainder_len);
+
+cpu_physical_memory_write(io-addr, io-remainder + 0x200 -
+ remainder_len, remainder_len);
+
+io-addr += remainder_len;
+io-len -= remainder_len;
+s-io_buffer_size = remainder_len;
+io-remainder_len -= remainder_len;
+/* treat remainder as individual transfer, start again */
+pmac_ide_atapi_transfer_cb(opaque, 0);
+return;
+}
+
+if (!s-packet_transfer_size) {
MACIO_DPRINTF(end of transfer\n);
ide_atapi_cmd_ok(s);
m-dma_active = false;
@@ -98,14 +122,40 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int
ret)
/* launch next transfer */
-MACIO_DPRINTF(io-len = %#x\n, io-len);
+/* handle unaligned accesses first, get them over with and only do the
+ remaining bulk transfer using our async DMA helpers */
+unaligned = io-len 0x1ff;
+if (unaligned) {
+int sector_num = (s-lba 2) + (s-io_buffer_index 9);
+int nsector = io-len 9;
-s-io_buffer_size = io-len;
+MACIO_DPRINTF(precopying unaligned %d bytes to %#lx\n,
+ unaligned, io-addr + io-len - unaligned);
+
+bdrv_read(s-bs, sector_num + nsector, io-remainder, 1);
+cpu_physical_memory_write(io-addr + io-len - unaligned,
+ io-remainder, unaligned);
+
+io-len -= unaligned;
+}
+
+MACIO_DPRINTF(io-len = %#x\n, io-len);
qemu_sglist_init(s-sg, io-len / MACIO_PAGE_SIZE + 1,
address_space_memory);
qemu_sglist_add(s-sg, io-addr, io-len);
-io-addr += io-len;
+io-addr += s-io_buffer_size;
+io-remainder_len = MIN(s-packet_transfer_size - s-io_buffer_size,
+(0x200 - unaligned) 0x1ff);
+MACIO_DPRINTF(set remainder to: %d\n, io-remainder_len);
+
+/* We would read no data from the block layer, thus not get a callback.
+ Just fake completion manually. */
+if (!io-len) {
+pmac_ide_atapi_transfer_cb(opaque, 0);
+return;
+}
+
io-len = 0;
MACIO_DPRINTF(sector_num=%d size=%d, cmd_cmd=%d\n,
@@ -128,14 +178,16 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
DBDMA_io *io = opaque;
MACIOIDEState *m = io-opaque;
IDEState *s = idebus_active_if(m-bus);
-int n;
+int n = 0;
int64_t sector_num;
+int unaligned;
if (ret 0) {
MACIO_DPRINTF(DMA error\n);
m-aiocb = NULL;
qemu_sglist_destroy(s-sg);
ide_dma_error(s);
+io-remainder_len = 0;
goto done;
}
@@ -158,7 +210,33 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
s-nsector -= n;
}
-if (s-nsector == 0) {
+MACIO_DPRINTF(remainder: %d io-len: %d nsector: %d sector_num: %ld\n,
+ io-remainder_len, io-len, s-nsector, sector_num);
+if (io-remainder_len io-len) {
+/* guest wants the rest of its previous
[Qemu-devel] [PATCH 04/17] PPC: dbdma: Replace tabs with spaces
s/^I//g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 102 +++---
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 2fc7f87..ab174f5 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -85,75 +85,75 @@
/* Bits in control and status registers */
-#define RUN0x8000
-#define PAUSE 0x4000
-#define FLUSH 0x2000
-#define WAKE 0x1000
-#define DEAD 0x0800
-#define ACTIVE 0x0400
-#define BT 0x0100
-#define DEVSTAT0x00ff
+#define RUN0x8000
+#define PAUSE 0x4000
+#define FLUSH 0x2000
+#define WAKE 0x1000
+#define DEAD 0x0800
+#define ACTIVE 0x0400
+#define BT 0x0100
+#define DEVSTAT0x00ff
/*
* DBDMA command structure. These fields are all little-endian!
*/
typedef struct dbdma_cmd {
-uint16_t req_count; /* requested byte transfer count */
-uint16_t command;/* command word (has bit-fields) */
-uint32_t phy_addr; /* physical data address */
-uint32_t cmd_dep;/* command-dependent field */
-uint16_t res_count; /* residual count after completion */
-uint16_t xfer_status; /* transfer status */
+uint16_t req_count; /* requested byte transfer count */
+uint16_t command;/* command word (has bit-fields) */
+uint32_t phy_addr; /* physical data address */
+uint32_t cmd_dep;/* command-dependent field */
+uint16_t res_count; /* residual count after completion */
+uint16_t xfer_status;/* transfer status */
} dbdma_cmd;
/* DBDMA command values in command field */
#define COMMAND_MASK0xf000
-#define OUTPUT_MORE0x /* transfer memory data to stream */
-#define OUTPUT_LAST0x1000 /* ditto followed by end marker */
-#define INPUT_MORE 0x2000 /* transfer stream data to memory */
-#define INPUT_LAST 0x3000 /* ditto, expect end marker */
-#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
-#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
-#define DBDMA_NOP 0x6000 /* do nothing */
-#define DBDMA_STOP 0x7000 /* suspend processing */
+#define OUTPUT_MORE 0x/* transfer memory data to stream */
+#define OUTPUT_LAST 0x1000/* ditto followed by end marker */
+#define INPUT_MORE 0x2000/* transfer stream data to memory */
+#define INPUT_LAST 0x3000/* ditto, expect end marker */
+#define STORE_WORD 0x4000/* write word (4 bytes) to device reg */
+#define LOAD_WORD 0x5000/* read word (4 bytes) from device reg */
+#define DBDMA_NOP 0x6000/* do nothing */
+#define DBDMA_STOP 0x7000/* suspend processing */
/* Key values in command field */
#define KEY_MASK0x0700
-#define KEY_STREAM00x /* usual data stream */
-#define KEY_STREAM10x0100 /* control/status stream */
-#define KEY_STREAM20x0200 /* device-dependent stream */
-#define KEY_STREAM30x0300 /* device-dependent stream */
-#define KEY_STREAM40x0400 /* reserved */
-#define KEY_REGS 0x0500 /* device register space */
-#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
-#define KEY_DEVICE 0x0700 /* device memory-mapped space */
+#define KEY_STREAM0 0x/* usual data stream */
+#define KEY_STREAM1 0x0100/* control/status stream */
+#define KEY_STREAM2 0x0200/* device-dependent stream */
+#define KEY_STREAM3 0x0300/* device-dependent stream */
+#define KEY_STREAM4 0x0400/* reserved */
+#define KEY_REGS0x0500/* device register space */
+#define KEY_SYSTEM 0x0600/* system memory-mapped space */
+#define KEY_DEVICE 0x0700/* device memory-mapped space */
/* Interrupt control values in command field */
#define INTR_MASK 0x0030
-#define INTR_NEVER 0x /* don't interrupt */
-#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
-#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
-#define INTR_ALWAYS0x0030 /* always interrupt */
+#define INTR_NEVER 0x/* don't interrupt */
+#define INTR_IFSET 0x0010/* intr if condition bit is 1 */
+#define INTR_IFCLR 0x0020/* intr if condition bit is 0 */
+#define INTR_ALWAYS 0x0030/* always interrupt */
/* Branch control values in command field */
#define BR_MASK 0x000c
-#define BR_NEVER 0x /* don't branch */
-#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
-#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
-#define BR_ALWAYS 0x000c /* always branch */
+#define BR_NEVER0x/* don't branch */
[Qemu-devel] [PATCH 12/17] PPC: dbdma: Move processing to io
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
While touching it, also change it into a bool
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- make processing a bool
---
hw/misc/macio/mac_dbdma.c | 10 ++
include/hw/ppc/mac_dbdma.h | 3 ++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index 95abbba..b8741a1 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -275,7 +275,9 @@ static void dbdma_end(DBDMA_io *io)
conditional_branch(ch);
wait:
-ch-processing = 0;
+/* Indicate that we're ready for a new DMA round */
+ch-io.processing = false;
+
if ((ch-regs[DBDMA_STATUS] RUN)
(ch-regs[DBDMA_STATUS] ACTIVE))
channel_run(ch);
@@ -301,7 +303,7 @@ static void start_output(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 1;
-ch-processing = 1;
+ch-io.processing = true;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -327,7 +329,7 @@ static void start_input(DBDMA_channel *ch, int key,
uint32_t addr,
ch-io.is_last = is_last;
ch-io.dma_end = dbdma_end;
ch-io.is_dma_out = 0;
-ch-processing = 1;
+ch-io.processing = true;
if (ch-rw) {
ch-rw(ch-io);
}
@@ -525,7 +527,7 @@ static void DBDMA_run(DBDMAState *s)
for (channel = 0; channel DBDMA_CHANNELS; channel++) {
DBDMA_channel *ch = s-channels[channel];
uint32_t status = ch-regs[DBDMA_STATUS];
-if (!ch-processing (status RUN) (status ACTIVE)) {
+if (!ch-io.processing (status RUN) (status ACTIVE)) {
channel_run(ch);
}
}
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index eb8e0f0..4d7318d 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -37,6 +37,8 @@ struct DBDMA_io {
int is_last;
int is_dma_out;
DBDMA_end dma_end;
+/* DMA is in progress, don't start another one */
+bool processing;
};
/*
@@ -148,7 +150,6 @@ typedef struct DBDMA_channel {
DBDMA_rw rw;
DBDMA_flush flush;
dbdma_cmd current;
-int processing;
} DBDMA_channel;
typedef struct {
--
1.8.1.4
[Qemu-devel] [PATCH 08/17] PPC: dbdma: Move defines into header file
We usually keep struct and constant definitions in header files. Move
them there to stay consistent and to make access to fields easier.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 117
include/hw/ppc/mac_dbdma.h | 118 +
2 files changed, 118 insertions(+), 117 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index ab32957..eff3368 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -54,123 +54,6 @@
/*
*/
-/*
- * DBDMA control/status registers. All little-endian.
- */
-
-#define DBDMA_CONTROL 0x00
-#define DBDMA_STATUS 0x01
-#define DBDMA_CMDPTR_HI 0x02
-#define DBDMA_CMDPTR_LO 0x03
-#define DBDMA_INTR_SEL0x04
-#define DBDMA_BRANCH_SEL 0x05
-#define DBDMA_WAIT_SEL0x06
-#define DBDMA_XFER_MODE 0x07
-#define DBDMA_DATA2PTR_HI 0x08
-#define DBDMA_DATA2PTR_LO 0x09
-#define DBDMA_RES10x0A
-#define DBDMA_ADDRESS_HI 0x0B
-#define DBDMA_BRANCH_ADDR_HI 0x0C
-#define DBDMA_RES20x0D
-#define DBDMA_RES30x0E
-#define DBDMA_RES40x0F
-
-#define DBDMA_REGS16
-#define DBDMA_SIZE(DBDMA_REGS * sizeof(uint32_t))
-
-#define DBDMA_CHANNEL_SHIFT 7
-#define DBDMA_CHANNEL_SIZE(1 DBDMA_CHANNEL_SHIFT)
-
-#define DBDMA_CHANNELS(0x1000 DBDMA_CHANNEL_SHIFT)
-
-/* Bits in control and status registers */
-
-#define RUN0x8000
-#define PAUSE 0x4000
-#define FLUSH 0x2000
-#define WAKE 0x1000
-#define DEAD 0x0800
-#define ACTIVE 0x0400
-#define BT 0x0100
-#define DEVSTAT0x00ff
-
-/*
- * DBDMA command structure. These fields are all little-endian!
- */
-
-typedef struct dbdma_cmd {
-uint16_t req_count; /* requested byte transfer count */
-uint16_t command;/* command word (has bit-fields) */
-uint32_t phy_addr; /* physical data address */
-uint32_t cmd_dep;/* command-dependent field */
-uint16_t res_count; /* residual count after completion */
-uint16_t xfer_status;/* transfer status */
-} dbdma_cmd;
-
-/* DBDMA command values in command field */
-
-#define COMMAND_MASK0xf000
-#define OUTPUT_MORE 0x/* transfer memory data to stream */
-#define OUTPUT_LAST 0x1000/* ditto followed by end marker */
-#define INPUT_MORE 0x2000/* transfer stream data to memory */
-#define INPUT_LAST 0x3000/* ditto, expect end marker */
-#define STORE_WORD 0x4000/* write word (4 bytes) to device reg */
-#define LOAD_WORD 0x5000/* read word (4 bytes) from device reg */
-#define DBDMA_NOP 0x6000/* do nothing */
-#define DBDMA_STOP 0x7000/* suspend processing */
-
-/* Key values in command field */
-
-#define KEY_MASK0x0700
-#define KEY_STREAM0 0x/* usual data stream */
-#define KEY_STREAM1 0x0100/* control/status stream */
-#define KEY_STREAM2 0x0200/* device-dependent stream */
-#define KEY_STREAM3 0x0300/* device-dependent stream */
-#define KEY_STREAM4 0x0400/* reserved */
-#define KEY_REGS0x0500/* device register space */
-#define KEY_SYSTEM 0x0600/* system memory-mapped space */
-#define KEY_DEVICE 0x0700/* device memory-mapped space */
-
-/* Interrupt control values in command field */
-
-#define INTR_MASK 0x0030
-#define INTR_NEVER 0x/* don't interrupt */
-#define INTR_IFSET 0x0010/* intr if condition bit is 1 */
-#define INTR_IFCLR 0x0020/* intr if condition bit is 0 */
-#define INTR_ALWAYS 0x0030/* always interrupt */
-
-/* Branch control values in command field */
-
-#define BR_MASK 0x000c
-#define BR_NEVER0x/* don't branch */
-#define BR_IFSET0x0004/* branch if condition bit is 1 */
-#define BR_IFCLR0x0008/* branch if condition bit is 0 */
-#define BR_ALWAYS 0x000c/* always branch */
-
-/* Wait control values in command field */
-
-#define WAIT_MASK 0x0003
-#define WAIT_NEVER 0x/* don't wait */
-#define WAIT_IFSET 0x0001/* wait if condition bit is 1 */
-#define WAIT_IFCLR 0x0002/* wait if condition bit is 0 */
-#define WAIT_ALWAYS 0x0003/* always wait */
-
-typedef struct DBDMA_channel {
-int channel;
-uint32_t regs[DBDMA_REGS];
-qemu_irq irq;
-DBDMA_io io;
-DBDMA_rw rw;
-DBDMA_flush flush;
-dbdma_cmd current;
-int processing;
-} DBDMA_channel;
-
-typedef struct {
-MemoryRegion mem;
-DBDMA_channel channels[DBDMA_CHANNELS];
-} DBDMAState;
-
#ifdef DEBUG_DBDMA
static void dump_dbdma_cmd(dbdma_cmd *cmd)
{
diff --git
[Qemu-devel] [PATCH 09/17] PPC: dbdma: Introduce kick function
The DBDMA engine really is running all the time, waiting for input. However
we don't want to waste cycles constantly polling.
So introduce a kick function that data providers can call to notify the
DBDMA controller of new input.
Signed-off-by: Alexander Graf ag...@suse.de
---
hw/misc/macio/mac_dbdma.c | 5 +
include/hw/ppc/mac_dbdma.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c
index eff3368..8434e90 100644
--- a/hw/misc/macio/mac_dbdma.c
+++ b/hw/misc/macio/mac_dbdma.c
@@ -536,6 +536,11 @@ static void DBDMA_run_bh(void *opaque)
DBDMA_run(s);
}
+void DBDMA_kick(DBDMAState *dbdma)
+{
+qemu_bh_schedule(dbdma_bh);
+}
+
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_rw rw, DBDMA_flush flush,
void *opaque)
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index 90be5d9..aaeab10 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -161,6 +161,7 @@ typedef struct {
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_rw rw, DBDMA_flush flush,
void *opaque);
+void DBDMA_kick(DBDMAState *dbdma);
void* DBDMA_init (MemoryRegion **dbdma_mem);
#endif
--
1.8.1.4
[Qemu-devel] [PATCH v3] linux-user: improve target_to_host_sock_type conversion
From: Petar Jovanovic petar.jovano...@imgtec.com
Previous implementation has failed to take into account different value of
SOCK_NONBLOCK on target and host, and existence of SOCK_CLOEXEC.
The same conversion has to be applied both for do_socket and do_socketpair,
so the code has been isolated in a static inline function.
enum sock_type in linux-user/socket.h has been extended to include
TARGET_SOCK_CLOEXEC and TARGET_SOCK_NONBLOCK, similar to definition in libc.
The patch also includes necessary code style changes (tab to spaces) in the
header file since most of the file has been touched by this change.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
v3:
- define TARGET_SOCK_* for the architectures that do not define
ARCH_HAS_SOCKET_TYPES
v2:
- the patch defines ARCH_HAS_SOCKET_TYPES for MIPS, SPARC and ALPHA
- values for sock_type are defined for SPARC and ALPHA in socket.h
linux-user/socket.h | 381 +-
linux-user/syscall.c | 43 +++---
2 files changed, 275 insertions(+), 149 deletions(-)
diff --git a/linux-user/socket.h b/linux-user/socket.h
index 339cae5..ae17959 100644
--- a/linux-user/socket.h
+++ b/linux-user/socket.h
@@ -1,91 +1,104 @@
#if defined(TARGET_MIPS)
- // MIPS special values for constants
-
- /*
-* For setsockopt(2)
-*
-* This defines are ABI conformant as far as Linux supports these ...
-*/
- #define TARGET_SOL_SOCKET 0x
-
- #define TARGET_SO_DEBUG0x0001 /* Record debugging information.
*/
- #define TARGET_SO_REUSEADDR0x0004 /* Allow reuse of local
addresses. */
- #define TARGET_SO_KEEPALIVE0x0008 /* Keep connections alive and
send
- SIGPIPE when they die. */
- #define TARGET_SO_DONTROUTE0x0010 /* Don't do local routing. */
- #define TARGET_SO_BROADCAST0x0020 /* Allow transmission of
- broadcast messages. */
- #define TARGET_SO_LINGER 0x0080 /* Block on close of a reliable
- socket to transmit pending data. */
- #define TARGET_SO_OOBINLINE 0x0100 /* Receive out-of-band data
in-band. */
- #if 0
- To add: #define TARGET_SO_REUSEPORT 0x0200 /* Allow local address
and port reuse. */
- #endif
-
- #define TARGET_SO_TYPE 0x1008 /* Compatible name for SO_STYLE.
*/
- #define TARGET_SO_STYLESO_TYPE /* Synonym */
- #define TARGET_SO_ERROR0x1007 /* get error status and clear */
- #define TARGET_SO_SNDBUF 0x1001 /* Send buffer size. */
- #define TARGET_SO_RCVBUF 0x1002 /* Receive buffer. */
- #define TARGET_SO_SNDLOWAT 0x1003 /* send low-water mark */
- #define TARGET_SO_RCVLOWAT 0x1004 /* receive low-water mark */
- #define TARGET_SO_SNDTIMEO 0x1005 /* send timeout */
- #define TARGET_SO_RCVTIMEO 0x1006 /* receive timeout */
- #define TARGET_SO_ACCEPTCONN 0x1009
-
- /* linux-specific, might as well be the same as on i386 */
- #define TARGET_SO_NO_CHECK 11
- #define TARGET_SO_PRIORITY 12
- #define TARGET_SO_BSDCOMPAT14
-
- #define TARGET_SO_PASSCRED 17
- #define TARGET_SO_PEERCRED 18
-
- /* Security levels - as per NRL IPv6 - don't actually do anything */
- #define TARGET_SO_SECURITY_AUTHENTICATION 22
- #define TARGET_SO_SECURITY_ENCRYPTION_TRANSPORT23
- #define TARGET_SO_SECURITY_ENCRYPTION_NETWORK 24
-
- #define TARGET_SO_BINDTODEVICE 25
-
- /* Socket filtering */
- #define TARGET_SO_ATTACH_FILTER26
- #define TARGET_SO_DETACH_FILTER27
-
- #define TARGET_SO_PEERNAME 28
- #define TARGET_SO_TIMESTAMP29
- #define SCM_TIMESTAMP SO_TIMESTAMP
-
- #define TARGET_SO_PEERSEC 30
- #define TARGET_SO_SNDBUFFORCE 31
- #define TARGET_SO_RCVBUFFORCE 33
-
- /** sock_type - Socket types
-*
-* Please notice that for binary compat reasons MIPS has to
-* override the enum sock_type in include/linux/net.h, so
-* we define ARCH_HAS_SOCKET_TYPES here.
-*
-* @SOCK_DGRAM - datagram (conn.less) socket
-* @SOCK_STREAM - stream (connection) socket
-* @SOCK_RAW - raw socket
-* @SOCK_RDM - reliably-delivered message
-* @SOCK_SEQPACKET - sequential packet socket
-* @SOCK_PACKET - linux specific way of getting packets at the dev
level.
-* For writing rarp and other similar things on the user
level.
-*/
- enum sock_type {
- TARGET_SOCK_DGRAM = 1,
- TARGET_SOCK_STREAM = 2,
- TARGET_SOCK_RAW = 3,
-
