[Qemu-devel] [PATCH 1/3] Make thread pool implementation modular
This patch introduces function pointers for the thread pool, so that
it's implementation can be set at run-time.
Signed-off-by: Matthias Brugger
---
include/block/thread-pool.h | 9 +
thread-pool.c | 32
2 files changed, 41 insertions(+)
diff --git a/include/block/thread-pool.h b/include/block/thread-pool.h
index 32afcdd..53a779f 100644
--- a/include/block/thread-pool.h
+++ b/include/block/thread-pool.h
@@ -38,4 +38,13 @@ int coroutine_fn thread_pool_submit_co(ThreadPool *pool,
ThreadPoolFunc *func, void *arg);
void thread_pool_submit(ThreadPool *pool, ThreadPoolFunc *func, void *arg);
+ThreadPoolFuncArr *thread_pool_probe(void);
+void thread_pool_delete(ThreadPoolFuncArr *tpf);
+
+struct ThreadPoolFuncArr {
+BlockDriverAIOCB *(*thread_pool_submit_aio)(ThreadPool *pool,
ThreadPoolFunc *func, void *arg, BlockDriverCompletionFunc *cb, void *opaque);
+ThreadPool *(*thread_pool_new)(AioContext *ctx);
+};
+
+
#endif
diff --git a/thread-pool.c b/thread-pool.c
index 3735fd3..8c5d1a2 100644
--- a/thread-pool.c
+++ b/thread-pool.c
@@ -26,6 +26,7 @@
#include "qemu/main-loop.h"
static void do_spawn_thread(ThreadPool *pool);
+void thread_pool_aio_free(ThreadPool *pool);
typedef struct ThreadPoolElement ThreadPoolElement;
@@ -77,6 +78,7 @@ struct ThreadPool {
int pending_threads; /* threads created but not running yet */
int pending_cancellations; /* whether we need a cond_broadcast */
bool stopping;
+void (*thread_pool_free)(ThreadPool *pool);
};
static void *worker_thread(void *opaque)
@@ -300,6 +302,7 @@ static void thread_pool_init_one(ThreadPool *pool,
AioContext *ctx)
qemu_sem_init(&pool->sem, 0);
pool->max_threads = 64;
pool->new_thread_bh = aio_bh_new(ctx, spawn_thread_bh_fn, pool);
+pool->thread_pool_free = &thread_pool_aio_free;
QLIST_INIT(&pool->head);
QTAILQ_INIT(&pool->request_list);
@@ -316,6 +319,11 @@ ThreadPool *thread_pool_new(AioContext *ctx)
void thread_pool_free(ThreadPool *pool)
{
+pool->thread_pool_free(pool);
+}
+
+void thread_pool_aio_free(ThreadPool *pool)
+{
if (!pool) {
return;
}
@@ -346,3 +354,27 @@ void thread_pool_free(ThreadPool *pool)
event_notifier_cleanup(&pool->notifier);
g_free(pool);
}
+
+ThreadPoolFuncArr *thread_pool_probe(void)
+{
+ThreadPoolFuncArr *tpf_pool = NULL;
+
+if (tpf_pool)
+return tpf_pool;
+
+tpf_pool = g_new(ThreadPoolFuncArr, 1); //TODO right now, this leaks!
+if (!tpf_pool) {
+printf("error allocating thread pool\n");
+return NULL;
+}
+
+tpf_pool->thread_pool_submit_aio = thread_pool_submit_aio;
+tpf_pool->thread_pool_new = thread_pool_new;
+
+return tpf_pool;
+}
+
+void thread_pool_delete(ThreadPoolFuncArr *tpf)
+{
+g_free(tpf);
+}
--
1.8.1.2
[Qemu-devel] [PATCH 2/3] Block layer uses modular thread pool
With this patch, the calls to the thread pool functions pass through the
new modular thread pool implementation.
Signed-off-by: Matthias Brugger
---
async.c | 4 ++--
block/raw-posix.c | 15 +++
block/raw-win32.c | 9 +++--
include/block/aio.h | 2 +-
include/qemu-common.h | 2 ++
5 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/async.c b/async.c
index 5fb3fa6..e66f70f 100644
--- a/async.c
+++ b/async.c
@@ -232,10 +232,10 @@ GSource *aio_get_g_source(AioContext *ctx)
return &ctx->source;
}
-ThreadPool *aio_get_thread_pool(AioContext *ctx)
+ThreadPool *aio_get_thread_pool(AioContext *ctx, ThreadPoolFuncArr *tpf)
{
if (!ctx->thread_pool) {
-ctx->thread_pool = thread_pool_new(ctx);
+ctx->thread_pool = tpf->thread_pool_new(ctx);
}
return ctx->thread_pool;
}
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 6f03fbf..22842ed 100644
--- a/block/raw-posix.c
+++ b/block/raw-posix.c
@@ -142,6 +142,7 @@ typedef struct BDRVRawState {
bool is_xfs : 1;
#endif
bool has_discard : 1;
+ThreadPoolFuncArr *tpf;
} BDRVRawState;
typedef struct BDRVRawReopenState {
@@ -345,6 +346,9 @@ static int raw_open(BlockDriverState *bs, QDict *options,
int flags,
int ret;
s->type = FTYPE_FILE;
+
+s->tpf = thread_pool_probe();
+
ret = raw_open_common(bs, options, flags, 0, &local_err);
if (error_is_set(&local_err)) {
error_propagate(errp, local_err);
@@ -792,6 +796,7 @@ static BlockDriverAIOCB *paio_submit(BlockDriverState *bs,
int fd,
int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
BlockDriverCompletionFunc *cb, void *opaque, int type)
{
+BDRVRawState *s = bs->opaque;
RawPosixAIOData *acb = g_slice_new(RawPosixAIOData);
ThreadPool *pool;
@@ -807,8 +812,8 @@ static BlockDriverAIOCB *paio_submit(BlockDriverState *bs,
int fd,
acb->aio_offset = sector_num * 512;
trace_paio_submit(acb, opaque, sector_num, nb_sectors, type);
-pool = aio_get_thread_pool(bdrv_get_aio_context(bs));
-return thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
+pool = aio_get_thread_pool(bdrv_get_aio_context(bs), s->tpf);
+return s->tpf->thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
}
static BlockDriverAIOCB *raw_aio_submit(BlockDriverState *bs,
@@ -874,6 +879,8 @@ static void raw_close(BlockDriverState *bs)
qemu_close(s->fd);
s->fd = -1;
}
+
+thread_pool_delete(s->tpf);
}
static int raw_truncate(BlockDriverState *bs, int64_t offset)
@@ -1490,8 +1497,8 @@ static BlockDriverAIOCB *hdev_aio_ioctl(BlockDriverState
*bs,
acb->aio_offset = 0;
acb->aio_ioctl_buf = buf;
acb->aio_ioctl_cmd = req;
-pool = aio_get_thread_pool(bdrv_get_aio_context(bs));
-return thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
+pool = aio_get_thread_pool(bdrv_get_aio_context(bs), s->tpf);
+return s->tpf->thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
}
#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
diff --git a/block/raw-win32.c b/block/raw-win32.c
index 676b570..dad1255 100644
--- a/block/raw-win32.c
+++ b/block/raw-win32.c
@@ -46,6 +46,7 @@ typedef struct RawWin32AIOData {
size_t aio_nbytes;
off64_t aio_offset;
int aio_type;
+ThreadPoolFuncArr *tpf;
} RawWin32AIOData;
typedef struct BDRVRawState {
@@ -159,8 +160,8 @@ static BlockDriverAIOCB *paio_submit(BlockDriverState *bs,
HANDLE hfile,
acb->aio_offset = sector_num * 512;
trace_paio_submit(acb, opaque, sector_num, nb_sectors, type);
-pool = aio_get_thread_pool(bdrv_get_aio_context(bs));
-return thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
+pool = aio_get_thread_pool(bdrv_get_aio_context(bs), s->tpf);
+return s->tpf->thread_pool_submit_aio(pool, aio_worker, acb, cb, opaque);
}
int qemu_ftruncate64(int fd, int64_t length)
@@ -248,6 +249,8 @@ static int raw_open(BlockDriverState *bs, QDict *options,
int flags,
s->type = FTYPE_FILE;
+s->tpf = thread_pool_probe();
+
opts = qemu_opts_create_nofail(&raw_runtime_opts);
qemu_opts_absorb_qdict(opts, options, &local_err);
if (error_is_set(&local_err)) {
@@ -339,6 +342,8 @@ static void raw_close(BlockDriverState *bs)
{
BDRVRawState *s = bs->opaque;
CloseHandle(s->hfile);
+
+thread_pool_delete(s->tpf);
}
static int raw_truncate(BlockDriverState *bs, int64_t offset)
diff --git a/include/block/aio.h b/include/block/aio.h
index 2efdf41..22d6fa0 100644
--- a/include/block/aio.h
+++ b/include/block/aio.h
@@ -231,7 +231,7 @@ void aio_set_event_notifier(AioContext *ctx,
GSource *aio_get_g_source(AioContext *ctx);
/* Return the ThreadPool bound to this AioContext */
-struct ThreadPool *aio_get_thread_pool(AioContext *ctx);
+struct ThreadPool *aio_get_thread_pool(AioContext *ctx, ThreadPoolFuncArr
*tpf);
/* Functions to operate on the m
[Qemu-devel] [PATCH 3/3] Add workerthreads configuration option
This patch allows the definition which thread pool will be used by
every block device. The defintion of the workerthreads option
allows this at the command line level.
At the moment only the thread pool implementation "pool" can be chosen.
Signed-off-by: Matthias Brugger
---
blockdev.c | 13 +
qemu-options.hx | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index b260477..8b83611 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -388,6 +388,15 @@ static DriveInfo *blockdev_init(QDict *bs_opts,
}
#endif
+if ((buf = qemu_opt_get(opts, "workerthreads")) != NULL) {
+if (!strcmp(buf, "pool")) {
+/* this is the default */
+} else {
+error_report("invalid workerthreads option");
+return NULL;
+}
+}
+
if ((buf = qemu_opt_get(opts, "format")) != NULL) {
if (is_help_option(buf)) {
error_printf("Supported formats:");
@@ -2269,6 +2278,10 @@ QemuOptsList qemu_common_drive_opts = {
.type = QEMU_OPT_STRING,
.help = "disk serial number",
},{
+.name = "workerthreads",
+.type = QEMU_OPT_STRING,
+.help = "type of worker threads (pool)",
+},{
.name = "rerror",
.type = QEMU_OPT_STRING,
.help = "read error action",
diff --git a/qemu-options.hx b/qemu-options.hx
index 5dc8b75..6f22242 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -408,7 +408,7 @@ DEF("drive", HAS_ARG, QEMU_OPTION_drive,
" [,cyls=c,heads=h,secs=s[,trans=t]][,snapshot=on|off]\n"
"
[,cache=writethrough|writeback|none|directsync|unsafe][,format=f]\n"
" [,serial=s][,addr=A][,id=name][,aio=threads|native]\n"
-" [,readonly=on|off][,copy-on-read=on|off]\n"
+" [,workerthreads=pool][,readonly=on|off][,copy-on-read=on|off]\n"
" [[,bps=b]|[[,bps_rd=r][,bps_wr=w]]]\n"
" [[,iops=i]|[[,iops_rd=r][,iops_wr=w]]]\n"
" [[,bps_max=bm]|[[,bps_rd_max=rm][,bps_wr_max=wm]]]\n"
--
1.8.1.2
[Qemu-devel] [Bug 1247122] [NEW] kernel guest 3.10.6 boot failure at sha_transform
Public bug reported: Error occured with - QEMU emulator version 1.6.1 and - QEMU emulator version 1.2.0 (qemu-kvm-1.2.0+noroms-0ubuntu2.12.10.5, Debian) started qemu-system-i386 with default settings and no additional arguments. Tested a kernel version 3.5.4 without any problems. Hint: new kernel CONFIG parameter CONFIG_CRYPTO_SHA256 is needed in kernel 3.10.6. Kernel panic with kernel 3.10.6 [0.00] Linux version 3.10.6-generic-1.0 (root@STAG-Linux6) (gcc version 4.5.0 (GCC) ) #1 SMP PREEMPT Fri Nov 1 07:51:10 UTC 2013 [0.00] e820: BIOS-provided physical RAM map: [0.00] BIOS-e820: [mem 0x-0x0009fbff] usable [0.00] BIOS-e820: [mem 0x0009fc00-0x0009] reserved [0.00] BIOS-e820: [mem 0x000f-0x000f] reserved [0.00] BIOS-e820: [mem 0x0010-0x07ffdfff] usable [0.00] BIOS-e820: [mem 0x07ffe000-0x07ff] reserved [0.00] BIOS-e820: [mem 0xfffc-0x] reserved [0.00] Notice: NX (Execute Disable) protection missing in CPU! [0.00] SMBIOS 2.4 present. [0.00] e820: last_pfn = 0x7ffe max_arch_pfn = 0x10 [0.00] found SMP MP-table at [mem 0x000f1850-0x000f185f] mapped at [c00f1850] [0.00] Scanning 1 areas for low memory corruption [0.00] init_memory_mapping: [mem 0x-0x000f] [0.00] init_memory_mapping: [mem 0x0780-0x07bf] [0.00] init_memory_mapping: [mem 0x0010-0x077f] [0.00] init_memory_mapping: [mem 0x07c0-0x07ffdfff] [0.00] ACPI: RSDP 000f16f0 00014 (v00 BOCHS ) [0.00] ACPI: RSDT 07ffe450 00034 (v01 BOCHS BXPCRSDT 0001 BXPC 0001) [0.00] ACPI: FACP 0780 00074 (v01 BOCHS BXPCFACP 0001 BXPC 0001) [0.00] ACPI: DSDT 07ffe490 01137 (v01 BXPC BXDSDT 0001 INTL 20100528) [0.00] ACPI: FACS 0740 00040 [0.00] ACPI: SSDT 07fff700 00838 (v01 BOCHS BXPCSSDT 0001 BXPC 0001) [0.00] ACPI: APIC 07fff610 00078 (v01 BOCHS BXPCAPIC 0001 BXPC 0001) [0.00] ACPI: HPET 07fff5d0 00038 (v01 BOCHS BXPCHPET 0001 BXPC 0001) [0.00] 0MB HIGHMEM available. [0.00] 127MB LOWMEM available. [0.00] mapped low ram: 0 - 07ffe000 [0.00] low ram: 0 - 07ffe000 [0.00] Zone ranges: [0.00] DMA [mem 0x1000-0x00ff] [0.00] Normal [mem 0x0100-0x07ffdfff] [0.00] HighMem empty [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x1000-0x0009efff] [0.00] node 0: [mem 0x0010-0x07ffdfff] [0.00] Using APIC driver default [0.00] ACPI: PM-Timer IO Port: 0xb008 [0.00] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [0.00] ACPI: LAPIC_NMI (acpi_id[0xff] dfl dfl lint[0x1]) [0.00] ACPI: IOAPIC (id[0x00] address[0xfec0] gsi_base[0]) [0.00] IOAPIC[0]: apic_id 0 already used, trying 1 [0.00] IOAPIC[0]: apic_id 1, version 17, address 0xfec0, GSI 0-23 [0.00] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [0.00] ACPI: INT_SRC_OVR (bus 0 bus_irq 5 global_irq 5 high level) [0.00] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [0.00] ACPI: INT_SRC_OVR (bus 0 bus_irq 10 global_irq 10 high level) [0.00] ACPI: INT_SRC_OVR (bus 0 bus_irq 11 global_irq 11 high level) [0.00] Using ACPI (MADT) for SMP configuration information [0.00] ACPI: HPET id: 0x8086a201 base: 0xfed0 [0.00] smpboot: Allowing 1 CPUs, 0 hotplug CPUs [0.00] e820: [mem 0x0800-0xfffb] available for PCI devices [0.00] Booting paravirtualized kernel on bare hardware [0.00] setup_percpu: NR_CPUS:4 nr_cpumask_bits:4 nr_cpu_ids:1 nr_node_ids:1 [0.00] PERCPU: Embedded 12 pages/cpu @c7eef000 s27200 r0 d21952 u49152 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32412 [0.00] Kernel command line: BOOT_IMAGE=/boot/vmlinux-3.10.6 root=/dev/sda1 ro acpi_enforce_resources=no console=ttyS0 [0.00] PID hash table entries: 512 (order: -1, 2048 bytes) [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Initializing CPU#0 [0.00] Initializing HighMem for node 0 (:) [0.00] Memory: 118364k/131064k available (7497k kernel code, 12308k reserved, 2513k data, 472k init, 0k highmem) [0.00] virtual kernel memory layout: [0.00] fixmap : 0xfff64000 - 0xf000 ( 620 kB) [0.00] pkmap : 0xff80 - 0xffc0 (4096 kB) [0.00] vmalloc : 0xc87fe000 - 0xff7fe000 ( 880 MB) [0.00] lowmem : 0xc
[Qemu-devel] Make thread pool implementation modular
This patch series makes the thread pool implementation modular. This allows each drive to use a special implementation. The patch series prepares qemu to be able to include thread pools different the one actually implemented. It will allow to implement approaches like paravirtualized block requests [1]. async.c | 4 ++-- block/raw-posix.c | 15 +++ block/raw-win32.c | 9 +++-- blockdev.c | 13 + include/block/aio.h | 2 +- include/block/thread-pool.h | 9 + include/qemu-common.h | 2 ++ qemu-options.hx | 2 +- thread-pool.c | 32 9 files changed, 78 insertions(+), 10 deletions(-) [1] http://www.linux-kvm.org/wiki/images/5/53/2012-forum-Brugger-lightningtalk.pdf
Re: [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception
On 10/29/2013 03:41 PM, Sebastian Macke wrote: > > What is included in the tb hash? The virtual pc + physical page + the > tb_flags? > Not the mmu_index? What's included is everything you return from cpu_get_tb_cpu_state. Note that cs_base is an interesting case. On i386 real mode, it's what the name implies -- the code segment base. On sparc, we (ab)use it to handle an insn beginning from a delay slot. (On Sparc, pc is the current insn, and npc is the next insn. For straight-line code, npc = pc + 4. After a branch, npc is the branch target. After every insn, the cpu copies pc = npc.) See my response to Peter for info re mmu_index. r~
Re: [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception
On 11/01/2013 11:58 AM, Peter Maydell wrote: >> > What is included in the tb hash? The virtual pc + physical page + the >> > tb_flags? Not the mmu_index? > You're right that the mmu_index is not included in the tb hash. > Does that mean that the CPU state which determines the > mmu_index needs to be in the tb_flags? I'm not sure and it's > not something I'd thought about before. Richard -- do you know? Normally the supervisor/hypervisor/whatever bit(s) is present in the tb_flags, and the mmu_index ought to be computed from that. That said, what normally happens is that we re-use cpu_mmu_index, which looks at env, which is technically wrong. But there's an assumption that the bits we're examining in env have been copied to tb_flags, so the data is actually in sync. r~
[Qemu-devel] [PATCH] qemu-ga: vss-win32: Install VSS provider COM+ application service
Currently, qemu-ga for Windows fails to execute guset-fsfreeze-freeze when
no user is logging in to Windows, with an error message:
{"error":{"class":"GenericError",
"desc":"failed to add C:\\ to snapshotset: (error: 8004230f)"}}
To enable guest-fsfreeze-freeze/thaw without logging in users, this installs
a service to execute qemu-ga VSS provider COM+ application that has full
access privileges to the local system. The service will automatically be
removed when the COM+ application is deregistered.
This patch replaces ICOMAdminCatalog interface with ICOMAdminCatalog2
interface that contains CreateServiceForApplication() method in addition.
Signed-off-by: Tomoki Sekiyama
---
qga/vss-win32/install.cpp | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index 37731a7..b791a6c 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -25,8 +25,8 @@ extern HINSTANCE g_hinstDll;
const GUID CLSID_COMAdminCatalog = { 0xF618C514, 0xDFB8, 0x11d1,
{0xA2, 0xCF, 0x00, 0x80, 0x5F, 0xC7, 0x92, 0x35} };
-const GUID IID_ICOMAdminCatalog = { 0xDD662187, 0xDFC2, 0x11d1,
-{0xA2, 0xCF, 0x00, 0x80, 0x5F, 0xC7, 0x92, 0x35} };
+const GUID IID_ICOMAdminCatalog2 = { 0x790C6E0B, 0x9194, 0x4cc9,
+{0x94, 0x26, 0xA4, 0x8A, 0x63, 0x18, 0x56, 0x96} };
const GUID CLSID_WbemLocator = { 0x4590f811, 0x1d3a, 0x11d0,
{0x89, 0x1f, 0x00, 0xaa, 0x00, 0x4b, 0x2e, 0x24} };
const GUID IID_IWbemLocator = { 0xdc12a687, 0x737f, 0x11cf,
@@ -141,7 +141,7 @@ static HRESULT QGAProviderFind(
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
-COMPointer pCatalog;
+COMPointer pCatalog;
COMPointer pColl;
COMPointer pObj;
_variant_t var;
@@ -149,7 +149,7 @@ static HRESULT QGAProviderFind(
chk(CoCreateInstance(CLSID_COMAdminCatalog, NULL, CLSCTX_INPROC_SERVER,
IID_IUnknown, (void **)pUnknown.replace()));
-chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog,
+chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog2,
(void **)pCatalog.replace()));
chk(pCatalog->GetCollection(_bstr_t(L"Applications"),
(IDispatch **)pColl.replace()));
@@ -206,7 +206,7 @@ STDAPI COMRegister(void)
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
-COMPointer pCatalog;
+COMPointer pCatalog;
COMPointer pApps, pRoles, pUsersInRole;
COMPointer pObj;
long n;
@@ -229,7 +229,7 @@ STDAPI COMRegister(void)
chk(CoCreateInstance(CLSID_COMAdminCatalog, NULL, CLSCTX_INPROC_SERVER,
IID_IUnknown, (void **)pUnknown.replace()));
-chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog,
+chk(pUnknown->QueryInterface(IID_ICOMAdminCatalog2,
(void **)pCatalog.replace()));
/* Install COM+ Component */
@@ -273,6 +273,10 @@ STDAPI COMRegister(void)
goto out;
}
+chk(pCatalog->CreateServiceForApplication(
+_bstr_t(QGA_PROVIDER_LNAME), _bstr_t(QGA_PROVIDER_LNAME),
+_bstr_t(L"SERVICE_AUTO_START"), _bstr_t(L"SERVICE_ERROR_NORMAL"),
+_bstr_t(L""), _bstr_t(L".\\localsystem"), _bstr_t(L""), FALSE));
chk(pCatalog->InstallComponent(_bstr_t(QGA_PROVIDER_LNAME),
_bstr_t(dllPath), _bstr_t(tlbPath),
_bstr_t("")));
Re: [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on exception
On 29 October 2013 22:41, Sebastian Macke wrote: > On 29/10/2013 12:47 PM, Peter Maydell wrote: >> >> On 29 October 2013 19:04, Sebastian Macke wrote: >>> /* Internal flags, delay slot flag */ >>> -#define D_FLAG1 >>> +#define D_FLAG2 >> >> Since this set of #defines effectively is the documentation for >> what the tb_flags usage is, can you update it to include the >> new flag you've added, please? > > > I will. I think I have done it in one of the later patches. > But the D_FLAG was there before. What I did was just changing it to 2 > because 1 is used by the new SR_SM > (supervisor mode) Flag. Yes, that's what I mean -- this patch is adding a new flag (because it's changing cpu_get_tb_cpu_state) and so it should also be updating this set of #defines. >> It looks suspicious that this patch doesn't include any change to >> translate.c which reads the tb flag you've just added. Either: >> (a) the translated code doesn't actually build in any dependencies >>on the SR_SM flag, in which case it doesn't need to be a tb_flag at all >> (b) the translated code is still referring directly to env->sr >> somewhere, >>in which case it needs to be changed to use the tb_flags version >> instead >> >> Also, are you sure that tlb_flush() is needed purely for the change to the >> SR_SM flags and not for any of the other CPU state changes that >> openrisc_cpu_do_interrupt() is making when it does the user->supervisor >> state change? > The exception is going into supervisor mode and disables the mmu. The > mmu_index is changed and it should work. > But then the emulated Linux crashes. > This does not happen when I add the supervisor mode flag to the tb_flags. > What is included in the tb hash? The virtual pc + physical page + the > tb_flags? Not the mmu_index? You're right that the mmu_index is not included in the tb hash. Does that mean that the CPU state which determines the mmu_index needs to be in the tb_flags? I'm not sure and it's not something I'd thought about before. Richard -- do you know? thanks -- PMM
[Qemu-devel] [PATCH 2/2] vfio-pci: Make use of new KVM-VFIO device
Add and remove groups from the KVM virtual VFIO device as we make
use of them. This allows KVM to optimize for performance and
correctness based on properties of the group.
Signed-off-by: Alex Williamson
---
hw/misc/vfio.c | 67
1 file changed, 67 insertions(+)
diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
index fe95e03..5a8c305 100644
--- a/hw/misc/vfio.c
+++ b/hw/misc/vfio.c
@@ -208,6 +208,17 @@ static QLIST_HEAD(, VFIOContainer)
static QLIST_HEAD(, VFIOGroup)
group_list = QLIST_HEAD_INITIALIZER(group_list);
+#ifdef CONFIG_KVM
+/*
+ * We have a single VFIO pseudo device per KVM VM. Once created it lives
+ * for the life of the VM. Closing the file descriptor only drops our
+ * reference to it and the device's reference to kvm. Therefore once
+ * initialized, this file descriptor is only released on QEMU exit and
+ * we'll re-use it should another vfio device be attached before then.
+ */
+static int vfio_kvm_device_fd = -1;
+#endif
+
static void vfio_disable_interrupts(VFIODevice *vdev);
static uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
static void vfio_pci_write_config(PCIDevice *pdev, uint32_t addr,
@@ -3041,6 +3052,59 @@ static void vfio_pci_reset_handler(void *opaque)
}
}
+static void vfio_kvm_device_add_group(VFIOGroup *group)
+{
+#ifdef CONFIG_KVM
+struct kvm_device_attr attr = {
+.group = KVM_DEV_VFIO_GROUP,
+.attr = KVM_DEV_VFIO_GROUP_ADD,
+.addr = (uint64_t)(unsigned long)&group->fd,
+};
+
+if (!kvm_enabled()) {
+return;
+}
+
+if (vfio_kvm_device_fd < 0) {
+struct kvm_create_device cd = {
+.type = KVM_DEV_TYPE_VFIO,
+};
+
+if (kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &cd)) {
+DPRINTF("KVM_CREATE_DEVICE: %m\n");
+return;
+}
+
+vfio_kvm_device_fd = cd.fd;
+}
+
+if (ioctl(vfio_kvm_device_fd, KVM_SET_DEVICE_ATTR, &attr)) {
+error_report("Failed to add group %d to KVM VFIO device: %m",
+ group->groupid);
+}
+#endif
+}
+
+static void vfio_kvm_device_del_group(VFIOGroup *group)
+{
+#ifdef CONFIG_KVM
+struct kvm_device_attr attr = {
+.group = KVM_DEV_VFIO_GROUP,
+.attr = KVM_DEV_VFIO_GROUP_DEL,
+.addr = (uint64_t)(unsigned long)&group->fd,
+};
+
+if (vfio_kvm_device_fd < 0) {
+return;
+}
+
+if (ioctl(vfio_kvm_device_fd, KVM_SET_DEVICE_ATTR, &attr)) {
+error_report("Failed to remove group %d to KVM VFIO device: %m",
+ group->groupid);
+}
+#endif
+}
+
static int vfio_connect_container(VFIOGroup *group)
{
VFIOContainer *container;
@@ -3189,6 +3253,8 @@ static VFIOGroup *vfio_get_group(int groupid)
QLIST_INSERT_HEAD(&group_list, group, next);
+vfio_kvm_device_add_group(group);
+
return group;
}
@@ -3198,6 +3264,7 @@ static void vfio_put_group(VFIOGroup *group)
return;
}
+vfio_kvm_device_del_group(group);
vfio_disconnect_container(group);
QLIST_REMOVE(group, next);
DPRINTF("vfio_put_group: close group->fd\n");
[Qemu-devel] [PATCH 0/2] vfio-pci: Enable KVM-VFIO device
The KVM-VFIO device was just introduced into kvm.git/next with an initial goal of managing whether guests are capable of non-coherent DMA. This is potentially important for any VFIO assigned device, but particularly important to some graphics cards which are known to make use of the NoSnoop capabilities of PCIe. By registering VFIO groups into the KVM-VFIO device, KVM is able to verify that a user has an assigned device and (eventually) query VFIO directly for properties of the IOMMU domain. In the short term, KVM assumes any VFIO assigned device is capable of non-coherent DMA. This support can certainly be seen as a bug fix (devices are capable of NoSnoop DMA today and qemu/kvm does not emulate coherency ops like WBINVD), so I'd certainly like to get feedback on whether this is acceptable QEMU 1.7 material. The fact that it depends on a kernel header update which is not yet in mainline may be a gating factor as well. We've taken linux-header updates from kvm.git in the past and barring a patch faux pas from Gleb & Paolo it will get into mainline. I've stated in the past that we should default to taking header updates from mainline, but the impending v3.12 release and merge window doesn't fit well with the QEMU 1.7 release timeframe. I could also strip the header update down to minimum required if that helps. The other option is to wait for QEMU 1.8 to open at which point we should be close to having a v3.13-rc1 tag to pull header updates from and I can propose both the KVM and QEMU patches for stable. Getting it in for QEMU 1.7 would make a lot of people playing with VGA passthrough very happy. Thoughts? Thanks, Alex --- Alex Williamson (2): linux-headers: Update from kvm.git 81e87e26796782e014fd1f2bb9cd8fb6ce4021a8 vfio-pci: Make use of new KVM-VFIO device hw/misc/vfio.c | 67 ++ linux-headers/asm-arm/kvm.h |3 + linux-headers/asm-powerpc/epapr_hcalls.h |4 +- linux-headers/asm-x86/kvm.h |6 +-- linux-headers/linux/kvm.h|7 +++ 5 files changed, 81 insertions(+), 6 deletions(-)
[Qemu-devel] [PATCH 1/2] linux-headers: Update from kvm.git 81e87e26796782e014fd1f2bb9cd8fb6ce4021a8
Current next branch.
Signed-off-by: Alex Williamson
---
linux-headers/asm-arm/kvm.h |3 ++-
linux-headers/asm-powerpc/epapr_hcalls.h |4 ++--
linux-headers/asm-x86/kvm.h |6 +++---
linux-headers/linux/kvm.h|7 +++
4 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index c1ee007..c498b60 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -63,7 +63,8 @@ struct kvm_regs {
/* Supported Processor Types */
#define KVM_ARM_TARGET_CORTEX_A15 0
-#define KVM_ARM_NUM_TARGETS1
+#define KVM_ARM_TARGET_CORTEX_A7 1
+#define KVM_ARM_NUM_TARGETS2
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
diff --git a/linux-headers/asm-powerpc/epapr_hcalls.h
b/linux-headers/asm-powerpc/epapr_hcalls.h
index 33b3f89..06f7247 100644
--- a/linux-headers/asm-powerpc/epapr_hcalls.h
+++ b/linux-headers/asm-powerpc/epapr_hcalls.h
@@ -78,7 +78,7 @@
#define EV_SUCCESS 0
#define EV_EPERM 1 /* Operation not permitted */
#define EV_ENOENT 2 /* Entry Not Found */
-#define EV_EIO 3 /* I/O error occurred */
+#define EV_EIO 3 /* I/O error occured */
#define EV_EAGAIN 4 /* The operation had insufficient
* resources to complete and should be
* retried
@@ -89,7 +89,7 @@
#define EV_ENODEV 7 /* No such device */
#define EV_EINVAL 8 /* An argument supplied to the hcall
was out of range or invalid */
-#define EV_INTERNAL9 /* An internal error occurred */
+#define EV_INTERNAL9 /* An internal error occured */
#define EV_CONFIG 10 /* A configuration error was detected */
#define EV_INVALID_STATE 11 /* The object is in an invalid state */
#define EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 5d9a303..d3a8778 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -211,9 +211,9 @@ struct kvm_cpuid_entry2 {
__u32 padding[3];
};
-#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
-#define KVM_CPUID_FLAG_STATEFUL_FUNC2
-#define KVM_CPUID_FLAG_STATE_READ_NEXT 4
+#define KVM_CPUID_FLAG_SIGNIFCANT_INDEXBIT(0)
+#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1)
+#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2)
/* for KVM_SET_CPUID2 */
struct kvm_cpuid2 {
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 13e890c..8544336 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -541,6 +541,7 @@ struct kvm_ppc_smmu_info {
#define KVM_TRACE_ENABLE __KVM_DEPRECATED_MAIN_W_0x06
#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
+#define KVM_GET_EMULATED_CPUID _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
/*
* Extension capability list.
@@ -668,6 +669,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_IRQ_XICS 92
#define KVM_CAP_ARM_EL1_32BIT 93
#define KVM_CAP_SPAPR_MULTITCE 94
+#define KVM_CAP_EXT_EMUL_CPUID 95
#ifdef KVM_CAP_IRQ_ROUTING
@@ -843,6 +845,10 @@ struct kvm_device_attr {
#define KVM_DEV_TYPE_FSL_MPIC_20 1
#define KVM_DEV_TYPE_FSL_MPIC_42 2
#define KVM_DEV_TYPE_XICS 3
+#define KVM_DEV_TYPE_VFIO 4
+#define KVM_DEV_VFIO_GROUP1
+#define KVM_DEV_VFIO_GROUP_ADD 1
+#define KVM_DEV_VFIO_GROUP_DEL 2
/*
* ioctls for VM fds
@@ -1012,6 +1018,7 @@ struct kvm_s390_ucas_mapping {
/* VM is being stopped by host */
#define KVM_KVMCLOCK_CTRL_IO(KVMIO, 0xad)
#define KVM_ARM_VCPU_INIT_IOW(KVMIO, 0xae, struct kvm_vcpu_init)
+#define KVM_ARM_PREFERRED_TARGET _IOR(KVMIO, 0xaf, struct kvm_vcpu_init)
#define KVM_GET_REG_LIST _IOWR(KVMIO, 0xb0, struct kvm_reg_list)
#define KVM_DEV_ASSIGN_ENABLE_IOMMU(1 << 0)
Re: [Qemu-devel] [PATCH] Adjust qapi-visit for python-2.4.3
On Thu, 31 Oct 2013 13:26:01 -0700
Richard Henderson wrote:
> We say we support python 2.4, but python 2.4.3 does not
> support the "expr if test else expr" syntax used here.
>
> This allows QEMU to compile on RHEL 5.3, the last release for ia64.
>
> Signed-off-by: Richard Henderson
Applied to the qmp branch, thanks.
> ---
> scripts/qapi-visit.py | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/scripts/qapi-visit.py b/scripts/qapi-visit.py
> index c39e628..65f1a54 100644
> --- a/scripts/qapi-visit.py
> +++ b/scripts/qapi-visit.py
> @@ -20,7 +20,10 @@ import errno
> def generate_visit_struct_fields(name, field_prefix, fn_prefix, members,
> base = None):
> substructs = []
> ret = ''
> -full_name = name if not fn_prefix else "%s_%s" % (name, fn_prefix)
> +if not fn_prefix:
> +full_name = name
> +else:
> +full_name = "%s_%s" % (name, fn_prefix)
>
> for argname, argentry, optional, structured in parse_args(members):
> if structured:
> @@ -97,7 +100,10 @@ if (!error_is_set(errp)) {
> ''')
> push_indent()
>
> -full_name = name if not field_prefix else "%s_%s" % (field_prefix, name)
> +if not field_prefix:
> +full_name = name
> +else:
> +full_name = "%s_%s" % (field_prefix, name)
>
> if len(field_prefix):
> ret += mcgen('''
> @@ -283,12 +289,17 @@ void visit_type_%(name)s(Visitor *m, %(name)s ** obj,
> const char *name, Error **
> name=name)
>
> pop_indent()
> +
> +if not discriminator:
> +desc_type = "type"
> +else:
> +desc_type = discriminator
> ret += mcgen('''
> visit_type_%(name)sKind(m, &(*obj)->kind, "%(type)s", &err);
> if (!err) {
> switch ((*obj)->kind) {
> ''',
> - name=name, type="type" if not discriminator else
> discriminator)
> + name=name, type=desc_type)
>
> for key in members:
> if not discriminator:
Re: [Qemu-devel] [sheepdog] [PATCH v5 RESENT 0/2] sheepdog: add user-defined redundancy option
At Fri, 1 Nov 2013 23:10:11 +0800, Liu Yuan wrote: > > v5: > - use pstrcpy instead of strncpy > - fix a segfalt for 'null' string option string > > v4: > - fix do_sd_create that forgot to pass nr_copies > - fix parse_redundancy dealing with replicated vdi > > v3: > - rework is_numeric > > v2: > - fix a typo in comment and commit log > > This patch set add one sheepdog specific option for qemu-img to control > redundancy. > > This patch set is on top of Kevin's block tree. > > Liu Yuan (2): > sheepdog: refactor do_sd_create() > sheepdog: support user-defined redundancy option > > block/sheepdog.c | 127 > + > include/block/block_int.h |1 + > 2 files changed, 105 insertions(+), 23 deletions(-) Reviewed-by: MORITA Kazutaka
Re: [Qemu-devel] [PATCH] Adjust qapi-visit for python-2.4.3
Quoting Richard Henderson (2013-10-31 15:26:01)
> We say we support python 2.4, but python 2.4.3 does not
> support the "expr if test else expr" syntax used here.
>
> This allows QEMU to compile on RHEL 5.3, the last release for ia64.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Michael Roth
> ---
> scripts/qapi-visit.py | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/scripts/qapi-visit.py b/scripts/qapi-visit.py
> index c39e628..65f1a54 100644
> --- a/scripts/qapi-visit.py
> +++ b/scripts/qapi-visit.py
> @@ -20,7 +20,10 @@ import errno
> def generate_visit_struct_fields(name, field_prefix, fn_prefix, members,
> base = None):
> substructs = []
> ret = ''
> -full_name = name if not fn_prefix else "%s_%s" % (name, fn_prefix)
> +if not fn_prefix:
> +full_name = name
> +else:
> +full_name = "%s_%s" % (name, fn_prefix)
>
> for argname, argentry, optional, structured in parse_args(members):
> if structured:
> @@ -97,7 +100,10 @@ if (!error_is_set(errp)) {
> ''')
> push_indent()
>
> -full_name = name if not field_prefix else "%s_%s" % (field_prefix, name)
> +if not field_prefix:
> +full_name = name
> +else:
> +full_name = "%s_%s" % (field_prefix, name)
>
> if len(field_prefix):
> ret += mcgen('''
> @@ -283,12 +289,17 @@ void visit_type_%(name)s(Visitor *m, %(name)s ** obj,
> const char *name, Error **
> name=name)
>
> pop_indent()
> +
> +if not discriminator:
> +desc_type = "type"
> +else:
> +desc_type = discriminator
> ret += mcgen('''
> visit_type_%(name)sKind(m, &(*obj)->kind, "%(type)s", &err);
> if (!err) {
> switch ((*obj)->kind) {
> ''',
> - name=name, type="type" if not discriminator else
> discriminator)
> + name=name, type=desc_type)
>
> for key in members:
> if not discriminator:
> --
> 1.8.3.1
Re: [Qemu-devel] [PATCH v8 00/19] VHDX log replay and write support, .bdrv_create()
On Thu, Oct 31, 2013 at 02:10:48PM +0100, Stefan Hajnoczi wrote: > On Wed, Oct 30, 2013 at 10:44:37AM -0400, Jeff Cody wrote: > > This patch series contains the initial VHDX log parsing, replay, > > write support, and image creation. > > > > === v8 changes === > > https://github.com/codyprime/qemu-kvm-jtc/tree/vhdx-write-v7-upstream > > > > Rebased to latest qemu/master > > > > Patch 10/19: * Added comments for bdrv_flush() (Stefan) > > > > Patch 11/19: * Added qemu_iovec_destroy(&hd_qiov) (Stefan) > > * On certain _writev errors, restore BAT cache (Stefan) > > > > Patch 16/19: * Replaced fprintf(stderr,...) with error_setg_errno() (Stefan) > > > > Patch 18/19: * Added filter for block_state_zero in qemu-iotest/common.rc > > > > Patch 19/19: * Moved log replay test name to 068 (part of rebase to master) > > > > === v7 changes === > > https://github.com/codyprime/qemu-kvm-jtc/tree/vhdx-write-v7-upstream > > > > Rebased to latest qemu/master (picked up vhdx r/o tests, migration blocker) > > > > Patch 8/19: * validate log descriptor_count (Stefan) > > * fix typos in comments (Stefan) > > * Removed unneccessary initialization (Stefan) > > * Replay log prior to metadata (Stefan) > > * In vhdx_log_flush(), call bdrv_flush() prior to zeroing > >out the log guid in the header. > > * In vhdx_close(), set freed pointers to NULL > > > > Patch 9/19: * correct logic for region overlap (Stefan) > > > > Patch 10/19: * add missing goto exit in error case (Stefan) > > * add bdrv_flush() to ensure data is stable on disk (Stefan) > > > > Patch 11/19: * fixed typos in comments (Stefan) > > * QEMU coding style changes (Stefan) > > * rename bat_entry to bat_entry_le for clarity (Stefan) > > * Add PAYLOAD_BLOCK_ZERO explicit zero padding for > >protocols that do not support zero init (Stefan) > > * rename PAYLOAD_BLOCK_FULL_PRESENT to > >PAYLOAD_BLOCK_FULLY_PRESENT (Stefan) > > > > Patch 13/19: * Fixed typo in commit message (Stefan) > > > > Patch 19/19: * New, adds qemu-io test for log replay of data sector > > > > v6 Patch 17/20: * Dropped (already upstream) > > v6 Patch 18/20: * Dropped (already upstream) > > > > > > > > === v6 changes === > > https://github.com/codyprime/qemu-kvm-jtc/tree/vhdx-write-v6-upstream > > > > Rebased to latest qemu/master: > > > > Patch 16/20: .bdrv_create() propagates Error, and bdrv_unref() used > > instead of bdrv_delete(). > > > > Patch 17 & 18 are already included in another series: > > [PATCH v3 0/3] qemu-iotests with sample images, vhdx test, cleanup > > > > They are included here to provide a base for patches 19 & 20. If the above > > series is applied before this series, then patches 17 and 18 can be ignored. > > > > Patch 19/20: In qemu-io tests _make_test_img(), filter out vhdx-specific > > options for .bdrv_create(). > > > > Patch 20/20: Add VHDX write test case to 064. > > > > > > === v5 changes === > > > > v5 is also available for testing from: > > https://github.com/codyprime/qemu-kvm-jtc/tree/vhdx-write-v5-upstream > > > > Most of the patches from v4 -> v5 are the same, but there are a few > > differences > > and a few new patches. Here is a summary of which patches are different > > and/or > > new: > > > > Patch highlights: > > > > Patch 7 just some minor code movement, in prep for changes in patch 8 > > > > Patch 8 incorporates review feedback from Stefan, for the previous Patch 7 > > in v4. > > > > Patch 9 adds region checking for log, region table, and metadata tables, > > per > > suggestion from Stefan. > > > > Patch 10 minor change from changes made in 8/16 (vhdx_guid_is_zero() is > > gone) > > > > Patch 12 is just some minor housekeeping, to get rid of bit shifting that > > doesn't need to happen. > > > > > > > > === v4 changes === > > > > v4 patches are available from github as well, on branch > > vhdx-write-v4-upstream: > > https://github.com/codyprime/qemu-kvm-jtc/tree/vhdx-write-v4-upstream > > https://github.com/codyprime/qemu-kvm-jtc.git > > > > Those in the midst of reviewing v3, don't fear - the only changes with v4 is > > the addition of patches on the end of the series (patches 10-13). These > > patches enable creating VHDX images. Image files created have been > > (briefly & lightly) tested on Hyper-V running on Windows Server 2012. > > > > Some of the new patches could be squashed with earlier patches in the > > series, > > but I refrained from doing so, since some of the patches have already been > > reviewed, and others are in the midst of review. I want to make it as easy > > as possible on those currently reviewing. There is nothing critical > > that needs to be pushed into the earlier patches. > > > > New patches: > > > > Patch 1
[Qemu-devel] [PATCH v5 0/2] sheepdog: add user-defined redundancy option
v5: - use pstrcpy instead of strncpy - fix a segfalt for 'null' string option string v4: - fix do_sd_create that forgot to pass nr_copies - fix parse_redundancy dealing with replicated vdi v3: - rework is_numeric v2: - fix a typo in comment and commit log This patch set add one sheepdog specific option for qemu-img to control redundancy. This patch set is on top of Kevin's block tree. Liu Yuan (2): sheepdog: refactor do_sd_create() sheepdog: support user-defined redundancy option block/sheepdog.c | 127 + include/block/block_int.h |1 + 2 files changed, 105 insertions(+), 23 deletions(-) -- 1.7.9.5
Re: [Qemu-devel] How to introduce bs->node_name ?
On Fri, 01 Nov 2013 08:59:20 -0600 Eric Blake wrote: > On 11/01/2013 08:51 AM, Luiz Capitulino wrote: > > On Wed, 30 Oct 2013 13:25:35 -0600 > > Eric Blake wrote: > > > >> On 10/30/2013 07:49 AM, Markus Armbruster wrote: > >> > >>> > >>> The first proposal is to add another parameter, say "id". Users can > >>> then refer either to an arbitrary BDS by "id", or (for backward > >>> compatibility) to the root BDS by "device". When the code sees > >>> "device", it'll look up the BB, then fetch its root BDS. > >>> > >>> CON: Existing parameter "device" becomes compatibility cruft. > >>> > >>> PRO: Clean and obvious semantics (in my opinion). > >> > >> I like this one as well. > > > > Does this proposal makes "device" optional for existing commands? If it > > does then I'm afraid it breaks compatibility because if you don't > > specify a device you'll get an error today. > > Changing from error to success is not backwards-incompatible. Old > applications will ALWAYS supply device (because it used to be > mandatory). That is, a management application that was intentionally > omitting 'device' and expecting an error is so unlikely to exist that we > can consider such a management app as buggy. Doing such changes makes me nervous nevertheless. In my mind a stable API doesn't change. Of course that there might exceptions, but 99.9% of those exceptions should be bug fixes not deliberate API extensions. A more compelling argument against it is the quality of the resulting command. I'm sure it's going to be anything but a simple, clean API. Anyways, let's wait for a concrete proposal to have more concrete feedback.
[Qemu-devel] [PATCH v5 2/2] sheepdog: support user-defined redundancy option
Sheepdog support two kinds of redundancy, full replication and erasure coding.
# create a fully replicated vdi with x copies
-o redundancy=x (1 <= x <= SD_MAX_COPIES)
# create a erasure coded vdi with x data strips and y parity strips
-o redundancy=x:y (x must be one of {2,4,8,16} and 1 <= y < SD_EC_MAX_STRIP)
E.g, to convert a vdi into sheepdog vdi 'test' with 8:3 erasure coding scheme
$ qemu-img convert -o redundancy=8:3 linux-0.2.img sheepdog:test
Cc: Kevin Wolf
Cc: Stefan Hajnoczi
Signed-off-by: Liu Yuan
---
block/sheepdog.c | 90 -
include/block/block_int.h |1 +
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 66b3ea8..a267d31 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -91,6 +91,14 @@
#define SD_NR_VDIS (1U << 24)
#define SD_DATA_OBJ_SIZE (UINT64_C(1) << 22)
#define SD_MAX_VDI_SIZE (SD_DATA_OBJ_SIZE * MAX_DATA_OBJS)
+/*
+ * For erasure coding, we use at most SD_EC_MAX_STRIP for data strips and
+ * (SD_EC_MAX_STRIP - 1) for parity strips
+ *
+ * SD_MAX_COPIES is sum of number of data trips and parity strips.
+ */
+#define SD_EC_MAX_STRIP 16
+#define SD_MAX_COPIES (SD_EC_MAX_STRIP * 2 - 1)
#define SD_INODE_SIZE (sizeof(SheepdogInode))
#define CURRENT_VDI_ID 0
@@ -1495,6 +1503,7 @@ static int do_sd_create(BDRVSheepdogState *s, uint32_t
*vdi_id, int snapshot)
hdr.data_length = wlen;
hdr.vdi_size = s->inode.vdi_size;
hdr.copy_policy = s->inode.copy_policy;
+hdr.copies = s->inode.nr_copies;
ret = do_req(fd, (SheepdogReq *)&hdr, buf, &wlen, &rlen);
@@ -1562,6 +1571,76 @@ out:
return ret;
}
+static bool is_numeric(const char *s)
+{
+const char *p = s;
+
+if (*p) {
+char c;
+
+while ((c = *p++))
+if (!isdigit(c)) {
+return false;
+}
+return true;
+}
+return false;
+}
+
+/*
+ * Sheepdog support two kinds of redundancy, full replication and erasure
+ * coding.
+ *
+ * # create a fully replicated vdi with x copies
+ * -o redundancy=x (1 <= x <= SD_MAX_COPIES)
+ *
+ * # create a erasure coded vdi with x data strips and y parity strips
+ * -o redundancy=x:y (x must be one of {2,4,8,16} and 1 <= y < SD_EC_MAX_STRIP)
+ */
+static int parse_redundancy(BDRVSheepdogState *s, const char *opt)
+{
+struct SheepdogInode *inode = &s->inode;
+const char *n1, *n2;
+uint8_t copy, parity;
+char p[10];
+
+pstrcpy(p, sizeof(p), opt);
+n1 = strtok(p, ":");
+n2 = strtok(NULL, ":");
+
+if (!n1 || !is_numeric(n1) || (n2 && !is_numeric(n2))) {
+return -EINVAL;
+}
+
+copy = strtol(n1, NULL, 10);
+if (copy > SD_MAX_COPIES) {
+return -EINVAL;
+}
+if (!n2) {
+inode->copy_policy = 0;
+inode->nr_copies = copy;
+return 0;
+}
+
+if (copy != 2 && copy != 4 && copy != 8 && copy != 16) {
+return -EINVAL;
+}
+
+parity = strtol(n2, NULL, 10);
+if (parity >= SD_EC_MAX_STRIP || parity == 0) {
+return -EINVAL;
+}
+
+/*
+ * 4 bits for parity and 4 bits for data.
+ * We have to compress upper data bits because it can't represent 16
+ */
+inode->copy_policy = ((copy / 2) << 4) + parity;
+inode->nr_copies = copy + parity;
+
+return 0;
+}
+
static int sd_create(const char *filename, QEMUOptionParameter *options,
Error **errp)
{
@@ -1602,6 +1681,11 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
ret = -EINVAL;
goto out;
}
+} else if (!strcmp(options->name, BLOCK_OPT_REDUNDANCY)) {
+ret = parse_redundancy(s, options->value.s);
+if (ret < 0) {
+goto out;
+}
}
options++;
}
@@ -1644,7 +1728,6 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
bdrv_unref(bs);
}
-/* TODO: allow users to specify copy number */
ret = do_sd_create(s, &vid, 0);
if (!prealloc || ret) {
goto out;
@@ -2416,6 +2499,11 @@ static QEMUOptionParameter sd_create_options[] = {
.type = OPT_STRING,
.help = "Preallocation mode (allowed values: off, full)"
},
+{
+.name = BLOCK_OPT_REDUNDANCY,
+.type = OPT_STRING,
+.help = "Redundancy of the image"
+},
{ NULL }
};
diff --git a/include/block/block_int.h b/include/block/block_int.h
index a48731d..b90862f 100644
--- a/include/block/block_int.h
+++ b/include/block/block_int.h
@@ -53,6 +53,7 @@
#define BLOCK_OPT_COMPAT_LEVEL "compat"
#define BLOCK_OPT_LAZY_REFCOUNTS"lazy_refcounts"
#define BLOCK_OPT_ADAPTER_TYPE "adapter_type"
+#define BLOCK_OPT_REDUNDANCY"redundancy"
typedef struct BdrvTrackedRequest {
BlockDriverState *bs;
--
1.7.9.5
[Qemu-devel] [PATCH v5 1/2] sheepdog: refactor do_sd_create()
We can actually use BDRVSheepdogState *s to pass most of the parameters.
Cc: Kevin Wolf
Cc: Stefan Hajnoczi
Signed-off-by: Liu Yuan
---
block/sheepdog.c | 37 +++--
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index ef387de..66b3ea8 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -1464,9 +1464,7 @@ out:
return ret;
}
-static int do_sd_create(BDRVSheepdogState *s, char *filename, int64_t vdi_size,
-uint32_t base_vid, uint32_t *vdi_id, int snapshot,
-uint8_t copy_policy)
+static int do_sd_create(BDRVSheepdogState *s, uint32_t *vdi_id, int snapshot)
{
SheepdogVdiReq hdr;
SheepdogVdiRsp *rsp = (SheepdogVdiRsp *)&hdr;
@@ -1483,11 +1481,11 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
* does not fit in buf? For now, just truncate and avoid buffer overrun.
*/
memset(buf, 0, sizeof(buf));
-pstrcpy(buf, sizeof(buf), filename);
+pstrcpy(buf, sizeof(buf), s->name);
memset(&hdr, 0, sizeof(hdr));
hdr.opcode = SD_OP_NEW_VDI;
-hdr.vdi_id = base_vid;
+hdr.vdi_id = s->inode.vdi_id;
wlen = SD_MAX_VDI_LEN;
@@ -1495,8 +1493,8 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
hdr.snapid = snapshot;
hdr.data_length = wlen;
-hdr.vdi_size = vdi_size;
-hdr.copy_policy = copy_policy;
+hdr.vdi_size = s->inode.vdi_size;
+hdr.copy_policy = s->inode.copy_policy;
ret = do_req(fd, (SheepdogReq *)&hdr, buf, &wlen, &rlen);
@@ -1507,7 +1505,7 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
}
if (rsp->result != SD_RES_SUCCESS) {
-error_report("%s, %s", sd_strerror(rsp->result), filename);
+error_report("%s, %s", sd_strerror(rsp->result), s->inode.name);
return -EIO;
}
@@ -1568,23 +1566,21 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
Error **errp)
{
int ret = 0;
-uint32_t vid = 0, base_vid = 0;
-int64_t vdi_size = 0;
+uint32_t vid = 0;
char *backing_file = NULL;
BDRVSheepdogState *s;
-char vdi[SD_MAX_VDI_LEN], tag[SD_MAX_VDI_TAG_LEN];
+char tag[SD_MAX_VDI_TAG_LEN];
uint32_t snapid;
bool prealloc = false;
Error *local_err = NULL;
s = g_malloc0(sizeof(BDRVSheepdogState));
-memset(vdi, 0, sizeof(vdi));
memset(tag, 0, sizeof(tag));
if (strstr(filename, "://")) {
-ret = sd_parse_uri(s, filename, vdi, &snapid, tag);
+ret = sd_parse_uri(s, filename, s->name, &snapid, tag);
} else {
-ret = parse_vdiname(s, filename, vdi, &snapid, tag);
+ret = parse_vdiname(s, filename, s->name, &snapid, tag);
}
if (ret < 0) {
goto out;
@@ -1592,7 +1588,7 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
while (options && options->name) {
if (!strcmp(options->name, BLOCK_OPT_SIZE)) {
-vdi_size = options->value.n;
+s->inode.vdi_size = options->value.n;
} else if (!strcmp(options->name, BLOCK_OPT_BACKING_FILE)) {
backing_file = options->value.s;
} else if (!strcmp(options->name, BLOCK_OPT_PREALLOC)) {
@@ -1610,7 +1606,7 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
options++;
}
-if (vdi_size > SD_MAX_VDI_SIZE) {
+if (s->inode.vdi_size > SD_MAX_VDI_SIZE) {
error_report("too big image size");
ret = -EINVAL;
goto out;
@@ -1645,12 +1641,11 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
goto out;
}
-base_vid = s->inode.vdi_id;
bdrv_unref(bs);
}
/* TODO: allow users to specify copy number */
-ret = do_sd_create(s, vdi, vdi_size, base_vid, &vid, 0, 0);
+ret = do_sd_create(s, &vid, 0);
if (!prealloc || ret) {
goto out;
}
@@ -1833,8 +1828,7 @@ static int sd_create_branch(BDRVSheepdogState *s)
* false bail out.
*/
deleted = sd_delete(s);
-ret = do_sd_create(s, s->name, s->inode.vdi_size, s->inode.vdi_id, &vid,
- !deleted, s->inode.copy_policy);
+ret = do_sd_create(s, &vid, !deleted);
if (ret) {
goto out;
}
@@ -2097,8 +2091,7 @@ static int sd_snapshot_create(BlockDriverState *bs,
QEMUSnapshotInfo *sn_info)
goto cleanup;
}
-ret = do_sd_create(s, s->name, s->inode.vdi_size, s->inode.vdi_id,
&new_vid,
- 1, s->inode.copy_policy);
+ret = do_sd_create(s, &new_vid, 1);
if (ret < 0) {
error_report("failed to create inode for snapshot. %s",
strerror(errno));
--
1.7.9.5
[Qemu-devel] [PATCH v5 RESENT 0/2] sheepdog: add user-defined redundancy option
v5: - use pstrcpy instead of strncpy - fix a segfalt for 'null' string option string v4: - fix do_sd_create that forgot to pass nr_copies - fix parse_redundancy dealing with replicated vdi v3: - rework is_numeric v2: - fix a typo in comment and commit log This patch set add one sheepdog specific option for qemu-img to control redundancy. This patch set is on top of Kevin's block tree. Liu Yuan (2): sheepdog: refactor do_sd_create() sheepdog: support user-defined redundancy option block/sheepdog.c | 127 + include/block/block_int.h |1 + 2 files changed, 105 insertions(+), 23 deletions(-) -- 1.7.9.5
Re: [Qemu-devel] [PATCH v5 0/2] sheepdog: add user-defined redundancy option
On Fri, Nov 01, 2013 at 11:06:20PM +0800, Liu Yuan wrote: > v5: > - use pstrcpy instead of strncpy > - fix a segfalt for 'null' string option string Oops, I sent the old patch set. Please ignore it I'll send a new v5. Thanks Yuan
[Qemu-devel] [PATCH v5 1/2] sheepdog: refactor do_sd_create()
We can actually use BDRVSheepdogState *s to pass most of the parameters.
Cc: Kevin Wolf
Cc: Stefan Hajnoczi
Signed-off-by: Liu Yuan
---
block/sheepdog.c | 37 +++--
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index ef387de..66b3ea8 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -1464,9 +1464,7 @@ out:
return ret;
}
-static int do_sd_create(BDRVSheepdogState *s, char *filename, int64_t vdi_size,
-uint32_t base_vid, uint32_t *vdi_id, int snapshot,
-uint8_t copy_policy)
+static int do_sd_create(BDRVSheepdogState *s, uint32_t *vdi_id, int snapshot)
{
SheepdogVdiReq hdr;
SheepdogVdiRsp *rsp = (SheepdogVdiRsp *)&hdr;
@@ -1483,11 +1481,11 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
* does not fit in buf? For now, just truncate and avoid buffer overrun.
*/
memset(buf, 0, sizeof(buf));
-pstrcpy(buf, sizeof(buf), filename);
+pstrcpy(buf, sizeof(buf), s->name);
memset(&hdr, 0, sizeof(hdr));
hdr.opcode = SD_OP_NEW_VDI;
-hdr.vdi_id = base_vid;
+hdr.vdi_id = s->inode.vdi_id;
wlen = SD_MAX_VDI_LEN;
@@ -1495,8 +1493,8 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
hdr.snapid = snapshot;
hdr.data_length = wlen;
-hdr.vdi_size = vdi_size;
-hdr.copy_policy = copy_policy;
+hdr.vdi_size = s->inode.vdi_size;
+hdr.copy_policy = s->inode.copy_policy;
ret = do_req(fd, (SheepdogReq *)&hdr, buf, &wlen, &rlen);
@@ -1507,7 +1505,7 @@ static int do_sd_create(BDRVSheepdogState *s, char
*filename, int64_t vdi_size,
}
if (rsp->result != SD_RES_SUCCESS) {
-error_report("%s, %s", sd_strerror(rsp->result), filename);
+error_report("%s, %s", sd_strerror(rsp->result), s->inode.name);
return -EIO;
}
@@ -1568,23 +1566,21 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
Error **errp)
{
int ret = 0;
-uint32_t vid = 0, base_vid = 0;
-int64_t vdi_size = 0;
+uint32_t vid = 0;
char *backing_file = NULL;
BDRVSheepdogState *s;
-char vdi[SD_MAX_VDI_LEN], tag[SD_MAX_VDI_TAG_LEN];
+char tag[SD_MAX_VDI_TAG_LEN];
uint32_t snapid;
bool prealloc = false;
Error *local_err = NULL;
s = g_malloc0(sizeof(BDRVSheepdogState));
-memset(vdi, 0, sizeof(vdi));
memset(tag, 0, sizeof(tag));
if (strstr(filename, "://")) {
-ret = sd_parse_uri(s, filename, vdi, &snapid, tag);
+ret = sd_parse_uri(s, filename, s->name, &snapid, tag);
} else {
-ret = parse_vdiname(s, filename, vdi, &snapid, tag);
+ret = parse_vdiname(s, filename, s->name, &snapid, tag);
}
if (ret < 0) {
goto out;
@@ -1592,7 +1588,7 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
while (options && options->name) {
if (!strcmp(options->name, BLOCK_OPT_SIZE)) {
-vdi_size = options->value.n;
+s->inode.vdi_size = options->value.n;
} else if (!strcmp(options->name, BLOCK_OPT_BACKING_FILE)) {
backing_file = options->value.s;
} else if (!strcmp(options->name, BLOCK_OPT_PREALLOC)) {
@@ -1610,7 +1606,7 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
options++;
}
-if (vdi_size > SD_MAX_VDI_SIZE) {
+if (s->inode.vdi_size > SD_MAX_VDI_SIZE) {
error_report("too big image size");
ret = -EINVAL;
goto out;
@@ -1645,12 +1641,11 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
goto out;
}
-base_vid = s->inode.vdi_id;
bdrv_unref(bs);
}
/* TODO: allow users to specify copy number */
-ret = do_sd_create(s, vdi, vdi_size, base_vid, &vid, 0, 0);
+ret = do_sd_create(s, &vid, 0);
if (!prealloc || ret) {
goto out;
}
@@ -1833,8 +1828,7 @@ static int sd_create_branch(BDRVSheepdogState *s)
* false bail out.
*/
deleted = sd_delete(s);
-ret = do_sd_create(s, s->name, s->inode.vdi_size, s->inode.vdi_id, &vid,
- !deleted, s->inode.copy_policy);
+ret = do_sd_create(s, &vid, !deleted);
if (ret) {
goto out;
}
@@ -2097,8 +2091,7 @@ static int sd_snapshot_create(BlockDriverState *bs,
QEMUSnapshotInfo *sn_info)
goto cleanup;
}
-ret = do_sd_create(s, s->name, s->inode.vdi_size, s->inode.vdi_id,
&new_vid,
- 1, s->inode.copy_policy);
+ret = do_sd_create(s, &new_vid, 1);
if (ret < 0) {
error_report("failed to create inode for snapshot. %s",
strerror(errno));
--
1.7.9.5
[Qemu-devel] [PATCH v5 2/2] sheepdog: support user-defined redundancy option
Sheepdog support two kinds of redundancy, full replication and erasure coding.
# create a fully replicated vdi with x copies
-o redundancy=x (1 <= x <= SD_MAX_COPIES)
# create a erasure coded vdi with x data strips and y parity strips
-o redundancy=x:y (x must be one of {2,4,8,16} and 1 <= y < SD_EC_MAX_STRIP)
E.g, to convert a vdi into sheepdog vdi 'test' with 8:3 erasure coding scheme
$ qemu-img convert -o redundancy=8:3 linux-0.2.img sheepdog:test
Cc: Kevin Wolf
Cc: Stefan Hajnoczi
Signed-off-by: Liu Yuan
---
block/sheepdog.c | 90 -
include/block/block_int.h |1 +
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 66b3ea8..6f5a523 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -91,6 +91,14 @@
#define SD_NR_VDIS (1U << 24)
#define SD_DATA_OBJ_SIZE (UINT64_C(1) << 22)
#define SD_MAX_VDI_SIZE (SD_DATA_OBJ_SIZE * MAX_DATA_OBJS)
+/*
+ * For erasure coding, we use at most SD_EC_MAX_STRIP for data strips and
+ * (SD_EC_MAX_STRIP - 1) for parity strips
+ *
+ * SD_MAX_COPIES is sum of number of data trips and parity strips.
+ */
+#define SD_EC_MAX_STRIP 16
+#define SD_MAX_COPIES (SD_EC_MAX_STRIP * 2 - 1)
#define SD_INODE_SIZE (sizeof(SheepdogInode))
#define CURRENT_VDI_ID 0
@@ -1495,6 +1503,7 @@ static int do_sd_create(BDRVSheepdogState *s, uint32_t
*vdi_id, int snapshot)
hdr.data_length = wlen;
hdr.vdi_size = s->inode.vdi_size;
hdr.copy_policy = s->inode.copy_policy;
+hdr.copies = s->inode.nr_copies;
ret = do_req(fd, (SheepdogReq *)&hdr, buf, &wlen, &rlen);
@@ -1562,6 +1571,76 @@ out:
return ret;
}
+static bool is_numeric(const char *s)
+{
+const char *p = s;
+
+if (*p) {
+char c;
+
+while ((c = *p++))
+if (!isdigit(c)) {
+return false;
+}
+return true;
+}
+return false;
+}
+
+/*
+ * Sheepdog support two kinds of redundancy, full replication and erasure
+ * coding.
+ *
+ * # create a fully replicated vdi with x copies
+ * -o redundancy=x (1 <= x <= SD_MAX_COPIES)
+ *
+ * # create a erasure coded vdi with x data strips and y parity strips
+ * -o redundancy=x:y (x must be one of {2,4,8,16} and 1 <= y < SD_EC_MAX_STRIP)
+ */
+static int parse_redundancy(BDRVSheepdogState *s, const char *opt)
+{
+struct SheepdogInode *inode = &s->inode;
+const char *n1, *n2;
+uint8_t copy, parity;
+char p[10];
+
+strncpy(p, opt, sizeof(p));
+n1 = strtok(p, ":");
+n2 = strtok(NULL, ":");
+
+if ((n1 && !is_numeric(n1)) || (n2 && !is_numeric(n2))) {
+return -EINVAL;
+}
+
+copy = strtol(n1, NULL, 10);
+if (copy > SD_MAX_COPIES) {
+return -EINVAL;
+}
+if (!n2) {
+inode->copy_policy = 0;
+inode->nr_copies = copy;
+return 0;
+}
+
+if (copy != 2 && copy != 4 && copy != 8 && copy != 16) {
+return -EINVAL;
+}
+
+parity = strtol(n2, NULL, 10);
+if (parity >= SD_EC_MAX_STRIP || parity == 0) {
+return -EINVAL;
+}
+
+/*
+ * 4 bits for parity and 4 bits for data.
+ * We have to compress upper data bits because it can't represent 16
+ */
+inode->copy_policy = ((copy / 2) << 4) + parity;
+inode->nr_copies = copy + parity;
+
+return 0;
+}
+
static int sd_create(const char *filename, QEMUOptionParameter *options,
Error **errp)
{
@@ -1602,6 +1681,11 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
ret = -EINVAL;
goto out;
}
+} else if (!strcmp(options->name, BLOCK_OPT_REDUNDANCY)) {
+ret = parse_redundancy(s, options->value.s);
+if (ret < 0) {
+goto out;
+}
}
options++;
}
@@ -1644,7 +1728,6 @@ static int sd_create(const char *filename,
QEMUOptionParameter *options,
bdrv_unref(bs);
}
-/* TODO: allow users to specify copy number */
ret = do_sd_create(s, &vid, 0);
if (!prealloc || ret) {
goto out;
@@ -2416,6 +2499,11 @@ static QEMUOptionParameter sd_create_options[] = {
.type = OPT_STRING,
.help = "Preallocation mode (allowed values: off, full)"
},
+{
+.name = BLOCK_OPT_REDUNDANCY,
+.type = OPT_STRING,
+.help = "Redundancy of the image"
+},
{ NULL }
};
diff --git a/include/block/block_int.h b/include/block/block_int.h
index a48731d..b90862f 100644
--- a/include/block/block_int.h
+++ b/include/block/block_int.h
@@ -53,6 +53,7 @@
#define BLOCK_OPT_COMPAT_LEVEL "compat"
#define BLOCK_OPT_LAZY_REFCOUNTS"lazy_refcounts"
#define BLOCK_OPT_ADAPTER_TYPE "adapter_type"
+#define BLOCK_OPT_REDUNDANCY"redundancy"
typedef struct BdrvTrackedRequest {
BlockDriverState *bs;
--
1.7.9.5
Re: [Qemu-devel] How to introduce bs->node_name ?
On 11/01/2013 08:51 AM, Luiz Capitulino wrote: > On Wed, 30 Oct 2013 13:25:35 -0600 > Eric Blake wrote: > >> On 10/30/2013 07:49 AM, Markus Armbruster wrote: >> >>> >>> The first proposal is to add another parameter, say "id". Users can >>> then refer either to an arbitrary BDS by "id", or (for backward >>> compatibility) to the root BDS by "device". When the code sees >>> "device", it'll look up the BB, then fetch its root BDS. >>> >>> CON: Existing parameter "device" becomes compatibility cruft. >>> >>> PRO: Clean and obvious semantics (in my opinion). >> >> I like this one as well. > > Does this proposal makes "device" optional for existing commands? If it > does then I'm afraid it breaks compatibility because if you don't > specify a device you'll get an error today. Changing from error to success is not backwards-incompatible. Old applications will ALWAYS supply device (because it used to be mandatory). That is, a management application that was intentionally omitting 'device' and expecting an error is so unlikely to exist that we can consider such a management app as buggy. For more examples of conversion from error to success, consider the 'block-commit' command. As introduced in 1.3, we did not yet have the implementation to commit the current image. But we designed the command with a view to the future (which we are nearly at, by the way, although I don't know if it will make 1.7 or be delayed to 1.8). In fact, we specifically made the 'top' argument mandatory at the time, and documented that if 'top' was the active layer that the command would fail; but with the full intent of removing the error and instead succeeding once we implement full commit; we also discussed the possibility in the 1.3 time-frame that 'top' could be made optional once block-commit could manage the current image. > > Have you considered adding new commands instead? I'm still not convinced we need new commands yet. But again, proposing the QMP schema first will make that clearer. -- Eric Blake eblake redhat com+1-919-301-3266 Libvirt virtualization library http://libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] How to introduce bs->node_name ?
On Wed, 30 Oct 2013 13:25:35 -0600 Eric Blake wrote: > On 10/30/2013 07:49 AM, Markus Armbruster wrote: > > > > > The first proposal is to add another parameter, say "id". Users can > > then refer either to an arbitrary BDS by "id", or (for backward > > compatibility) to the root BDS by "device". When the code sees > > "device", it'll look up the BB, then fetch its root BDS. > > > > CON: Existing parameter "device" becomes compatibility cruft. > > > > PRO: Clean and obvious semantics (in my opinion). > > I like this one as well. Does this proposal makes "device" optional for existing commands? If it does then I'm afraid it breaks compatibility because if you don't specify a device you'll get an error today. Have you considered adding new commands instead? > > I think we should review with the QMP schema first, code second. > > Yes, get the interface right, and then it's easier to review the code > that implements the interface. Agreed.
Re: [Qemu-devel] [RFC] vmstate: Add info vmstate HMP command (WIP)
On Thu, 24 Oct 2013 16:34:50 +0100 Andreas Färber wrote: > This adds a command "info vmstate" for dumping a textual representation > of the currently registered VMStateDescriptions. > > Being purely for debugging, intentionally no QMP schema is set in stone. We had a discussion in the past about prefixing such QMP commands with x- or adding a special vendor extension for them. I don't remember the conclusion there, although I see that we do have x-rdma-pin-all in the schema.
[Qemu-devel] [Bug 1246012] Re: QEMU removes postgresql
Agreed, closing against QEMU project. If you feel this is a bug in the ubuntu qemu package, then please target it as such (but I suspect that will also become invalid) ** Changed in: qemu Status: Incomplete => Invalid -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1246012 Title: QEMU removes postgresql Status in QEMU: Invalid Bug description: >sudo apt-get install kvm virt-manager removed postgresql-9.2 from my system. Furthermore, it seem impossible for me to run postgresql and qemu at the same time. Starting one, kills the other. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1246012/+subscriptions
Re: [Qemu-devel] [PATCH 0/6] qapi: generate event defines automatically
On Mon, 21 Oct 2013 10:15:59 +0800
Wenchao Xia wrote:
> This series move the event define to qapi code, so later other components
> could use it easily, it also make monitor code less and easier to decouple
> with other code.
Yes, this is an improvement over the current code. But it doesn't move
in the direction we (or better Anthony) originally had for events in
the QAPI.
Basically, *iirc*, the idea was to have an event type, so that we could
declare events as:
{ 'event': 'BLOCK_IO_ERROR', 'data': { 'device': 'str',
'operation': 'str',
'action': 'str' } }
(Note that keys 'operation' and 'action' should be enums)
Then the QAPI could generate C functions to register and de-register from
an event. This way C code could benefit from events too, and we could
also allow QMP clients to register/de-register to/from events.
Maybe we could apply this series as a first step, but I can't tell if
later on we'll regret it due to compatibility issues or if we'll realize
it was unneeded churn.
Re: [Qemu-devel] [sheepdog] [PATCH v4 2/2] sheepdog: support user-defined redundancy option
At Thu, 31 Oct 2013 13:49:28 +0800,
Liu Yuan wrote:
>
> +/*
> + * Sheepdog support two kinds of redundancy, full replication and erasure
> + * coding.
> + *
> + * # create a fully replicated vdi with x copies
> + * -o redundancy=x (1 <= x <= SD_MAX_COPIES)
> + *
> + * # create a erasure coded vdi with x data strips and y parity strips
> + * -o redundancy=x:y (x must be one of {2,4,8,16} and 1 <= y <
> SD_EC_MAX_STRIP)
> + */
> +static int parse_redundancy(BDRVSheepdogState *s, const char *opt)
> +{
> +struct SheepdogInode *inode = &s->inode;
> +const char *n1, *n2;
> +uint8_t copy, parity;
> +char p[10];
> +
> +strncpy(p, opt, sizeof(p));
strncpy() is not safe here. Please use pstrcpy() instead.
> +n1 = strtok(p, ":");
> +n2 = strtok(NULL, ":");
> +
> +if ((n1 && !is_numeric(n1)) || (n2 && !is_numeric(n2))) {
> +return -EINVAL;
> +}
This cannot detect an error when 'opt' is empty. Actually, the
following command causes a segfault.
$ qemu-img create -o redundancy= sheepdog:test 4G
Thanks,
Kazutaka
Re: [Qemu-devel] [libvirt] QEMU 1.6 and drive discard parameter
Hey guys,
I've just rolled out Qemu 1.6 to fix problems I've been having, which worked
fine .. but I've now
lost discard support which is a problem. Is there an easy / quick fix for this
without digging through
other people's code? I'm happy to compile up whatever is necessary, I just need
the "discard" option
to work for Libvirt / Qemu 1.6 ...
tia
Gareth.
On Thu, Oct 31, 2013 at 04:35:43PM +0800, Amos Kong wrote:
> On Thu, Oct 31, 2013 at 04:07:15PM +0800, Osier Yang wrote:
> > CC to Amos.
> >
> > On 30/10/13 16:19, whitearchey wrote:
> > >
> > >In QEMU 1.6 parameters of 'drive' option were removed:
> > >
> > >QemuOptsList qemu_drive_opts = {
> > >.name = "drive",
> > >.head = QTAILQ_HEAD_INITIALIZER(qemu_drive_opts.head),
> > >.desc = {
> > >/*
> > > * no elements => accept any params
> > > * validation will happen later
> > > */
> > >{ /* end of list */ }
> > >},
> > >};
> > >
> > >But libvirt still checks for QEMU_CAPS_DRIVE_DISCARD using QMP
> > >query-command-line-options:
> > >
> > >static struct virQEMUCapsCommandLineProps virQEMUCapsCommandLine[] = {
> > >{ "machine", "mem-merge", QEMU_CAPS_MEM_MERGE },
> > >{ "drive", "discard", QEMU_CAPS_DRIVE_DISCARD },
> > >{ "realtime", "mlock", QEMU_CAPS_MLOCK },
> > >};
> > >...
> > >qemuMonitorGetCommandLineOptionParameters(mon,
> > >virQEMUCapsCommandLine[i].option, &values)
> > >
> > >So, when I try to use discard option in domain xml I get this error:
> > >
> > >error : qemuBuildDriveStr:3986 : unsupported configuration:
> > >discard is not supported by this QEMU binary
> > >
> >
> > It's a qemu problem, the command "query-command-line-options" should
> > keep working
> > after the structures were changed for any option, in this case, all
> > the option descs were
> > moved to "qemu_common_drive_opts" instead.
>
> { 'execute': 'query-command-line-options', 'arguments': { 'option': 'drive' }
> }
>
> {
> "return": [
> {
> "parameters": [
> ],
> "option": "drive"
> }
> ]
> }
>
> It returns a NULL parameters list, that's true, some error handling
> should be done by libvirt.
Re: [Qemu-devel] savevm/loadvm
Hi,
Sorry I'm just now replying to this. I ran into the same issue (and
another one) and it should be fixed by the upstream commits
eedff66f21e542650d895801549ce05ac108278b and
6e13610aa454beba52944e8df6d93158d68ab911. Those have been merged to
master yesterday, so could you re-build qemu from master and try again?
Kind regards,
Max
On 08.10.2013 10:40, Alexey Kardashevskiy wrote:
> Hi!
>
> I need the community help with savevm/loadvm.
>
> I run QEMU like this:
>
> ./qemu-system-ppc64 \
> -drive file=virtimg/fc19_16GB.qcow2 \
> -nodefaults \
> -m "2048" \
> -machine "pseries" \
> -nographic \
> -vga "none" \
> -enable-kvm
>
>
> The disk image is an 16GB qcow2 image.
>
> Now I start the guest and do "savevm 1" and "loadvm 1" from the qemu
> console. Everything works. Then I exit qemu, make sure that the snapshot is
> there and run QEMU as above plus "-loadvm 1". It fails with:
>
> qemu-system-ppc64: qcow2: Loading snapshots with different disk size is not
> implemented
> qemu-system-ppc64: Error -95 while activating snapshot '2' on 'scsi0-hd0'
>
> The check is added by commit 90b277593df873d3a2480f002e2eb5fe1f8e5277
> "qcow2: Save disk size in snapshot header".
>
> As I cannot realize the whole idea of the patch, I looked a bit deeper.
> This is the check:
>
> int qcow2_snapshot_goto(BlockDriverState *bs, const char *snapshot_id)
> {
> [...]
> if (sn->disk_size != bs->total_sectors * BDRV_SECTOR_SIZE) {
> error_report("qcow2: Loading snapshots with different disk "
> "size is not implemented");
> ret = -ENOTSUP;
> goto fail;
> }
>
>
> My understanding of the patch was that the disk_size should remain 16GB
> (0x4..) as it uses bs->total_sectors and never changes it. And
> bs->growable is 0 for qcow2 image because it is not really growable. At
> least the total_sectors value from the qcow2 file header does not change
> between QEMU starts.
>
> However qcow2_save_vmstate() sets bs->growable to 1 for a short time
> (commit 178e08a58f40dd5aef2ce774fe0850f5d0e56918 from 2009) and this
> triggers a branch in bdrv_co_do_writev() which changes bs->total_sectors.
> So when QEMU writes snapshots to the file, the disk_size field of a
> snapshot has bigger value (for example 0x4.007b.8180).
>
> And the check above fails. It does not fail if to do "loadvm"
> _in_the_same_run_ after "savevm" because QEMU operates with the updated
> bs->total_sectors.
>
> What the proper fix would be? Or it is not a bug at all and I should be
> using something else for "-loadvm"? Thanks.
>
>
>
Re: [Qemu-devel] [PATCH 3/6] qapi: rename prefix QEVENT to Q_EVENT
On Tue, 29 Oct 2013 10:09:40 -0600 Eric Blake wrote: > On 10/28/2013 11:22 PM, Wenchao Xia wrote: > > >> > > MONITOR_EVENT seems tide to monitor too much, since it will be present > > in qapi-schema, I think Q_EVENT_ or QMP_EVENT_KIND would be better? > > I don't have a strong enough opinion on the bikeshed color. > MONITOR_EVENT implies the event is always associated with delivery over > a monitor; but how else would you receive an event without a monitor? Today QMP is tied to the Monitor, but one of the goals of the QAPI is to untangle them. This would allow for a separate QMP server, which could have QMP only features like session support.
Re: [Qemu-devel] [PATCH 2/6] qapi: rename MonitorEvent to QEvent
On Mon, 21 Oct 2013 10:16:01 +0800
Wenchao Xia wrote:
> Signed-off-by: Wenchao Xia
> ---
> block.c|2 +-
> include/block/block_int.h |2 +-
> include/monitor/monitor.h |6 +++---
> monitor.c | 12 ++--
> stubs/mon-protocol-event.c |2 +-
> ui/vnc.c |2 +-
> 6 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/block.c b/block.c
> index 2c15e5d..458a4f8 100644
> --- a/block.c
> +++ b/block.c
> @@ -1760,7 +1760,7 @@ void bdrv_set_dev_ops(BlockDriverState *bs, const
> BlockDevOps *ops,
> }
>
> void bdrv_emit_qmp_error_event(const BlockDriverState *bdrv,
> - MonitorEvent ev,
> + QEvent ev,
> BlockErrorAction action, bool is_read)
> {
> QObject *data;
> diff --git a/include/block/block_int.h b/include/block/block_int.h
> index bcc72e2..bfdaf84 100644
> --- a/include/block/block_int.h
> +++ b/include/block/block_int.h
> @@ -337,7 +337,7 @@ AioContext *bdrv_get_aio_context(BlockDriverState *bs);
> int is_windows_drive(const char *filename);
> #endif
> void bdrv_emit_qmp_error_event(const BlockDriverState *bdrv,
> - MonitorEvent ev,
> + QEvent ev,
> BlockErrorAction action, bool is_read);
>
> /**
> diff --git a/include/monitor/monitor.h b/include/monitor/monitor.h
> index 10fa0e3..8b14a6f 100644
> --- a/include/monitor/monitor.h
> +++ b/include/monitor/monitor.h
> @@ -20,7 +20,7 @@ extern Monitor *default_mon;
> #define MONITOR_CMD_ASYNC 0x0001
>
> /* QMP events */
> -typedef enum MonitorEvent {
> +typedef enum QEvent {
Qt has a QEvent class, so QEvent is not a good name for us if we're
considering making it public in the schema (which could become an
external library in the distant future).
I suggest calling it QMPEvent.
> QEVENT_SHUTDOWN,
> QEVENT_RESET,
> QEVENT_POWERDOWN,
> @@ -54,11 +54,11 @@ typedef enum MonitorEvent {
> * defining new events here */
>
> QEVENT_MAX,
> -} MonitorEvent;
> +} QEvent;
>
> int monitor_cur_is_qmp(void);
>
> -void monitor_protocol_event(MonitorEvent event, QObject *data);
> +void monitor_protocol_event(QEvent event, QObject *data);
> void monitor_init(CharDriverState *chr, int flags);
>
> int monitor_suspend(Monitor *mon);
> diff --git a/monitor.c b/monitor.c
> index 74f3f1b..9377834 100644
> --- a/monitor.c
> +++ b/monitor.c
> @@ -175,7 +175,7 @@ typedef struct MonitorControl {
> * instance.
> */
> typedef struct MonitorEventState {
> -MonitorEvent event; /* Event being tracked */
> +QEvent event; /* Event being tracked */
> int64_t rate; /* Period over which to throttle. 0 to disable */
> int64_t last; /* Time at which event was last emitted */
> QEMUTimer *timer; /* Timer for handling delayed events */
> @@ -517,7 +517,7 @@ QemuMutex monitor_event_state_lock;
> * Emits the event to every monitor instance
> */
> static void
> -monitor_protocol_event_emit(MonitorEvent event,
> +monitor_protocol_event_emit(QEvent event,
> QObject *data)
> {
> Monitor *mon;
> @@ -536,7 +536,7 @@ monitor_protocol_event_emit(MonitorEvent event,
> * applying any rate limiting if required.
> */
> static void
> -monitor_protocol_event_queue(MonitorEvent event,
> +monitor_protocol_event_queue(QEvent event,
> QObject *data)
> {
> MonitorEventState *evstate;
> @@ -614,7 +614,7 @@ static void monitor_protocol_event_handler(void *opaque)
> * milliseconds
> */
> static void
> -monitor_protocol_event_throttle(MonitorEvent event,
> +monitor_protocol_event_throttle(QEvent event,
> int64_t rate)
> {
> MonitorEventState *evstate;
> @@ -650,7 +650,7 @@ static void monitor_protocol_event_init(void)
> *
> * Event-specific data can be emitted through the (optional) 'data'
> parameter.
> */
> -void monitor_protocol_event(MonitorEvent event, QObject *data)
> +void monitor_protocol_event(QEvent event, QObject *data)
> {
> QDict *qmp;
> const char *event_name;
> @@ -1067,7 +1067,7 @@ CommandInfoList *qmp_query_commands(Error **errp)
> EventInfoList *qmp_query_events(Error **errp)
> {
> EventInfoList *info, *ev_list = NULL;
> -MonitorEvent e;
> +QEvent e;
>
> for (e = 0 ; e < QEVENT_MAX ; e++) {
> const char *event_name = monitor_event_names[e];
> diff --git a/stubs/mon-protocol-event.c b/stubs/mon-protocol-event.c
> index 0946e94..e769729 100644
> --- a/stubs/mon-protocol-event.c
> +++ b/stubs/mon-protocol-event.c
> @@ -1,6 +1,6 @@
> #include "qemu-common.h"
> #include "monitor/monitor.h"
>
> -void monitor_protocol_event(MonitorEvent event, QObject *data)
> +void monitor_protocol_event(QEvent event, QObject *data)
> {
> }
> diff --git a/ui/vnc.c b/u
Re: [Qemu-devel] savevm/loadvm
On 10/16/2013 05:51 PM, Alexey Kardashevskiy wrote:
> On 10/10/2013 02:50 PM, Alexey Kardashevskiy wrote:
>> On 10/09/2013 06:47 PM, Paolo Bonzini wrote:
>>> Il 09/10/2013 09:15, Alexey Kardashevskiy ha scritto:
Sorry for my ignorance (I never ever touched this part of qemu) but how can
you possibly avoid block.c while doing savevm? The qcow2 driver must not
use posix read()/write(), right? So no matter how, all writes end up in
bdrv_co_do_writev() which changes blocks number. Or use
raw_aio_readv()/raw_aio_writev() API directly? Please give some more hints.
Thanks.
>>>
>>> I think Kevin was suggesting using qcow_aio_writev directly, or
>>> something like that. But it is not trivial, especially because
>>> save_vm_state takes byte offsets instead of sectors. So for now I'd
>>> still go for the more hacky solution.
>>
>> I failed to find qcow_aio_writev() or anything like that. qcow2_co_writev()
>> uses block.c. And I tried this:
>>
>> diff --git a/block/qcow2.c b/block/qcow2.c
>> index 4a9888c..17faf8b 100644
>> --- a/block/qcow2.c
>> +++ b/block/qcow2.c
>> @@ -1837,10 +1837,16 @@ static int qcow2_save_vmstate(BlockDriverState *bs,
>> QEMUIOVector *qiov,
>> BDRVQcowState *s = bs->opaque;
>> int growable = bs->growable;
>> int ret;
>> +int64_t total_sectors = bs->total_sectors;
>>
>> BLKDBG_EVENT(bs->file, BLKDBG_VMSTATE_SAVE);
>> bs->growable = 1;
>> ret = bdrv_pwritev(bs, qcow2_vm_state_offset(s) + pos, qiov);
>> +/*
>> + * Setting @growable may cause underlying bdrv_co_do_writev()
>> + * to increase bs->total_sectors and we do not want this to happen.
>> + */
>> +bs->total_sectors = total_sectors;
>> bs->growable = growable;
>>
>> return ret;
>>
>>
>> It breaks loadvm in a different (weird) way, the error is something like
>> "ram" or "spapr/htab" (streams registered with register_savevm_live())
>> chunk cannot be read. Need to debug more...
>
>
> Just to keep the conversation going :) The patch below helps while the
> patch above creates snapshots which cannot be loaded.
>
> And there is no qcow_aio_writev-like API to fix it, what did you mean?
>
> Why not just revert the breaking patch?
Ping? Or it is all fixed now?
> Thanks.
>
> diff --git a/savevm.c b/savevm.c
> index e0c8aee..aeda0d1 100644
> --- a/savevm.c
> +++ b/savevm.c
> @@ -42,6 +42,7 @@
> #include "qemu/iov.h"
> #include "block/snapshot.h"
> #include "block/qapi.h"
> +#include "block/block_int.h"
>
> #define SELF_ANNOUNCE_ROUNDS 5
>
> @@ -2389,6 +2390,7 @@ void do_savevm(Monitor *mon, const QDict *qdict)
> qemu_timeval tv;
> struct tm tm;
> const char *name = qdict_get_try_str(qdict, "name");
> +int64_t total_sectors;
>
> /* Verify if there is a device that doesn't support snapshots and is
> writable */
> bs = NULL;
> @@ -2442,6 +2444,7 @@ void do_savevm(Monitor *mon, const QDict *qdict)
> }
>
> /* save the VM state */
> +total_sectors = bs->total_sectors;
> f = qemu_fopen_bdrv(bs, 1);
> if (!f) {
> monitor_printf(mon, "Could not open VM state file\n");
> @@ -2450,6 +2453,11 @@ void do_savevm(Monitor *mon, const QDict *qdict)
> ret = qemu_savevm_state(f);
> vm_state_size = qemu_ftell(f);
> qemu_fclose(f);
> +/*
> + * Setting @growable may cause underlying bdrv_co_do_writev()
> + * to increase bs->total_sectors and we do not want this to happen.
> + */
> +bs->total_sectors = total_sectors;
> if (ret < 0) {
> monitor_printf(mon, "Error %d while writing VM\n", ret);
> goto the_end;
>
>
>
>
--
Alexey
[Qemu-devel] [PATCH V3 06/19] Add VSX ISA2.06 xmul Instructions
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
V2: re-implemented VSX_MUL macro.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |3 +++
target-ppc/translate.c |6 ++
3 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index a577d28..51ca589 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1809,3 +1809,49 @@ VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+/* VSX_MUL - VSX floating point multiply
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_MUL(op, nels, tp, fld, sfprf)\
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xt, xa, xb;\
+int i; \
+ \
+getVSR(xA(opcode), &xa, env);\
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_mul(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(xb.fld[i])) || \
+(tp##_is_infinity(xb.fld[i]) && tp##_is_zero(xa.fld[i]))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf);\
+} else if (tp##_is_signaling_nan(xa.fld[i]) || \
+ tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+ \
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_MUL(xsmuldp, 1, float64, f64, 1)
+VSX_MUL(xvmuldp, 2, float64, f64, 0)
+VSX_MUL(xvmulsp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 966200d..ecb900f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -253,12 +253,15 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
+DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
+DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
+DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d20b269..1fb21b7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7297,12 +7297,15 @@ static void gen_##name(DisasContext * ctx)
\
GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
GE
[Qemu-devel] [Bug 1246990] Re: [qemu-x86-64-linux-user 1.6.1] qemu: uncaught target signal 11 (Segmentation fault) - core dumped
and, `strace ./rjsuuplicant -n eth0 -u USER -p PASS -d 1 -s internet` is attached as strace_native.log ** Attachment added: "strace_native.log" https://bugs.launchpad.net/qemu/+bug/1246990/+attachment/3897370/+files/strace_native.log ** Also affects: qemu (Ubuntu) Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1246990 Title: [qemu-x86-64-linux-user 1.6.1] qemu: uncaught target signal 11 (Segmentation fault) - core dumped Status in QEMU: New Status in “qemu” package in Ubuntu: New Bug description: Rjsupplicant is an authentication client of Campus Network in most universities in China. Its Linux version has only x86 and amd64 version. On linux: ./qemu-x86_64 is compiled from latest qemu 1.6.1, with ./configure options: --enable-debug --target-list=x86_64-linux-user . Compiler is gcc version 4.7.3 (Debian 4.7.3-4) $ sudo ./qemu-x86_64 ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet qemu: uncaught target signal 11 (Segmentation fault) - core dumped $ sudo gdb ./qemu-x86_64 (gdb) r ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet (gdb) where #0 0x559c21bd in static_code_gen_buffer () #1 0x555b74d5 in cpu_tb_exec (cpu=0x57972580, tb_ptr=0x559c2190 "A\213n\250\205\355\017\205\257") at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:56 #2 0x555b817d in cpu_x86_exec (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:631 #3 0x555d997a in cpu_loop (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/main.c:283 #4 0x555eca6b in clone_func (arg=0x7fffc1d0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/syscall.c:4266 #5 0x771bfe0e in start_thread (arg=0x77f04700) at pthread_create.c:311 #6 0x76ef493d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:113 $ file rjsupplicant rjsupplicant: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux 2.6.9, not stripped $ uname -r 3.10-2-amd64 And it can be run on Linux amd64 successfully. Though I don't have the source code of rjsupplicant, so I don't have further information. `qemu-x86_64 -strace ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet` is attached as strace_qemu.log The binary is available to download at http://ge.tt/6pgG1tw/v/0 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1246990/+subscriptions
[Qemu-devel] [Bug 1246990] [NEW] [qemu-x86-64-linux-user 1.6.1] qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Public bug reported: Rjsupplicant is an authentication client of Campus Network in most universities in China. Its Linux version has only x86 and amd64 version. On linux: ./qemu-x86_64 is compiled from latest qemu 1.6.1, with ./configure options: --enable-debug --target-list=x86_64-linux-user . Compiler is gcc version 4.7.3 (Debian 4.7.3-4) $ sudo ./qemu-x86_64 ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet qemu: uncaught target signal 11 (Segmentation fault) - core dumped $ sudo gdb ./qemu-x86_64 (gdb) r ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet (gdb) where #0 0x559c21bd in static_code_gen_buffer () #1 0x555b74d5 in cpu_tb_exec (cpu=0x57972580, tb_ptr=0x559c2190 "A\213n\250\205\355\017\205\257") at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:56 #2 0x555b817d in cpu_x86_exec (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:631 #3 0x555d997a in cpu_loop (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/main.c:283 #4 0x555eca6b in clone_func (arg=0x7fffc1d0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/syscall.c:4266 #5 0x771bfe0e in start_thread (arg=0x77f04700) at pthread_create.c:311 #6 0x76ef493d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:113 $ file rjsupplicant rjsupplicant: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux 2.6.9, not stripped $ uname -r 3.10-2-amd64 And it can be run on Linux amd64 successfully. Though I don't have the source code of rjsupplicant, so I don't have further information. `qemu-x86_64 -strace ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet` is attached as strace_qemu.log The binary is available to download at http://ge.tt/6pgG1tw/v/0 ** Affects: qemu Importance: Undecided Status: New ** Affects: qemu (Ubuntu) Importance: Undecided Status: New ** Attachment added: "strace_qemu.log" https://bugs.launchpad.net/bugs/1246990/+attachment/3897368/+files/strace_qemu.log -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1246990 Title: [qemu-x86-64-linux-user 1.6.1] qemu: uncaught target signal 11 (Segmentation fault) - core dumped Status in QEMU: New Status in “qemu” package in Ubuntu: New Bug description: Rjsupplicant is an authentication client of Campus Network in most universities in China. Its Linux version has only x86 and amd64 version. On linux: ./qemu-x86_64 is compiled from latest qemu 1.6.1, with ./configure options: --enable-debug --target-list=x86_64-linux-user . Compiler is gcc version 4.7.3 (Debian 4.7.3-4) $ sudo ./qemu-x86_64 ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet qemu: uncaught target signal 11 (Segmentation fault) - core dumped $ sudo gdb ./qemu-x86_64 (gdb) r ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet (gdb) where #0 0x559c21bd in static_code_gen_buffer () #1 0x555b74d5 in cpu_tb_exec (cpu=0x57972580, tb_ptr=0x559c2190 "A\213n\250\205\355\017\205\257") at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:56 #2 0x555b817d in cpu_x86_exec (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/cpu-exec.c:631 #3 0x555d997a in cpu_loop (env=0x579726b0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/main.c:283 #4 0x555eca6b in clone_func (arg=0x7fffc1d0) at /home/USER/x/rjsupplicant/x64/qemu-1.6.1/linux-user/syscall.c:4266 #5 0x771bfe0e in start_thread (arg=0x77f04700) at pthread_create.c:311 #6 0x76ef493d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:113 $ file rjsupplicant rjsupplicant: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), dynamically linked (uses shared libs), for GNU/Linux 2.6.9, not stripped $ uname -r 3.10-2-amd64 And it can be run on Linux amd64 successfully. Though I don't have the source code of rjsupplicant, so I don't have further information. `qemu-x86_64 -strace ./rjsupplicant -n eth0 -u USER -p PASS -d 1 -s internet` is attached as strace_qemu.log The binary is available to download at http://ge.tt/6pgG1tw/v/0 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1246990/+subscriptions
[Qemu-devel] [PATCH V3 19/19] Add VSX Rounding Instructions
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
- xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
- xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 68 +++
target-ppc/helper.h | 15 ++
target-ppc/translate.c | 30
3 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index f913ad7..f3d02cc 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2548,3 +2548,71 @@ VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, u64[i],
f32[j], \
2*i + JOFFSET, 0)
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0)
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0)
+
+/* For "use current rounding mode", define a value that will not be one of
+ * the existing rounding model enums.
+ */
+#define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
+ float_round_up + float_round_to_zero)
+
+/* VSX_ROUND - VSX floating point round
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * rmode - rounding mode
+ * sfprf - set FPRF
+ */
+#define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode)\
+{ \
+ppc_vsr_t xt, xb; \
+int i; \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+ \
+if (rmode != FLOAT_ROUND_CURRENT) {\
+set_float_rounding_mode(rmode, &env->fp_status); \
+} \
+ \
+for (i = 0; i < nels; i++) { \
+if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
+} else { \
+xt.fld[i] = tp##_round_to_int(xb.fld[i], &env->fp_status); \
+} \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf);\
+} \
+} \
+ \
+/* If this is not a "use current rounding mode" instruction, \
+ * then inhibit setting of the XX bit and restore rounding \
+ * mode from FPSCR */ \
+if (rmode != FLOAT_ROUND_CURRENT) {\
+fpscr_set_rounding_mode(env); \
+env->fp_status.float_exception_flags &= ~float_flag_inexact; \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env);\
+}
+
+VSX_ROUND(xsrdpi, 1, float64, f64, float_round_nearest_even, 1)
+VSX_ROUND(xsrdpic, 1, float64, f64, FLOAT_ROUND_CURRENT, 1)
+VSX_ROUND(xsrdpim, 1, float64, f64, float_round_down, 1)
+VSX_ROUND(xsrdpip, 1, float64, f64, float_round_up, 1)
+VSX_ROUND(xsrdpiz, 1, float64, f64, float_round_to_zero, 1)
+
+VSX_ROUND(xvrdpi, 2, float64, f64, float_round_nearest_even, 0)
+VSX_ROUND(xvrdpic, 2, float64, f64, FLOAT_ROUND_CURRENT, 0)
+VSX_ROUND(xvrdpim, 2, float64, f64, float_round_down, 0)
+VSX_ROUND(xvrdpip, 2, float64, f64, float_round_up, 0)
+VSX_ROUND(xvrdpiz, 2, float64, f64, float_round_to_zero, 0)
+
+VSX_ROUND(xvrspi, 4, float32, f32, float_round_nearest_even, 0)
+VSX_ROUND(xvrspic, 4, float32, f32, FLOAT_ROUND_CURRENT, 0)
+VSX_ROUND(xvrspim, 4, float32, f32, float_round_down, 0)
+VSX_ROUND(xvrspip, 4, float32, f32, float_round_up, 0)
+VSX_ROUND(xvrspiz, 4, float32, f32, float_round_to_zero, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index de46b6f..0276b02 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -280,6 +280,11 @@ DEF_HELPER_2(xscvd
[Qemu-devel] [PATCH V3 17/19] Add VSX Floating Point to Floating Point Conversion Instructions
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |4
target-ppc/translate.c |8
3 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index ec1df4f..c9fb59f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2395,3 +2395,49 @@ VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define JOFFSET 0
+#else
+#define JOFFSET 1
+#endif
+
+/* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * stp - source type (float32 or float64)
+ * ttp - target type (float32 or float64)
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf)\
+void helper_##op(CPUPPCState *env, uint32_t opcode)\
+{ \
+ppc_vsr_t xt, xb; \
+int i; \
+ \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+ \
+for (i = 0; i < nels; i++) { \
+int j = 2*i + JOFFSET; \
+xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);\
+if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+} \
+if (sfprf) { \
+helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
+&env->fp_status), sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env);\
+}
+
+VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, f64[i], f32[j], 1)
+VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], f64[i], 1)
+VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
+VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 35389c5..dd9518c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -272,6 +272,8 @@ DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -295,6 +297,7 @@ DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HELPER_2(xvcmpeqdp, void, env, i32)
DEF_HELPER_2(xvcmpgedp, void, env, i32)
DEF_HELPER_2(xvcmpgtdp, void, env, i32)
+DEF_HELPER_2(xvcvdpsp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -318,6 +321,7 @@ DEF_HELPER_2(xvminsp, void, env, i32)
DEF_HELPER_2(xvcmpeqsp, void, env, i32)
DEF_HELPER_2(xvcmpgesp, void, env, i32)
DEF_HELPER_2(xvcmpgtsp, void, env, i32)
+DEF_HELPER_2(xvcvspdp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 377a482..1366ced 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7316,6 +7316,8 @@ GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7339,6 +7341,7 @@ GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E,
[Qemu-devel] [PATCH V3 16/19] Add VSX Vector Compare Instructions
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 57 +++
target-ppc/helper.h |6 +
target-ppc/translate.c | 23 +++
3 files changed, 86 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b90541c..ec1df4f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2338,3 +2338,60 @@ VSX_MAX_MIN(xvmaxsp, max, 4, float32, f32)
VSX_MAX_MIN(xsmindp, min, 1, float64, f64)
VSX_MAX_MIN(xvmindp, min, 2, float64, f64)
VSX_MAX_MIN(xvminsp, min, 4, float32, f32)
+
+/* VSX_CMP - VSX floating point compare
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * cmp - comparison operation
+ * svxvc - set VXVC bit
+ */
+#define VSX_CMP(op, nels, tp, fld, cmp, svxvc)\
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xa, xb; \
+int i;\
+int all_true = 1; \
+int all_false = 1;\
+ \
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+ \
+for (i = 0; i < nels; i++) { \
+if (unlikely(tp##_is_any_nan(xa.fld[i]) ||\
+ tp##_is_any_nan(xb.fld[i]))) { \
+if (tp##_is_signaling_nan(xa.fld[i]) || \
+tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);\
+} \
+if (svxvc) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+} \
+xt.fld[i] = 0;\
+all_true = 0; \
+} else { \
+if (tp##_##cmp(xb.fld[i], xa.fld[i], &env->fp_status) == 1) { \
+xt.fld[i] = -1; \
+all_false = 0;\
+} else { \
+xt.fld[i] = 0;\
+all_true = 0; \
+} \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+if ((opcode >> (31-21)) & 1) {\
+env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
+} \
+helper_float_check_status(env); \
+ }
+
+VSX_CMP(xvcmpeqdp, 2, float64, f64, eq, 0)
+VSX_CMP(xvcmpgedp, 2, float64, f64, le, 1)
+VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
+VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
+VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
+VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4a65d39..35389c5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -292,6 +292,9 @@ DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
DEF_HELPER_2(xvmaxdp, void, env, i32)
DEF_HELPER_2(xvmindp, void, env, i32)
+DEF_HELPER_2(xvcmpeqdp, void, env, i32)
+DEF_HELPER_2(xvcmpgedp, void, env, i32)
+DEF_HELPER_2(xvcmpgtdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -312,6 +315,9 @@ DEF_HELPER_2(xvnmsubasp, void, env, i32)
DEF_HELPER_2(xvnmsubmsp, void, env
[Qemu-devel] [PATCH V3 15/19] Add VSX xmax/xmin Instructions
This patch adds the VSX floating point maximum and minimum
instructions:
- xsmaxdp, xvmaxdp, xvmaxsp
- xsmindp, xvmindp, xvminsp
Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
V2: consolidated into a single macro, using the softfloat
float*_max/float*_min routines.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 50 +++
target-ppc/helper.h |6 +
target-ppc/translate.c | 12 +++
3 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index eb5d878..b90541c 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2288,3 +2288,53 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_SCALAR_CMP(xscmpodp, 1)
VSX_SCALAR_CMP(xscmpudp, 0)
+
+#define float64_snan_to_qnan(x) ((x) | 0x0008ul)
+#define float32_snan_to_qnan(x) ((x) | 0x0040)
+
+/* VSX_MAX_MIN - VSX floating point maximum/minimum
+ * name - instruction mnemonic
+ * op- operation (max or min)
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ */
+#define VSX_MAX_MIN(name, op, nels, tp, fld) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xa, xb; \
+int i;\
+ \
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+ \
+for (i = 0; i < nels; i++) { \
+if (unlikely(tp##_is_any_nan(xa.fld[i]) ||\
+ tp##_is_any_nan(xb.fld[i]))) { \
+if (tp##_is_signaling_nan(xa.fld[i])) { \
+xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]); \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);\
+} else if (tp##_is_signaling_nan(xb.fld[i])) {\
+xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);\
+} else if (tp##_is_quiet_nan(xb.fld[i])) {\
+xt.fld[i] = xa.fld[i];\
+} else { /* XA is QNaN */ \
+xt.fld[i] = xb.fld[i];\
+} \
+} else { \
+xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env); \
+}
+
+VSX_MAX_MIN(xsmaxdp, max, 1, float64, f64)
+VSX_MAX_MIN(xvmaxdp, max, 2, float64, f64)
+VSX_MAX_MIN(xvmaxsp, max, 4, float32, f32)
+VSX_MAX_MIN(xsmindp, min, 1, float64, f64)
+VSX_MAX_MIN(xvmindp, min, 2, float64, f64)
+VSX_MAX_MIN(xvminsp, min, 4, float32, f32)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index cd72388..4a65d39 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -270,6 +270,8 @@ DEF_HELPER_2(xsnmsubadp, void, env, i32)
DEF_HELPER_2(xsnmsubmdp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
+DEF_HELPER_2(xsmaxdp, void, env, i32)
+DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -288,6 +290,8 @@ DEF_HELPER_2(xvnmaddadp, void, env, i32)
DEF_HELPER_2(xvnmaddmdp, void, env, i32)
DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
+DEF_HELPER_2(xvmaxdp, void, env, i32)
+DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HE
[Qemu-devel] [PATCH V3 18/19] Add VSX ISA2.06 Integer Conversion Instructions
This patch adds the VSX Integer Conversion instructions defined by
V2.06 of the PowerPC ISA:
- xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws
- xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws
- xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws
- xscvsxddp, xscvuxddp
- xvcvsxddp, xscvsxwdp, xvcvuxddp, xvcvuxwdp
- xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 107 +++
target-ppc/helper.h | 22 ++
target-ppc/translate.c | 44 +++
3 files changed, 173 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c9fb59f..f913ad7 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2441,3 +2441,110 @@ VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, f64[i],
f32[j], 1)
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], f64[i], 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
+
+/* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * stp - source type (float32 or float64)
+ * ttp - target type (int32, uint32, int64 or uint64)
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field
+ * jdef - definition of the j index (i or 2*i)
+ * rnan - resulting NaN
+ */
+#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, jdef, rnan)\
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xt, xb;\
+int i; \
+ \
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+ \
+for (i = 0; i < nels; i++) { \
+int j = jdef;\
+if (unlikely(stp##_is_any_nan(xb.sfld))) { \
+if (stp##_is_signaling_nan(xb.sfld)) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+}\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);\
+xt.tfld = rnan; \
+} else { \
+xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
+if (env->fp_status.float_exception_flags & float_flag_invalid) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);\
+}\
+}\
+}\
+ \
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, f64[j], u64[i], i, \
+ 0x8000ul)
+VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, f64[i], u32[j], \
+ 2*i + JOFFSET, 0x8000l)
+VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, f64[j], u64[i], i, 0ul)
+VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, f64[i], u32[j], \
+ 2*i + JOFFSET, 0)
+VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, f64[j], u64[i], i, \
+ 0x8000ul)
+VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, f64[i], u32[j], \
+ 2*i + JOFFSET, 0x8000l)
+VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, f64[j], u64[i], i, 0ul)
+VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, f64[i], u32[j], \
+ 2*i + JOFFSET, 0)
+VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, f32[j], u64[i], \
+ 2*i + JOFFSET, 0x8000ul)
+VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, f32[j], u32[j], i, \
+ 0x8000l)
+VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, f32[j], u64[i], \
+ 2*i + JOFFSET, 0ul)
+VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, f32[j], u32[i], i, 0)
+
+/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
+ * op- instruction mnemonic
+ * nels - number of element
[Qemu-devel] [PATCH V3 10/19] Add VSX ISA2.06 xrsqrte Instructions
This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.
V2: re-implemented VSX_RSQRTE macro.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 45 +
target-ppc/helper.h |3 +++
target-ppc/translate.c |6 ++
3 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 060e6a0..31669f1 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1983,3 +1983,48 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_SQRT(xssqrtdp, 1, float64, f64, 1)
VSX_SQRT(xvsqrtdp, 2, float64, f64, 0)
VSX_SQRT(xvsqrtsp, 4, float32, f32, 0)
+
+/* VSX_RSQRTE - VSX floating point reciprocal square root estimate
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_RSQRTE(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xt, xb;\
+int i; \
+ \
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat);\
+xt.fld[i] = tp##_div(tp##_one, xt.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
+} else if (tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+ \
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1)
+VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0)
+VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a6e7e62..4d5e31b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -257,6 +257,7 @@ DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xssqrtdp, void, env, i32)
+DEF_HELPER_2(xsrsqrtedp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -264,6 +265,7 @@ DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvdivdp, void, env, i32)
DEF_HELPER_2(xvredp, void, env, i32)
DEF_HELPER_2(xvsqrtdp, void, env, i32)
+DEF_HELPER_2(xvrsqrtedp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -271,6 +273,7 @@ DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(xvdivsp, void, env, i32)
DEF_HELPER_2(xvresp, void, env, i32)
DEF_HELPER_2(xvsqrtsp, void, env, i32)
+DEF_HELPER_2(xvrsqrtesp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c5c97ba..287b924 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7301,6 +7301,7 @@ GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0,
[Qemu-devel] [PATCH V3 13/19] Add VSX ISA2.06 Multiply Add Instructions
This patch adds the VSX floating point multiply/add instructions
defined by V2.06 of the PowerPC ISA:
- xsmaddadp, xvmaddadp, xvmaddasp
- xsmaddmdp, xvmaddmdp, xvmaddmsp
- xsmsubadp, xvmsubadp, xvmsubasp
- xsmsubmdp, xvmsubmdp, xvmsubmsp
- xsnmaddadp, xvnmaddadp, xvnmaddasp
- xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
- xsnmsubadp, xvnmsubadp, xvnmsubasp
- xsnmsubmdp, xvnmsubmdp, xvnmsubmsp
V2: reworked implementation per comments from Richard Henderson and
Peter Maydell.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 100 +++
target-ppc/helper.h | 24 +++
target-ppc/translate.c | 48 ++
3 files changed, 172 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 73227b7..54c47c8 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2149,3 +2149,103 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_TSQRT(xstsqrtdp, 1, float64, f64, -1022, 52)
VSX_TSQRT(xvtsqrtdp, 2, float64, f64, -1022, 52)
VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
+
+/* VSX_MADD - VSX floating point muliply/add variations
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * maddflgs - flags for the float*muladd routine that control the
+ * various forms (madd, msub, nmadd, nmsub)
+ * afrm - A form (1=A, 0=M)
+ * sfprf - set FPRF
+ */
+#define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf)\
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt_in, xa, xb, xt_out; \
+ppc_vsr_t *b, *c; \
+int i;\
+ \
+if (afrm) { /* AxB + T */ \
+b = &xb; \
+c = &xt_in; \
+} else { /* AxT + B */\
+b = &xt_in; \
+c = &xb; \
+} \
+ \
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt_in, env); \
+ \
+xt_out = xt_in; \
+ \
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat); \
+xt_out.fld[i] = tp##_muladd(xa.fld[i], b->fld[i], c->fld[i], \
+ maddflgs, &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
+if (tp##_is_signaling_nan(xa.fld[i]) || \
+tp##_is_signaling_nan(b->fld[i]) || \
+tp##_is_signaling_nan(c->fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
+tstat.float_exception_flags &= ~float_flag_invalid; \
+} \
+if ((tp##_is_infinity(xa.fld[i]) && tp##_is_zero(b->fld[i])) || \
+(tp##_is_zero(xa.fld[i]) && tp##_is_infinity(b->fld[i]))) { \
+xt_out.fld[i] = float64_to_##tp(fload_invalid_op_excp(env,\
+POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \
+tstat.float_exception_flags &= ~float_flag_invalid; \
+}
[Qemu-devel] [PATCH V3 07/19] Add VSX ISA2.06 xdiv Instructions
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
V2: re-implemented the VSX_DIV macro.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 49 +++
target-ppc/helper.h |3 ++
target-ppc/translate.c |6 +
3 files changed, 58 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 51ca589..c84f432 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1855,3 +1855,52 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_MUL(xsmuldp, 1, float64, f64, 1)
VSX_MUL(xvmuldp, 2, float64, f64, 0)
VSX_MUL(xvmulsp, 4, float32, f32, 0)
+
+/* VSX_DIV - VSX floating point divide
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_DIV(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xa, xb; \
+int i;\
+ \
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat); \
+xt.fld[i] = tp##_div(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
+if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
+} else if (tp##_is_zero(xa.fld[i]) && \
+tp##_is_zero(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
+} else if (tp##_is_signaling_nan(xa.fld[i]) ||\
+tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
+} \
+} \
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env); \
+}
+
+VSX_DIV(xsdivdp, 1, float64, f64, 1)
+VSX_DIV(xvdivdp, 2, float64, f64, 0)
+VSX_DIV(xvdivsp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ecb900f..6ede7ea 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -254,14 +254,17 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
+DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
+DEF_HELPER_2(xvdivdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
DEF_HELPER_2(xvmulsp, void, env, i32)
+DEF_HELPER_2(xvdivsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1fb21b7..e77fcde 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7298,14 +7298,17 @@ static void gen_##name(DisasContext *
[Qemu-devel] [PATCH V3 14/19] Add VSX xscmp*dp Instructions
This patch adds the VSX scalar floating point compare ordered
and unordered instructions.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 39 +++
target-ppc/helper.h |2 ++
target-ppc/translate.c |4
3 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 54c47c8..eb5d878 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2249,3 +2249,42 @@ VSX_MADD(xvnmaddasp, 4, float32, f32, NMADD_FLGS, 1, 0)
VSX_MADD(xvnmaddmsp, 4, float32, f32, NMADD_FLGS, 0, 0)
VSX_MADD(xvnmsubasp, 4, float32, f32, NMSUB_FLGS, 1, 0)
VSX_MADD(xvnmsubmsp, 4, float32, f32, NMSUB_FLGS, 0, 0)
+
+#define VSX_SCALAR_CMP(op, ordered) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xa, xb;\
+uint32_t cc = 0; \
+ \
+getVSR(xA(opcode), &xa, env);\
+getVSR(xB(opcode), &xb, env);\
+ \
+if (unlikely(float64_is_any_nan(xa.f64[0]) ||\
+ float64_is_any_nan(xb.f64[0]))) { \
+if (float64_is_signaling_nan(xa.f64[0]) || \
+float64_is_signaling_nan(xb.f64[0])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+}\
+if (ordered) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+}\
+cc = 1; \
+} else { \
+if (float64_lt(xa.f64[0], xb.f64[0], &env->fp_status)) { \
+cc = 8; \
+} else if (!float64_le(xa.f64[0], xb.f64[0], &env->fp_status)) { \
+cc = 4; \
+} else { \
+cc = 2; \
+}\
+}\
+ \
+env->fpscr &= ~(0x0F << FPSCR_FPRF); \
+env->fpscr |= cc << FPSCR_FPRF; \
+env->crf[BF(opcode)] = cc; \
+ \
+helper_float_check_status(env); \
+}
+
+VSX_SCALAR_CMP(xscmpodp, 1)
+VSX_SCALAR_CMP(xscmpudp, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 7368908..cd72388 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -268,6 +268,8 @@ DEF_HELPER_2(xsnmaddadp, void, env, i32)
DEF_HELPER_2(xsnmaddmdp, void, env, i32)
DEF_HELPER_2(xsnmsubadp, void, env, i32)
DEF_HELPER_2(xsnmsubmdp, void, env, i32)
+DEF_HELPER_2(xscmpodp, void, env, i32)
+DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3a62125..a2a4e2d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7312,6 +7312,8 @@ GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10048,6 +10050,8 @@ GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
+GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
+GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
--
1.7.1
[Qemu-devel] [PATCH V3 05/19] Add VSX ISA2.06 xadd/xsub Instructions
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
V2: re-implemented helper macro and combined add and substract.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 51 +++
target-ppc/helper.h |9
target-ppc/translate.c | 18
3 files changed, 78 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index cea94ac..a577d28 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1758,3 +1758,54 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState
*env)
}
#define float64_to_float64(x, env) x
+
+
+/* VSX_ADD_SUB - VSX floating point add/subract
+ * name - instruction mnemonic
+ * op- operation (add or sub)
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \
+void helper_##name(CPUPPCState *env, uint32_t opcode)\
+{\
+ppc_vsr_t xt, xa, xb;\
+int i; \
+ \
+getVSR(xA(opcode), &xa, env);\
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &tstat); \
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);\
+} else if (tp##_is_signaling_nan(xa.fld[i]) || \
+ tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
+VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
+VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
+VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
+VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
+VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6d282bb..966200d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -251,6 +251,15 @@ DEF_HELPER_4(vcfsx, void, env, avr, avr, i32)
DEF_HELPER_4(vctuxs, void, env, avr, avr, i32)
DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
+DEF_HELPER_2(xsadddp, void, env, i32)
+DEF_HELPER_2(xssubdp, void, env, i32)
+
+DEF_HELPER_2(xvadddp, void, env, i32)
+DEF_HELPER_2(xvsubdp, void, env, i32)
+
+DEF_HELPER_2(xvaddsp, void, env, i32)
+DEF_HELPER_2(xvsubsp, void, env, i32)
+
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
DEF_HELPER_2(efscfuf, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0453900..d20b269 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7295,6 +7295,15 @@ static void gen_##name(DisasContext * ctx)
\
tcg_temp_free_i32(opc); \
}
+GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
+
+GEN_VSX_HELPER_2(xvadddp, 0x00, 0
[Qemu-devel] [PATCH V3 08/19] Add VSX ISA2.06 xre Instructions
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 35 +++
target-ppc/helper.h |3 +++
target-ppc/translate.c |6 ++
3 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c84f432..5908e41 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1904,3 +1904,38 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_DIV(xsdivdp, 1, float64, f64, 1)
VSX_DIV(xvdivdp, 2, float64, f64, 0)
VSX_DIV(xvdivsp, 4, float32, f32, 0)
+
+/* VSX_RE - VSX floating point reciprocal estimate
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_RE(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xt, xb; \
+int i;\
+ \
+getVSR(xB(opcode), &xb, env); \
+getVSR(xT(opcode), &xt, env); \
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+if (unlikely(tp##_is_signaling_nan(xb.fld[i]))) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);\
+} \
+xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status); \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[0], sfprf); \
+} \
+} \
+ \
+putVSR(xT(opcode), &xt, env); \
+helper_float_check_status(env); \
+}
+
+VSX_RE(xsredp, 1, float64, f64, 1)
+VSX_RE(xvredp, 2, float64, f64, 0)
+VSX_RE(xvresp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6ede7ea..fe5b61c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -255,16 +255,19 @@ DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
+DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvdivdp, void, env, i32)
+DEF_HELPER_2(xvredp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(xvdivsp, void, env, i32)
+DEF_HELPER_2(xvresp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e77fcde..d2060b7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7299,16 +7299,19 @@ GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op)\
static void glue(gen_, name)(DisasContext * ctx) \
@@ -9996,16 +,19 @@ GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
+GEN_XX2
[Qemu-devel] [PATCH V3 12/19] Add VSX ISA2.06 xtsqrt Instructions
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
V2: (a) using locally implemented ppc_float*_get_unbiased_exp
routines (b) eliminated dependency on float*_is_denormal().
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 54 +++
target-ppc/helper.h |3 ++
target-ppc/translate.c |6 +
3 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index ee03942..73227b7 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2095,3 +2095,57 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
+
+/* VSX_TSQRT - VSX floating point test for square root
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * emin - minimum unbiased exponent
+ * emax - maximum unbiased exponent
+ * nbits - number of fraction bits
+ */
+#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xa, xb; \
+int i; \
+int fe_flag = 0;\
+int fg_flag = 0;\
+\
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+\
+for (i = 0; i < nels; i++) {\
+if (unlikely(tp##_is_infinity(xb.fld[i]) || \
+ tp##_is_zero(xb.fld[i]))) {\
+fe_flag = 1;\
+fg_flag = 1;\
+} else {\
+int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
+\
+if (unlikely(tp##_is_any_nan(xb.fld[i]))) { \
+fe_flag = 1;\
+} else if (unlikely(tp##_is_zero(xb.fld[i]))) { \
+fe_flag = 1;\
+} else if (unlikely(tp##_is_neg(xb.fld[i]))) { \
+fe_flag = 1;\
+} else if (!tp##_is_zero(xb.fld[i]) && \
+ (e_b <= (emin+nbits))) { \
+fe_flag = 1;\
+} \
+\
+if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) {\
+/* XB is not zero because of the above check and */ \
+/* therefore must be denormalized. */ \
+fg_flag = 1;\
+} \
+} \
+} \
+\
+env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
+}
+
+VSX_TSQRT(xstsqrtdp, 1, float64, f64, -1022, 52)
+VSX_TSQRT(xvtsqrtdp, 2, float64, f64, -1022, 52)
+VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 80cffc9..c413c98 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -259,6 +259,7 @@ DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xssqrtdp, void, env, i32)
DEF_HELPER_2(xsrsqrtedp, void, env, i32)
DEF_HELPER_2(xstdivdp, void, env, i32)
+DEF_HELPER_2(xstsqrtdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -268,6 +269,7 @@ DEF_HELPER_2(xvredp, void, env, i32)
DEF_HELPER_2(xvsqrtdp, void, env, i32)
DEF_HELPER_2(xvrsqrtedp, void, env, i32)
DEF_HELPER_2(xvtdivdp, void, env, i32)
+DEF_HELPER_2(xvtsqrtdp, void, env, i32)
[Qemu-devel] [PATCH V3 09/19] Add VSX ISA2.06 xsqrt Instructions
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
V2: re-implemented the VSX_SQRT macro.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 44
target-ppc/helper.h |3 +++
target-ppc/translate.c |6 ++
3 files changed, 53 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 5908e41..060e6a0 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1939,3 +1939,47 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_RE(xsredp, 1, float64, f64, 1)
VSX_RE(xvredp, 2, float64, f64, 0)
VSX_RE(xvresp, 4, float32, f32, 0)
+
+/* VSX_SQRT - VSX floating point square root
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_SQRT(op, nels, tp, fld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{\
+ppc_vsr_t xt, xb;\
+int i; \
+ \
+getVSR(xB(opcode), &xb, env);\
+getVSR(xT(opcode), &xt, env);\
+helper_reset_fpstatus(env); \
+ \
+for (i = 0; i < nels; i++) { \
+float_status tstat = env->fp_status; \
+set_float_exception_flags(0, &tstat);\
+xt.fld[i] = tp##_sqrt(xb.fld[i], &tstat);\
+env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {\
+if (tp##_is_neg(xb.fld[i]) && !tp##_is_zero(xb.fld[i])) {\
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
+} else if (tp##_is_signaling_nan(xb.fld[i])) { \
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
+}\
+}\
+ \
+if (sfprf) { \
+helper_compute_fprf(env, xt.fld[i], sfprf); \
+}\
+}\
+ \
+putVSR(xT(opcode), &xt, env);\
+helper_float_check_status(env); \
+}
+
+VSX_SQRT(xssqrtdp, 1, float64, f64, 1)
+VSX_SQRT(xvsqrtdp, 2, float64, f64, 0)
+VSX_SQRT(xvsqrtsp, 4, float32, f32, 0)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index fe5b61c..a6e7e62 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -256,18 +256,21 @@ DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xsredp, void, env, i32)
+DEF_HELPER_2(xssqrtdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
DEF_HELPER_2(xvdivdp, void, env, i32)
DEF_HELPER_2(xvredp, void, env, i32)
+DEF_HELPER_2(xvsqrtdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
DEF_HELPER_2(xvmulsp, void, env, i32)
DEF_HELPER_2(xvdivsp, void, env, i32)
DEF_HELPER_2(xvresp, void, env, i32)
+DEF_HELPER_2(xvsqrtsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d2060b7..c5c97ba 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7300,18 +7300,21 @@ GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
[Qemu-devel] [PATCH V3 11/19] Add VSX ISA2.06 xtdiv Instructions
This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.
V2: added ppc_float*_get_unbiased_exp() routines (pulled back from
softfloat). Eliminated dependency on float*_is_denormalized()
routines.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 67 +++
target-ppc/helper.h |3 ++
target-ppc/translate.c |6
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 31669f1..ee03942 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2028,3 +2028,70 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1)
VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0)
VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0)
+
+static inline int ppc_float32_get_unbiased_exp(float32 f)
+{
+return ((f >> 23) & 0xFF) - 127;
+}
+
+static inline int ppc_float64_get_unbiased_exp(float64 f)
+{
+return ((f >> 52) & 0x7FF) - 1023;
+}
+
+/* VSX_TDIV - VSX floating point test for divide
+ * op- instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp- type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * emin - minimum unbiased exponent
+ * emax - maximum unbiased exponent
+ * nbits - number of fraction bits
+ */
+#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ppc_vsr_t xa, xb; \
+int i; \
+int fe_flag = 0;\
+int fg_flag = 0;\
+\
+getVSR(xA(opcode), &xa, env); \
+getVSR(xB(opcode), &xb, env); \
+\
+for (i = 0; i < nels; i++) {\
+if (unlikely(tp##_is_infinity(xa.fld[i]) || \
+ tp##_is_infinity(xb.fld[i]) || \
+ tp##_is_zero(xb.fld[i]))) {\
+fe_flag = 1;\
+fg_flag = 1;\
+} else {\
+int e_a = ppc_##tp##_get_unbiased_exp(xa.fld[i]); \
+int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
+\
+if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+fe_flag = 1;\
+} else if ((e_b <= emin) || (e_b >= (emax-2))) {\
+fe_flag = 1;\
+} else if (!tp##_is_zero(xa.fld[i]) && \
+ (((e_a - e_b) >= emax) ||\
+((e_a - e_b) <= (emin+1)) ||\
+ (e_a <= (emin+nbits { \
+fe_flag = 1;\
+} \
+\
+if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) {\
+/* XB is not zero because of the above check and */ \
+/* so must be denormalized. */ \
+fg_flag = 1;\
+} \
+} \
+} \
+\
+env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
+}
+
+VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
+VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
+VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4d5e31b..80cffc9 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -258,6 +258,7 @@ DEF_HELPER_2(xsdivdp, void, env, i32)
DEF_HELPER_2(xsredp, void, env
[Qemu-devel] [PATCH V3 04/19] General Support for VSX Helpers
This patch adds general support that will be used by the VSX helper
routines:
- a union describing the various VSR subfields.
- access routines to get and set VSRs
- VSX decoders
- a general routine to generate a handler that invokes a VSX
helper.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 41 +
target-ppc/translate.c | 14 ++
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index f0b0a49..cea94ac 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1717,3 +1717,44 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1,
uint64_t op2)
/* XXX: TODO: test special values (NaN, infinites, ...) */
return helper_efdtsteq(env, op1, op2);
}
+
+#define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
+(opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |\
+ (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
+
+#define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
+#define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
+#define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
+#define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5)
+#define BF(opcode) (((opcode) >> (31-8)) & 7)
+
+typedef union _ppc_vsr_t {
+uint64_t u64[2];
+uint32_t u32[4];
+float32 f32[4];
+float64 f64[2];
+} ppc_vsr_t;
+
+static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+if (n < 32) {
+vsr->f64[0] = env->fpr[n];
+vsr->u64[1] = env->vsr[n];
+} else {
+vsr->u64[0] = env->avr[n-32].u64[0];
+vsr->u64[1] = env->avr[n-32].u64[1];
+}
+}
+
+static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+if (n < 32) {
+env->fpr[n] = vsr->f64[0];
+env->vsr[n] = vsr->u64[1];
+} else {
+env->avr[n-32].u64[0] = vsr->u64[0];
+env->avr[n-32].u64[1] = vsr->u64[1];
+}
+}
+
+#define float64_to_float64(x, env) x
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ce07a56..0453900 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7280,6 +7280,20 @@ VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext * ctx)\
+{ \
+TCGv_i32 opc; \
+if (unlikely(!ctx->vsx_enabled)) {\
+gen_exception(ctx, POWERPC_EXCP_VSXU);\
+return; \
+} \
+/* NIP cannot be restored if the memory exception comes from an helper */ \
+gen_update_nip(ctx, ctx->nip - 4);\
+opc = tcg_const_i32(ctx->opcode); \
+gen_helper_##name(cpu_env, opc); \
+tcg_temp_free_i32(opc); \
+}
#define VSX_LOGICAL(name, tcg_op)\
static void glue(gen_, name)(DisasContext * ctx) \
--
1.7.1
[Qemu-devel] [PATCH V3 02/19] Add float32_to_uint64()
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
V2: Reduced patch to just this single routine per feedback from Peter
Maydell.
Signed-off-by: Tom Musta
---
fpu/softfloat.c | 45 +
include/fpu/softfloat.h |1 +
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3070eaa..cb03dca 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1550,6 +1550,51 @@ int64 float32_to_int64( float32 a STATUS_PARAM )
/*
| Returns the result of converting the single-precision floating-point value
+| `a' to the 64-bit unsigned integer format. The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode. If `a' is a NaN, the largest
+| unsigned integer is returned. Otherwise, if the conversion overflows, the
+| largest unsigned integer is returned. If the 'a' is negative, zero is
+| returned.
+**/
+
+uint64 float32_to_uint64(float32 a STATUS_PARAM)
+{
+flag aSign;
+int_fast16_t aExp, shiftCount;
+uint32_t aSig;
+uint64_t aSig64, aSigExtra;
+a = float32_squash_input_denormal(a STATUS_VAR);
+
+aSig = extractFloat32Frac(a);
+aExp = extractFloat32Exp(a);
+aSign = extractFloat32Sign(a);
+if (aSign) {
+if (aExp) {
+float_raise(float_flag_invalid STATUS_VAR);
+} else if (aSig) { /* negative denormalized */
+float_raise(float_flag_inexact STATUS_VAR);
+}
+return 0;
+}
+shiftCount = 0xBE - aExp;
+if (aExp) {
+aSig |= 0x0080;
+}
+if (shiftCount < 0) {
+float_raise(float_flag_invalid STATUS_VAR);
+return (int64_t)LIT64(0x);
+}
+
+aSig64 = aSig;
+aSig64 <<= 40;
+shift64ExtraRightJamming(aSig64, 0, shiftCount, &aSig64, &aSigExtra);
+return roundAndPackUint64(aSig64, aSigExtra STATUS_VAR);
+}
+
+/*
+| Returns the result of converting the single-precision floating-point value
| `a' to the 64-bit two's complement integer format. The conversion is
| performed according to the IEC/IEEE Standard for Binary Floating-Point
| Arithmetic, except that the conversion is always rounded toward zero. If
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index f3927e2..6448082 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -272,6 +272,7 @@ int32 float32_to_int32_round_to_zero( float32 STATUS_PARAM
);
uint32 float32_to_uint32( float32 STATUS_PARAM );
uint32 float32_to_uint32_round_to_zero( float32 STATUS_PARAM );
int64 float32_to_int64( float32 STATUS_PARAM );
+uint64 float32_to_uint64(float32 STATUS_PARAM);
int64 float32_to_int64_round_to_zero( float32 STATUS_PARAM );
float64 float32_to_float64( float32 STATUS_PARAM );
floatx80 float32_to_floatx80( float32 STATUS_PARAM );
--
1.7.1
[Qemu-devel] [PATCH V3 03/19] Add set_fprf Argument to fload_invalid_op_excp()
The fload_invalid_op_excp() function sets assorted invalid
operation status bits. However, it also implicitly modifies
the FPRF field of the PowerPC FPSCR. Many VSX instructions
set invalid operation bits but do not alter FPRF. Thus the
function is more generally useful if the setting of the FPRF
field is made conditional via a parameter.
All invocations of this routine in existing instructions are
modified to pass 1 and thus retain their current behavior.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 103 +--
1 files changed, 55 insertions(+), 48 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 4f60218..f0b0a49 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -106,7 +106,8 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t
arg, uint32_t set_fprf)
}
/* Floating-point invalid operations exception */
-static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
+static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
+ int set_fpcc)
{
uint64_t ret = 0;
int ve;
@@ -138,8 +139,10 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState
*env, int op)
case POWERPC_EXCP_FP_VXVC:
/* Ordered comparison of NaN */
env->fpscr |= 1 << FPSCR_VXVC;
-env->fpscr &= ~(0xF << FPSCR_FPCC);
-env->fpscr |= 0x11 << FPSCR_FPCC;
+if (set_fpcc) {
+env->fpscr &= ~(0xF << FPSCR_FPCC);
+env->fpscr |= 0x11 << FPSCR_FPCC;
+}
/* We must update the target FPR before raising the exception */
if (ve != 0) {
env->exception_index = POWERPC_EXCP_PROGRAM;
@@ -158,8 +161,10 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState
*env, int op)
if (ve == 0) {
/* Set the result to quiet NaN */
ret = 0x7FF8ULL;
-env->fpscr &= ~(0xF << FPSCR_FPCC);
-env->fpscr |= 0x11 << FPSCR_FPCC;
+if (set_fpcc) {
+env->fpscr &= ~(0xF << FPSCR_FPCC);
+env->fpscr |= 0x11 << FPSCR_FPCC;
+}
}
break;
case POWERPC_EXCP_FP_VXCVI:
@@ -169,8 +174,10 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState
*env, int op)
if (ve == 0) {
/* Set the result to quiet NaN */
ret = 0x7FF8ULL;
-env->fpscr &= ~(0xF << FPSCR_FPCC);
-env->fpscr |= 0x11 << FPSCR_FPCC;
+if (set_fpcc) {
+env->fpscr &= ~(0xF << FPSCR_FPCC);
+env->fpscr |= 0x11 << FPSCR_FPCC;
+}
}
break;
}
@@ -505,12 +512,12 @@ uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1,
uint64_t arg2)
if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d)
&&
float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
/* Magnitude subtraction of infinities */
-farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
+farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
} else {
if (unlikely(float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d))) {
/* sNaN addition */
-fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
}
@@ -529,12 +536,12 @@ uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1,
uint64_t arg2)
if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d)
&&
float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
/* Magnitude subtraction of infinities */
-farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
+farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
} else {
if (unlikely(float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d))) {
/* sNaN subtraction */
-fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
+fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
}
farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
}
@@ -553,12 +560,12 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1,
uint64_t arg2)
if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
(float64_is_zero(farg1.d) && float64_is_infinity(farg2.d {
/* Multiplication of zero by infinity */
-farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
+farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
} else {
if (unlikely(float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d))) {
[Qemu-devel] [PATCH V3 00/19] PowerPC VSX Stage 3
NOTE: this is a resubmission of the previous (V2) patch series. There was corruption in some of the patches. The logical content is identical to V2. This is the third series of patches to add PowerPC VSX emulation support to QEMU. This series adds the floating point arithmetic, compare, conversion and rounding instructions. Instructions are implemented using helpers and wherever practical, existing floating point code such as the softfloat library and the existing PowerPC floating point helper code. As with the previous series, the Power ISA V2.06 instructions are added but the V2.07 instructions are not. The latter will be implemented in a future patch series. V2: Implemented changes based on feedback from Richard Henderson and Peter Maydell: - Included float64_to_uint64() patch in this series rather than just cite it as a pre-requesite. - Isolated float32_to_uint64() in its own patch. - Re-implemented helpers and eliminated the need for some of the proposed softfloat routines (float*_is_denormal, float*_get_unbiased_exp). - Re-implemented severy helpers so that corner cases (e.g. invalid operations) are detected by softfloat. - Re-implemented fused multiply-add to use the softfloat muladd routines. - Re-implemented the min/max instructions to used the softfloat min/max functions. - assorted style fixes V3: re-submitting due to patch corruption. Tom Musta (19): Fix float64_to_uint64 Add float32_to_uint64() Add set_fprf Argument to fload_invalid_op_excp() General Support for VSX Helpers Add VSX ISA2.06 xadd/xsub Instructions Add VSX ISA2.06 xmul Instructions Add VSX ISA2.06 xdiv Instructions Add VSX ISA2.06 xre Instructions Add VSX ISA2.06 xsqrt Instructions Add VSX ISA2.06 xrsqrte Instructions Add VSX ISA2.06 xtdiv Instructions Add VSX ISA2.06 xtsqrt Instructions Add VSX ISA2.06 Multiply Add Instructions Add VSX xscmp*dp Instructions Add VSX xmax/xmin Instructions Add VSX Vector Compare Instructions Add VSX Floating Point to Floating Point Conversion Instructions Add VSX ISA2.06 Integer Conversion Instructions Add VSX Rounding Instructions fpu/softfloat.c | 140 +++- include/fpu/softfloat.h |1 + target-ppc/fpu_helper.c | 1002 --- target-ppc/helper.h | 109 + target-ppc/translate.c | 243 5 files changed, 1439 insertions(+), 56 deletions(-)
[Qemu-devel] [PATCH V3 01/19] Fix float64_to_uint64
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.
This contribution can be licensed under either the softfloat-2a or -2b
license.
V2: Added softfloat license statement.
V3: Modified to meet QEMU coding conventions.
Signed-off-by: Tom Musta
---
fpu/softfloat.c | 95 ++-
1 files changed, 87 insertions(+), 8 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7ba51b6..3070eaa 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -204,6 +204,47 @@ static int64 roundAndPackInt64( flag zSign, uint64_t
absZ0, uint64_t absZ1 STATU
}
/*
+| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and
+| `absZ1', with binary point between bits 63 and 64 (between the input words),
+| and returns the properly rounded 64-bit unsigned integer corresponding to the
+| input. Ordinarily, the fixed-point input is simply rounded to an integer,
+| with the inexact exception raised if the input cannot be represented exactly
+| as an integer. However, if the fixed-point input is too large, the invalid
+| exception is raised and the largest unsigned integer is returned.
+**/
+
+static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
+{
+int8 roundingMode;
+flag roundNearestEven, increment;
+int64_t z;
+
+roundingMode = STATUS(float_rounding_mode);
+roundNearestEven = (roundingMode == float_round_nearest_even);
+increment = ((int64_t) absZ1 < 0);
+if (!roundNearestEven) {
+if (roundingMode == float_round_to_zero) {
+increment = 0;
+} else {
+increment = (roundingMode == float_round_up) && absZ1;
+}
+}
+if (increment) {
+++absZ0;
+if (absZ0 == 0) {
+float_raise(float_flag_invalid STATUS_VAR);
+return LIT64(0x);
+}
+absZ0 &= ~(((uint64_t)(absZ1<<1) == 0) & roundNearestEven);
+}
+z = absZ0;
+if (absZ1) {
+STATUS(float_exception_flags) |= float_flag_inexact;
+}
+return z;
+}
+
+/*
| Returns the fraction bits of the single-precision floating-point value `a'.
**/
@@ -6536,18 +6577,56 @@ uint_fast16_t float64_to_uint16_round_to_zero(float64 a
STATUS_PARAM)
return res;
}
-/* FIXME: This looks broken. */
-uint64_t float64_to_uint64 (float64 a STATUS_PARAM)
-{
-int64_t v;
+/*
+| Returns the result of converting the double-precision floating-point value
+| `a' to the 64-bit unsigned integer format. The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode. If `a' is a NaN, the largest
+| positive integer is returned. If the conversion overflows, the
+| largest unsigned integer is returned. If 'a' is negative, zero is
+| returned.
+**/
-v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
-v += float64_val(a);
-v = float64_to_int64(make_float64(v) STATUS_VAR);
+uint64_t float64_to_uint64(float64 a STATUS_PARAM)
+{
+flag aSign;
+int_fast16_t aExp, shiftCount;
+uint64_t aSig, aSigExtra;
+a = float64_squash_input_denormal(a STATUS_VAR);
-return v - INT64_MIN;
+aSig = extractFloat64Frac(a);
+aExp = extractFloat64Exp(a);
+aSign = extractFloat64Sign(a);
+if (aSign) {
+if (aExp) {
+float_raise(float_flag_invalid STATUS_VAR);
+} else if (aSig) { /* negative denormalized */
+float_raise(float_flag_inexact STATUS_VAR);
+}
+return 0;
+}
+if (aExp) {
+aSig |= LIT64(0x0010);
+}
+shiftCount = 0x433 - aExp;
+if (shiftCount <= 0) {
+if (0x43E < aExp) {
+if ((aSig != LIT64(0x0010)) ||
+ (aExp == 0x7FF)) {
+float_raise(float_flag_invalid STATUS_VAR);
+}
+return LIT64(0x);
+}
+aSigExtra = 0;
+aSig <<= -shiftCount;
+} else {
+shift64ExtraRightJamming(aSig, 0, shiftCount, &aSig, &aSigExtra);
+}
+return roundAndPackUint64(aSig, aSigExtra STATUS_VAR);
}
+
uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM)
{
int64_t v;
--
1.7.1
[Qemu-devel] [PATCH V3 13/13] Add xxsldwi
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 62
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f52ec8b..ce07a56 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -500,6 +500,7 @@ EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
EXTRACT_HELPER(UIM, 16, 2);
+EXTRACT_HELPER(SHW, 8, 2);
/*/
/* PowerPC instructions table*/
@@ -7398,6 +7399,66 @@ static void gen_xxspltw(DisasContext *ctx)
tcg_temp_free(b2);
}
+static void gen_xxsldwi(DisasContext *ctx)
+{
+TCGv_i64 xth, xtl;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+xth = tcg_temp_new();
+xtl = tcg_temp_new();
+
+switch (SHW(ctx->opcode)) {
+case 0: {
+tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+break;
+}
+case 1: {
+TCGv_i64 t0 = tcg_temp_new();
+tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
+tcg_gen_shli_i64(xth, xth, 32);
+tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
+tcg_gen_shri_i64(t0, t0, 32);
+tcg_gen_or_i64(xth, xth, t0);
+tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
+tcg_gen_shli_i64(xtl, xtl, 32);
+tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+tcg_gen_shri_i64(t0, t0, 32);
+tcg_gen_or_i64(xtl, xtl, t0);
+tcg_temp_free(t0);
+break;
+}
+case 2: {
+tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+break;
+}
+case 3: {
+TCGv_i64 t0 = tcg_temp_new();
+tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
+tcg_gen_shli_i64(xth, xth, 32);
+tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
+tcg_gen_shri_i64(t0, t0, 32);
+tcg_gen_or_i64(xth, xth, t0);
+tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
+tcg_gen_shli_i64(xtl, xtl, 32);
+tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
+tcg_gen_shri_i64(t0, t0, 32);
+tcg_gen_or_i64(xtl, xtl, t0);
+tcg_temp_free(t0);
+break;
+}
+}
+
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
+
+tcg_temp_free(xth);
+tcg_temp_free(xtl);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9914,6 +9975,7 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
+GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
1.7.1
[Qemu-devel] [PATCH V3 06/13] Add stxvw4x
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4860e53..047e876 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7107,6 +7107,33 @@ static void gen_stxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_stxvw4x(DisasContext *ctx)
+{
+TCGv EA, tmp;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+tmp = tcg_temp_new();
+
+tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
+gen_qemu_st32(ctx, tmp, EA);
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+
+tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_st32(ctx, tmp, EA);
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+
+tcg_temp_free(EA);
+tcg_temp_free(tmp);
+}
+
static void gen_xxpermdi(DisasContext *ctx)
{
TCGv_i64 xh, xl;
@@ -9593,6 +9620,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE,
PPC2_VSX),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
--
1.7.1
[Qemu-devel] [PATCH V3 10/13] Add xxmrgh/xxmrgl
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 41 +
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ab78bf5..e69cbbf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7297,6 +7297,45 @@ VSX_LOGICAL(xxlor, tcg_gen_or_tl)
VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
+#define VSX_XXMRG(name, high) \
+static void glue(gen_, name)(DisasContext * ctx)\
+{ \
+TCGv_i64 a0, a1, b0, b1;\
+if (unlikely(!ctx->vsx_enabled)) { \
+gen_exception(ctx, POWERPC_EXCP_VSXU); \
+return; \
+} \
+a0 = tcg_temp_new();\
+a1 = tcg_temp_new();\
+b0 = tcg_temp_new();\
+b1 = tcg_temp_new();\
+if (high) { \
+tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
+tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
+tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
+tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
+} else {\
+tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
+tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
+tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
+tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
+} \
+tcg_gen_shri_i64(a0, a0, 32); \
+tcg_gen_shri_i64(b0, b0, 32); \
+tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
+b0, a0, 32, 32);\
+tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
+b1, a1, 32, 32);\
+tcg_temp_free(a0); \
+tcg_temp_free(a1); \
+tcg_temp_free(b0); \
+tcg_temp_free(b1); \
+}
+
+VSX_XXMRG(xxmrghw, 1)
+VSX_XXMRG(xxmrglw, 0)
+
+
/*** SPE extension ***/
/* Register moves */
@@ -9809,6 +9848,8 @@ VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
+GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--
1.7.1
[Qemu-devel] [PATCH V3 12/13] Add xxspltw
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8d32465..f52ec8b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -499,6 +499,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
/*/
/* PowerPC instructions table*/
@@ -7368,6 +7369,35 @@ static void gen_xxsel(DisasContext * ctx)
tcg_temp_free(c);
}
+static void gen_xxspltw(DisasContext *ctx)
+{
+TCGv_i64 b, b2;
+TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
+ cpu_vsrl(xB(ctx->opcode)) :
+ cpu_vsrh(xB(ctx->opcode));
+
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+
+b = tcg_temp_new();
+b2 = tcg_temp_new();
+
+if (UIM(ctx->opcode) & 1) {
+tcg_gen_ext32u_i64(b, vsr);
+} else {
+tcg_gen_shri_i64(b, vsr, 32);
+}
+
+tcg_gen_shli_i64(b2, b, 32);
+tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+
+tcg_temp_free(b);
+tcg_temp_free(b2);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9883,6 +9913,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
1.7.1
[Qemu-devel] [PATCH V3 07/13] Add VSX Scalar Move Instructions
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd (Scalar Negative Absolute Value Double-Precision)
- xsnegdp (Scalar Negate Double-Precision)
- xscpsgndp (Scalar Copy Sign Double-Precision)
A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
V3: Per feedback from Paolo Bonzini, moved the sign mask into a
temporary and used andc.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 69
1 files changed, 69 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 047e876..7409f77 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7163,6 +7163,58 @@ static void gen_xxpermdi(DisasContext *ctx)
tcg_temp_free(xh);
tcg_temp_free(xl);
}
+#define OP_ABS 1
+#define OP_NABS 2
+#define OP_NEG 3
+#define OP_CPSGN 4
+#define SGN_MASK_DP 0x8000ul
+#define SGN_MASK_SP 0x80008000ul
+
+#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+{ \
+TCGv_i64 xb, sgm; \
+if (unlikely(!ctx->vsx_enabled)) {\
+gen_exception(ctx, POWERPC_EXCP_VSXU);\
+return; \
+} \
+xb = tcg_temp_new(); \
+sgm = tcg_temp_new(); \
+tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
+tcg_gen_movi_i64(sgm, sgn_mask); \
+switch (op) { \
+case OP_ABS: {\
+tcg_gen_andc_i64(xb, xb, sgm);\
+break;\
+} \
+case OP_NABS: { \
+tcg_gen_or_i64(xb, xb, sgm); \
+break;\
+} \
+case OP_NEG: {\
+tcg_gen_xor_i64(xb, xb, sgm); \
+break;\
+} \
+case OP_CPSGN: { \
+TCGv_i64 xa = tcg_temp_new(); \
+tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
+tcg_gen_and_i64(xa, xa, sgm); \
+tcg_gen_andc_i64(xb, xb, sgm);\
+tcg_gen_or_i64(xb, xb, xa); \
+tcg_temp_free(xa);\
+break;\
+} \
+} \
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
+tcg_temp_free(xb);\
+tcg_temp_free(sgm); \
+}
+
+VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+
/*** SPE extension ***/
/* Register moves */
@@ -9622,6 +9674,18 @@ GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE,
PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
+#undef GEN_XX2FORM
+#define GEN_XX2FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+
+#undef GEN_XX3FORM
+#define GEN_XX3FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3,
[Qemu-devel] [PATCH V3 11/13] Add xxsel
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.
The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This
overloading is done in matrix fashion with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation
using tcg_gen_andc_i64.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 76
1 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e69cbbf..8d32465 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -497,6 +497,7 @@ EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
+EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
/*/
/* PowerPC instructions table*/
@@ -7335,6 +7336,38 @@ static void glue(gen_, name)(DisasContext * ctx)
\
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
+static void gen_xxsel(DisasContext * ctx)
+{
+TCGv_i64 a, b, c;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+a = tcg_temp_new();
+b = tcg_temp_new();
+c = tcg_temp_new();
+
+tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
+tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
+tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
+
+tcg_gen_and_i64(b, b, c);
+tcg_gen_andc_i64(a, a, c);
+tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
+
+tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
+tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
+tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
+
+tcg_gen_and_i64(b, b, c);
+tcg_gen_andc_i64(a, a, c);
+tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
+
+tcg_temp_free(a);
+tcg_temp_free(b);
+tcg_temp_free(c);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9851,6 +9884,49 @@ VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+#define GEN_XXSEL_ROW(opc3) \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
+GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
+
+GEN_XXSEL_ROW(0x00)
+GEN_XXSEL_ROW(0x01)
+GEN_XXSEL_ROW(0x02)
+GEN_XXSEL_ROW(0x03)
+GEN_XXSEL_ROW(0x04)
+GEN_XXSEL_ROW(0x05)
+GEN_XXSEL_ROW(0x06)
+GEN_XXSEL_ROW(0x07)
+GEN_XXSEL_ROW(0x08)
+GEN_XXSEL_ROW(0x09)
+GEN_XXSEL_ROW(0x0A)
+GEN_XXSEL_ROW(0x0B)
+GEN_XXSEL_ROW(0x0C)
+GEN_XXSEL_ROW(0x0D)
+GEN_XXSEL_ROW(0x0E)
+GEN_XXSEL_ROW(0x0F)
+GEN_XXSEL_ROW(0x10)
+GEN_XXSEL_ROW(0x11)
+GEN_XXSEL_ROW(0x12)
+GEN_XXSEL_ROW(0x13)
+GEN_XXSEL_ROW(0x14)
+GEN_XXSEL_ROW(0x15)
+GEN_XXSEL_ROW(0x16)
+GEN_XXSEL_ROW(0x17)
+GEN_XXSEL_ROW(0x18)
+GEN_XXSEL_ROW(0x19)
+GEN_XXSEL_ROW(0x1A)
+GEN_XXSEL_ROW(0x1B)
+GEN_XXSEL_ROW(0x1C)
+GEN_XXSEL_ROW(0x1D)
+GEN_XXSEL_ROW(0x1E)
+GEN_XXSEL_ROW(0x1F)
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
[Qemu-devel] [PATCH V3 08/13] Add VSX Vector Move Instructions
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Absolute Value Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 71
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7409f77..e7d40a4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7215,6 +7215,69 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext * ctx) \
+{\
+TCGv_i64 xbh, xbl, sgm; \
+if (unlikely(!ctx->vsx_enabled)) { \
+gen_exception(ctx, POWERPC_EXCP_VSXU); \
+return; \
+}\
+xbh = tcg_temp_new();\
+xbl = tcg_temp_new();\
+sgm = tcg_temp_new();\
+tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
+tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
+tcg_gen_movi_i64(sgm, sgn_mask); \
+switch (op) {\
+case OP_ABS: { \
+tcg_gen_andc_i64(xbh, xbh, sgm); \
+tcg_gen_andc_i64(xbl, xbl, sgm); \
+break; \
+}\
+case OP_NABS: { \
+tcg_gen_or_i64(xbh, xbh, sgm); \
+tcg_gen_or_i64(xbl, xbl, sgm); \
+break; \
+}\
+case OP_NEG: { \
+tcg_gen_xor_i64(xbh, xbh, sgm); \
+tcg_gen_xor_i64(xbl, xbl, sgm); \
+break; \
+}\
+case OP_CPSGN: { \
+TCGv_i64 xah = tcg_temp_new(); \
+TCGv_i64 xal = tcg_temp_new(); \
+tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
+tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
+tcg_gen_and_i64(xah, xah, sgm); \
+tcg_gen_and_i64(xal, xal, sgm); \
+tcg_gen_andc_i64(xbh, xbh, sgm); \
+tcg_gen_andc_i64(xbl, xbl, sgm); \
+tcg_gen_or_i64(xbh, xbh, xah); \
+tcg_gen_or_i64(xbl, xbl, xal); \
+tcg_temp_free(xah); \
+tcg_temp_free(xal); \
+break; \
+}\
+}\
+tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
+tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
+tcg_temp_free(xbh); \
+tcg_temp_free(xbl); \
+tcg_temp_free(sgm); \
+}
+
+VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
+VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
+VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+
+
/*** SPE extension ***/
/* Register
[Qemu-devel] [PATCH V3 09/13] Add Power7 VSX Logical Instructions
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e7d40a4..ab78bf5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7278,6 +7278,24 @@ VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
+#define VSX_LOGICAL(name, tcg_op)\
+static void glue(gen_, name)(DisasContext * ctx) \
+{\
+if (unlikely(!ctx->vsx_enabled)) { \
+gen_exception(ctx, POWERPC_EXCP_VSXU); \
+return; \
+}\
+tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
+cpu_vsrh(xB(ctx->opcode))); \
+tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
+cpu_vsrl(xB(ctx->opcode))); \
+}
+
+VSX_LOGICAL(xxland, tcg_gen_and_tl)
+VSX_LOGICAL(xxlandc, tcg_gen_andc_tl)
+VSX_LOGICAL(xxlor, tcg_gen_or_tl)
+VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
+VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
/*** SPE extension ***/
/* Register moves */
@@ -9781,6 +9799,17 @@ GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
+
+#undef VSX_LOGICAL
+#define VSX_LOGICAL(name, opc2, opc3, fl2) \
+GEN_XX3FORM(name, opc2, opc3, fl2)
+
+VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
+VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
+VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
+VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
+VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
+
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
#undef GEN_SPE
--
1.7.1
[Qemu-devel] [PATCH V3 03/13] Add lxvdsx
This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1e2cce1..6a359a2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7034,6 +7034,21 @@ static void gen_lxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_lxvdsx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+tcg_temp_free(EA);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9531,6 +9546,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
[Qemu-devel] [PATCH V3 05/13] Add stxsdx
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7e5b363..4860e53 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7077,6 +7077,20 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free(tmp);
}
+static void gen_stxsdx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+tcg_temp_free(EA);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9577,6 +9591,7 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE,
PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
#undef GEN_XX3FORM_DM
--
1.7.1
[Qemu-devel] [PATCH V3 02/13] Add lxsdx
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9d315f4..1e2cce1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7003,6 +7003,21 @@ static inline TCGv_i64 cpu_vsrl(int n)
}
}
+static void gen_lxsdx(DisasContext *ctx)
+{
+TCGv EA;
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+/* NOTE: cpu_vsrl is undefined */
+tcg_temp_free(EA);
+}
+
static void gen_lxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9514,6 +9529,7 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
[Qemu-devel] [PATCH V3 04/13] Add lxvw4x
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta
---
target-ppc/translate.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6a359a2..7e5b363 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7049,6 +7049,34 @@ static void gen_lxvdsx(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_lxvw4x(DisasContext *ctx)
+{
+TCGv EA, tmp;
+TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+if (unlikely(!ctx->vsx_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_VSXU);
+return;
+}
+gen_set_access_type(ctx, ACCESS_INT);
+EA = tcg_temp_new();
+tmp = tcg_temp_new();
+gen_addr_reg_index(ctx, EA);
+gen_qemu_ld32u(ctx, tmp, EA);
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_ld32u(ctx, xth, EA);
+tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
+
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_ld32u(ctx, tmp, EA);
+tcg_gen_addi_tl(EA, EA, 4);
+gen_qemu_ld32u(ctx, xtl, EA);
+tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
+
+tcg_temp_free(EA);
+tcg_temp_free(tmp);
+}
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
@@ -9547,6 +9575,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
[Qemu-devel] [PATCH V3 01/13] Abandon GEN_VSX_* macros
This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which did not provide significant value above the general GEN_HANDLER_E macro. Signed-off-by: Tom Musta --- target-ppc/translate.c | 12 ++-- 1 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2f337f1..9d315f4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9514,17 +9514,9 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), -#undef GEN_VSX_LXVNX -#define GEN_VSX_LXVNX(name, opc2, opc3) \ - GEN_HANDLER_E(lxv##name, 0x1F, opc2, opc3, 0x, PPC_NONE, PPC2_VSX) +GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), -GEN_VSX_LXVNX(d2x, 0x0C, 0x1A), - -#undef GEN_VSX_STXVNX -#define GEN_VSX_STXVNX(name, opc2, opc3) \ - GEN_HANDLER_E(stxv##name, 0x1F, opc2, opc3, 0x, PPC_NONE, PPC2_VSX) - -GEN_VSX_STXVNX(d2x, 0x0C, 0x1E), +GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), #undef GEN_XX3FORM_DM #define GEN_XX3FORM_DM(name, opc2, opc3) \ -- 1.7.1
[Qemu-devel] [PATCH V3 00/13] Stage 2 VSX Support
NOTE: this is a resubmission of this patch series. Alex discovered some corruption in the patches from my previous submission. This patch series continues adding support for the PowerPC Vector Scalar Extension (VSX). Patches are relative to the Stage 1 delivery (see http://lists.nongnu.org/archive/html/qemu-ppc/2013-09/msg00231.html). This series adds the following: a) all remaining load and store instructions defined by the V2.06 Power ISA (aka Power7). b) The vector and scalar move instructions. c) The logical instructions defined by V2.06. d) Assorted permute and select instructions. V2: reworked patches 4, 10, 11 and 12 per comments from Richard Henderson (thanks, Richard!) V3: reworked patches 7 & 8 per comments from Paolo Bonzini (thanks, Paulo) Tom Musta (13): Abandon GEN_VSX_* macros Add lxsdx Add lxvdsx Add lxvw4x Add stxsdx Add stxvw4x Add VSX Scalar Move Instructions Add VSX Vector Move Instructions Add Power7 VSX Logical Instructions Add xxmrgh/xxmrgl Add xxsel Add xxspltw Add xxsldwi target-ppc/translate.c | 491 +++- 1 files changed, 483 insertions(+), 8 deletions(-)
Re: [Qemu-devel] [RFC PATCH] spapr: add ibmveth to the supported network adapters list
Am 01.11.2013 um 03:52 schrieb Alexey Kardashevskiy :
> On 10/28/2013 05:03 AM, Alexander Graf wrote:
>>
>> On 10.10.2013, at 20:09, Alexey Kardashevskiy wrote:
>>
>>> The problem is that "-net nic,model=?" does not print "ibmveth" in
>>> the list while it is actually supported.
>>>
>>> Most of the QEMU emulated network devices are PCI but "ibmveth"
>>> (a.k.a. spapr-vlan) is not. However with "-net nic,model=?", QEMU prints
>>> only PCI devices in the list, even if it does not say that the list is
>>> all about PCI devices.
>>>
>>> This adds "?"/"help" handling in spapr.c and adds "ibmveth" in the beginning
>>> of the list.
>>>
>>> Signed-off-by: Alexey Kardashevskiy
>>> ---
>>>
>>> This is an RFC patch.
>>>
>>> The other solutions could be:
>>> 1. add "ibmveth" into pci_nic_models[] in hw/pci/pci.c but this would not
>>> be correct as "ibmveth" is not PCI and it must appear only on pseries
>>> machine.
>>>
>>> 2. implemement short version of qdev_print_category_devices() and call it
>>> with DEVICE_CATEGORY_NETWORK but that would print more devices than
>>> pci_nic_init_nofail() can handle (vmxnet3, usb-bt-dongle).
>>>
>>> 3. fix qemu_check_nic_model() to specifically say that this is a list of
>>> PCI devices and there might be some other devices which "-net nic,model+"
>>> supports but there are not PCI but that could break compatibility (some
>>> management software may rely on this exact string).
>>>
>>> 4. Reject the patch and just say that people must stop using "-net". Ok for
>>> me :)
>>>
>>> Since "-net" is kind of obsolete interface and does not seem to be extended
>>> ever,
>>> the proposed patch does not look too ugly, does not it?
>>> ---
>>> hw/ppc/spapr.c | 15 +++
>>> 1 file changed, 15 insertions(+)
>>>
>>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>>> index c0613e4..45ed3da 100644
>>> --- a/hw/ppc/spapr.c
>>> +++ b/hw/ppc/spapr.c
>>> @@ -1276,6 +1276,21 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
>>>
>>>if (strcmp(nd->model, "ibmveth") == 0) {
>>>spapr_vlan_create(spapr->vio_bus, nd);
>>> +} else if (is_help_option(nd->model)) {
>>> +static const char * const nic_models[] = {
>>> +"ibmveth",
>>> +"ne2k_pci",
>>> +"i82551",
>>> +"i82557b",
>>> +"i82559er",
>>> +"rtl8139",
>>> +"e1000",
>>> +"pcnet",
>>> +"virtio",
>>> +NULL
>>> +};
>>
>> I don't like the idea of duplicating that list.
>
> Neither do I :) But the list itself already looks quite ugly.
>
>> Basically the list of supported -net models is incorrect today even on
>> x86 where you can say -net nic,model=ne2k_isa. It really is only a list
>> of PCI devices.
>
>
>> I can think of a number of convoluted ways to fix this up, but I think
>> that ignoring fully accuracy of the output of -net model=? is the most
>> straight forward thing to do.
>
> Does any of your "convoluted" ways include adding a new category
> (DEVICE_CATEGORY_NETWORK_LEGACY?) into enum DeviceCategory, adding devices
> from the list above and fixing qemu_show_nic_models() to show what is in
> the category?
Most of them consist of a full redesign of the way -net works :).
>
> Or "-net" interface is "deprecated" and we do not want even touch it?
I don't think we should deprecate it. It's easier to use than anything else.
Ahci adoption heavily suffered from not being enabled in -drive - I don't want
that again here.
Alex
>
>
>
> --
> Alexey
Re: [Qemu-devel] [Qemu-trivial] [PATCH] vl: fix build when configured with no graphic support
On Fri, 01 Nov 2013 15:18:28 +0400 Michael Tokarev wrote: > 01.11.2013 15:14, Antony Pavlov wrote: > > On Fri, 01 Nov 2013 14:29:24 +0400 > > Michael Tokarev wrote: > > > >> 29.10.2013 08:36, Antony Pavlov wrote > >>> The following error occurs when building no graphic output support: > > ^ > > Can you plese fix misprint in my git commit message too. > > Fixed. Thank you for pointing this out. > > >> +(void)ds; /* avoid warning if no display is configured */ > > Are you okay with me adding the comment? :) IMHO your comment is useful, thanks! -- Best regards, Antony Pavlov
Re: [Qemu-devel] [Qemu-ppc] [v2 02/13] Add lxsdx
On 10/31/2013 5:58 PM, Alexander Graf wrote: > > On 11.10.2013, at 05:57, Tom Musta wrote: > >> This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) >> instruction. >> >> The lower 8 bytes of the target register are undefined; this >> implementation leaves those bytes unaltered. >> >> Signed-off-by: Tom Musta > > The diff seems to be broken. Patchworks and my mail client show 2 spaces in > "already existing code" parts of the patch. > > > Alex Arrgh. Sorry about that. I am still fighting with my email client. But I have also now installed and configured git send-email. So I will resubmit the entire patch series.
Re: [Qemu-devel] [PATCH] qapi: Fix comment for create-type to match code.
On 11/01/2013 03:35 AM, Fam Zheng wrote: > Signed-off-by: Fam Zheng > --- > qapi-schema.json | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/qapi-schema.json b/qapi-schema.json > index 81a375b..76c98a7 100644 > --- a/qapi-schema.json > +++ b/qapi-schema.json > @@ -227,7 +227,7 @@ > ## > # @ImageInfoSpecificVmdk: > # > -# @create_type: The create type of VMDK image > +# @create-type: The create type of VMDK image > # > # @cid: Content id of image > # Reviewed-by: Eric Blake and adding qemu-trivial in case it's faster to pull in via that channel. -- Eric Blake eblake redhat com+1-919-301-3266 Libvirt virtualization library http://libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] VHD suport in QEMU?
On Fri, Nov 01, 2013 at 06:04:19AM +0100, Philipp Hahn wrote: > Hello, > > sorry for high-jacking this thread, but I have a questing regarding VHD > (without the X): Xen-4.3 switched to upstream QEMUs support for VHD. The > dropped their own VHD implementation in blktap2, which supported backing > chains, which QEMU currently doesn't. The Xen implementation > (xen/tools/blktap2/vhd/lib/ is BSD 3 clause) also supports some kind of > journal. > 1. Does someone know if the journal support for VHD is somehow related to > VHDX? I don't believe it is. Despite the similarity in names, VHD and VHDX are completely different formats. I just went and looked at Xen's libvhd-journal, and per my understanding it is a journal written into a separate file, not related to the actual VHD spec itself. It appears to be used by the VHD utility tools, when updating a VHD image file with operations such as resize, etc.., so they can write a finalized bitmap of all header/metadata changes at once to minimize any potential corruption. Jeff
[Qemu-devel] [Bug 1246012] Re: QEMU removes postgresql
Furthermore, I completely fail to see how this is relevant to the qemu project. This bug should be filed against the distribution supplied the binary packages, whose metadata is (apparently) wrong. Upstream qemu does not provide .deb packages and repositories. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1246012 Title: QEMU removes postgresql Status in QEMU: Incomplete Bug description: >sudo apt-get install kvm virt-manager removed postgresql-9.2 from my system. Furthermore, it seem impossible for me to run postgresql and qemu at the same time. Starting one, kills the other. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1246012/+subscriptions
[Qemu-devel] [Bug 1246012] Re: QEMU removes postgresql
(Having said that, I'd say this bugreport should be closed as invalid instead of being investigated further) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1246012 Title: QEMU removes postgresql Status in QEMU: Incomplete Bug description: >sudo apt-get install kvm virt-manager removed postgresql-9.2 from my system. Furthermore, it seem impossible for me to run postgresql and qemu at the same time. Starting one, kills the other. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1246012/+subscriptions
Re: [Qemu-devel] [v2, 3/4] qemu-char: add support for U-prefixed symbols
01.11.2013 13:59, Michael Tokarev пишет:
16.10.2013 16:40, Jan Krupa wrote:
This patch adds support for Unicode symbols in keymap files. This
feature was already used in some keyboard layouts in QEMU generated
from XKB (e.g. Arabic) but it wasn't implemented in QEMU source code.
There is no need for check of validity of the hex string after U character
because strtol returns 0 in case the conversion was unsuccessful.
Signed-off-by: Jan Krupa
---
ui/keymaps.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/ui/keymaps.c b/ui/keymaps.c
index f373cc5..426a893 100644
--- a/ui/keymaps.c
+++ b/ui/keymaps.c
@@ -33,6 +33,9 @@ static int get_keysym(const name2keysym_t *table,
if (!strcmp(p->name, name))
return p->keysym;
}
+if (strlen(name) == 5 && name[0] == 'U') {
+return (int)strtol(name + 1, NULL, 16);
+}
return 0;
}
I still dislike this. People already complained that the keysyms
should be case-insensitive. And there might be many words starting
with "u" and of 5 chars long.
How about this:
Author: Jan Krupa
Date: Wed Oct 16 14:40:05 2013 +0200
qemu-char: add support for U-prefixed symbols
This patch adds support for Unicode symbols in keymap files. This
feature was already used in some keyboard layouts in QEMU generated
from XKB (e.g. Arabic) but it wasn't implemented in QEMU source code.
There is no need for check of validity of the hex string after U character
because strtol returns 0 in case the conversion was unsuccessful.
Signed-off-by: Jan Krupa
Signed-off-by: Michael Tokarev
diff --git a/ui/keymaps.c b/ui/keymaps.c
index f373cc5..80d658d 100644
--- a/ui/keymaps.c
+++ b/ui/keymaps.c
@@ -33,6 +33,12 @@ static int get_keysym(const name2keysym_t *table,
if (!strcmp(p->name, name))
return p->keysym;
}
+if (name[0] == 'U' && strlen(name) == 5) { /* try unicode U */
+char *end;
+int ret = (int)strtoul(name + 1, &end, 16);
Maybe strtol() here as in original.. On my system, both work
the same anyway :)
/mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] vl: fix build when configured with no graphic support
01.11.2013 15:14, Antony Pavlov wrote: On Fri, 01 Nov 2013 14:29:24 +0400 Michael Tokarev wrote: 29.10.2013 08:36, Antony Pavlov wrote The following error occurs when building no graphic output support: ^ Can you plese fix misprint in my git commit message too. Fixed. Thank you for pointing this out. +(void)ds; /* avoid warning if no display is configured */ Are you okay with me adding the comment? :) /mjt
Re: [Qemu-devel] [RFC PATCH] spapr: add ibmveth to the supported network adapters list
On 10/28/2013 05:03 AM, Alexander Graf wrote:
>
> On 10.10.2013, at 20:09, Alexey Kardashevskiy wrote:
>
>> The problem is that "-net nic,model=?" does not print "ibmveth" in
>> the list while it is actually supported.
>>
>> Most of the QEMU emulated network devices are PCI but "ibmveth"
>> (a.k.a. spapr-vlan) is not. However with "-net nic,model=?", QEMU prints
>> only PCI devices in the list, even if it does not say that the list is
>> all about PCI devices.
>>
>> This adds "?"/"help" handling in spapr.c and adds "ibmveth" in the beginning
>> of the list.
>>
>> Signed-off-by: Alexey Kardashevskiy
>> ---
>>
>> This is an RFC patch.
>>
>> The other solutions could be:
>> 1. add "ibmveth" into pci_nic_models[] in hw/pci/pci.c but this would not
>> be correct as "ibmveth" is not PCI and it must appear only on pseries
>> machine.
>>
>> 2. implemement short version of qdev_print_category_devices() and call it
>> with DEVICE_CATEGORY_NETWORK but that would print more devices than
>> pci_nic_init_nofail() can handle (vmxnet3, usb-bt-dongle).
>>
>> 3. fix qemu_check_nic_model() to specifically say that this is a list of
>> PCI devices and there might be some other devices which "-net nic,model+"
>> supports but there are not PCI but that could break compatibility (some
>> management software may rely on this exact string).
>>
>> 4. Reject the patch and just say that people must stop using "-net". Ok for
>> me :)
>>
>> Since "-net" is kind of obsolete interface and does not seem to be extended
>> ever,
>> the proposed patch does not look too ugly, does not it?
>> ---
>> hw/ppc/spapr.c | 15 +++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>> index c0613e4..45ed3da 100644
>> --- a/hw/ppc/spapr.c
>> +++ b/hw/ppc/spapr.c
>> @@ -1276,6 +1276,21 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
>>
>> if (strcmp(nd->model, "ibmveth") == 0) {
>> spapr_vlan_create(spapr->vio_bus, nd);
>> +} else if (is_help_option(nd->model)) {
>> +static const char * const nic_models[] = {
>> +"ibmveth",
>> +"ne2k_pci",
>> +"i82551",
>> +"i82557b",
>> +"i82559er",
>> +"rtl8139",
>> +"e1000",
>> +"pcnet",
>> +"virtio",
>> +NULL
>> +};
>
> I don't like the idea of duplicating that list.
Neither do I :) But the list itself already looks quite ugly.
> Basically the list of supported -net models is incorrect today even on
> x86 where you can say -net nic,model=ne2k_isa. It really is only a list
> of PCI devices.
> I can think of a number of convoluted ways to fix this up, but I think
> that ignoring fully accuracy of the output of -net model=? is the most
> straight forward thing to do.
Does any of your "convoluted" ways include adding a new category
(DEVICE_CATEGORY_NETWORK_LEGACY?) into enum DeviceCategory, adding devices
from the list above and fixing qemu_show_nic_models() to show what is in
the category?
Or "-net" interface is "deprecated" and we do not want even touch it?
--
Alexey
Re: [Qemu-devel] [Bug 1246890] [NEW] AC97 sound card crashes QEMU
On 2013-10-31 21:48, John Arbuckle wrote: > Public bug reported: > > The AC97 sound card does not work. It stops QEMU on startup. The cause > appears to be some kind of deadlock. > > Steps to reproduce: > Just add -soundhw ac97 to QEMU's arguments. Example: qemu-system-ppc -soundhw > ac97 > > The example above is all it takes to reproduce the problem. > > This problem has been observed on Mac OS X and Debian Linux. > > I question whether the ac97 support ever worked. It is a file that was > taken from VirtualBox and added to QEMU. I do know that VirtualBox's > support for the ac97 sound card works perfectly. > > The exact line of code that stops QEMU in its tracks is located in the > file main-loop.c, in the function os_host_main_loop_wait(), the call > made to qemu_mutex_lock_iothread(). The is where QEMU stops under Mac OS > X. > > ** Affects: qemu > Importance: Undecided > Status: New > Maybe this is just a regression: I'm using ac97 for a win7 guest for a while, and since recently (don't recall when precisely, some weeks maybe) I'm getting "main-loop: WARNING: I/O thread spun for 1000 iterations", a temporarily stuck guest and broken sound output. This used to work fine. Someone has to bisect, I didn't find the time yet. Jan signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PATCH] spapr: make sure RMA is in first mode of first memory node
SLOF gets really confused if RTAS/device-tree and everything else what SLOF can use is not in the very first block of the very first memory node. This makes sure that the RMA area is where SLOF expects it to be. Cc: Benjamin Herrenschmidt Cc: Nikunj A Dadhania Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 09dc635..09a5d94 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1113,7 +1113,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) int i; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); -hwaddr rma_alloc_size; +hwaddr rma_alloc_size, node0_size; uint32_t initrd_base = 0; long kernel_size = 0, initrd_size = 0; long load_limit, rtas_limit, fw_size; @@ -1154,6 +1154,12 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) spapr->rma_size = MIN(spapr->rma_size, 0x1000); } } +/* + * SLOF gets confused if RMA resides not in the first block + * of the first memory node so let's fix it. + */ +node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size; +spapr->rma_size = MIN(spapr->rma_size, node0_size); /* We place the device tree and RTAS just below either the top of the RMA, * or just below 2GB, whichever is lowere, so that it can be -- 1.8.4.rc4
Re: [Qemu-devel] [Qemu-trivial] [PATCH] vl: fix build when configured with no graphic support
29.10.2013 08:36, Antony Pavlov wrote
The following error occurs when building no graphic output support:
vl.c: In function ‘main’:
vl.c:2829:19: error: variable ‘ds’ set but not used
[-Werror=unused-but-set-variable]
DisplayState *ds;
^
cc1: all warnings being treated as errors
Thanks, applied to the trivial-patches queue.
While at it, I also added a comment to the line being added,
telling what this is all about:
--- a/vl.c
+++ b/vl.c
@@ -4269,6 +4269,7 @@ int main(int argc, char **argv, char **envp)
/* init local displays */
switch (display_type) {
case DT_NOGRAPHIC:
+(void)ds; /* avoid warning if no display is configured */
break;
#if defined(CONFIG_CURSES)
case DT_CURSES:
Hopefully it is okay... ;)
/mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] usb: drop unused USBNetState.inpkt field
29.10.2013 18:44, Stefan Hajnoczi wrote: [] Thanks, applied to the trivial-patches queue. /mjt
[Qemu-devel] [PATCH] qemu: Broken -smb with latest SAMBA package. (Unsupported security=share option)
01.11.2013 13:54, Michael Büsch wrote: On Fri, 01 Nov 2013 13:32:49 +0400 Michael Tokarev wrote: That looks right. Are you okay adding your Signed-off-by to the patch you initially submitted? If yes, I'll make a formal patch submission upstream. Here you go. Thank you! Adding Jan as slirp maintainer, and my Reviewed-by: Michael Tokarev If Jan picks it up, that's fine. If not, I think it can go to the trivial patches queue. Jan, if you missed context, it is in http://bugs.debian.org/727756 It is not the first time this issue pops up on qemu-devel@ /mjt From: Michael Buesch Subject: [PATCH] qemu/slirp: Fix SMB security configuration on newer samba versions The smb.conf automatically generated by qemu's -smb option fails on current samba, because smbd rejects the security=share option with the following warning: > WARNING: Ignoring invalid value 'share' for parameter 'security' Which makes it fall back to security=user without guest login. This results in being unable to login to the samba server from the guest OS. This fixes it by selecting 'user' explicitly and mapping unknown users to guest logins. Signed-off-by: Michael Buesch --- Index: qemu-1.6.0+dfsg/net/slirp.c === --- qemu-1.6.0+dfsg.orig/net/slirp.c +++ qemu-1.6.0+dfsg/net/slirp.c @@ -529,7 +529,8 @@ static int slirp_smb(SlirpState* s, cons "state directory=%s\n" "log file=%s/log.smbd\n" "smb passwd file=%s/smbpasswd\n" -"security = share\n" +"security = user\n" +"map to guest = Bad User\n" "[qemu]\n" "path=%s\n" "read only=no\n"
Re: [Qemu-devel] [v2,2/4] qemu-char: add Czech keymap file
16.10.2013 16:40, Jan Krupa wrote: This patch adds Czech keyboard layout to available keymap files and Makefile. Thanks, applied to the trivial-patches queue. Again, I rely solely on you for the correctness of the keymap itself. I'm sorry this took so long. /mjt
Re: [Qemu-devel] [v2, 1/4] qemu-char: add Czech characters to VNC keysyms
16.10.2013 16:40, Jan Krupa wrote: This patch adds missing Czech characters to the VNC keysym table. Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [v2, 4/4] qemu-char: add missing characters used in keymaps
16.10.2013 16:40, Jan Krupa wrote: This patch adds all missing characters used in regional keymap files which already exist in QEMU. I checked for the missing characters by going through all of the keymaps and matching that with records in vnc_keysym.h. If the key wasn't found I looked it up in libxkbcommon library [1]. If I understood it correctly this is also the same place where most of the keymaps were exported from according to the comment on the first line in those files. I was able to find all symbols except "quotebl" used in Netherland keymap. I tested this update with Czech keyboard by myself. I also asked Matej Serc to test Slovenian keyboard layout - he reported problems with it few days ago on this mailing list. Both layouts seems to work fine. I wasn't able to test the remaining layouts but since this change doesn't modify any existing symbols, just adds new ones, I don't expect any sideeffects. Yes, this patch, while large, is trivial and without any side effects. Except of one question. Where we add these entries? Should we maybe sort the table somehow, or introduce some more groups of chars? (I'm fine with applying this to qemu-trivial as-is). Thanks, /mjt
Re: [Qemu-devel] [v2, 3/4] qemu-char: add support for U-prefixed symbols
16.10.2013 16:40, Jan Krupa wrote:
This patch adds support for Unicode symbols in keymap files. This
feature was already used in some keyboard layouts in QEMU generated
from XKB (e.g. Arabic) but it wasn't implemented in QEMU source code.
There is no need for check of validity of the hex string after U character
because strtol returns 0 in case the conversion was unsuccessful.
Signed-off-by: Jan Krupa
---
ui/keymaps.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/ui/keymaps.c b/ui/keymaps.c
index f373cc5..426a893 100644
--- a/ui/keymaps.c
+++ b/ui/keymaps.c
@@ -33,6 +33,9 @@ static int get_keysym(const name2keysym_t *table,
if (!strcmp(p->name, name))
return p->keysym;
}
+if (strlen(name) == 5 && name[0] == 'U') {
+return (int)strtol(name + 1, NULL, 16);
+}
return 0;
}
I still dislike this. People already complained that the keysyms
should be case-insensitive. And there might be many words starting
with "u" and of 5 chars long.
How about this:
Author: Jan Krupa
Date: Wed Oct 16 14:40:05 2013 +0200
qemu-char: add support for U-prefixed symbols
This patch adds support for Unicode symbols in keymap files. This
feature was already used in some keyboard layouts in QEMU generated
from XKB (e.g. Arabic) but it wasn't implemented in QEMU source code.
There is no need for check of validity of the hex string after U character
because strtol returns 0 in case the conversion was unsuccessful.
Signed-off-by: Jan Krupa
Signed-off-by: Michael Tokarev
diff --git a/ui/keymaps.c b/ui/keymaps.c
index f373cc5..80d658d 100644
--- a/ui/keymaps.c
+++ b/ui/keymaps.c
@@ -33,6 +33,12 @@ static int get_keysym(const name2keysym_t *table,
if (!strcmp(p->name, name))
return p->keysym;
}
+if (name[0] == 'U' && strlen(name) == 5) { /* try unicode U */
+char *end;
+int ret = (int)strtoul(name + 1, &end, 16);
+if (*end == '\0' && ret > 0)
+ return ret;
+}
return 0;
}
?
(I'm not sure about the author here, I just commit --amend'ed your change)
Thanks,
/mjt
Re: [Qemu-devel] Bug#727756: qemu: Broken -smb with latest SAMBA package. (Unsupported security=share option)
On Fri, 01 Nov 2013 13:32:49 +0400 Michael Tokarev wrote: > That looks right. Are you okay adding your Signed-off-by to the patch > you initially submitted? If yes, I'll make a formal patch submission > upstream. Here you go. From: Michael Buesch Subject: [PATCH] qemu/slirp: Fix SMB security configuration on newer samba versions The smb.conf automatically generated by qemu's -smb option fails on current samba, because smbd rejects the security=share option with the following warning: > WARNING: Ignoring invalid value 'share' for parameter 'security' Which makes it fall back to security=user without guest login. This results in being unable to login to the samba server from the guest OS. This fixes it by selecting 'user' explicitly and mapping unknown users to guest logins. Signed-off-by: Michael Buesch --- Index: qemu-1.6.0+dfsg/net/slirp.c === --- qemu-1.6.0+dfsg.orig/net/slirp.c +++ qemu-1.6.0+dfsg/net/slirp.c @@ -529,7 +529,8 @@ static int slirp_smb(SlirpState* s, cons "state directory=%s\n" "log file=%s/log.smbd\n" "smb passwd file=%s/smbpasswd\n" -"security = share\n" +"security = user\n" +"map to guest = Bad User\n" "[qemu]\n" "path=%s\n" "read only=no\n" signature.asc Description: PGP signature
[Qemu-devel] [PATCH] qapi: Fix comment for create-type to match code.
Signed-off-by: Fam Zheng --- qapi-schema.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qapi-schema.json b/qapi-schema.json index 81a375b..76c98a7 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -227,7 +227,7 @@ ## # @ImageInfoSpecificVmdk: # -# @create_type: The create type of VMDK image +# @create-type: The create type of VMDK image # # @cid: Content id of image # -- 1.8.3.1
Re: [Qemu-devel] [PULL 30/30] vmdk: Implment bdrv_get_specific_info
On Thu, 10/31 17:20, Kevin Wolf wrote: > Am 31.10.2013 um 17:13 hat Eric Blake geschrieben: > > On 10/31/2013 09:48 AM, Kevin Wolf wrote: > > > From: Fam Zheng > > > > > > Implement .bdrv_get_specific_info to return the extent information. > > > > > > Signed-off-by: Fam Zheng > > > Signed-off-by: Kevin Wolf > > > --- > > > > > +++ b/qapi-schema.json > > > @@ -225,6 +225,27 @@ > > >} } > > > > > > ## > > > +# @ImageInfoSpecificVmdk: > > > +# > > > +# @create_type: The create type of VMDK image > > > > If it's not too late, can we fix this typo without having to do it in a > > followup patch? s/_/-/ > > Okay, I'll fix that quickly, but I'm not going send a v3 on the list. > Let's just hope that nobody's looking. :-) Thanks, but looks like Anthony already merged it. I'll send a follow up patch to fix it. Fam
Re: [Qemu-devel] Bug#727756: qemu: Broken -smb with latest SAMBA package. (Unsupported security=share option)
26.10.2013 20:44, Michael Büsch wrote: [] Also, which users are "bad" -- will it be possible for our user to "clash" with some built-in/known user? 'bad" users seem to be users that are not in the smbpasswd file. As qemu creates an empty smbpasswd file, all users probably are "bad". That looks right. Are you okay adding your Signed-off-by to the patch you initially submitted? If yes, I'll make a formal patch submission upstream. Because, well, this bothers several people already. Thank you! /mjt
Re: [Qemu-devel] VHD suport in QEMU?
On Fri, Nov 01, 2013 at 06:04:19AM +0100, Philipp Hahn wrote: > sorry for high-jacking this thread, but I have a questing regarding VHD > (without the X): Xen-4.3 switched to upstream QEMUs support for VHD. The > dropped their own VHD implementation in blktap2, which supported backing > chains, which QEMU currently doesn't. The Xen implementation > (xen/tools/blktap2/vhd/lib/ is BSD 3 clause) also supports some kind of > journal. > 1. Does someone know if the journal support for VHD is somehow related to > VHDX? > 2. Has somewone put some work into supporting backing chains? I started to > have a look myself some time ago, but had to do other work since then. Hi Philipp, I'm not aware of block/vpc.c (classic VHD) improvements at this time. Out of interest, are the VHD Differencing images you'd like to use come from Xen, VirtualPC, or something else? Stefan
Re: [Qemu-devel] [PATCH v4 0/2] sheepdog: add user-defined redundancy option
On Thu, Oct 31, 2013 at 01:49:26PM +0800, Liu Yuan wrote: > v4: > - fix do_sd_create that forgot to pass nr_copies > - fix parse_redundancy dealing with replicated vdi Hello Kevin, Could you pick these two patches to your block tree (so QEMU next release can enjoy the full erasure coding feature from Sheepdog) ? Thanks Yuan
Re: [Qemu-devel] [PULL v2 00/30] Block patches
On Thu, Oct 31, 2013 at 10:52 PM, Paolo Bonzini wrote: > Il 31/10/2013 21:50, Anthony Liguori ha scritto: >> /x86_64/ide/bmdma/setup: OK >> /x86_64/ide/bmdma/simple_rw: OK >> /x86_64/ide/bmdma/short_prdt:OK >> /x86_64/ide/bmdma/long_prdt: OK >> /x86_64/ide/bmdma/no_busmaster: >> Broken pipe >> FAIL >> GTester: last random seed: R02Sc1c266d6688697d47a58af063ff343c5 >> (pid=720) >> /x86_64/ide/bmdma/teardown: FAIL >> GTester: last random seed: R02S2c481529260b1d513b7a498b45a5b420 >> (pid=736) >> FAIL: tests/ide-test > > It might not help, but I suggest that you merge "[PATCH 1.7] timers: fix > stop/cont with -icount" before anything else. It appears to help actually. I'll do some more testing and push if I don't find anything else. Thanks Paolo! Regards, Anthony Liguori > Paolo
