Re: [Qemu-devel] [PATCH 1/2 v2] pci: change default value of rom_bar to 2
On Wed, Feb 19, 2014 at 03:20:54PM -0500, Bandan Das wrote:
The following patch depends on the value of rom_bar to
determine rom blacklist behavior. Existing code shouldn't
be affected by changing the default value of rom_bar since
all relevant decisions only rely on whether rom_bar is zero
or non-zero.
Signed-off-by: Bandan Das b...@redhat.com
---
hw/pci/pci.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 4e0701d..12c3e27 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -53,7 +53,12 @@ static void pci_bus_finalize(Object *obj);
static Property pci_props[] = {
DEFINE_PROP_PCI_DEVFN(addr, PCIDevice, devfn, -1),
DEFINE_PROP_STRING(romfile, PCIDevice, romfile),
-DEFINE_PROP_UINT32(rombar, PCIDevice, rom_bar, 1),
+/*
+ * 0 = disable
+ * 1 = user requested on, force loading even if rom blacklisted
+ * 2 = enabled but disables loading of blacklisted roms (default)
+ */
+DEFINE_PROP_UINT32(rombar, PCIDevice, rom_bar, 2),
How do users figure out this interface?
Read code?
Could we add a bit property rombarforce=on/off instead?
Seems better.
Maybe we should teach bool type visitors
about 0 and 1 being legal values
(call out to int visitor, then check value 0 or 1),
then rombar can be changed to bit property too.
Also, this will need QMP support right?
IIUC rombar is not exposed in QMP ATM.
DEFINE_PROP_BIT(multifunction, PCIDevice, cap_present,
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
DEFINE_PROP_BIT(command_serr_enable, PCIDevice, cap_present,
--
1.8.3.1
Re: [Qemu-devel] [PATCH 1/2 v2] pci: change default value of rom_bar to 2
On Wed, Feb 19, 2014 at 01:36:45PM -0700, Alex Williamson wrote:
On Wed, 2014-02-19 at 15:20 -0500, Bandan Das wrote:
The following patch depends on the value of rom_bar to
determine rom blacklist behavior. Existing code shouldn't
be affected by changing the default value of rom_bar since
all relevant decisions only rely on whether rom_bar is zero
or non-zero.
Signed-off-by: Bandan Das b...@redhat.com
---
hw/pci/pci.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 4e0701d..12c3e27 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -53,7 +53,12 @@ static void pci_bus_finalize(Object *obj);
static Property pci_props[] = {
DEFINE_PROP_PCI_DEVFN(addr, PCIDevice, devfn, -1),
DEFINE_PROP_STRING(romfile, PCIDevice, romfile),
-DEFINE_PROP_UINT32(rombar, PCIDevice, rom_bar, 1),
+/*
+ * 0 = disable
+ * 1 = user requested on, force loading even if rom blacklisted
+ * 2 = enabled but disables loading of blacklisted roms (default)
+ */
+DEFINE_PROP_UINT32(rombar, PCIDevice, rom_bar, 2),
DEFINE_PROP_BIT(multifunction, PCIDevice, cap_present,
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
DEFINE_PROP_BIT(command_serr_enable, PCIDevice, cap_present,
A slightly more satisfying option might be to define rom_bar as int32_t
with default of -1. I don't know if that would break libvirt though.
I'll let MST weigh in. Thanks,
Alex
I don't see rombar in json schema at all.
I think it was designed as an internal flag
for compatibility with legacy machine types.
As such it's likely not a good interface
for users.
--
MST
Re: [Qemu-devel] [PATCH v14 06/14] block: Add backing_blocker in BlockDriverState
On Thu, 02/20 00:08, Jeff Cody wrote:
On Thu, Feb 20, 2014 at 01:01:38PM +0800, Fam Zheng wrote:
On Wed, 02/19 16:17, Jeff Cody wrote:
On Wed, Feb 19, 2014 at 09:42:23PM +0800, Fam Zheng wrote:
This makes use of op_blocker and blocks all the operations except for
commit target, on each BlockDriverState-backing_hd.
The asserts for op_blocker in bdrv_swap are removed because with this
change, the target of block commit has at least the backing blocker of
its child, so the assertion is not true. Callers should do their check.
Signed-off-by: Fam Zheng f...@redhat.com
---
block.c | 19 +++
include/block/block_int.h | 3 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/block.c b/block.c
index dec44d4..95d8c1f 100644
--- a/block.c
+++ b/block.c
@@ -1044,19 +1044,33 @@ fail:
void bdrv_set_backing_hd(BlockDriverState *bs, BlockDriverState
*backing_hd)
{
if (bs-backing_hd) {
+assert(error_is_set(bs-backing_blocker));
When I run block-commit, on either the active or non-active layer, I
get an assertion here. The qemu-iotests do not catch it, and I
presume it is because happens a couple of seconds or so after the
success message is returned over QMP.
I can't reproduce this, could you give some specific steps? Thanks.
Sure - I am guessing the key is performing some live block snapshots
first. Here is what I did (this is from memory, but I think the steps
are right):
Nothing special really about the cmdline:
qemu-system-x86_64 -drive file=/home/jtc/test.qcow2,if=virtio -qmp stdio ...
The QMP commands:
For the non-active layer case:
{ execute: qmp_capabilities }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap1.qcow2,format: qcow2 } }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap2.qcow2,format: qcow2 } }
{ execute: block-commit, arguments: { device: virtio0, top:
/tmp/snap1.qcow2 } }
For the active layer case (I think I still had 2 snapshots here, not
entirely positive):
{ execute: qmp_capabilities }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap1.qcow2,format: qcow2 } }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap2.qcow2,format: qcow2 } }
{ execute: block-commit, arguments: { device: virtio0, top:
/tmp/snap2.qcow2 } }
{ execute: block-job-complete, arguments: { device: virtio0 }}
Yes. I forgot to use bdrv_set_backing_hd in bdrv_append.
Could you try if the below patch fixes it? Thanks.
Fam
---
diff --git a/block.c b/block.c
index 1af43b9..66a8e35 100644
--- a/block.c
+++ b/block.c
@@ -1978,7 +1978,7 @@ void bdrv_append(BlockDriverState *bs_new,
BlockDriverState *bs_top)
/* The contents of 'tmp' will become bs_top, as we are
* swapping bs_new and bs_top contents. */
-bs_top-backing_hd = bs_new;
+bdrv_set_backing_hd(bs_top, bs_new);
bs_top-open_flags = ~BDRV_O_NO_BACKING;
pstrcpy(bs_top-backing_file, sizeof(bs_top-backing_file),
bs_new-filename);
Re: [Qemu-devel] [PATCH v14 08/14] block: Support dropping active in bdrv_drop_intermediate
On Thu, 02/20 00:57, Jeff Cody wrote:
On Thu, Feb 20, 2014 at 12:37:17PM +0800, Fam Zheng wrote:
On Wed, 02/19 18:24, Jeff Cody wrote:
On Wed, Feb 19, 2014 at 04:22:30PM -0500, Jeff Cody wrote:
On Wed, Feb 19, 2014 at 09:42:25PM +0800, Fam Zheng wrote:
/*
- * Drops images above 'base' up to and including 'top', and sets the
image
- * above 'top' to have base as its backing file.
+ * Drops images above 'base' up to and including 'top', and sets new
'base'
+ * as backing_hd of top_overlay (the image orignally has 'top' as
backing
What is 'top_overlay'? Do you mean top's overlay by this?
Yes, as noted in the parenthesis.
I would just say top's overlay. What I found confusing by that, is
when you reference something like 'top_overlay', it looks like an
actual variable name. So I was searching for that variable name, and
wondered if it was just vestigial from an earlier revision. Maybe
that is just me, though :)
I will update the wording for less confusion. Sorry about that.
And in the non-active case here, everything between top-backing_hd
and the original base is orphaned as well. These should all be
explicitly unreferenced.
Same here, bdrv_unref() will eventually go through the chain, starting
from top-backing_hd. But this is a problem; won't we end up in a
loop then?
Although the content is swapped, the pointer is not:
(I presume your [base] and [top] are denoting content, not pointer)
Correct. But part of the content that is swapped, are the backing_hd
pointers.
Take this chain:
drop_start = [A]
|||-- ([base]) -- [B] --- [A] --- ([top]) --- [active]
^ ^
| |
base top
bdrv_swap(top, base):
-- [B] -- [A] -- ([top])|||--- ([base]) -- [active]
^ ^
| |
base top
|^
||
-
Correct, those are the pointers.
Then we call bdrv_unref(drop_start (or bdrv_set_backing_hd() does),
and we end up with:
dropping an anchor here: [1]
bdrv_unref(A)
bdrv_unref(B)
bdrv_unref(top)
bdrv_unref(A) --- assert
.
So I think we want this line:
+bdrv_set_backing_hd(base, NULL);
so, this breaks the chain,
Yes, you are right, we want base-backing_hd to be NULL. But the
chain has not been broken yet.
The loop [1] still exists, because once we enter bdrv_set_backing_hd()
we begin to call bdrv_unref(A). And base_ptr-backing_hd still points
to A, and B will point to base_ptr.
Yes, that need to be fixed.
Here is the first part of bdrv_set_backing_hd():
if (bs-backing_hd) {
bdrv_op_unblock_all(bs-backing_hd, bs-backing_blocker);
bdrv_unref(bs-backing_hd);
To be:
+bdrv_set_backing_hd(top, NULL);
This will lose track of original base's backing_hd.
Right, we don't want that, sorry... I shouldn't have written that, my
brain failed me. I mentally conflated top and [top].
So I think we are OK here.
I don't think we are, we still need to address the backing_hd loop,
and I think it needs to be done here, where we have the information.
Again, you are right :)
Thanks,
Fam
Re: [Qemu-devel] [PATCH v4 0/8] spapr: bootindex support
On 02/14/2014 07:26 PM, Alexey Kardashevskiy wrote: On 02/14/2014 06:29 PM, Paolo Bonzini wrote: Il 14/02/2014 04:25, Alexey Kardashevskiy ha scritto: Nobody seems picking up the bits I am interested in from this :-/ What can I possibly do to get this in upstream?... I feel I am doing something systematically wrong but nobody is telling me what exactly. Thanks. No, you're not. Ping agraf on IRC if he doesn't answer. This almost never helps... Tried. Did not help. Oh. I also would like to post a patchset adding NMI for ppc64 and since I am not allowed to post yet another #ifdef PPC64 thing, I tried making it an NMI interface for a machine (same as FWPathProvider) but found out that even qdev: introduce FWPathProvider interface it is not upstream yet - where is it now and what are the plans about it? -- Alexey
Re: [Qemu-devel] [PATCH] sparc: Set HostID in NVRAM
On 29/12/13 23:51, Olivier Danet wrote: On SparcStations, the HostID field in the NVRAM is equal to the last three bytes of the MAC address (which is also stored in the NVRAM). This constant is used as an identification/serial number on Solaris. signed-off-by : Olivier Danet oda...@caramail.com --- include/hw/nvram/openbios_firmware_abi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/nvram/openbios_firmware_abi.h b/include/hw/nvram/openbios_firmware_abi.h index 5e6e5d4..492c8d5 100644 --- a/include/hw/nvram/openbios_firmware_abi.h +++ b/include/hw/nvram/openbios_firmware_abi.h @@ -62,6 +62,8 @@ Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id header-type = 1; header-machine_id = machine_id 0xff; memcpy(header-macaddr, macaddr, 6); + memcpy(header-hostid , macaddr[3],3); I think there is some whitespace damage on this patch? At least I couldn't apply it as is :/ Also the lack of a space after the final comma on the line above looks suspicious too... have you tried running scripts/checkpatch.pl on the resulting diffs? + /* Calculate checksum */ tmp = 0; tmpptr = (uint8_t *)header; Apart from the whitespace issues, the basic patch looks fine though. ATB, Mark.
Re: [Qemu-devel] [PATCH] Sun4m : SCSI ESP controller
On 16/02/14 23:13, Olivier Danet wrote:
Two small fixes for the ESP (AM53C94) SCSI controller
* Signal the end of the DMA transfer after a SCSI command.
* The status register (RSTAT) is cleared after reading the interrupt
status register (RINTR), except for the TC bit (=Count To Zero) and the
scsi phase bits, which mirror SCSI signals levels.
Fixes the bug esp0: !TC on DATA XFER with NetBSD
https://bugs.launchpad.net/qemu/+bug/1055090
Signed-off-by: Olivier Danet oda...@caramail.com
---
hw/scsi/esp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 2d150bf..5e91077 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -246,6 +246,7 @@ static void esp_do_dma(ESPState *s)
s-cmdlen = 0;
s-do_cmd = 0;
do_cmd(s, s-cmdbuf);
+ esp_dma_done(s);
return;
}
if (s-async_len == 0) {
@@ -417,10 +418,9 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
except TC */
old_val = s-rregs[ESP_RINTR];
s-rregs[ESP_RINTR] = 0;
- s-rregs[ESP_RSTAT] = ~STAT_TC;
s-rregs[ESP_RSEQ] = SEQ_CD;
esp_lower_irq(s);
-
+ s-rregs[ESP_RSTAT] = STAT_TC | STAT_MI;
return old_val;
default:
break;
Hi Olivier,
I've applied the non-whitespace damaged patch (attached) but
unfortunately I still see the !TC on DATA XFER bug with my NetBSD 5
ISO under qemu-system-sparc :/ Note that the second part of the patch
showed some fuzz so I'm wondering if this patch is complete or whether
part of it is still missing?
Also ESP patches should have an esp or scsi/esp prefix in the subject
line and should CC the current SCSI maintainer (see MAINTAINERS file)
which is currently Paolo.
HTH,
Mark.
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Re: [Qemu-devel] [PATCH 0/7] qemu-img: Fix handling of multiply specified options
Am 20.02.2014 um 08:18 hat Markus Armbruster geschrieben: Kevin Wolf kw...@redhat.com writes: If you specify the same option more than once (e.g. -o cluster_size=4k -o lazy_refcounts=on), qemu-img silently ignores all but the last one. This Sounds like perfectly common behavior to me. I guess it depends on the kind of option. For -o it's no less surprising than 'gcc -Wall -Werror' giving you only -Werror without -Wall. series fixes it to either consider all options or to give an error message. Doesn't this break usage like Compiled-in default is no good for me, create wrapper script setting my defaults followed by $@, then override them on command line? It does. Would you be happy with a series that accumulates -o options (like this one does) and leaves the other options alone? Kevin
Re: [Qemu-devel] [PATCH] net: Disable netmap backend when not supported
On Wed, Feb 19, 2014 at 10:30:03AM -0800, Luigi Rizzo wrote: On Wed, Feb 19, 2014 at 7:30 AM, Stefan Hajnoczi stefa...@gmail.com wrote: On Fri, Feb 14, 2014 at 05:40:24PM +0100, Vincenzo Maffione wrote: diff --git a/configure b/configure index 88133a1..61eb932 100755 --- a/configure +++ b/configure @@ -2118,6 +2118,9 @@ if test $netmap != no ; then #include net/if.h #include net/netmap.h #include net/netmap_user.h +#if (NETMAP_API 11) || (NETMAP_API 15) +#error +#endif Why error when NETMAP_API 15? this is meant to simulate a minor/major version number. We will mark minor new features with values up to 15, and if something happens that requires a change in the backend we will move above 15, at which point we will submit backend fixes and also the necessary update to ./configure I see. A comment in the code would be nice to explain that. -ring-cur = NETMAP_RING_NEXT(ring, i); -ring-avail--; +ring-cur = ring-head = nm_ring_next(ring, i); ioctl(s-me.fd, NIOCTXSYNC, NULL); return size; Are these changes related to the NETMAP_WITH_LIBS macro? Please do that in a separate patch so we keep the version checking change separate from the NETMAP_WITH_LIBS change. netmap version 11 and above has NETMAP_WITH_LIBS, while previous versions do not, so this ./configure change has to go together with the change in the backend. The netmap 11 code has already been committed to the FreeBSD source repositories (for HEAD, 10 and 9) and to code.google.com/p/netmap/ (for those who want it on linux). So there is really no point, in my opinion, to make one intermediate commit just to ./configure to disable netmap detection on FreeBSD (it is already off on linux), immediately followed by this one that uses the new feature. Just to clarify: with one exception (fields in struct netmap_ring) the netmap changes that we have are not at the kernel/user boundary but in a library which avoids replicating long and boring code (interface name parsing, parameter setting) in applications. Avoiding the single incompatible struct change would have been of course possible, but at the cost extra complexity in the kernel and in userspace (to support two slightly different interfaces). Since netmap is (so far) relatively little used I thought it was more important to fix the API and keep it simple. Thanks for explaining. Please put justification for the NETMAP_WITH_LIBS changes in the commit description. Stefan
Re: [Qemu-devel] [PATCH 0/7] qemu-img: Fix handling of multiply specified options
Kevin Wolf kw...@redhat.com writes: Am 20.02.2014 um 08:18 hat Markus Armbruster geschrieben: Kevin Wolf kw...@redhat.com writes: If you specify the same option more than once (e.g. -o cluster_size=4k -o lazy_refcounts=on), qemu-img silently ignores all but the last one. This Sounds like perfectly common behavior to me. I guess it depends on the kind of option. For -o it's no less surprising than 'gcc -Wall -Werror' giving you only -Werror without -Wall. I agree that multiple -OPT KEY=VALUE,... accumulating is nicer than the last one wiping out its predecessors. series fixes it to either consider all options or to give an error message. Doesn't this break usage like Compiled-in default is no good for me, create wrapper script setting my defaults followed by $@, then override them on command line? It does. Would you be happy with a series that accumulates -o options (like this one does) and leaves the other options alone? No objections.
Re: [Qemu-devel] [PATCH] net: Disable netmap backend when not supported
On Wed, Feb 19, 2014 at 04:57:28PM +0100, Vincenzo Maffione wrote:
2014-02-19 16:30 GMT+01:00 Stefan Hajnoczi stefa...@gmail.com:
On Fri, Feb 14, 2014 at 05:40:24PM +0100, Vincenzo Maffione wrote:
@@ -56,31 +58,6 @@ typedef struct NetmapState {
struct ioveciov[IOV_MAX];
} NetmapState;
-#define D(format, ...) \
-do {\
-struct timeval __xxts; \
-gettimeofday(__xxts, NULL);\
-printf(%03d.%06d %s [%d] format \n,\
-(int)__xxts.tv_sec % 1000, (int)__xxts.tv_usec, \
-__func__, __LINE__, ##__VA_ARGS__); \
-} while (0)
-
-/* Rate limited version of D, lps indicates how many per second */
-#define RD(lps, format, ...)\
-do {\
-static int t0, __cnt; \
-struct timeval __xxts; \
-gettimeofday(__xxts, NULL);\
-if (t0 != __xxts.tv_sec) { \
-t0 = __xxts.tv_sec; \
-__cnt = 0; \
-} \
-if (__cnt++ lps) {\
-D(format, ##__VA_ARGS__); \
-} \
-} while (0)
-
-
#ifndef __FreeBSD__
#define pkt_copy bcopy
#else
Why are you deleting this?
Because now equivalent code is contained by netmap_user.h
Please mention that in the commit description.
(I guess it's too late to give them a NETMAP_* prefix since defining D()
and RD() in a system header has a fair chance of causing namespace
conflicts.)
Stefan
[Qemu-devel] [PULL] Chardev fix
Hi, This fix by Gal Hammer has been on list for quite a while, please pull. The following changes since commit 46eef33b89e936ca793e13c4aeea1414e97e8dbb: Fix QEMU build on OpenBSD on x86 archs (2014-02-17 11:44:00 +) are available in the git repository at: git://git.kernel.org/pub/scm/virt/qemu/amit/virtio-serial.git char-fixes for you to fetch changes up to 5f9b4bcaefa6ed4c7ce7181bd041d2a5b774bd5e: char: restore read callback on a reattached (hotplug) chardev (2014-02-20 15:17:32 +0530) Gal Hammer (1): char: restore read callback on a reattached (hotplug) chardev qemu-char.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) Amit
Re: [Qemu-devel] who do a send a link request to
On Sun, Feb 16, 2014 at 09:14:37PM -0500, Aryeh Friedman wrote: PetiteCloud is a layer 0 cloud platform (see site for details of what that means and how it fits into the virtualization/cloud computing land scape) http://petitecloud.org/info.jsp doesn't do it for me. I see a lot of buzzwords (some of the new to me, did you invent vertical industry level clustering and horizontal sector level clustering?) and spelling mistakes but no summary of what this thing does. My guess: PetiteCloud is a web-based management interface that runs on baremetal or on a cloud, it lets you control your own sub-cloud. Like, proxmox or kimchi for the cloud? That's what the screenshots tell me but maybe I didn't understand the point. that supports among other hypervisors (I know qemu hates the term but that's what everyone else calls) QEMU. How do I go about getting a link on qemu.org for it (we already have several to qemu for example in our hypervisor support matrix) Where would you add PetiteCloud on http://qemu-project.org/Links? I guess Other management tools/systems. Please post the actual snippet that you want on the wiki. qemu-project.org is a wiki, you can request an account but for this small edit I'm happy to do it. Note that the links are rel=nofollow so they won't count towards Search Engine Optimization but they may steer human visitors to your site. Stefan
Re: [Qemu-devel] [RFC PATCH v2 01/12] mc: add documentation for micro-checkpointing
* Michael R. Hines (mrhi...@linux.vnet.ibm.com) wrote: On 02/19/2014 07:27 PM, Dr. David Alan Gilbert wrote: I was just wondering if a separate 'max buffer size' knob would allow you to more reasonably bound memory without setting policy; I don't think people like having potentially x2 memory. Note: Checkpoint memory is not monotonic in this patchset (which is unique to this implementation). Only if the guest actually dirties 100% of it's memory between one checkpoint to the next will the host experience 2x memory usage for a short period of time. Right, but that doesn't really help - if someone comes along and says 'How much memory do I need to be able to run an mc system?' the only safe answer is 2x, otherwise we're adding a reason why the previously stable guest might OOM. The patch has a 'slab' mechanism built in to it which implements a water-mark style policy that throws away unused portions of the 2x checkpoint memory if later checkpoints are much smaller (which is likely to be the case if the writable working set size changes). However, to answer your question: Such a knob could be achieved, but the same could be achieved simply by tuning the checkpoint frequency itself. Memory usage would thus be a function of the checkpoint frequency. If the guest application was maniacal, banging away at all the memory, there's very little that can be done in the first place, but if the guest application was mildly busy, you don't want to throw away your ability to be fault tolerant - you would just need more frequent checkpoints to keep up with the dirty rate. I'm not convinced; I can tune my checkpoint frequency until normal operation makes a reasonable trade off between mc frequency and RAM usage, but that doesn't prevent it running away when a garbage collect or some other thing suddenly dirties a load of ram in one particular checkpoint. Some management tool that watches ram usage etc can also help tune it, but in the end it can't stop it taking loads of RAM. Once the application died down - the water-mark policy would kick in and start freeing checkpoint memory. (Note: this policy happens on both sides in the patchset because the patch has to be fully compatible with RDMA memory pinning). What is *not* exposed, however, is the watermark knobs themselves, I definitely think that needs to be exposed - that would also get you a similar control to 'max buffer size' - you could place a time limit on the slab list in the patch or something like that... Good question in general - I'll add it to the FAQ. The patch implements a basic 'transaction' mechanism in coordination with an outbound I/O buffer (documented further down). With these two things in places, split-brain is not possible because the destination is not running. We don't allow the destination to resume execution until a committed transaction has been acknowledged by the destination and only until then do we allow any outbound network traffic to be release to the outside world. Yeh I see the IO buffer, what I've not figured out is how: 1) MC over TCP/IP gets an acknowledge on the source to know when it can unplug it's buffer. Only partially correct (See the steps on the wiki). There are two I/O buffers at any given time which protect against a split-brain scenario: One buffer for the current checkpoint that is being generated (running VM) and one buffer for the checkpoint that is being committed in a transaction. 2) Lets say the MC connection fails, so that ack never arrives, the source must assume the destination has failed and release it's packets and carry on. Only the packets for Buffer A are released for the current committed checkpoint after a completed transaction. The packets for Buffer B (the current running VM) are still being held up until the next transaction starts. Later once the transaction completes and A is released, B becomes the new A and a new buffer is installed to become the new Buffer B for the current running VM. The destination must assume the source has failed and take over. The destination must also receive an ACK. The ack goes both ways. Once the source and destination both acknowledge a completed transation does the source VM resume execution - and even then it's packets are still being buffered until the next transaction starts. (That's why it's important to checkpoint as frequently as possible). I think I understand normal operation - my question here is about failure; what happens when neither side gets any ACKs. 3) If we're relying on TCP/IP timeout that's quite long. Actually, my experience is been that TCP seems to have more than one kind of timeout - if receiver is not responding *at all* - it seems that TCP has a dedicated timer for that. The socket API immediately sends back an error code and the patchset closes the conneciton on the destination and recovers. How did you
Re: [Qemu-devel] [PATCH 0/4] Tracetool cleanup
On Wed, Feb 19, 2014 at 04:19:10PM +0100, Lluís Vilanova wrote: Stefan Hajnoczi writes: On Mon, Feb 17, 2014 at 08:36:19PM +0100, Lluís Vilanova wrote: Minimizes the amount of backend code, making it simpler to add new/different backends. Also performs other cleanups all around. Signed-off-by: Lluís Vilanova vilan...@ac.upc.edu --- Lluís Vilanova (4): trace: [tracetool] Add method 'Event.api' to build event names trace: [tracetool,trivial] Style changes trace: [tracetool] Identify formats directly used by QEMU trace: [tracetool] Minimize the amount of per-backend code I think we stretched the concepts of backends and formats too far. There are formats that only work with one backend (like 'stap'). And there are backends that behave differently from all other backends. As a result we're trying to abstract and make common a bunch of stuff that isn't really common. This problem existed before this patch series, but I feel we're going further down a direction that increasingly seems to be wrong. It's simpler if we turn the design inside-out. Instead of making backends export all sorts of interfaces and flags, tracetool should just parse trace-events and hand the list over to the backend. Let the backend do whatever it wants. The format option simply becomes an option telling the backend which type of output to generate (events.h, events.c, .stp, etc). Common behavior should live in plain old Python modules/functions. TL;DR moving to a library design would simplify and clean up more than trying to improve the current framework design What do you think? This series moves into that direction; some of the formats are simply not handled by backends. For example, the stap, events_c and events_h formats have no backend-specific contents. Also, having common code for the format, and then relying on backends for a small piece of the contents simplifies later patches like the multi-backend tracing. The thing here is that maybe we should change format to file, since it actually refers to a specific output file. You have a point. tracetool needs to output a particular file (e.g. generated-events.c, generated-tracers.h), which is kind of what a format has become. So the format is the primary piece of code that emits output. But if it needs to do something backend-specific (like generated-tracers.h) then it should call into backend modules. I am still concerned about the weird and wonderful interfaces that we're creating (like the API field in this patch series). They make it harder to understand the code and add new backends. Will think about this more when reviewing the next revision of this series. Stefan
Re: [Qemu-devel] [PULL 0/3] qtest: avoid pidfile and QEMU process leaks
On Wed, Feb 19, 2014 at 07:23:24PM +0100, Andreas Färber wrote: Am 19.02.2014 15:50, schrieb Stefan Hajnoczi: Reviewed by Paolo and Markus. Here is the pull request. v2: * Don't call qtest_end() from SIGABRT handler to avoid reentrancy [Paolo] * Use sigemptyset() to avoid assumption about signal mask [Markus] * if (fd != -1) close(fd) is no longer necessary [Markus] This series prevents the following qtest issues: 1. Leaking the pidfile if QEMU startup fails, as discovered by Andreas Färber. 2. Leaking the QEMU process when a test case aborts. Applying this series should make buildbots and manual make check users have a more pleasant and less leaky experience :). The following changes since commit 46eef33b89e936ca793e13c4aeea1414e97e8dbb: Fix QEMU build on OpenBSD on x86 archs (2014-02-17 11:44:00 +) are available in the git repository at: git://github.com/stefanha/qemu.git tags/qtest-monitor-process-pull-request for you to fetch changes up to b15d422a23a3e4cf1b4195af209211eccdb88d51: qtest: kill QEMU process on g_assert() failure (2014-02-19 15:45:51 +0100) qtest resource cleanup pull request Stefan Hajnoczi (3): qtest: drop unused child_pid field qtest: make QEMU our direct child process qtest: kill QEMU process on g_assert() failure tests/libqtest.c | 59 +--- 1 file changed, 26 insertions(+), 33 deletions(-) Ack, my pending pull touches qtest.c rather than libqtest.c (hope you remembered to check!) and changes look OK, didn't test yet though. I took a quick look and don't see any conflicts/issues.
Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07
Tom, I tested your patches [see below] and I found they work very well. They solve all the immediate problems that libguestfs was hitting with qemu not emulating certain POWER7 instructions. I am now running a full libguestfs test which will take several hours, but it looks as if -- even if this test fails -- it won't be because of lack of emulation / missing instructions in qemu. Thanks, Rich. 1258017 (HEAD, master) target-ppc: Fix xxpermdi When T==A or T==B a5a770e target-ppc: Altivec 2.07: Vector Permute and Exclusive OR d2235b6 target-ppc: Altivec 2.07: Vector SHA Sigma Instructions 823d8bc target-ppc: Altivec 2.07: AES Instructions de692f8 target-ppc: Altivec 2.07: Binary Coded Decimal Instructions e57670e target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum 7aa4e18 target-ppc: Altivec 2.07: Vector Gather Bits by Bytes 0407211 target-ppc: Altivec 2.07: Doubleword Compares fa643cd target-ppc: Altivec 2.07: vbpermq Instruction 3eefbc5 target-ppc: Altivec 2.07: Quadword Addition and Subtracation 679b19f target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions c33fb5a target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts 0d0e6fc target-ppc: Altivec 2.07: Vector Merge Instructions 535ddb7 target-ppc: Altivec 2.07: Unpack Signed Word Instructions 7c25020 target-ppc: Altivec 2.07: Pack Doubleword Instructions 1bfa3da target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions 46b62bf target-ppc: Altivec 2.07: Vector Population Count Instructions 1208e47 target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes 7560038 target-ppc: Altivec 2.07: vmuluw Instruction 5219437 target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions e6d9b50 target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers b00c954 target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo 59bae01 target-ppc: Altivec 2.07: Vector Logical Instructions 652fb6b target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions 1278f7d target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions 96645c6 target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions c7dc903 target-ppc: Altivec 2.07: Add GEN_VXFORM3 cc356ef target-ppc: Altivec 2.07: Update AVR Structure 236fce3 target-ppc: Altivec 2.07: Add Instruction Flag 1963af7 target-ppc: Add Store Quadword Conditional f74301d target-ppc: Add Load Quadword and Reserve 755065e target-ppc: Store Quadword b278fa5 target-ppc: Load Quadword aae0775 target-ppc: Add is_user_mode Utility Routine 702c075 target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions c103fc8 target-ppc: Add bctar Instruction cab1f12 target-ppc: Add Target Address SPR (TAR) to Power8 b904000 target-ppc: Add Flag for bctar e1adfb7 target-ppc: Add ISA2.06 lfiwzx Instruction ef84f63 target-ppc: Enable frsqrtes on Power7 and Power8 cfc3d6c target-ppc: Add ISA 2.06 ftsqrt 003634e target-ppc: Add ISA 2.06 ftdiv Instruction 8e28300 target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions 795d567 target-ppc: Fix and enable fri[mnpz] 7d69a6f target-ppc: Add ISA 2.06 fcfid[u][s] Instructions 18f088a target-ppc: Add ISA2.06 Float to Integer Instructions 6211a33 target-ppc: Add Flag for ISA V2.06 Floating Point Conversion bb961d5 target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions 42cb1ee target-ppc: Add ISA2.06 lbarx, lharx Instructions 3ee50eb target-ppc: Add Flag for ISA2.06 Atomic Instructions a38a0de target-ppc: Add ISA 2.06 divwe[o] Instructions 0964b12 target-ppc: Add ISA 2.06 divweu[o] Instructions 57c8cb1 target-ppc: Add ISA2.06 divde[o] Instructions e711f0f target-ppc: Add ISA2.06 divdeu[o] Instructions 4360fcf target-ppc: Add Flag for ISA2.06 Divide Extended Instructions 3813bf9 target-ppc: Add ISA2.06 bpermd Instruction 07cafd8 target-ppc: Scalar Non-Signalling Conversions e3b40b5 target-ppc: Scalar Round to Single Precision 622d9fc target-ppc: Floating Merge Word Instructions aab0146 target-ppc: Move To/From VSR Instructions f716b79 target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc 613656c target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp a80fde4 target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds 0ce9239 target-ppc: VSX Stage 4: add xsrsqrtesp 32dc58c target-ppc: VSX Stage 4: Add xssqrtsp 71b162a target-ppc: VSX Stage 4: Add xsresp 78a46d8 target-ppc: VSX Stage 4: Add xsdivsp 1c71eda target-ppc: VSX Stage 4: Add xsmulsp c4ddfce target-ppc: VSX Stage 4: Add xsaddsp and xssubsp 76bec27 target-ppc: VSX Stage 4: Add stxsiwx and stxsspx 68de7cb target-ppc: VSX Stage 4: Refactor stxsdx 151f526 target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx bdfbd58 target-ppc: VSX Stage 4: Refactor lxsdx a918cda target-ppc: VSX Stage 4: Add VSX 2.07 Flag 18bf3f4 target-ppc: Add VSX Rounding Instructions 586ceee target-ppc: Add VSX ISA2.06 Integer Conversion Instructions 88d8f61 target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions 3cd430d target-ppc: Add VSX Vector Compare
Re: [Qemu-devel] [PULL 0/6] Tracing patches
On Wed, Feb 19, 2014 at 05:01:47PM +0100, Lluís Vilanova wrote: Stefan Hajnoczi writes: Lluis: CCed you since Mohamad's LTTng 2.x patches conflict with your cleanup series. Will rebase and adjust. Sorry about that. I had most of these patches merged for a while and forgot about them :(.
Re: [Qemu-devel] [Spice-devel] [PATCH] qxl: add sanity check
Looks good, ACK.
Christophe
On Wed, Feb 19, 2014 at 11:40:50AM +0100, Gerd Hoffmann wrote:
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/display/qxl.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index 1471cc0..2a559eb 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -1429,7 +1429,7 @@ static int qxl_destroy_primary(PCIQXLDevice *d,
qxl_async_io async)
return 1;
}
-static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
+static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
{
pcibus_t start = d-pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
pcibus_t end = d-pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
@@ -1439,6 +1439,12 @@ static void qxl_set_mode(PCIQXLDevice *d, int modenr,
int loadvm)
.mem_start = start,
.mem_end = end
};
+
+if (modenr = d-modes-n_modes) {
+qxl_set_guest_bug(d, mode number out of range);
+return;
+}
+
QXLSurfaceCreate surface = {
.width = mode-x_res,
.height = mode-y_res,
--
1.8.3.1
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Re: [Qemu-devel] [PATCH v4 0/8] spapr: bootindex support
Il 20/02/2014 09:37, Alexey Kardashevskiy ha scritto: On 02/14/2014 07:26 PM, Alexey Kardashevskiy wrote: On 02/14/2014 06:29 PM, Paolo Bonzini wrote: Il 14/02/2014 04:25, Alexey Kardashevskiy ha scritto: Nobody seems picking up the bits I am interested in from this :-/ What can I possibly do to get this in upstream?... I feel I am doing something systematically wrong but nobody is telling me what exactly. Thanks. No, you're not. Ping agraf on IRC if he doesn't answer. This almost never helps... Tried. Did not help. Oh. I also would like to post a patchset adding NMI for ppc64 and since I am not allowed to post yet another #ifdef PPC64 thing, I tried making it an NMI interface for a machine (same as FWPathProvider) but found out that even qdev: introduce FWPathProvider interface it is not upstream yet - where is it now and what are the plans about it? Well, that would also be for Alex since the sole user is pseries. I suggest you just repost the whole series, either Alex or Andreas can pick it up. Paolo
Re: [Qemu-devel] [PATCH] Sun4m : SCSI ESP controller
Il 20/02/2014 09:58, Mark Cave-Ayland ha scritto: Hi Olivier, I've applied the non-whitespace damaged patch (attached) but unfortunately I still see the !TC on DATA XFER bug with my NetBSD 5 ISO under qemu-system-sparc :/ Note that the second part of the patch showed some fuzz so I'm wondering if this patch is complete or whether part of it is still missing? Also ESP patches should have an esp or scsi/esp prefix in the subject line and should CC the current SCSI maintainer (see MAINTAINERS file) which is currently Paolo. BTW, Mark, should you add yourself to MAINTAINERS for sparc? Paolo
[Qemu-devel] [PATCH 2/3] vhost_net: use offload API instead of bypassing it
There is no need to access backend-info-has_vnet_hdr() and friends
anymore. Use the qemu_has_vnet_hdr() API instead.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/net/vhost_net.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index c90b9ec..a1de2f4 100644
--- a/hw/net/vhost_net.c
+++ b/hw/net/vhost_net.c
@@ -106,7 +106,7 @@ struct vhost_net *vhost_net_init(NetClientState *backend,
int devfd,
goto fail;
}
net-nc = backend;
-net-dev.backend_features = backend-info-has_vnet_hdr(backend) ? 0 :
+net-dev.backend_features = qemu_has_vnet_hdr(backend) ? 0 :
(1 VHOST_NET_F_VIRTIO_NET_HDR);
net-backend = r;
@@ -117,8 +117,8 @@ struct vhost_net *vhost_net_init(NetClientState *backend,
int devfd,
if (r 0) {
goto fail;
}
-if (!backend-info-has_vnet_hdr_len(backend,
- sizeof(struct virtio_net_hdr_mrg_rxbuf))) {
+if (!qemu_has_vnet_hdr_len(backend,
+ sizeof(struct virtio_net_hdr_mrg_rxbuf))) {
net-dev.features = ~(1 VIRTIO_NET_F_MRG_RXBUF);
}
if (~net-dev.features net-dev.backend_features) {
--
1.8.5.3
[Qemu-devel] [PATCH 0/3] net: drop implicit peer from offload API
This series is based on my net tree, which already has Vincenzo's Add netmap backend offloadings support patch series merged. After merging the series I realized we were bypassing the net.h API and directly accessing nc-info-... in some cases. This series cleans that up, at the cost of moving -peer back up to offload API callers. I think that's the right thing to do to make net.h APIs consistent (the other functions don't have implicit -peer) and avoid bypassing the API. Stefan Hajnoczi (3): net: remove implicit peer from offload API vhost_net: use offload API instead of bypassing it virtio-net: use qemu_get_queue() where possible hw/net/vhost_net.c | 6 +++--- hw/net/virtio-net.c | 12 ++-- hw/net/vmxnet3.c| 18 +- include/net/net.h | 14 +++--- net/net.c | 36 ++-- 5 files changed, 43 insertions(+), 43 deletions(-) -- 1.8.5.3
[Qemu-devel] [PATCH 1/3] net: remove implicit peer from offload API
The virtio_net offload APIs are used on the NIC's peer (i.e. the tap
device). The API was defined to implicitly use nc-peer, saving the
caller the trouble.
This wasn't ideal because:
1. There are callers who have the peer but not the NIC. Currently they
are forced to bypass the API and access peer-info-... directly.
2. The rest of the net.h API uses nc, not nc-peer, so it is
inconsistent.
This patch pushes nc-peer back up to callers.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/net/virtio-net.c | 12 ++--
hw/net/vmxnet3.c| 18 +-
include/net/net.h | 14 +++---
net/net.c | 36 ++--
4 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index cda8c75..9218a09 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -325,7 +325,7 @@ static void peer_test_vnet_hdr(VirtIONet *n)
return;
}
-n-has_vnet_hdr = qemu_peer_has_vnet_hdr(nc);
+n-has_vnet_hdr = qemu_has_vnet_hdr(nc-peer);
}
static int peer_has_vnet_hdr(VirtIONet *n)
@@ -338,7 +338,7 @@ static int peer_has_ufo(VirtIONet *n)
if (!peer_has_vnet_hdr(n))
return 0;
-n-has_ufo = qemu_peer_has_ufo(qemu_get_queue(n-nic));
+n-has_ufo = qemu_has_ufo(qemu_get_queue(n-nic)-peer);
return n-has_ufo;
}
@@ -357,8 +357,8 @@ static void virtio_net_set_mrg_rx_bufs(VirtIONet *n, int
mergeable_rx_bufs)
nc = qemu_get_subqueue(n-nic, i);
if (peer_has_vnet_hdr(n)
-qemu_peer_has_vnet_hdr_len(nc, n-guest_hdr_len)) {
-qemu_peer_set_vnet_hdr_len(nc, n-guest_hdr_len);
+qemu_has_vnet_hdr_len(nc-peer, n-guest_hdr_len)) {
+qemu_set_vnet_hdr_len(nc-peer, n-guest_hdr_len);
n-host_hdr_len = n-guest_hdr_len;
}
}
@@ -459,7 +459,7 @@ static uint32_t virtio_net_bad_features(VirtIODevice *vdev)
static void virtio_net_apply_guest_offloads(VirtIONet *n)
{
-qemu_peer_set_offload(qemu_get_subqueue(n-nic, 0),
+qemu_set_offload(qemu_get_subqueue(n-nic, 0)-peer,
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_CSUM)),
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_TSO4)),
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_TSO6)),
@@ -1540,7 +1540,7 @@ static void virtio_net_device_realize(DeviceState *dev,
Error **errp)
peer_test_vnet_hdr(n);
if (peer_has_vnet_hdr(n)) {
for (i = 0; i n-max_queues; i++) {
-qemu_peer_using_vnet_hdr(qemu_get_subqueue(n-nic, i), true);
+qemu_using_vnet_hdr(qemu_get_subqueue(n-nic, i)-peer, true);
}
n-host_hdr_len = sizeof(struct virtio_net_hdr);
} else {
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 0524684..5be807c 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -1290,12 +1290,12 @@ static void vmxnet3_update_features(VMXNET3State *s)
s-lro_supported, rxcso_supported,
s-rx_vlan_stripping);
if (s-peer_has_vhdr) {
-qemu_peer_set_offload(qemu_get_queue(s-nic),
-rxcso_supported,
-s-lro_supported,
-s-lro_supported,
-0,
-0);
+qemu_set_offload(qemu_get_queue(s-nic)-peer,
+ rxcso_supported,
+ s-lro_supported,
+ s-lro_supported,
+ 0,
+ 0);
}
}
@@ -1885,7 +1885,7 @@ static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
{
NetClientState *nc = qemu_get_queue(s-nic);
-if (qemu_peer_has_vnet_hdr(nc)) {
+if (qemu_has_vnet_hdr(nc-peer)) {
return true;
}
@@ -1933,10 +1933,10 @@ static void vmxnet3_net_init(VMXNET3State *s)
s-lro_supported = false;
if (s-peer_has_vhdr) {
-qemu_peer_set_vnet_hdr_len(qemu_get_queue(s-nic),
+qemu_set_vnet_hdr_len(qemu_get_queue(s-nic)-peer,
sizeof(struct virtio_net_hdr));
-qemu_peer_using_vnet_hdr(qemu_get_queue(s-nic), 1);
+qemu_using_vnet_hdr(qemu_get_queue(s-nic)-peer, 1);
}
qemu_format_nic_info_str(qemu_get_queue(s-nic), s-conf.macaddr.a);
diff --git a/include/net/net.h b/include/net/net.h
index 7b25394..8166345 100644
--- a/include/net/net.h
+++ b/include/net/net.h
@@ -132,13 +132,13 @@ ssize_t qemu_send_packet_async(NetClientState *nc, const
uint8_t *buf,
void qemu_purge_queued_packets(NetClientState *nc);
void qemu_flush_queued_packets(NetClientState *nc);
void qemu_format_nic_info_str(NetClientState *nc, uint8_t macaddr[6]);
-bool qemu_peer_has_ufo(NetClientState *nc);
-bool qemu_peer_has_vnet_hdr(NetClientState *nc);
-bool qemu_peer_has_vnet_hdr_len(NetClientState *nc, int len);
-void qemu_peer_using_vnet_hdr(NetClientState *nc, bool enable);
-void qemu_peer_set_offload(NetClientState *nc, int
[Qemu-devel] [PATCH 3/3] virtio-net: use qemu_get_queue() where possible
qemu_get_queue() is a shorthand for qemu_get_subqueue(n-nic, 0). Use
the shorthand where possible.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/net/virtio-net.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 9218a09..3c0342e 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -459,7 +459,7 @@ static uint32_t virtio_net_bad_features(VirtIODevice *vdev)
static void virtio_net_apply_guest_offloads(VirtIONet *n)
{
-qemu_set_offload(qemu_get_subqueue(n-nic, 0)-peer,
+qemu_set_offload(qemu_get_queue(n-nic)-peer,
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_CSUM)),
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_TSO4)),
!!(n-curr_guest_offloads (1ULL VIRTIO_NET_F_GUEST_TSO6)),
--
1.8.5.3
Re: [Qemu-devel] [RFC PATCH v2 01/12] mc: add documentation for micro-checkpointing
Dr. David Alan Gilbert wrote: * Michael R. Hines (mrhi...@linux.vnet.ibm.com) wrote: On 02/19/2014 07:27 PM, Dr. David Alan Gilbert wrote: I was just wondering if a separate 'max buffer size' knob would allow you to more reasonably bound memory without setting policy; I don't think people like having potentially x2 memory. Note: Checkpoint memory is not monotonic in this patchset (which is unique to this implementation). Only if the guest actually dirties 100% of it's memory between one checkpoint to the next will the host experience 2x memory usage for a short period of time. Right, but that doesn't really help - if someone comes along and says 'How much memory do I need to be able to run an mc system?' the only safe answer is 2x, otherwise we're adding a reason why the previously stable guest might OOM. so we may have to involve some disk operations to handle memory exhaustion. Thanks! The patch has a 'slab' mechanism built in to it which implements a water-mark style policy that throws away unused portions of the 2x checkpoint memory if later checkpoints are much smaller (which is likely to be the case if the writable working set size changes). However, to answer your question: Such a knob could be achieved, but the same could be achieved simply by tuning the checkpoint frequency itself. Memory usage would thus be a function of the checkpoint frequency. If the guest application was maniacal, banging away at all the memory, there's very little that can be done in the first place, but if the guest application was mildly busy, you don't want to throw away your ability to be fault tolerant - you would just need more frequent checkpoints to keep up with the dirty rate. I'm not convinced; I can tune my checkpoint frequency until normal operation makes a reasonable trade off between mc frequency and RAM usage, but that doesn't prevent it running away when a garbage collect or some other thing suddenly dirties a load of ram in one particular checkpoint. Some management tool that watches ram usage etc can also help tune it, but in the end it can't stop it taking loads of RAM. Once the application died down - the water-mark policy would kick in and start freeing checkpoint memory. (Note: this policy happens on both sides in the patchset because the patch has to be fully compatible with RDMA memory pinning). What is *not* exposed, however, is the watermark knobs themselves, I definitely think that needs to be exposed - that would also get you a similar control to 'max buffer size' - you could place a time limit on the slab list in the patch or something like that... Good question in general - I'll add it to the FAQ. The patch implements a basic 'transaction' mechanism in coordination with an outbound I/O buffer (documented further down). With these two things in places, split-brain is not possible because the destination is not running. We don't allow the destination to resume execution until a committed transaction has been acknowledged by the destination and only until then do we allow any outbound network traffic to be release to the outside world. Yeh I see the IO buffer, what I've not figured out is how: 1) MC over TCP/IP gets an acknowledge on the source to know when it can unplug it's buffer. Only partially correct (See the steps on the wiki). There are two I/O buffers at any given time which protect against a split-brain scenario: One buffer for the current checkpoint that is being generated (running VM) and one buffer for the checkpoint that is being committed in a transaction. 2) Lets say the MC connection fails, so that ack never arrives, the source must assume the destination has failed and release it's packets and carry on. Only the packets for Buffer A are released for the current committed checkpoint after a completed transaction. The packets for Buffer B (the current running VM) are still being held up until the next transaction starts. Later once the transaction completes and A is released, B becomes the new A and a new buffer is installed to become the new Buffer B for the current running VM. The destination must assume the source has failed and take over. The destination must also receive an ACK. The ack goes both ways. Once the source and destination both acknowledge a completed transation does the source VM resume execution - and even then it's packets are still being buffered until the next transaction starts. (That's why it's important to checkpoint as frequently as possible). I think I understand normal operation - my question here is about failure; what happens when neither side gets any ACKs. 3) If we're relying on TCP/IP timeout that's quite long. Actually, my experience is been that TCP seems to have more than one kind of timeout - if receiver is not responding *at all* - it seems that TCP has a
[Qemu-devel] [PULL 09/30] target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-same
and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,
FACGT, FMLA and FMLS.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/helper-a64.c| 60 ++
target-arm/helper-a64.h| 4
target-arm/helper.h| 2 ++
target-arm/neon_helper.c | 16 +
target-arm/translate-a64.c | 52
5 files changed, 130 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index b4cab51..c2ce33e 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -198,3 +198,63 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void
*fpstp)
float_status *fpst = fpstp;
return -float64_lt(b, a, fpst);
}
+
+/* Reciprocal step and sqrt step. Note that unlike the A32/T32
+ * versions, these do a fully fused multiply-add or
+ * multiply-add-and-halve.
+ */
+#define float32_two make_float32(0x4000)
+#define float32_three make_float32(0x4040)
+#define float32_one_point_five make_float32(0x3fc0)
+
+#define float64_two make_float64(0x4000ULL)
+#define float64_three make_float64(0x4008ULL)
+#define float64_one_point_five make_float64(0x3FF8ULL)
+
+float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+a = float32_chs(a);
+if ((float32_is_infinity(a) float32_is_zero(b)) ||
+(float32_is_infinity(b) float32_is_zero(a))) {
+return float32_two;
+}
+return float32_muladd(a, b, float32_two, 0, fpst);
+}
+
+float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+a = float64_chs(a);
+if ((float64_is_infinity(a) float64_is_zero(b)) ||
+(float64_is_infinity(b) float64_is_zero(a))) {
+return float64_two;
+}
+return float64_muladd(a, b, float64_two, 0, fpst);
+}
+
+float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+a = float32_chs(a);
+if ((float32_is_infinity(a) float32_is_zero(b)) ||
+(float32_is_infinity(b) float32_is_zero(a))) {
+return float32_one_point_five;
+}
+return float32_muladd(a, b, float32_three, float_muladd_halve_result,
fpst);
+}
+
+float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+a = float64_chs(a);
+if ((float64_is_infinity(a) float64_is_zero(b)) ||
+(float64_is_infinity(b) float64_is_zero(a))) {
+return float64_one_point_five;
+}
+return float64_muladd(a, b, float64_three, float_muladd_halve_result,
fpst);
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index bf20466..ab9933c 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -32,3 +32,7 @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64,
ptr)
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
+DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
+DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
+DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
+DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 951e6ad..7c60121 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -382,6 +382,8 @@ DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr)
+DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr)
+DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr)
/* iwmmxt_helper.c */
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index b4c8690..13752ba 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -1823,6 +1823,22 @@ uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b,
void *fpstp)
return -float32_lt(f1, f0, fpst);
}
+uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, void *fpstp)
+{
+float_status *fpst = fpstp;
+float64 f0 = float64_abs(make_float64(a));
+float64 f1 = float64_abs(make_float64(b));
+return -float64_le(f1, f0, fpst);
+}
+
+uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp)
+{
+float_status *fpst = fpstp;
+float64 f0 = float64_abs(make_float64(a));
+float64 f1 = float64_abs(make_float64(b));
+return -float64_lt(f1, f0, fpst);
+}
+
#define ELEM(V, N, SIZE) (((V) ((N) * (SIZE))) ((1ull (SIZE)) - 1))
void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
diff --git
[Qemu-devel] [PULL 30/30] linux-user: AArch64: Fix exclusive store of the zero register
From: Janne Grunau j...@jannau.net
Signed-off-by: Janne Grunau j...@jannau.net
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
linux-user/main.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index cabc9e1..9192977 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -953,7 +953,8 @@ static int do_strex_a64(CPUARMState *env)
goto finish;
}
}
-val = env-xregs[rt];
+/* handle the zero register */
+val = rt == 31 ? 0 : env-xregs[rt];
switch (size) {
case 0:
segv = put_user_u8(val, addr);
@@ -972,7 +973,8 @@ static int do_strex_a64(CPUARMState *env)
goto error;
}
if (is_pair) {
-val = env-xregs[rt2];
+/* handle the zero register */
+val = rt2 == 31 ? 0 : env-xregs[rt2];
if (size == 2) {
segv = put_user_u32(val, addr + 4);
} else {
--
1.8.5
[Qemu-devel] [PULL 28/30] target-arm: A64: Implement narrowing three-reg-diff operations
Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 60 +-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 511f15e..cb630d8 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7152,6 +7152,60 @@ static void handle_3rd_wide(DisasContext *s, int is_q,
int is_u, int size,
}
}
+static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in)
+{
+tcg_gen_shri_i64(in, in, 32);
+tcg_gen_trunc_i64_i32(res, in);
+}
+
+static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
+{
+tcg_gen_addi_i64(in, in, 1U 31);
+do_narrow_high_u32(res, in);
+}
+
+static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
+ int opcode, int rd, int rn, int rm)
+{
+TCGv_i32 tcg_res[2];
+int part = is_q ? 2 : 0;
+int pass;
+
+for (pass = 0; pass 2; pass++) {
+TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+TCGv_i64 tcg_wideres = tcg_temp_new_i64();
+static NeonGenNarrowFn * const narrowfns[3][2] = {
+{ gen_helper_neon_narrow_high_u8,
+ gen_helper_neon_narrow_round_high_u8 },
+{ gen_helper_neon_narrow_high_u16,
+ gen_helper_neon_narrow_round_high_u16 },
+{ do_narrow_high_u32, do_narrow_round_high_u32 },
+};
+NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
+
+read_vec_element(s, tcg_op1, rn, pass, MO_64);
+read_vec_element(s, tcg_op2, rm, pass, MO_64);
+
+gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
+
+tcg_temp_free_i64(tcg_op1);
+tcg_temp_free_i64(tcg_op2);
+
+tcg_res[pass] = tcg_temp_new_i32();
+gennarrow(tcg_res[pass], tcg_wideres);
+tcg_temp_free_i64(tcg_wideres);
+}
+
+for (pass = 0; pass 2; pass++) {
+write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
+tcg_temp_free_i32(tcg_res[pass]);
+}
+if (!is_q) {
+clear_vec_high(s, rd);
+}
+}
+
/* C3.6.15 AdvSIMD three different
* 31 30 29 28 24 23 22 21 20 16 1512 11 10 95 40
* +---+---+---+---+--+---+--++-+--+--+
@@ -7191,7 +7245,11 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
/* 128 x 128 - 64 */
-unsupported_encoding(s, insn);
+if (size == 3) {
+unallocated_encoding(s);
+return;
+}
+handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
break;
case 14: /* PMULL, PMULL2 */
if (is_u || size == 1 || size == 2) {
--
1.8.5
[Qemu-devel] [PULL 10/30] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_* constant to include all the ones currently supported by the kernel headers we are using. Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- target-arm/kvm-consts.h | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index 0e7f889..6009a33 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -50,15 +50,29 @@ MISMATCH_CHECK(PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) MISMATCH_CHECK(PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) MISMATCH_CHECK(PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) +/* Note that KVM uses overlapping values for AArch32 and AArch64 + * target CPU numbers. AArch32 targets: + */ #define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 +#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 + +/* AArch64 targets: */ +#define QEMU_KVM_ARM_TARGET_AEM_V8 0 +#define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 +#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 /* There's no kernel define for this: sentinel value which * matches no KVM target value for either 64 or 32 bit */ #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX -#ifndef TARGET_AARCH64 +#ifdef TARGET_AARCH64 +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) +#else MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) #endif #define CP_REG_ARM64 0x6000ULL -- 1.8.5
[Qemu-devel] [PULL 29/30] target-arm: A64: Implement unprivileged load/store
Implement the unprivileged load and store instructions.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 69 +-
1 file changed, 37 insertions(+), 32 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cb630d8..8752e7e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -618,20 +618,26 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64
t0, TCGv_i64 t1)
*/
/*
- * Store from GPR register to memory
+ * Store from GPR register to memory.
*/
+static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
+ TCGv_i64 tcg_addr, int size, int memidx)
+{
+g_assert(size = 3);
+tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size);
+}
+
static void do_gpr_st(DisasContext *s, TCGv_i64 source,
TCGv_i64 tcg_addr, int size)
{
-g_assert(size = 3);
-tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size);
+do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
}
/*
* Load from memory to GPR register
*/
-static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
- int size, bool is_signed, bool extend)
+static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
+ int size, bool is_signed, bool extend, int memidx)
{
TCGMemOp memop = MO_TE + size;
@@ -641,7 +647,7 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,
TCGv_i64 tcg_addr,
memop += MO_SIGN;
}
-tcg_gen_qemu_ld_i64(dest, tcg_addr, get_mem_index(s), memop);
+tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
if (extend is_signed) {
g_assert(size 3);
@@ -649,6 +655,13 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,
TCGv_i64 tcg_addr,
}
}
+static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
+ int size, bool is_signed, bool extend)
+{
+do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
+ get_mem_index(s));
+}
+
/*
* Store from FP register to memory
*/
@@ -1824,6 +1837,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
* ++---+---+-+-+---++-+--+--+
*
* idx = 01 - post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
+ 10 - unprivileged
* V = 0 - non-vector
* size: 00 - 8 bit, 01 - 16 bit, 10 - 32 bit, 11 - 64bit
* opc: 00 - store, 01 - loadu, 10 - loads 64, 11 - loads 32
@@ -1839,6 +1853,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
+bool is_unpriv = (idx == 2);
bool is_vector = extract32(insn, 26, 1);
bool post_index;
bool writeback;
@@ -1847,7 +1862,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
if (is_vector) {
size |= (opc 2) 1;
-if (size 4) {
+if (size 4 || is_unpriv) {
unallocated_encoding(s);
return;
}
@@ -1855,6 +1870,10 @@ static void disas_ldst_reg_imm9(DisasContext *s,
uint32_t insn)
} else {
if (size == 3 opc == 2) {
/* PRFM - prefetch */
+if (is_unpriv) {
+unallocated_encoding(s);
+return;
+}
return;
}
if (opc == 3 size 1) {
@@ -1868,6 +1887,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
switch (idx) {
case 0:
+case 2:
post_index = false;
writeback = false;
break;
@@ -1879,9 +1899,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
post_index = false;
writeback = true;
break;
-case 2:
-g_assert(false);
-break;
}
if (rn == 31) {
@@ -1901,10 +1918,13 @@ static void disas_ldst_reg_imm9(DisasContext *s,
uint32_t insn)
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
+int memidx = is_unpriv ? 1 : get_mem_index(s);
+
if (is_store) {
-do_gpr_st(s, tcg_rt, tcg_addr, size);
+do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
} else {
-do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
+do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
+ is_signed, is_extended, memidx);
}
}
@@ -2084,25 +2104,6 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s,
uint32_t insn)
}
}
-/* Load/store register (immediate forms) */
-static void disas_ldst_reg_imm(DisasContext *s, uint32_t insn)
-{
-switch (extract32(insn, 10, 2)) {
-case 0: case 1: case 3:
-/* Load/store register (unscaled immediate) */
-/*
[Qemu-devel] [PULL 16/30] target-arm: Split cpreg access checks out from read/write functions
Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedicated
check access rights function pointer in the ARMCPRegInfo.
This will allow us to simplify some of the register definitions,
which no longer need read/write functions purely to handle
the access checks.
We take the opportunity to define the return value from the
access checking function in a way that allows us to set the
correct exception syndrome information for exceptions taken
to AArch64 (which may need to distinguish access failures due
to a configurable trap or enable from other kinds of access
failure).
This commit defines the new mechanism but does not move any
of the registers across to use it.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu.h | 29 +
target-arm/helper.h| 1 +
target-arm/op_helper.c | 18 ++
target-arm/translate-a64.c | 11 +++
target-arm/translate.c | 11 +++
5 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ab57f55..cc3d0ac 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -811,14 +811,29 @@ static inline int arm_current_pl(CPUARMState *env)
typedef struct ARMCPRegInfo ARMCPRegInfo;
-/* Access functions for coprocessor registers. These should return
- * 0 on success, or one of the EXCP_* constants if access should cause
- * an exception (in which case *value is not written).
- */
+typedef enum CPAccessResult {
+/* Access is permitted */
+CP_ACCESS_OK = 0,
+/* Access fails due to a configurable trap or enable which would
+ * result in a categorized exception syndrome giving information about
+ * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
+ * 0xc or 0x18).
+ */
+CP_ACCESS_TRAP = 1,
+/* Access fails and results in an exception syndrome 0x0 (uncategorized).
+ * Note that this is not a catch-all case -- the set of cases which may
+ * result in this failure is specifically defined by the architecture.
+ */
+CP_ACCESS_TRAP_UNCATEGORIZED = 2,
+} CPAccessResult;
+
+/* Access functions for coprocessor registers. These should always succeed. */
typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t *value);
typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value);
+/* Access permission check functions for coprocessor registers. */
+typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo
*opaque);
/* Hook function for register reset */
typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
@@ -872,6 +887,12 @@ struct ARMCPRegInfo {
* 2. both readfn and writefn are specified
*/
ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+/* Function for making any access checks for this register in addition to
+ * those specified by the 'access' permissions bits. If NULL, no extra
+ * checks required. The access check is performed at runtime, not at
+ * translate time.
+ */
+CPAccessFn *accessfn;
/* Function for handling reads of this register. If NULL, then reads
* will be done by loading from the offset into CPUARMState specified
* by fieldoffset.
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 7c60121..19bd620 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -57,6 +57,7 @@ DEF_HELPER_1(cpsr_read, i32, env)
DEF_HELPER_3(v7m_msr, void, env, i32, i32)
DEF_HELPER_2(v7m_mrs, i32, env, i32)
+DEF_HELPER_2(access_check_cp_reg, void, env, ptr)
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index a918e5b..34c5e7f 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -273,6 +273,24 @@ void HELPER(set_user_reg)(CPUARMState *env, uint32_t
regno, uint32_t val)
}
}
+void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip)
+{
+const ARMCPRegInfo *ri = rip;
+switch (ri-accessfn(env, ri)) {
+case CP_ACCESS_OK:
+return;
+case CP_ACCESS_TRAP:
+case CP_ACCESS_TRAP_UNCATEGORIZED:
+/* These cases will eventually need to generate different
+ * syndrome information.
+ */
+break;
+default:
+g_assert_not_reached();
+}
+raise_exception(env, EXCP_UDEF);
+}
+
void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
{
const ARMCPRegInfo *ri = rip;
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index
[Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns
From: Alex Bennée alex.ben...@linaro.org
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 124 +++--
1 file changed, 86 insertions(+), 38 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bcf32a1..91128f5 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7105,39 +7105,22 @@ static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1,
TCGv_i32 op2)
tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
}
-/* Pairwise op subgroup of C3.6.16. */
-static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
+/* Pairwise op subgroup of C3.6.16.
+ *
+ * This is called directly or via the handle_3same_float for float pairwise
+ * operations where the opcode and size are calculated differently.
+ */
+static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int
opcode,
+ int size, int rn, int rm, int rd)
{
-int is_q = extract32(insn, 30, 1);
-int u = extract32(insn, 29, 1);
-int size = extract32(insn, 22, 2);
-int opcode = extract32(insn, 11, 5);
-int rm = extract32(insn, 16, 5);
-int rn = extract32(insn, 5, 5);
-int rd = extract32(insn, 0, 5);
+TCGv_ptr fpst;
int pass;
-if (size == 3 !is_q) {
-unallocated_encoding(s);
-return;
-}
-
-switch (opcode) {
-case 0x14: /* SMAXP, UMAXP */
-case 0x15: /* SMINP, UMINP */
-if (size == 3) {
-unallocated_encoding(s);
-return;
-}
-break;
-case 0x17:
-if (u) {
-unallocated_encoding(s);
-return;
-}
-break;
-default:
-g_assert_not_reached();
+/* Floating point operations need fpst */
+if (opcode = 0x58) {
+fpst = get_fpstatus_ptr();
+} else {
+TCGV_UNUSED_PTR(fpst);
}
/* These operations work on the concatenated rm:rn, with each pair of
@@ -7155,9 +7138,28 @@ static void disas_simd_3same_pair(DisasContext *s,
uint32_t insn)
read_vec_element(s, tcg_op2, passreg, 1, MO_64);
tcg_res[pass] = tcg_temp_new_i64();
-/* The only 64 bit pairwise integer op is ADDP */
-assert(opcode == 0x17);
-tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
+switch (opcode) {
+case 0x17: /* ADDP */
+tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
+break;
+case 0x58: /* FMAXNMP */
+gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x5a: /* FADDP */
+gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x5e: /* FMAXP */
+gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x78: /* FMINNMP */
+gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x7e: /* FMINP */
+gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+default:
+g_assert_not_reached();
+}
tcg_temp_free_i64(tcg_op1);
tcg_temp_free_i64(tcg_op2);
@@ -7174,7 +7176,7 @@ static void disas_simd_3same_pair(DisasContext *s,
uint32_t insn)
for (pass = 0; pass maxpass; pass++) {
TCGv_i32 tcg_op1 = tcg_temp_new_i32();
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
-NeonGenTwoOpFn *genfn;
+NeonGenTwoOpFn *genfn = NULL;
int passreg = pass (maxpass / 2) ? rn : rm;
int passelt = (is_q (pass 1)) ? 2 : 0;
@@ -7213,11 +7215,30 @@ static void disas_simd_3same_pair(DisasContext *s,
uint32_t insn)
genfn = fns[size][u];
break;
}
+/* The FP operations are all on single floats (32 bit) */
+case 0x58: /* FMAXNMP */
+gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x5a: /* FADDP */
+gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x5e: /* FMAXP */
+gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst);
+break;
+case 0x78: /* FMINNMP */
+
[Qemu-devel] [PULL 27/30] target-arm: A64: Implement the wide 3-reg-different operations
Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 809fbdb..511f15e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7117,6 +7117,41 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
tcg_temp_free_i64(tcg_res[1]);
}
+static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
+int opcode, int rd, int rn, int rm)
+{
+TCGv_i64 tcg_res[2];
+int part = is_q ? 2 : 0;
+int pass;
+
+for (pass = 0; pass 2; pass++) {
+TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
+static NeonGenWidenFn * const widenfns[3][2] = {
+{ gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
+{ gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
+{ tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
+};
+NeonGenWidenFn *widenfn = widenfns[size][is_u];
+
+read_vec_element(s, tcg_op1, rn, pass, MO_64);
+read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
+widenfn(tcg_op2_wide, tcg_op2);
+tcg_temp_free_i32(tcg_op2);
+tcg_res[pass] = tcg_temp_new_i64();
+gen_neon_addl(size, (opcode == 3),
+ tcg_res[pass], tcg_op1, tcg_op2_wide);
+tcg_temp_free_i64(tcg_op1);
+tcg_temp_free_i64(tcg_op2_wide);
+}
+
+for (pass = 0; pass 2; pass++) {
+write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
+tcg_temp_free_i64(tcg_res[pass]);
+}
+}
+
/* C3.6.15 AdvSIMD three different
* 31 30 29 28 24 23 22 21 20 16 1512 11 10 95 40
* +---+---+---+---+--+---+--++-+--+--+
@@ -7147,7 +7182,11 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
/* 64 x 128 - 128 */
-unsupported_encoding(s, insn);
+if (size == 3) {
+unallocated_encoding(s);
+return;
+}
+handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
break;
case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
--
1.8.5
[Qemu-devel] [PULL 00/30] target-arm queue
Here's the latest target-arm pull request. There are definitely more things still in the pipeline so there will be at least one more before softfreeze... thanks -- PMM The following changes since commit 46eef33b89e936ca793e13c4aeea1414e97e8dbb: Fix QEMU build on OpenBSD on x86 archs (2014-02-17 11:44:00 +) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140220 for you to fetch changes up to 2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177: linux-user: AArch64: Fix exclusive store of the zero register (2014-02-20 10:35:56 +) target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as groundwork for AArch64 system mode * Fix bug in linux-user A64 store-exclusive of XZR Alex Bennée (2): target-arm: A64: Implement SIMD FP compare and set insns target-arm: A64: Implement floating point pairwise insns Janne Grunau (1): linux-user: AArch64: Fix exclusive store of the zero register Peter Maydell (27): hw/intc/arm_gic: Fix NVIC assertion failure target-arm: A64: Implement plain vector SIMD indexed element insns target-arm: A64: Implement long vector x indexed insns target-arm: A64: Implement SIMD scalar indexed instructions target-arm: A64: Implement scalar three different instructions softfloat: Support halving the result of muladd operation target-arm: A64: Implement remaining 3-same instructions target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs target-arm: Define names for SCTLR bits target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Remove unused ARMCPUState sr substruct target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Stop underdecoding ARM946 PRBS registers target-arm: Split cpreg access checks out from read/write functions target-arm: Convert performance monitor reginfo to accessfn target-arm: Convert generic timer reginfo to accessfn target-arm: Convert miscellaneous reginfo structs to accessfn target-arm: Drop success/fail return from cpreg read and write functions target-arm: Remove unnecessary code now read/write fns can't fail target-arm: Remove failure status return from read/write_raw_cp_reg target-arm: Fix incorrect type for value argument to write_raw_cp_reg target-arm: A64: Implement store-exclusive for system mode target-arm: A64: Add opcode comments to disas_simd_three_reg_diff target-arm: A64: Add most remaining three-reg-diff widening ops target-arm: A64: Implement the wide 3-reg-different operations target-arm: A64: Implement narrowing three-reg-diff operations target-arm: A64: Implement unprivileged load/store fpu/softfloat.c| 38 ++ hw/arm/pxa2xx.c| 36 +- hw/arm/pxa2xx_pic.c| 11 +- hw/intc/arm_gic.c |2 +- include/fpu/softfloat.h|3 + linux-user/main.c |6 +- target-arm/cpu.c |8 +- target-arm/cpu.h | 105 +++- target-arm/helper-a64.c| 105 target-arm/helper-a64.h|9 + target-arm/helper.c| 620 +--- target-arm/helper.h|3 + target-arm/kvm-consts.h| 16 +- target-arm/neon_helper.c | 16 + target-arm/op_helper.c | 46 +- target-arm/translate-a64.c | 1358 ++-- target-arm/translate.c | 28 +- 17 files changed, 1815 insertions(+), 595 deletions(-)
[Qemu-devel] [PULL 19/30] target-arm: Convert miscellaneous reginfo structs to accessfn
Convert the remaining miscellaneous cases of reginfo read/write
functions returning EXCP_UDEF to use an accessfn instead:
TEEHBR, and the ATS address-translation operations.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 44 +++-
1 file changed, 19 insertions(+), 25 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aec052b..00117c2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -682,27 +682,12 @@ static int teecr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
return 0;
}
-static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static CPAccessResultg teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
-/* This is a helper function because the user access rights
- * depend on the value of the TEECR.
- */
if (arm_current_pl(env) == 0 (env-teecr 1)) {
-return EXCP_UDEF;
-}
-*value = env-teehbr;
-return 0;
-}
-
-static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t value)
-{
-if (arm_current_pl(env) == 0 (env-teecr 1)) {
-return EXCP_UDEF;
+return CP_ACCESS_TRAP;
}
-env-teehbr = value;
-return 0;
+return CP_ACCESS_OK;
}
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
@@ -712,8 +697,7 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
.writefn = teecr_write },
{ .name = TEEHBR, .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
- .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
- .readfn = teehbr_read, .writefn = teehbr_write },
+ .accessfn = teehbr_access, .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -1031,6 +1015,19 @@ static inline bool
extended_addresses_enabled(CPUARMState *env)
(env-cp15.c2_control (1U 31));
}
+static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+if (ri-opc2 4) {
+/* Other states are only available with TrustZone; in
+ * a non-TZ implementation these registers don't exist
+ * at all, which is an Uncategorized trap. This underdecoding
+ * is safe because the reginfo is NO_MIGRATE.
+ */
+return CP_ACCESS_TRAP_UNCATEGORIZED;
+}
+return CP_ACCESS_OK;
+}
+
static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
hwaddr phys_addr;
@@ -1039,10 +1036,6 @@ static int ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
int ret, is_user = ri-opc2 2;
int access_type = ri-opc2 1;
-if (ri-opc2 4) {
-/* Other states are only available with TrustZone */
-return EXCP_UDEF;
-}
ret = get_phys_addr(env, value, access_type, is_user,
phys_addr, prot, page_size);
if (extended_addresses_enabled(env)) {
@@ -1095,7 +1088,8 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
.writefn = par_write },
#ifndef CONFIG_USER_ONLY
{ .name = ATS, .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
+ .access = PL1_W, .accessfn = ats_access,
+ .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
#endif
REGINFO_SENTINEL
};
--
1.8.5
[Qemu-devel] [PULL 25/30] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 3de9cad..d4e7a20 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7091,24 +7091,24 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
/* 128 x 128 - 64 */
unsupported_encoding(s, insn);
break;
-case 9:
-case 11:
-case 13:
-case 14:
+case 9: /* SQDMLAL, SQDMLAL2 */
+case 11: /* SQDMLSL, SQDMLSL2 */
+case 13: /* SQDMULL, SQDMULL2 */
+case 14: /* PMULL, PMULL2 */
if (is_u) {
unallocated_encoding(s);
return;
}
/* fall through */
-case 0:
-case 2:
+case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
+case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
unsupported_encoding(s, insn);
break;
-case 5:
-case 7:
-case 8:
-case 10:
-case 12:
+case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
+case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
+case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
/* 64 x 64 - 128 */
if (size == 3) {
unallocated_encoding(s);
--
1.8.5
[Qemu-devel] [PULL 03/30] target-arm: A64: Implement long vector x indexed insns
Implement the 'long' operations in the vector x indexed
element category.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 144 +++--
1 file changed, 139 insertions(+), 5 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a96ee4a..f1cd08a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7909,11 +7909,6 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
}
}
-if (is_long) {
-unsupported_encoding(s, insn);
-return;
-}
-
if (is_fp) {
fpst = get_fpstatus_ptr();
} else {
@@ -8055,6 +8050,145 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
}
} else {
/* long ops: 16x16-32 or 32x32-64 */
+TCGv_i64 tcg_res[2];
+int pass;
+bool satop = extract32(opcode, 0, 1);
+TCGMemOp memop = MO_32;
+
+if (satop || !u) {
+memop |= MO_SIGN;
+}
+
+if (size == 2) {
+TCGv_i64 tcg_idx = tcg_temp_new_i64();
+
+read_vec_element(s, tcg_idx, rm, index, memop);
+
+for (pass = 0; pass 2; pass++) {
+TCGv_i64 tcg_op = tcg_temp_new_i64();
+TCGv_i64 tcg_passres;
+
+read_vec_element(s, tcg_op, rn, pass + (is_q * 2), memop);
+
+tcg_res[pass] = tcg_temp_new_i64();
+
+if (opcode == 0xa || opcode == 0xb) {
+/* Non-accumulating ops */
+tcg_passres = tcg_res[pass];
+} else {
+tcg_passres = tcg_temp_new_i64();
+}
+
+tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
+tcg_temp_free_i64(tcg_op);
+
+if (satop) {
+/* saturating, doubling */
+gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
+ tcg_passres,
tcg_passres);
+}
+
+if (opcode == 0xa || opcode == 0xb) {
+continue;
+}
+
+/* Accumulating op: handle accumulate step */
+read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
+
+switch (opcode) {
+case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
+tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
+break;
+case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
+tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
+break;
+case 0x7: /* SQDMLSL, SQDMLSL2 */
+tcg_gen_neg_i64(tcg_passres, tcg_passres);
+/* fall through */
+case 0x3: /* SQDMLAL, SQDMLAL2 */
+gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
+ tcg_res[pass],
+ tcg_passres);
+break;
+default:
+g_assert_not_reached();
+}
+tcg_temp_free_i64(tcg_passres);
+}
+tcg_temp_free_i64(tcg_idx);
+} else {
+TCGv_i32 tcg_idx = tcg_temp_new_i32();
+
+assert(size == 1);
+read_vec_element_i32(s, tcg_idx, rm, index, size);
+
+/* The simplest way to handle the 16x16 indexed ops is to duplicate
+ * the index into both halves of the 32 bit tcg_idx and then use
+ * the usual Neon helpers.
+ */
+tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
+
+for (pass = 0; pass 2; pass++) {
+TCGv_i32 tcg_op = tcg_temp_new_i32();
+TCGv_i64 tcg_passres;
+
+read_vec_element_i32(s, tcg_op, rn, pass + (is_q * 2), MO_32);
+tcg_res[pass] = tcg_temp_new_i64();
+
+if (opcode == 0xa || opcode == 0xb) {
+/* Non-accumulating ops */
+tcg_passres = tcg_res[pass];
+} else {
+tcg_passres = tcg_temp_new_i64();
+}
+
+if (memop MO_SIGN) {
+gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
+} else {
+gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
+}
+if (satop) {
+gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
+ tcg_passres,
tcg_passres);
+}
+tcg_temp_free_i32(tcg_op);
+
+if (opcode == 0xa || opcode == 0xb) {
+continue;
+
[Qemu-devel] [PULL 26/30] target-arm: A64: Add most remaining three-reg-diff widening ops
Add the remainder of the 64x64-128 operations in the three-reg-diff
category except for PMULL, PMULL2.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 109 -
1 file changed, 88 insertions(+), 21 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d4e7a20..809fbdb 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -75,8 +75,10 @@ typedef struct AArch64DecodeTable {
/* Function prototype for gen_ functions for calling Neon helpers */
typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
@@ -6879,6 +6881,24 @@ static void disas_simd_shift_imm(DisasContext *s,
uint32_t insn)
}
}
+/* Generate code to do a long addition or subtraction, ie one done in
+ * TCGv_i64 on vector lanes twice the width specified by size.
+ */
+static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
+ TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
+{
+static NeonGenTwo64OpFn * const fns[3][2] = {
+{ gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
+{ gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
+{ tcg_gen_add_i64, tcg_gen_sub_i64 },
+};
+NeonGenTwo64OpFn *genfn;
+assert(size 3);
+
+genfn = fns[size][is_sub];
+genfn(tcg_res, tcg_op1, tcg_op2);
+}
+
static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
int opcode, int rd, int rn, int rm)
{
@@ -6934,6 +6954,12 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
}
switch (opcode) {
+case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
+tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
+break;
+case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
+tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
+break;
case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
{
@@ -6954,15 +6980,31 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
break;
+case 9: /* SQDMLAL, SQDMLAL2 */
+case 11: /* SQDMLSL, SQDMLSL2 */
+case 13: /* SQDMULL, SQDMULL2 */
+tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
+gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
+ tcg_passres, tcg_passres);
+break;
default:
g_assert_not_reached();
}
-if (accop 0) {
+if (opcode == 9 || opcode == 11) {
+/* saturating accumulate ops */
+if (accop 0) {
+tcg_gen_neg_i64(tcg_passres, tcg_passres);
+}
+gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
+ tcg_res[pass], tcg_passres);
+} else if (accop 0) {
tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
-tcg_temp_free_i64(tcg_passres);
} else if (accop 0) {
tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
+}
+
+if (accop != 0) {
tcg_temp_free_i64(tcg_passres);
}
@@ -6987,6 +7029,23 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
}
switch (opcode) {
+case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
+case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
+{
+TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
+static NeonGenWidenFn * const widenfns[2][2] = {
+{ gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
+{ gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
+};
+NeonGenWidenFn *widenfn = widenfns[size][is_u];
+
+widenfn(tcg_op2_64, tcg_op2);
+widenfn(tcg_passres, tcg_op1);
+gen_neon_addl(size, (opcode == 2), tcg_passres,
+ tcg_passres, tcg_op2_64);
+
[Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from read/write_raw_cp_reg
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 36
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f04e15e..59db883 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -126,35 +126,30 @@ static void raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t *v)
+static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
{
-/* Raw read of a coprocessor register (as needed for migration, etc)
- * return true on success, false if the read is impossible for some reason.
- */
+/* Raw read of a coprocessor register (as needed for migration, etc). */
if (ri-type ARM_CP_CONST) {
-*v = ri-resetvalue;
+return ri-resetvalue;
} else if (ri-raw_readfn) {
-*v = ri-raw_readfn(env, ri);
+return ri-raw_readfn(env, ri);
} else if (ri-readfn) {
-*v = ri-readfn(env, ri);
+return ri-readfn(env, ri);
} else {
-*v = raw_read(env, ri);
+return raw_read(env, ri);
}
-return true;
}
-static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
+static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
int64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
- * Return true on success, false if the write is impossible for some
reason.
* Note that constant registers are treated as write-ignored; the
* caller should check for success by whether a readback gives the
* value written.
*/
if (ri-type ARM_CP_CONST) {
-return true;
+return;
} else if (ri-raw_writefn) {
ri-raw_writefn(env, ri, v);
} else if (ri-writefn) {
@@ -162,7 +157,6 @@ static bool write_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri,
} else {
raw_write(env, ri, v);
}
-return true;
}
bool write_cpustate_to_list(ARMCPU *cpu)
@@ -174,7 +168,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
for (i = 0; i cpu-cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu-cpreg_indexes[i]);
const ARMCPRegInfo *ri;
-uint64_t v;
+
ri = get_arm_cp_reginfo(cpu-cp_regs, regidx);
if (!ri) {
ok = false;
@@ -183,11 +177,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
if (ri-type ARM_CP_NO_MIGRATE) {
continue;
}
-if (!read_raw_cp_reg(cpu-env, ri, v)) {
-ok = false;
-continue;
-}
-cpu-cpreg_values[i] = v;
+cpu-cpreg_values[i] = read_raw_cp_reg(cpu-env, ri);
}
return ok;
}
@@ -200,7 +190,6 @@ bool write_list_to_cpustate(ARMCPU *cpu)
for (i = 0; i cpu-cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu-cpreg_indexes[i]);
uint64_t v = cpu-cpreg_values[i];
-uint64_t readback;
const ARMCPRegInfo *ri;
ri = get_arm_cp_reginfo(cpu-cp_regs, regidx);
@@ -215,9 +204,8 @@ bool write_list_to_cpustate(ARMCPU *cpu)
* (to catch read-only registers and partially read-only
* registers where the incoming migration value doesn't match)
*/
-if (!write_raw_cp_reg(cpu-env, ri, v) ||
-!read_raw_cp_reg(cpu-env, ri, readback) ||
-readback != v) {
+write_raw_cp_reg(cpu-env, ri, v);
+if (read_raw_cp_reg(cpu-env, ri) != v) {
ok = false;
}
}
--
1.8.5
[Qemu-devel] [PULL 24/30] target-arm: A64: Implement store-exclusive for system mode
System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 68 ++
1 file changed, 62 insertions(+), 6 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ef305e3..3de9cad 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1487,12 +1487,68 @@ static void gen_store_exclusive(DisasContext *s, int
rd, int rt, int rt2,
}
#else
static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
-TCGv_i64 addr, int size, int is_pair)
-{
-qemu_log_mask(LOG_UNIMP,
- %s:%d: system mode store_exclusive unsupported
- at pc=%016 PRIx64 \n,
- __FILE__, __LINE__, s-pc - 4);
+TCGv_i64 inaddr, int size, int is_pair)
+{
+/* if (env-exclusive_addr == addr env-exclusive_val == [addr]
+ * (!is_pair || env-exclusive_high == [addr + datasize])) {
+ * [addr] = {Rt};
+ * if (is_pair) {
+ * [addr + datasize] = {Rt2};
+ * }
+ * {Rd} = 0;
+ * } else {
+ * {Rd} = 1;
+ * }
+ * env-exclusive_addr = -1;
+ */
+int fail_label = gen_new_label();
+int done_label = gen_new_label();
+TCGv_i64 addr = tcg_temp_local_new_i64();
+TCGv_i64 tmp;
+
+/* Copy input into a local temp so it is not trashed when the
+ * basic block ends at the branch insn.
+ */
+tcg_gen_mov_i64(addr, inaddr);
+tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
+
+tmp = tcg_temp_new_i64();
+tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
+tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
+tcg_temp_free_i64(tmp);
+
+if (is_pair) {
+TCGv_i64 addrhi = tcg_temp_new_i64();
+TCGv_i64 tmphi = tcg_temp_new_i64();
+
+tcg_gen_addi_i64(addrhi, addr, 1 size);
+tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
+tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
+
+tcg_temp_free_i64(tmphi);
+tcg_temp_free_i64(addrhi);
+}
+
+/* We seem to still have the exclusive monitor, so do the store */
+tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
+if (is_pair) {
+TCGv_i64 addrhi = tcg_temp_new_i64();
+
+tcg_gen_addi_i64(addrhi, addr, 1 size);
+tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
+get_mem_index(s), MO_TE + size);
+tcg_temp_free_i64(addrhi);
+}
+
+tcg_temp_free_i64(addr);
+
+tcg_gen_movi_i64(cpu_reg(s, rd), 0);
+tcg_gen_br(done_label);
+gen_set_label(fail_label);
+tcg_gen_movi_i64(cpu_reg(s, rd), 1);
+gen_set_label(done_label);
+tcg_gen_movi_i64(cpu_exclusive_addr, -1);
+
}
#endif
--
1.8.5
[Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure
Commit 40d225009ef accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
gic_acknowledge_irq: Assertion `s-sgi_pending[irq][cpu] != 0' failed.
Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
---
hw/intc/arm_gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 93eaa6b..955b8d4 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -189,7 +189,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
}
s-last_active[irq][cpu] = s-running_irq[cpu];
-if (s-revision == REV_11MPCORE) {
+if (s-revision == REV_11MPCORE || s-revision == REV_NVIC) {
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
--
1.8.5
[Qemu-devel] [PULL 08/30] softfloat: Support halving the result of muladd operation
The ARMv8 instruction set includes a fused floating point
reciprocal square root step instruction which demands an
(x * y + z) / 2 fused operation. Support this by adding
a flag to the softfloat muladd operations which requests
that the result is halved before rounding.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
fpu/softfloat.c | 38 ++
include/fpu/softfloat.h | 3 +++
2 files changed, 41 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index e0ea599..fc0b179 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2372,6 +2372,17 @@ float32 float32_muladd(float32 a, float32 b, float32 c,
int flags STATUS_PARAM)
}
}
/* Zero plus something non-zero : just return the something */
+if (flags float_muladd_halve_result) {
+if (cExp == 0) {
+normalizeFloat32Subnormal(cSig, cExp, cSig);
+}
+/* Subtract one to halve, and one again because roundAndPackFloat32
+ * wants one less than the true exponent.
+ */
+cExp -= 2;
+cSig = (cSig | 0x0080) 7;
+return roundAndPackFloat32(cSign ^ signflip, cExp, cSig
STATUS_VAR);
+}
return packFloat32(cSign ^ signflip, cExp, cSig);
}
@@ -2408,6 +2419,9 @@ float32 float32_muladd(float32 a, float32 b, float32 c,
int flags STATUS_PARAM)
/* Throw out the special case of c being an exact zero now */
shift64RightJamming(pSig64, 32, pSig64);
pSig = pSig64;
+if (flags float_muladd_halve_result) {
+pExp--;
+}
return roundAndPackFloat32(zSign, pExp - 1,
pSig STATUS_VAR);
}
@@ -2472,6 +2486,10 @@ float32 float32_muladd(float32 a, float32 b, float32 c,
int flags STATUS_PARAM)
zSig64 = shiftcount;
zExp -= shiftcount;
}
+if (flags float_muladd_halve_result) {
+zExp--;
+}
+
shift64RightJamming(zSig64, 32, zSig64);
return roundAndPackFloat32(zSign, zExp, zSig64 STATUS_VAR);
}
@@ -4088,6 +4106,17 @@ float64 float64_muladd(float64 a, float64 b, float64 c,
int flags STATUS_PARAM)
}
}
/* Zero plus something non-zero : just return the something */
+if (flags float_muladd_halve_result) {
+if (cExp == 0) {
+normalizeFloat64Subnormal(cSig, cExp, cSig);
+}
+/* Subtract one to halve, and one again because roundAndPackFloat64
+ * wants one less than the true exponent.
+ */
+cExp -= 2;
+cSig = (cSig | 0x0010ULL) 10;
+return roundAndPackFloat64(cSign ^ signflip, cExp, cSig
STATUS_VAR);
+}
return packFloat64(cSign ^ signflip, cExp, cSig);
}
@@ -4123,6 +4152,9 @@ float64 float64_muladd(float64 a, float64 b, float64 c,
int flags STATUS_PARAM)
if (!cSig) {
/* Throw out the special case of c being an exact zero now */
shift128RightJamming(pSig0, pSig1, 64, pSig0, pSig1);
+if (flags float_muladd_halve_result) {
+pExp--;
+}
return roundAndPackFloat64(zSign, pExp - 1,
pSig1 STATUS_VAR);
}
@@ -4159,6 +4191,9 @@ float64 float64_muladd(float64 a, float64 b, float64 c,
int flags STATUS_PARAM)
zExp--;
}
shift128RightJamming(zSig0, zSig1, 64, zSig0, zSig1);
+if (flags float_muladd_halve_result) {
+zExp--;
+}
return roundAndPackFloat64(zSign, zExp, zSig1 STATUS_VAR);
} else {
/* Subtraction */
@@ -4209,6 +4244,9 @@ float64 float64_muladd(float64 a, float64 b, float64 c,
int flags STATUS_PARAM)
zExp -= (shiftcount + 64);
}
}
+if (flags float_muladd_halve_result) {
+zExp--;
+}
return roundAndPackFloat64(zSign, zExp, zSig0 STATUS_VAR);
}
}
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 806ae13..4b4df88 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -249,11 +249,14 @@ void float_raise( int8 flags STATUS_PARAM);
| Using these differs from negating an input or output before calling
| the muladd function in that this means that a NaN doesn't have its
| sign bit inverted before it is propagated.
+| We also support halving the result before rounding, as a special
+| case to support the ARM fused-sqrt-step instruction FRSQRTS.
**/
enum {
float_muladd_negate_c = 1,
float_muladd_negate_product = 2,
float_muladd_negate_result = 4,
+float_muladd_halve_result = 8,
};
[Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 52894fc..ab57f55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -217,11 +217,6 @@ typedef struct CPUARMState {
uint32_t c15_power_control; /* power control */
} cp15;
-/* System registers (AArch64) */
-struct {
-uint64_t tpidr_el0;
-} sr;
-
struct {
uint32_t other_sp;
uint32_t vecbase;
--
1.8.5
[Qemu-devel] [PULL 23/30] target-arm: Fix incorrect type for value argument to write_raw_cp_reg
The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 59db883..1b111b6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -141,7 +141,7 @@ static uint64_t read_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri)
}
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
- int64_t v)
+ uint64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
* Note that constant registers are treated as write-ignored; the
--
1.8.5
[Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions
Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 115 -
1 file changed, 82 insertions(+), 33 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f1cd08a..a52a3e7 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6322,17 +6322,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
}
}
-/* C3.6.13 AdvSIMD scalar x indexed element
- * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 95 40
- * +-+---+---+--+---+---+--+-+---+---+--+--+
- * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
- * +-+---+---+--+---+---+--+-+---+---+--+--+
- */
-static void disas_simd_scalar_indexed(DisasContext *s, uint32_t insn)
-{
-unsupported_encoding(s, insn);
-}
-
/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
int immh, int immb, int opcode, int rn, int
rd)
@@ -7805,13 +7794,18 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6.18 AdvSIMD vector x indexed element
+/* C3.6.13 AdvSIMD scalar x indexed element
+ * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 95 40
+ * +-+---+---+--+---+---+--+-+---+---+--+--+
+ * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
+ * +-+---+---+--+---+---+--+-+---+---+--+--+
+ * C3.6.18 AdvSIMD vector x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 95 40
* +---+---+---+---+--+---+---+--+-+---+---+--+--+
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
* +---+---+---+---+--+---+---+--+-+---+---+--+--+
*/
-static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
+static void disas_simd_indexed(DisasContext *s, uint32_t insn)
{
/* This encoding has two kinds of instruction:
* normal, where we perform elt x idxelt = elt for each
@@ -7820,6 +7814,7 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
* double the width of the input element
* The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
*/
+bool is_scalar = extract32(insn, 28, 1);
bool is_q = extract32(insn, 30, 1);
bool u = extract32(insn, 29, 1);
int size = extract32(insn, 22, 2);
@@ -7839,7 +7834,7 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
switch (opcode) {
case 0x0: /* MLA */
case 0x4: /* MLS */
-if (!u) {
+if (!u || is_scalar) {
unallocated_encoding(s);
return;
}
@@ -7847,6 +7842,10 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
+if (is_scalar) {
+unallocated_encoding(s);
+return;
+}
is_long = true;
break;
case 0x3: /* SQDMLAL, SQDMLAL2 */
@@ -7856,12 +7855,17 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
/* fall through */
case 0xc: /* SQDMULH */
case 0xd: /* SQRDMULH */
-case 0x8: /* MUL */
if (u) {
unallocated_encoding(s);
return;
}
break;
+case 0x8: /* MUL */
+if (u || is_scalar) {
+unallocated_encoding(s);
+return;
+}
+break;
case 0x1: /* FMLA */
case 0x5: /* FMLS */
if (u) {
@@ -7923,7 +7927,7 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
read_vec_element(s, tcg_idx, rm, index, MO_64);
-for (pass = 0; pass 2; pass++) {
+for (pass = 0; pass (is_scalar ? 1 : 2); pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();
@@ -7954,15 +7958,28 @@ static void disas_simd_indexed_vector(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_res);
}
+if (is_scalar) {
+clear_vec_high(s, rd);
+}
+
tcg_temp_free_i64(tcg_idx);
} else if (!is_long) {
-/* 32 bit floating point, or 16 or 32 bit integer */
+/* 32 bit floating point, or 16 or 32 bit integer.
+ * For the 16 bit scalar case we use the usual Neon helpers and
+ * rely on the fact that 0
[Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns
Implement all the SIMD vector x indexed element instructions
in the subcategory which are not 'long' ops.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/helper-a64.c| 26 +
target-arm/helper-a64.h| 2 +
target-arm/translate-a64.c | 248 -
3 files changed, 275 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 6ca958a..fe90a5c 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -123,6 +123,32 @@ uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void
*fp_status)
return float_rel_to_flags(float64_compare(x, y, fp_status));
}
+float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+if ((float32_is_zero(a) float32_is_infinity(b)) ||
+(float32_is_infinity(a) float32_is_zero(b))) {
+/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+return make_float32((1U 30) |
+((float32_val(a) ^ float32_val(b)) (1U 31)));
+}
+return float32_mul(a, b, fpst);
+}
+
+float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+
+if ((float64_is_zero(a) float64_is_infinity(b)) ||
+(float64_is_infinity(a) float64_is_zero(b))) {
+/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+return make_float64((1ULL 62) |
+((float64_val(a) ^ float64_val(b)) (1ULL
63)));
+}
+return float64_mul(a, b, fpst);
+}
+
uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
uint32_t rn, uint32_t numregs)
{
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index 99832ee..84310e8 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -27,3 +27,5 @@ DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32)
+DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
+DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d60223a..a96ee4a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7813,7 +7813,253 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
*/
static void disas_simd_indexed_vector(DisasContext *s, uint32_t insn)
{
-unsupported_encoding(s, insn);
+/* This encoding has two kinds of instruction:
+ * normal, where we perform elt x idxelt = elt for each
+ * element in the vector
+ * long, where we perform elt x idxelt and generate a result of
+ * double the width of the input element
+ * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
+ */
+bool is_q = extract32(insn, 30, 1);
+bool u = extract32(insn, 29, 1);
+int size = extract32(insn, 22, 2);
+int l = extract32(insn, 21, 1);
+int m = extract32(insn, 20, 1);
+/* Note that the Rm field here is only 4 bits, not 5 as it usually is */
+int rm = extract32(insn, 16, 4);
+int opcode = extract32(insn, 12, 4);
+int h = extract32(insn, 11, 1);
+int rn = extract32(insn, 5, 5);
+int rd = extract32(insn, 0, 5);
+bool is_long = false;
+bool is_fp = false;
+int index;
+TCGv_ptr fpst;
+
+switch (opcode) {
+case 0x0: /* MLA */
+case 0x4: /* MLS */
+if (!u) {
+unallocated_encoding(s);
+return;
+}
+break;
+case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
+case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
+case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
+is_long = true;
+break;
+case 0x3: /* SQDMLAL, SQDMLAL2 */
+case 0x7: /* SQDMLSL, SQDMLSL2 */
+case 0xb: /* SQDMULL, SQDMULL2 */
+is_long = true;
+/* fall through */
+case 0xc: /* SQDMULH */
+case 0xd: /* SQRDMULH */
+case 0x8: /* MUL */
+if (u) {
+unallocated_encoding(s);
+return;
+}
+break;
+case 0x1: /* FMLA */
+case 0x5: /* FMLS */
+if (u) {
+unallocated_encoding(s);
+return;
+}
+/* fall through */
+case 0x9: /* FMUL, FMULX */
+if (!extract32(size, 1, 1)) {
+unallocated_encoding(s);
+return;
+}
+is_fp = true;
+break;
+default:
+unallocated_encoding(s);
+return;
+}
+
+if (is_fp) {
+/* low bit of size indicates single/double */
+size = extract32(size, 0, 1) ? 3 : 2;
+if (size == 2) {
+index = h 1 | l;
+} else {
+if (l || !is_q) {
+
[Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean up
their prototypes:
* write functions return void
* read functions return the value rather than taking a pointer
to write the value to
This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/arm/pxa2xx.c| 36 +++
hw/arm/pxa2xx_pic.c| 11 +-
target-arm/cpu.c | 6 +-
target-arm/cpu.h | 23 ++--
target-arm/helper.c| 288 -
target-arm/op_helper.c | 28 ++---
6 files changed, 154 insertions(+), 238 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 25ec549..64422f0 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -224,27 +224,24 @@ static const VMStateDescription vmstate_pxa2xx_cm = {
}
};
-static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
-*value = s-clkcfg;
-return 0;
+return s-clkcfg;
}
-static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
s-clkcfg = value 0xf;
if (value 2) {
printf(%s: CPU frequency change attempt\n, __func__);
}
-return 0;
}
-static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t value)
+static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
static const char *pwrmode[8] = {
@@ -310,36 +307,29 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const
ARMCPRegInfo *ri,
printf(%s: machine entered %s mode\n, __func__,
pwrmode[value 7]);
}
-
-return 0;
}
-static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
-*value = s-pmnc;
-return 0;
+return s-pmnc;
}
-static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
s-pmnc = value;
-return 0;
}
-static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
PXA2xxState *s = (PXA2xxState *)ri-opaque;
if (s-pmnc 1) {
-*value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
} else {
-*value = 0;
+return 0;
}
-return 0;
}
static const ARMCPRegInfo pxa_cp_reginfo[] = {
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index 46d337c..345fa4a 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -217,20 +217,17 @@ static const int pxa2xx_cp_reg_map[0x10] = {
[0xa] = ICPR2,
};
-static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
int offset = pxa2xx_cp_reg_map[ri-crn];
-*value = pxa2xx_pic_mem_read(ri-opaque, offset, 4);
-return 0;
+return pxa2xx_pic_mem_read(ri-opaque, offset, 4);
}
-static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
{
int offset = pxa2xx_cp_reg_map[ri-crn];
pxa2xx_pic_mem_write(ri-opaque, offset, value, 4);
-return 0;
}
#define REGINFO_FOR_PIC_CP(NAME, CRN) \
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8294342..6e7ce89 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -681,14 +681,12 @@ static void cortex_a9_initfn(Object *obj)
}
#ifndef CONFIG_USER_ONLY
-static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
[Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers
The ARM946 has 8 PRBS (protection region base and size) registers.
Currently we implement these with a CP_ANY reginfo; however this
underdecodes (since there are 16 possible values of CRm but only
8 registers) and we catch the invalid values in the read and
write functions. However this causes issues with migration since
we only migrate the first of a wildcard register set, so we only
migrate c6_region[0]. It also makes it awkward to pull reginfo
access checks out into their own function.
Avoid all these problems by just defining separate reginfo structs
for each of the 8 registers; this also lets us avoid having any
read or write functions and will result in more efficient direct
field accesses from generated code.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 47 ---
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 13707a3..135a357 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1162,26 +1162,6 @@ static int pmsav5_insn_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri,
return 0;
}
-static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t *value)
-{
-if (ri-crm = 8) {
-return EXCP_UDEF;
-}
-*value = env-cp15.c6_region[ri-crm];
-return 0;
-}
-
-static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
-if (ri-crm = 8) {
-return EXCP_UDEF;
-}
-env-cp15.c6_region[ri-crm] = value;
-return 0;
-}
-
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
{ .name = DATA_AP, .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
@@ -1204,9 +1184,30 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
/* Protection region base and size registers */
-{ .name = 946_PRBS, .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW,
- .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
+{ .name = 946_PRBS0, .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
+{ .name = 946_PRBS1, .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
+{ .name = 946_PRBS2, .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
+{ .name = 946_PRBS3, .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
+{ .name = 946_PRBS4, .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
+{ .name = 946_PRBS5, .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
+{ .name = 946_PRBS6, .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
+{ .name = 946_PRBS7, .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
+ .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
REGINFO_SENTINEL
};
--
1.8.5
[Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn
Convert the performance monitor reginfo definitions to use
an accessfn rather than returning EXCP_UDEF from read and
write functions. This also allows us to fix a couple of XXX
cases where we weren't imposing the access restrictions on
RAZ/WI or constant registers.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 70 +
1 file changed, 28 insertions(+), 42 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 135a357..49894a8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -485,26 +485,20 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
REGINFO_SENTINEL
};
-
-static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
+static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
-/* Generic performance monitor register read function for where
- * user access may be allowed by PMUSERENR.
+/* Perfomance monitor registers user accessibility is controlled
+ * by PMUSERENR.
*/
if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
+return CP_ACCESS_TRAP;
}
-*value = CPREG_FIELD32(env, ri);
-return 0;
+return CP_ACCESS_OK;
}
static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
-if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
-}
/* only the DP, X, D and E bits are writable */
env-cp15.c9_pmcr = ~0x39;
env-cp15.c9_pmcr |= (value 0x39);
@@ -514,9 +508,6 @@ static int pmcr_write(CPUARMState *env, const ARMCPRegInfo
*ri,
static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
-if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
-}
value = (1 31);
env-cp15.c9_pmcnten |= value;
return 0;
@@ -525,9 +516,6 @@ static int pmcntenset_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
-if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
-}
value = (1 31);
env-cp15.c9_pmcnten = ~value;
return 0;
@@ -536,9 +524,6 @@ static int pmcntenclr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
-if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
-}
env-cp15.c9_pmovsr = ~value;
return 0;
}
@@ -546,9 +531,6 @@ static int pmovsr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
-if (arm_current_pl(env) == 0 !env-cp15.c9_pmuserenr) {
-return EXCP_UDEF;
-}
env-cp15.c9_pmxevtyper = value 0xff;
return 0;
}
@@ -624,37 +606,41 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = PMCNTENSET, .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 =
1,
.access = PL0_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
- .readfn = pmreg_read, .writefn = pmcntenset_write,
- .raw_readfn = raw_read, .raw_writefn = raw_write },
+ .writefn = pmcntenset_write,
+ .accessfn = pmreg_access,
+ .raw_writefn = raw_write },
{ .name = PMCNTENCLR, .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 =
2,
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
- .readfn = pmreg_read, .writefn = pmcntenclr_write,
+ .accessfn = pmreg_access,
+ .writefn = pmcntenclr_write,
.type = ARM_CP_NO_MIGRATE },
{ .name = PMOVSR, .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
- .readfn = pmreg_read, .writefn = pmovsr_write,
- .raw_readfn = raw_read, .raw_writefn = raw_write },
-/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
- * respect PMUSERENR.
- */
+ .accessfn = pmreg_access,
+ .writefn = pmovsr_write,
+ .raw_writefn = raw_write },
+/* Unimplemented so WI. */
{ .name = PMSWINC, .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
- .access = PL0_W, .type = ARM_CP_NOP },
+ .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
- * We choose to RAZ/WI. XXX should respect PMUSERENR.
+ * We choose to RAZ/WI.
*/
{ .name = PMSELR, .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-/* Unimplemented, RAZ/WI. XXX PMUSERENR */
+ .access = PL0_RW, .type =
[Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/translate-a64.c | 7 ++-
target-arm/translate.c | 13 +
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index c96ba68..f6500e5 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1177,7 +1177,12 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
crn, crm, op0, op1, op2));
if (!ri) {
-/* Unknown register */
+/* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+qemu_log_mask(LOG_UNIMP, %s access to unsupported AArch64
+ system register op0:%d op1:%d crn:%d crm:%d op2:%d\n,
+ isread ? read : write, op0, op1, crn, crm, op2);
unallocated_encoding(s);
return;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 782aab8..6d822c6 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6962,6 +6962,19 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
return 0;
}
+/* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+if (is64) {
+qemu_log_mask(LOG_UNIMP, %s access to unsupported AArch32
+ 64 bit system register cp:%d opc1: %d crm:%d\n,
+ isread ? read : write, cpnum, opc1, crm);
+} else {
+qemu_log_mask(LOG_UNIMP, %s access to unsupported AArch32
+ system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n,
+ isread ? read : write, cpnum, opc1, crn, crm, opc2);
+}
+
return 1;
}
--
1.8.5
[Qemu-devel] [PULL 06/30] target-arm: A64: Implement SIMD FP compare and set insns
From: Alex Bennée alex.ben...@linaro.org
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers or
some new helpers for the 64bit double cases. Most of the code paths are
common although the 2misc versions are a little special as they compare
against zero.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
[PMM: fixed some minor bugs, added the 2-misc-scalar encoding]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/helper-a64.c| 19 +
target-arm/helper-a64.h| 3 +
target-arm/translate-a64.c | 197 ++---
3 files changed, 207 insertions(+), 12 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index fe90a5c..b4cab51 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -179,3 +179,22 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t
result, uint64_t indices,
}
return result;
}
+
+/* 64bit/double versions of the neon float compare functions */
+uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+return -float64_eq_quiet(a, b, fpst);
+}
+
+uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+return -float64_le(b, a, fpst);
+}
+
+uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
+{
+float_status *fpst = fpstp;
+return -float64_lt(b, a, fpst);
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index 84310e8..bf20466 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -29,3 +29,6 @@ DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32)
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
+DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
+DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
+DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 13f7f77..bcf32a1 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -77,6 +77,8 @@ typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
/* initialize TCG globals. */
void a64_translate_init(void)
@@ -6049,6 +6051,9 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
case 0x1a: /* FADD */
gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+case 0x1c: /* FCMEQ */
+gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
+break;
case 0x1e: /* FMAX */
gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
@@ -6064,6 +6069,9 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
case 0x5b: /* FMUL */
gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+case 0x5c: /* FCMGE */
+gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
+break;
case 0x5f: /* FDIV */
gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
break;
@@ -6071,6 +6079,9 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
gen_helper_vfp_absd(tcg_res, tcg_res);
break;
+case 0x7c: /* FCMGT */
+gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
+break;
default:
g_assert_not_reached();
}
@@ -6093,6 +6104,9 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
case 0x1a: /* FADD */
gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+case 0x1c: /* FCMEQ */
+gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
+break;
case 0x1e: /* FMAX */
gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
break;
@@ -6111,6 +6125,9 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
case 0x5b: /* FMUL */
gen_helper_vfp_muls(tcg_res, tcg_op1,
[Qemu-devel] [PULL 18/30] target-arm: Convert generic timer reginfo to accessfn
Convert the reginfo structs for the generic timer registers
to use access functions rather than returning EXCP_UDEF from
their read handlers. In some cases this allows us to remove
a read handler completely.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 122
1 file changed, 66 insertions(+), 56 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 49894a8..aec052b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -743,6 +743,59 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
+static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo
*ri)
+{
+/* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
+if (arm_current_pl(env) == 0 !extract32(env-cp15.c14_cntkctl, 0, 2)) {
+return CP_ACCESS_TRAP;
+}
+return CP_ACCESS_OK;
+}
+
+static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
+{
+/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
+if (arm_current_pl(env) == 0
+!extract32(env-cp15.c14_cntkctl, timeridx, 1)) {
+return CP_ACCESS_TRAP;
+}
+return CP_ACCESS_OK;
+}
+
+static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
+{
+/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
+ * EL0[PV]TEN is zero.
+ */
+if (arm_current_pl(env) == 0
+!extract32(env-cp15.c14_cntkctl, 9 - timeridx, 1)) {
+return CP_ACCESS_TRAP;
+}
+return CP_ACCESS_OK;
+}
+
+static CPAccessResult gt_pct_access(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+return gt_counter_access(env, GTIMER_PHYS);
+}
+
+static CPAccessResult gt_vct_access(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+return gt_counter_access(env, GTIMER_VIRT);
+}
+
+static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo
*ri)
+{
+return gt_timer_access(env, GTIMER_PHYS);
+}
+
+static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo
*ri)
+{
+return gt_timer_access(env, GTIMER_VIRT);
+}
+
static uint64_t gt_get_countervalue(CPUARMState *env)
{
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
@@ -788,17 +841,6 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
}
}
-static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
-{
-/* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
-if (arm_current_pl(env) == 0 !extract32(env-cp15.c14_cntkctl, 0, 2)) {
-return EXCP_UDEF;
-}
-*value = env-cp15.c14_cntfrq;
-return 0;
-}
-
static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
@@ -810,29 +852,10 @@ static void gt_cnt_reset(CPUARMState *env, const
ARMCPRegInfo *ri)
static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
{
-int timeridx = ri-opc1 1;
-
-if (arm_current_pl(env) == 0
-!extract32(env-cp15.c14_cntkctl, timeridx, 1)) {
-return EXCP_UDEF;
-}
*value = gt_get_countervalue(env);
return 0;
}
-static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-uint64_t *value)
-{
-int timeridx = ri-opc1 1;
-
-if (arm_current_pl(env) == 0
-!extract32(env-cp15.c14_cntkctl, 9 - timeridx, 1)) {
-return EXCP_UDEF;
-}
-*value = env-cp15.c14_timer[timeridx].cval;
-return 0;
-}
-
static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -847,10 +870,6 @@ static int gt_tval_read(CPUARMState *env, const
ARMCPRegInfo *ri,
{
int timeridx = ri-crm 1;
-if (arm_current_pl(env) == 0
-!extract32(env-cp15.c14_cntkctl, 9 - timeridx, 1)) {
-return EXCP_UDEF;
-}
*value = (uint32_t)(env-cp15.c14_timer[timeridx].cval -
gt_get_countervalue(env));
return 0;
@@ -867,19 +886,6 @@ static int gt_tval_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return 0;
}
-static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *value)
-{
-int timeridx = ri-crm 1;
-
-if (arm_current_pl(env) == 0
-!extract32(env-cp15.c14_cntkctl, 9 - timeridx, 1)) {
-return EXCP_UDEF;
-}
-*value = env-cp15.c14_timer[timeridx].ctl;
-return 0;
-}
-
static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -924,7 +930,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.access = PL1_RW | PL0_R,
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
.resetvalue = (1000 *
[Qemu-devel] [PULL 11/30] target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c| 2 +-
target-arm/cpu.h| 52
target-arm/helper.c | 16
3 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 45ad7f0..8294342 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -128,7 +128,7 @@ static void arm_cpu_reset(CPUState *s)
}
}
-if (env-cp15.c1_sys (1 13)) {
+if (env-cp15.c1_sys SCTLR_V) {
env-regs[15] = 0x;
}
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 383c582..52894fc 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -337,6 +337,58 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
+/* SCTLR bit meanings. Several bits have been reused in newer
+ * versions of the architecture; in that case we define constants
+ * for both old and new bit meanings. Code which tests against those
+ * bits should probably check or otherwise arrange that the CPU
+ * is the architectural version it expects.
+ */
+#define SCTLR_M (1U 0)
+#define SCTLR_A (1U 1)
+#define SCTLR_C (1U 2)
+#define SCTLR_W (1U 3) /* up to v6; RAO in v7 */
+#define SCTLR_SA (1U 3)
+#define SCTLR_P (1U 4) /* up to v5; RAO in v6 and v7 */
+#define SCTLR_SA0 (1U 4) /* v8 onward, AArch64 only */
+#define SCTLR_D (1U 5) /* up to v5; RAO in v6 */
+#define SCTLR_CP15BEN (1U 5) /* v7 onward */
+#define SCTLR_L (1U 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
+#define SCTLR_B (1U 7) /* up to v6; RAZ in v7 */
+#define SCTLR_ITD (1U 7) /* v8 onward */
+#define SCTLR_S (1U 8) /* up to v6; RAZ in v7 */
+#define SCTLR_SED (1U 8) /* v8 onward */
+#define SCTLR_R (1U 9) /* up to v6; RAZ in v7 */
+#define SCTLR_UMA (1U 9) /* v8 onward, AArch64 only */
+#define SCTLR_F (1U 10) /* up to v6 */
+#define SCTLR_SW (1U 10) /* v7 onward */
+#define SCTLR_Z (1U 11)
+#define SCTLR_I (1U 12)
+#define SCTLR_V (1U 13)
+#define SCTLR_RR (1U 14) /* up to v7 */
+#define SCTLR_DZE (1U 14) /* v8 onward, AArch64 only */
+#define SCTLR_L4 (1U 15) /* up to v6; RAZ in v7 */
+#define SCTLR_UCT (1U 15) /* v8 onward, AArch64 only */
+#define SCTLR_DT (1U 16) /* up to ??, RAO in v6 and v7 */
+#define SCTLR_nTWI(1U 16) /* v8 onward */
+#define SCTLR_HA (1U 17)
+#define SCTLR_IT (1U 18) /* up to ??, RAO in v6 and v7 */
+#define SCTLR_nTWE(1U 18) /* v8 onward */
+#define SCTLR_WXN (1U 19)
+#define SCTLR_ST (1U 20) /* up to ??, RAZ in v6 */
+#define SCTLR_UWXN(1U 20) /* v7 onward */
+#define SCTLR_FI (1U 21)
+#define SCTLR_U (1U 22)
+#define SCTLR_XP (1U 23) /* up to v6; v7 onward RAO */
+#define SCTLR_VE (1U 24) /* up to v7 */
+#define SCTLR_E0E (1U 24) /* v8 onward, AArch64 only */
+#define SCTLR_EE (1U 25)
+#define SCTLR_L2 (1U 26) /* up to v6, RAZ in v7 */
+#define SCTLR_UCI (1U 26) /* v8 onward, AArch64 only */
+#define SCTLR_NMFI(1U 27)
+#define SCTLR_TRE (1U 28)
+#define SCTLR_AFE (1U 29)
+#define SCTLR_TE (1U 30)
+
#define CPSR_M (0x1fU)
#define CPSR_T (1U 5)
#define CPSR_F (1U 6)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5ae08c9..d9e94f2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2718,7 +2718,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
/* High vectors. */
-if (env-cp15.c1_sys (1 13)) {
+if (env-cp15.c1_sys SCTLR_V) {
/* when enabled, base address cannot be remapped. */
addr += 0x;
} else {
@@ -2741,7 +2741,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
* and we should just guard the thumb mode on V4 */
if (arm_feature(env, ARM_FEATURE_V4T)) {
-env-thumb = (env-cp15.c1_sys (1 30)) != 0;
+env-thumb = (env-cp15.c1_sys SCTLR_TE) != 0;
}
env-regs[14] = env-regs[15] + offset;
env-regs[15] = addr;
@@ -2769,10 +2769,10 @@ static inline int check_ap(CPUARMState *env, int ap,
int domain_prot,
case 0:
if (access_type == 1)
return 0;
- switch ((env-cp15.c1_sys 8) 3) {
- case 1:
+ switch (env-cp15.c1_sys (SCTLR_S | SCTLR_R)) {
+ case SCTLR_S:
return is_user ? 0 : PAGE_READ;
- case 2:
+ case SCTLR_R:
return PAGE_READ;
default:
return
[Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d9e94f2..13707a3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2767,6 +2767,9 @@ static inline int check_ap(CPUARMState *env, int ap, int
domain_prot,
switch (ap) {
case 0:
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ return 0;
+ }
if (access_type == 1)
return 0;
switch (env-cp15.c1_sys (SCTLR_S | SCTLR_R)) {
--
1.8.5
[Qemu-devel] [PULL 05/30] target-arm: A64: Implement scalar three different instructions
Implement the scalar three different instruction group:
it only has three instructions in it.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Richard Henderson r...@twiddle.net
---
target-arm/translate-a64.c | 95 +-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a52a3e7..13f7f77 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5838,7 +5838,100 @@ static void disas_simd_scalar_shift_imm(DisasContext
*s, uint32_t insn)
*/
static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
{
-unsupported_encoding(s, insn);
+bool is_u = extract32(insn, 29, 1);
+int size = extract32(insn, 22, 2);
+int opcode = extract32(insn, 12, 4);
+int rm = extract32(insn, 16, 5);
+int rn = extract32(insn, 5, 5);
+int rd = extract32(insn, 0, 5);
+
+if (is_u) {
+unallocated_encoding(s);
+return;
+}
+
+switch (opcode) {
+case 0x9: /* SQDMLAL, SQDMLAL2 */
+case 0xb: /* SQDMLSL, SQDMLSL2 */
+case 0xd: /* SQDMULL, SQDMULL2 */
+if (size == 0 || size == 3) {
+unallocated_encoding(s);
+return;
+}
+break;
+default:
+unallocated_encoding(s);
+return;
+}
+
+if (size == 2) {
+TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+TCGv_i64 tcg_res = tcg_temp_new_i64();
+
+read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
+read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
+
+tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
+gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
+
+switch (opcode) {
+case 0xd: /* SQDMULL, SQDMULL2 */
+break;
+case 0xb: /* SQDMLSL, SQDMLSL2 */
+tcg_gen_neg_i64(tcg_res, tcg_res);
+/* fall through */
+case 0x9: /* SQDMLAL, SQDMLAL2 */
+read_vec_element(s, tcg_op1, rd, 0, MO_64);
+gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
+ tcg_res, tcg_op1);
+break;
+default:
+g_assert_not_reached();
+}
+
+write_fp_dreg(s, rd, tcg_res);
+
+tcg_temp_free_i64(tcg_op1);
+tcg_temp_free_i64(tcg_op2);
+tcg_temp_free_i64(tcg_res);
+} else {
+TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+TCGv_i64 tcg_res = tcg_temp_new_i64();
+
+read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
+read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
+
+gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
+gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
+
+switch (opcode) {
+case 0xd: /* SQDMULL, SQDMULL2 */
+break;
+case 0xb: /* SQDMLSL, SQDMLSL2 */
+gen_helper_neon_negl_u32(tcg_res, tcg_res);
+/* fall through */
+case 0x9: /* SQDMLAL, SQDMLAL2 */
+{
+TCGv_i64 tcg_op3 = tcg_temp_new_i64();
+read_vec_element(s, tcg_op3, rd, 0, MO_32);
+gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
+ tcg_res, tcg_op3);
+tcg_temp_free_i64(tcg_op3);
+break;
+}
+default:
+g_assert_not_reached();
+}
+
+tcg_gen_ext32u_i64(tcg_res, tcg_res);
+write_fp_dreg(s, rd, tcg_res);
+
+tcg_temp_free_i32(tcg_op1);
+tcg_temp_free_i32(tcg_op2);
+tcg_temp_free_i64(tcg_res);
+}
}
static void handle_3same_64(DisasContext *s, int opcode, bool u,
--
1.8.5
[Qemu-devel] [Aarch64] Bug in add/sub extended reg
Hello,
there's a bug in SP handling in disas_add_sub_ext_reg:
/* non-flag setting ops may use SP */
if (!setflags) {
tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rd = cpu_reg_sp(s, rd);
} else {
tcg_rn = read_cpu_reg(s, rn, sf);
tcg_rd = cpu_reg(s, rd);
}
rn can always be SP no matter whether flags are set or not.
Thanks,
Laurent
Re: [Qemu-devel] [PATCH 0/3] net: drop implicit peer from offload API
Hello, It looks ok to me. Cheers Vincenzo 2014-02-20 12:14 GMT+01:00 Stefan Hajnoczi stefa...@redhat.com: This series is based on my net tree, which already has Vincenzo's Add netmap backend offloadings support patch series merged. After merging the series I realized we were bypassing the net.h API and directly accessing nc-info-... in some cases. This series cleans that up, at the cost of moving -peer back up to offload API callers. I think that's the right thing to do to make net.h APIs consistent (the other functions don't have implicit -peer) and avoid bypassing the API. Stefan Hajnoczi (3): net: remove implicit peer from offload API vhost_net: use offload API instead of bypassing it virtio-net: use qemu_get_queue() where possible hw/net/vhost_net.c | 6 +++--- hw/net/virtio-net.c | 12 ++-- hw/net/vmxnet3.c| 18 +- include/net/net.h | 14 +++--- net/net.c | 36 ++-- 5 files changed, 43 insertions(+), 43 deletions(-) -- 1.8.5.3 -- Vincenzo Maffione
Re: [Qemu-devel] [PATCH v14 06/14] block: Add backing_blocker in BlockDriverState
On Thu, Feb 20, 2014 at 04:28:56PM +0800, Fam Zheng wrote:
On Thu, 02/20 00:08, Jeff Cody wrote:
On Thu, Feb 20, 2014 at 01:01:38PM +0800, Fam Zheng wrote:
On Wed, 02/19 16:17, Jeff Cody wrote:
On Wed, Feb 19, 2014 at 09:42:23PM +0800, Fam Zheng wrote:
This makes use of op_blocker and blocks all the operations except for
commit target, on each BlockDriverState-backing_hd.
The asserts for op_blocker in bdrv_swap are removed because with this
change, the target of block commit has at least the backing blocker of
its child, so the assertion is not true. Callers should do their
check.
Signed-off-by: Fam Zheng f...@redhat.com
---
block.c | 19 +++
include/block/block_int.h | 3 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/block.c b/block.c
index dec44d4..95d8c1f 100644
--- a/block.c
+++ b/block.c
@@ -1044,19 +1044,33 @@ fail:
void bdrv_set_backing_hd(BlockDriverState *bs, BlockDriverState
*backing_hd)
{
if (bs-backing_hd) {
+assert(error_is_set(bs-backing_blocker));
When I run block-commit, on either the active or non-active layer, I
get an assertion here. The qemu-iotests do not catch it, and I
presume it is because happens a couple of seconds or so after the
success message is returned over QMP.
I can't reproduce this, could you give some specific steps? Thanks.
Sure - I am guessing the key is performing some live block snapshots
first. Here is what I did (this is from memory, but I think the steps
are right):
Nothing special really about the cmdline:
qemu-system-x86_64 -drive file=/home/jtc/test.qcow2,if=virtio -qmp stdio ...
The QMP commands:
For the non-active layer case:
{ execute: qmp_capabilities }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap1.qcow2,format: qcow2 } }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap2.qcow2,format: qcow2 } }
{ execute: block-commit, arguments: { device: virtio0, top:
/tmp/snap1.qcow2 } }
For the active layer case (I think I still had 2 snapshots here, not
entirely positive):
{ execute: qmp_capabilities }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap1.qcow2,format: qcow2 } }
{ execute: blockdev-snapshot-sync, arguments: { device:
virtio0,snapshot-file:/tmp/snap2.qcow2,format: qcow2 } }
{ execute: block-commit, arguments: { device: virtio0, top:
/tmp/snap2.qcow2 } }
{ execute: block-job-complete, arguments: { device: virtio0 }}
Yes. I forgot to use bdrv_set_backing_hd in bdrv_append.
Could you try if the below patch fixes it? Thanks.
Yep, this seems to fix it.
Fam
---
diff --git a/block.c b/block.c
index 1af43b9..66a8e35 100644
--- a/block.c
+++ b/block.c
@@ -1978,7 +1978,7 @@ void bdrv_append(BlockDriverState *bs_new,
BlockDriverState *bs_top)
/* The contents of 'tmp' will become bs_top, as we are
* swapping bs_new and bs_top contents. */
-bs_top-backing_hd = bs_new;
+bdrv_set_backing_hd(bs_top, bs_new);
bs_top-open_flags = ~BDRV_O_NO_BACKING;
pstrcpy(bs_top-backing_file, sizeof(bs_top-backing_file),
bs_new-filename);
Re: [Qemu-devel] [PULL 00/12] Build system changes for 2014-02-17
On 17 February 2014 17:35, Paolo Bonzini pbonz...@redhat.com wrote: Anthony, Peter, The following changes since commit 89e4a51ca9546a7bbe1998c4e3d4a3ac3a0c19be: Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging (2014-01-31 11:13:08 +) are available in the git repository at: git://github.com/bonzini/qemu.git configure for you to fetch changes up to 2001070d5d4b14a2350a14a772aaf26d08ce8d90: build: softmmu targets do not have a main.o file This has merge conflicts in rules.mak -- Paolo has kindly agreed to do a respin for me. thanks -- PMM
Re: [Qemu-devel] [PATCH v4 6/8] qdev: introduce FWPathProvider interface
Am 11.12.2013 11:22, schrieb Alexey Kardashevskiy:
QEMU supports firmware names for all devices in the QEMU tree but
some architectures expect some parts of firmware path names in different
format.
This introduces a firmware-pathname-change interface definition.
If some machines needs to redefine the firmware path format, it has
to add the TYPE_FW_PATH_PROVIDER interface to an object that is above
the device on the QOM tree (typically /machine).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Changes:
v4:
* added fw-path-provider.o into tests/Makefile
* fixed 80chars warning from checkpatch.pl
I am puzzled that the patch ends in Paolo's Sob but was sent by Alexey.
Was this picked up from another series or is it even in multiple
concurrent series? Were changes performed since Paolo signed it off? If
not, please provide a Patchwork link to the original for convenience. :)
---
hw/core/Makefile.objs | 1 +
hw/core/fw-path-provider.c| 36
hw/core/qdev.c| 18 +-
include/hw/fw-path-provider.h | 32
tests/Makefile| 1 +
5 files changed, 87 insertions(+), 1 deletion(-)
create mode 100644 hw/core/fw-path-provider.c
create mode 100644 include/hw/fw-path-provider.h
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 950146c..d829479 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -1,5 +1,6 @@
# core qdev-related obj files, also used by *-user:
common-obj-y += qdev.o qdev-properties.o
+common-obj-y += fw-path-provider.o
# irq.o needed for qdev GPIO handling:
common-obj-y += irq.o
diff --git a/hw/core/fw-path-provider.c b/hw/core/fw-path-provider.c
new file mode 100644
index 000..0187568
--- /dev/null
+++ b/hw/core/fw-path-provider.c
@@ -0,0 +1,36 @@
+#include hw/fw-path-provider.h
This new file is lacking a license header. Same for the header file below.
+
+char *fw_path_provider_get_dev_path(FWPathProvider *p, BusState *bus,
+DeviceState *dev)
+{
+FWPathProviderClass *k = FW_PATH_PROVIDER_GET_CLASS(p);
+
+return k-get_dev_path(p, bus, dev);
+}
+
+char *fw_path_provider_try_get_dev_path(Object *o, BusState *bus,
+DeviceState *dev)
+{
+FWPathProvider *p = (FWPathProvider *)
+object_dynamic_cast(o, TYPE_FW_PATH_PROVIDER);
+
+if (p) {
+return fw_path_provider_get_dev_path(p, bus, dev);
+}
+
+return NULL;
+}
+
+static const TypeInfo fw_path_provider_info = {
+.name = TYPE_FW_PATH_PROVIDER,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(FWPathProviderClass),
Indentation looks inconsistent.
+};
+
Double white line seems unintentional.
+
+static void fw_path_provider_register_types(void)
+{
+type_register_static(fw_path_provider_info);
+}
+
+type_init(fw_path_provider_register_types)
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 959130c..81a0e75 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -26,6 +26,7 @@
this API directly. */
#include hw/qdev.h
+#include hw/fw-path-provider.h
#include sysemu/sysemu.h
#include qapi/error.h
#include qapi/qmp/qerror.h
@@ -503,6 +504,18 @@ static char *bus_get_fw_dev_path(BusState *bus,
DeviceState *dev)
return NULL;
}
+static char *qdev_get_fw_dev_path_from_handler(BusState *bus, DeviceState
*dev)
+{
+Object *obj = OBJECT(dev);
+char *d = NULL;
+
+while (!d obj-parent) {
+obj = obj-parent;
+d = fw_path_provider_try_get_dev_path(obj, bus, dev);
+}
+return d;
+}
+
static int qdev_get_fw_dev_path_helper(DeviceState *dev, char *p, int size)
{
int l = 0;
@@ -510,7 +523,10 @@ static int qdev_get_fw_dev_path_helper(DeviceState *dev,
char *p, int size)
if (dev dev-parent_bus) {
char *d;
l = qdev_get_fw_dev_path_helper(dev-parent_bus-parent, p, size);
-d = bus_get_fw_dev_path(dev-parent_bus, dev);
+d = qdev_get_fw_dev_path_from_handler(dev-parent_bus, dev);
+if (!d) {
+d = bus_get_fw_dev_path(dev-parent_bus, dev);
+}
if (d) {
l += snprintf(p + l, size - l, %s, d);
g_free(d);
diff --git a/include/hw/fw-path-provider.h b/include/hw/fw-path-provider.h
new file mode 100644
index 000..765170b
--- /dev/null
+++ b/include/hw/fw-path-provider.h
@@ -0,0 +1,32 @@
+#ifndef FW_PATH_PROVIDER_H
+#define FW_PATH_PROVIDER_H 1
+
+#include qemu-common.h
+#include qom/object.h
+
+#define TYPE_FW_PATH_PROVIDER fw-path-provider
+
+#define FW_PATH_PROVIDER_CLASS(klass) \
+ OBJECT_CLASS_CHECK(FWPathProviderClass, (klass), TYPE_FW_PATH_PROVIDER)
+#define FW_PATH_PROVIDER_GET_CLASS(obj) \
+
Re: [Qemu-devel] [PATCH V7 02/11] qapi script: add check for duplicated key
Wenchao Xia xiaw...@linux.vnet.ibm.com writes: It is bad that same key was specified twice, especially when a union have two branches with same condition. This patch can prevent it. Signed-off-by: Wenchao Xia xiaw...@linux.vnet.ibm.com --- scripts/qapi.py |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/scripts/qapi.py b/scripts/qapi.py index bd81f06..3732fe1 100644 --- a/scripts/qapi.py +++ b/scripts/qapi.py @@ -116,6 +116,8 @@ class QAPISchema: if self.tok != ':': raise QAPISchemaError(self, 'Expected :') self.accept() +if key in expr: +raise QAPISchemaError(self, 'Duplicate key %s' % key) expr[key] = self.get_expr(True) if self.tok == '}': self.accept() The test for this error is in 11/11. If you need to respin anyway, consider adding error tests in the same patch as the error they test.
Re: [Qemu-devel] [PATCH V7 01/11] qapi script: remember enum values
Wenchao Xia xiaw...@linux.vnet.ibm.com writes:
Later other scripts will need to check the enum values.
Signed-off-by: Wenchao Xia xiaw...@linux.vnet.ibm.com
Reviewed-by: Eric Blake ebl...@redhat.com
---
scripts/qapi.py| 18 ++
tests/qapi-schema/comments.out |2 +-
tests/qapi-schema/qapi-schema-test.out | 10 +-
3 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/scripts/qapi.py b/scripts/qapi.py
index f3c2a20..bd81f06 100644
--- a/scripts/qapi.py
+++ b/scripts/qapi.py
@@ -169,7 +169,7 @@ def parse_schema(fp):
for expr in schema.exprs:
if expr.has_key('enum'):
-add_enum(expr['enum'])
+add_enum(expr['enum'], expr['data'])
This is an explicitly defined enum.
elif expr.has_key('union'):
add_union(expr)
add_enum('%sKind' % expr['union'])
elif expr.has_key('type'):
add_struct(expr)
exprs.append(expr)
# Try again for hidden UnionKind enum
for expr_elem in schema.exprs:
expr = expr_elem['expr']
if expr.has_key('union'):
try:
enum_define = discriminator_find_enum_define(expr_elem)
except QAPIExprError, e:
print sys.stderr, e
exit(1)
if not enum_define:
add_enum('%sKind' % expr['union'])
This is an implicitly defined enum.
@@ -289,13 +289,23 @@ def find_union(name):
return union
return None
-def add_enum(name):
+def add_enum(name, enum_values = None):
global enum_types
-enum_types.append(name)
+enum_types.append({enum_name: name, enum_values: enum_values})
You remember enum values only for the explicitly defined enums. Let's
see how that works out later in this series. In any case, mentioning it
in the commit message wouldn't hurt :)
+
+def find_enum(name):
+global enum_types
+for enum in enum_types:
+if enum['enum_name'] == name:
+return enum
+return None
def is_enum(name):
global enum_types
-return (name in enum_types)
+for enum in enum_types:
+if enum['enum_name'] == name:
+return True
+return False
Duplicates find_enum()'s loop. Consider simplifying to
def is_enum(name):
return find_enum(name) != None
def c_type(name):
if name == 'str':
diff --git a/tests/qapi-schema/comments.out b/tests/qapi-schema/comments.out
index e3bd904..4ce3dcf 100644
--- a/tests/qapi-schema/comments.out
+++ b/tests/qapi-schema/comments.out
@@ -1,3 +1,3 @@
[OrderedDict([('enum', 'Status'), ('data', ['good', 'bad', 'ugly'])])]
-['Status']
+[{'enum_name': 'Status', 'enum_values': ['good', 'bad', 'ugly']}]
[]
diff --git a/tests/qapi-schema/qapi-schema-test.out
b/tests/qapi-schema/qapi-schema-test.out
index 89b53d4..01685d4 100644
--- a/tests/qapi-schema/qapi-schema-test.out
+++ b/tests/qapi-schema/qapi-schema-test.out
@@ -15,11 +15,11 @@
OrderedDict([('command', 'user_def_cmd2'), ('data', OrderedDict([('ud1a',
'UserDefOne'), ('*ud1b', 'UserDefOne')])), ('returns', 'UserDefTwo')]),
OrderedDict([('command', 'user_def_cmd3'), ('data', OrderedDict([('a',
'int'), ('*b', 'int')])), ('returns', 'int')]),
OrderedDict([('type', 'UserDefOptions'), ('data', OrderedDict([('*i64',
['int']), ('*u64', ['uint64']), ('*u16', ['uint16']), ('*i64x', 'int'),
('*u64x', 'uint64')]))])]
-['EnumOne',
- 'UserDefUnionKind',
- 'UserDefFlatUnionKind',
- 'UserDefAnonUnionKind',
- 'UserDefNativeListUnionKind']
+[{'enum_name': 'EnumOne', 'enum_values': ['value1', 'value2', 'value3']},
Explicitly defined enum with values.
+ {'enum_name': 'UserDefUnionKind', 'enum_values': None},
+ {'enum_name': 'UserDefFlatUnionKind', 'enum_values': None},
+ {'enum_name': 'UserDefAnonUnionKind', 'enum_values': None},
+ {'enum_name': 'UserDefNativeListUnionKind', 'enum_values': None}]
Four implicitly defined enums without values.
[OrderedDict([('type', 'NestedEnumsOne'), ('data', OrderedDict([('enum1',
'EnumOne'), ('*enum2', 'EnumOne'), ('enum3', 'EnumOne'), ('*enum4',
'EnumOne')]))]),
OrderedDict([('type', 'UserDefZero'), ('data', OrderedDict([('integer',
'int')]))]),
OrderedDict([('type', 'UserDefOne'), ('base', 'UserDefZero'), ('data',
OrderedDict([('string', 'str'), ('*enum1', 'EnumOne')]))]),
[Qemu-devel] [PULL 21/30] target-arm: Remove unnecessary code now read/write fns can't fail
Now that cpreg read and write functions can't fail and throw an
exception, we can remove the code from the translator that synchronises
the guest PC in case an exception is thrown.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/translate-a64.c | 2 --
target-arm/translate.c | 4
2 files changed, 6 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e70d14f..ef305e3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1231,7 +1231,6 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
tcg_gen_movi_i64(tcg_rt, ri-resetvalue);
} else if (ri-readfn) {
TCGv_ptr tmpptr;
-gen_a64_set_pc_im(s-pc - 4);
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
tcg_temp_free_ptr(tmpptr);
@@ -1244,7 +1243,6 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
return;
} else if (ri-writefn) {
TCGv_ptr tmpptr;
-gen_a64_set_pc_im(s-pc - 4);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
tcg_temp_free_ptr(tmpptr);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0805053..6ccf0ba 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6876,7 +6876,6 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp64 = tcg_const_i64(ri-resetvalue);
} else if (ri-readfn) {
TCGv_ptr tmpptr;
-gen_set_pc_im(s, s-pc);
tmp64 = tcg_temp_new_i64();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
@@ -6899,7 +6898,6 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp = tcg_const_i32(ri-resetvalue);
} else if (ri-readfn) {
TCGv_ptr tmpptr;
-gen_set_pc_im(s, s-pc);
tmp = tcg_temp_new_i32();
tmpptr = tcg_const_ptr(ri);
gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
@@ -6934,7 +6932,6 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmphi);
if (ri-writefn) {
TCGv_ptr tmpptr = tcg_const_ptr(ri);
-gen_set_pc_im(s, s-pc);
gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
tcg_temp_free_ptr(tmpptr);
} else {
@@ -6945,7 +6942,6 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
if (ri-writefn) {
TCGv_i32 tmp;
TCGv_ptr tmpptr;
-gen_set_pc_im(s, s-pc);
tmp = load_reg(s, rt);
tmpptr = tcg_const_ptr(ri);
gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
--
1.8.5
Re: [Qemu-devel] [PATCH V7 03/11] qapi-script: remember line number in schema parsing
Wenchao Xia xiaw...@linux.vnet.ibm.com writes: Before this patch, 'QAPISchemaError' scans whole input until 'pos' to get error line number. After this patch, the scan is avoided since line number is remembered in schema parsing. This patch also benefits other error report functions, which would be introduced later. Not sure avoiding the scan is worthwhile, but since you coded it already... no objections. Signed-off-by: Wenchao Xia xiaw...@linux.vnet.ibm.com --- scripts/qapi.py | 14 -- 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/scripts/qapi.py b/scripts/qapi.py index 3732fe1..c504eb4 100644 --- a/scripts/qapi.py +++ b/scripts/qapi.py @@ -39,12 +39,10 @@ class QAPISchemaError(Exception): def __init__(self, schema, msg): self.fp = schema.fp self.msg = msg -self.line = self.col = 1 -for ch in schema.src[0:schema.pos]: -if ch == '\n': -self.line += 1 -self.col = 1 -elif ch == '\t': +self.col = 1 +self.line = schema.line +for ch in schema.src[schema.line_pos:schema.pos]: +if ch == '\t': self.col = (self.col + 7) % 8 + 1 Column computation is wrong. Should be something like self.col = ((self.col + 7) ~7) + 1 Not your fault, of course, and you don't have to fix it to get my R-by. If you want to fix it, separate patch, and please include suitable tests. else: self.col += 1 @@ -60,6 +58,8 @@ class QAPISchema: if self.src == '' or self.src[-1] != '\n': self.src += '\n' self.cursor = 0 +self.line = 1 +self.line_pos = 0 self.exprs = [] self.accept() @@ -100,6 +100,8 @@ class QAPISchema: if self.cursor == len(self.src): self.tok = None return +self.line += 1 +self.line_pos = self.cursor elif not self.tok.isspace(): raise QAPISchemaError(self, 'Stray %s' % self.tok)
Re: [Qemu-devel] [PATCHv3 1/2] sun4m: Add Sun CG3 framebuffer and corresponding OpenBIOS FCode ROM
On Wed, Feb 19, 2014 at 09:39:09PM +, Mark Cave-Ayland wrote:
On 19/02/14 13:35, Leandro Dorileo wrote:
Hi Leandro,
+static void cg3_realizefn(DeviceState *dev, Error **errp)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+CG3State *s = CG3(dev);
+int ret;
+char *fcode_filename;
+
+/* FCode ROM */
+memory_region_init_ram(s-rom, NULL, cg3.prom, FCODE_MAX_ROM_SIZE);
+vmstate_register_ram_global(s-rom);
+memory_region_set_readonly(s-rom, true);
+sysbus_init_mmio(sbd,s-rom);
+
I think this initialization code could be done in a SysBusDeviceClass init
operation,
don't you think?
I think it's possible since these MemoryRegions don't depend upon
properties, but I leave that to Andres who seems reasonably happy with the
patchset in its current form.
Yes, I just saw his comment in the patch 02...
+fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
+if (fcode_filename) {
+ret = load_image_targphys(fcode_filename, s-prom_addr,
+ FCODE_MAX_ROM_SIZE);
+if (ret 0 || ret FCODE_MAX_ROM_SIZE) {
+error_report(cg3: could not load prom '%s', CG3_ROM_FILE);
What happens if we fail to load the rom file? is the framebuffer supposed to
work?
I guess the framebuffer would still work although nothing would be able to
find its address because the node wouldn't exist in the device tree?
Ok, when we move this code to an instance init op we handle it a bit better.
ATB,
Mark.
--
Leandro Dorileo
Re: [Qemu-devel] [Aarch64] Bug in add/sub extended reg
On 20 February 2014 11:51, Laurent Desnogues
laurent.desnog...@gmail.com wrote:
Hello,
there's a bug in SP handling in disas_add_sub_ext_reg:
/* non-flag setting ops may use SP */
if (!setflags) {
tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rd = cpu_reg_sp(s, rd);
} else {
tcg_rn = read_cpu_reg(s, rn, sf);
tcg_rd = cpu_reg(s, rd);
}
rn can always be SP no matter whether flags are set or not.
Yep, pseudocode agrees:
bits(datasize) operand1 = if n == 31 then SP[] else X[n];
It's only Rd that has this 31 means SP only if
we're not setting flags behaviour.
thanks
-- PMM
[Qemu-devel] [PULL respin 00/12] Build system changes for 2014-02-20
Anthony, Peter, The following changes since commit 89e4a51ca9546a7bbe1998c4e3d4a3ac3a0c19be: Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging (2014-01-31 11:13:08 +) are available in the git repository at: git://github.com/bonzini/qemu.git configure for you to fetch changes up to f966f9ddd175bdf82f12650c3b7b5a93cc421d88: build: softmmu targets do not have a main.o file (2014-02-20 13:14:18 +0100) No changes except context, but close enough to modified lines that git flags a conflict. Paolo Don Slutz (1): configure: Disable libtool if -fPIE does not work with it (bug #1257099) Fam Zheng (9): util: Split out exec_dir from os_find_datadir rules.mak: fix $(obj) to a real relative path rules.mak: allow per object cflags and libs block: use per-object cflags and libs rules.mak: introduce DSO rules module: implement module loading Makefile: install modules with make install Makefile: introduce common-obj-m and block-obj-m for DSO block: convert block drivers linked with libs to modules Paolo Bonzini (2): darwin: do not use -mdynamic-no-pic build: softmmu targets do not have a main.o file .gitignore| 3 + Makefile | 29 +- Makefile.objs | 19 +- Makefile.target | 23 ++-- block/Makefile.objs | 13 - configure | 156 -- include/qemu-common.h | 2 +- include/qemu/module.h | 23 +++- include/qemu/osdep.h | 9 +++ module-common.c | 10 os-posix.c| 42 +++--- os-win32.c| 21 +-- qemu-img.c| 1 + qemu-io.c | 1 + qemu-nbd.c| 1 + rules.mak | 80 +- scripts/create_config | 3 + util/module.c | 145 +- util/oslib-posix.c| 54 + util/oslib-win32.c| 30 ++ vl.c | 3 +- 21 files changed, 541 insertions(+), 127 deletions(-) create mode 100644 module-common.c -- 1.8.3.1
[Qemu-devel] [PULL 02/12] rules.mak: fix $(obj) to a real relative path
From: Fam Zheng f...@redhat.com Makefile.target includes rule.mak and unnested common-obj-y, then prefix them with '../', this will ignore object specific QEMU_CFLAGS in subdir Makefile.objs: $(obj)/curl.o: QEMU_CFLAGS += $(CURL_CFLAGS) Because $(obj) here is './block', instead of '../block'. This doesn't hurt compiling because we basically build all .o from top Makefile, before entering Makefile.target, but it will affact arriving per-object libs support. The starting point of $(obj) is passed in as argument of unnest-vars, as well as nested variables, so that different Makefiles can pass in a right value. Signed-off-by: Fam Zheng f...@redhat.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- Makefile| 14 ++ Makefile.objs | 17 + Makefile.target | 17 + configure | 1 + rules.mak | 14 +- 5 files changed, 38 insertions(+), 25 deletions(-) diff --git a/Makefile b/Makefile index 807054b..52b1958 100644 --- a/Makefile +++ b/Makefile @@ -122,6 +122,16 @@ defconfig: ifneq ($(wildcard config-host.mak),) include $(SRC_PATH)/Makefile.objs +endif + +dummy := $(call unnest-vars,, \ +stub-obj-y \ +util-obj-y \ +qga-obj-y \ +block-obj-y \ +common-obj-y) + +ifneq ($(wildcard config-host.mak),) include $(SRC_PATH)/tests/Makefile endif ifeq ($(CONFIG_SMARTCARD_NSS),y) @@ -130,6 +140,10 @@ endif all: $(DOCS) $(TOOLS) $(HELPERS-y) recurse-all +vl.o: QEMU_CFLAGS+=$(GPROF_CFLAGS) + +vl.o: QEMU_CFLAGS+=$(SDL_CFLAGS) + config-host.h: config-host.h-timestamp config-host.h-timestamp: config-host.mak qemu-options.def: $(SRC_PATH)/qemu-options.hx diff --git a/Makefile.objs b/Makefile.objs index ac1d0e1..1914080 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -41,7 +41,7 @@ libcacard-y += libcacard/vcardt.o # single QEMU executable should support all CPUs and machines. ifeq ($(CONFIG_SOFTMMU),y) -common-obj-y = $(block-obj-y) blockdev.o blockdev-nbd.o block/ +common-obj-y = blockdev.o blockdev-nbd.o block/ common-obj-y += net/ common-obj-y += qdev-monitor.o device-hotplug.o common-obj-$(CONFIG_WIN32) += os-win32.o @@ -111,18 +111,3 @@ version-lobj-$(CONFIG_WIN32) += $(BUILD_DIR)/version.lo # by libqemuutil.a. These should be moved to a separate .json schema. qga-obj-y = qga/ qapi-types.o qapi-visit.o qga-vss-dll-obj-y = qga/ - -vl.o: QEMU_CFLAGS+=$(GPROF_CFLAGS) - -vl.o: QEMU_CFLAGS+=$(SDL_CFLAGS) - -QEMU_CFLAGS+=$(GLIB_CFLAGS) - -nested-vars += \ - stub-obj-y \ - util-obj-y \ - qga-obj-y \ - qga-vss-dll-obj-y \ - block-obj-y \ - common-obj-y -dummy := $(call unnest-vars) diff --git a/Makefile.target b/Makefile.target index af6ac7e..9a6e7dd 100644 --- a/Makefile.target +++ b/Makefile.target @@ -139,13 +139,22 @@ endif # CONFIG_SOFTMMU # Workaround for http://gcc.gnu.org/PR55489, see configure. %/translate.o: QEMU_CFLAGS += $(TRANSLATE_OPT_CFLAGS) -nested-vars += obj-y +dummy := $(call unnest-vars,,obj-y) -# This resolves all nested paths, so it must come last +# we are making another call to unnest-vars with different vars, protect obj-y, +# it can be overriden in subdir Makefile.objs +obj-y-save := $(obj-y) + +block-obj-y := +common-obj-y := include $(SRC_PATH)/Makefile.objs +dummy := $(call unnest-vars,..,block-obj-y common-obj-y) + +# Now restore obj-y +obj-y := $(obj-y-save) -all-obj-y = $(obj-y) -all-obj-y += $(addprefix ../, $(common-obj-y)) +all-obj-y = $(obj-y) $(common-obj-y) +all-obj-$(CONFIG_SOFTMMU) += $(block-obj-y) ifndef CONFIG_HAIKU LIBS+=-lm diff --git a/configure b/configure index 4648117..66b1d30 100755 --- a/configure +++ b/configure @@ -2360,6 +2360,7 @@ fi if $pkg_config --atleast-version=$glib_req_ver gthread-2.0; then glib_cflags=`$pkg_config --cflags gthread-2.0` glib_libs=`$pkg_config --libs gthread-2.0` +CFLAGS=$glib_cflags $CFLAGS LIBS=$glib_libs $LIBS libs_qga=$glib_libs $libs_qga else diff --git a/rules.mak b/rules.mak index 391d6eb..a95fb76 100644 --- a/rules.mak +++ b/rules.mak @@ -146,9 +146,6 @@ clean: clean-timestamp # magic to descend into other directories -obj := . -old-nested-dirs := - define push-var $(eval save-$2-$1 = $(value $1)) $(eval $1 :=) @@ -162,9 +159,11 @@ endef define unnest-dir $(foreach var,$(nested-vars),$(call push-var,$(var),$1/)) -$(eval obj := $(obj)/$1) +$(eval obj-parent-$1 := $(obj)) +$(eval obj := $(if $(obj),$(obj)/$1,$1)) $(eval include $(SRC_PATH)/$1/Makefile.objs) -$(eval obj := $(patsubst %/$1,%,$(obj))) +$(eval obj := $(obj-parent-$1)) +$(eval obj-parent-$1 := ) $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/)) endef @@ -179,7 +178,12 @@ $(if $(nested-dirs), endef define unnest-vars +$(eval obj := $1) +$(eval nested-vars := $2) +$(eval old-nested-dirs := ) $(call unnest-vars-1) +$(if $1,$(foreach v,$(nested-vars),$(eval \ + $v := $(addprefix
[Qemu-devel] [PULL 01/12] util: Split out exec_dir from os_find_datadir
From: Fam Zheng f...@redhat.com
With this change, main() calls qemu_init_exec_dir and uses argv[0] to
init exec_dir. The saved value can be retrieved with
qemu_get_exec_dir later. It will be reused by module loading.
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
include/qemu-common.h | 2 +-
include/qemu/osdep.h | 9 +
os-posix.c| 42 +++
os-win32.c| 21 ++--
qemu-img.c| 1 +
qemu-io.c | 1 +
qemu-nbd.c| 1 +
util/oslib-posix.c| 54 +++
util/oslib-win32.c| 30
vl.c | 3 ++-
10 files changed, 108 insertions(+), 56 deletions(-)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 5054836..17c2959 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -360,7 +360,7 @@ char *qemu_find_file(int type, const char *name);
/* OS specific functions */
void os_setup_early_signal_handling(void);
-char *os_find_datadir(const char *argv0);
+char *os_find_datadir(void);
void os_parse_cmd_args(int index, const char *optarg);
void os_pidfile_error(void);
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index eac7172..ffb2966 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -215,6 +215,15 @@ bool fips_get_state(void);
*/
char *qemu_get_local_state_pathname(const char *relative_pathname);
+/* Find program directory, and save it for later usage with
+ * qemu_get_exec_dir().
+ * Try OS specific API first, if not working, parse from argv0. */
+void qemu_init_exec_dir(const char *argv0);
+
+/* Get the saved exec dir.
+ * Caller needs to release the returned string by g_free() */
+char *qemu_get_exec_dir(void);
+
/**
* qemu_getauxval:
* @type: the auxiliary vector key to lookup
diff --git a/os-posix.c b/os-posix.c
index d39261d..6187301 100644
--- a/os-posix.c
+++ b/os-posix.c
@@ -84,46 +84,17 @@ void os_setup_signal_handling(void)
running from the build tree this will be $bindir/../pc-bios. */
#define SHARE_SUFFIX /share/qemu
#define BUILD_SUFFIX /pc-bios
-char *os_find_datadir(const char *argv0)
+char *os_find_datadir(void)
{
-char *dir;
-char *p = NULL;
+char *dir, *exec_dir;
char *res;
-char buf[PATH_MAX];
size_t max_len;
-#if defined(__linux__)
-{
-int len;
-len = readlink(/proc/self/exe, buf, sizeof(buf) - 1);
-if (len 0) {
-buf[len] = 0;
-p = buf;
-}
-}
-#elif defined(__FreeBSD__)
-{
-static int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1};
-size_t len = sizeof(buf) - 1;
-
-*buf = '\0';
-if (!sysctl(mib, ARRAY_SIZE(mib), buf, len, NULL, 0)
-*buf) {
-buf[sizeof(buf) - 1] = '\0';
-p = buf;
-}
-}
-#endif
-/* If we don't have any way of figuring out the actual executable
- location then try argv[0]. */
-if (!p) {
-p = realpath(argv0, buf);
-if (!p) {
-return NULL;
-}
+exec_dir = qemu_get_exec_dir();
+if (exec_dir == NULL) {
+return NULL;
}
-dir = dirname(p);
-dir = dirname(dir);
+dir = dirname(exec_dir);
max_len = strlen(dir) +
MAX(strlen(SHARE_SUFFIX), strlen(BUILD_SUFFIX)) + 1;
@@ -137,6 +108,7 @@ char *os_find_datadir(const char *argv0)
}
}
+g_free(exec_dir);
return res;
}
#undef SHARE_SUFFIX
diff --git a/os-win32.c b/os-win32.c
index 50b7f6f..5f95caa 100644
--- a/os-win32.c
+++ b/os-win32.c
@@ -84,26 +84,9 @@ void os_setup_early_signal_handling(void)
}
/* Look for support files in the same directory as the executable. */
-char *os_find_datadir(const char *argv0)
+char *os_find_datadir(void)
{
-char *p;
-char buf[MAX_PATH];
-DWORD len;
-
-len = GetModuleFileName(NULL, buf, sizeof(buf) - 1);
-if (len == 0) {
-return NULL;
-}
-
-buf[len] = 0;
-p = buf + len - 1;
-while (p != buf *p != '\\')
-p--;
-*p = 0;
-if (access(buf, R_OK) == 0) {
-return g_strdup(buf);
-}
-return NULL;
+return qemu_get_exec_dir();
}
void os_set_line_buffering(void)
diff --git a/qemu-img.c b/qemu-img.c
index c989850..45fcddd 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -2719,6 +2719,7 @@ int main(int argc, char **argv)
#endif
error_set_progname(argv[0]);
+qemu_init_exec_dir(argv[0]);
qemu_init_main_loop();
bdrv_init();
diff --git a/qemu-io.c b/qemu-io.c
index 7f459d8..b74ac45 100644
--- a/qemu-io.c
+++ b/qemu-io.c
@@ -381,6 +381,7 @@ int main(int argc, char **argv)
#endif
progname = basename(argv[0]);
+qemu_init_exec_dir(argv[0]);
while ((c = getopt_long(argc, argv, sopt, lopt, opt_index)) != -1) {
switch (c) {
diff --git a/qemu-nbd.c b/qemu-nbd.c
index
[Qemu-devel] [PULL 04/12] block: use per-object cflags and libs
From: Fam Zheng f...@redhat.com
No longer adds flags and libs for them to global variables, instead
create config-host.mak variables like FOO_CFLAGS and FOO_LIBS, which is
used as per object cflags and libs.
This removes unwanted dependencies from libcacard.
Signed-off-by: Fam Zheng f...@redhat.com
[Split from Fam's patch to enable modules. - Paolo]
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
block/Makefile.objs | 13 -
configure | 25 ++---
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/block/Makefile.objs b/block/Makefile.objs
index e254a21..673aa7c 100644
--- a/block/Makefile.objs
+++ b/block/Makefile.objs
@@ -24,4 +24,15 @@ common-obj-y += commit.o
common-obj-y += mirror.o
common-obj-y += backup.o
-$(obj)/curl.o: QEMU_CFLAGS+=$(CURL_CFLAGS)
+iscsi.o-cflags := $(LIBISCSI_CFLAGS)
+iscsi.o-libs := $(LIBISCSI_LIBS)
+curl.o-cflags := $(CURL_CFLAGS)
+curl.o-libs:= $(CURL_LIBS)
+rbd.o-cflags := $(RBD_CFLAGS)
+rbd.o-libs := $(RBD_LIBS)
+gluster.o-cflags := $(GLUSTERFS_CFLAGS)
+gluster.o-libs := $(GLUSTERFS_LIBS)
+ssh.o-cflags := $(LIBSSH2_CFLAGS)
+ssh.o-libs := $(LIBSSH2_LIBS)
+qcow.o-libs:= -lz
+linux-aio.o-libs := -laio
diff --git a/configure b/configure
index 66b1d30..1201cc3 100755
--- a/configure
+++ b/configure
@@ -2318,8 +2318,6 @@ EOF
curl_libs=`$curlconfig --libs 2/dev/null`
if compile_prog $curl_cflags $curl_libs ; then
curl=yes
-libs_tools=$curl_libs $libs_tools
-libs_softmmu=$curl_libs $libs_softmmu
else
if test $curl = yes ; then
feature_not_found curl Install libcurl devel
@@ -2475,8 +2473,6 @@ EOF
rbd_libs=-lrbd -lrados
if compile_prog $rbd_libs ; then
rbd=yes
-libs_tools=$rbd_libs $libs_tools
-libs_softmmu=$rbd_libs $libs_softmmu
else
if test $rbd = yes ; then
feature_not_found rados block device Install librbd/ceph devel
@@ -2493,9 +2489,6 @@ if test $libssh2 != no ; then
libssh2_cflags=`$pkg_config libssh2 --cflags`
libssh2_libs=`$pkg_config libssh2 --libs`
libssh2=yes
-libs_tools=$libssh2_libs $libs_tools
-libs_softmmu=$libssh2_libs $libs_softmmu
-QEMU_CFLAGS=$QEMU_CFLAGS $libssh2_cflags
else
if test $libssh2 = yes ; then
error_exit libssh2 = $min_libssh2_version required for
--enable-libssh2
@@ -2541,8 +2534,6 @@ int main(void) { io_setup(0, NULL); io_set_eventfd(NULL,
0); eventfd(0, 0); retu
EOF
if compile_prog -laio ; then
linux_aio=yes
-libs_softmmu=$libs_softmmu -laio
-libs_tools=$libs_tools -laio
else
if test $linux_aio = yes ; then
feature_not_found linux AIO Install libaio devel
@@ -2711,9 +2702,6 @@ if test $glusterfs != no ; then
glusterfs=yes
glusterfs_cflags=`$pkg_config --cflags glusterfs-api`
glusterfs_libs=`$pkg_config --libs glusterfs-api`
-CFLAGS=$CFLAGS $glusterfs_cflags
-libs_tools=$glusterfs_libs $libs_tools
-libs_softmmu=$glusterfs_libs $libs_softmmu
if $pkg_config --atleast-version=5 glusterfs-api; then
glusterfs_discard=yes
fi
@@ -3084,11 +3072,9 @@ EOF
libiscsi=yes
libiscsi_cflags=$($pkg_config --cflags libiscsi)
libiscsi_libs=$($pkg_config --libs libiscsi)
-CFLAGS=$CFLAGS $libiscsi_cflags
-LIBS=$LIBS $libiscsi_libs
elif compile_prog -liscsi ; then
libiscsi=yes
-LIBS=$LIBS -liscsi
+libiscsi_libs=-liscsi
else
if test $libiscsi = yes ; then
feature_not_found libiscsi Install libiscsi devel
@@ -4101,6 +4087,7 @@ fi
if test $curl = yes ; then
echo CONFIG_CURL=y $config_host_mak
echo CURL_CFLAGS=$curl_cflags $config_host_mak
+ echo CURL_LIBS=$curl_libs $config_host_mak
fi
if test $brlapi = yes ; then
echo CONFIG_BRLAPI=y $config_host_mak
@@ -4193,6 +4180,8 @@ if test $libiscsi = yes ; then
if test $libiscsi_version = 1.4.0; then
echo CONFIG_LIBISCSI_1_4=y $config_host_mak
fi
+ echo LIBISCSI_CFLAGS=$libiscsi_cflags $config_host_mak
+ echo LIBISCSI_LIBS=$libiscsi_libs $config_host_mak
fi
if test $libnfs = yes ; then
@@ -4218,6 +4207,8 @@ if test $qom_cast_debug = yes ; then
fi
if test $rbd = yes ; then
echo CONFIG_RBD=y $config_host_mak
+ echo RBD_CFLAGS=$rbd_cflags $config_host_mak
+ echo RBD_LIBS=$rbd_libs $config_host_mak
fi
echo CONFIG_COROUTINE_BACKEND=$coroutine $config_host_mak
@@ -4261,6 +4252,8 @@ fi
if test $glusterfs = yes ; then
echo CONFIG_GLUSTERFS=y $config_host_mak
+ echo GLUSTERFS_CFLAGS=$glusterfs_cflags $config_host_mak
+ echo GLUSTERFS_LIBS=$glusterfs_libs $config_host_mak
fi
if test $glusterfs_discard = yes ; then
@@ -4273,6 +4266,8 @@ fi
if test $libssh2 = yes ; then
echo CONFIG_LIBSSH2=y $config_host_mak
+ echo LIBSSH2_CFLAGS=$libssh2_cflags $config_host_mak
+ echo LIBSSH2_LIBS=$libssh2_libs
[Qemu-devel] [PULL 05/12] darwin: do not use -mdynamic-no-pic
While -mdynamic-no-pic can speed up the code somewhat, it is only used on the legacy PowerPC Mac OS X, and I am not sure if anyone is still testing that. Disabling PIC can cause problems when enabling modules, so do not do that. Signed-off-by: Paolo Bonzini pbonz...@redhat.com Signed-off-by: Fam Zheng f...@redhat.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- configure | 2 -- 1 file changed, 2 deletions(-) diff --git a/configure b/configure index 1201cc3..c69d4d9 100755 --- a/configure +++ b/configure @@ -518,8 +518,6 @@ Darwin) if [ $cpu = x86_64 ] ; then QEMU_CFLAGS=-arch x86_64 $QEMU_CFLAGS LDFLAGS=-arch x86_64 $LDFLAGS - else -QEMU_CFLAGS=-mdynamic-no-pic $QEMU_CFLAGS fi cocoa=yes audio_drv_list=coreaudio -- 1.8.3.1
[Qemu-devel] [PULL 08/12] Makefile: install modules with make install
From: Fam Zheng f...@redhat.com
Install all the modules to ${MODDIR}.
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Makefile | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Makefile b/Makefile
index 07d1ed7..57d83a3 100644
--- a/Makefile
+++ b/Makefile
@@ -368,6 +368,12 @@ install-datadir install-localstatedir
ifneq ($(TOOLS),)
$(INSTALL_PROG) $(STRIP_OPT) $(TOOLS) $(DESTDIR)$(bindir)
endif
+ifneq ($(CONFIG_MODULES),)
+ $(INSTALL_DIR) $(DESTDIR)$(qemu_moddir)
+ for s in $(patsubst %.mo,%$(DSOSUF),$(modules-m)); do \
+ $(INSTALL_PROG) $(STRIP_OPT) $$s
$(DESTDIR)$(qemu_moddir)/$${s//\//-}; \
+ done
+endif
ifneq ($(HELPERS-y),)
$(INSTALL_DIR) $(DESTDIR)$(libexecdir)
$(INSTALL_PROG) $(STRIP_OPT) $(HELPERS-y) $(DESTDIR)$(libexecdir)
--
1.8.3.1
[Qemu-devel] [PULL 06/12] rules.mak: introduce DSO rules
From: Fam Zheng f...@redhat.com
Add necessary rules and flags for shared object generation.
The new rules introduced here are:
1) %.o in $(common-obj-m) is compiled to %.o, then linked to %.so.
2) %.mo in $(common-obj-m) is the placeholder for %.so for pattern
matching in Makefile. It's linked to -shared with all its dependencies
(multiple *.o) as input. Which means the list of depended objects must
be specified in each sub-Makefile.objs:
foo.mo-objs := bar.o baz.o qux.o
in the same style with foo.o-cflags and foo.o-libs. The objects here
will be prefixed with $(obj)/ if it's a subdirectory Makefile.objs.
3) For all files ending up in %.so, the following is added automatically:
foo.o-cflags += -fPIC -DBUILD_DSO
Also introduce --enable-modules in configure, the option will enable
support of shared object build. Otherwise objects are static linked to
executables.
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
.gitignore | 3 +++
Makefile | 4 +++-
configure | 15 +++
rules.mak | 52 +++-
4 files changed, 64 insertions(+), 10 deletions(-)
diff --git a/.gitignore b/.gitignore
index 6e48b5e..6e74d63 100644
--- a/.gitignore
+++ b/.gitignore
@@ -64,6 +64,9 @@ libuser
*.cp
*.dvi
*.exe
+*.dll
+*.so
+*.mo
*.fn
*.ky
*.log
diff --git a/Makefile b/Makefile
index 52b1958..9d53117 100644
--- a/Makefile
+++ b/Makefile
@@ -138,7 +138,7 @@ ifeq ($(CONFIG_SMARTCARD_NSS),y)
include $(SRC_PATH)/libcacard/Makefile
endif
-all: $(DOCS) $(TOOLS) $(HELPERS-y) recurse-all
+all: $(DOCS) $(TOOLS) $(HELPERS-y) recurse-all modules
vl.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)
@@ -256,6 +256,8 @@ clean:
rm -f qemu-options.def
find . -name '*.[oda]' -type f -exec rm -f {} +
find . -name '*.l[oa]' -type f -exec rm -f {} +
+ find . -name '*$(DSOSUF)' -type f -exec rm -f {} +
+ find . -name '*.mo' -type f -exec rm -f {} +
rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) qemu-ga TAGS cscope.*
*.pod *~ */*~
rm -f fsdev/*.pod
rm -rf .libs */.libs
diff --git a/configure b/configure
index c69d4d9..e3bc04e 100755
--- a/configure
+++ b/configure
@@ -205,6 +205,9 @@ mingw32=no
gcov=no
gcov_tool=gcov
EXESUF=
+DSOSUF=.so
+LDFLAGS_SHARED=-shared
+modules=no
prefix=/usr/local
mandir=\${prefix}/share/man
datadir=\${prefix}/share
@@ -515,6 +518,7 @@ OpenBSD)
Darwin)
bsd=yes
darwin=yes
+ LDFLAGS_SHARED=-bundle -undefined dynamic_lookup
if [ $cpu = x86_64 ] ; then
QEMU_CFLAGS=-arch x86_64 $QEMU_CFLAGS
LDFLAGS=-arch x86_64 $LDFLAGS
@@ -608,6 +612,7 @@ fi
if test $mingw32 = yes ; then
EXESUF=.exe
+ DSOSUF=.dll
QEMU_CFLAGS=-DWIN32_LEAN_AND_MEAN -DWINVER=0x501 $QEMU_CFLAGS
# enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later)
QEMU_CFLAGS=-D__USE_MINGW_ANSI_STDIO=1 $QEMU_CFLAGS
@@ -674,6 +679,9 @@ for opt do
;;
--disable-debug-info)
;;
+ --enable-modules)
+ modules=yes
+ ;;
--cpu=*)
;;
--target-list=*) target_list=$optarg
@@ -1130,6 +1138,7 @@ Advanced options (experts only):
--sysconfdir=PATHinstall config in PATH$confsuffix
--localstatedir=PATH install local state in PATH (set at runtime on
win32)
--with-confsuffix=SUFFIX suffix for QEMU data inside datadir and sysconfdir
[$confsuffix]
+ --enable-modules enable modules support
--enable-debug-tcg enable TCG debugging
--disable-debug-tcg disable TCG debugging (default)
--enable-debug-info enable debugging information (default)
@@ -3768,6 +3777,7 @@ echo python$python
if test $slirp = yes ; then
echo smbd $smbd
fi
+echo module support$modules
echo host CPU $cpu
echo host big endian $bigendian
echo target list $target_list
@@ -4012,6 +4022,9 @@ echo TARGET_DIRS=$target_list $config_host_mak
if [ $docs = yes ] ; then
echo BUILD_DOCS=yes $config_host_mak
fi
+if test $modules = yes; then
+ echo CONFIG_MODULES=y $config_host_mak
+fi
if test $sdl = yes ; then
echo CONFIG_SDL=y $config_host_mak
echo SDL_CFLAGS=$sdl_cflags $config_host_mak
@@ -4396,6 +4409,8 @@ echo LIBTOOLFLAGS=$LIBTOOLFLAGS $config_host_mak
echo LIBS+=$LIBS $config_host_mak
echo LIBS_TOOLS+=$libs_tools $config_host_mak
echo EXESUF=$EXESUF $config_host_mak
+echo DSOSUF=$DSOSUF $config_host_mak
+echo LDFLAGS_SHARED=$LDFLAGS_SHARED $config_host_mak
echo LIBS_QGA+=$libs_qga $config_host_mak
echo POD2MAN=$POD2MAN $config_host_mak
echo TRANSLATE_OPT_CFLAGS=$TRANSLATE_OPT_CFLAGS $config_host_mak
diff --git a/rules.mak b/rules.mak
index 0db7031..0abf3d1 100644
--- a/rules.mak
+++ b/rules.mak
@@ -22,7 +22,12 @@ QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(*D)/$(*F).d
# Same as -I$(SRC_PATH) -I., but for the nested source/object directories
QEMU_INCLUDES += -I$(D) -I$(@D)
-extract-libs = $(strip $(foreach o,$1,$($o-libs)))
+maybe-add =
[Qemu-devel] [PULL 07/12] module: implement module loading
From: Fam Zheng f...@redhat.com
This patch adds loading, stamp checking and initialization of modules.
The init function of dynamic module is no longer directly called as
__attribute__((constructor)) in static linked version, it is called
only after passed the checking of presense of stamp symbol:
qemu_stamp_$RELEASEHASH
where $RELEASEHASH is generated by hashing version strings and content
of configure script.
With this, modules built from a different tree/version/configure will
not be loaded.
The module loading code requires gmodule-2.0.
Modules are searched under
- CONFIG_MODDIR
- executable folder (to allow running qemu-{img,io} in the build
directory)
- ../ of executable folder (to allow running system emulator in the
build directory)
Modules are linked under their subdir respectively, then copied to top
level of build directory for above convinience, e.g.:
$(BUILD_DIR)/block/curl.so - $(BUILD_DIR)/block-curl.so
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
Makefile | 3 ++
configure | 42 +++
include/qemu/module.h | 23 +++-
module-common.c | 10
rules.mak | 3 ++
scripts/create_config | 3 ++
util/module.c | 145 +-
7 files changed, 217 insertions(+), 12 deletions(-)
create mode 100644 module-common.c
diff --git a/Makefile b/Makefile
index 9d53117..07d1ed7 100644
--- a/Makefile
+++ b/Makefile
@@ -201,6 +201,9 @@ Makefile: $(version-obj-y) $(version-lobj-y)
libqemustub.a: $(stub-obj-y)
libqemuutil.a: $(util-obj-y) qapi-types.o qapi-visit.o
+block-modules = $(foreach o,$(block-obj-m),$(basename $(subst /,-,$o)),) NULL
+util/module.o-cflags = -D'CONFIG_BLOCK_MODULES=$(block-modules)'
+
##
qemu-img.o: qemu-img-cmds.h
diff --git a/configure b/configure
index e3bc04e..136a8f0 100755
--- a/configure
+++ b/configure
@@ -1137,7 +1137,7 @@ Advanced options (experts only):
--libdir=PATHinstall libraries in PATH
--sysconfdir=PATHinstall config in PATH$confsuffix
--localstatedir=PATH install local state in PATH (set at runtime on
win32)
- --with-confsuffix=SUFFIX suffix for QEMU data inside datadir and sysconfdir
[$confsuffix]
+ --with-confsuffix=SUFFIX suffix for QEMU data inside
datadir/libdir/sysconfdir [$confsuffix]
--enable-modules enable modules support
--enable-debug-tcg enable TCG debugging
--disable-debug-tcg disable TCG debugging (default)
@@ -2362,14 +2362,32 @@ if test $mingw32 = yes; then
else
glib_req_ver=2.12
fi
-if $pkg_config --atleast-version=$glib_req_ver gthread-2.0; then
-glib_cflags=`$pkg_config --cflags gthread-2.0`
-glib_libs=`$pkg_config --libs gthread-2.0`
-CFLAGS=$glib_cflags $CFLAGS
-LIBS=$glib_libs $LIBS
-libs_qga=$glib_libs $libs_qga
-else
-error_exit glib-$glib_req_ver required to compile QEMU
+
+for i in gthread-2.0 gmodule-2.0; do
+if $pkg_config --atleast-version=$glib_req_ver $i; then
+glib_cflags=`$pkg_config --cflags $i`
+glib_libs=`$pkg_config --libs $i`
+CFLAGS=$glib_cflags $CFLAGS
+LIBS=$glib_libs $LIBS
+libs_qga=$glib_libs $libs_qga
+else
+error_exit glib-$glib_req_ver $i is required to compile QEMU
+fi
+done
+
+##
+# SHA command probe for modules
+if test $modules = yes; then
+shacmd_probe=sha1sum sha1 shasum
+for c in $shacmd_probe; do
+if which $c /dev/null; then
+shacmd=$c
+break
+fi
+done
+if test $shacmd = ; then
+error_exit one of the checksum commands is required to enable
modules: $shacmd_probe
+fi
fi
##
@@ -3661,6 +3679,7 @@ if test $mingw32 = yes ; then
fi
qemu_confdir=$sysconfdir$confsuffix
+qemu_moddir=$libdir$confsuffix
qemu_datadir=$datadir$confsuffix
qemu_localedir=$datadir/locale
@@ -3751,6 +3770,7 @@ echo Install prefix$prefix
echo BIOS directory`eval echo $qemu_datadir`
echo binary directory `eval echo $bindir`
echo library directory `eval echo $libdir`
+echo module directory `eval echo $qemu_moddir`
echo libexec directory `eval echo $libexecdir`
echo include directory `eval echo $includedir`
echo config directory `eval echo $sysconfdir`
@@ -3890,6 +3910,7 @@ echo sysconfdir=$sysconfdir $config_host_mak
echo qemu_confdir=$qemu_confdir $config_host_mak
echo qemu_datadir=$qemu_datadir $config_host_mak
echo qemu_docdir=$qemu_docdir $config_host_mak
+echo qemu_moddir=$qemu_moddir $config_host_mak
if test $mingw32 = no ; then
echo qemu_localstatedir=$local_statedir $config_host_mak
fi
@@ -4023,6 +4044,9 @@ if [ $docs = yes ] ; then
echo BUILD_DOCS=yes $config_host_mak
fi
if test
[Qemu-devel] [PULL 10/12] block: convert block drivers linked with libs to modules
From: Fam Zheng f...@redhat.com The converted block drivers are: curl iscsi rbd ssh glusterfs Signed-off-by: Fam Zheng f...@redhat.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- configure | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/configure b/configure index 136a8f0..66d7633 100755 --- a/configure +++ b/configure @@ -4120,7 +4120,7 @@ if test $bswap_h = yes ; then echo CONFIG_MACHINE_BSWAP_H=y $config_host_mak fi if test $curl = yes ; then - echo CONFIG_CURL=y $config_host_mak + echo CONFIG_CURL=m $config_host_mak echo CURL_CFLAGS=$curl_cflags $config_host_mak echo CURL_LIBS=$curl_libs $config_host_mak fi @@ -4211,7 +4211,7 @@ if test $glx = yes ; then fi if test $libiscsi = yes ; then - echo CONFIG_LIBISCSI=y $config_host_mak + echo CONFIG_LIBISCSI=m $config_host_mak if test $libiscsi_version = 1.4.0; then echo CONFIG_LIBISCSI_1_4=y $config_host_mak fi @@ -4241,7 +4241,7 @@ if test $qom_cast_debug = yes ; then echo CONFIG_QOM_CAST_DEBUG=y $config_host_mak fi if test $rbd = yes ; then - echo CONFIG_RBD=y $config_host_mak + echo CONFIG_RBD=m $config_host_mak echo RBD_CFLAGS=$rbd_cflags $config_host_mak echo RBD_LIBS=$rbd_libs $config_host_mak fi @@ -4286,7 +4286,7 @@ if test $getauxval = yes ; then fi if test $glusterfs = yes ; then - echo CONFIG_GLUSTERFS=y $config_host_mak + echo CONFIG_GLUSTERFS=m $config_host_mak echo GLUSTERFS_CFLAGS=$glusterfs_cflags $config_host_mak echo GLUSTERFS_LIBS=$glusterfs_libs $config_host_mak fi @@ -4300,7 +4300,7 @@ if test $glusterfs_zerofill = yes ; then fi if test $libssh2 = yes ; then - echo CONFIG_LIBSSH2=y $config_host_mak + echo CONFIG_LIBSSH2=m $config_host_mak echo LIBSSH2_CFLAGS=$libssh2_cflags $config_host_mak echo LIBSSH2_LIBS=$libssh2_libs $config_host_mak fi -- 1.8.3.1
[Qemu-devel] [PULL 11/12] configure: Disable libtool if -fPIE does not work with it (bug #1257099)
From: Don Slutz dsl...@verizon.com
Adjust TMPO and added TMPB, TMPL, and TMPA. libtool needs the names
to be fixed (TMPB).
Add new functions do_libtool and libtool_prog.
Add check for broken gcc and libtool.
Signed-off-by: Don Slutz dsl...@verizon.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
configure | 63 ++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 66d7633..46b5b6d 100755
--- a/configure
+++ b/configure
@@ -12,7 +12,10 @@ else
fi
TMPC=${TMPDIR1}/qemu-conf-${RANDOM}-$$-${RANDOM}.c
-TMPO=${TMPDIR1}/qemu-conf-${RANDOM}-$$-${RANDOM}.o
+TMPB=qemu-conf-${RANDOM}-$$-${RANDOM}
+TMPO=${TMPDIR1}/${TMPB}.o
+TMPL=${TMPDIR1}/${TMPB}.lo
+TMPA=${TMPDIR1}/lib${TMPB}.la
TMPE=${TMPDIR1}/qemu-conf-${RANDOM}-$$-${RANDOM}.exe
# NB: do not call exit in the trap handler; this is buggy with some shells;
@@ -86,6 +89,38 @@ compile_prog() {
do_cc $QEMU_CFLAGS $local_cflags -o $TMPE $TMPC $LDFLAGS $local_ldflags
}
+do_libtool() {
+local mode=$1
+shift
+# Run the compiler, capturing its output to the log.
+echo $libtool $mode --tag=CC $cc $@ config.log
+$libtool $mode --tag=CC $cc $@ config.log 21 || return $?
+# Test passed. If this is an --enable-werror build, rerun
+# the test with -Werror and bail out if it fails. This
+# makes warning-generating-errors in configure test code
+# obvious to developers.
+if test $werror != yes; then
+return 0
+fi
+# Don't bother rerunning the compile if we were already using -Werror
+case $* in
+*-Werror*)
+ return 0
+;;
+esac
+echo $libtool $mode --tag=CC $cc -Werror $@ config.log
+$libtool $mode --tag=CC $cc -Werror $@ config.log 21 return $?
+error_exit configure test passed without -Werror but failed with
-Werror. \
+This is probably a bug in the configure script. The failing command \
+will be at the bottom of config.log. \
+You can run configure with --disable-werror to bypass this check.
+}
+
+libtool_prog() {
+do_libtool --mode=compile $QEMU_CFLAGS -c -fPIE -DPIE -o $TMPO $TMPC ||
return $?
+do_libtool --mode=link $LDFLAGS -o $TMPA $TMPL -rpath /usr/local/lib
+}
+
# symbolically link $1 to $2. Portable version of ln -sf.
symlink() {
rm -rf $2
@@ -1406,6 +1441,32 @@ EOF
fi
fi
+# check for broken gcc and libtool in RHEL5
+if test -n $libtool -a $pie != no ; then
+ cat $TMPC EOF
+
+void *f(unsigned char *buf, int len);
+void *g(unsigned char *buf, int len);
+
+void *
+f(unsigned char *buf, int len)
+{
+return (void*)0L;
+}
+
+void *
+g(unsigned char *buf, int len)
+{
+return f(buf, len);
+}
+
+EOF
+ if ! libtool_prog; then
+echo Disabling libtool due to broken toolchain support
+libtool=
+ fi
+fi
+
##
# __sync_fetch_and_and requires at least -march=i486. Many toolchains
# use i686 as default anyway, but for those that don't, an explicit
--
1.8.3.1
[Qemu-devel] [PULL 09/12] Makefile: introduce common-obj-m and block-obj-m for DSO
From: Fam Zheng f...@redhat.com $(common-obj-m) will include $(block-obj-m), like $(common-obj-y) does for $(block-obj-y). Signed-off-by: Fam Zheng f...@redhat.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- Makefile| 4 +++- Makefile.objs | 2 ++ Makefile.target | 6 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 57d83a3..992cd23 100644 --- a/Makefile +++ b/Makefile @@ -129,7 +129,9 @@ dummy := $(call unnest-vars,, \ util-obj-y \ qga-obj-y \ block-obj-y \ -common-obj-y) +block-obj-m \ +common-obj-y \ +common-obj-m) ifneq ($(wildcard config-host.mak),) include $(SRC_PATH)/tests/Makefile diff --git a/Makefile.objs b/Makefile.objs index 1914080..4a62913 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -19,6 +19,8 @@ block-obj-y += qemu-coroutine.o qemu-coroutine-lock.o qemu-coroutine-io.o block-obj-y += qemu-coroutine-sleep.o block-obj-y += coroutine-$(CONFIG_COROUTINE_BACKEND).o +block-obj-m = block/ + ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy) # Lots of the fsdev/9pcode is pulled in by vl.c via qemu_fsdev_add. # only pull in the actual virtio-9p device if we also enabled virtio. diff --git a/Makefile.target b/Makefile.target index 9a6e7dd..3945260 100644 --- a/Makefile.target +++ b/Makefile.target @@ -148,7 +148,11 @@ obj-y-save := $(obj-y) block-obj-y := common-obj-y := include $(SRC_PATH)/Makefile.objs -dummy := $(call unnest-vars,..,block-obj-y common-obj-y) +dummy := $(call unnest-vars,.., \ + block-obj-y \ + block-obj-m \ + common-obj-y \ + common-obj-m) # Now restore obj-y obj-y := $(obj-y-save) -- 1.8.3.1
Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07
On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote: I am now running a full libguestfs test which will take several hours, but it looks as if -- even if this test fails -- it won't be because of lack of emulation / missing instructions in qemu. The tests ran. I hit two bugs, but neither seems to be related to qemu emulation. Please push these patches into upstream qemu :-) One bug is in btrfs and is related to page size being different (and much larger) on ppc64. The second bug is kind of interesting. If you add ~ 256 disks (using virtio-scsi), then it looks as if the firmware crashes. The total console output is below. It looks as if c is some kind of prompt. qemu spins using 100% of CPU after this. -- Populating /vdevice methods Populating /vdevice/vty@3000 Populating /vdevice/nvram@7100 C0580\b\b\b\b\bC05A0\b\b\b\b\bPopulating /pci@8002000 ^M Adapters on 08002000 00 (D) : 106b 003fserial bus [ usb-ohci ] 00 0800 (D) : 1af4 1004virtio [ scsi ] Populating /pci@8002000/scsi@1 SCSI: Looking for devices 100 DISK : QEMU QEMU HARDDISK1.7. 101 DISK : QEMU QEMU HARDDISK1.7. 102 DISK : QEMU QEMU HARDDISK1.7. 103 DISK : QEMU QEMU HARDDISK1.7. 104 DISK : QEMU QEMU HARDDISK1.7. 105 DISK : QEMU QEMU HARDDISK1.7. 106 DISK : QEMU QEMU HARDDISK1.7. 107 DISK : QEMU QEMU HARDDISK1.7. 108 DISK : QEMU QEMU HARDDISK1.7. C0600\b\b\b\b\bC0640\b\b\b\b\bC0690\b\b\b\b\bC06A0\b\b\b\b\bC06A8\b\b\b\b\bC06B0\b\b\b\b\bC06B8\b\b\b\b\bC06C0\b\b\b\b\b ( 700 ) Program Exception [ 2e51cb00 ] R0 .. R7 R8 .. R15 R16 .. R23 R24 .. R31 2dca41ec 2dcfe058 0006 2e5198e0 2e5a91c0 2dcb3900 2dcbcb00 2dcb7b38 2dca0d10 2e51a050 2e51cb00 2dd121f0 2dcbabd8 2dcb5e48 2dcfe050 03d0 0056 0003 2e51cb00 2dcf2e4e 0007 2e5b0751 2e516010 0003 2dca0c30 2e50fae0 CR / XER LR / CTR SRR0 / SRR1DAR / DSISR 8488 2dca1d40 2dcb7b38 2dcb7b38 8008 c \x1b7 -- Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones Read my programming blog: http://rwmj.wordpress.com Fedora now supports 80 OCaml packages (the OPEN alternative to F#)
Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07
On 20.02.2014, at 13:34, Richard W.M. Jones rjo...@redhat.com wrote: On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote: I am now running a full libguestfs test which will take several hours, but it looks as if -- even if this test fails -- it won't be because of lack of emulation / missing instructions in qemu. The tests ran. I hit two bugs, but neither seems to be related to qemu emulation. Please push these patches into upstream qemu :-) They will get into 2.0, no worries :). One bug is in btrfs and is related to page size being different (and much larger) on ppc64. I remember bugs (oopses) with btrfs when you use a 4k page size created fs and use it on a 64k page size kernel and vice versa. They still haven't fixed that? The second bug is kind of interesting. If you add ~ 256 disks (using virtio-scsi), then it looks as if the firmware crashes. The total console output is below. It looks as if c is some kind of prompt. qemu spins using 100% of CPU after this. How much RAM do you pass into the guest? Could you please try to increase that size to see whether it makes a difference? If it doesn't, Aneesh is your man :) Alex
Re: [Qemu-devel] [RFC v2 1/6] rfifolock: add recursive FIFO lock
On Mon, Jan 20, 2014 at 06:22:28PM +0800, Fam Zheng wrote: On Fri, 01/10 09:45, Stefan Hajnoczi wrote: QemuMutex does not guarantee fairness and cannot be acquired recursively: Fairness means each locker gets a turn and the scheduler cannot cause starvation. Recursive locking is useful for composition, it allows a sequence of locking operations to be invoked atomically by acquiring the lock around them. This patch adds RFifoLock, a recursive lock that guarantees FIFO order. Its first user is added in the next patch. RFifoLock has one additional feature: it can be initialized with an optional contention callback. The callback is invoked whenever a thread must wait for the lock. For example, it can be used to poke the current owner so that they release the lock soon. Is it better to make the contention callback per-caller than per-lock? Considering that different caller may want to do different things depending on current code path. Perhaps it will make sense to change it in the future. For now it means callers use the standard lock/unlock function. They don't have to know what actions are needed to poke the current lock-holder.
Re: [Qemu-devel] [RFC v2 2/6] aio: add aio_context_acquire() and aio_context_release()
On Mon, Jan 20, 2014 at 06:29:50PM +0800, Fam Zheng wrote: On Fri, 01/10 09:45, Stefan Hajnoczi wrote: +/* Take ownership of the AioContext. If the AioContext will be shared between + * threads, a thread must have ownership when calling aio_poll(). + * + * Note that multiple threads calling aio_poll() means timers, BHs, and + * callbacks may be invoked from a different thread than they were registered + * from. Therefore, code must use AioContext acquire/release or use + * fine-grained synchronization to protect shared state if other threads will + * be accessing it simultaneously. + */ +void aio_context_acquire(AioContext *ctx); + +/* Reliquinish ownership of the AioContext. */ s/Reliquinish/Relinquish/ Fixed in next version.
Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07
On Thu, Feb 20, 2014 at 01:36:57PM +0100, Alexander Graf wrote: On 20.02.2014, at 13:34, Richard W.M. Jones rjo...@redhat.com wrote: On Thu, Feb 20, 2014 at 10:23:42AM +, Richard W.M. Jones wrote: I am now running a full libguestfs test which will take several hours, but it looks as if -- even if this test fails -- it won't be because of lack of emulation / missing instructions in qemu. The tests ran. I hit two bugs, but neither seems to be related to qemu emulation. Please push these patches into upstream qemu :-) They will get into 2.0, no worries :). One bug is in btrfs and is related to page size being different (and much larger) on ppc64. I remember bugs (oopses) with btrfs when you use a 4k page size created fs and use it on a 64k page size kernel and vice versa. They still haven't fixed that? The failure from the log is: wipefs -a --force /dev/sda1 mkfs.btrfs --alloc-start 0 --byte-count 268435456 --data single --leafsize 4096 --label test --metadata single --nodesize 4096 --sectorsize 512 /dev/sda1 Illegal leafsize (or nodesize) 4096 (smaller than 65536) I have not analysed this beyond simply looking at the command line now, but it seems that this is NOT a bug in btrfs, but a bug in the test suite, selecting a too small --leafsize parameter. Or perhaps a limitation in btrfs. Anyway, doesn't look serious. The second bug is kind of interesting. If you add ~ 256 disks (using virtio-scsi), then it looks as if the firmware crashes. The total console output is below. It looks as if c is some kind of prompt. qemu spins using 100% of CPU after this. How much RAM do you pass into the guest? Could you please try to increase that size to see whether it makes a difference? If it doesn't, Aneesh is your man :) In the test case we used -m 768. I reran the test with -m 2048 -- it crashed the same way. I reran the test with -m 20480 -- it crashed the same way. Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones virt-df lists disk usage of guests without needing to install any software inside the virtual machine. Supports Linux and Windows. http://people.redhat.com/~rjones/virt-df/
Re: [Qemu-devel] [qom-cpu PATCH v2] target-i386: Don't declare variables in the middle of blocks
Am 19.02.2014 20:39, schrieb Eduardo Habkost: Some of my recent changes introduced variable declarations in the middle of code blocks. Fix the code so that it compiles without warnings when using -Wdeclaration-after-statement. Signed-off-by: Eduardo Habkost ehabk...@redhat.com --- Changes v2: * Rebased on top of qom-cpu I could've sworn that I applied v1, but it's indeed not on qom-cpu... Thanks for rebasing, applied to qom-cpu: https://github.com/afaerber/qemu-cpu/commits/qom-cpu Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH v3 0/6] dataplane: switch to N:M devices-per-thread model
v2: * Based off Igor's -object/object-add support custom location and 2nd stage initialization series * Dropped dedicated -iothread option in favor of -object * Avoid re-acquiring rfifo in iothread_run() [mdroth] v3: * Fixed Reliquinish typo [fam] * Rebased onto qemu.git/master which now has Igor's -object improvements This series moves the event loop thread out of dataplane code. It makes -object iothread,id=foo a separate concept so several devices can be bound to same iothread. Syntax: qemu -object iothread,id=iothread0 \ -device virtio-blk-pci,iothread=iothread0,x-data-plane=on,... For backwards-compatibility the iothread= parameter can be omitted. A per-device IOThread will be created behind the scenes (just like the old 1:1 threading model). This series includes the aio_context_acquire/release API which makes it easy to synchronize access to AioContext across threads. After this series I will send separate patches for a query-iothreads command that returns thread IDs similar to query-cpus. This will allow binding dataplane threads to host CPUs. Stefan Hajnoczi (6): rfifolock: add recursive FIFO lock aio: add aio_context_acquire() and aio_context_release() iothread: add I/O thread object qdev: add get_pointer_and_free() for temporary strings iothread: add iothread qdev property type dataplane: replace internal thread with IOThread Makefile.objs| 1 + async.c | 18 ++ hw/block/dataplane/virtio-blk.c | 96 +- hw/core/qdev-properties-system.c | 65 + include/block/aio.h | 18 ++ include/hw/qdev-properties.h | 3 + include/hw/virtio/virtio-blk.h | 8 ++- include/qemu/rfifolock.h | 54 + include/sysemu/iothread.h| 30 ++ iothread.c | 123 +++ tests/Makefile | 2 + tests/test-aio.c | 58 ++ tests/test-rfifolock.c | 90 util/Makefile.objs | 1 + util/rfifolock.c | 78 + 15 files changed, 601 insertions(+), 44 deletions(-) create mode 100644 include/qemu/rfifolock.h create mode 100644 include/sysemu/iothread.h create mode 100644 iothread.c create mode 100644 tests/test-rfifolock.c create mode 100644 util/rfifolock.c -- 1.8.5.3
[Qemu-devel] [PATCH v3 3/6] iothread: add I/O thread object
This is a stand-in for Michael Roth's QContext. I expect this to be
replaced once QContext is completed.
The IOThread object is an AioContext event loop thread. This patch adds
the concept of multiple event loop threads, allowing users to define
them.
When SMP guests run on SMP hosts it makes sense to instantiate multiple
IOThreads. This spreads event loop processing across multiple cores.
Note that additional patches are required to actually bind a device to
an IOThread.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
Makefile.objs | 1 +
include/sysemu/iothread.h | 30 +++
iothread.c| 123 ++
3 files changed, 154 insertions(+)
create mode 100644 include/sysemu/iothread.h
create mode 100644 iothread.c
diff --git a/Makefile.objs b/Makefile.objs
index ac1d0e1..e24b89c 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -42,6 +42,7 @@ libcacard-y += libcacard/vcardt.o
ifeq ($(CONFIG_SOFTMMU),y)
common-obj-y = $(block-obj-y) blockdev.o blockdev-nbd.o block/
+common-obj-y += iothread.o
common-obj-y += net/
common-obj-y += qdev-monitor.o device-hotplug.o
common-obj-$(CONFIG_WIN32) += os-win32.o
diff --git a/include/sysemu/iothread.h b/include/sysemu/iothread.h
new file mode 100644
index 000..a32214a
--- /dev/null
+++ b/include/sysemu/iothread.h
@@ -0,0 +1,30 @@
+/*
+ * Event loop thread
+ *
+ * Copyright Red Hat Inc., 2013
+ *
+ * Authors:
+ * Stefan Hajnoczi stefa...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef IOTHREAD_H
+#define IOTHREAD_H
+
+#include block/aio.h
+
+#define TYPE_IOTHREAD iothread
+
+typedef struct IOThread IOThread;
+
+#define IOTHREAD(obj) \
+ OBJECT_CHECK(IOThread, obj, TYPE_IOTHREAD)
+
+IOThread *iothread_find(const char *id);
+char *iothread_get_id(IOThread *iothread);
+AioContext *iothread_get_aio_context(IOThread *iothread);
+
+#endif /* IOTHREAD_H */
diff --git a/iothread.c b/iothread.c
new file mode 100644
index 000..033de7f
--- /dev/null
+++ b/iothread.c
@@ -0,0 +1,123 @@
+/*
+ * Event loop thread
+ *
+ * Copyright Red Hat Inc., 2013
+ *
+ * Authors:
+ * Stefan Hajnoczi stefa...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include qom/object.h
+#include qom/object_interfaces.h
+#include qemu/module.h
+#include qemu/thread.h
+#include block/aio.h
+#include sysemu/iothread.h
+
+#define IOTHREADS_PATH /objects
+
+typedef ObjectClass IOThreadClass;
+struct IOThread {
+Object parent;
+QemuThread thread;
+AioContext *ctx;
+bool stopping;
+};
+
+#define IOTHREAD_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IOThreadClass, obj, TYPE_IOTHREAD)
+#define IOTHREAD_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IOThreadClass, klass, TYPE_IOTHREAD)
+
+static void *iothread_run(void *opaque)
+{
+IOThread *iothread = opaque;
+
+while (!iothread-stopping) {
+aio_context_acquire(iothread-ctx);
+while (!iothread-stopping aio_poll(iothread-ctx, true)) {
+/* Progress was made, keep going */
+}
+aio_context_release(iothread-ctx);
+}
+return NULL;
+}
+
+static void iothread_instance_finalize(Object *obj)
+{
+IOThread *iothread = IOTHREAD(obj);
+
+iothread-stopping = true;
+aio_notify(iothread-ctx);
+qemu_thread_join(iothread-thread);
+aio_context_unref(iothread-ctx);
+}
+
+static void iothread_complete(UserCreatable *obj, Error **errp)
+{
+IOThread *iothread = IOTHREAD(obj);
+
+iothread-stopping = false;
+iothread-ctx = aio_context_new();
+
+/* This assumes we are called from a thread with useful CPU affinity for us
+ * to inherit.
+ */
+qemu_thread_create(iothread-thread, iothread_run,
+ iothread, QEMU_THREAD_JOINABLE);
+}
+
+static void iothread_class_init(ObjectClass *klass, void *class_data)
+{
+UserCreatableClass *ucc = USER_CREATABLE_CLASS(klass);
+ucc-complete = iothread_complete;
+}
+
+static const TypeInfo iothread_info = {
+.name = TYPE_IOTHREAD,
+.parent = TYPE_OBJECT,
+.class_init = iothread_class_init,
+.instance_size = sizeof(IOThread),
+.instance_finalize = iothread_instance_finalize,
+.interfaces = (InterfaceInfo[]) {
+{TYPE_USER_CREATABLE},
+{}
+},
+};
+
+static void iothread_register_types(void)
+{
+type_register_static(iothread_info);
+}
+
+type_init(iothread_register_types)
+
+IOThread *iothread_find(const char *id)
+{
+Object *container = container_get(object_get_root(), IOTHREADS_PATH);
+Object *child;
+
+child = object_property_get_link(container, id, NULL);
+if (!child) {
+return NULL;
+}
+return (IOThread *)object_dynamic_cast(child, TYPE_IOTHREAD);
+}
+
+char *iothread_get_id(IOThread *iothread)
+{
+/* The last
[Qemu-devel] [PATCH v3 2/6] aio: add aio_context_acquire() and aio_context_release()
It can be useful to run an AioContext from a thread which normally does
not own the AioContext. For example, request draining can be
implemented by acquiring the AioContext and looping aio_poll() until all
requests have been completed.
The following pattern should work:
/* Event loop thread */
while (running) {
aio_context_acquire(ctx);
aio_poll(ctx, true);
aio_context_release(ctx);
}
/* Another thread */
aio_context_acquire(ctx);
bdrv_read(bs, 0x1000, buf, 1);
aio_context_release(ctx);
This patch implements aio_context_acquire() and aio_context_release().
Note that existing aio_poll() callers do not need to worry about
acquiring and releasing - it is only needed when multiple threads will
call aio_poll() on the same AioContext.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
async.c | 18 +
include/block/aio.h | 18 +
tests/test-aio.c| 58 +
3 files changed, 94 insertions(+)
diff --git a/async.c b/async.c
index 5fb3fa6..6930185 100644
--- a/async.c
+++ b/async.c
@@ -214,6 +214,7 @@ aio_ctx_finalize(GSource *source)
thread_pool_free(ctx-thread_pool);
aio_set_event_notifier(ctx, ctx-notifier, NULL);
event_notifier_cleanup(ctx-notifier);
+rfifolock_destroy(ctx-lock);
qemu_mutex_destroy(ctx-bh_lock);
g_array_free(ctx-pollfds, TRUE);
timerlistgroup_deinit(ctx-tlg);
@@ -250,6 +251,12 @@ static void aio_timerlist_notify(void *opaque)
aio_notify(opaque);
}
+static void aio_rfifolock_cb(void *opaque)
+{
+/* Kick owner thread in case they are blocked in aio_poll() */
+aio_notify(opaque);
+}
+
AioContext *aio_context_new(void)
{
AioContext *ctx;
@@ -257,6 +264,7 @@ AioContext *aio_context_new(void)
ctx-pollfds = g_array_new(FALSE, FALSE, sizeof(GPollFD));
ctx-thread_pool = NULL;
qemu_mutex_init(ctx-bh_lock);
+rfifolock_init(ctx-lock, aio_rfifolock_cb, ctx);
event_notifier_init(ctx-notifier, false);
aio_set_event_notifier(ctx, ctx-notifier,
(EventNotifierHandler *)
@@ -275,3 +283,13 @@ void aio_context_unref(AioContext *ctx)
{
g_source_unref(ctx-source);
}
+
+void aio_context_acquire(AioContext *ctx)
+{
+rfifolock_lock(ctx-lock);
+}
+
+void aio_context_release(AioContext *ctx)
+{
+rfifolock_unlock(ctx-lock);
+}
diff --git a/include/block/aio.h b/include/block/aio.h
index 2efdf41..a92511b 100644
--- a/include/block/aio.h
+++ b/include/block/aio.h
@@ -19,6 +19,7 @@
#include qemu/queue.h
#include qemu/event_notifier.h
#include qemu/thread.h
+#include qemu/rfifolock.h
#include qemu/timer.h
typedef struct BlockDriverAIOCB BlockDriverAIOCB;
@@ -47,6 +48,9 @@ typedef void IOHandler(void *opaque);
struct AioContext {
GSource source;
+/* Protects all fields from multi-threaded access */
+RFifoLock lock;
+
/* The list of registered AIO handlers */
QLIST_HEAD(, AioHandler) aio_handlers;
@@ -104,6 +108,20 @@ void aio_context_ref(AioContext *ctx);
*/
void aio_context_unref(AioContext *ctx);
+/* Take ownership of the AioContext. If the AioContext will be shared between
+ * threads, a thread must have ownership when calling aio_poll().
+ *
+ * Note that multiple threads calling aio_poll() means timers, BHs, and
+ * callbacks may be invoked from a different thread than they were registered
+ * from. Therefore, code must use AioContext acquire/release or use
+ * fine-grained synchronization to protect shared state if other threads will
+ * be accessing it simultaneously.
+ */
+void aio_context_acquire(AioContext *ctx);
+
+/* Relinquish ownership of the AioContext. */
+void aio_context_release(AioContext *ctx);
+
/**
* aio_bh_new: Allocate a new bottom half structure.
*
diff --git a/tests/test-aio.c b/tests/test-aio.c
index 592721e..d384b0b 100644
--- a/tests/test-aio.c
+++ b/tests/test-aio.c
@@ -112,6 +112,63 @@ static void test_notify(void)
g_assert(!aio_poll(ctx, false));
}
+typedef struct {
+QemuMutex start_lock;
+bool thread_acquired;
+} AcquireTestData;
+
+static void *test_acquire_thread(void *opaque)
+{
+AcquireTestData *data = opaque;
+
+/* Wait for other thread to let us start */
+qemu_mutex_lock(data-start_lock);
+qemu_mutex_unlock(data-start_lock);
+
+aio_context_acquire(ctx);
+aio_context_release(ctx);
+
+data-thread_acquired = true; /* success, we got here */
+
+return NULL;
+}
+
+static void dummy_notifier_read(EventNotifier *unused)
+{
+g_assert(false); /* should never be invoked */
+}
+
+static void test_acquire(void)
+{
+QemuThread thread;
+EventNotifier notifier;
+AcquireTestData data;
+
+/* Dummy event notifier ensures aio_poll() will block */
+event_notifier_init(notifier, false);
+aio_set_event_notifier(ctx, notifier, dummy_notifier_read);
+g_assert(!aio_poll(ctx, false)); /* consume aio_notify() */
+
+
[Qemu-devel] [PATCH v3 4/6] qdev: add get_pointer_and_free() for temporary strings
get_pointer() assumes the string has unspecified lifetime (at least as
long as the object is alive). In some cases we can only produce a
temporary string that should be freed when get_pointer() is done.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/core/qdev-properties-system.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 3f29b49..aaebb87 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -31,6 +31,20 @@ static void get_pointer(Object *obj, Visitor *v, Property
*prop,
visit_type_str(v, p, name, errp);
}
+/* Same as get_pointer() but frees heap-allocated print() return value */
+static void get_pointer_and_free(Object *obj, Visitor *v, Property *prop,
+ char *(*print)(void *ptr),
+ const char *name, Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+void **ptr = qdev_get_prop_ptr(dev, prop);
+char *p;
+
+p = *ptr ? print(*ptr) : g_strdup();
+visit_type_str(v, p, name, errp);
+g_free(p);
+}
+
static void set_pointer(Object *obj, Visitor *v, Property *prop,
int (*parse)(DeviceState *dev, const char *str,
void **ptr),
--
1.8.5.3
[Qemu-devel] [PATCH v3 5/6] iothread: add iothread qdev property type
Add a iothread qdev property type so devices can be hooked up to an
IOThread from the comand-line:
qemu -object iothread,id=iothread0 \
-device some-device,iothread=iothread0
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/core/qdev-properties-system.c | 51
include/hw/qdev-properties.h | 3 +++
2 files changed, 54 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index aaebb87..82f2514 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -18,6 +18,7 @@
#include net/hub.h
#include qapi/visitor.h
#include sysemu/char.h
+#include sysemu/iothread.h
static void get_pointer(Object *obj, Visitor *v, Property *prop,
const char *(*print)(void *ptr),
@@ -392,6 +393,56 @@ void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
nd-instantiated = 1;
}
+/* --- iothread --- */
+
+static char *print_iothread(void *ptr)
+{
+return iothread_get_id(ptr);
+}
+
+static int parse_iothread(DeviceState *dev, const char *str, void **ptr)
+{
+IOThread *iothread;
+
+iothread = iothread_find(str);
+if (!iothread) {
+return -ENOENT;
+}
+object_ref(OBJECT(iothread));
+*ptr = iothread;
+return 0;
+}
+
+static void get_iothread(Object *obj, struct Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+get_pointer_and_free(obj, v, opaque, print_iothread, name, errp);
+}
+
+static void set_iothread(Object *obj, struct Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+set_pointer(obj, v, opaque, parse_iothread, name, errp);
+}
+
+static void release_iothread(Object *obj, const char *name, void *opaque)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+IOThread **ptr = qdev_get_prop_ptr(dev, prop);
+
+if (*ptr) {
+object_unref(OBJECT(*ptr));
+}
+}
+
+PropertyInfo qdev_prop_iothread = {
+.name = iothread,
+.get = get_iothread,
+.set = set_iothread,
+.release = release_iothread,
+};
+
static int qdev_add_one_global(QemuOpts *opts, void *opaque)
{
GlobalProperty *g;
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 77c6f7c..d0ab148 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -25,6 +25,7 @@ extern PropertyInfo qdev_prop_bios_chs_trans;
extern PropertyInfo qdev_prop_drive;
extern PropertyInfo qdev_prop_netdev;
extern PropertyInfo qdev_prop_vlan;
+extern PropertyInfo qdev_prop_iothread;
extern PropertyInfo qdev_prop_pci_devfn;
extern PropertyInfo qdev_prop_blocksize;
extern PropertyInfo qdev_prop_pci_host_devaddr;
@@ -151,6 +152,8 @@ extern PropertyInfo qdev_prop_arraylen;
DEFINE_PROP(_n, _s, _f, qdev_prop_vlan, NICPeers)
#define DEFINE_PROP_DRIVE(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockDriverState *)
+#define DEFINE_PROP_IOTHREAD(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_iothread, IOThread *)
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
#define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
--
1.8.5.3
[Qemu-devel] [PATCH v3 1/6] rfifolock: add recursive FIFO lock
QemuMutex does not guarantee fairness and cannot be acquired
recursively:
Fairness means each locker gets a turn and the scheduler cannot cause
starvation.
Recursive locking is useful for composition, it allows a sequence of
locking operations to be invoked atomically by acquiring the lock around
them.
This patch adds RFifoLock, a recursive lock that guarantees FIFO order.
Its first user is added in the next patch.
RFifoLock has one additional feature: it can be initialized with an
optional contention callback. The callback is invoked whenever a thread
must wait for the lock. For example, it can be used to poke the current
owner so that they release the lock soon.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
include/qemu/rfifolock.h | 54 +
tests/Makefile | 2 ++
tests/test-rfifolock.c | 90
util/Makefile.objs | 1 +
util/rfifolock.c | 78 +
5 files changed, 225 insertions(+)
create mode 100644 include/qemu/rfifolock.h
create mode 100644 tests/test-rfifolock.c
create mode 100644 util/rfifolock.c
diff --git a/include/qemu/rfifolock.h b/include/qemu/rfifolock.h
new file mode 100644
index 000..b23ab53
--- /dev/null
+++ b/include/qemu/rfifolock.h
@@ -0,0 +1,54 @@
+/*
+ * Recursive FIFO lock
+ *
+ * Copyright Red Hat, Inc. 2013
+ *
+ * Authors:
+ * Stefan Hajnoczi stefa...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef QEMU_RFIFOLOCK_H
+#define QEMU_RFIFOLOCK_H
+
+#include qemu/thread.h
+
+/* Recursive FIFO lock
+ *
+ * This lock provides more features than a plain mutex:
+ *
+ * 1. Fairness - enforces FIFO order.
+ * 2. Nesting - can be taken recursively.
+ * 3. Contention callback - optional, called when thread must wait.
+ *
+ * The recursive FIFO lock is heavyweight so prefer other synchronization
+ * primitives if you do not need its features.
+ */
+typedef struct {
+QemuMutex lock; /* protects all fields */
+
+/* FIFO order */
+unsigned int head; /* active ticket number */
+unsigned int tail; /* waiting ticket number */
+QemuCond cond; /* used to wait for our ticket number */
+
+/* Nesting */
+QemuThread owner_thread;/* thread that currently has ownership */
+unsigned int nesting; /* amount of nesting levels */
+
+/* Contention callback */
+void (*cb)(void *); /* called when thread must wait, with -lock
+ * held so it may not recursively lock/unlock
+ */
+void *cb_opaque;
+} RFifoLock;
+
+void rfifolock_init(RFifoLock *r, void (*cb)(void *), void *opaque);
+void rfifolock_destroy(RFifoLock *r);
+void rfifolock_lock(RFifoLock *r);
+void rfifolock_unlock(RFifoLock *r);
+
+#endif /* QEMU_RFIFOLOCK_H */
diff --git a/tests/Makefile b/tests/Makefile
index 9a7d2f1..55191fb 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -31,6 +31,7 @@ check-unit-y += tests/test-visitor-serialization$(EXESUF)
check-unit-y += tests/test-iov$(EXESUF)
gcov-files-test-iov-y = util/iov.c
check-unit-y += tests/test-aio$(EXESUF)
+check-unit-y += tests/test-rfifolock$(EXESUF)
check-unit-y += tests/test-throttle$(EXESUF)
gcov-files-test-aio-$(CONFIG_WIN32) = aio-win32.c
gcov-files-test-aio-$(CONFIG_POSIX) = aio-posix.c
@@ -154,6 +155,7 @@ tests/check-qjson$(EXESUF): tests/check-qjson.o
libqemuutil.a libqemustub.a
tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o
$(qom-core-obj) libqemuutil.a libqemustub.a
tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(block-obj-y)
libqemuutil.a libqemustub.a
tests/test-aio$(EXESUF): tests/test-aio.o $(block-obj-y) libqemuutil.a
libqemustub.a
+tests/test-rfifolock$(EXESUF): tests/test-rfifolock.o libqemuutil.a
libqemustub.a
tests/test-throttle$(EXESUF): tests/test-throttle.o $(block-obj-y)
libqemuutil.a libqemustub.a
tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(block-obj-y)
libqemuutil.a libqemustub.a
tests/test-iov$(EXESUF): tests/test-iov.o libqemuutil.a
diff --git a/tests/test-rfifolock.c b/tests/test-rfifolock.c
new file mode 100644
index 000..440dbcb
--- /dev/null
+++ b/tests/test-rfifolock.c
@@ -0,0 +1,90 @@
+/*
+ * RFifoLock tests
+ *
+ * Copyright Red Hat, Inc. 2013
+ *
+ * Authors:
+ * Stefan Hajnoczistefa...@redhat.com
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2 or later.
+ * See the COPYING.LIB file in the top-level directory.
+ */
+
+#include glib.h
+#include qemu-common.h
+#include qemu/rfifolock.h
+
+static void test_nesting(void)
+{
+RFifoLock lock;
+
+/* Trivial test, ensure the lock is recursive */
+rfifolock_init(lock, NULL, NULL);
+rfifolock_lock(lock);
+rfifolock_lock(lock);
+rfifolock_lock(lock);
+
[Qemu-devel] [PATCH v3 6/6] dataplane: replace internal thread with IOThread
Today virtio-blk dataplane uses a 1:1 device-per-thread model. Now that
IOThreads have been introduced we can generalize this to N:M devices per
threads.
This patch drops thread code from dataplane in favor of running inside
an IOThread AioContext.
As a bonus we solve the case where a guest keeps submitting I/O requests
while dataplane is trying to stop. Previously the dataplane thread
would continue to process requests until the request gave it a break.
Now we can shut down in bounded time thanks to
aio_context_acquire/release.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/block/dataplane/virtio-blk.c | 96 +++--
include/hw/virtio/virtio-blk.h | 8 +++-
2 files changed, 60 insertions(+), 44 deletions(-)
diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c
index 2237edb..a5afc21 100644
--- a/hw/block/dataplane/virtio-blk.c
+++ b/hw/block/dataplane/virtio-blk.c
@@ -23,6 +23,7 @@
#include virtio-blk.h
#include block/aio.h
#include hw/virtio/virtio-bus.h
+#include monitor/monitor.h /* for object_add() */
enum {
SEG_MAX = 126, /* maximum number of I/O segments */
@@ -44,8 +45,6 @@ struct VirtIOBlockDataPlane {
bool started;
bool starting;
bool stopping;
-QEMUBH *start_bh;
-QemuThread thread;
VirtIOBlkConf *blk;
int fd; /* image file descriptor */
@@ -59,12 +58,14 @@ struct VirtIOBlockDataPlane {
* (because you don't own the file descriptor or handle; you just
* use it).
*/
+IOThread *iothread;
+bool internal_iothread;
AioContext *ctx;
EventNotifier io_notifier; /* Linux AIO completion */
EventNotifier host_notifier;/* doorbell */
IOQueue ioqueue;/* Linux AIO queue (should really be per
- dataplane thread) */
+ IOThread) */
VirtIOBlockRequest requests[REQ_MAX]; /* pool of requests, managed by the
queue */
@@ -342,26 +343,7 @@ static void handle_io(EventNotifier *e)
}
}
-static void *data_plane_thread(void *opaque)
-{
-VirtIOBlockDataPlane *s = opaque;
-
-while (!s-stopping || s-num_reqs 0) {
-aio_poll(s-ctx, true);
-}
-return NULL;
-}
-
-static void start_data_plane_bh(void *opaque)
-{
-VirtIOBlockDataPlane *s = opaque;
-
-qemu_bh_delete(s-start_bh);
-s-start_bh = NULL;
-qemu_thread_create(s-thread, data_plane_thread,
- s, QEMU_THREAD_JOINABLE);
-}
-
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *blk,
VirtIOBlockDataPlane **dataplane,
Error **errp)
@@ -408,12 +390,33 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev,
VirtIOBlkConf *blk,
s-fd = fd;
s-blk = blk;
+if (blk-iothread) {
+s-internal_iothread = false;
+s-iothread = blk-iothread;
+object_ref(OBJECT(s-iothread));
+} else {
+/* Create per-device IOThread if none specified */
+Error *local_err = NULL;
+
+s-internal_iothread = true;
+object_add(TYPE_IOTHREAD, vdev-name, NULL, NULL, local_err);
+if (error_is_set(local_err)) {
+error_propagate(errp, local_err);
+g_free(s);
+return;
+}
+s-iothread = iothread_find(vdev-name);
+assert(s-iothread);
+}
+s-ctx = iothread_get_aio_context(s-iothread);
+
/* Prevent block operations that conflict with data plane thread */
bdrv_set_in_use(blk-conf.bs, 1);
*dataplane = s;
}
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s)
{
if (!s) {
@@ -422,9 +425,14 @@ void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s)
virtio_blk_data_plane_stop(s);
bdrv_set_in_use(s-blk-conf.bs, 0);
+object_unref(OBJECT(s-iothread));
+if (s-internal_iothread) {
+object_unparent(OBJECT(s-iothread));
+}
g_free(s);
}
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(s-vdev)));
@@ -448,8 +456,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
return;
}
-s-ctx = aio_context_new();
-
/* Set up guest notifier (irq) */
if (k-set_guest_notifiers(qbus-parent, 1, true) != 0) {
fprintf(stderr, virtio-blk failed to set guest notifier,
@@ -464,7 +470,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
exit(1);
}
s-host_notifier = *virtio_queue_get_host_notifier(vq);
-aio_set_event_notifier(s-ctx, s-host_notifier, handle_notify);
/* Set up ioqueue */
ioq_init(s-ioqueue, s-fd, REQ_MAX);
@@ -472,7 +477,6 @@ void
Re: [Qemu-devel] [PATCH v3 6/6] dataplane: replace internal thread with IOThread
Il 20/02/2014 13:50, Stefan Hajnoczi ha scritto:
Today virtio-blk dataplane uses a 1:1 device-per-thread model. Now that
IOThreads have been introduced we can generalize this to N:M devices per
threads.
This patch drops thread code from dataplane in favor of running inside
an IOThread AioContext.
As a bonus we solve the case where a guest keeps submitting I/O requests
while dataplane is trying to stop. Previously the dataplane thread
would continue to process requests until the request gave it a break.
Now we can shut down in bounded time thanks to
aio_context_acquire/release.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/block/dataplane/virtio-blk.c | 96 +++--
include/hw/virtio/virtio-blk.h | 8 +++-
2 files changed, 60 insertions(+), 44 deletions(-)
diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c
index 2237edb..a5afc21 100644
--- a/hw/block/dataplane/virtio-blk.c
+++ b/hw/block/dataplane/virtio-blk.c
@@ -23,6 +23,7 @@
#include virtio-blk.h
#include block/aio.h
#include hw/virtio/virtio-bus.h
+#include monitor/monitor.h /* for object_add() */
enum {
SEG_MAX = 126, /* maximum number of I/O segments */
@@ -44,8 +45,6 @@ struct VirtIOBlockDataPlane {
bool started;
bool starting;
bool stopping;
-QEMUBH *start_bh;
-QemuThread thread;
VirtIOBlkConf *blk;
int fd; /* image file descriptor */
@@ -59,12 +58,14 @@ struct VirtIOBlockDataPlane {
* (because you don't own the file descriptor or handle; you just
* use it).
*/
+IOThread *iothread;
+bool internal_iothread;
AioContext *ctx;
EventNotifier io_notifier; /* Linux AIO completion */
EventNotifier host_notifier;/* doorbell */
IOQueue ioqueue;/* Linux AIO queue (should really be per
- dataplane thread) */
+ IOThread) */
VirtIOBlockRequest requests[REQ_MAX]; /* pool of requests, managed by the
queue */
@@ -342,26 +343,7 @@ static void handle_io(EventNotifier *e)
}
}
-static void *data_plane_thread(void *opaque)
-{
-VirtIOBlockDataPlane *s = opaque;
-
-while (!s-stopping || s-num_reqs 0) {
-aio_poll(s-ctx, true);
-}
-return NULL;
-}
-
-static void start_data_plane_bh(void *opaque)
-{
-VirtIOBlockDataPlane *s = opaque;
-
-qemu_bh_delete(s-start_bh);
-s-start_bh = NULL;
-qemu_thread_create(s-thread, data_plane_thread,
- s, QEMU_THREAD_JOINABLE);
-}
-
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *blk,
VirtIOBlockDataPlane **dataplane,
Error **errp)
@@ -408,12 +390,33 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev,
VirtIOBlkConf *blk,
s-fd = fd;
s-blk = blk;
+if (blk-iothread) {
+s-internal_iothread = false;
+s-iothread = blk-iothread;
+object_ref(OBJECT(s-iothread));
+} else {
+/* Create per-device IOThread if none specified */
+Error *local_err = NULL;
+
+s-internal_iothread = true;
+object_add(TYPE_IOTHREAD, vdev-name, NULL, NULL, local_err);
+if (error_is_set(local_err)) {
+error_propagate(errp, local_err);
+g_free(s);
+return;
+}
+s-iothread = iothread_find(vdev-name);
+assert(s-iothread);
+}
+s-ctx = iothread_get_aio_context(s-iothread);
+
/* Prevent block operations that conflict with data plane thread */
bdrv_set_in_use(blk-conf.bs, 1);
*dataplane = s;
}
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s)
{
if (!s) {
@@ -422,9 +425,14 @@ void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s)
virtio_blk_data_plane_stop(s);
bdrv_set_in_use(s-blk-conf.bs, 0);
+object_unref(OBJECT(s-iothread));
+if (s-internal_iothread) {
+object_unparent(OBJECT(s-iothread));
+}
g_free(s);
}
+/* Context: QEMU global mutex held */
void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
{
BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(s-vdev)));
@@ -448,8 +456,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
return;
}
-s-ctx = aio_context_new();
-
/* Set up guest notifier (irq) */
if (k-set_guest_notifiers(qbus-parent, 1, true) != 0) {
fprintf(stderr, virtio-blk failed to set guest notifier,
@@ -464,7 +470,6 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s)
exit(1);
}
s-host_notifier = *virtio_queue_get_host_notifier(vq);
-aio_set_event_notifier(s-ctx, s-host_notifier, handle_notify);
/* Set up ioqueue */
ioq_init(s-ioqueue, s-fd, REQ_MAX);
Re: [Qemu-devel] [PATCH v3 5/6] iothread: add iothread qdev property type
Il 20/02/2014 13:50, Stefan Hajnoczi ha scritto:
Add a iothread qdev property type so devices can be hooked up to an
IOThread from the comand-line:
qemu -object iothread,id=iothread0 \
-device some-device,iothread=iothread0
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/core/qdev-properties-system.c | 51
include/hw/qdev-properties.h | 3 +++
2 files changed, 54 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index aaebb87..82f2514 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -18,6 +18,7 @@
#include net/hub.h
#include qapi/visitor.h
#include sysemu/char.h
+#include sysemu/iothread.h
static void get_pointer(Object *obj, Visitor *v, Property *prop,
const char *(*print)(void *ptr),
@@ -392,6 +393,56 @@ void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)
nd-instantiated = 1;
}
+/* --- iothread --- */
+
+static char *print_iothread(void *ptr)
+{
+return iothread_get_id(ptr);
+}
+
+static int parse_iothread(DeviceState *dev, const char *str, void **ptr)
+{
+IOThread *iothread;
+
+iothread = iothread_find(str);
+if (!iothread) {
+return -ENOENT;
+}
+object_ref(OBJECT(iothread));
+*ptr = iothread;
+return 0;
+}
+
+static void get_iothread(Object *obj, struct Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+get_pointer_and_free(obj, v, opaque, print_iothread, name, errp);
+}
+
+static void set_iothread(Object *obj, struct Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+set_pointer(obj, v, opaque, parse_iothread, name, errp);
+}
+
+static void release_iothread(Object *obj, const char *name, void *opaque)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+IOThread **ptr = qdev_get_prop_ptr(dev, prop);
+
+if (*ptr) {
+object_unref(OBJECT(*ptr));
+}
+}
+
+PropertyInfo qdev_prop_iothread = {
+.name = iothread,
+.get = get_iothread,
+.set = set_iothread,
+.release = release_iothread,
+};
+
static int qdev_add_one_global(QemuOpts *opts, void *opaque)
{
GlobalProperty *g;
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 77c6f7c..d0ab148 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -25,6 +25,7 @@ extern PropertyInfo qdev_prop_bios_chs_trans;
extern PropertyInfo qdev_prop_drive;
extern PropertyInfo qdev_prop_netdev;
extern PropertyInfo qdev_prop_vlan;
+extern PropertyInfo qdev_prop_iothread;
extern PropertyInfo qdev_prop_pci_devfn;
extern PropertyInfo qdev_prop_blocksize;
extern PropertyInfo qdev_prop_pci_host_devaddr;
@@ -151,6 +152,8 @@ extern PropertyInfo qdev_prop_arraylen;
DEFINE_PROP(_n, _s, _f, qdev_prop_vlan, NICPeers)
#define DEFINE_PROP_DRIVE(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockDriverState *)
+#define DEFINE_PROP_IOTHREAD(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_iothread, IOThread *)
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
#define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
Should become a link sooner rather than later, but I'm not holding the
series for this.
Paolo
[Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- target-ppc/translate.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 951f15e055d4..431358a83ac3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0001, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), -- 1.7.10.4
[Qemu-devel] [PULL 12/12] build: softmmu targets do not have a main.o file
Thus this rule is useless. Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- Makefile.target | 2 -- 1 file changed, 2 deletions(-) diff --git a/Makefile.target b/Makefile.target index 3945260..ba12340 100644 --- a/Makefile.target +++ b/Makefile.target @@ -130,8 +130,6 @@ else obj-y += hw/$(TARGET_BASE_ARCH)/ endif -main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS) - GENERATED_HEADERS += hmp-commands.h qmp-commands-old.h endif # CONFIG_SOFTMMU -- 1.8.3.1
Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
On 02/20/2014 02:07 PM, Alexander Graf wrote: On 20.02.2014, at 14:01, Cédric Le Goater c...@fr.ibm.com wrote: The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 indicating that that bit should be reserved and I prefer to have those two instructions be consistent with each other. ok. I will send a v2. Thanks, C.
[Qemu-devel] [PULL 03/12] rules.mak: allow per object cflags and libs
From: Fam Zheng f...@redhat.com Adds extract-libs in LINK to expand any per object libs, the syntax to define such a libs options is like: foo.o-libs := $(CURL_LIBS) in block/Makefile.objs. Similarly, foo.o-cflags := $(FOO_CFLAGS) is also supported. foo.o must be listed in a nested var (e.g. common-obj-y) to make the option variables effective. Signed-off-by: Fam Zheng f...@redhat.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- rules.mak | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/rules.mak b/rules.mak index a95fb76..0db7031 100644 --- a/rules.mak +++ b/rules.mak @@ -22,8 +22,10 @@ QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(*D)/$(*F).d # Same as -I$(SRC_PATH) -I., but for the nested source/object directories QEMU_INCLUDES += -I$(D) -I$(@D) +extract-libs = $(strip $(foreach o,$1,$($o-libs))) + %.o: %.c - $(call quiet-command,$(CC) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) -c -o $@ $, CC$(TARGET_DIR)$@) + $(call quiet-command,$(CC) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) $($@-cflags) -c -o $@ $, CC$(TARGET_DIR)$@) %.o: %.rc $(call quiet-command,$(WINDRES) -I. -o $@ $, RC$(TARGET_DIR)$@) @@ -34,7 +36,7 @@ LINKPROG = $(or $(CXX),$(CC)) ifeq ($(LIBTOOL),) LINK = $(call quiet-command,$(LINKPROG) $(QEMU_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ \ $(sort $(filter %.o, $1)) $(filter-out %.o, $1) $(version-obj-y) \ - $(LIBS), LINK $(TARGET_DIR)$@) + $(call extract-libs,$^) $(LIBS), LINK $(TARGET_DIR)$@) else LIBTOOL += $(if $(V),,--quiet) %.lo: %.c @@ -50,7 +52,7 @@ LINK = $(call quiet-command,\ $(sort $(filter %.o, $1)) $(filter-out %.o, $1) \ $(if $(filter %.lo %.la,$^),$(version-lobj-y),$(version-obj-y)) \ $(if $(filter %.lo %.la,$^),$(LIBTOOLFLAGS)) \ - $(LIBS),$(if $(filter %.lo %.la,$^),lt LINK , LINK )$(TARGET_DIR)$@) + $(call extract-libs,$^) $(LIBS),$(if $(filter %.lo %.la,$^),lt LINK , LINK )$(TARGET_DIR)$@) endif %.asm: %.S @@ -157,11 +159,22 @@ $(eval $1 = $(value save-$2-$1) $$(subdir-$2-$1)) $(eval save-$2-$1 :=) endef +define fix-obj-vars +$(foreach v,$($1), \ + $(if $($v-cflags), \ + $(eval $2$v-cflags := $($v-cflags)) \ + $(eval $v-cflags := )) \ + $(if $($v-libs), \ + $(eval $2$v-libs := $($v-libs)) \ + $(eval $v-libs := ))) +endef + define unnest-dir $(foreach var,$(nested-vars),$(call push-var,$(var),$1/)) $(eval obj-parent-$1 := $(obj)) $(eval obj := $(if $(obj),$(obj)/$1,$1)) $(eval include $(SRC_PATH)/$1/Makefile.objs) +$(foreach v,$(nested-vars),$(call fix-obj-vars,$v,$(if $(obj),$(obj)/))) $(eval obj := $(obj-parent-$1)) $(eval obj-parent-$1 := ) $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/)) -- 1.8.3.1
Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
On 20.02.2014, at 14:01, Cédric Le Goater c...@fr.ibm.com wrote: The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes as no-ops just like the 'dcbt' instruction. Other 'dcb*' instructions might be impacted but they have not showed up yet. Signed-off-by: Cédric Le Goater c...@fr.ibm.com Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 indicating that that bit should be reserved and I prefer to have those two instructions be consistent with each other. Alex --- target-ppc/translate.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 951f15e055d4..431358a83ac3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0001, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), -- 1.7.10.4
Re: [Qemu-devel] [PULL 00/22] QMP queue
On 17 February 2014 17:46, Luiz Capitulino lcapitul...@redhat.com wrote: On Sat, 15 Feb 2014 15:36:05 + Peter Maydell peter.mayd...@linaro.org wrote: On 13 February 2014 15:30, Luiz Capitulino lcapitul...@redhat.com wrote: The following changes since commit 9d74f6fef0801ca2ce5c9d38d59b85bf03c27669: Merge remote-tracking branch 'remotes/alon/pull-libcacard.glusterfs' into staging (2014-02-12 17:53:31 +) are available in the git repository at: git://repo.or.cz/qemu/qmp-unstable.git queue/qmp for you to fetch changes up to ebdc5cbd04a47af74f8b853f8ec95ab6291c7b53: monitor: Add object_add class argument completion. (2014-02-13 08:49:35 -0500) Hi. This doesn't build on 32 bit hosts, I'm afraid: CCaarch64-softmmu/dump.o /root/qemu/dump.c: In function 'write_dump_pages': /root/qemu/dump.c:1356:21: error: passing argument 2 of 'compress2' from incompatible pointer type [-Werror] In file included from /root/qemu/dump.c:28:0: /usr/include/zlib.h:1157:12: note: expected 'uLongf *' but argument is of type 'size_t *' cc1: all warnings being treated as errors I dropped the offending series, can you try again please? Updated branch applied, thanks. -- PMM
[Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst
The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 000a7cc0 memrchr: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addir2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addir7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 which breaks grep, and other commands, in TCG mode : invalid bits: 0200 for opcode: 1f - 16 - 08 (7e09322c) 3fff799feca0 This patch adds the extended opcodes for dcbt/dcbtst as no-ops just like the 'dcbt' instruction. Signed-off-by: Cédric Le Goater c...@fr.ibm.com --- Changes in v2: - added extended opcodes for dcbtst target-ppc/translate.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Index: qemu-agraf.git/target-ppc/translate.c === --- qemu-agraf.git.orig/target-ppc/translate.c +++ qemu-agraf.git/target-ppc/translate.c @@ -9596,8 +9596,8 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C1, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E1, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E1, PPC_CACHE), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0201, PPC_CACHE), -GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0201, PPC_CACHE), +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x0001, PPC_CACHE), +GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x0001, PPC_CACHE), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C1, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x0181, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x0201, PPC_ALTIVEC), -- 1.7.10.4
