[Qemu-devel] [PATCH] mirror: Fix coroutine reentrance
This fixes a regression introduced by commit dcfb3beb (mirror: Do zero
write on target if sectors not allocated), which was reported to cause
aborts with the message Co-routine re-entered recursively.
The cause for this bug is the following code in mirror_iteration_done():
if (s-common.busy) {
qemu_coroutine_enter(s-common.co, NULL);
}
This has always been ugly because - unlike most places that reenter - it
doesn't have a specific yield that it pairs with, but is more
uncontrolled. What we really mean here is reenter the coroutine if
it's in one of the four explicit yields in mirror.c.
This used to be equivalent with s-common.busy because neither
mirror_run() nor mirror_iteration() call any function that could yield.
However since commit dcfb3beb this doesn't hold true any more:
bdrv_get_block_status_above() can yield.
So what happens is that bdrv_get_block_status_above() wants to take a
lock that is already held, so it adds itself to the queue of waiting
coroutines and yields. Instead of being woken up by the unlock function,
however, it gets woken up by mirror_iteration_done(), which is obviously
wrong.
In most cases the code actually happens to cope fairly well with such
cases, but in this specific case, the unlock must already have scheduled
the coroutine for wakeup when mirror_iteration_done() reentered it. And
then the coroutine happened to process the scheduled restarts and tried
to reenter itself recursively.
This patch fixes the problem by pairing the reenter in
mirror_iteration_done() with specific yields instead of abusing
s-common.busy.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Kevin Wolf kw...@redhat.com
---
block/mirror.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/block/mirror.c b/block/mirror.c
index fc4d8f5..b2fb4b9 100644
--- a/block/mirror.c
+++ b/block/mirror.c
@@ -60,6 +60,7 @@ typedef struct MirrorBlockJob {
int sectors_in_flight;
int ret;
bool unmap;
+bool waiting_for_io;
} MirrorBlockJob;
typedef struct MirrorOp {
@@ -114,11 +115,7 @@ static void mirror_iteration_done(MirrorOp *op, int ret)
qemu_iovec_destroy(op-qiov);
g_slice_free(MirrorOp, op);
-/* Enter coroutine when it is not sleeping. The coroutine sleeps to
- * rate-limit itself. The coroutine will eventually resume since there is
- * a sleep timeout so don't wake it early.
- */
-if (s-common.busy) {
+if (s-waiting_for_io) {
qemu_coroutine_enter(s-common.co, NULL);
}
}
@@ -203,7 +200,9 @@ static uint64_t coroutine_fn
mirror_iteration(MirrorBlockJob *s)
/* Wait for I/O to this cluster (from a previous iteration) to be done. */
while (test_bit(next_chunk, s-in_flight_bitmap)) {
trace_mirror_yield_in_flight(s, sector_num, s-in_flight);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
do {
@@ -239,7 +238,9 @@ static uint64_t coroutine_fn
mirror_iteration(MirrorBlockJob *s)
*/
while (nb_chunks == 0 s-buf_free_count added_chunks) {
trace_mirror_yield_buf_busy(s, nb_chunks, s-in_flight);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
if (s-buf_free_count nb_chunks + added_chunks) {
trace_mirror_break_buf_busy(s, nb_chunks, s-in_flight);
@@ -333,7 +334,9 @@ static void mirror_free_init(MirrorBlockJob *s)
static void mirror_drain(MirrorBlockJob *s)
{
while (s-in_flight 0) {
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
}
@@ -506,7 +509,9 @@ static void coroutine_fn mirror_run(void *opaque)
if (s-in_flight == MAX_IN_FLIGHT || s-buf_free_count == 0 ||
(cnt == 0 s-in_flight 0)) {
trace_mirror_yield(s, s-in_flight, s-buf_free_count, cnt);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
continue;
} else if (cnt != 0) {
delay_ns = mirror_iteration(s);
--
1.8.3.1
Re: [Qemu-devel] [v2 0/4] Fix long vm downtime during live migration
On 13/08/2015 07:46, Liang Li wrote: Some cleanup operations take long time during the pause and copy stage, especially with the KVM patch 3ea3b7fa9af067, do these operations after the completion of live migration can help to reduce VM downtime. Ony the first patch changes the behavior, the rest 3 patches are for code cleanup. Changes: * Remove qemu_savevm_sate_cancel() in migrate_fd_cleanup() * Add 2 more patches for code clean up Reviewed-by: Paolo Bonzini pbonz...@redhat.com
Re: [Qemu-devel] [PATCH 08/10] tcg: add memory barriers in page_find_alloc accesses
On 12/08/2015 22:37, Emilio G. Cota wrote: page_find is reading the radix tree outside all locks, so it has to use the RCU primitives. It does not need RCU critical sections because the PageDescs are never removed, so there is never a need to wait for the end of code sections that use a PageDesc. Note that rcu_find_alloc might end up writing to the tree, see below. Yes, but in that case it's always called with the mmap_lock held, see patch 7. page_find_alloc is only called by tb_alloc_page (called by tb_link_page which takes mmap_lock), or by page_set_flags (called with mmap_lock held by linux-user/mmap.c). BTW the fact that there are no removals makes the use of RCU unnecessary. It only makes it not use the RCU synchronization primitives. You still need the memory barriers. I argue however that it is better to call page_find/_alloc with a mutex held, since otherwise we'd have to add per-PageDesc locks (it's very common to call page_find and then update the PageDesc). The fields are protected by either the mmap_lock (e.g. the flags, see page_unprotect and tb_alloc_page) or the tb_lock (e.g. the tb lists). The code is complicated and could definitely use more documentation, especially for struct PageDesc, but it seems correct to me apart from the lock inversion fixed in patch 10. Paolo
Re: [Qemu-devel] Qemu-devel Digest, Vol 149, Issue 266
On 08/13/2015 08:32 AM, Ouyang, Changchun wrote:
-Original Message-
Date: Wed, 12 Aug 2015 14:15:54 +0300
From: Michael S. Tsirkin m...@redhat.com
To: Marcel Apfelbaum mar...@redhat.com
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] virtio/vhost: drop unnecessary
VHOST_SET_VRING call
Message-ID: 20150812141448-mutt-send-email-...@redhat.com
Content-Type: text/plain; charset=us-ascii
On Wed, Aug 12, 2015 at 02:10:56PM +0300, Marcel Apfelbaum wrote:
On 08/12/2015 01:34 PM, Michael S. Tsirkin wrote:
On Wed, Aug 12, 2015 at 01:19:51PM +0300, Marcel Apfelbaum wrote:
No need to send VHOST_SET_VRING_CALL to backend before the
negotiation with the guest is finished.
Signed-off-by: Marcel Apfelbaum mar...@redhat.com
Well - we do need to set it to the masked notifier initially to avoid
losing events. You can't just drop it - need to move this call
somewhere else.
Agree with m.s.t.
We could not drop it.
Vhost-user multi queue also need this.
I'll try to call it a little bit later instead of dropping it.
Thanks,
Marcel
What do we need to set?
I just dropped the call to VHOST_SET_VRING_CALL.
Thanks,
Marcel
We use two eventfds: masked and unmasked one.
We switch dynamically dependent on msi mask value.
Code assumes we start out masked, so we need to match that.
---
hw/virtio/vhost.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index
2712c6f..b448542 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -875,24 +875,13 @@ static void
vhost_eventfd_del(MemoryListener
*listener,
static int vhost_virtqueue_init(struct vhost_dev *dev,
struct vhost_virtqueue *vq, int n)
{
-struct vhost_vring_file file = {
-.index = n,
-};
int r = event_notifier_init(vq-masked_notifier, 0);
+
if (r 0) {
return r;
}
-file.fd = event_notifier_get_fd(vq-masked_notifier);
-r = dev-vhost_ops-vhost_call(dev, VHOST_SET_VRING_CALL, file);
-if (r) {
-r = -errno;
-goto fail_call;
-}
return 0;
-fail_call:
-event_notifier_cleanup(vq-masked_notifier);
-return r;
}
static void vhost_virtqueue_cleanup(struct vhost_virtqueue *vq)
--
2.1.0
[Qemu-devel] [PULL 12/27] i.MX: Fix Coding style for AVIC emulator.
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
01e1d9026220992405819f25640ebd5bb843fc93.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/intc/imx_avic.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c
index c5eecb5..96c376b 100644
--- a/hw/intc/imx_avic.c
+++ b/hw/intc/imx_avic.c
@@ -22,7 +22,7 @@
#ifdef DEBUG_INT
#define DPRINTF(fmt, args...) \
-do { printf(imx_avic: fmt , ##args); } while (0)
+do { printf(%s: fmt , TYPE_IMX_AVIC, ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif
@@ -34,13 +34,13 @@ do { printf(imx_avic: fmt , ##args); } while (0)
#define DEBUG_IMPLEMENTATION 1
#if DEBUG_IMPLEMENTATION
# define IPRINTF(fmt, args...) \
-do { fprintf(stderr, imx_avic: fmt, ##args); } while (0)
+do { fprintf(stderr, %s: fmt, TYPE_IMX_AVIC, ##args); } while (0)
#else
# define IPRINTF(fmt, args...) do {} while (0)
#endif
static const VMStateDescription vmstate_imx_avic = {
-.name = imx-avic,
+.name = TYPE_IMX_AVIC,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
@@ -54,8 +54,6 @@ static const VMStateDescription vmstate_imx_avic = {
},
};
-
-
static inline int imx_avic_prio(IMXAVICState *s, int irq)
{
uint32_t word = irq / PRIO_PER_WORD;
@@ -215,7 +213,7 @@ static uint64_t imx_avic_read(void *opaque,
return 0x4;
default:
-IPRINTF(imx_avic_read: Bad offset 0x%x\n, (int)offset);
+IPRINTF(%s: Bad offset 0x%x\n, __func__, (int)offset);
return 0;
}
}
@@ -227,12 +225,12 @@ static void imx_avic_write(void *opaque, hwaddr offset,
/* Vector Registers not yet supported */
if (offset = 0x100 offset = 0x2fc) {
-IPRINTF(imx_avic_write to vector register %d ignored\n,
+IPRINTF(%s to vector register %d ignored\n, __func__,
(unsigned int)((offset - 0x100) 2));
return;
}
-DPRINTF(imx_avic_write(0x%x) = %x\n,
+DPRINTF(%s(0x%x) = %x\n, __func__,
(unsigned int)offset2, (unsigned int)val);
switch (offset 2) {
case 0: /* Interrupt Control Register, INTCNTL */
@@ -307,7 +305,7 @@ static void imx_avic_write(void *opaque, hwaddr offset,
return;
default:
-IPRINTF(imx_avic_write: Bad offset %x\n, (int)offset);
+IPRINTF(%s: Bad offset %x\n, __func__, (int)offset);
}
imx_avic_update(s);
}
--
1.9.1
[Qemu-devel] [PULL 04/27] target-arm: Pass timeridx as argument to various timer functions
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Prepare for adding the Hypervisor timer, no functional change.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1436791864-4582-5-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 99 +
1 file changed, 77 insertions(+), 22 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8dee980..0dcc0ec 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1261,10 +1261,10 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
}
}
-static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
+ int timeridx)
{
ARMCPU *cpu = arm_env_get_cpu(env);
-int timeridx = ri-opc1 1;
timer_del(cpu-gt_timer[timeridx]);
}
@@ -1280,17 +1280,16 @@ static uint64_t gt_virt_cnt_read(CPUARMState *env,
const ARMCPRegInfo *ri)
}
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ int timeridx,
uint64_t value)
{
-int timeridx = ri-opc1 1;
-
env-cp15.c14_timer[timeridx].cval = value;
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
-static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
+ int timeridx)
{
-int timeridx = ri-crm 1;
uint64_t offset = timeridx == GTIMER_VIRT ? env-cp15.cntvoff_el2 : 0;
return (uint32_t)(env-cp15.c14_timer[timeridx].cval -
@@ -1298,9 +1297,9 @@ static uint64_t gt_tval_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ int timeridx,
uint64_t value)
{
-int timeridx = ri-crm 1;
uint64_t offset = timeridx == GTIMER_VIRT ? env-cp15.cntvoff_el2 : 0;
env-cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
@@ -1309,10 +1308,10 @@ static void gt_tval_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ int timeridx,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
-int timeridx = ri-crm 1;
uint32_t oldval = env-cp15.c14_timer[timeridx].ctl;
env-cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
@@ -1328,6 +1327,62 @@ static void gt_ctl_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
+static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+gt_timer_reset(env, ri, GTIMER_PHYS);
+}
+
+static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_cval_write(env, ri, GTIMER_PHYS, value);
+}
+
+static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+return gt_tval_read(env, ri, GTIMER_PHYS);
+}
+
+static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_tval_write(env, ri, GTIMER_PHYS, value);
+}
+
+static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_ctl_write(env, ri, GTIMER_PHYS, value);
+}
+
+static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+gt_timer_reset(env, ri, GTIMER_VIRT);
+}
+
+static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_cval_write(env, ri, GTIMER_VIRT, value);
+}
+
+static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+return gt_tval_read(env, ri, GTIMER_VIRT);
+}
+
+static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_tval_write(env, ri, GTIMER_VIRT, value);
+}
+
+static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_ctl_write(env, ri, GTIMER_VIRT, value);
+}
+
static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1380,7 +1435,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.accessfn = gt_ptimer_access,
.fieldoffset = offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_PHYS].ctl),
- .writefn = gt_ctl_write, .raw_writefn = raw_write,
+ .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
},
{ .name = CNTP_CTL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
@@ -1388,14 +1443,14 @@ static
[Qemu-devel] [PULL 00/27] target-arm queue
Flushing the accumulated changes from during the 2.4 freeze... -- PMM The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596: Open 2.5 development tree (2015-08-11 23:15:55 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150813 for you to fetch changes up to f7a6785e12d834d05200b0595070db453344b25d: i.MX: Fix UART driver to work with unitialized chardev device (2015-08-13 11:26:22 +0100) target-arm queue: * i.MX code cleanup/refactorings * i.MX UART fix to work with uninitialized chardev * minor GIC code refactorings * implement the ARM Secure physical timer * implement the ARM Hypervisor timer Edgar E. Iglesias (7): target-arm: Add CNTVOFF_EL2 target-arm: Add CNTHCTL_EL2 target-arm: Rename and move gt_cnt_reset target-arm: Pass timeridx as argument to various timer functions target-arm: Add the Hypervisor timer hw/arm/virt: Replace magic IRQ constants with macros hw/arm/virt: Connect the Hypervisor timer Jean-Christophe Dubois (12): i.MX: Split UART emulator in a header file and a source file i.MX: Move serial initialization to init/realize of DeviceClass. i.MX:Fix Coding style for UART emulator. i.MX: Split AVIC emulator in a header file and a source file i.MX: Fix Coding style for AVIC emulator. i.MX: Split CCM emulator in a header file and a source file i.MX: Fix Coding style for CCM emulator i.MX: Split EPIT emulator in a header file and a source file i.MX: Fix Coding style for EPIT emulator i.MX: Split GPT emulator in a header file and a source file i.MX: Fix Coding style for GPT emulator i.MX: Fix UART driver to work with unitialized chardev device Pavel Fedin (3): Merge memory_region_init_reservation() into memory_region_init_io() hw/arm/gic: Kill code duplication Introduce gic_class_name() instead of repeating condition Peter Maydell (5): target-arm: Add debug check for mismatched cpreg resets target-arm: Add the AArch64 view of the Secure physical timer target-arm: Add AArch32 banked register access to secure physical timer hw/arm/virt: Wire up secure timer interrupt hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts hw/arm/kzm.c | 5 +- hw/arm/virt.c| 32 ++-- hw/char/imx_serial.c | 159 + hw/cpu/a15mpcore.c | 29 ++-- hw/intc/arm_gic.c| 64 ++- hw/intc/arm_gic_common.c | 41 + hw/intc/arm_gic_kvm.c| 28 +-- hw/intc/imx_avic.c | 56 ++ hw/misc/imx_ccm.c| 81 + hw/timer/imx_epit.c | 64 +-- hw/timer/imx_gpt.c | 85 + include/exec/memory.h| 14 +- include/hw/arm/imx.h | 12 +- include/hw/char/imx_serial.h | 102 +++ include/hw/intc/arm_gic_common.h | 3 + include/hw/intc/imx_avic.h | 55 ++ include/hw/misc/imx_ccm.h| 91 ++ include/hw/timer/imx_epit.h | 79 + include/hw/timer/imx_gpt.h | 107 memory.c | 10 +- target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 27 +++ target-arm/cpu.h | 9 +- target-arm/helper.c | 367 +++ target-arm/kvm_arm.h | 5 + 25 files changed, 1003 insertions(+), 524 deletions(-) create mode 100644 include/hw/char/imx_serial.h create mode 100644 include/hw/intc/imx_avic.h create mode 100644 include/hw/misc/imx_ccm.h create mode 100644 include/hw/timer/imx_epit.h create mode 100644 include/hw/timer/imx_gpt.h
[Qemu-devel] [PATCH 0/5] Migration cleanups
From: Dr. David Alan Gilbert dgilb...@redhat.com This series is a set of small cleanups, some of which are from my postcopy series. Dave Dr. David Alan Gilbert (5): migration/ram.c: Use RAMBlock rather than MemoryRegion Split out end of migration code from migration_thread Init page sizes in qtest migration: size_t'ify some of qemu-file migration: qemu-file more size_t'ifying include/migration/qemu-file.h | 18 +-- migration/migration.c | 75 +++ migration/qemu-file-buf.c | 7 ++-- migration/qemu-file-stdio.c | 11 --- migration/qemu-file-unix.c| 6 ++-- migration/qemu-file.c | 22 ++--- migration/ram.c | 26 +++ migration/rdma.c | 13 migration/savevm.c| 7 ++-- qtest.c | 1 + trace-events | 4 ++- 11 files changed, 107 insertions(+), 83 deletions(-) -- 2.4.3
[Qemu-devel] [PATCH 4/5] migration: size_t'ify some of qemu-file
From: Dr. David Alan Gilbert dgilb...@redhat.com
This is a start on using size_t more in qemu-file and friends;
it fixes up QEMUFilePutBufferFunc and QEMUFileGetBufferFunc
to take size_t lengths and return ssize_t return values (like read(2))
and fixes up all the different implementations of them.
Note that I've not yet followed this deeply into bdrv_ implementations.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
include/migration/qemu-file.h | 8
migration/qemu-file-buf.c | 7 ---
migration/qemu-file-stdio.c | 11 ++-
migration/qemu-file-unix.c| 6 --
migration/rdma.c | 13 +++--
migration/savevm.c| 7 ---
trace-events | 2 +-
7 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index ea49f33..e1e2bab 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -31,15 +31,15 @@
* The pos argument can be ignored if the file is only being used for
* streaming. The handler should try to write all of the data it can.
*/
-typedef int (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf,
-int64_t pos, int size);
+typedef ssize_t (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf,
+int64_t pos, size_t size);
/* Read a chunk of data from a file at the given position. The pos argument
* can be ignored if the file is only be used for streaming. The number of
* bytes actually read should be returned.
*/
-typedef int (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf,
-int64_t pos, int size);
+typedef ssize_t (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf,
+int64_t pos, size_t size);
/* Close a file
*
diff --git a/migration/qemu-file-buf.c b/migration/qemu-file-buf.c
index 2de9330..1d9528e 100644
--- a/migration/qemu-file-buf.c
+++ b/migration/qemu-file-buf.c
@@ -372,7 +372,8 @@ typedef struct QEMUBuffer {
bool qsb_allocated;
} QEMUBuffer;
-static int buf_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t buf_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUBuffer *s = opaque;
ssize_t len = qsb_get_length(s-qsb) - pos;
@@ -387,8 +388,8 @@ static int buf_get_buffer(void *opaque, uint8_t *buf,
int64_t pos, int size)
return qsb_get_buffer(s-qsb, pos, len, buf);
}
-static int buf_put_buffer(void *opaque, const uint8_t *buf,
- int64_t pos, int size)
+static ssize_t buf_put_buffer(void *opaque, const uint8_t *buf,
+ int64_t pos, size_t size)
{
QEMUBuffer *s = opaque;
diff --git a/migration/qemu-file-stdio.c b/migration/qemu-file-stdio.c
index 285068b..dc91137 100644
--- a/migration/qemu-file-stdio.c
+++ b/migration/qemu-file-stdio.c
@@ -37,11 +37,11 @@ static int stdio_get_fd(void *opaque)
return fileno(s-stdio_file);
}
-static int stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos,
-int size)
+static ssize_t stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos,
+size_t size)
{
QEMUFileStdio *s = opaque;
-int res;
+size_t res;
res = fwrite(buf, 1, size, s-stdio_file);
@@ -51,11 +51,12 @@ static int stdio_put_buffer(void *opaque, const uint8_t
*buf, int64_t pos,
return res;
}
-static int stdio_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t stdio_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+size_t size)
{
QEMUFileStdio *s = opaque;
FILE *fp = s-stdio_file;
-int bytes;
+ssize_t bytes;
for (;;) {
clearerr(fp);
diff --git a/migration/qemu-file-unix.c b/migration/qemu-file-unix.c
index bfbc086..adfe91a 100644
--- a/migration/qemu-file-unix.c
+++ b/migration/qemu-file-unix.c
@@ -54,7 +54,8 @@ static int socket_get_fd(void *opaque)
return s-fd;
}
-static int socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUFileSocket *s = opaque;
ssize_t len;
@@ -138,7 +139,8 @@ static ssize_t unix_writev_buffer(void *opaque, struct
iovec *iov, int iovcnt,
return total;
}
-static int unix_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t unix_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUFileSocket *s = opaque;
ssize_t len;
diff --git a/migration/rdma.c b/migration/rdma.c
index 74876fd..fd430c7 100644
--- a/migration/rdma.c
+++ b/migration/rdma.c
@@ -2519,8 +2519,8 @@ static void
[Qemu-devel] [PATCH v9 0/5] vGICv3 support
This series introduces support for GICv3 by KVM. Software emulation is currently not supported. This patchset applies on top of: http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg00518.html v8 = v9 - Removed all limitations on CPU and IRQ number from the base class - Added back missing properties, interface is now the same as in GICv2 - Refactored reusable parts of vGICv2 code, decreased number of changes - Removed GIC type check from kvm_arch_irqchip_create(), no more need to specify GIC type early - Fixed up all commit messages / logs - Removed 'nvic' field assignment in virt machine (was forgotten in v8) - CPU number limitation for 'virt' machine now comes from memory map (how many redistributors can be placed). With current layout it appears to be 126. v7 = v8 - Removed all unused SW emulation code - Removed unnecessary attributes from common class - Set unmigratable flag for GICv3 device - Removed unnecessary conditions from kvm_arm_gicv3_realize() - Fixed GIC type setting in vexpress model, was done in wrong place - Fixed condition style in hw/intc/Makefile.objs - Cleaned up virt machine memory map v6 = v7 - Wrap own GIC type definitions on top of KVM ones. Fixed build on non-ARM-Linux hosts v5 = v6 - Fixed various checkpatch.pl style warnings - Removed TODO in gicv3_init_irqs_and_mmio(), relevant memory API patch included - gicv3_init_irqs_and_mmio() now takes 3 arguments instead of 4. It is more convenient to pass MMIO descriptors as array v4 = v5 - Do not reintroduce several constants shared with GICv2, reuse them instead. - Added gicv3_init_irqs_and_mmio() in base class, to be used by both software emulation and KVM code. Avoids code duplication. - Do not add NULL msi-parent phandle to PCI device in the FDT - Removed a couple of stale things from virt.c v3 = v4 - Fixed stupid build breakage in patch 0002 - Rebased on top of current master, patch 0003 adjusted according to kvm_irqchip_create() changes - Added assertion against uninitialized kernel_irqchip_type - Removed kernel_irqchip_type initialization from models which do not use KVM vGIC v2 = v3 - Removed some unrelated and unnecessary changes from virt machine, occasionally slipped in; some of them caused qemu to crash on ARM32. - Fixed build for ARM32; vGICv3 code requires definitions which are present only in ARM64 kernel v1 = v2 - Base class included, taken from the series by Shlomo Pongratz: http://lists.nongnu.org/archive/html/qemu-devel/2015-06/msg01512.html The code is refactored as little as possible in order to simplify further addition of software emulation: - Minor fixes in code style and comments, according to old reviews - Removed REV_V3 definition because it's currently not used, and it does not add any meaning to number 3. - Removed reserved regions for MBI and ITS (except for 'virt' machine memory map). These should go to separate classes when implemented. - Improved commit messages - vGIC patches restructured - Use 'gicversion' option instead of virt-v3 machine Pavel Fedin (4): intc/gic: Extract some reusable vGIC code arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create() hw/intc: Initial implementation of vGICv3 hw/arm/virt: Add gicversion option to virt machine Shlomo Pongratz (1): hw/intc: Implement GIC-500 base class hw/arm/virt.c | 111 ++- hw/intc/Makefile.objs | 2 + hw/intc/arm_gic_kvm.c | 40 +- hw/intc/arm_gicv3_common.c | 140 ++ hw/intc/arm_gicv3_kvm.c| 149 + hw/intc/vgic_common.h | 55 ++ include/hw/arm/fdt.h | 2 +- include/hw/arm/virt.h | 5 +- include/hw/intc/arm_gicv3_common.h | 68 + target-arm/kvm.c | 10 +-- target-arm/kvm_arm.h | 10 +++ target-arm/machine.c | 18 + 12 files changed, 556 insertions(+), 54 deletions(-) create mode 100644 hw/intc/arm_gicv3_common.c create mode 100644 hw/intc/arm_gicv3_kvm.c create mode 100644 hw/intc/vgic_common.h create mode 100644 include/hw/intc/arm_gicv3_common.h -- 1.9.5.msysgit.0
[Qemu-devel] [PATCH v9 3/5] arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()
This allows to use different GIC types from v2. There are no kernels which
could advertise KVM_CAP_DEVICE_CTRL without the actual ability to create
GIC with it.
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
target-arm/kvm.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index b278542..22383c5 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -585,18 +585,10 @@ void kvm_arch_init_irq_routing(KVMState *s)
int kvm_arch_irqchip_create(KVMState *s)
{
-int ret;
-
/* If we can create the VGIC using the newer device control API, we
* let the device do this when it initializes itself, otherwise we
* fall back to the old API */
-
-ret = kvm_create_device(s, KVM_DEV_TYPE_ARM_VGIC_V2, true);
-if (ret == 0) {
-return 1;
-}
-
-return 0;
+return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
}
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
--
1.9.5.msysgit.0
[Qemu-devel] [PULL 02/27] target-arm: Add CNTHCTL_EL2
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Adds control for trapping selected timer and counter accesses to EL2.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1436791864-4582-3-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 33 +++--
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b1fa287..ea41052 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -358,6 +358,7 @@ typedef struct CPUARMState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
+uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b8188ad..3f8d06e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1154,23 +1154,41 @@ static CPAccessResult gt_cntfrq_access(CPUARMState
*env, const ARMCPRegInfo *ri)
static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
+unsigned int cur_el = arm_current_el(env);
+bool secure = arm_is_secure(env);
+
/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
-if (arm_current_el(env) == 0
+if (cur_el == 0
!extract32(env-cp15.c14_cntkctl, timeridx, 1)) {
return CP_ACCESS_TRAP;
}
+
+if (arm_feature(env, ARM_FEATURE_EL2)
+timeridx == GTIMER_PHYS !secure cur_el 2
+!extract32(env-cp15.cnthctl_el2, 0, 1)) {
+return CP_ACCESS_TRAP_EL2;
+}
return CP_ACCESS_OK;
}
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
+unsigned int cur_el = arm_current_el(env);
+bool secure = arm_is_secure(env);
+
/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
* EL0[PV]TEN is zero.
*/
-if (arm_current_el(env) == 0
+if (cur_el == 0
!extract32(env-cp15.c14_cntkctl, 9 - timeridx, 1)) {
return CP_ACCESS_TRAP;
}
+
+if (arm_feature(env, ARM_FEATURE_EL2)
+timeridx == GTIMER_PHYS !secure cur_el 2
+!extract32(env-cp15.cnthctl_el2, 1, 1)) {
+return CP_ACCESS_TRAP_EL2;
+}
return CP_ACCESS_OK;
}
@@ -2631,6 +2649,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = HTTBR, .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = CNTHCTL_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = CNTVOFF_EL2, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2749,6 +2770,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vaa_write },
#ifndef CONFIG_USER_ONLY
+{ .name = CNTHCTL_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
+ * reset values as IMPDEF. We choose to reset to 3 to comply with
+ * both ARMv7 and ARMv8.
+ */
+ .access = PL2_RW, .resetvalue = 3,
+ .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
{ .name = CNTVOFF_EL2, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
--
1.9.1
[Qemu-devel] [PATCH v9 2/5] intc/gic: Extract some reusable vGIC code
These functions are useful also for vGICv3 implementation. Make them accessible
from within other modules.
Actually kvm_dist_get() and kvm_dist_put() could also be made reusable, but
they would require two extra parameters (s-dev_fd and s-num_cpu) as well as
lots of typecasts of 's' to DeviceState * and back to GICState *. This makes
the code very ugly so i decided to stop at this point. I tried also an
approach with making a base class for all possible GICs, but it would contain
only three variables (dev_fd, cpu_num and irq_num), and accessing them through
the rest of the code would be again tedious (either ugly casts or qemu-style
separate object pointer). So i disliked it too.
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
hw/intc/arm_gic_kvm.c | 40 -
hw/intc/vgic_common.h | 55 +++
2 files changed, 72 insertions(+), 23 deletions(-)
create mode 100644 hw/intc/vgic_common.h
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index e5d0f67..e12296e 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -23,6 +23,7 @@
#include sysemu/kvm.h
#include kvm_arm.h
#include gic_internal.h
+#include vgic_common.h
//#define DEBUG_GIC_KVM
@@ -52,7 +53,7 @@ typedef struct KVMARMGICClass {
void (*parent_reset)(DeviceState *dev);
} KVMARMGICClass;
-static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
+void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
{
/* Meaning of the 'irq' parameter:
* [0..N-1] : external interrupts
@@ -63,10 +64,9 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int
level)
* has separate fields in the irq number for type,
* CPU number and interrupt number.
*/
-GICState *s = (GICState *)opaque;
int kvm_irq, irqtype, cpu;
-if (irq (s-num_irq - GIC_INTERNAL)) {
+if (irq (num_irq - GIC_INTERNAL)) {
/* External interrupt. The kernel numbers these like the GIC
* hardware, with external interrupt IDs starting after the
* internal ones.
@@ -77,7 +77,7 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int
level)
} else {
/* Internal interrupt: decode into (cpu, interrupt id) */
irqtype = KVM_ARM_IRQ_TYPE_PPI;
-irq -= (s-num_irq - GIC_INTERNAL);
+irq -= (num_irq - GIC_INTERNAL);
cpu = irq / GIC_INTERNAL;
irq %= GIC_INTERNAL;
}
@@ -87,6 +87,13 @@ static void kvm_arm_gic_set_irq(void *opaque, int irq, int
level)
kvm_set_irq(kvm_state, kvm_irq, !!level);
}
+static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
+{
+GICState *s = (GICState *)opaque;
+
+kvm_arm_gic_set_irq(s-num_irq, irq, level);
+}
+
static bool kvm_arm_gic_can_save_restore(GICState *s)
{
return s-dev_fd = 0;
@@ -107,7 +114,7 @@ static bool kvm_gic_supports_attr(GICState *s, int group,
int attrnum)
return kvm_device_ioctl(s-dev_fd, KVM_HAS_DEVICE_ATTR, attr) == 0;
}
-static void kvm_gic_access(GICState *s, int group, int offset,
+void kvm_gic_access(int dev_fd, int group, int offset,
int cpu, uint32_t *val, bool write)
{
struct kvm_device_attr attr;
@@ -130,7 +137,7 @@ static void kvm_gic_access(GICState *s, int group, int
offset,
type = KVM_GET_DEVICE_ATTR;
}
-err = kvm_device_ioctl(s-dev_fd, type, attr);
+err = kvm_device_ioctl(dev_fd, type, attr);
if (err 0) {
fprintf(stderr, KVM_{SET/GET}_DEVICE_ATTR failed: %s\n,
strerror(-err));
@@ -138,20 +145,6 @@ static void kvm_gic_access(GICState *s, int group, int
offset,
}
}
-static void kvm_gicd_access(GICState *s, int offset, int cpu,
-uint32_t *val, bool write)
-{
-kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
- offset, cpu, val, write);
-}
-
-static void kvm_gicc_access(GICState *s, int offset, int cpu,
-uint32_t *val, bool write)
-{
-kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
- offset, cpu, val, write);
-}
-
#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
for (_ctr = 0; _ctr ((_max_irq) / (32 / (_field_width))); _ctr++)
@@ -559,7 +552,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error
**errp)
return;
}
-gic_init_irqs_and_mmio(s, kvm_arm_gic_set_irq, NULL);
+gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL);
for (i = 0; i s-num_irq - GIC_INTERNAL; i++) {
qemu_irq irq = qdev_get_gpio_in(dev, i);
@@ -578,13 +571,14 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error
**errp)
if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
uint32_t numirqs = s-num_irq;
-kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0, numirqs, 1);
+kvm_gic_access(s-dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0,
+
[Qemu-devel] [PULL 26/27] hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
Since we now support both the hypervisor and the secure physical timer, wire
their interrupt lines up in the a15mpcore wrapper object.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1437047249-2357-5-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/cpu/a15mpcore.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index e31a1f9..58ac02e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -75,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
for (i = 0; i s-num_cpu; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s-num_irq - 32 + i * 32;
-/* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+int irq;
+/* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs used on the A15:
*/
-qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev, ppibase + 30));
-/* virtual timer */
-qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev, ppibase + 27));
+const int timer_irq[] = {
+[GTIMER_PHYS] = 30,
+[GTIMER_VIRT] = 27,
+[GTIMER_HYP] = 26,
+[GTIMER_SEC] = 29,
+};
+for (irq = 0; irq ARRAY_SIZE(timer_irq); irq++) {
+qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+}
}
/* Memory map (addresses are offsets from PERIPHBASE):
--
1.9.1
Re: [Qemu-devel] [PATCH v6 2/2] vhost-user: new protocol feature for multi queue
On Wed, Aug 12, 2015 at 02:25:42PM +0800, Ouyang Changchun wrote:
This patch is based on top of vhost-user: protocol updates series
proposed earlier by Michael S. Tsirkin.
Use new message VHOST_USER_SET_VRING_FLAG to enable and disable an
actual virt queue, which is similar to attach/detach queue for tap device.
virtio driver on guest doesn't have to use max virt queue pair, it could
enable any number of virt queue ranging from 1 to max virt queue pair.
It requires that VHOST_USER_F_PROTOCOL_FEATURES is present.
Signed-off-by: Changchun Ouyang changchun.ouy...@intel.com
---
This is added since v5
docs/specs/vhost-user.txt | 17 +
hw/net/vhost_net.c| 18 ++
hw/net/virtio-net.c | 2 ++
hw/virtio/vhost-user.c| 35 +--
include/hw/virtio/vhost-backend.h | 2 ++
include/net/vhost_net.h | 1 +
6 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/docs/specs/vhost-user.txt b/docs/specs/vhost-user.txt
index 9390f89..cca3e5b 100644
--- a/docs/specs/vhost-user.txt
+++ b/docs/specs/vhost-user.txt
@@ -135,6 +135,10 @@ As older slaves don't support negotiating protocol
features,
a feature bit was dedicated for this purpose:
#define VHOST_USER_F_PROTOCOL_FEATURES 30
+The Slave uses vring flag to notify the vhost-user whether one virtq is
enabled
+or not. This request doesn't require replies:
+#define VHOST_USER_PROTOCOL_F_VRING_FLAG 2
+
Multi queue support
---
The protocol supports multiple queues by setting all index fields in the sent
@@ -306,3 +310,16 @@ Message types
Bits (0-7) of the payload contain the vring index. Bit 8 is the
invalid FD flag. This flag is set when there is no file descriptor
in the ancillary data.
+
+ * VHOST_USER_SET_VRING_FLAG
+
+ Id: 18
+ Equivalent ioctl: N/A
+ Master payload: vring state description
+
+ Set the flag(enable or disable) in the vring, the vhost user backend
+ enable or disable the vring according to state.num. Olny legal if
feature
+ bit VHOST_USER_F_PROTOCOL_FEATURES is present in VHOST_USER_GET_FEATURE
+ and feature bit VHOST_USER_PROTOCOL_F_VRING_FLAG is present in
+ VHOST_USER_GET_PROTOCOL_FEATURES. The vring is enabled when state.num
is
+ 1, otherwise, the vring is disabled.
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index 9cd6c05..5fa341c 100644
--- a/hw/net/vhost_net.c
+++ b/hw/net/vhost_net.c
@@ -405,6 +405,19 @@ VHostNetState *get_vhost_net(NetClientState *nc)
return vhost_net;
}
+
+int vhost_set_vring_flag(NetClientState *nc, unsigned int enable)
+{
+if (nc-info-type == NET_CLIENT_OPTIONS_KIND_VHOST_USER) {
+struct vhost_net *net = get_vhost_net(nc);
+const VhostOps *vhost_ops = net-dev.vhost_ops;
+if (vhost_ops-vhost_backend_mq_set_vring_flag)
+return vhost_ops-vhost_backend_mq_set_vring_flag(net-dev,
enable);
+}
+
+return 0;
+}
+
#else
struct vhost_net *vhost_net_init(VhostNetOptions *options)
{
@@ -455,4 +468,9 @@ VHostNetState *get_vhost_net(NetClientState *nc)
{
return 0;
}
+
+int vhost_set_vring_flag(NetClientState *nc, unsigned int enable)
+{
+return 0;
+}
#endif
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 3af6faf..272b77d 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -396,6 +396,7 @@ static int peer_attach(VirtIONet *n, int index)
}
if (nc-peer-info-type != NET_CLIENT_OPTIONS_KIND_TAP) {
+vhost_set_vring_flag(nc-peer, 1);
return 0;
}
@@ -411,6 +412,7 @@ static int peer_detach(VirtIONet *n, int index)
}
if (nc-peer-info-type != NET_CLIENT_OPTIONS_KIND_TAP) {
+vhost_set_vring_flag(nc-peer, 0);
return 0;
}
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index fb11d4c..d806ce2 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -25,7 +25,8 @@
#define VHOST_MEMORY_MAX_NREGIONS8
#define VHOST_USER_F_PROTOCOL_FEATURES 30
-#define VHOST_USER_PROTOCOL_FEATURE_MASK 0x0ULL
+#define VHOST_USER_PROTOCOL_F_VRING_FLAG 2
+#define VHOST_USER_PROTOCOL_FEATURE_MASK 0x7ULL
typedef enum VhostUserRequest {
VHOST_USER_NONE = 0,
@@ -45,6 +46,7 @@ typedef enum VhostUserRequest {
VHOST_USER_SET_VRING_ERR = 14,
VHOST_USER_GET_PROTOCOL_FEATURES = 15,
VHOST_USER_SET_PROTOCOL_FEATURES = 16,
+VHOST_USER_SET_VRING_FLAG = 18,
VHOST_USER_MAX
} VhostUserRequest;
@@ -399,6 +401,34 @@ static int vhost_user_init(struct vhost_dev *dev, void
*opaque)
return 0;
}
+static int vhost_user_set_vring_flag(struct vhost_dev *dev, unsigned int
enable)
+{
+VhostUserMsg msg = { 0 };
+int err;
+
+assert(dev-vhost_ops-backend_type == VHOST_BACKEND_TYPE_USER);
[Qemu-devel] [PULL 09/27] i.MX: Move serial initialization to init/realize of DeviceClass.
From: Jean-Christophe Dubois j...@tribudubois.net
Move constructor to DeviceClass methods
* imx_serial_init
* imx_serial_realize
imx32_serial_properties is renamed to imx_serial_properties.
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
6854bd75e2b5af312e04e760587e249dbaff807f.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/char/imx_serial.c | 35 +++
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 1dcb325..f0ed255 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -306,16 +306,10 @@ static const struct MemoryRegionOps imx_serial_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int imx_serial_init(SysBusDevice *dev)
+static void imx_serial_realize(DeviceState *dev, Error **errp)
{
IMXSerialState *s = IMX_SERIAL(dev);
-
-memory_region_init_io(s-iomem, OBJECT(s), imx_serial_ops, s,
- imx-serial, 0x1000);
-sysbus_init_mmio(dev, s-iomem);
-sysbus_init_irq(dev, s-irq);
-
if (s-chr) {
qemu_chr_add_handlers(s-chr, imx_can_receive, imx_receive,
imx_event, s);
@@ -323,8 +317,17 @@ static int imx_serial_init(SysBusDevice *dev)
DPRINTF(No char dev for uart at 0x%lx\n,
(unsigned long)s-iomem.ram_addr);
}
+}
+
+static void imx_serial_init(Object *obj)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+IMXSerialState *s = IMX_SERIAL(obj);
-return 0;
+memory_region_init_io(s-iomem, obj, imx_serial_ops, s,
+ TYPE_IMX_SERIAL, 0x1000);
+sysbus_init_mmio(sbd, s-iomem);
+sysbus_init_irq(sbd, s-irq);
}
void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
@@ -361,7 +364,7 @@ void imx_serial_create(int uart, const hwaddr addr,
qemu_irq irq)
}
-static Property imx32_serial_properties[] = {
+static Property imx_serial_properties[] = {
DEFINE_PROP_CHR(chardev, IMXSerialState, chr),
DEFINE_PROP_END_OF_LIST(),
};
@@ -369,21 +372,21 @@ static Property imx32_serial_properties[] = {
static void imx_serial_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
-SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-k-init = imx_serial_init;
+dc-realize = imx_serial_realize;
dc-vmsd = vmstate_imx_serial;
dc-reset = imx_serial_reset_at_boot;
set_bit(DEVICE_CATEGORY_INPUT, dc-categories);
dc-desc = i.MX series UART;
-dc-props = imx32_serial_properties;
+dc-props = imx_serial_properties;
}
static const TypeInfo imx_serial_info = {
-.name = TYPE_IMX_SERIAL,
-.parent = TYPE_SYS_BUS_DEVICE,
-.instance_size = sizeof(IMXSerialState),
-.class_init = imx_serial_class_init,
+.name = TYPE_IMX_SERIAL,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(IMXSerialState),
+.instance_init = imx_serial_init,
+.class_init = imx_serial_class_init,
};
static void imx_serial_register_types(void)
--
1.9.1
[Qemu-devel] [PULL 15/27] i.MX: Split EPIT emulator in a header file and a source file
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
948927cab0c85da9a753c5f6d5501323d5604c8e.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/timer/imx_epit.c | 52 ++---
include/hw/timer/imx_epit.h | 79 +
2 files changed, 82 insertions(+), 49 deletions(-)
create mode 100644 include/hw/timer/imx_epit.h
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index ffefc22..f1f82e9 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -5,23 +5,18 @@
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
* Updated by Peter Chubb
- * Updated by Jean-Christophe Dubois
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
*
* This code is licensed under GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
*/
-#include hw/hw.h
-#include qemu/bitops.h
-#include qemu/timer.h
-#include hw/ptimer.h
-#include hw/sysbus.h
#include hw/arm/imx.h
+#include hw/timer/imx_epit.h
+#include hw/misc/imx_ccm.h
#include qemu/main-loop.h
-#define TYPE_IMX_EPIT imx.epit
-
#define DEBUG_TIMER 0
#if DEBUG_TIMER
@@ -61,30 +56,6 @@ static char const *imx_epit_reg_name(uint32_t reg)
# define IPRINTF(fmt, args...) do {} while (0)
#endif
-#define IMX_EPIT(obj) \
-OBJECT_CHECK(IMXEPITState, (obj), TYPE_IMX_EPIT)
-
-/*
- * EPIT: Enhanced periodic interrupt timer
- */
-
-#define CR_EN (1 0)
-#define CR_ENMOD(1 1)
-#define CR_OCIEN(1 2)
-#define CR_RLD (1 3)
-#define CR_PRESCALE_SHIFT (4)
-#define CR_PRESCALE_MASK (0xfff)
-#define CR_SWR (1 16)
-#define CR_IOVW (1 17)
-#define CR_DBGEN(1 18)
-#define CR_WAITEN (1 19)
-#define CR_DOZEN(1 20)
-#define CR_STOPEN (1 21)
-#define CR_CLKSRC_SHIFT (24)
-#define CR_CLKSRC_MASK (0x3 CR_CLKSRC_SHIFT)
-
-#define EPIT_TIMER_MAX 0XUL
-
/*
* Exact clock frequencies vary from board to board.
* These are typical.
@@ -96,23 +67,6 @@ static const IMXClk imx_epit_clocks[] = {
CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
};
-typedef struct {
-SysBusDevice busdev;
-ptimer_state *timer_reload;
-ptimer_state *timer_cmp;
-MemoryRegion iomem;
-DeviceState *ccm;
-
-uint32_t cr;
-uint32_t sr;
-uint32_t lr;
-uint32_t cmp;
-uint32_t cnt;
-
-uint32_t freq;
-qemu_irq irq;
-} IMXEPITState;
-
/*
* Update interrupt status
*/
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
new file mode 100644
index 000..c5328ae
--- /dev/null
+++ b/include/hw/timer/imx_epit.h
@@ -0,0 +1,79 @@
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (c) 2008 OK Labs
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Peter Chubb
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef IMX_EPIT_H
+#define IMX_EPIT_H
+
+#include hw/sysbus.h
+#include hw/ptimer.h
+
+/*
+ * EPIT: Enhanced periodic interrupt timer
+ */
+
+#define CR_EN (1 0)
+#define CR_ENMOD(1 1)
+#define CR_OCIEN(1 2)
+#define CR_RLD (1 3)
+#define CR_PRESCALE_SHIFT (4)
+#define CR_PRESCALE_MASK (0xfff)
+#define CR_SWR (1 16)
+#define CR_IOVW (1 17)
+#define CR_DBGEN(1 18)
+#define CR_WAITEN (1 19)
+#define CR_DOZEN(1 20)
+#define CR_STOPEN (1 21)
+#define CR_CLKSRC_SHIFT (24)
+#define CR_CLKSRC_MASK (0x3 CR_CLKSRC_SHIFT)
+
+#define EPIT_TIMER_MAX 0XUL
+
+#define TYPE_IMX_EPIT imx.epit
+#define IMX_EPIT(obj) OBJECT_CHECK(IMXEPITState, (obj), TYPE_IMX_EPIT)
+
+typedef struct IMXEPITState{
+/* private */
+SysBusDevice parent_obj;
+
+/* public */
+ptimer_state *timer_reload;
+ptimer_state *timer_cmp;
+
[Qemu-devel] [PULL 20/27] hw/arm/gic: Kill code duplication
From: Pavel Fedin p.fe...@samsung.com
Extracted duplicated initialization code from SW-emulated and KVM GIC
implementations and put into gic_init_irqs_and_mmio()
Signed-off-by: Pavel Fedin p.fe...@samsung.com
Message-id:
8ea5b2781ef39cb5989420987fc73c70e377687d.1438758065.git.p.fe...@samsung.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/intc/arm_gic.c| 64
hw/intc/arm_gic_common.c | 41 +
hw/intc/arm_gic_kvm.c| 28 +-
include/hw/intc/arm_gic_common.h | 3 ++
4 files changed, 64 insertions(+), 72 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 454bfd7..a8c5d19 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -922,12 +922,6 @@ static MemTxResult gic_dist_write(void *opaque, hwaddr
offset, uint64_t data,
}
}
-static const MemoryRegionOps gic_dist_ops = {
-.read_with_attrs = gic_dist_read,
-.write_with_attrs = gic_dist_write,
-.endianness = DEVICE_NATIVE_ENDIAN,
-};
-
static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
uint64_t *data, MemTxAttrs attrs)
{
@@ -1056,10 +1050,17 @@ static MemTxResult gic_do_cpu_write(void *opaque,
hwaddr addr,
return gic_cpu_write(s, id, addr, value, attrs);
}
-static const MemoryRegionOps gic_thiscpu_ops = {
-.read_with_attrs = gic_thiscpu_read,
-.write_with_attrs = gic_thiscpu_write,
-.endianness = DEVICE_NATIVE_ENDIAN,
+static const MemoryRegionOps gic_ops[2] = {
+{
+.read_with_attrs = gic_dist_read,
+.write_with_attrs = gic_dist_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+},
+{
+.read_with_attrs = gic_thiscpu_read,
+.write_with_attrs = gic_thiscpu_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+}
};
static const MemoryRegionOps gic_cpu_ops = {
@@ -1068,31 +1069,10 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+/* This function is used by nvic model */
void gic_init_irqs_and_distributor(GICState *s)
{
-SysBusDevice *sbd = SYS_BUS_DEVICE(s);
-int i;
-
-i = s-num_irq - GIC_INTERNAL;
-/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
- * GPIO array layout is thus:
- * [0..N-1] SPIs
- * [N..N+31] PPIs for CPU 0
- * [N+32..N+63] PPIs for CPU 1
- * ...
- */
-if (s-revision != REV_NVIC) {
-i += (GIC_INTERNAL * s-num_cpu);
-}
-qdev_init_gpio_in(DEVICE(s), gic_set_irq, i);
-for (i = 0; i NUM_CPU(s); i++) {
-sysbus_init_irq(sbd, s-parent_irq[i]);
-}
-for (i = 0; i NUM_CPU(s); i++) {
-sysbus_init_irq(sbd, s-parent_fiq[i]);
-}
-memory_region_init_io(s-iomem, OBJECT(s), gic_dist_ops, s,
- gic_dist, 0x1000);
+gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
}
static void arm_gic_realize(DeviceState *dev, Error **errp)
@@ -1110,28 +1090,22 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
return;
}
-gic_init_irqs_and_distributor(s);
+/* This creates distributor and main CPU interface (s-cpuiomem[0]) */
+gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
-/* Memory regions for the CPU interfaces (NVIC doesn't have these):
- * a region for CPU interface for this core, then a region for
- * CPU interface for core 0, for core 1, ...
+/* Extra core-specific regions for the CPU interfaces. This is
+ * necessary for franken-GIC implementations, for example on
+ * Exynos 4.
* NB that the memory region size of 0x100 applies for the 11MPCore
* and also cores following the GIC v1 spec (ie A9).
* GIC v2 defines a larger memory region (0x1000) so this will need
* to be extended when we implement A15.
*/
-memory_region_init_io(s-cpuiomem[0], OBJECT(s), gic_thiscpu_ops, s,
- gic_cpu, 0x100);
for (i = 0; i NUM_CPU(s); i++) {
s-backref[i] = s;
memory_region_init_io(s-cpuiomem[i+1], OBJECT(s), gic_cpu_ops,
s-backref[i], gic_cpu, 0x100);
-}
-/* Distributor */
-sysbus_init_mmio(sbd, s-iomem);
-/* cpu interfaces (one for current cpu plus one per cpu) */
-for (i = 0; i = NUM_CPU(s); i++) {
-sysbus_init_mmio(sbd, s-cpuiomem[i]);
+sysbus_init_mmio(sbd, s-cpuiomem[i+1]);
}
}
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index a64d071..fe64b51 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -84,6 +84,47 @@ static const VMStateDescription vmstate_gic = {
}
};
+void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
+const MemoryRegionOps *ops)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+int i = s-num_irq - GIC_INTERNAL;
+
+
[Qemu-devel] [PULL 27/27] i.MX: Fix UART driver to work with unitialized chardev device
From: Jean-Christophe Dubois j...@tribudubois.net
The chardev property initialization might have failed (for example because
there are not enough chardevs provided by QEMU).
The serial device emulator needs to be able to work with an uninitialized
(NULL) chardev device pointer.
This patch adds some missing tests on the chr pointer value before
using it.
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id: 1438342461-18967-1-git-send-email-...@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/char/imx_serial.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index f9da59f..801156d 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -125,7 +125,9 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
s-usr2 = ~USR2_RDR;
s-uts1 |= UTS1_RXEMPTY;
imx_update(s);
-qemu_chr_accept_input(s-chr);
+if (s-chr) {
+qemu_chr_accept_input(s-chr);
+}
}
return c;
@@ -212,7 +214,9 @@ static void imx_serial_write(void *opaque, hwaddr offset,
}
if (value UCR2_RXEN) {
if (!(s-ucr2 UCR2_RXEN)) {
-qemu_chr_accept_input(s-chr);
+if (s-chr) {
+qemu_chr_accept_input(s-chr);
+}
}
}
s-ucr2 = value 0x;
--
1.9.1
[Qemu-devel] [PATCH 3/5] Init page sizes in qtest
From: Dr. David Alan Gilbert dgilb...@redhat.com One of my patches used a loop that was based on host page size; it dies in qtest since qtest hadn't bothered init'ing it. Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com Reviewed-by: Juan Quintela quint...@redhat.com Reviewed-by: Amit Shah amit.s...@redhat.com --- qtest.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qtest.c b/qtest.c index 05cefd2..8e10340 100644 --- a/qtest.c +++ b/qtest.c @@ -657,6 +657,7 @@ void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp) inbuf = g_string_new(); qtest_chr = chr; +page_size_init(); } bool qtest_driver(void) -- 2.4.3
[Qemu-devel] [PULL 05/27] target-arm: Add the Hypervisor timer
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1436791864-4582-6-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 3 ++-
target-arm/helper.c | 68
4 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 3cbc4a0..54db337 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -224,6 +224,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf,
int reg);
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
+void arm_gt_htimer_cb(void *opaque);
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 8b4323d..3525348 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -453,6 +453,8 @@ static void arm_cpu_initfn(Object *obj)
arm_gt_ptimer_cb, cpu);
cpu-gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_vtimer_cb, cpu);
+cpu-gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
+arm_gt_htimer_cb, cpu);
qdev_init_gpio_out(DEVICE(cpu), cpu-gt_timer_outputs,
ARRAY_SIZE(cpu-gt_timer_outputs));
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ea41052..7346c5f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -113,7 +113,8 @@ typedef struct ARMGenericTimer {
#define GTIMER_PHYS 0
#define GTIMER_VIRT 1
-#define NUM_GTIMERS 2
+#define GTIMER_HYP 2
+#define NUM_GTIMERS 3
typedef struct {
uint64_t raw_tcr;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0dcc0ec..4a7dd24 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1392,6 +1392,34 @@ static void gt_cntvoff_write(CPUARMState *env, const
ARMCPRegInfo *ri,
gt_recalc_timer(cpu, GTIMER_VIRT);
}
+static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+gt_timer_reset(env, ri, GTIMER_HYP);
+}
+
+static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_cval_write(env, ri, GTIMER_HYP, value);
+}
+
+static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+return gt_tval_read(env, ri, GTIMER_HYP);
+}
+
+static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_tval_write(env, ri, GTIMER_HYP, value);
+}
+
+static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_ctl_write(env, ri, GTIMER_HYP, value);
+}
+
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
@@ -1406,6 +1434,13 @@ void arm_gt_vtimer_cb(void *opaque)
gt_recalc_timer(cpu, GTIMER_VIRT);
}
+void arm_gt_htimer_cb(void *opaque)
+{
+ARMCPU *cpu = opaque;
+
+gt_recalc_timer(cpu, GTIMER_HYP);
+}
+
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Note that CNTFRQ is purely reads-as-written for the benefit
* of software; writing it doesn't actually change the timer frequency.
@@ -2711,6 +2746,18 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = CNTVOFF, .cp = 15, .opc1 = 4, .crm = 14,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
.resetvalue = 0 },
+{ .name = CNTHP_CVAL_EL2, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = CNTHP_CVAL, .cp = 15, .opc1 = 6, .crm = 14,
+ .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
+ .resetvalue = 0 },
+{ .name = CNTHP_TVAL_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+{ .name = CNTHP_CTL_EL2, .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -2840,6 +2887,27 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
.writefn = gt_cntvoff_write,
.fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
+{ .name = CNTHP_CVAL_EL2, .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
+ .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
+ .type =
[Qemu-devel] [PATCH v9 4/5] hw/intc: Initial implementation of vGICv3
This is the initial version of KVM-accelerated GICv3 support.
State load and save are not yet supported, live migration is
not possible.
In order to get correct class name in a simpler way, gicv3_class_name()
function is implemented, similar to gic_class_name().
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_kvm.c | 149
target-arm/kvm_arm.h| 10
target-arm/machine.c| 18 ++
4 files changed, 178 insertions(+)
create mode 100644 hw/intc/arm_gicv3_kvm.c
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 1317e5a..004b0c2 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -17,6 +17,7 @@ common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
+obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
new file mode 100644
index 000..8070a2a
--- /dev/null
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -0,0 +1,149 @@
+/*
+ * ARM Generic Interrupt Controller using KVM in-kernel support
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Written by Pavel Fedin
+ * Based on vGICv2 code by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+
+#include hw/intc/arm_gicv3_common.h
+#include hw/sysbus.h
+#include sysemu/kvm.h
+#include kvm_arm.h
+#include vgic_common.h
+
+#ifdef DEBUG_GICV3_KVM
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, kvm_gicv3: fmt, ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do { } while (0)
+#endif
+
+#define TYPE_KVM_ARM_GICV3 kvm-arm-gicv3
+#define KVM_ARM_GICV3(obj) \
+ OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3)
+#define KVM_ARM_GICV3_CLASS(klass) \
+ OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3)
+#define KVM_ARM_GICV3_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
+
+typedef struct KVMARMGICv3Class {
+ARMGICv3CommonClass parent_class;
+DeviceRealize parent_realize;
+void (*parent_reset)(DeviceState *dev);
+} KVMARMGICv3Class;
+
+static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
+{
+GICv3State *s = (GICv3State *)opaque;
+
+kvm_arm_gic_set_irq(s-num_irq, irq, level);
+}
+
+static void kvm_arm_gicv3_put(GICv3State *s)
+{
+/* TODO */
+DPRINTF(Cannot put kernel gic state, no kernel interface\n);
+}
+
+static void kvm_arm_gicv3_get(GICv3State *s)
+{
+/* TODO */
+DPRINTF(Cannot get kernel gic state, no kernel interface\n);
+}
+
+static void kvm_arm_gicv3_reset(DeviceState *dev)
+{
+GICv3State *s = ARM_GICV3_COMMON(dev);
+KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
+
+DPRINTF(Reset\n);
+
+kgc-parent_reset(dev);
+kvm_arm_gicv3_put(s);
+}
+
+static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
+{
+GICv3State *s = KVM_ARM_GICV3(dev);
+KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
+Error *local_err = NULL;
+
+DPRINTF(kvm_arm_gicv3_realize\n);
+
+kgc-parent_realize(dev, local_err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+
+if (s-security_extn) {
+error_setg(errp, the in-kernel VGICv3 does not implement the
+ security extensions);
+return;
+}
+
+gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
+
+/* Try to create the device via the device control API */
+s-dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
+if (s-dev_fd 0) {
+error_setg_errno(errp, -s-dev_fd, error creating in-kernel VGIC);
+return;
+}
+
+kvm_gic_access(s-dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS,
+ 0, 0, s-num_irq, 1);
+
+/* Tell the kernel to complete VGIC initialization now */
+kvm_gic_access(s-dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
+ KVM_DEV_ARM_VGIC_CTRL_INIT, 0, 0, 1);
+
+kvm_arm_register_device(s-iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR,
+KVM_VGIC_V3_ADDR_TYPE_DIST, s-dev_fd);
+
Re: [Qemu-devel] [PATCH v6 1/2] vhost-user: add multi queue support
On Wed, Aug 12, 2015 at 02:25:41PM +0800, Ouyang Changchun wrote:
Based on patch by Nikolay Nikolaev:
Vhost-user will implement the multi queue support in a similar way
to what vhost already has - a separate thread for each queue.
To enable the multi queue functionality - a new command line parameter
queues is introduced for the vhost-user netdev.
The RESET_OWNER change is based on commit:
294ce717e0f212ed0763307f3eab72b4a1bdf4d0
If it is reverted, the patch need update for it accordingly.
Signed-off-by: Nikolay Nikolaev n.nikol...@virtualopensystems.com
Signed-off-by: Changchun Ouyang changchun.ouy...@intel.com
---
Changes since v5:
- fix the message descption for VHOST_RESET_OWNER in vhost-user txt
Changes since v4:
- remove the unnecessary trailing '\n'
Changes since v3:
- fix one typo and wrap one long line
Changes since v2:
- fix vq index issue for set_vring_call
When it is the case of VHOST_SET_VRING_CALL, The vq_index is not
initialized before it is used,
thus it could be a random value. The random value leads to crash in vhost
after passing down
to vhost, as vhost use this random value to index an array index.
- fix the typo in the doc and description
- address vq index for reset_owner
Changes since v1:
- use s-nc.info_str when bringing up/down the backend
docs/specs/vhost-user.txt | 7 ++-
hw/net/vhost_net.c| 3 ++-
hw/virtio/vhost-user.c| 11 ++-
net/vhost-user.c | 37 -
qapi-schema.json | 6 +-
qemu-options.hx | 5 +++--
6 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/docs/specs/vhost-user.txt b/docs/specs/vhost-user.txt
index 70da3b1..9390f89 100644
--- a/docs/specs/vhost-user.txt
+++ b/docs/specs/vhost-user.txt
@@ -135,6 +135,11 @@ As older slaves don't support negotiating protocol
features,
a feature bit was dedicated for this purpose:
#define VHOST_USER_F_PROTOCOL_FEATURES 30
+Multi queue support
+---
+The protocol supports multiple queues by setting all index fields in the sent
+messages to a properly calculated value.
+
Message types
-
@@ -198,7 +203,7 @@ Message types
Id: 4
Equivalent ioctl: VHOST_RESET_OWNER
- Master payload: N/A
+ Master payload: vring state description
Issued when a new connection is about to be closed. The Master will no
longer own this connection (and will usually close it).
This is an interface change, isn't it?
We can't make it unconditionally, need to make it dependent
on a protocol flag.
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index 1f25cb3..9cd6c05 100644
--- a/hw/net/vhost_net.c
+++ b/hw/net/vhost_net.c
@@ -159,6 +159,7 @@ struct vhost_net *vhost_net_init(VhostNetOptions *options)
net-dev.nvqs = 2;
net-dev.vqs = net-vqs;
+net-dev.vq_index = net-nc-queue_index;
r = vhost_dev_init(net-dev, options-opaque,
options-backend_type, options-force);
@@ -269,7 +270,7 @@ static void vhost_net_stop_one(struct vhost_net *net,
for (file.index = 0; file.index net-dev.nvqs; ++file.index) {
const VhostOps *vhost_ops = net-dev.vhost_ops;
int r = vhost_ops-vhost_call(net-dev, VHOST_RESET_OWNER,
- NULL);
+ file);
assert(r = 0);
}
}
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 27ba035..fb11d4c 100644
--- a/hw/virtio/vhost-user.c
+++ b/hw/virtio/vhost-user.c
@@ -219,7 +219,12 @@ static int vhost_user_call(struct vhost_dev *dev,
unsigned long int request,
break;
case VHOST_USER_SET_OWNER:
+break;
+
case VHOST_USER_RESET_OWNER:
+memcpy(msg.state, arg, sizeof(struct vhost_vring_state));
+msg.state.index += dev-vq_index;
+msg.size = sizeof(m.state);
break;
case VHOST_USER_SET_MEM_TABLE:
@@ -262,17 +267,20 @@ static int vhost_user_call(struct vhost_dev *dev,
unsigned long int request,
case VHOST_USER_SET_VRING_NUM:
case VHOST_USER_SET_VRING_BASE:
memcpy(msg.state, arg, sizeof(struct vhost_vring_state));
+msg.state.index += dev-vq_index;
msg.size = sizeof(m.state);
break;
case VHOST_USER_GET_VRING_BASE:
memcpy(msg.state, arg, sizeof(struct vhost_vring_state));
+msg.state.index += dev-vq_index;
msg.size = sizeof(m.state);
need_reply = 1;
break;
case VHOST_USER_SET_VRING_ADDR:
memcpy(msg.addr, arg, sizeof(struct vhost_vring_addr));
+msg.addr.index += dev-vq_index;
msg.size = sizeof(m.addr);
break;
@@ -280,7 +288,7 @@ static int vhost_user_call(struct vhost_dev *dev,
unsigned long int request,
case
[Qemu-devel] [PULL 10/27] i.MX:Fix Coding style for UART emulator.
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
23ab872b7cd30b1399384fb26a2ebb75e9761d7b.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/char/imx_serial.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index f0ed255..f9da59f 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -26,7 +26,7 @@
//#define DEBUG_SERIAL 1
#ifdef DEBUG_SERIAL
#define DPRINTF(fmt, args...) \
-do { printf(imx_serial: fmt , ##args); } while (0)
+do { printf(%s: fmt , TYPE_IMX_SERIAL, ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif
@@ -38,13 +38,13 @@ do { printf(imx_serial: fmt , ##args); } while (0)
//#define DEBUG_IMPLEMENTATION 1
#ifdef DEBUG_IMPLEMENTATION
# define IPRINTF(fmt, args...) \
-do { fprintf(stderr, imx_serial: fmt, ##args); } while (0)
+do { fprintf(stderr, %s: fmt, TYPE_IMX_SERIAL, ##args); } while (0)
#else
# define IPRINTF(fmt, args...) do {} while (0)
#endif
static const VMStateDescription vmstate_imx_serial = {
-.name = imx-serial,
+.name = TYPE_IMX_SERIAL,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
@@ -164,13 +164,13 @@ static uint64_t imx_serial_read(void *opaque, hwaddr
offset,
return 0x0; /* TODO */
default:
-IPRINTF(imx_serial_read: bad offset: 0x%x\n, (int)offset);
+IPRINTF(%s: bad offset: 0x%x\n, __func__, (int)offset);
return 0;
}
}
static void imx_serial_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
+ uint64_t value, unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
unsigned char ch;
@@ -220,25 +220,25 @@ static void imx_serial_write(void *opaque, hwaddr offset,
case 0x25: /* USR1 */
value = USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
-USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
+ USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
s-usr1 = ~value;
break;
case 0x26: /* USR2 */
- /*
-* Writing 1 to some bits clears them; all other
-* values are ignored
-*/
+/*
+ * Writing 1 to some bits clears them; all other
+ * values are ignored
+ */
value = USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
-USR2_RIDELT | USR2_IRINT | USR2_WAKE |
-USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
+ USR2_RIDELT | USR2_IRINT | USR2_WAKE |
+ USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
s-usr2 = ~value;
break;
-/*
- * Linux expects to see what it writes to these registers
- * We don't currently alter the baud rate
- */
+/*
+ * Linux expects to see what it writes to these registers
+ * We don't currently alter the baud rate
+ */
case 0x29: /* UBIR */
s-ubrc = value 0x;
break;
@@ -266,7 +266,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
break;
default:
-IPRINTF(imx_serial_write: Bad offset 0x%x\n, (int)offset);
+IPRINTF(%s: Bad offset 0x%x\n, __func__, (int)offset);
}
}
--
1.9.1
[Qemu-devel] [PULL 08/27] i.MX: Split UART emulator in a header file and a source file
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
a51ef50fa222a614169056d5389a6d3ed6a63b04.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/char/imx_serial.c | 82 +-
include/hw/char/imx_serial.h | 102 +++
2 files changed, 104 insertions(+), 80 deletions(-)
create mode 100644 include/hw/char/imx_serial.h
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index f3fbc77..1dcb325 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -4,6 +4,7 @@
* Copyright (c) 2008 OKL
* Originally Written by Hans Jiang
* Copyright (c) 2011 NICTA Pty Ltd.
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -17,8 +18,7 @@
* is a real serial device.
*/
-#include hw/hw.h
-#include hw/sysbus.h
+#include hw/char/imx_serial.h
#include sysemu/sysemu.h
#include sysemu/char.h
#include hw/arm/imx.h
@@ -43,35 +43,6 @@ do { printf(imx_serial: fmt , ##args); } while (0)
# define IPRINTF(fmt, args...) do {} while (0)
#endif
-#define TYPE_IMX_SERIAL imx-serial
-#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
-
-typedef struct IMXSerialState {
-SysBusDevice parent_obj;
-
-MemoryRegion iomem;
-int32_t readbuff;
-
-uint32_t usr1;
-uint32_t usr2;
-uint32_t ucr1;
-uint32_t ucr2;
-uint32_t uts1;
-
-/*
- * The registers below are implemented just so that the
- * guest OS sees what it has written
- */
-uint32_t onems;
-uint32_t ufcr;
-uint32_t ubmr;
-uint32_t ubrc;
-uint32_t ucr3;
-
-qemu_irq irq;
-CharDriverState *chr;
-} IMXSerialState;
-
static const VMStateDescription vmstate_imx_serial = {
.name = imx-serial,
.version_id = 1,
@@ -91,55 +62,6 @@ static const VMStateDescription vmstate_imx_serial = {
},
};
-
-#define URXD_CHARRDY(115) /* character read is valid */
-#define URXD_ERR(114) /* Character has error */
-#define URXD_BRK(111) /* Break received */
-
-#define USR1_PARTYER(115) /* Parity Error */
-#define USR1_RTSS (114) /* RTS pin status */
-#define USR1_TRDY (113) /* Tx ready */
-#define USR1_RTSD (112) /* RTS delta: pin changed state */
-#define USR1_ESCF (111) /* Escape sequence interrupt */
-#define USR1_FRAMERR(110) /* Framing error */
-#define USR1_RRDY (19)/* receiver ready */
-#define USR1_AGTIM (18)/* Aging timer interrupt */
-#define USR1_DTRD (17)/* DTR changed */
-#define USR1_RXDS (16)/* Receiver is idle */
-#define USR1_AIRINT (15)/* Aysnch IR interrupt */
-#define USR1_AWAKE (14)/* Falling edge detected on RXd pin */
-
-#define USR2_ADET (115) /* Autobaud complete */
-#define USR2_TXFE (114) /* Transmit FIFO empty */
-#define USR2_DTRF (113) /* DTR/DSR transition */
-#define USR2_IDLE (112) /* UART has been idle for too long */
-#define USR2_ACST (111) /* Autobaud counter stopped */
-#define USR2_RIDELT (110) /* Ring Indicator delta */
-#define USR2_RIIN (19)/* Ring Indicator Input */
-#define USR2_IRINT (18)/* Serial Infrared Interrupt */
-#define USR2_WAKE (17)/* Start bit detected */
-#define USR2_DCDDELT(16)/* Data Carrier Detect delta */
-#define USR2_DCDIN (15)/* Data Carrier Detect Input */
-#define USR2_RTSF (14)/* RTS transition */
-#define USR2_TXDC (13)/* Transmission complete */
-#define USR2_BRCD (12)/* Break condition detected */
-#define USR2_ORE(11)/* Overrun error */
-#define USR2_RDR(10)/* Receive data ready */
-
-#define UCR1_TRDYEN (113) /* Tx Ready Interrupt Enable */
-#define UCR1_RRDYEN (19)/* Rx Ready Interrupt Enable */
-#define UCR1_TXMPTYEN (16)/* Tx Empty Interrupt Enable */
-#define UCR1_UARTEN (10)/* UART Enable */
-
-#define UCR2_TXEN (12)/* Transmitter enable */
-#define UCR2_RXEN (11)/* Receiver enable */
-#define UCR2_SRST (10)/* Reset complete */
-
-#define UTS1_TXEMPTY(16)
-#define UTS1_RXEMPTY(15)
-#define UTS1_TXFULL (14)
-#define UTS1_RXFULL (13)
-
static void imx_update(IMXSerialState *s)
{
uint32_t flags;
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
new file mode 100644
index 000..6cd75c0
--- /dev/null
+++ b/include/hw/char/imx_serial.h
@@ -0,0 +1,102 @@
+/*
+ * Device model for i.MX UART
+ *
+ * Copyright (c) 2008 OKL
+ * Originally Written by Hans Jiang
+ * Copyright (c) 2011 NICTA Pty Ltd.
+ * Updated by Jean-Christophe Dubois
[Qemu-devel] [PULL 07/27] hw/arm/virt: Connect the Hypervisor timer
From: Edgar E. Iglesias edgar.igles...@xilinx.com Reviewed-by: Peter Maydell peter.mayd...@linaro.org Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com Message-id: 1436791864-4582-8-git-send-email-edgar.igles...@gmail.com Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- hw/arm/virt.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 42efad1..aab99f7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -402,6 +402,10 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) qdev_connect_gpio_out(cpudev, 1, qdev_get_gpio_in(gicdev, ppibase + ARCH_TIMER_VIRT_IRQ)); +/* Hypervisor timer. */ +qdev_connect_gpio_out(cpudev, 2, + qdev_get_gpio_in(gicdev, + ppibase + ARCH_TIMER_NS_EL2_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, -- 1.9.1
[Qemu-devel] [PULL 14/27] i.MX: Fix Coding style for CCM emulator
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
ff0b6720b1c55204e663f07be47c0203f6871084.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/misc/imx_ccm.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
index 2e9bd9c..2e19dbb 100644
--- a/hw/misc/imx_ccm.c
+++ b/hw/misc/imx_ccm.c
@@ -16,11 +16,10 @@
#define CKIH_FREQ 2600 /* 26MHz crystal input */
#define CKIL_FREQ32768 /* nominal 32khz clock */
-
//#define DEBUG_CCM 1
#ifdef DEBUG_CCM
#define DPRINTF(fmt, args...) \
-do { printf(imx_ccm: fmt , ##args); } while (0)
+do { printf(%s: fmt , TYPE_IMX_CCM, ##args); } while (0)
#else
#define DPRINTF(fmt, args...) do {} while (0)
#endif
@@ -28,7 +27,7 @@ do { printf(imx_ccm: fmt , ##args); } while (0)
static int imx_ccm_post_load(void *opaque, int version_id);
static const VMStateDescription vmstate_imx_ccm = {
-.name = imx-ccm,
+.name = TYPE_IMX_CCM,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
@@ -110,7 +109,7 @@ static void update_clocks(IMXCCMState *s)
s-hsp_clk_freq = s-mcu_clk_freq / (1 + EXTRACT(s-pdr0, HSP));
s-ipg_clk_freq = s-hsp_clk_freq / (1 + EXTRACT(s-pdr0, IPG));
-DPRINTF(Clocks: mcu %uMHz, HSP %uMHz, IPG %uHz\n,
+DPRINTF(%s: mcu %uMHz, HSP %uMHz, IPG %uHz\n, __func__,
s-mcu_clk_freq / 100,
s-hsp_clk_freq / 100,
s-ipg_clk_freq);
@@ -136,7 +135,7 @@ static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
{
IMXCCMState *s = (IMXCCMState *)opaque;
-DPRINTF(read(offset=%x), offset 2);
+DPRINTF(%s(offset=%x), __func__, offset 2);
switch (offset 2) {
case 0: /* CCMR */
DPRINTF( ccmr = 0x%x\n, s-ccmr);
@@ -177,7 +176,7 @@ static void imx_ccm_write(void *opaque, hwaddr offset,
{
IMXCCMState *s = (IMXCCMState *)opaque;
-DPRINTF(write(offset=%x, value = %x)\n,
+DPRINTF(%s(offset=%x, value = %x)\n, __func__,
offset 2, (unsigned int)value);
switch (offset 2) {
case 0:
--
1.9.1
[Qemu-devel] [PATCH 1/5] migration/ram.c: Use RAMBlock rather than MemoryRegion
From: Dr. David Alan Gilbert dgilb...@redhat.com
RAM migration mainly works on RAMBlocks but in a few places
uses data from MemoryRegions to access the same information that's
already held in RAMBlocks; clean it up just to avoid the
MemoryRegion use.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
migration/ram.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 7f007e6..7df9157 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -497,13 +497,13 @@ static int save_xbzrle_page(QEMUFile *f, uint8_t
**current_data,
/* Called with rcu_read_lock() to protect migration_bitmap */
static inline
-ram_addr_t migration_bitmap_find_and_reset_dirty(MemoryRegion *mr,
+ram_addr_t migration_bitmap_find_and_reset_dirty(RAMBlock *rb,
ram_addr_t start)
{
-unsigned long base = mr-ram_addr TARGET_PAGE_BITS;
+unsigned long base = rb-offset TARGET_PAGE_BITS;
unsigned long nr = base + (start TARGET_PAGE_BITS);
-uint64_t mr_size = TARGET_PAGE_ALIGN(memory_region_size(mr));
-unsigned long size = base + (mr_size TARGET_PAGE_BITS);
+uint64_t rb_size = rb-used_length;
+unsigned long size = base + (rb_size TARGET_PAGE_BITS);
unsigned long *bitmap;
unsigned long next;
@@ -573,7 +573,7 @@ static void migration_bitmap_sync(void)
qemu_mutex_lock(migration_bitmap_mutex);
rcu_read_lock();
QLIST_FOREACH_RCU(block, ram_list.blocks, next) {
-migration_bitmap_sync_range(block-mr-ram_addr, block-used_length);
+migration_bitmap_sync_range(block-offset, block-used_length);
}
rcu_read_unlock();
qemu_mutex_unlock(migration_bitmap_mutex);
@@ -668,12 +668,11 @@ static int ram_save_page(QEMUFile *f, RAMBlock* block,
ram_addr_t offset,
int pages = -1;
uint64_t bytes_xmit;
ram_addr_t current_addr;
-MemoryRegion *mr = block-mr;
uint8_t *p;
int ret;
bool send_async = true;
-p = memory_region_get_ram_ptr(mr) + offset;
+p = block-host + offset;
/* In doubt sent page as normal */
bytes_xmit = 0;
@@ -744,7 +743,7 @@ static int do_compress_ram_page(CompressParam *param)
RAMBlock *block = param-block;
ram_addr_t offset = param-offset;
-p = memory_region_get_ram_ptr(block-mr) + (offset TARGET_PAGE_MASK);
+p = block-host + (offset TARGET_PAGE_MASK);
bytes_sent = save_page_header(param-file, block, offset |
RAM_SAVE_FLAG_COMPRESS_PAGE);
@@ -852,11 +851,10 @@ static int ram_save_compressed_page(QEMUFile *f, RAMBlock
*block,
{
int pages = -1;
uint64_t bytes_xmit;
-MemoryRegion *mr = block-mr;
uint8_t *p;
int ret;
-p = memory_region_get_ram_ptr(mr) + offset;
+p = block-host + offset;
bytes_xmit = 0;
ret = ram_control_save_page(f, block-offset,
@@ -929,14 +927,12 @@ static int ram_find_and_save_block(QEMUFile *f, bool
last_stage,
ram_addr_t offset = last_offset;
bool complete_round = false;
int pages = 0;
-MemoryRegion *mr;
if (!block)
block = QLIST_FIRST_RCU(ram_list.blocks);
while (true) {
-mr = block-mr;
-offset = migration_bitmap_find_and_reset_dirty(mr, offset);
+offset = migration_bitmap_find_and_reset_dirty(block, offset);
if (complete_round block == last_seen_block
offset = last_offset) {
break;
@@ -1344,7 +1340,7 @@ static inline void *host_from_stream_offset(QEMUFile *f,
return NULL;
}
-return memory_region_get_ram_ptr(block-mr) + offset;
+return block-host + offset;
}
len = qemu_get_byte(f);
@@ -1354,7 +1350,7 @@ static inline void *host_from_stream_offset(QEMUFile *f,
QLIST_FOREACH_RCU(block, ram_list.blocks, next) {
if (!strncmp(id, block-idstr, sizeof(id))
block-max_length offset) {
-return memory_region_get_ram_ptr(block-mr) + offset;
+return block-host + offset;
}
}
--
2.4.3
Re: [Qemu-devel] [PULL 00/20] SCSI, build, TCG, RCU, misc patches for 2015-08-12
On 12 August 2015 at 14:36, Paolo Bonzini pbonz...@redhat.com wrote: The following changes since commit cb48f67ad8c7b33c617d4f8144a27706e69fd688: bsd-user: Fix operand to cpu_x86_exec (2015-07-30 12:38:49 +0100) are available in the git repository at: git://github.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 70c6c8bdc7c91bb111710156e1eee7bbe769985f: disas: Defeature print_target_address (2015-08-12 15:32:57 +0200) * SCSI fixes from Stefan and Fam * vhost-scsi fix from Igor and Lu Lina * a build system fix from Daniel * two more multi-arch-related patches from Peter C. * TCG patches from myself and Sergey Fedorov * RCU improvement from Wen Congyang * a few more simple cleanups This fails to configure for me: config-host.mak is out-of-date, running configure ../../configure: 2789: local: -I/usr/include/glib-2.0: bad variable name line 2789 is local probe_cflags=$($pkg_config --cflags $1) 'local' isn't part of POSIX shell. It is supported by 'dash', but only in the form 'local varname ...', not the bash-specific 'local varname=value ...' form. We do use 'local' in a couple of places in configure already, but it would probably be better to avoid it entirely. thanks -- PMM
Re: [Qemu-devel] [PULL 00/20] SCSI, build, TCG, RCU, misc patches for 2015-08-12
On 13 August 2015 at 10:37, Paolo Bonzini pbonz...@redhat.com wrote: On 13/08/2015 11:28, Peter Maydell wrote: config-host.mak is out-of-date, running configure ../../configure: 2789: local: -I/usr/include/glib-2.0: bad variable name line 2789 is local probe_cflags=$($pkg_config --cflags $1) 'local' isn't part of POSIX shell. It is supported by 'dash', but only in the form 'local varname ...', not the bash-specific 'local varname=value ...' form. This is not entirely correct; dash is clearly supporting assignments in local as well; we have: local compiler=$1 The dash manpage doesn't document that it supports var=value. https://wiki.ubuntu.com/DashAsBinSh#local suggests that it's probably safest to just have 'local' do the declaration part only and one variable per line, though. But we have a lot of places in configure which avoid local and instead have variables named 'local_foo' too. -- PMM
[Qemu-devel] [PATCH 5/5] migration: qemu-file more size_t'ifying
From: Dr. David Alan Gilbert dgilb...@redhat.com
This time convert the external functions:
qemu_get_buffer, qemu_peek_buffer
qemu_put_buffer and qemu_put_buffer_async
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
include/migration/qemu-file.h | 10 +-
migration/qemu-file.c | 22 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index e1e2bab..29a338d 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -126,13 +126,13 @@ int qemu_get_fd(QEMUFile *f);
int qemu_fclose(QEMUFile *f);
int64_t qemu_ftell(QEMUFile *f);
int64_t qemu_ftell_fast(QEMUFile *f);
-void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
+void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, size_t size);
void qemu_put_byte(QEMUFile *f, int v);
/*
* put_buffer without copying the buffer.
* The buffer should be available till it is sent asynchronously.
*/
-void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size);
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, size_t size);
bool qemu_file_mode_is_not_valid(const char *mode);
bool qemu_file_is_writable(QEMUFile *f);
@@ -161,8 +161,8 @@ static inline void qemu_put_ubyte(QEMUFile *f, unsigned int
v)
void qemu_put_be16(QEMUFile *f, unsigned int v);
void qemu_put_be32(QEMUFile *f, unsigned int v);
void qemu_put_be64(QEMUFile *f, uint64_t v);
-int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int size, size_t offset);
-int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
+size_t qemu_peek_buffer(QEMUFile *f, uint8_t **buf, size_t size, size_t
offset);
+size_t qemu_get_buffer(QEMUFile *f, uint8_t *buf, size_t size);
ssize_t qemu_put_compression_data(QEMUFile *f, const uint8_t *p, size_t size,
int level);
int qemu_put_qemu_file(QEMUFile *f_des, QEMUFile *f_src);
@@ -237,7 +237,7 @@ static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
}
// Signed versions for type safety
-static inline void qemu_put_sbuffer(QEMUFile *f, const int8_t *buf, int size)
+static inline void qemu_put_sbuffer(QEMUFile *f, const int8_t *buf, size_t
size)
{
qemu_put_buffer(f, (const uint8_t *)buf, size);
}
diff --git a/migration/qemu-file.c b/migration/qemu-file.c
index 6bb3dc1..b273b1a 100644
--- a/migration/qemu-file.c
+++ b/migration/qemu-file.c
@@ -270,7 +270,7 @@ int qemu_fclose(QEMUFile *f)
return ret;
}
-static void add_to_iovec(QEMUFile *f, const uint8_t *buf, int size)
+static void add_to_iovec(QEMUFile *f, const uint8_t *buf, size_t size)
{
/* check for adjacent buffer and coalesce them */
if (f-iovcnt 0 buf == f-iov[f-iovcnt - 1].iov_base +
@@ -286,7 +286,7 @@ static void add_to_iovec(QEMUFile *f, const uint8_t *buf,
int size)
}
}
-void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size)
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, size_t size)
{
if (!f-ops-writev_buffer) {
qemu_put_buffer(f, buf, size);
@@ -301,9 +301,9 @@ void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf,
int size)
add_to_iovec(f, buf, size);
}
-void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size)
+void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, size_t size)
{
-int l;
+size_t l;
if (f-last_error) {
return;
@@ -363,10 +363,10 @@ void qemu_file_skip(QEMUFile *f, int size)
* return as many as it managed to read (assuming blocking fd's which
* all current QEMUFile are)
*/
-int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int size, size_t offset)
+size_t qemu_peek_buffer(QEMUFile *f, uint8_t **buf, size_t size, size_t offset)
{
-int pending;
-int index;
+ssize_t pending;
+size_t index;
assert(!qemu_file_is_writable(f));
assert(offset IO_BUF_SIZE);
@@ -411,13 +411,13 @@ int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int
size, size_t offset)
* return as many as it managed to read (assuming blocking fd's which
* all current QEMUFile are)
*/
-int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size)
+size_t qemu_get_buffer(QEMUFile *f, uint8_t *buf, size_t size)
{
-int pending = size;
-int done = 0;
+size_t pending = size;
+size_t done = 0;
while (pending 0) {
-int res;
+size_t res;
uint8_t *src;
res = qemu_peek_buffer(f, src, MIN(pending, IO_BUF_SIZE), 0);
--
2.4.3
[Qemu-devel] [PULL 25/27] hw/arm/virt: Wire up secure timer interrupt
Wire up the secure timer interrupt. Since we've defined
that the plain old physical timer is the NS timer, we can
drop the now-out-of-date comment about QEMU not having TZ.
Use a data-driven loop to wire up the timer interrupts, since
we now have four of them and the code is the same for each.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1437047249-2357-4-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
hw/arm/virt.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 94694d6..d5a8417 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -391,20 +391,22 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
for (i = 0; i smp_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
-/* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+int irq;
+/* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs we use for the virt board.
*/
-qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL1_IRQ));
-/* virtual timer */
-qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_VIRT_IRQ));
-/* Hypervisor timer. */
-qdev_connect_gpio_out(cpudev, 2,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL2_IRQ));
+const int timer_irq[] = {
+[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
+[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
+[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
+[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
+};
+
+for (irq = 0; irq ARRAY_SIZE(timer_irq); irq++) {
+qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+}
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
--
1.9.1
Re: [Qemu-devel] [PATCH v11 0/5] Update tests/qemu-iotests failing cases for the s390 platform
Max replied that ignoring the UTF-8 error for 130 patch reported by checkpatch.pl is fine. Could you please apply the series if there are no further objections. thanks On 07/03/2015 03:28 PM, Bo Tu wrote: v11. 1. Add Reviewed-by of Sascha 2. Refine code change in common.config in order to be easier to read and be shorter 3. Add more comments in patch description 4. Combine the fix for 041 and 055 in one patch since they address the same issue 5. Remove the fix for 051 since it fails now 6. checkpatch.pl reports invaid UTF-8 error for 130 patch, because 130.out contains some non-text data. v10. 1. Add Reviewed-by statements for test 049 2. Removed the backslash in qemu-option.c 3. Please apply the series if there are no further objections v9. 1.Fix issue of line over 80 characters for test 049 2.Add Reviewed-by statements for test 051,130 v8. 1.Modify error message in qemu-option.c when image size is invalid 2.Remove Reviewed-by statements if any functional changes in a new patch version for test 049,051,130 3.Change patch subject for test 130 4.Add id definition for a drive which will work for all platforms in test 130 5.Disable virtio-scsi-pci for non-PCI systems in test 051 v7. 1. Add a pc specific output file for test 130. 2. A new variable device_id is defined in test 130 to support multiplatform. 3. Update the output file for test 051 based on it's current output. 4. change util/qemu-option.c and test case 049, generate error message when image size is a negtive value or exceeds the maximum of uint64 v6. 1. Change the filter name from _filter_s390 to _filter_orphan. 2. Update the output file for tese case 081 because no default floopy and cd-rom. v5: 1. Add a pc specific output file for test 051. 2. Add a filter to test case 051 to filter s390 specific warnings. 3. Check whether the machine type is pc or not rather than check whether the machine type is s390. 4. When using a machine specific reference file if the default machine has an alias then use the alias as the output file name otherwise use the default machine name as the output file name. v4: 1. Generate all patches based on the latest master branch. 2. Rearrange patches v3: 1. Fix a typo in v2. v2: 1. Drop the patches for test 039 for it has been fixed in upstream. 2. Integrate patches for test 071, 067 and 087. 3. Keep the other patches. v1: 1. updated the test suite to be default-machine-type-aware, from the previous platform-aware 2. created a new patch qemu-iotests: run qemu with -nodefaults to counterpart the impact from the commit: c88930a6866e74953e931ae749781e98e486e5c8 qemu-char: Permit only a single stdio character device When more than one is used, the terminal settings aren't restored correctly on exit. Fixable. However, such usage makes no sense, because the users race for input, so outlaw it instead. If you want to connect multiple things to stdio, use the mux chardev. 3. updated all the checking of platform name to the current machine name Bo Tu (5): qemu-iotests: qemu machine type support qemu-iotests: disable default qemu devices for cross-platform compatibility qemu-iotests: s390x: fix test 041 and 055 qemu-iotests: s390x: fix test 049, reject negative sizes in QemuOpts qemu-iotests: s390x: fix test 130 tests/qemu-iotests/041 | 6 + tests/qemu-iotests/049.out | 10 +- tests/qemu-iotests/055 | 9 ++ tests/qemu-iotests/067 | 8 +- tests/qemu-iotests/067.out | 266 +-- tests/qemu-iotests/071.out | 4 - tests/qemu-iotests/081.out | 2 - tests/qemu-iotests/087.out | 12 -- tests/qemu-iotests/130 | 8 +- tests/qemu-iotests/130.out | 4 +- tests/qemu-iotests/check | 5 + tests/qemu-iotests/common| 1 + tests/qemu-iotests/common.config | 11 +- tests/qemu-iotests/common.qemu | 2 +- tests/qemu-iotests/iotests.py| 1 + util/qemu-option.c | 5 + 16 files changed, 53 insertions(+), 301 deletions(-)
Re: [Qemu-devel] [PATCH v8 5/5] Add gicversion option to virt machine
Hello! I am now finishing v9 and (i hope) i fixed everything except this one. Sorry, too many mails, i occasionally skipped this one earlier. Any particular reason for having two separate VIRT_ITS_* entries? The spec mandates that the two 64K pages of ITS have to be consecutive, so it would make life easier for boards if they were just a single memory region. Yes, there is a reason. It is because of how in-kernel vITS works. It handles only control region. Translation register has to be handled in userspace and writes there need to be converted to KVM_SIGNAL_MSI ioctl. Therefore two regions are more convenient to use. Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia
Re: [Qemu-devel] [RFC PATCH V7 11/19] tcg: switch on multithread.
On 10/08/2015 17:27, fred.kon...@greensocs.com wrote:
+while (!cpu-exit_request) {
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
(cpu-singlestep_enabled SSTEP_NOTIMER) == 0);
@@ -1507,7 +1480,7 @@ static void tcg_exec_all(void)
}
}
-first_cpu-exit_request = 0;
+cpu-exit_request = 0;
One issue here is that when tcg_cpu_exec returns EXCP_HALTED, the
function keeps looping. There is no need to set cpu-exit_request in
that case, since in fact there is no request pending, so the while loop
probably should be an if.
Also, cpu-interrupt_request is not protected by any mutex, so
everything apart from the non-zero test must take the iothread mutex.
Paolo
Re: [Qemu-devel] [PATCH v6 1/2] vhost-user: add multi queue support
On Thu, Aug 13, 2015 at 11:18 AM, Michael S. Tsirkin m...@redhat.com wrote: On Wed, Aug 12, 2015 at 02:25:41PM +0800, Ouyang Changchun wrote: Based on patch by Nikolay Nikolaev: Vhost-user will implement the multi queue support in a similar way to what vhost already has - a separate thread for each queue. To enable the multi queue functionality - a new command line parameter queues is introduced for the vhost-user netdev. The RESET_OWNER change is based on commit: 294ce717e0f212ed0763307f3eab72b4a1bdf4d0 If it is reverted, the patch need update for it accordingly. Signed-off-by: Nikolay Nikolaev n.nikol...@virtualopensystems.com Signed-off-by: Changchun Ouyang changchun.ouy...@intel.com --- Changes since v5: - fix the message descption for VHOST_RESET_OWNER in vhost-user txt Changes since v4: - remove the unnecessary trailing '\n' Changes since v3: - fix one typo and wrap one long line Changes since v2: - fix vq index issue for set_vring_call When it is the case of VHOST_SET_VRING_CALL, The vq_index is not initialized before it is used, thus it could be a random value. The random value leads to crash in vhost after passing down to vhost, as vhost use this random value to index an array index. - fix the typo in the doc and description - address vq index for reset_owner Changes since v1: - use s-nc.info_str when bringing up/down the backend docs/specs/vhost-user.txt | 7 ++- hw/net/vhost_net.c| 3 ++- hw/virtio/vhost-user.c| 11 ++- net/vhost-user.c | 37 - qapi-schema.json | 6 +- qemu-options.hx | 5 +++-- 6 files changed, 50 insertions(+), 19 deletions(-) diff --git a/docs/specs/vhost-user.txt b/docs/specs/vhost-user.txt index 70da3b1..9390f89 100644 --- a/docs/specs/vhost-user.txt +++ b/docs/specs/vhost-user.txt @@ -135,6 +135,11 @@ As older slaves don't support negotiating protocol features, a feature bit was dedicated for this purpose: #define VHOST_USER_F_PROTOCOL_FEATURES 30 +Multi queue support +--- +The protocol supports multiple queues by setting all index fields in the sent +messages to a properly calculated value. + Message types - @@ -198,7 +203,7 @@ Message types Id: 4 Equivalent ioctl: VHOST_RESET_OWNER - Master payload: N/A + Master payload: vring state description Issued when a new connection is about to be closed. The Master will no longer own this connection (and will usually close it). This is an interface change, isn't it? We can't make it unconditionally, need to make it dependent on a protocol flag. Agree. It can potential break vhost-user driver implementation checking the size of the message. We should not change the vhost-user protocol without a new protocol flag. I think the first issue here that VHOST_RESET_OWNER should happen on vhost_dev_cleanup and not in vhost_net_stop_one. VHOST_RESET_OWNER should be the counter part of VHOST_SET_OWNER. So it don't need to have a payload like VHOST_SET_OWNER. Thus I agree with this email (http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg05971.html) Maybe should we use an other message to tell to the backend that the vring is not anymore available in vhost_net_stop_one ? Maxime
[Qemu-devel] [PULL 18/27] i.MX: Fix Coding style for GPT emulator
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
cc7d1589e774e87c346b75a6c25e07957f436ced.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/timer/imx_gpt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index f61d4e5..01f802e 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -70,7 +70,7 @@ static char const *imx_gpt_reg_name(uint32_t reg)
#endif
static const VMStateDescription vmstate_imx_timer_gpt = {
-.name = imx.gpt,
+.name = TYPE_IMX_GPT,
.version_id = 3,
.minimum_version_id = 3,
.fields = (VMStateField[]) {
@@ -107,7 +107,7 @@ static void imx_gpt_set_freq(IMXGPTState *s)
{
uint32_t clksrc = extract32(s-cr, GPT_CR_CLKSRC_SHIFT, 3);
uint32_t freq = imx_clock_frequency(s-ccm, imx_gpt_clocks[clksrc])
-/ (1 + s-pr);
+/ (1 + s-pr);
s-freq = freq;
DPRINTF(Setting clksrc %d to frequency %d\n, clksrc, freq);
@@ -134,7 +134,7 @@ static uint32_t imx_gpt_update_count(IMXGPTState *s)
}
static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
- uint32_t timeout)
+ uint32_t timeout)
{
if ((count reg) (timeout reg)) {
timeout = reg;
--
1.9.1
[Qemu-devel] [PULL 16/27] i.MX: Fix Coding style for EPIT emulator
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Message-id:
d8d70683c6a48ac318c1635595619cfb0eb31681.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/timer/imx_epit.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index f1f82e9..10c5d2b 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -128,9 +128,9 @@ static void imx_epit_reset(DeviceState *dev)
static uint32_t imx_epit_update_count(IMXEPITState *s)
{
- s-cnt = ptimer_get_count(s-timer_reload);
+s-cnt = ptimer_get_count(s-timer_reload);
- return s-cnt;
+return s-cnt;
}
static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
@@ -298,13 +298,13 @@ void imx_timerp_create(const hwaddr addr, qemu_irq irq,
DeviceState *ccm)
}
static const MemoryRegionOps imx_epit_ops = {
- .read = imx_epit_read,
- .write = imx_epit_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+.read = imx_epit_read,
+.write = imx_epit_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_imx_timer_epit = {
-.name = imx.epit,
+.name = TYPE_IMX_EPIT,
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
--
1.9.1
[Qemu-devel] [PULL 22/27] target-arm: Add debug check for mismatched cpreg resets
It's easy to accidentally define two cpregs which both try
to reset the same underlying state field (for instance a
clash between an AArch64 EL3 definition and an AArch32
banked register definition). if the two definitions disagree
about the reset value then the result is dependent on which
one happened to be reached last in the hashtable enumeration.
Add a consistency check to detect and assert in these cases:
after reset, we run a second pass where we check that the
reset operation doesn't change the value of the register.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1436797559-20835-1-git-send-email-peter.mayd...@linaro.org
---
target-arm/cpu.c| 23 +++
target-arm/cpu.h| 3 +++
target-arm/helper.c | 2 +-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3525348..3c84f72 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -79,6 +79,27 @@ static void cp_reg_reset(gpointer key, gpointer value,
gpointer opaque)
}
}
+static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
+{
+/* Purely an assertion check: we've already done reset once,
+ * so now check that running the reset for the cpreg doesn't
+ * change its value. This traps bugs where two different cpregs
+ * both try to reset the same state field but to different values.
+ */
+ARMCPRegInfo *ri = value;
+ARMCPU *cpu = opaque;
+uint64_t oldvalue, newvalue;
+
+if (ri-type (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
+return;
+}
+
+oldvalue = read_raw_cp_reg(cpu-env, ri);
+cp_reg_reset(key, value, opaque);
+newvalue = read_raw_cp_reg(cpu-env, ri);
+assert(oldvalue == newvalue);
+}
+
/* CPUClass::reset() */
static void arm_cpu_reset(CPUState *s)
{
@@ -90,6 +111,8 @@ static void arm_cpu_reset(CPUState *s)
memset(env, 0, offsetof(CPUARMState, features));
g_hash_table_foreach(cpu-cp_regs, cp_reg_reset, cpu);
+g_hash_table_foreach(cpu-cp_regs, cp_reg_check_reset, cpu);
+
env-vfp.xregs[ARM_VFP_FPSID] = cpu-reset_fpsid;
env-vfp.xregs[ARM_VFP_MVFR0] = cpu-mvfr0;
env-vfp.xregs[ARM_VFP_MVFR1] = cpu-mvfr1;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7346c5f..ebca342 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1448,6 +1448,9 @@ static inline bool cp_access_ok(int current_el,
return (ri-access ((current_el * 2) + isread)) 1;
}
+/* Raw read of a coprocessor register (as needed for migration, etc) */
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
+
/**
* write_list_to_cpustate
* @cpu: ARMCPU
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4a7dd24..49ce612 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -144,7 +144,7 @@ static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo
*ri)
return (char *)env + ri-fieldoffset;
}
-static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Raw read of a coprocessor register (as needed for migration, etc). */
if (ri-type ARM_CP_CONST) {
--
1.9.1
[Qemu-devel] [PULL 23/27] target-arm: Add the AArch64 view of the Secure physical timer
On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1437047249-2357-2-git-send-email-peter.mayd...@linaro.org
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 3 +-
target-arm/helper.c | 87
4 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 54db337..00c0716 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -225,6 +225,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf,
int reg);
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
+void arm_gt_stimer_cb(void *opaque);
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3c84f72..cc6c6f3 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -478,6 +478,8 @@ static void arm_cpu_initfn(Object *obj)
arm_gt_vtimer_cb, cpu);
cpu-gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_htimer_cb, cpu);
+cpu-gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
+arm_gt_stimer_cb, cpu);
qdev_init_gpio_out(DEVICE(cpu), cpu-gt_timer_outputs,
ARRAY_SIZE(cpu-gt_timer_outputs));
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ebca342..2e680da 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -114,7 +114,8 @@ typedef struct ARMGenericTimer {
#define GTIMER_PHYS 0
#define GTIMER_VIRT 1
#define GTIMER_HYP 2
-#define NUM_GTIMERS 3
+#define GTIMER_SEC 3
+#define NUM_GTIMERS 4
typedef struct {
uint64_t raw_tcr;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 49ce612..7cf6ffd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1214,6 +1214,32 @@ static CPAccessResult gt_vtimer_access(CPUARMState *env,
const ARMCPRegInfo *ri)
return gt_timer_access(env, GTIMER_VIRT);
}
+static CPAccessResult gt_stimer_access(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+/* The AArch64 register view of the secure physical timer is
+ * always accessible from EL3, and configurably accessible from
+ * Secure EL1.
+ */
+switch (arm_current_el(env)) {
+case 1:
+if (!arm_is_secure(env)) {
+return CP_ACCESS_TRAP;
+}
+if (!(env-cp15.scr_el3 SCR_ST)) {
+return CP_ACCESS_TRAP_EL3;
+}
+return CP_ACCESS_OK;
+case 0:
+case 2:
+return CP_ACCESS_TRAP;
+case 3:
+return CP_ACCESS_OK;
+default:
+g_assert_not_reached();
+}
+}
+
static uint64_t gt_get_countervalue(CPUARMState *env)
{
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
@@ -1420,6 +1446,34 @@ static void gt_hyp_ctl_write(CPUARMState *env, const
ARMCPRegInfo *ri,
gt_ctl_write(env, ri, GTIMER_HYP, value);
}
+static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+gt_timer_reset(env, ri, GTIMER_SEC);
+}
+
+static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_cval_write(env, ri, GTIMER_SEC, value);
+}
+
+static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+return gt_tval_read(env, ri, GTIMER_SEC);
+}
+
+static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_tval_write(env, ri, GTIMER_SEC, value);
+}
+
+static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+gt_ctl_write(env, ri, GTIMER_SEC, value);
+}
+
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
@@ -1441,6 +1495,13 @@ void arm_gt_htimer_cb(void *opaque)
gt_recalc_timer(cpu, GTIMER_HYP);
}
+void arm_gt_stimer_cb(void *opaque)
+{
+ARMCPU *cpu = opaque;
+
+gt_recalc_timer(cpu, GTIMER_SEC);
+}
+
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Note that CNTFRQ is purely reads-as-written for the benefit
* of software; writing it doesn't actually change the timer frequency.
@@ -1570,6 +1631,32 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.resetvalue = 0, .accessfn = gt_vtimer_access,
.writefn = gt_virt_cval_write, .raw_writefn = raw_write,
},
+/* Secure timer -- this is actually restricted to only EL3
+ * and configurably Secure-EL1 via the accessfn.
+ */
+{ .name = CNTPS_TVAL_EL1, .state =
Re: [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops
On Fri, Aug 07, 2015 at 01:33:24PM +0100, Peter Maydell wrote: This series does three things: Hi, Looks good to me! Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com Cheers, Edgar (1) implement the flush the TLB only for a specified MMU index functionality that we talked about when we added all the new MMU index values for ARM for EL2 and EL3 (2) use that to restrict the AArch64 TLB maintenance operations to only the MMU indexes they need to touch (3) add all the missing EL2 and EL3 related TLB operations for AArch64 I did a quick performance test by running hackbench. Measuring suggests that performance is improved by between half and one percent, which isn't fantastic but then I don't know how much of hackbench's runtime is bottlenecked by TLB flushes. I would expect that a workload that actually used EL2 and EL3 will benefit by not having the EL2 and EL3 flushes taking out the EL10 TLB too. Disclaimer: the EL2 and EL3 parts of this code are untested because we haven't completely implemented those for AArch64 yet. Peter Maydell (6): cputlb: Add functions for flushing TLB for a single MMU index target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Implement missing EL2 TLBI operations target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement AArch64 TLBI operations on IPAs cputlb.c| 81 include/exec/exec-all.h | 47 +++ target-arm/helper.c | 329 +--- 3 files changed, 412 insertions(+), 45 deletions(-) -- 1.9.1
[Qemu-devel] [PULL 06/27] hw/arm/virt: Replace magic IRQ constants with macros
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Replace magic constants with macros from
hw/arm/virt.h and hw/intc/arm_gic_common.h.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1436791864-4582-7-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/virt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4846892..42efad1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -48,6 +48,7 @@
#include hw/arm/sysbus-fdt.h
#include hw/platform-bus.h
#include hw/arm/fdt.h
+#include hw/intc/arm_gic_common.h
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
@@ -390,15 +391,17 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
*/
for (i = 0; i smp_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
-int ppibase = NUM_IRQS + i * 32;
+int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
/* physical timer; we wire it up to the non-secure timer's ID,
* since a real A15 always has TrustZone but QEMU doesn't.
*/
qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev, ppibase + 30));
+ qdev_get_gpio_in(gicdev,
+ ppibase + ARCH_TIMER_NS_EL1_IRQ));
/* virtual timer */
qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev, ppibase + 27));
+ qdev_get_gpio_in(gicdev,
+ ppibase + ARCH_TIMER_VIRT_IRQ));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
--
1.9.1
[Qemu-devel] [PULL 21/27] Introduce gic_class_name() instead of repeating condition
From: Pavel Fedin p.fe...@samsung.com
This small inline returns correct GIC class name depending on whether we
use KVM acceleration or not. Avoids duplicating the condition everywhere.
Signed-off-by: Pavel Fedin p.fe...@samsung.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Message-id:
4f26901be9b844b563673ce3ad08eeedbb7a7132.1438758065.git.p.fe...@samsung.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/virt.c| 7 +++
hw/cpu/a15mpcore.c | 8 ++--
target-arm/kvm_arm.h | 5 +
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index aab99f7..94694d6 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -49,6 +49,7 @@
#include hw/platform-bus.h
#include hw/arm/fdt.h
#include hw/intc/arm_gic_common.h
+#include kvm_arm.h
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
@@ -366,12 +367,10 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
/* We create a standalone GIC v2 */
DeviceState *gicdev;
SysBusDevice *gicbusdev;
-const char *gictype = arm_gic;
+const char *gictype;
int i;
-if (kvm_irqchip_in_kernel()) {
-gictype = kvm-arm-gic;
-}
+gictype = gic_class_name();
gicdev = qdev_create(NULL, gictype);
qdev_prop_set_uint32(gicdev, revision, 2);
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index acc419e..e31a1f9 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -20,6 +20,7 @@
#include hw/cpu/a15mpcore.h
#include sysemu/kvm.h
+#include kvm_arm.h
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{
@@ -33,16 +34,11 @@ static void a15mp_priv_initfn(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
A15MPPrivState *s = A15MPCORE_PRIV(obj);
DeviceState *gicdev;
-const char *gictype = arm_gic;
-
-if (kvm_irqchip_in_kernel()) {
-gictype = kvm-arm-gic;
-}
memory_region_init(s-container, obj, a15mp-priv-container, 0x8000);
sysbus_init_mmio(sbd, s-container);
-object_initialize(s-gic, sizeof(s-gic), gictype);
+object_initialize(s-gic, sizeof(s-gic), gic_class_name());
gicdev = DEVICE(s-gic);
qdev_set_parent_bus(gicdev, sysbus_get_default());
qdev_prop_set_uint32(gicdev, revision, 2);
diff --git a/target-arm/kvm_arm.h b/target-arm/kvm_arm.h
index 7912d74..b3e0ab7 100644
--- a/target-arm/kvm_arm.h
+++ b/target-arm/kvm_arm.h
@@ -191,4 +191,9 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu);
#endif
+static inline const char *gic_class_name(void)
+{
+return kvm_irqchip_in_kernel() ? kvm-arm-gic : arm_gic;
+}
+
#endif
--
1.9.1
Re: [Qemu-devel] [PATCH v6 1/2] vhost-user: add multi queue support
On Thu, Aug 13, 2015 at 12:24:16PM +0200, Maxime Leroy wrote: On Thu, Aug 13, 2015 at 11:18 AM, Michael S. Tsirkin m...@redhat.com wrote: On Wed, Aug 12, 2015 at 02:25:41PM +0800, Ouyang Changchun wrote: Based on patch by Nikolay Nikolaev: Vhost-user will implement the multi queue support in a similar way to what vhost already has - a separate thread for each queue. To enable the multi queue functionality - a new command line parameter queues is introduced for the vhost-user netdev. The RESET_OWNER change is based on commit: 294ce717e0f212ed0763307f3eab72b4a1bdf4d0 If it is reverted, the patch need update for it accordingly. Signed-off-by: Nikolay Nikolaev n.nikol...@virtualopensystems.com Signed-off-by: Changchun Ouyang changchun.ouy...@intel.com --- Changes since v5: - fix the message descption for VHOST_RESET_OWNER in vhost-user txt Changes since v4: - remove the unnecessary trailing '\n' Changes since v3: - fix one typo and wrap one long line Changes since v2: - fix vq index issue for set_vring_call When it is the case of VHOST_SET_VRING_CALL, The vq_index is not initialized before it is used, thus it could be a random value. The random value leads to crash in vhost after passing down to vhost, as vhost use this random value to index an array index. - fix the typo in the doc and description - address vq index for reset_owner Changes since v1: - use s-nc.info_str when bringing up/down the backend docs/specs/vhost-user.txt | 7 ++- hw/net/vhost_net.c| 3 ++- hw/virtio/vhost-user.c| 11 ++- net/vhost-user.c | 37 - qapi-schema.json | 6 +- qemu-options.hx | 5 +++-- 6 files changed, 50 insertions(+), 19 deletions(-) diff --git a/docs/specs/vhost-user.txt b/docs/specs/vhost-user.txt index 70da3b1..9390f89 100644 --- a/docs/specs/vhost-user.txt +++ b/docs/specs/vhost-user.txt @@ -135,6 +135,11 @@ As older slaves don't support negotiating protocol features, a feature bit was dedicated for this purpose: #define VHOST_USER_F_PROTOCOL_FEATURES 30 +Multi queue support +--- +The protocol supports multiple queues by setting all index fields in the sent +messages to a properly calculated value. + Message types - @@ -198,7 +203,7 @@ Message types Id: 4 Equivalent ioctl: VHOST_RESET_OWNER - Master payload: N/A + Master payload: vring state description Issued when a new connection is about to be closed. The Master will no longer own this connection (and will usually close it). This is an interface change, isn't it? We can't make it unconditionally, need to make it dependent on a protocol flag. Agree. It can potential break vhost-user driver implementation checking the size of the message. We should not change the vhost-user protocol without a new protocol flag. I think the first issue here that VHOST_RESET_OWNER should happen on vhost_dev_cleanup and not in vhost_net_stop_one. VHOST_RESET_OWNER should be the counter part of VHOST_SET_OWNER. So it don't need to have a payload like VHOST_SET_OWNER. Thus I agree with this email (http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg05971.html) Maybe should we use an other message to tell to the backend that the vring is not anymore available in vhost_net_stop_one ? Maxime I think the cleanest fix is to rename this message to e.g. VHOST_RESET_DEVICE. This way we won't break existing users. -- MST
[Qemu-devel] [PULL 03/27] target-arm: Rename and move gt_cnt_reset
From: Edgar E. Iglesias edgar.igles...@gmail.com
Rename gt_cnt_reset to gt_timer_reset as the function really
resets the timers and not the counters. Move the registration
from counter regs to timer regs.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1436791864-4582-4-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3f8d06e..8dee980 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1261,7 +1261,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
}
}
-static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int timeridx = ri-opc1 1;
@@ -1414,7 +1414,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = CNTP_TVAL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_ptimer_access,
+ .accessfn = gt_ptimer_access, .resetfn = gt_timer_reset,
.readfn = gt_tval_read, .writefn = gt_tval_write,
},
{ .name = CNTV_TVAL, .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
@@ -1425,7 +1425,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = CNTV_TVAL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_vtimer_access,
+ .accessfn = gt_vtimer_access, .resetfn = gt_timer_reset,
.readfn = gt_tval_read, .writefn = gt_tval_write,
},
/* The counter itself */
@@ -1437,8 +1437,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = CNTPCT_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
- .accessfn = gt_pct_access,
- .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
},
{ .name = CNTVCT, .cp = 15, .crm = 14, .opc1 = 1,
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
@@ -1448,8 +1447,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = CNTVCT_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
- .accessfn = gt_vct_access,
- .readfn = gt_virt_cnt_read, .resetfn = gt_cnt_reset,
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
},
/* Comparison value, indicating when the timer goes off */
{ .name = CNTP_CVAL, .cp = 15, .crm = 14, .opc1 = 2,
--
1.9.1
[Qemu-devel] [PATCH v9 1/5] hw/intc: Implement GIC-500 base class
From: Shlomo Pongratz shlomo.pongr...@huawei.com
This class is to be used by both software and KVM implementations of GICv3
Currently it is mostly a placeholder, but in future it is supposed to hold
qemu's representation of GICv3 state, which is necessary for migration.
The interface of this class is fully compatible with GICv2 one. This is
done in order to simplify integration with existing code.
Signed-off-by: Shlomo Pongratz shlomo.pongr...@huawei.com
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
hw/intc/Makefile.objs | 1 +
hw/intc/arm_gicv3_common.c | 140 +
include/hw/intc/arm_gicv3_common.h | 68 ++
3 files changed, 209 insertions(+)
create mode 100644 hw/intc/arm_gicv3_common.c
create mode 100644 include/hw/intc/arm_gicv3_common.h
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 092d8a8..1317e5a 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
common-obj-$(CONFIG_ARM_GIC) += arm_gicv2m.o
+common-obj-$(CONFIG_ARM_GIC) += arm_gicv3_common.o
common-obj-$(CONFIG_OPENPIC) += openpic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
new file mode 100644
index 000..032ece2
--- /dev/null
+++ b/hw/intc/arm_gicv3_common.c
@@ -0,0 +1,140 @@
+/*
+ * ARM GICv3 support - common bits of emulated and KVM kernel model
+ *
+ * Copyright (c) 2012 Linaro Limited
+ * Copyright (c) 2015 Huawei.
+ * Written by Peter Maydell
+ * Extended to 64 cores by Shlomo Pongratz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see http://www.gnu.org/licenses/.
+ */
+
+#include hw/intc/arm_gicv3_common.h
+
+static void gicv3_pre_save(void *opaque)
+{
+GICv3State *s = (GICv3State *)opaque;
+ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
+
+if (c-pre_save) {
+c-pre_save(s);
+}
+}
+
+static int gicv3_post_load(void *opaque, int version_id)
+{
+GICv3State *s = (GICv3State *)opaque;
+ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
+
+if (c-post_load) {
+c-post_load(s);
+}
+return 0;
+}
+
+static const VMStateDescription vmstate_gicv3 = {
+.name = arm_gicv3,
+.unmigratable = 1,
+.pre_save = gicv3_pre_save,
+.post_load = gicv3_post_load,
+};
+
+void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
+ const MemoryRegionOps *ops)
+{
+SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+int i;
+
+/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
+ * GPIO array layout is thus:
+ * [0..N-1] spi
+ * [N..N+31] PPIs for CPU 0
+ * [N+32..N+63] PPIs for CPU 1
+ * ...
+ */
+i = s-num_irq - GIC_INTERNAL + GIC_INTERNAL * s-num_cpu;
+qdev_init_gpio_in(DEVICE(s), handler, i);
+
+s-parent_irq = g_malloc(s-num_cpu * sizeof(qemu_irq));
+s-parent_fiq = g_malloc(s-num_cpu * sizeof(qemu_irq));
+
+for (i = 0; i s-num_cpu; i++) {
+sysbus_init_irq(sbd, s-parent_irq[i]);
+}
+for (i = 0; i s-num_cpu; i++) {
+sysbus_init_irq(sbd, s-parent_fiq[i]);
+}
+
+memory_region_init_io(s-iomem_dist, OBJECT(s), ops, s,
+ gicv3_dist, 0x1);
+memory_region_init_io(s-iomem_redist, OBJECT(s), ops ? ops[1] : NULL, s,
+ gicv3_redist, 0x2 * s-num_cpu);
+
+sysbus_init_mmio(sbd, s-iomem_dist);
+sysbus_init_mmio(sbd, s-iomem_redist);
+}
+
+static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
+{
+GICv3State *s = ARM_GICV3_COMMON(dev);
+
+/* revision property is actually reserved and currently used only in order
+ * to keep the interface compatible with GICv2 code, avoiding extra
+ * conditions. However, in future it could be used, for example, if we
+ * implement GICv4.
+ */
+if (s-revision != 3) {
+error_setg(errp, unsupported GIC revision %d, s-revision);
+return;
+}
+}
+
+static void arm_gicv3_common_reset(DeviceState *dev)
+{
+/* TODO */
+}
+
+static Property arm_gicv3_common_properties[] = {
+DEFINE_PROP_UINT32(num-cpu, GICv3State, num_cpu, 1),
+DEFINE_PROP_UINT32(num-irq, GICv3State, num_irq, 32),
+
Re: [Qemu-devel] [PATCH] mirror: Fix coroutine reentrance
On 13/08/2015 10:41, Kevin Wolf wrote:
This fixes a regression introduced by commit dcfb3beb (mirror: Do zero
write on target if sectors not allocated), which was reported to cause
aborts with the message Co-routine re-entered recursively.
The cause for this bug is the following code in mirror_iteration_done():
if (s-common.busy) {
qemu_coroutine_enter(s-common.co, NULL);
}
This has always been ugly because - unlike most places that reenter - it
doesn't have a specific yield that it pairs with, but is more
uncontrolled. What we really mean here is reenter the coroutine if
it's in one of the four explicit yields in mirror.c.
This used to be equivalent with s-common.busy because neither
mirror_run() nor mirror_iteration() call any function that could yield.
However since commit dcfb3beb this doesn't hold true any more:
bdrv_get_block_status_above() can yield.
So what happens is that bdrv_get_block_status_above() wants to take a
lock that is already held, so it adds itself to the queue of waiting
coroutines and yields. Instead of being woken up by the unlock function,
however, it gets woken up by mirror_iteration_done(), which is obviously
wrong.
In most cases the code actually happens to cope fairly well with such
cases, but in this specific case, the unlock must already have scheduled
the coroutine for wakeup when mirror_iteration_done() reentered it. And
then the coroutine happened to process the scheduled restarts and tried
to reenter itself recursively.
This patch fixes the problem by pairing the reenter in
mirror_iteration_done() with specific yields instead of abusing
s-common.busy.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Kevin Wolf kw...@redhat.com
Reviewed-by: Paolo Bonzini pbonz...@redhat.com
---
block/mirror.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/block/mirror.c b/block/mirror.c
index fc4d8f5..b2fb4b9 100644
--- a/block/mirror.c
+++ b/block/mirror.c
@@ -60,6 +60,7 @@ typedef struct MirrorBlockJob {
int sectors_in_flight;
int ret;
bool unmap;
+bool waiting_for_io;
} MirrorBlockJob;
typedef struct MirrorOp {
@@ -114,11 +115,7 @@ static void mirror_iteration_done(MirrorOp *op, int ret)
qemu_iovec_destroy(op-qiov);
g_slice_free(MirrorOp, op);
-/* Enter coroutine when it is not sleeping. The coroutine sleeps to
- * rate-limit itself. The coroutine will eventually resume since there
is
- * a sleep timeout so don't wake it early.
- */
-if (s-common.busy) {
+if (s-waiting_for_io) {
qemu_coroutine_enter(s-common.co, NULL);
}
}
@@ -203,7 +200,9 @@ static uint64_t coroutine_fn
mirror_iteration(MirrorBlockJob *s)
/* Wait for I/O to this cluster (from a previous iteration) to be done.
*/
while (test_bit(next_chunk, s-in_flight_bitmap)) {
trace_mirror_yield_in_flight(s, sector_num, s-in_flight);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
do {
@@ -239,7 +238,9 @@ static uint64_t coroutine_fn
mirror_iteration(MirrorBlockJob *s)
*/
while (nb_chunks == 0 s-buf_free_count added_chunks) {
trace_mirror_yield_buf_busy(s, nb_chunks, s-in_flight);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
if (s-buf_free_count nb_chunks + added_chunks) {
trace_mirror_break_buf_busy(s, nb_chunks, s-in_flight);
@@ -333,7 +334,9 @@ static void mirror_free_init(MirrorBlockJob *s)
static void mirror_drain(MirrorBlockJob *s)
{
while (s-in_flight 0) {
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
}
}
@@ -506,7 +509,9 @@ static void coroutine_fn mirror_run(void *opaque)
if (s-in_flight == MAX_IN_FLIGHT || s-buf_free_count == 0 ||
(cnt == 0 s-in_flight 0)) {
trace_mirror_yield(s, s-in_flight, s-buf_free_count, cnt);
+s-waiting_for_io = true;
qemu_coroutine_yield();
+s-waiting_for_io = false;
continue;
} else if (cnt != 0) {
delay_ns = mirror_iteration(s);
Re: [Qemu-devel] [PULL 00/20] SCSI, build, TCG, RCU, misc patches for 2015-08-12
On 13/08/2015 11:28, Peter Maydell wrote:
config-host.mak is out-of-date, running configure
../../configure: 2789: local: -I/usr/include/glib-2.0: bad variable name
line 2789 is
local probe_cflags=$($pkg_config --cflags $1)
'local' isn't part of POSIX shell. It is supported by 'dash', but
only in the form 'local varname ...', not the bash-specific
'local varname=value ...' form.
This is not entirely correct; dash is clearly supporting assignments in
local as well; we have:
local compiler=$1
However, it's not automatically quoting the RHS of the assignment, like
normal variable assignment does. But since this RHS is a bit more
complex than usual, I'll just apply this:
diff --git a/configure b/configure
index 28bf755..6faeb00 100755
--- a/configure
+++ b/configure
@@ -2787,8 +2787,10 @@ fi
glib_pkg_config()
{
if $pkg_config --atleast-version=$glib_req_ver $1; then
-local probe_cflags=$($pkg_config --cflags $1)
-local probe_libs=$($pkg_config --libs $1)
+local probe_cflags
+local probe_libs
+probe_cflags=$($pkg_config --cflags $1)
+probe_libs=$($pkg_config --libs $1)
CFLAGS=$probe_cflags $CFLAGS
LIBS=$probe_libs $LIBS
libs_qga=$probe_libs $libs_qga
Paolo
[Qemu-devel] [PULL 24/27] target-arm: Add AArch32 banked register access to secure physical timer
If EL3 is AArch32, then the secure physical timer is accessed via
banking of the registers used for the non-secure physical timer.
Implement this banking.
Note that the access controls for the AArch32 banked registers
remain the same as the physical-timer checks; they are not the
same as the controls on the AArch64 secure timer registers.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Message-id: 1437047249-2357-3-git-send-email-peter.mayd...@linaro.org
Reviewed-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/helper.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7cf6ffd..1568aa6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1527,12 +1527,22 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
/* per-timer control */
{ .name = CNTP_CTL, .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
+ .secure = ARM_CP_SECSTATE_NS,
.type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
.accessfn = gt_ptimer_access,
.fieldoffset = offsetoflow32(CPUARMState,
cp15.c14_timer[GTIMER_PHYS].ctl),
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
},
+{ .name = CNTP_CTL(S),
+ .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
+ .secure = ARM_CP_SECSTATE_S,
+ .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
+ .accessfn = gt_ptimer_access,
+ .fieldoffset = offsetoflow32(CPUARMState,
+ cp15.c14_timer[GTIMER_SEC].ctl),
+ .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
+},
{ .name = CNTP_CTL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
@@ -1558,10 +1568,18 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
/* TimerValue views: a 32 bit downcounting view of the underlying state */
{ .name = CNTP_TVAL, .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
+ .secure = ARM_CP_SECSTATE_NS,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
.accessfn = gt_ptimer_access,
.readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
},
+{ .name = CNTP_TVAL(S),
+ .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
+ .secure = ARM_CP_SECSTATE_S,
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
+ .accessfn = gt_ptimer_access,
+ .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
+},
{ .name = CNTP_TVAL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
@@ -1602,12 +1620,21 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
/* Comparison value, indicating when the timer goes off */
{ .name = CNTP_CVAL, .cp = 15, .crm = 14, .opc1 = 2,
+ .secure = ARM_CP_SECSTATE_NS,
.access = PL1_RW | PL0_R,
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
.accessfn = gt_ptimer_access,
.writefn = gt_phys_cval_write, .raw_writefn = raw_write,
},
+{ .name = CNTP_CVAL(S), .cp = 15, .crm = 14, .opc1 = 2,
+ .secure = ARM_CP_SECSTATE_S,
+ .access = PL1_RW | PL0_R,
+ .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
+ .accessfn = gt_ptimer_access,
+ .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
+},
{ .name = CNTP_CVAL_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
.access = PL1_RW | PL0_R,
--
1.9.1
[Qemu-devel] [PULL 19/27] Merge memory_region_init_reservation() into memory_region_init_io()
From: Pavel Fedin p.fe...@samsung.com
Just specifying ops = NULL in some cases can be more convenient than having
two functions.
Signed-off-by: Pavel Fedin p.fe...@samsung.com
Acked-by: Paolo Bonzini pbonz...@redhat.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Message-id:
78a379ab1b6b30ab497db7971ad336dad1dbee76.1438758065.git.p.fe...@samsung.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
include/exec/memory.h | 14 +++---
memory.c | 10 +-
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 94d20ea..b18b351 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -437,6 +437,9 @@ void memory_region_init_alias(MemoryRegion *mr,
* memory_region_init_rom_device: Initialize a ROM memory region. Writes are
* handled via callbacks.
*
+ * If NULL callbacks pointer is given, then I/O space is not supposed to be
+ * handled by QEMU itself. Any access via the memory API will cause an abort().
+ *
* @mr: the #MemoryRegion to be initialized.
* @owner: the object that tracks the region's reference count
* @ops: callbacks for write access handling.
@@ -459,16 +462,21 @@ void memory_region_init_rom_device(MemoryRegion *mr,
* A reservation region primariy serves debugging purposes. It claims I/O
* space that is not supposed to be handled by QEMU itself. Any access via
* the memory API will cause an abort().
+ * This function is deprecated. Use memory_region_init_io() with NULL
+ * callbacks instead.
*
* @mr: the #MemoryRegion to be initialized
* @owner: the object that tracks the region's reference count
* @name: used for debugging; not visible to the user or ABI
* @size: size of the region.
*/
-void memory_region_init_reservation(MemoryRegion *mr,
-struct Object *owner,
+static inline void memory_region_init_reservation(MemoryRegion *mr,
+Object *owner,
const char *name,
-uint64_t size);
+uint64_t size)
+{
+memory_region_init_io(mr, owner, NULL, mr, name, size);
+}
/**
* memory_region_init_iommu: Initialize a memory region that translates
diff --git a/memory.c b/memory.c
index 4eb138a..0d8b2d9 100644
--- a/memory.c
+++ b/memory.c
@@ -1182,7 +1182,7 @@ void memory_region_init_io(MemoryRegion *mr,
uint64_t size)
{
memory_region_init(mr, owner, name, size);
-mr-ops = ops;
+mr-ops = ops ? ops : unassigned_mem_ops;
mr-opaque = opaque;
mr-terminates = true;
}
@@ -1300,14 +1300,6 @@ void memory_region_init_iommu(MemoryRegion *mr,
notifier_list_init(mr-iommu_notify);
}
-void memory_region_init_reservation(MemoryRegion *mr,
-Object *owner,
-const char *name,
-uint64_t size)
-{
-memory_region_init_io(mr, owner, unassigned_mem_ops, mr, name, size);
-}
-
static void memory_region_finalize(Object *obj)
{
MemoryRegion *mr = MEMORY_REGION(obj);
--
1.9.1
[Qemu-devel] [PULL 11/27] i.MX: Split AVIC emulator in a header file and a source file
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
06829257e845d693be05c7d491134313c1615d1a.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/kzm.c | 3 ++-
hw/intc/imx_avic.c | 40 +++--
include/hw/intc/imx_avic.h | 55 ++
3 files changed, 60 insertions(+), 38 deletions(-)
create mode 100644 include/hw/intc/imx_avic.h
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 5be0369..c906da7 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -22,6 +22,7 @@
#include sysemu/sysemu.h
#include hw/boards.h
#include hw/char/serial.h
+#include hw/intc/imx_avic.h
#include hw/arm/imx.h
/* Memory map for Kzm Emulation Baseboard:
@@ -106,7 +107,7 @@ static void kzm_init(MachineState *machine)
memory_region_init_ram(sram, NULL, kzm.sram, 0x4000, error_abort);
memory_region_add_subregion(address_space_mem, 0x1FFFC000, sram);
-dev = sysbus_create_varargs(imx_avic, 0x6800,
+dev = sysbus_create_varargs(TYPE_IMX_AVIC, 0x6800,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
NULL);
diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c
index e48f66c..c5eecb5 100644
--- a/hw/intc/imx_avic.c
+++ b/hw/intc/imx_avic.c
@@ -7,6 +7,7 @@
* Copyright (c) 2008 OKL
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
@@ -14,9 +15,7 @@
* TODO: implement vectors.
*/
-#include hw/hw.h
-#include hw/sysbus.h
-#include qemu/host-utils.h
+#include hw/intc/imx_avic.h
#define DEBUG_INT 1
#undef DEBUG_INT /* comment out for debugging */
@@ -40,39 +39,6 @@ do { printf(imx_avic: fmt , ##args); } while (0)
# define IPRINTF(fmt, args...) do {} while (0)
#endif
-#define IMX_AVIC_NUM_IRQS 64
-
-/* Interrupt Control Bits */
-#define ABFLAG (125)
-#define ABFEN (124)
-#define NIDIS (122) /* Normal Interrupt disable */
-#define FIDIS (121) /* Fast interrupt disable */
-#define NIAD (120) /* Normal Interrupt Arbiter Rise ARM level */
-#define FIAD (119) /* Fast Interrupt Arbiter Rise ARM level */
-#define NM(118) /* Normal interrupt mode */
-
-
-#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
-#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
-
-#define TYPE_IMX_AVIC imx_avic
-#define IMX_AVIC(obj) \
-OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
-
-typedef struct IMXAVICState {
-SysBusDevice parent_obj;
-
-MemoryRegion iomem;
-uint64_t pending;
-uint64_t enabled;
-uint64_t is_fiq;
-uint32_t intcntl;
-uint32_t intmask;
-qemu_irq irq;
-qemu_irq fiq;
-uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
-} IMXAVICState;
-
static const VMStateDescription vmstate_imx_avic = {
.name = imx-avic,
.version_id = 1,
@@ -370,7 +336,7 @@ static int imx_avic_init(SysBusDevice *sbd)
IMXAVICState *s = IMX_AVIC(dev);
memory_region_init_io(s-iomem, OBJECT(s), imx_avic_ops, s,
- imx_avic, 0x1000);
+ TYPE_IMX_AVIC, 0x1000);
sysbus_init_mmio(sbd, s-iomem);
qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
diff --git a/include/hw/intc/imx_avic.h b/include/hw/intc/imx_avic.h
new file mode 100644
index 000..1b80769
--- /dev/null
+++ b/include/hw/intc/imx_avic.h
@@ -0,0 +1,55 @@
+/*
+ * i.MX31 Vectored Interrupt Controller
+ *
+ * Note this is NOT the PL192 provided by ARM, but
+ * a custom implementation by Freescale.
+ *
+ * Copyright (c) 2008 OKL
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * TODO: implement vectors.
+ */
+#ifndef IMX_AVIC_H
+#define IMX_AVIC_H
+
+#include hw/sysbus.h
+
+#define TYPE_IMX_AVIC imx.avic
+#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
+
+#define IMX_AVIC_NUM_IRQS 64
+
+/* Interrupt Control Bits */
+#define ABFLAG (125)
+#define ABFEN (124)
+#define NIDIS (122) /* Normal Interrupt disable */
+#define FIDIS (121) /* Fast interrupt disable */
+#define NIAD (120) /* Normal Interrupt Arbiter Rise ARM level */
+#define FIAD (119) /* Fast Interrupt Arbiter Rise ARM level */
+#define NM (118) /* Normal interrupt mode */
+
+#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
+#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
+
+typedef struct IMXAVICState{
+/* private */
+SysBusDevice parent_obj;
[Qemu-devel] [PULL 01/27] target-arm: Add CNTVOFF_EL2
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Adds support for the virtual timer offset controlled by EL2.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Message-id: 1436791864-4582-2-git-send-email-edgar.igles...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 47 +--
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7e89152..b1fa287 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -358,6 +358,7 @@ typedef struct CPUARMState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
+uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
uint32_t c15_ticonfig; /* TI925T configuration byte. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 01f0d0d..b8188ad 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1209,9 +1209,11 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
/* Timer enabled: calculate and set current ISTATUS, irq, and
* reset timer to when ISTATUS next has to change
*/
+uint64_t offset = timeridx == GTIMER_VIRT ?
+ cpu-env.cp15.cntvoff_el2 : 0;
uint64_t count = gt_get_countervalue(cpu-env);
/* Note that this must be unsigned 64 bit arithmetic: */
-int istatus = count = gt-cval;
+int istatus = count - offset = gt-cval;
uint64_t nexttick;
gt-ctl = deposit32(gt-ctl, 2, 1, istatus);
@@ -1222,7 +1224,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
nexttick = UINT64_MAX;
} else {
/* Next transition is when we hit cval */
-nexttick = gt-cval;
+nexttick = gt-cval + offset;
}
/* Note that the desired next expiry time might be beyond the
* signed-64-bit range of a QEMUTimer -- in this case we just
@@ -1254,6 +1256,11 @@ static uint64_t gt_cnt_read(CPUARMState *env, const
ARMCPRegInfo *ri)
return gt_get_countervalue(env);
}
+static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+return gt_get_countervalue(env) - env-cp15.cntvoff_el2;
+}
+
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1266,17 +1273,19 @@ static void gt_cval_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
int timeridx = ri-crm 1;
+uint64_t offset = timeridx == GTIMER_VIRT ? env-cp15.cntvoff_el2 : 0;
return (uint32_t)(env-cp15.c14_timer[timeridx].cval -
- gt_get_countervalue(env));
+ (gt_get_countervalue(env) - offset));
}
static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int timeridx = ri-crm 1;
+uint64_t offset = timeridx == GTIMER_VIRT ? env-cp15.cntvoff_el2 : 0;
-env-cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
+env-cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
sextract64(value, 0, 32);
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
@@ -1301,6 +1310,15 @@ static void gt_ctl_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
+static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ARMCPU *cpu = arm_env_get_cpu(env);
+
+raw_write(env, ri, value);
+gt_recalc_timer(cpu, GTIMER_VIRT);
+}
+
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
@@ -1407,13 +1425,13 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
{ .name = CNTVCT, .cp = 15, .crm = 14, .opc1 = 1,
.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
.accessfn = gt_vct_access,
- .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
},
{ .name = CNTVCT_EL0, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
.accessfn = gt_vct_access,
- .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
+ .readfn = gt_virt_cnt_read, .resetfn = gt_cnt_reset,
},
/* Comparison value, indicating when the timer goes off */
{ .name = CNTP_CVAL, .cp = 15, .crm = 14, .opc1 = 2,
@@ -2613,6 +2631,12 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = HTTBR, .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW,
[Qemu-devel] [PULL 17/27] i.MX: Split GPT emulator in a header file and a source file
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
e32fba56b9dae3cc7c83726550514b2d0c890ae0.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/timer/imx_gpt.c | 79 ++---
include/hw/timer/imx_gpt.h | 107 +
2 files changed, 110 insertions(+), 76 deletions(-)
create mode 100644 include/hw/timer/imx_gpt.h
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 3b31010..f61d4e5 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -5,23 +5,18 @@
* Copyright (c) 2011 NICTA Pty Ltd
* Originally written by Hans Jiang
* Updated by Peter Chubb
- * Updated by Jean-Christophe Dubois
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
*
* This code is licensed under GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
*/
-#include hw/hw.h
-#include qemu/bitops.h
-#include qemu/timer.h
-#include hw/ptimer.h
-#include hw/sysbus.h
#include hw/arm/imx.h
+#include hw/timer/imx_gpt.h
+#include hw/misc/imx_ccm.h
#include qemu/main-loop.h
-#define TYPE_IMX_GPT imx.gpt
-
/*
* Define to 1 for debug messages
*/
@@ -74,74 +69,6 @@ static char const *imx_gpt_reg_name(uint32_t reg)
# define IPRINTF(fmt, args...) do {} while (0)
#endif
-#define IMX_GPT(obj) \
-OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
-/*
- * GPT : General purpose timer
- *
- * This timer counts up continuously while it is enabled, resetting itself
- * to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
- * reaches the value of one of the ocrX (in periodic mode).
- */
-
-#define GPT_TIMER_MAX 0XUL
-
-/* Control register. Not all of these bits have any effect (yet) */
-#define GPT_CR_EN (1 0) /* GPT Enable */
-#define GPT_CR_ENMOD (1 1) /* GPT Enable Mode */
-#define GPT_CR_DBGEN (1 2) /* GPT Debug mode enable */
-#define GPT_CR_WAITEN (1 3) /* GPT Wait Mode Enable */
-#define GPT_CR_DOZEN (1 4) /* GPT Doze mode enable */
-#define GPT_CR_STOPEN (1 5) /* GPT Stop Mode Enable */
-#define GPT_CR_CLKSRC_SHIFT (6)
-#define GPT_CR_CLKSRC_MASK (0x7)
-
-#define GPT_CR_FRR(1 9) /* Freerun or Restart */
-#define GPT_CR_SWR(1 15) /* Software Reset */
-#define GPT_CR_IM1(3 16) /* Input capture channel 1 mode (2 bits) */
-#define GPT_CR_IM2(3 18) /* Input capture channel 2 mode (2 bits) */
-#define GPT_CR_OM1(7 20) /* Output Compare Channel 1 Mode (3 bits) */
-#define GPT_CR_OM2(7 23) /* Output Compare Channel 2 Mode (3 bits) */
-#define GPT_CR_OM3(7 26) /* Output Compare Channel 3 Mode (3 bits) */
-#define GPT_CR_FO1(1 29) /* Force Output Compare Channel 1 */
-#define GPT_CR_FO2(1 30) /* Force Output Compare Channel 2 */
-#define GPT_CR_FO3(1 31) /* Force Output Compare Channel 3 */
-
-#define GPT_SR_OF1 (1 0)
-#define GPT_SR_OF2 (1 1)
-#define GPT_SR_OF3 (1 2)
-#define GPT_SR_ROV (1 5)
-
-#define GPT_IR_OF1IE (1 0)
-#define GPT_IR_OF2IE (1 1)
-#define GPT_IR_OF3IE (1 2)
-#define GPT_IR_ROVIE (1 5)
-
-typedef struct {
-SysBusDevice busdev;
-ptimer_state *timer;
-MemoryRegion iomem;
-DeviceState *ccm;
-
-uint32_t cr;
-uint32_t pr;
-uint32_t sr;
-uint32_t ir;
-uint32_t ocr1;
-uint32_t ocr2;
-uint32_t ocr3;
-uint32_t icr1;
-uint32_t icr2;
-uint32_t cnt;
-
-uint32_t next_timeout;
-uint32_t next_int;
-
-uint32_t freq;
-
-qemu_irq irq;
-} IMXGPTState;
-
static const VMStateDescription vmstate_imx_timer_gpt = {
.name = imx.gpt,
.version_id = 3,
diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
new file mode 100644
index 000..3f02d3b
--- /dev/null
+++ b/include/hw/timer/imx_gpt.h
@@ -0,0 +1,107 @@
+/*
+ * i.MX GPT Timer
+ *
+ * Copyright (c) 2008 OK Labs
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Peter Chubb
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the Software), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ *
[Qemu-devel] [PATCH 2/5] Split out end of migration code from migration_thread
From: Dr. David Alan Gilbert dgilb...@redhat.com
The code that gets run at the end of the migration process
is getting large, and I'm about to add more for postcopy.
Split it into a separate function.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
migration/migration.c | 75 ---
trace-events | 2 ++
2 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 662e77e..46bb410 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -913,6 +913,50 @@ int64_t migrate_xbzrle_cache_size(void)
return s-xbzrle_cache_size;
}
+/**
+ * migration_completion: Used by migration_thread when there's not much left.
+ * The caller 'breaks' the loop when this returns.
+ *
+ * @s: Current migration state
+ * @*old_vm_running: Pointer to old_vm_running flag
+ * @*start_time: Pointer to time to update
+ */
+static void migration_completion(MigrationState *s, bool *old_vm_running,
+ int64_t *start_time)
+{
+int ret;
+
+qemu_mutex_lock_iothread();
+*start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
+*old_vm_running = runstate_is_running();
+
+ret = global_state_store();
+if (!ret) {
+ret = vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
+if (ret = 0) {
+qemu_file_set_rate_limit(s-file, INT64_MAX);
+qemu_savevm_state_complete(s-file);
+}
+}
+qemu_mutex_unlock_iothread();
+
+if (ret 0) {
+goto fail;
+}
+
+if (qemu_file_get_error(s-file)) {
+trace_migration_completion_file_err();
+goto fail;
+}
+
+migrate_set_state(s, MIGRATION_STATUS_ACTIVE, MIGRATION_STATUS_COMPLETED);
+return;
+
+fail:
+migrate_set_state(s, MIGRATION_STATUS_ACTIVE, MIGRATION_STATUS_FAILED);
+}
+
/* migration thread support */
static void *migration_thread(void *opaque)
@@ -943,34 +987,9 @@ static void *migration_thread(void *opaque)
if (pending_size pending_size = max_size) {
qemu_savevm_state_iterate(s-file);
} else {
-int ret;
-
-qemu_mutex_lock_iothread();
-start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
-qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
-old_vm_running = runstate_is_running();
-
-ret = global_state_store();
-if (!ret) {
-ret = vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
-if (ret = 0) {
-qemu_file_set_rate_limit(s-file, INT64_MAX);
-qemu_savevm_state_complete(s-file);
-}
-}
-qemu_mutex_unlock_iothread();
-
-if (ret 0) {
-migrate_set_state(s, MIGRATION_STATUS_ACTIVE,
- MIGRATION_STATUS_FAILED);
-break;
-}
-
-if (!qemu_file_get_error(s-file)) {
-migrate_set_state(s, MIGRATION_STATUS_ACTIVE,
- MIGRATION_STATUS_COMPLETED);
-break;
-}
+trace_migration_thread_low_pending(pending_size);
+migration_completion(s, old_vm_running, start_time);
+break;
}
}
diff --git a/trace-events b/trace-events
index 94bf3bb..1509e5b 100644
--- a/trace-events
+++ b/trace-events
@@ -1406,6 +1406,8 @@ migrate_transferred(uint64_t tranferred, uint64_t
time_spent, double bandwidth,
migrate_state_too_big(void)
migrate_global_state_post_load(const char *state) loaded state: %s
migrate_global_state_pre_save(const char *state) saved state: %s
+migration_completion_file_err(void)
+migration_thread_low_pending(uint64_t pending) % PRIu64
# migration/rdma.c
qemu_rdma_accept_incoming_migration(void)
--
2.4.3
Re: [Qemu-devel] [PATCH for-2.5] virtio: avoid leading underscores for helpers
On Wed, Jul 29, 2015 at 02:22:47PM +0200, Cornelia Huck wrote:
Commit ef546f1275f6563e8934dd5e338d29d9f9909ca6 (virtio: add
feature checking helpers) introduced a helper __virtio_has_feature.
We don't want to use reserved identifiers, though, so let's
rename __virtio_has_feature to virtio_has_feature and virtio_has_feature
to virtio_vdev_has_feature.
Signed-off-by: Cornelia Huck cornelia.h...@de.ibm.com
---
hw/block/virtio-blk.c | 7 ---
hw/char/virtio-serial-bus.c | 2 +-
hw/net/vhost_net.c| 2 +-
hw/net/virtio-net.c | 31 ---
hw/scsi/virtio-scsi.c | 8
hw/virtio/dataplane/vring.c | 10 +-
hw/virtio/vhost.c | 4 ++--
hw/virtio/virtio-balloon.c| 2 +-
hw/virtio/virtio.c| 14 +++---
include/hw/virtio/virtio-access.h | 2 +-
include/hw/virtio/virtio.h| 9 +
11 files changed, 47 insertions(+), 44 deletions(-)
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 1556c9c..f9301ae 100644
--- a/hw/block/virtio-blk.c
+++ b/hw/block/virtio-blk.c
@@ -731,7 +731,7 @@ static uint64_t virtio_blk_get_features(VirtIODevice
*vdev, uint64_t features,
virtio_add_feature(features, VIRTIO_BLK_F_GEOMETRY);
virtio_add_feature(features, VIRTIO_BLK_F_TOPOLOGY);
virtio_add_feature(features, VIRTIO_BLK_F_BLK_SIZE);
-if (__virtio_has_feature(features, VIRTIO_F_VERSION_1)) {
+if (virtio_has_feature(features, VIRTIO_F_VERSION_1)) {
if (s-conf.scsi) {
error_setg(errp, Please set scsi=off for virtio-blk devices in
order to use virtio 1.0);
return 0;
@@ -782,10 +782,11 @@ static void virtio_blk_set_status(VirtIODevice *vdev,
uint8_t status)
*
* s-blk would erroneously be placed in writethrough mode.
*/
-if (!virtio_has_feature(vdev, VIRTIO_BLK_F_CONFIG_WCE)) {
+if (!virtio_vdev_has_feature(vdev, VIRTIO_BLK_F_CONFIG_WCE)) {
aio_context_acquire(blk_get_aio_context(s-blk));
blk_set_enable_write_cache(s-blk,
- virtio_has_feature(vdev,
VIRTIO_BLK_F_WCE));
+ virtio_vdev_has_feature(vdev,
+
VIRTIO_BLK_F_WCE));
aio_context_release(blk_get_aio_context(s-blk));
}
}
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
index bc56f5d..be97058 100644
--- a/hw/char/virtio-serial-bus.c
+++ b/hw/char/virtio-serial-bus.c
@@ -76,7 +76,7 @@ static VirtIOSerialPort *find_port_by_name(char *name)
static bool use_multiport(VirtIOSerial *vser)
{
VirtIODevice *vdev = VIRTIO_DEVICE(vser);
-return virtio_has_feature(vdev, VIRTIO_CONSOLE_F_MULTIPORT);
+return virtio_vdev_has_feature(vdev, VIRTIO_CONSOLE_F_MULTIPORT);
}
static size_t write_to_port(VirtIOSerialPort *port,
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
index 5c1d11f..1d76b94 100644
--- a/hw/net/vhost_net.c
+++ b/hw/net/vhost_net.c
@@ -197,7 +197,7 @@ static int vhost_net_set_vnet_endian(VirtIODevice *dev,
NetClientState *peer,
{
int r = 0;
-if (virtio_has_feature(dev, VIRTIO_F_VERSION_1) ||
+if (virtio_vdev_has_feature(dev, VIRTIO_F_VERSION_1) ||
(virtio_legacy_is_cross_endian(dev) !virtio_is_big_endian(dev))) {
r = qemu_set_vnet_le(peer, set);
if (r) {
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 1510839..628074e 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -86,8 +86,8 @@ static void virtio_net_set_config(VirtIODevice *vdev, const
uint8_t *config)
memcpy(netcfg, config, n-config_size);
-if (!virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_MAC_ADDR)
-!virtio_has_feature(vdev, VIRTIO_F_VERSION_1)
+if (!virtio_vdev_has_feature(vdev, VIRTIO_NET_F_CTRL_MAC_ADDR)
+!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)
memcmp(netcfg.mac, n-mac, ETH_ALEN)) {
memcpy(n-mac, netcfg.mac, ETH_ALEN);
qemu_format_nic_info_str(qemu_get_queue(n-nic), n-mac);
@@ -304,7 +304,7 @@ static RxFilterInfo
*virtio_net_query_rxfilter(NetClientState *nc)
info-multicast_table = str_list;
info-vlan_table = get_vlan_table(n);
-if (!virtio_has_feature(vdev, VIRTIO_NET_F_CTRL_VLAN)) {
+if (!virtio_vdev_has_feature(vdev, VIRTIO_NET_F_CTRL_VLAN)) {
info-vlan = RX_STATE_ALL;
} else if (!info-vlan_table) {
info-vlan = RX_STATE_NONE;
@@ -529,13 +529,13 @@ static void virtio_net_set_features(VirtIODevice *vdev,
uint64_t features)
int i;
virtio_net_set_multiqueue(n,
- __virtio_has_feature(features,
VIRTIO_NET_F_MQ));
+ virtio_has_feature(features, VIRTIO_NET_F_MQ));
Re: [Qemu-devel] [PATCH for-2.5 15/18] pc: Remove redundant arguments from xen_hvm_init()
On Fri, Aug 07, 2015 at 04:55:56PM -0300, Eduardo Habkost wrote:
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
hw/i386/pc_piix.c| 4 +---
hw/i386/pc_q35.c | 4 +---
include/hw/xen/xen.h | 4 ++--
xen-hvm.c| 25 -
4 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ce51cd1..d964f8d 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -134,9 +134,7 @@ static void pc_init1(MachineState *machine)
pcms-below_4g_mem_size = machine-ram_size;
}
-if (xen_enabled() xen_hvm_init(pcms-below_4g_mem_size,
- pcms-above_4g_mem_size,
- ram_memory) != 0) {
+if (xen_enabled() xen_hvm_init(pcms, ram_memory) != 0) {
fprintf(stderr, xen hardware virtual machine initialisation
failed\n);
exit(1);
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index cd4ecc3..b7b8709 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -125,9 +125,7 @@ static void pc_q35_init(MachineState *machine)
pcms-below_4g_mem_size = machine-ram_size;
}
-if (xen_enabled() xen_hvm_init(pcms-below_4g_mem_size,
- pcms-above_4g_mem_size,
- ram_memory) != 0) {
+if (xen_enabled() xen_hvm_init(pcms, ram_memory) != 0) {
fprintf(stderr, xen hardware virtual machine initialisation
failed\n);
exit(1);
}
diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h
index 4356af4..e90931a 100644
--- a/include/hw/xen/xen.h
+++ b/include/hw/xen/xen.h
@@ -10,6 +10,7 @@
#include hw/irq.h
#include qemu-common.h
+#include qemu/typedefs.h
/* xen-machine.c */
enum xen_mode {
@@ -38,8 +39,7 @@ qemu_irq *xen_interrupt_controller_init(void);
void xenstore_store_pv_console_info(int i, struct CharDriverState *chr);
#if defined(NEED_CPU_H) !defined(CONFIG_USER_ONLY)
-int xen_hvm_init(ram_addr_t *below_4g_mem_size, ram_addr_t
*above_4g_mem_size,
- MemoryRegion **ram_memory);
+int xen_hvm_init(PCMachineState *pcms, MemoryRegion **ram_memory);
void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
struct MemoryRegion *mr);
void xen_modified_memory(ram_addr_t start, ram_addr_t length);
diff --git a/xen-hvm.c b/xen-hvm.c
index 0408462..55bce3a 100644
--- a/xen-hvm.c
+++ b/xen-hvm.c
@@ -180,8 +180,7 @@ qemu_irq *xen_interrupt_controller_init(void)
/* Memory Ops */
-static void xen_ram_init(ram_addr_t *below_4g_mem_size,
- ram_addr_t *above_4g_mem_size,
+static void xen_ram_init(PCMachineState *pcms,
ram_addr_t ram_size, MemoryRegion **ram_memory_p)
{
MemoryRegion *sysmem = get_system_memory();
@@ -198,20 +197,20 @@ static void xen_ram_init(ram_addr_t *below_4g_mem_size,
}
if (ram_size = user_lowmem) {
-*above_4g_mem_size = ram_size - user_lowmem;
-*below_4g_mem_size = user_lowmem;
+pcms-above_4g_mem_size = ram_size - user_lowmem;
+pcms-below_4g_mem_size = user_lowmem;
} else {
-*above_4g_mem_size = 0;
-*below_4g_mem_size = ram_size;
+pcms-above_4g_mem_size = 0;
+pcms-below_4g_mem_size = ram_size;
}
-if (!*above_4g_mem_size) {
+if (!pcms-above_4g_mem_size) {
block_len = ram_size;
} else {
/*
* Xen does not allocate the memory continuously, it keeps a
* hole of the size computed above or passed in.
*/
-block_len = (1ULL 32) + *above_4g_mem_size;
+block_len = (1ULL 32) + pcms-above_4g_mem_size;
}
memory_region_init_ram(ram_memory, NULL, xen.ram, block_len,
error_abort);
@@ -229,12 +228,12 @@ static void xen_ram_init(ram_addr_t *below_4g_mem_size,
*/
memory_region_init_alias(ram_lo, NULL, xen.ram.lo,
ram_memory, 0xc,
- *below_4g_mem_size - 0xc);
+ pcms-below_4g_mem_size - 0xc);
memory_region_add_subregion(sysmem, 0xc, ram_lo);
-if (*above_4g_mem_size 0) {
+if (pcms-above_4g_mem_size 0) {
memory_region_init_alias(ram_hi, NULL, xen.ram.hi,
ram_memory, 0x1ULL,
- *above_4g_mem_size);
+ pcms-above_4g_mem_size);
memory_region_add_subregion(sysmem, 0x1ULL, ram_hi);
}
}
@@ -1159,7 +1158,7 @@ static void xen_wakeup_notifier(Notifier *notifier,
void *data)
}
/* return 0 means OK, or -1 means critical issue -- will exit(1) */
-int xen_hvm_init(ram_addr_t *below_4g_mem_size, ram_addr_t
[Qemu-devel] [PULL 13/27] i.MX: Split CCM emulator in a header file and a source file
From: Jean-Christophe Dubois j...@tribudubois.net
Signed-off-by: Jean-Christophe Dubois j...@tribudubois.net
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
b1d6f990229b2608bbaba24f4ff359571c0b07da.1437080501.git@tribudubois.net
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/arm/kzm.c | 2 +-
hw/misc/imx_ccm.c | 70 ++--
include/hw/arm/imx.h | 12 ++-
include/hw/misc/imx_ccm.h | 91 +++
4 files changed, 97 insertions(+), 78 deletions(-)
create mode 100644 include/hw/misc/imx_ccm.h
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index c906da7..d7af230 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -115,7 +115,7 @@ static void kzm_init(MachineState *machine)
imx_serial_create(0, 0x43f9, qdev_get_gpio_in(dev, 45));
imx_serial_create(1, 0x43f94000, qdev_get_gpio_in(dev, 32));
-ccm = sysbus_create_simple(imx_ccm, 0x53f8, NULL);
+ccm = sysbus_create_simple(TYPE_IMX_CCM, 0x53f8, NULL);
imx_timerp_create(0x53f94000, qdev_get_gpio_in(dev, 28), ccm);
imx_timerp_create(0x53f98000, qdev_get_gpio_in(dev, 27), ccm);
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
index 0920288..2e9bd9c 100644
--- a/hw/misc/imx_ccm.c
+++ b/hw/misc/imx_ccm.c
@@ -2,6 +2,7 @@
* IMX31 Clock Control Module
*
* Copyright (C) 2012 NICTA
+ * Updated by Jean-Christophe Dubois j...@tribudubois.net
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -10,10 +11,7 @@
* the CCM.
*/
-#include hw/hw.h
-#include hw/sysbus.h
-#include sysemu/sysemu.h
-#include hw/arm/imx.h
+#include hw/misc/imx_ccm.h
#define CKIH_FREQ 2600 /* 26MHz crystal input */
#define CKIL_FREQ32768 /* nominal 32khz clock */
@@ -29,30 +27,6 @@ do { printf(imx_ccm: fmt , ##args); } while (0)
static int imx_ccm_post_load(void *opaque, int version_id);
-#define TYPE_IMX_CCM imx_ccm
-#define IMX_CCM(obj) OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM)
-
-typedef struct IMXCCMState {
-SysBusDevice parent_obj;
-
-MemoryRegion iomem;
-
-uint32_t ccmr;
-uint32_t pdr0;
-uint32_t pdr1;
-uint32_t mpctl;
-uint32_t spctl;
-uint32_t cgr[3];
-uint32_t pmcr0;
-uint32_t pmcr1;
-
-/* Frequencies precalculated on register changes */
-uint32_t pll_refclk_freq;
-uint32_t mcu_clk_freq;
-uint32_t hsp_clk_freq;
-uint32_t ipg_clk_freq;
-} IMXCCMState;
-
static const VMStateDescription vmstate_imx_ccm = {
.name = imx-ccm,
.version_id = 1,
@@ -72,44 +46,6 @@ static const VMStateDescription vmstate_imx_ccm = {
.post_load = imx_ccm_post_load,
};
-/* CCMR */
-#define CCMR_FPME (10)
-#define CCMR_MPE (13)
-#define CCMR_MDS (17)
-#define CCMR_FPMF (126)
-#define CCMR_PRCS (31)
-
-/* PDR0 */
-#define PDR0_MCU_PODF_SHIFT (0)
-#define PDR0_MCU_PODF_MASK (0x7)
-#define PDR0_MAX_PODF_SHIFT (3)
-#define PDR0_MAX_PODF_MASK (0x7)
-#define PDR0_IPG_PODF_SHIFT (6)
-#define PDR0_IPG_PODF_MASK (0x3)
-#define PDR0_NFC_PODF_SHIFT (8)
-#define PDR0_NFC_PODF_MASK (0x7)
-#define PDR0_HSP_PODF_SHIFT (11)
-#define PDR0_HSP_PODF_MASK (0x7)
-#define PDR0_PER_PODF_SHIFT (16)
-#define PDR0_PER_PODF_MASK (0x1f)
-#define PDR0_CSI_PODF_SHIFT (23)
-#define PDR0_CSI_PODF_MASK (0x1ff)
-
-#define EXTRACT(value, name) (((value) PDR0_##name##_PODF_SHIFT) \
- PDR0_##name##_PODF_MASK)
-#define INSERT(value, name) (((value) PDR0_##name##_PODF_MASK) \
- PDR0_##name##_PODF_SHIFT)
-/* PLL control registers */
-#define PD(v) (((v) 26) 0xf)
-#define MFD(v) (((v) 16) 0x3ff)
-#define MFI(v) (((v) 10) 0xf);
-#define MFN(v) ((v) 0x3ff)
-
-#define PLL_PD(x) (((x) 0xf) 26)
-#define PLL_MFD(x) (((x) 0x3ff) 16)
-#define PLL_MFI(x) (((x) 0xf) 10)
-#define PLL_MFN(x) (((x) 0x3ff) 0)
-
uint32_t imx_clock_frequency(DeviceState *dev, IMXClk clock)
{
IMXCCMState *s = IMX_CCM(dev);
@@ -286,7 +222,7 @@ static int imx_ccm_init(SysBusDevice *dev)
IMXCCMState *s = IMX_CCM(dev);
memory_region_init_io(s-iomem, OBJECT(dev), imx_ccm_ops, s,
- imx_ccm, 0x1000);
+ TYPE_IMX_CCM, 0x1000);
sysbus_init_mmio(dev, s-iomem);
return 0;
diff --git a/include/hw/arm/imx.h b/include/hw/arm/imx.h
index ea9e093..b188560 100644
--- a/include/hw/arm/imx.h
+++ b/include/hw/arm/imx.h
@@ -11,17 +11,9 @@
#ifndef IMX_H
#define IMX_H
-void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
-
-typedef enum {
-NOCLK,
-MCU,
-HSP,
-IPG,
-CLK_32k
-} IMXClk;
+#include hw/misc/imx_ccm.h
-uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
+void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
void imx_timerp_create(const hwaddr addr,
[Qemu-devel] [PATCH v9 5/5] hw/arm/virt: Add gicversion option to virt machine
Add gic_version to VirtMachineState, set it to value of the option
and pass it around where necessary. Instantiate devices and fdt
nodes according to the choice.
max_cpus for virt machine increased to 126 (calculated from redistributor
space available in the memory map). GICv2 compatibility check happens
inside arm_gic_common_realize().
ITS regions are added to the memory map too, however currently they
are not used, just reserved.
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
hw/arm/virt.c | 111 +-
include/hw/arm/fdt.h | 2 +-
include/hw/arm/virt.h | 5 ++-
3 files changed, 96 insertions(+), 22 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 943e523..05bf130 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -49,6 +49,7 @@
#include hw/platform-bus.h
#include hw/arm/fdt.h
#include kvm_arm.h
+#include qapi/visitor.h
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 256
@@ -78,6 +79,7 @@ typedef struct {
typedef struct {
MachineState parent;
bool secure;
+int32_t gic_version;
} VirtMachineState;
#define TYPE_VIRT_MACHINE virt
@@ -108,6 +110,9 @@ static const MemMapEntry a15memmap[] = {
[VIRT_GIC_DIST] = { 0x0800, 0x0001 },
[VIRT_GIC_CPU] ={ 0x0801, 0x0001 },
[VIRT_GIC_V2M] ={ 0x0802, 0x1000 },
+[VIRT_ITS_CONTROL] ={ 0x0802, 0x0001 },
+[VIRT_ITS_TRANSLATION] ={ 0x0803, 0x0001 },
+[VIRT_GIC_REDIST] = { 0x0804, 0x00FC },
[VIRT_UART] = { 0x0900, 0x1000 },
[VIRT_RTC] ={ 0x0901, 0x1000 },
[VIRT_FW_CFG] = { 0x0902, 0x000a },
@@ -257,10 +262,13 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
* they are edge-triggered.
*/
ARMCPU *armcpu;
+uint32_t max;
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
+/* Argument is 32 bit but 8 bits are reserved for flags */
+max = (vbi-smp_cpus = 24) ? 24 : vbi-smp_cpus;
irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
- GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 vbi-smp_cpus) - 1);
+ GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 max) - 1);
qemu_fdt_add_subnode(vbi-fdt, /timer);
@@ -284,6 +292,18 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
{
int cpu;
+/*
+ * From Documentation/devicetree/bindings/arm/cpus.txt
+ * On ARM v8 64-bit systems value should be set to 2,
+ * that corresponds to the MPIDR_EL1 register size.
+ * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
+ * in the system, #address-cells can be set to 1, since
+ * MPIDR_EL1[63:32] bits are not used for CPUs
+ * identification.
+ *
+ * Now GIC500 doesn't support affinities 2 3 so currently
+ * #address-cells can stay 1 until future GIC
+ */
qemu_fdt_add_subnode(vbi-fdt, /cpus);
qemu_fdt_setprop_cell(vbi-fdt, /cpus, #address-cells, 0x1);
qemu_fdt_setprop_cell(vbi-fdt, /cpus, #size-cells, 0x0);
@@ -320,25 +340,36 @@ static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
qemu_fdt_setprop_cell(vbi-fdt, /intc/v2m, phandle, vbi-v2m_phandle);
}
-static void fdt_add_gic_node(VirtBoardInfo *vbi)
+static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
{
vbi-gic_phandle = qemu_fdt_alloc_phandle(vbi-fdt);
qemu_fdt_setprop_cell(vbi-fdt, /, interrupt-parent, vbi-gic_phandle);
qemu_fdt_add_subnode(vbi-fdt, /intc);
-/* 'cortex-a15-gic' means 'GIC v2' */
-qemu_fdt_setprop_string(vbi-fdt, /intc, compatible,
-arm,cortex-a15-gic);
qemu_fdt_setprop_cell(vbi-fdt, /intc, #interrupt-cells, 3);
qemu_fdt_setprop(vbi-fdt, /intc, interrupt-controller, NULL, 0);
-qemu_fdt_setprop_sized_cells(vbi-fdt, /intc, reg,
- 2, vbi-memmap[VIRT_GIC_DIST].base,
- 2, vbi-memmap[VIRT_GIC_DIST].size,
- 2, vbi-memmap[VIRT_GIC_CPU].base,
- 2, vbi-memmap[VIRT_GIC_CPU].size);
qemu_fdt_setprop_cell(vbi-fdt, /intc, #address-cells, 0x2);
qemu_fdt_setprop_cell(vbi-fdt, /intc, #size-cells, 0x2);
qemu_fdt_setprop(vbi-fdt, /intc, ranges, NULL, 0);
+if (type == 3) {
+qemu_fdt_setprop_string(vbi-fdt, /intc, compatible,
+arm,gic-v3);
+qemu_fdt_setprop_sized_cells(vbi-fdt, /intc, reg,
+ 2, vbi-memmap[VIRT_GIC_DIST].base,
+ 2, vbi-memmap[VIRT_GIC_DIST].size,
+ 2, vbi-memmap[VIRT_GIC_REDIST].base,
+ 2, vbi-memmap[VIRT_GIC_REDIST].size);
+} else {
+/* 'cortex-a15-gic' means 'GIC v2' */
+
[Qemu-devel] Win32 stdio not working if SDL is enabled
When debugging some patches on Windows, I discovered that nothing printed
to stderr ever appears on the console. Eventually I discovered that if I
build with --disable-sdl, then stderr appears just fine.
Looking at the code in vl.c I see a hack for SDL introduced in
commit 59a36a2f6728081050afc6ec97d0018467999f79
Author: Stefan Weil w...@mail.berlios.de
Date: Thu Jun 18 20:11:03 2009 +0200
Win32: Fix compilation with SDL.
If I mostly kill the hack from vl.c, and just leave a plain '#undef main'
then I get working console stderr once again.
eg I applied
diff --git a/vl.c b/vl.c
index 0adbbd6..8e1481b 100644
--- a/vl.c
+++ b/vl.c
@@ -39,16 +39,8 @@
#endif
#ifdef CONFIG_SDL
-#if defined(__APPLE__) || defined(main)
#include SDL.h
-int qemu_main(int argc, char **argv, char **envp);
-int main(int argc, char **argv)
-{
-return qemu_main(argc, argv, NULL);
-}
#undef main
-#define main qemu_main
-#endif
#endif /* CONFIG_SDL */
#ifdef CONFIG_COCOA
FWIW, I'm building on Fedora 22 using
# ./configure --cross-prefix=i686-w64-mingw32- \
--prefix=$HOME/usr/qemu-git-win32 \
--target-list=x86_64-softmmu \
--disable-libusb --disable-usb-redir
Which has
mingw32-SDL-1.2.15-5.fc21.noarch
To test I just run
C: qemu-system-x86_64 -object foobar
qemu-system-x86_64: -object foobar: Parameter 'id' is missing
to get it to print an error about bad -object arg. The message
never appears unless I apply that patch above, though I lack any
explanation as to why this is happening, aside from SDL black magic
Regards,
Daniel
--
|: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :|
|: http://libvirt.org -o- http://virt-manager.org :|
|: http://autobuild.org -o- http://search.cpan.org/~danberr/ :|
|: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
[Qemu-devel] [PULL 04/24] pc: Use PC_COMPAT_* for CPUID feature compatibility
From: Eduardo Habkost ehabk...@redhat.com
Now we can use compat_props to keep CPUID feature compatibility, using
the boolean QOM properties for CPUID feature flags.
This simplifies the compatibility code, and reduces duplication between
pc_piix.c and pc_q35.c.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 114 ++-
hw/i386/pc_piix.c| 22 --
hw/i386/pc_q35.c | 22 --
3 files changed, 112 insertions(+), 46 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 954203d..1dca7e7 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -374,11 +374,111 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t
*);
#define PC_COMPAT_2_2 \
PC_COMPAT_2_3 \
-HW_COMPAT_2_2
+HW_COMPAT_2_2 \
+{\
+.driver = kvm64 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = kvm32 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Conroe - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Penryn - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Nehalem - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Westmere - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = SandyBridge - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Haswell - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Broadwell - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Opteron_G1 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Opteron_G2 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Opteron_G3 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Opteron_G4 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Opteron_G5 - TYPE_X86_CPU,\
+.property = vme,\
+.value = off,\
+},\
+{\
+.driver = Haswell - TYPE_X86_CPU,\
+.property = f16c,\
+.value = off,\
+},\
+{\
+.driver = Haswell - TYPE_X86_CPU,\
+.property = rdrand,\
+.value = off,\
+},\
+{\
+.driver = Broadwell - TYPE_X86_CPU,\
+.property = f16c,\
+.value = off,\
+},\
+{\
+.driver = Broadwell - TYPE_X86_CPU,\
+.property = rdrand,\
+.value = off,\
+},
#define PC_COMPAT_2_1 \
PC_COMPAT_2_2 \
-HW_COMPAT_2_1
+HW_COMPAT_2_1 \
+{\
+.driver = coreduo - TYPE_X86_CPU,\
+.property = vmx,\
+.value = on,\
+},\
+{\
+.driver = core2duo - TYPE_X86_CPU,\
+.property = vmx,\
+.value = on,\
+},
#define PC_COMPAT_2_0 \
PC_COMPAT_2_1 \
@@ -589,6 +689,16 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = 486- TYPE_X86_CPU,\
.property = model,\
.value= stringify(0),\
+},\
+{\
+.driver = n270 - TYPE_X86_CPU,\
+.property = movbe,\
+.value = off,\
+},\
+{\
+.driver = Westmere - TYPE_X86_CPU,\
+.property = pclmulqdq,\
+.value = off,\
},
static inline void pc_common_machine_options(MachineClass *m)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index a896624..482555f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -319,24 +319,6 @@ static void pc_compat_2_2(MachineState *machine)
{
pc_compat_2_3(machine);
rsdp_in_ram = false;
-x86_cpu_compat_set_features(kvm64, FEAT_1_EDX, 0, CPUID_VME);
-x86_cpu_compat_set_features(kvm32, FEAT_1_EDX, 0, CPUID_VME);
-x86_cpu_compat_set_features(Conroe, FEAT_1_EDX, 0, CPUID_VME);
-x86_cpu_compat_set_features(Penryn, FEAT_1_EDX, 0, CPUID_VME);
-x86_cpu_compat_set_features(Nehalem, FEAT_1_EDX, 0, CPUID_VME);
-x86_cpu_compat_set_features(Westmere, FEAT_1_EDX, 0, CPUID_VME);
-
[Qemu-devel] [PULL 14/24] pc: Use PCMachineState as pc_guest_info_init() argument
From: Eduardo Habkost ehabk...@redhat.com
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 3 +--
hw/i386/pc.c | 7 +++
hw/i386/pc_piix.c| 3 +--
hw/i386/pc_q35.c | 3 +--
4 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e1d20ad..94d7afb 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -165,8 +165,7 @@ void pc_cpus_init(const char *cpu_model, DeviceState
*icc_bridge);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);
-PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
-ram_addr_t above_4g_mem_size);
+PcGuestInfo *pc_guest_info_init(PCMachineState *pcms);
void pc_set_legacy_acpi_data_size(void);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a9a9cf4..081ef83 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1189,15 +1189,14 @@ void pc_guest_info_machine_done(Notifier *notifier,
void *data)
acpi_setup(guest_info_state-info);
}
-PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
-ram_addr_t above_4g_mem_size)
+PcGuestInfo *pc_guest_info_init(PCMachineState *pcms)
{
PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
PcGuestInfo *guest_info = guest_info_state-info;
int i, j;
-guest_info-ram_size_below_4g = below_4g_mem_size;
-guest_info-ram_size = below_4g_mem_size + above_4g_mem_size;
+guest_info-ram_size_below_4g = pcms-below_4g_mem_size;
+guest_info-ram_size = pcms-below_4g_mem_size + pcms-above_4g_mem_size;
guest_info-apic_id_limit = pc_apic_id_limit(max_cpus);
guest_info-apic_xrupt_override = kvm_allows_irq0_override();
guest_info-numa_nodes = nb_numa_nodes;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 559f4e5..9364c47 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -160,8 +160,7 @@ static void pc_init1(MachineState *machine)
rom_memory = system_memory;
}
-guest_info = pc_guest_info_init(pcms-below_4g_mem_size,
-pcms-above_4g_mem_size);
+guest_info = pc_guest_info_init(pcms);
guest_info-has_acpi_build = has_acpi_build;
guest_info-legacy_acpi_table_size = legacy_acpi_table_size;
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 489dfcb..af5fd9f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -151,8 +151,7 @@ static void pc_q35_init(MachineState *machine)
rom_memory = get_system_memory();
}
-guest_info = pc_guest_info_init(pcms-below_4g_mem_size,
-pcms-above_4g_mem_size);
+guest_info = pc_guest_info_init(pcms);
guest_info-isapc_ram_fw = false;
guest_info-has_acpi_build = has_acpi_build;
guest_info-has_reserved_memory = has_reserved_memory;
--
MST
[Qemu-devel] [PULL 18/24] pci: allow 0 address for PCI IO/MEM regions
From: Laurent Vivier lviv...@redhat.com
Some kernels program a 0 address for io regions. PCI 3.0 spec
section 6.2.5.1 doesn't seem to disallow this.
based on patch by Michael Roth mdr...@linux.vnet.ibm.com
Add pci_allow_0_addr in MachineClass to conditionally
allow addr 0 for pseries, as this can break other architectures.
This patch allows to hotplug PCI card in pseries machine, as the first
added card BAR0 is always set to 0 address.
This as a temporary hack, waiting to fix PCI memory priorities for more
machine types...
Signed-off-by: Laurent Vivier lviv...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/boards.h | 3 ++-
hw/pci/pci.c| 12 +---
hw/ppc/spapr.c | 1 +
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 2aec9cb..3f84afd 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -100,7 +100,8 @@ struct MachineClass {
no_cdrom:1,
no_sdcard:1,
has_dynamic_sysbus:1,
-no_tco:1;
+no_tco:1,
+pci_allow_0_address:1;
int is_default;
const char *default_machine_opts;
const char *default_boot_order;
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index a017614..9f57aea 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -38,6 +38,7 @@
#include hw/pci/msix.h
#include exec/address-spaces.h
#include hw/hotplug.h
+#include hw/boards.h
//#define DEBUG_PCI
#ifdef DEBUG_PCI
@@ -1065,6 +1066,10 @@ static pcibus_t pci_bar_address(PCIDevice *d,
pcibus_t new_addr, last_addr;
int bar = pci_bar(d, reg);
uint16_t cmd = pci_get_word(d-config + PCI_COMMAND);
+Object *machine = qdev_get_machine();
+ObjectClass *oc = object_get_class(machine);
+MachineClass *mc = MACHINE_CLASS(oc);
+bool allow_0_address = mc-pci_allow_0_address;
if (type PCI_BASE_ADDRESS_SPACE_IO) {
if (!(cmd PCI_COMMAND_IO)) {
@@ -1075,7 +1080,8 @@ static pcibus_t pci_bar_address(PCIDevice *d,
/* Check if 32 bit BAR wraps around explicitly.
* TODO: make priorities correct and remove this work around.
*/
-if (last_addr = new_addr || new_addr == 0 || last_addr = UINT32_MAX)
{
+if (last_addr = new_addr || last_addr = UINT32_MAX ||
+(!allow_0_address new_addr == 0)) {
return PCI_BAR_UNMAPPED;
}
return new_addr;
@@ -1099,8 +1105,8 @@ static pcibus_t pci_bar_address(PCIDevice *d,
/* XXX: as we cannot support really dynamic
mappings, we handle specific values as invalid
mappings. */
-if (last_addr = new_addr || new_addr == 0 ||
-last_addr == PCI_BAR_UNMAPPED) {
+if (last_addr = new_addr || last_addr == PCI_BAR_UNMAPPED ||
+(!allow_0_address new_addr == 0)) {
return PCI_BAR_UNMAPPED;
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a6f1947..bf0c64f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1835,6 +1835,7 @@ static void spapr_machine_class_init(ObjectClass *oc,
void *data)
mc-default_ram_size = 512 * M_BYTE;
mc-kvm_type = spapr_kvm_type;
mc-has_dynamic_sysbus = true;
+mc-pci_allow_0_address = true;
fwc-get_dev_path = spapr_get_fw_dev_path;
nc-nmi_monitor_handler = spapr_nmi;
--
MST
[Qemu-devel] [PULL 17/24] pc: Remove redundant arguments from pc_memory_init()
From: Eduardo Habkost ehabk...@redhat.com
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 2 --
hw/i386/pc.c | 18 +-
hw/i386/pc_piix.c| 1 -
hw/i386/pc_q35.c | 1 -
4 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index a56f70c..d0cad87 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -184,8 +184,6 @@ FWCfgState *xen_load_linux(PCMachineState *pcms,
PcGuestInfo *guest_info);
FWCfgState *pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
- ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
MemoryRegion *rom_memory,
MemoryRegion **ram_memory,
PcGuestInfo *guest_info);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 681ea85..0c828e4 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1285,8 +1285,6 @@ FWCfgState *xen_load_linux(PCMachineState *pcms,
FWCfgState *pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
- ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
MemoryRegion *rom_memory,
MemoryRegion **ram_memory,
PcGuestInfo *guest_info)
@@ -1297,7 +1295,8 @@ FWCfgState *pc_memory_init(PCMachineState *pcms,
FWCfgState *fw_cfg;
MachineState *machine = MACHINE(pcms);
-assert(machine-ram_size == below_4g_mem_size + above_4g_mem_size);
+assert(machine-ram_size == pcms-below_4g_mem_size +
+pcms-above_4g_mem_size);
linux_boot = (machine-kernel_filename != NULL);
@@ -1311,16 +1310,17 @@ FWCfgState *pc_memory_init(PCMachineState *pcms,
*ram_memory = ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, NULL, ram-below-4g, ram,
- 0, below_4g_mem_size);
+ 0, pcms-below_4g_mem_size);
memory_region_add_subregion(system_memory, 0, ram_below_4g);
-e820_add_entry(0, below_4g_mem_size, E820_RAM);
-if (above_4g_mem_size 0) {
+e820_add_entry(0, pcms-below_4g_mem_size, E820_RAM);
+if (pcms-above_4g_mem_size 0) {
ram_above_4g = g_malloc(sizeof(*ram_above_4g));
memory_region_init_alias(ram_above_4g, NULL, ram-above-4g, ram,
- below_4g_mem_size, above_4g_mem_size);
+ pcms-below_4g_mem_size,
+ pcms-above_4g_mem_size);
memory_region_add_subregion(system_memory, 0x1ULL,
ram_above_4g);
-e820_add_entry(0x1ULL, above_4g_mem_size, E820_RAM);
+e820_add_entry(0x1ULL, pcms-above_4g_mem_size, E820_RAM);
}
if (!guest_info-has_reserved_memory
@@ -1353,7 +1353,7 @@ FWCfgState *pc_memory_init(PCMachineState *pcms,
}
pcms-hotplug_memory.base =
-ROUND_UP(0x1ULL + above_4g_mem_size, 1ULL 30);
+ROUND_UP(0x1ULL + pcms-above_4g_mem_size, 1ULL 30);
if (pcms-enforce_aligned_dimm) {
/* size hotplug region assuming 1G page max alignment per slot */
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c98635f..ce51cd1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -179,7 +179,6 @@ static void pc_init1(MachineState *machine)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, system_memory,
- pcms-below_4g_mem_size, pcms-above_4g_mem_size,
rom_memory, ram_memory, guest_info);
} else if (machine-kernel_filename != NULL) {
/* For xen HVM direct kernel boot, load linux here */
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 79e3f9b..cd4ecc3 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -171,7 +171,6 @@ static void pc_q35_init(MachineState *machine)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, get_system_memory(),
- pcms-below_4g_mem_size, pcms-above_4g_mem_size,
rom_memory, ram_memory, guest_info);
}
--
MST
[Qemu-devel] [PULL 24/24] MAINTAINERS: list smbios maintainers
Now that smbios has its own directory, list its maintainers. Same people as ACPI so just reuse that entry. Signed-off-by: Michael S. Tsirkin m...@redhat.com --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 978b717..a059d5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -645,13 +645,15 @@ S: Supported F: include/hw/pci/* F: hw/pci/* -ACPI +ACPI/SMBIOS M: Michael S. Tsirkin m...@redhat.com M: Igor Mammedov imamm...@redhat.com S: Supported F: include/hw/acpi/* +F: include/hw/smbios/* F: hw/mem/* F: hw/acpi/* +F: hw/smbios/* F: hw/i386/acpi-build.[hc] F: hw/i386/*dsl F: hw/arm/virt-acpi-build.c -- MST
Re: [Qemu-devel] [PATCH 1/5] migration/ram.c: Use RAMBlock rather than MemoryRegion
On 13/08/2015 12:51, Dr. David Alan Gilbert (git) wrote:
From: Dr. David Alan Gilbert dgilb...@redhat.com
RAM migration mainly works on RAMBlocks but in a few places
uses data from MemoryRegions to access the same information that's
already held in RAMBlocks; clean it up just to avoid the
MemoryRegion use.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
migration/ram.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 7f007e6..7df9157 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -497,13 +497,13 @@ static int save_xbzrle_page(QEMUFile *f, uint8_t
**current_data,
/* Called with rcu_read_lock() to protect migration_bitmap */
static inline
-ram_addr_t migration_bitmap_find_and_reset_dirty(MemoryRegion *mr,
+ram_addr_t migration_bitmap_find_and_reset_dirty(RAMBlock *rb,
ram_addr_t start)
{
-unsigned long base = mr-ram_addr TARGET_PAGE_BITS;
+unsigned long base = rb-offset TARGET_PAGE_BITS;
unsigned long nr = base + (start TARGET_PAGE_BITS);
-uint64_t mr_size = TARGET_PAGE_ALIGN(memory_region_size(mr));
-unsigned long size = base + (mr_size TARGET_PAGE_BITS);
+uint64_t rb_size = rb-used_length;
+unsigned long size = base + (rb_size TARGET_PAGE_BITS);
unsigned long *bitmap;
unsigned long next;
@@ -573,7 +573,7 @@ static void migration_bitmap_sync(void)
qemu_mutex_lock(migration_bitmap_mutex);
rcu_read_lock();
QLIST_FOREACH_RCU(block, ram_list.blocks, next) {
-migration_bitmap_sync_range(block-mr-ram_addr, block-used_length);
+migration_bitmap_sync_range(block-offset, block-used_length);
}
rcu_read_unlock();
qemu_mutex_unlock(migration_bitmap_mutex);
@@ -668,12 +668,11 @@ static int ram_save_page(QEMUFile *f, RAMBlock* block,
ram_addr_t offset,
int pages = -1;
uint64_t bytes_xmit;
ram_addr_t current_addr;
-MemoryRegion *mr = block-mr;
uint8_t *p;
int ret;
bool send_async = true;
-p = memory_region_get_ram_ptr(mr) + offset;
+p = block-host + offset;
/* In doubt sent page as normal */
bytes_xmit = 0;
@@ -744,7 +743,7 @@ static int do_compress_ram_page(CompressParam *param)
RAMBlock *block = param-block;
ram_addr_t offset = param-offset;
-p = memory_region_get_ram_ptr(block-mr) + (offset TARGET_PAGE_MASK);
+p = block-host + (offset TARGET_PAGE_MASK);
bytes_sent = save_page_header(param-file, block, offset |
RAM_SAVE_FLAG_COMPRESS_PAGE);
@@ -852,11 +851,10 @@ static int ram_save_compressed_page(QEMUFile *f,
RAMBlock *block,
{
int pages = -1;
uint64_t bytes_xmit;
-MemoryRegion *mr = block-mr;
uint8_t *p;
int ret;
-p = memory_region_get_ram_ptr(mr) + offset;
+p = block-host + offset;
bytes_xmit = 0;
ret = ram_control_save_page(f, block-offset,
@@ -929,14 +927,12 @@ static int ram_find_and_save_block(QEMUFile *f, bool
last_stage,
ram_addr_t offset = last_offset;
bool complete_round = false;
int pages = 0;
-MemoryRegion *mr;
if (!block)
block = QLIST_FIRST_RCU(ram_list.blocks);
while (true) {
-mr = block-mr;
-offset = migration_bitmap_find_and_reset_dirty(mr, offset);
+offset = migration_bitmap_find_and_reset_dirty(block, offset);
if (complete_round block == last_seen_block
offset = last_offset) {
break;
@@ -1344,7 +1340,7 @@ static inline void *host_from_stream_offset(QEMUFile *f,
return NULL;
}
-return memory_region_get_ram_ptr(block-mr) + offset;
+return block-host + offset;
}
len = qemu_get_byte(f);
@@ -1354,7 +1350,7 @@ static inline void *host_from_stream_offset(QEMUFile *f,
QLIST_FOREACH_RCU(block, ram_list.blocks, next) {
if (!strncmp(id, block-idstr, sizeof(id))
block-max_length offset) {
-return memory_region_get_ram_ptr(block-mr) + offset;
+return block-host + offset;
}
}
Acked-by: Paolo Bonzini pbonz...@redhat.com
It would be nice in a follow-up patch to move RAMBlock-related
definitions into include/exec/ram_addr.h.
Paolo
Re: [Qemu-devel] [PATCH 05/10] cpu-exec: elide more icount code if CONFIG_USER_ONLY
On 12/08/2015 18:40, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
cpu-exec.c | 6 ++
1 file changed, 6 insertions(+)
What about the icount part in CPUState and the tb_start/end ?
Can't this be removed as well?
Fred
diff --git a/cpu-exec.c b/cpu-exec.c
index 599e64d..bde5fd1 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -228,6 +228,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu,
uint8_t *tb_ptr)
return next_tb;
}
+#if defined(CONFIG_SOFTMMU)
/* Execute the code without caching the generated code. An interpreter
could be used if available. */
static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
@@ -251,6 +252,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
tb_phys_invalidate(tb, -1);
tb_free(tb);
}
+#endif
static TranslationBlock *tb_find_slow(CPUState *cpu,
target_ulong pc,
@@ -523,6 +525,9 @@ int cpu_exec(CPUState *cpu)
case TB_EXIT_ICOUNT_EXPIRED:
{
/* Instruction counter expired. */
+#ifdef CONFIG_USER_ONLY
+abort();
+#else
int insns_left = cpu-icount_decr.u32;
if (cpu-icount_extra insns_left = 0) {
/* Refill decrementer and continue execution. */
@@ -542,6 +547,7 @@ int cpu_exec(CPUState *cpu)
cpu_loop_exit(cpu);
}
break;
+#endif
}
default:
break;
[Qemu-devel] [PULL 03/24] piix: Document coreboot-specific RAM size config register
From: Eduardo Habkost ehabk...@redhat.com
The existing i440fx initialization code sets a PCI config register that
isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is
DRAMC (DRAM Control) and has nothing to do with the RAM size.
This was implemented in commit ec5f92ce6ac8ec09056be77e03c941be188648fa
because old coreboot code tried to read registers 0x5a-0x5f,0x56,0x57 to
get the RAM size from QEMU, but I couldn't find out why coreboot did
that. I assume it was a mistake, and the original code was supposed to
be reading the DRB[0-7] registers (offsets 0x60-0x67).
Document that coreboot-specific register offset in a macro and a
comment, for future reference.
Cc: Ed Swierk eswi...@skyportsystems.com
Cc: Richard Smith smithb...@gmail.com
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/pci-host/piix.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index ad55f99..1cb25f3 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -117,6 +117,11 @@ struct PCII440FXState {
#define I440FX_PAM_SIZE 7
#define I440FX_SMRAM0x72
+/* Older coreboot versions (4.0 and older) read a config register that doesn't
+ * exist in real hardware, to get the RAM size from QEMU.
+ */
+#define I440FX_COREBOOT_RAM_SIZE 0x57
+
static void piix3_set_irq(void *opaque, int pirq, int level);
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
static void piix3_write_config_xen(PCIDevice *dev,
@@ -394,7 +399,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
if (ram_size 255) {
ram_size = 255;
}
-d-config[0x57] = ram_size;
+d-config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
i440fx_update_memory_mappings(f);
--
MST
[Qemu-devel] [PULL 02/24] make: load only required dependency files.
From: Victor Kaplansky vict...@redhat.com The old rules.mak loads dependency .d files using include directive with file glob pattern *.d. This breaks the build when build tree has left-over *.d files from another build. This patch fixes this by - loading precise list of .d files made from *.o and *.mo. - specifying explicit list of required dependency info files for *.hex autogenerated sources. Note that Makefile still includes some .d in root directory by including *.d. Signed-off-by: Victor Kaplansky vict...@redhat.com Reviewed-by: Michael S. Tsirkin m...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/i386/Makefile.objs | 8 +++- rules.mak | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index bd4f147..ecdb400 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -7,8 +7,14 @@ obj-$(CONFIG_XEN) += ../xenpv/ xen/ obj-y += kvmvapic.o obj-y += acpi-build.o + +gen-hex-y += hw/i386/acpi-dsdt.hex +gen-hex-y += hw/i386/q35-acpi-dsdt.hex + hw/i386/acpi-build.o: hw/i386/acpi-build.c \ - hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex + $(gen-hex-y) + +-include $(gen-hex-y:.hex=.d) iasl-option=$(shell if test -z `$(1) $(2) 21 /dev/null` \ ; then echo $(2); else echo $(3); fi ;) diff --git a/rules.mak b/rules.mak index 6e35c36..4551b9e 100644 --- a/rules.mak +++ b/rules.mak @@ -368,6 +368,6 @@ define unnest-vars $(error $o added in $v but $o-objs is not set))) $(shell mkdir -p ./ $(sort $(dir $($v # Include all the .d files -$(eval -include $(addsuffix *.d, $(sort $(dir $($v) +$(eval -include $(patsubst %.o,%.d,$(patsubst %.mo,%.d,$($v $(eval $v := $(filter-out %/,$($v endef -- MST
Re: [Qemu-devel] Win32 stdio not working if SDL is enabled
Hello! Looking at the code in vl.c I see a hack for SDL introduced in commit 59a36a2f6728081050afc6ec97d0018467999f79 Author: Stefan Weil w...@mail.berlios.de Date: Thu Jun 18 20:11:03 2009 +0200 Win32: Fix compilation with SDL. Just a hint which may have to do with this. Looks like SDL introduces its own entry point, but it's WinMain() instead of main(). In this case standard CRT setup is omitted. But it is very easy to recover in this case. Just call: freopen(CONOUT$, w, stderr); This performs the necessary setup and relinks CRT's stderr with Windows console stream. It is a well known hack. More info here: http://stackoverflow.com/questions/9020790/using-stdin-with-an-allocconsole Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia
[Qemu-devel] [PULL 00/24] virtio,pc,acpi fixes, cleanups
The following changes since commit 5c79ae3615d5dafdf1bb09b7a356a3a005714e3d:
Update version for v2.4.0 release (2015-08-11 15:30:34 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch changes up to d31e5ae7f2c16de2caf752b7f7f903569fea894d:
MAINTAINERS: list smbios maintainers (2015-08-13 14:08:31 +0300)
virtio,pc,acpi fixes, cleanups
Mostly cleanups, notably Eduardo's compat code rework,
and smbios rearrangement for use by ARM.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Daniel P. Berrange (1):
acpi: avoid potential uninitialized access to cpu_hp_io_base
Eduardo Habkost (15):
piix: Document coreboot-specific RAM size config register
pc: Use PC_COMPAT_* for CPUID feature compatibility
target-i386: Remove x86_cpu_compat_set_features()
pc: Use error_abort when registering properties
pc: Rename pc_machine variables to pcms
pc: Move PCMachineClass, PCMachineState to qemu/typedefs.h
pc: Eliminate pc_common_machine_options()
pc: Eliminate pc_default_machine_options()
pc: Use PCMachineState for pc_cmos_init() argument
pc: Use PCMachineState for pc_memory_init() argument
pc: Move {above,below}_4g_mem_size variables to PCMachineState
pc: Use PCMachineState as pc_guest_info_init() argument
pc: Remove redundant arguments from *load_linux()
pc: Remove redundant arguments from pc_cmos_init()
pc: Remove redundant arguments from pc_memory_init()
Jason Wang (1):
virtio-net: remove useless codes
Laurent Vivier (1):
pci: allow 0 address for PCI IO/MEM regions
Michael S. Tsirkin (1):
MAINTAINERS: list smbios maintainers
Victor Kaplansky (2):
make: fix where dependency *.d are stored.
make: load only required dependency files.
Wei Huang (3):
smbios: extract x86 smbios building code into a function
smbios: remove dependency on x86 e820 tables
smbios: move smbios code into a common folder
include/hw/boards.h | 3 +-
include/hw/i386/pc.h | 146 +---
include/hw/{i386 = smbios}/smbios.h | 10 ++-
include/hw/virtio/virtio-net.h | 1 -
include/qemu/typedefs.h | 2 +
target-i386/cpu.h| 3 -
arch_init.c | 2 +-
hw/i386/acpi-build.c | 1 +
hw/i386/pc.c | 156 +++
hw/i386/pc_piix.c| 77 ++---
hw/i386/pc_q35.c | 69 +---
hw/net/virtio-net.c | 8 +-
hw/pci-host/piix.c | 7 +-
hw/pci/pci.c | 12 ++-
hw/ppc/spapr.c | 1 +
hw/{i386 = smbios}/smbios.c | 19 ++---
target-i386/cpu.c| 26 --
tests/bios-tables-test.c | 2 +-
vl.c | 2 +-
MAINTAINERS | 4 +-
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/Makefile.objs | 1 +
hw/i386/Makefile.objs| 10 ++-
hw/i386/acpi-dsdt.dsl| 1 -
hw/i386/q35-acpi-dsdt.dsl| 1 +
hw/smbios/Makefile.objs | 1 +
rules.mak| 4 +-
28 files changed, 312 insertions(+), 259 deletions(-)
rename include/hw/{i386 = smbios}/smbios.h (95%)
rename hw/{i386 = smbios}/smbios.c (98%)
create mode 100644 hw/smbios/Makefile.objs
[Qemu-devel] [PULL 08/24] pc: Move PCMachineClass, PCMachineState to qemu/typedefs.h
From: Eduardo Habkost ehabk...@redhat.com
They will be used inside hw/xen/xen.h, which doesn't include
hw/i386/pc.h.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h| 4 +---
include/qemu/typedefs.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 1dca7e7..6746097 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -2,6 +2,7 @@
#define HW_PC_H
#include qemu-common.h
+#include qemu/typedefs.h
#include exec/memory.h
#include hw/boards.h
#include hw/isa/isa.h
@@ -61,9 +62,6 @@ struct PCMachineClass {
DeviceState *dev);
};
-typedef struct PCMachineState PCMachineState;
-typedef struct PCMachineClass PCMachineClass;
-
#define TYPE_PC_MACHINE generic-pc-machine
#define PC_MACHINE(obj) \
OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 6fdcbcd..f8a9dd6 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -58,6 +58,8 @@ typedef struct PCIESlot PCIESlot;
typedef struct PCIExpressDevice PCIExpressDevice;
typedef struct PCIExpressHost PCIExpressHost;
typedef struct PCIHostState PCIHostState;
+typedef struct PCMachineState PCMachineState;
+typedef struct PCMachineClass PCMachineClass;
typedef struct PCMCIACardState PCMCIACardState;
typedef struct PixelFormat PixelFormat;
typedef struct PropertyInfo PropertyInfo;
--
MST
[Qemu-devel] [PULL 05/24] target-i386: Remove x86_cpu_compat_set_features()
From: Eduardo Habkost ehabk...@redhat.com
The function is not used by PC code anymore and can be removed.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
target-i386/cpu.h | 3 ---
target-i386/cpu.c | 26 --
2 files changed, 29 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ead2832..74b674d 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1332,9 +1332,6 @@ void cpu_smm_update(X86CPU *cpu);
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
-void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
- uint32_t feat_add, uint32_t feat_remove);
-
void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features);
void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 7a779b1..cfb8aa7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1392,32 +1392,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
};
-/**
- * x86_cpu_compat_set_features:
- * @cpu_model: CPU model name to be changed. If NULL, all CPU models are
changed
- * @w: Identifies the feature word to be changed.
- * @feat_add: Feature bits to be added to feature word
- * @feat_remove: Feature bits to be removed from feature word
- *
- * Change CPU model feature bits for compatibility.
- *
- * This function may be used by machine-type compatibility functions
- * to enable or disable feature bits on specific CPU models.
- */
-void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
- uint32_t feat_add, uint32_t feat_remove)
-{
-X86CPUDefinition *def;
-int i;
-for (i = 0; i ARRAY_SIZE(builtin_x86_defs); i++) {
-def = builtin_x86_defs[i];
-if (!cpu_model || !strcmp(cpu_model, def-name)) {
-def-features[w] |= feat_add;
-def-features[w] = ~feat_remove;
-}
-}
-}
-
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only);
--
MST
[Qemu-devel] [PULL 09/24] pc: Eliminate pc_common_machine_options()
From: Eduardo Habkost ehabk...@redhat.com
All TYPE_PC_MACHINE subclasses call pc_common_machine_options().
TYPE_PC_MACHINE can simply initialize the common options on class_init
directly.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 6 --
hw/i386/pc.c | 1 +
hw/i386/pc_piix.c| 2 --
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 6746097..1d21ab2 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -699,14 +699,8 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.value = off,\
},
-static inline void pc_common_machine_options(MachineClass *m)
-{
-m-default_boot_order = cad;
-}
-
static inline void pc_default_machine_options(MachineClass *m)
{
-pc_common_machine_options(m);
m-hot_add_cpu = pc_hot_add_cpu;
m-max_cpus = 255;
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ad1a861..583c47a 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1938,6 +1938,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
pcmc-get_hotplug_handler = mc-get_hotplug_handler;
mc-get_hotplug_handler = pc_get_hotpug_handler;
mc-cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
+mc-default_boot_order = cad;
hc-plug = pc_machine_device_plug_cb;
hc-unplug_request = pc_machine_device_unplug_request_cb;
hc-unplug = pc_machine_device_unplug_cb;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c88ed0d..d722518 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -887,7 +887,6 @@ DEFINE_I440FX_MACHINE(v0_10, pc-0.10, pc_compat_0_13,
static void isapc_machine_options(MachineClass *m)
{
-pc_common_machine_options(m);
m-desc = ISA-only PC;
m-max_cpus = 1;
}
@@ -899,7 +898,6 @@ DEFINE_PC_MACHINE(isapc, isapc, pc_init_isa,
#ifdef CONFIG_XEN
static void xenfv_machine_options(MachineClass *m)
{
-pc_common_machine_options(m);
m-desc = Xen Fully-virtualized PC;
m-max_cpus = HVM_MAX_VCPUS;
m-default_machine_opts = accel=xen;
--
MST
[Qemu-devel] [PULL 11/24] pc: Use PCMachineState for pc_cmos_init() argument
From: Eduardo Habkost ehabk...@redhat.com
pc_cmos_init() already expects a PCMachineState object, there's no point
in upcasting it to MachineState before calling the function.
While doing it, reorder the arguments so PCMachineState is the first
function argument.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 5 +++--
hw/i386/pc.c | 10 +-
hw/i386/pc_piix.c| 5 +++--
hw/i386/pc_q35.c | 5 +++--
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 0273bec..d8184cd 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -200,8 +200,9 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
bool no_vmport,
uint32 hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
-void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
- const char *boot_device, MachineState *machine,
+void pc_cmos_init(PCMachineState *pcms,
+ ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
+ const char *boot_device,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 29f2b90..255476b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -428,14 +428,14 @@ static void pc_cmos_init_late(void *opaque)
qemu_unregister_reset(pc_cmos_init_late, opaque);
}
-void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
- const char *boot_device, MachineState *machine,
+void pc_cmos_init(PCMachineState *pcms,
+ ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
+ const char *boot_device,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
{
int val;
static pc_cmos_init_late_arg arg;
-PCMachineState *pcms = PC_MACHINE(machine);
Error *local_err = NULL;
/* various important CMOS locations needed by PC/Bochs bios */
@@ -476,12 +476,12 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t
above_4g_mem_size,
/* set the number of CPU */
rtc_set_memory(s, 0x5f, smp_cpus - 1);
-object_property_add_link(OBJECT(machine), rtc_state,
+object_property_add_link(OBJECT(pcms), rtc_state,
TYPE_ISA_DEVICE,
(Object **)pcms-rtc,
object_property_allow_set_link,
OBJ_PROP_LINK_UNREF_ON_RELEASE, error_abort);
-object_property_set_link(OBJECT(machine), OBJECT(s),
+object_property_set_link(OBJECT(pcms), OBJECT(s),
rtc_state, error_abort);
set_boot_dev(s, boot_device, local_err);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 48d56c0..b975c21 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -271,8 +271,9 @@ static void pc_init1(MachineState *machine)
}
}
-pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine-boot_order,
- machine, idebus[0], idebus[1], rtc_state);
+pc_cmos_init(pcms,
+ below_4g_mem_size, above_4g_mem_size, machine-boot_order,
+ idebus[0], idebus[1], rtc_state);
if (pci_enabled usb_enabled()) {
pci_create_simple(pci_bus, piix3_devfn + 2, piix3-usb-uhci);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 0706934..441e9d9 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -276,8 +276,9 @@ static void pc_q35_init(MachineState *machine)
0xb100),
8, NULL, 0);
-pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine-boot_order,
- machine, idebus[0], idebus[1], rtc_state);
+pc_cmos_init(pcms,
+ below_4g_mem_size, above_4g_mem_size, machine-boot_order,
+ idebus[0], idebus[1], rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
pc_vga_init(isa_bus, host_bus);
--
MST
[Qemu-devel] [PULL 23/24] smbios: move smbios code into a common folder
From: Wei Huang w...@redhat.com
To share smbios among different architectures, this patch moves SMBIOS
code (smbios.c and smbios.h) from x86 specific folders into new
hw/smbios directories. As a result, CONFIG_SMBIOS=y is defined in
x86 default config files.
Acked-by: Gabriel Somlo so...@cmu.edu
Tested-by: Gabriel Somlo so...@cmu.edu
Reviewed-by: Laszlo Ersek ler...@redhat.com
Tested-by: Leif Lindholm leif.lindh...@linaro.org
Signed-off-by: Wei Huang w...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/{i386 = smbios}/smbios.h | 0
arch_init.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/pc_piix.c| 2 +-
hw/i386/pc_q35.c | 2 +-
hw/{i386 = smbios}/smbios.c | 5 ++---
tests/bios-tables-test.c | 2 +-
vl.c | 2 +-
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/Makefile.objs | 1 +
hw/i386/Makefile.objs| 2 +-
hw/smbios/Makefile.objs | 1 +
13 files changed, 13 insertions(+), 10 deletions(-)
rename include/hw/{i386 = smbios}/smbios.h (100%)
rename hw/{i386 = smbios}/smbios.c (99%)
create mode 100644 hw/smbios/Makefile.objs
diff --git a/include/hw/i386/smbios.h b/include/hw/smbios/smbios.h
similarity index 100%
rename from include/hw/i386/smbios.h
rename to include/hw/smbios/smbios.h
diff --git a/arch_init.c b/arch_init.c
index 725c638..38f5fb9 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -26,7 +26,7 @@
#include sysemu/arch_init.h
#include hw/pci/pci.h
#include hw/audio/audio.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include qemu/config-file.h
#include qemu/error-report.h
#include qmp-commands.h
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0973596..9f2924e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -33,7 +33,7 @@
#include hw/pci/pci_bus.h
#include hw/nvram/fw_cfg.h
#include hw/timer/hpet.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include hw/loader.h
#include elf.h
#include multiboot.h
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ce51cd1..9558467 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -28,7 +28,7 @@
#include hw/loader.h
#include hw/i386/pc.h
#include hw/i386/apic.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include hw/pci/pci.h
#include hw/pci/pci_ids.h
#include hw/usb.h
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index cd4ecc3..c07d65b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -39,7 +39,7 @@
#include hw/pci-host/q35.h
#include exec/address-spaces.h
#include hw/i386/ich9.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include hw/ide/pci.h
#include hw/ide/ahci.h
#include hw/usb.h
diff --git a/hw/i386/smbios.c b/hw/smbios/smbios.c
similarity index 99%
rename from hw/i386/smbios.c
rename to hw/smbios/smbios.c
index 6f715c6..efdbb5d 100644
--- a/hw/i386/smbios.c
+++ b/hw/smbios/smbios.c
@@ -19,10 +19,9 @@
#include qemu/error-report.h
#include sysemu/sysemu.h
#include sysemu/cpus.h
-#include hw/i386/pc.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include hw/loader.h
-
+#include exec/cpu-common.h
/* legacy structures and constants for = 2.0 machines */
struct smbios_header {
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 0de1742..613867a 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -18,7 +18,7 @@
#include libqtest.h
#include qemu/compiler.h
#include hw/acpi/acpi-defs.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include qemu/bitmap.h
#define MACHINE_PC pc
diff --git a/vl.c b/vl.c
index 0adbbd6..584ca88 100644
--- a/vl.c
+++ b/vl.c
@@ -68,7 +68,7 @@ int main(int argc, char **argv)
#include hw/isa/isa.h
#include hw/bt.h
#include sysemu/watchdog.h
-#include hw/i386/smbios.h
+#include hw/smbios/smbios.h
#include hw/xen/xen.h
#include hw/qdev.h
#include hw/loader.h
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 48b5762..5eaafa1 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -49,3 +49,4 @@ CONFIG_MEM_HOTPLUG=y
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
+CONFIG_SMBIOS=y
diff --git a/default-configs/x86_64-softmmu.mak
b/default-configs/x86_64-softmmu.mak
index 4962ed7..28e2099 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -50,3 +50,4 @@ CONFIG_MEM_HOTPLUG=y
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
+CONFIG_SMBIOS=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 73afa41..7e7c241 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -31,6 +31,7 @@ devices-dirs-$(CONFIG_VIRTIO) += virtio/
devices-dirs-$(CONFIG_SOFTMMU) += watchdog/
devices-dirs-$(CONFIG_SOFTMMU) += xen/
devices-dirs-$(CONFIG_MEM_HOTPLUG) += mem/
[Qemu-devel] [PULL 19/24] virtio-net: remove useless codes
From: Jason Wang jasow...@redhat.com
After commit 40bad8f3deba15e2074ff34cfe923c12916b1cc5(virtio-net: fix
used len for tx), async_tx.len was no longer used afterwards. So
remove useless codes with it.
Signed-off-by: Jason Wang jasow...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/virtio/virtio-net.h | 1 -
hw/net/virtio-net.c| 8 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/include/hw/virtio/virtio-net.h b/include/hw/virtio/virtio-net.h
index 60b11d5..f3cc25f 100644
--- a/include/hw/virtio/virtio-net.h
+++ b/include/hw/virtio/virtio-net.h
@@ -48,7 +48,6 @@ typedef struct VirtIONetQueue {
int tx_waiting;
struct {
VirtQueueElement elem;
-ssize_t len;
} async_tx;
struct VirtIONet *n;
} VirtIONetQueue;
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 1510839..8d28e45 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -1124,7 +1124,7 @@ static void virtio_net_tx_complete(NetClientState *nc,
ssize_t len)
virtqueue_push(q-tx_vq, q-async_tx.elem, 0);
virtio_notify(vdev, q-tx_vq);
-q-async_tx.elem.out_num = q-async_tx.len = 0;
+q-async_tx.elem.out_num = 0;
virtio_queue_set_notification(q-tx_vq, 1);
virtio_net_flush_tx(q);
@@ -1148,7 +1148,7 @@ static int32_t virtio_net_flush_tx(VirtIONetQueue *q)
}
while (virtqueue_pop(q-tx_vq, elem)) {
-ssize_t ret, len;
+ssize_t ret;
unsigned int out_num = elem.out_num;
struct iovec *out_sg = elem.out_sg[0];
struct iovec sg[VIRTQUEUE_MAX_SIZE], sg2[VIRTQUEUE_MAX_SIZE + 1];
@@ -1196,18 +1196,14 @@ static int32_t virtio_net_flush_tx(VirtIONetQueue *q)
out_sg = sg;
}
-len = n-guest_hdr_len;
-
ret = qemu_sendv_packet_async(qemu_get_subqueue(n-nic, queue_index),
out_sg, out_num, virtio_net_tx_complete);
if (ret == 0) {
virtio_queue_set_notification(q-tx_vq, 0);
q-async_tx.elem = elem;
-q-async_tx.len = len;
return -EBUSY;
}
-len += ret;
drop:
virtqueue_push(q-tx_vq, elem, 0);
virtio_notify(vdev, q-tx_vq);
--
MST
Re: [Qemu-devel] [PATCH 12/10] tcg: protect TBContext with tb_lock.
On 12/08/2015 18:41, Paolo Bonzini wrote:
From: KONRAD Frederic fred.kon...@greensocs.com
This protects TBContext with tb_lock to make tb_* thread safe.
We can still have issue with tb_flush in case of multithread TCG:
another CPU can be executing code during a flush.
This can be fixed later by making all other TCG thread exiting before calling
tb_flush().
Signed-off-by: KONRAD Frederic fred.kon...@greensocs.com
Changes:
V6 - V7:
* Drop a tb_lock in already locked restore_state_to_opc.
V5 - V6:
* Drop a tb_lock arround tb_find_fast in cpu-exec.c.
Message-Id: 1439220437-23957-8-git-send-email-fred.kon...@greensocs.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
cpu-exec.c | 6 ++
exec.c | 3 +++
hw/i386/kvmvapic.c | 2 ++
translate-all.c| 38 --
4 files changed, 43 insertions(+), 6 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index e712c6a..89b66f5 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -241,16 +241,22 @@ static void cpu_exec_nocache(CPUState *cpu, int
max_cycles,
if (max_cycles CF_COUNT_MASK)
max_cycles = CF_COUNT_MASK;
+tb_lock();
tb = tb_gen_code(cpu, orig_tb-pc, orig_tb-cs_base, orig_tb-flags,
max_cycles | CF_NOCACHE);
tb_gen_code() calls tb_alloc() which calls tb_flush() we end in a double
tb_lock here.
But that's probably not really important here as we want to either do a
tb_flush
outside cpu_exec or realloc an other code buffer.
Fred
tb-orig_tb = tcg_ctx.tb_ctx.tb_invalidated_flag ? NULL : orig_tb;
cpu-current_tb = tb;
+tb_unlock();
+
/* execute the generated code */
trace_exec_tb_nocache(tb, tb-pc);
cpu_tb_exec(cpu, tb-tc_ptr);
+
+tb_lock();
cpu-current_tb = NULL;
tb_phys_invalidate(tb, -1);
tb_free(tb);
+tb_unlock();
}
#endif
diff --git a/exec.c b/exec.c
index 856a859..9083307 100644
--- a/exec.c
+++ b/exec.c
@@ -1948,6 +1948,9 @@ static void check_watchpoint(int offset, int len,
MemTxAttrs attrs, int flags)
wp-hitattrs = attrs;
if (!cpu-watchpoint_hit) {
cpu-watchpoint_hit = wp;
+
+/* Unlocked by cpu_loop_exit or cpu_resume_from_signal. */
+tb_lock();
tb_check_watchpoint(cpu);
if (wp-flags BP_STOP_BEFORE_ACCESS) {
cpu-exception_index = EXCP_DEBUG;
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index c6d34b2..d823e15 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -445,6 +445,8 @@ static void patch_instruction(VAPICROMState *s, X86CPU
*cpu, target_ulong ip)
resume_all_vcpus();
if (!kvm_enabled()) {
+/* Unlocked by cpu_resume_from_signal. */
+tb_lock();
cs-current_tb = NULL;
tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(cs, NULL);
diff --git a/translate-all.c b/translate-all.c
index 17d3cd1..7a4f8f1 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -301,6 +301,8 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
{
TranslationBlock *tb;
+tb_lock();
+
tb = tb_find_pc(retaddr);
if (tb) {
cpu_restore_state_from_tb(cpu, tb, retaddr);
@@ -310,8 +312,12 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
tb_phys_invalidate(tb, -1);
tb_free(tb);
}
+
+tb_unlock();
return true;
}
+
+tb_unlock();
return false;
}
@@ -820,6 +826,8 @@ static void page_flush_tb(void)
/* XXX: tb_flush is currently not thread safe */
void tb_flush(CPUState *cpu)
{
+tb_lock();
+
#if defined(DEBUG_FLUSH)
printf(qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n,
(unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer),
@@ -844,6 +852,8 @@ void tb_flush(CPUState *cpu)
/* XXX: flush processor icache at this point if cache flush is
expensive */
tcg_ctx.tb_ctx.tb_flush_count++;
+
+tb_unlock();
}
#ifdef DEBUG_TB_CHECK
@@ -1151,6 +1161,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start,
tb_page_addr_t end,
/* we remove all the TBs in the range [start, end[ */
/* XXX: see if in some cases it could be faster to invalidate all
the code */
+tb_lock();
tb = p-first_tb;
while (tb != NULL) {
n = (uintptr_t)tb 3;
@@ -1218,12 +1229,13 @@ void tb_invalidate_phys_page_range(tb_page_addr_t
start, tb_page_addr_t end,
if (current_tb_modified) {
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
- itself */
+ itself. cpu_resume_from_signal unlocks tb_lock. */
cpu-current_tb = NULL;
tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
Re: [Qemu-devel] [PATCH 12/10] tcg: protect TBContext with tb_lock.
+tb_lock(); tb = tb_gen_code(cpu, orig_tb-pc, orig_tb-cs_base, orig_tb-flags, max_cycles | CF_NOCACHE); tb_gen_code() calls tb_alloc() which calls tb_flush() we end in a double tb_lock here. But that's probably not really important here as we want to either do a tb_flush outside cpu_exec or realloc an other code buffer. You're right! Honestly I haven't tested tb_flush() at all with these patches since it's documented as broken with multiple threads. Luckily the bug is not in the first 10 patches. :) Paolo
Re: [Qemu-devel] [PATCH 12/10] tcg: protect TBContext with tb_lock.
On 13/08/2015 15:01, Paolo Bonzini wrote: +tb_lock(); tb = tb_gen_code(cpu, orig_tb-pc, orig_tb-cs_base, orig_tb-flags, max_cycles | CF_NOCACHE); tb_gen_code() calls tb_alloc() which calls tb_flush() we end in a double tb_lock here. But that's probably not really important here as we want to either do a tb_flush outside cpu_exec or realloc an other code buffer. You're right! Honestly I haven't tested tb_flush() at all with these patches since it's documented as broken with multiple threads. Luckily the bug is not in the first 10 patches. :) Fortunately this revealed my yesterday bug with tb_alloc :). Fred Paolo
Re: [Qemu-devel] [PATCH 02/10] cpus: remove tcg_halt_cond global variable.
On 13/08/2015 15:05, Frederic Konrad wrote: This removes tcg_halt_cond global variable. We need one QemuCond per virtual cpu for multithread TCG. Signed-off-by: KONRAD Frederic fred.kon...@greensocs.com Message-Id: 1439220437-23957-9-git-send-email-fred.kon...@greensocs.com [Keep tcg_halt_cond for bisectability, while making it static. - Paolo] How does that help bisectability? With your patch (08/19), QEMU will only wait on first_cpu-halt_cond but will call broadcast on cpu-halt_cond. Here I do the opposite: I wait on cpu-halt_cond from some random CPU, but all of them point to the same condvar tcg_halt_cond. Paolo
Re: [Qemu-devel] [PATCH 5/5] migration: qemu-file more size_t'ifying
On 2015/8/13 18:51, Dr. David Alan Gilbert (git) wrote:
From: Dr. David Alan Gilbert dgilb...@redhat.com
This time convert the external functions:
qemu_get_buffer, qemu_peek_buffer
qemu_put_buffer and qemu_put_buffer_async
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
Reviewed-by: zhanghailiang zhang.zhanghaili...@huawei.com
include/migration/qemu-file.h | 10 +-
migration/qemu-file.c | 22 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index e1e2bab..29a338d 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -126,13 +126,13 @@ int qemu_get_fd(QEMUFile *f);
int qemu_fclose(QEMUFile *f);
int64_t qemu_ftell(QEMUFile *f);
int64_t qemu_ftell_fast(QEMUFile *f);
-void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
+void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, size_t size);
void qemu_put_byte(QEMUFile *f, int v);
/*
* put_buffer without copying the buffer.
* The buffer should be available till it is sent asynchronously.
*/
-void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size);
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, size_t size);
bool qemu_file_mode_is_not_valid(const char *mode);
bool qemu_file_is_writable(QEMUFile *f);
@@ -161,8 +161,8 @@ static inline void qemu_put_ubyte(QEMUFile *f, unsigned int
v)
void qemu_put_be16(QEMUFile *f, unsigned int v);
void qemu_put_be32(QEMUFile *f, unsigned int v);
void qemu_put_be64(QEMUFile *f, uint64_t v);
-int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int size, size_t offset);
-int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
+size_t qemu_peek_buffer(QEMUFile *f, uint8_t **buf, size_t size, size_t
offset);
+size_t qemu_get_buffer(QEMUFile *f, uint8_t *buf, size_t size);
ssize_t qemu_put_compression_data(QEMUFile *f, const uint8_t *p, size_t size,
int level);
int qemu_put_qemu_file(QEMUFile *f_des, QEMUFile *f_src);
@@ -237,7 +237,7 @@ static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
}
// Signed versions for type safety
-static inline void qemu_put_sbuffer(QEMUFile *f, const int8_t *buf, int size)
+static inline void qemu_put_sbuffer(QEMUFile *f, const int8_t *buf, size_t
size)
{
qemu_put_buffer(f, (const uint8_t *)buf, size);
}
diff --git a/migration/qemu-file.c b/migration/qemu-file.c
index 6bb3dc1..b273b1a 100644
--- a/migration/qemu-file.c
+++ b/migration/qemu-file.c
@@ -270,7 +270,7 @@ int qemu_fclose(QEMUFile *f)
return ret;
}
-static void add_to_iovec(QEMUFile *f, const uint8_t *buf, int size)
+static void add_to_iovec(QEMUFile *f, const uint8_t *buf, size_t size)
{
/* check for adjacent buffer and coalesce them */
if (f-iovcnt 0 buf == f-iov[f-iovcnt - 1].iov_base +
@@ -286,7 +286,7 @@ static void add_to_iovec(QEMUFile *f, const uint8_t *buf,
int size)
}
}
-void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, int size)
+void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf, size_t size)
{
if (!f-ops-writev_buffer) {
qemu_put_buffer(f, buf, size);
@@ -301,9 +301,9 @@ void qemu_put_buffer_async(QEMUFile *f, const uint8_t *buf,
int size)
add_to_iovec(f, buf, size);
}
-void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size)
+void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, size_t size)
{
-int l;
+size_t l;
if (f-last_error) {
return;
@@ -363,10 +363,10 @@ void qemu_file_skip(QEMUFile *f, int size)
* return as many as it managed to read (assuming blocking fd's which
* all current QEMUFile are)
*/
-int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int size, size_t offset)
+size_t qemu_peek_buffer(QEMUFile *f, uint8_t **buf, size_t size, size_t offset)
{
-int pending;
-int index;
+ssize_t pending;
+size_t index;
assert(!qemu_file_is_writable(f));
assert(offset IO_BUF_SIZE);
@@ -411,13 +411,13 @@ int qemu_peek_buffer(QEMUFile *f, uint8_t **buf, int
size, size_t offset)
* return as many as it managed to read (assuming blocking fd's which
* all current QEMUFile are)
*/
-int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size)
+size_t qemu_get_buffer(QEMUFile *f, uint8_t *buf, size_t size)
{
-int pending = size;
-int done = 0;
+size_t pending = size;
+size_t done = 0;
while (pending 0) {
-int res;
+size_t res;
uint8_t *src;
res = qemu_peek_buffer(f, src, MIN(pending, IO_BUF_SIZE), 0);
[Qemu-devel] [PULL 13/24] pc: Move {above, below}_4g_mem_size variables to PCMachineState
From: Eduardo Habkost ehabk...@redhat.com
This will make the info readily available for the other initialization
functions, and will allow us to simplify their argument list.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 1 +
hw/i386/pc_piix.c| 26 ++
hw/i386/pc_q35.c | 24 +---
3 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 4fa2b3f..e1d20ad 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -40,6 +40,7 @@ struct PCMachineState {
OnOffAuto vmport;
OnOffAuto smm;
bool enforce_aligned_dimm;
+ram_addr_t below_4g_mem_size, above_4g_mem_size;
};
#define PC_MACHINE_ACPI_DEVICE_PROP acpi-device
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 18e9aa5..559f4e5 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -82,7 +82,6 @@ static void pc_init1(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
int i;
-ram_addr_t below_4g_mem_size, above_4g_mem_size;
PCIBus *pci_bus;
ISABus *isa_bus;
PCII440FXState *i440fx_state;
@@ -128,14 +127,15 @@ static void pc_init1(MachineState *machine)
}
if (machine-ram_size = lowmem) {
-above_4g_mem_size = machine-ram_size - lowmem;
-below_4g_mem_size = lowmem;
+pcms-above_4g_mem_size = machine-ram_size - lowmem;
+pcms-below_4g_mem_size = lowmem;
} else {
-above_4g_mem_size = 0;
-below_4g_mem_size = machine-ram_size;
+pcms-above_4g_mem_size = 0;
+pcms-below_4g_mem_size = machine-ram_size;
}
-if (xen_enabled() xen_hvm_init(below_4g_mem_size, above_4g_mem_size,
+if (xen_enabled() xen_hvm_init(pcms-below_4g_mem_size,
+ pcms-above_4g_mem_size,
ram_memory) != 0) {
fprintf(stderr, xen hardware virtual machine initialisation
failed\n);
exit(1);
@@ -160,7 +160,8 @@ static void pc_init1(MachineState *machine)
rom_memory = system_memory;
}
-guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
+guest_info = pc_guest_info_init(pcms-below_4g_mem_size,
+pcms-above_4g_mem_size);
guest_info-has_acpi_build = has_acpi_build;
guest_info-legacy_acpi_table_size = legacy_acpi_table_size;
@@ -179,14 +180,14 @@ static void pc_init1(MachineState *machine)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(pcms, system_memory,
- below_4g_mem_size, above_4g_mem_size,
+ pcms-below_4g_mem_size, pcms-above_4g_mem_size,
rom_memory, ram_memory, guest_info);
} else if (machine-kernel_filename != NULL) {
/* For xen HVM direct kernel boot, load linux here */
xen_load_linux(machine-kernel_filename,
machine-kernel_cmdline,
machine-initrd_filename,
- below_4g_mem_size,
+ pcms-below_4g_mem_size,
guest_info);
}
@@ -202,8 +203,8 @@ static void pc_init1(MachineState *machine)
if (pci_enabled) {
pci_bus = i440fx_init(i440fx_state, piix3_devfn, isa_bus, gsi,
system_memory, system_io, machine-ram_size,
- below_4g_mem_size,
- above_4g_mem_size,
+ pcms-below_4g_mem_size,
+ pcms-above_4g_mem_size,
pci_memory, ram_memory);
} else {
pci_bus = NULL;
@@ -272,7 +273,8 @@ static void pc_init1(MachineState *machine)
}
pc_cmos_init(pcms,
- below_4g_mem_size, above_4g_mem_size, machine-boot_order,
+ pcms-below_4g_mem_size, pcms-above_4g_mem_size,
+ machine-boot_order,
idebus[0], idebus[1], rtc_state);
if (pci_enabled usb_enabled()) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6763f0d..489dfcb 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -66,7 +66,6 @@ static bool has_reserved_memory = true;
static void pc_q35_init(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
-ram_addr_t below_4g_mem_size, above_4g_mem_size;
Q35PCIHost *q35_host;
PCIHostState *phb;
PCIBus *host_bus;
@@ -119,14 +118,15 @@ static void pc_q35_init(MachineState *machine)
}
if (machine-ram_size = lowmem) {
-above_4g_mem_size = machine-ram_size - lowmem;
-below_4g_mem_size = lowmem;
+pcms-above_4g_mem_size = machine-ram_size - lowmem;
+
Re: [Qemu-devel] [PATCH 11/10] tcg: comment on which functions have to be called with tb_lock held
On 12/08/2015 18:41, Paolo Bonzini wrote:
softmmu requires more functions to be thread-safe, because translation
blocks can be invalidated from e.g. notdirty callbacks. Probably the
same holds for user-mode emulation, it's just that no one has ever
tried to produce a coherent locking there.
This patch will guide the introduction of more tb_lock and tb_unlock
calls for system emulation.
Note that after this patch some (most) of the mentioned functions are
still called outside tb_lock/tb_unlock. The next one will rectify this.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
exec.c | 1 +
include/exec/exec-all.h | 2 ++
include/qom/cpu.h | 3 +++
tcg/tcg.h | 2 ++
translate-all.c | 35 ---
5 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/exec.c b/exec.c
index 54cd70a..856a859 100644
--- a/exec.c
+++ b/exec.c
@@ -748,6 +748,7 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int
flags,
{
CPUBreakpoint *bp;
+/* TODO: locking (RCU?) */
bp = g_malloc(sizeof(*bp));
bp-pc = pc;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b3f900a..943d97a 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -74,6 +74,7 @@ typedef struct TranslationBlock TranslationBlock;
void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
+/* Called with tb_lock held. */
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
int pc_pos);
@@ -278,6 +279,7 @@ static inline void tb_set_jmp_target(TranslationBlock *tb,
#endif
+/* Called with tb_lock held. */
static inline void tb_add_jump(TranslationBlock *tb, int n,
TranslationBlock *tb_next)
{
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 77bbff2..56b1f4d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -285,7 +285,10 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
+
+/* Protected by tb_lock. */
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
This is temporary as a first step?
+
struct GDBRegisterState *gdb_regs;
int gdb_num_regs;
int gdb_num_g_regs;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 0ae648f..a2cad31 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -590,6 +590,7 @@ static inline bool tcg_op_buf_full(void)
/* pool based memory allocation */
+/* tb_lock must be held for tcg_malloc_internal. */
void *tcg_malloc_internal(TCGContext *s, int size);
void tcg_pool_reset(TCGContext *s);
void tcg_pool_delete(TCGContext *s);
@@ -598,6 +599,7 @@ void tb_lock(void);
void tb_unlock(void);
void tb_lock_reset(void);
+/* Called with tb_lock held. */
static inline void *tcg_malloc(int size)
{
TCGContext *s = tcg_ctx;
diff --git a/translate-all.c b/translate-all.c
index edb9cb1..17d3cd1 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -237,6 +237,7 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb,
int *gen_code_size_ptr
}
/* The cpu state corresponding to 'searched_pc' is restored.
+ * Called with tb_lock held.
*/
static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t searched_pc)
@@ -424,6 +425,7 @@ static void page_init(void)
}
/* If alloc=1:
+ * Called with tb_lock held for system emulation.
* Called with mmap_lock held for user-mode emulation.
*/
static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
@@ -734,8 +736,12 @@ bool tcg_enabled(void)
return tcg_ctx.code_gen_buffer != NULL;
}
-/* Allocate a new translation block. Flush the translation buffer if
- too many translation blocks or too much generated code. */
+/*
+ * Allocate a new translation block. Flush the translation buffer if
+ * too many translation blocks or too much generated code.
+ *
+ * Called with tb_lock held.
+ */
static TranslationBlock *tb_alloc(target_ulong pc)
{
There is the famous tb_flush which needs to be called with tb_lock held
as well.
There are several place where it's called.
TranslationBlock *tb;
@@ -751,6 +757,7 @@ static TranslationBlock *tb_alloc(target_ulong pc)
return tb;
}
+/* Called with tb_lock held. */
void tb_free(TranslationBlock *tb)
{
/* In practice this is mostly used for single use temporary TB
@@ -859,7 +866,10 @@ static void tb_invalidate_check(target_ulong address)
}
}
-/* verify that all the pages have correct rights for code */
+/* verify that all the pages have correct rights for code
+ *
+ * Called with tb_lock held.
+ */
static void tb_page_check(void)
{
TranslationBlock *tb;
@@ -947,7 +957,10 @@ static inline void tb_reset_jump(TranslationBlock *tb, int
n)
[Qemu-devel] [PATCH RFC] pseries: define coldplugged devices as configured
When a device is hotplugged, attach() sets configured to false, waiting an action from the OS to configure it and then to call ibm,configure-connector. On ibm,configure-connector, the hypervisor sets configured to true. In case of coldplugged device, attach() sets configured to false, but firmware and OS never call the ibm,configure-connector in this case, so it remains set to false. It could be harmless, but when we unplug a device, hypervisor waits the device becomes configured because for it, a not configured device is a device being configured, so it waits the end of configuration to unplug it... and it never happens, so it is never unplugged. This patch set by default coldplugged device to configured=true, hotplugged device to configured=false. Signed-off-by: Laurent Vivier lviv...@redhat.com --- hw/ppc/spapr_drc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index ee87432..e86babf 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -310,7 +310,7 @@ static void attach(sPAPRDRConnector *drc, DeviceState *d, void *fdt, drc-dev = d; drc-fdt = fdt; drc-fdt_start_offset = fdt_start_offset; -drc-configured = false; +drc-configured = coldplug; object_property_add_link(OBJECT(drc), device, object_get_typename(OBJECT(drc-dev)), -- 2.1.0
Re: [Qemu-devel] [PATCH v7 04/11] target-mips: improve exception handling
On 10/07/2015 10:57, Pavel Dovgalyuk wrote: @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, #if defined(TARGET_MIPS64) case OPC_SCD: case R6_OPC_SCD: -save_cpu_state(ctx, 1); op_st_scd(t1, t0, rt, ctx); opn = scd; break; #endif case OPC_SC: case R6_OPC_SC: -save_cpu_state(ctx, 1); op_st_sc(t1, t0, rt, ctx); opn = sc; break; Wouldn't we be better off assuming that conditional stores in linux-user always take an exception (we generate fake EXCP_SC exception) and avoid retranslation? After applying these changes I observed significant impact on performance in linux-user multithreaded apps, for instance c11-atomic-exec test before the change took just 2 seconds to finish, whereas now more than 30... Thanks, Leon PS: multithreaded MIPS apps fail horribly in linux-user with this patch as it's much more likely to get bitten by race conditions in translate-all.c. But translate-all.c thread-safety patch series seem to fix it.
Re: [Qemu-devel] [PATCH 03/10] replace spinlock by QemuMutex.
On 13/08/2015 14:17, Frederic Konrad wrote:
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..fd06ce9 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -107,7 +107,7 @@ static int pending_cpus;
/* Make sure everything is in a consistent state for calling
fork(). */
void fork_start(void)
{
-pthread_mutex_lock(tcg_ctx.tb_ctx.tb_lock);
+qemu_mutex_lock(tcg_ctx.tb_ctx.tb_lock);
pthread_mutex_lock(exclusive_lock);
mmap_fork_start();
}
@@ -129,11 +129,11 @@ void fork_end(int child)
pthread_mutex_init(cpu_list_mutex, NULL);
pthread_cond_init(exclusive_cond, NULL);
pthread_cond_init(exclusive_resume, NULL);
-pthread_mutex_init(tcg_ctx.tb_ctx.tb_lock, NULL);
+qemu_mutex_init(tcg_ctx.tb_ctx.tb_lock);
gdbserver_fork(thread_cpu);
} else {
pthread_mutex_unlock(exclusive_lock);
-pthread_mutex_unlock(tcg_ctx.tb_ctx.tb_lock);
+qemu_mutex_unlock(tcg_ctx.tb_ctx.tb_lock);
We might want to use tb_lock/unlock in user code as well instead of
calling directly qemu_mutex_* ?
You cannot do that because of the recursive locking assertions; the
child is not using qemu_mutex_unlock, it's using qemu_mutex_init. So I
would have to add some kind of tb_lock_reset_after_fork() function which
is a bit ugly.
@@ -676,6 +709,7 @@ static inline void code_gen_alloc(size_t tb_size)
CODE_GEN_AVG_BLOCK_SIZE;
tcg_ctx.tb_ctx.tbs =
g_malloc(tcg_ctx.code_gen_max_blocks *
sizeof(TranslationBlock));
+qemu_mutex_init(tcg_ctx.tb_ctx.tb_lock);
Maybe we can initialize the mutex only for CONFIG_USER_ONLY?
It's okay, it doesn't consume system resources.
Paolo
Re: [Qemu-devel] [PATCH 03/10] replace spinlock by QemuMutex.
On 13/08/2015 15:12, Paolo Bonzini wrote:
On 13/08/2015 14:17, Frederic Konrad wrote:
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..fd06ce9 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -107,7 +107,7 @@ static int pending_cpus;
/* Make sure everything is in a consistent state for calling
fork(). */
void fork_start(void)
{
-pthread_mutex_lock(tcg_ctx.tb_ctx.tb_lock);
+qemu_mutex_lock(tcg_ctx.tb_ctx.tb_lock);
pthread_mutex_lock(exclusive_lock);
mmap_fork_start();
}
@@ -129,11 +129,11 @@ void fork_end(int child)
pthread_mutex_init(cpu_list_mutex, NULL);
pthread_cond_init(exclusive_cond, NULL);
pthread_cond_init(exclusive_resume, NULL);
-pthread_mutex_init(tcg_ctx.tb_ctx.tb_lock, NULL);
+qemu_mutex_init(tcg_ctx.tb_ctx.tb_lock);
gdbserver_fork(thread_cpu);
} else {
pthread_mutex_unlock(exclusive_lock);
-pthread_mutex_unlock(tcg_ctx.tb_ctx.tb_lock);
+qemu_mutex_unlock(tcg_ctx.tb_ctx.tb_lock);
We might want to use tb_lock/unlock in user code as well instead of
calling directly qemu_mutex_* ?
You cannot do that because of the recursive locking assertions; the
child is not using qemu_mutex_unlock, it's using qemu_mutex_init. So I
would have to add some kind of tb_lock_reset_after_fork() function which
is a bit ugly.
True.
Fred
@@ -676,6 +709,7 @@ static inline void code_gen_alloc(size_t tb_size)
CODE_GEN_AVG_BLOCK_SIZE;
tcg_ctx.tb_ctx.tbs =
g_malloc(tcg_ctx.code_gen_max_blocks *
sizeof(TranslationBlock));
+qemu_mutex_init(tcg_ctx.tb_ctx.tb_lock);
Maybe we can initialize the mutex only for CONFIG_USER_ONLY?
It's okay, it doesn't consume system resources.
Paolo
Re: [Qemu-devel] [PATCH v11 0/5] Update tests/qemu-iotests failing cases for the s390 platform
Am 03.07.2015 um 09:28 hat Bo Tu geschrieben: Bo Tu (5): qemu-iotests: qemu machine type support qemu-iotests: disable default qemu devices for cross-platform compatibility qemu-iotests: s390x: fix test 041 and 055 qemu-iotests: s390x: fix test 049, reject negative sizes in QemuOpts qemu-iotests: s390x: fix test 130 Thanks, applied to the block branch. Kevin
[Qemu-devel] [PULL 20/24] acpi: avoid potential uninitialized access to cpu_hp_io_base
From: Daniel P. Berrange berra...@redhat.com
When building QEMU with Mingw64 toolchain I see a warning
CCx86_64-softmmu/hw/i386/acpi-build.o
hw/i386/acpi-build.c: In function 'acpi_build':
hw/i386/acpi-build.c:1138:9: warning: 'pm.cpu_hp_io_base' may be used
uninitialized in this function [-Wmaybe-uninitialized]
aml_append(crs,
^
hw/i386/acpi-build.c:1666:16: note: 'pm.cpu_hp_io_base' was declared here
AcpiPmInfo pm;
^
In acpi_get_pm_info() some of the fields are pre-initialized
to 0, but this one was missed.
Signed-off-by: Daniel P. Berrange berra...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
Reviewed-by: Igor Mammedov imamm...@redhat.com
---
hw/i386/acpi-build.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 46eddb8..95e0c65 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -169,6 +169,7 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
Object *obj = NULL;
QObject *o;
+pm-cpu_hp_io_base = 0;
pm-pcihp_io_base = 0;
pm-pcihp_io_len = 0;
if (piix) {
--
MST
Re: [Qemu-devel] [PATCH 2/5] Split out end of migration code from migration_thread
On 2015/8/13 18:51, Dr. David Alan Gilbert (git) wrote:
From: Dr. David Alan Gilbert dgilb...@redhat.com
The code that gets run at the end of the migration process
is getting large, and I'm about to add more for postcopy.
Split it into a separate function.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
Reviewed-by: zhanghailiang zhang.zhanghaili...@huawei.com
migration/migration.c | 75 ---
trace-events | 2 ++
2 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 662e77e..46bb410 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -913,6 +913,50 @@ int64_t migrate_xbzrle_cache_size(void)
return s-xbzrle_cache_size;
}
+/**
+ * migration_completion: Used by migration_thread when there's not much left.
+ * The caller 'breaks' the loop when this returns.
+ *
+ * @s: Current migration state
+ * @*old_vm_running: Pointer to old_vm_running flag
+ * @*start_time: Pointer to time to update
+ */
+static void migration_completion(MigrationState *s, bool *old_vm_running,
+ int64_t *start_time)
+{
+int ret;
+
+qemu_mutex_lock_iothread();
+*start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
+*old_vm_running = runstate_is_running();
+
+ret = global_state_store();
+if (!ret) {
+ret = vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
+if (ret = 0) {
+qemu_file_set_rate_limit(s-file, INT64_MAX);
+qemu_savevm_state_complete(s-file);
+}
+}
+qemu_mutex_unlock_iothread();
+
+if (ret 0) {
+goto fail;
+}
+
+if (qemu_file_get_error(s-file)) {
+trace_migration_completion_file_err();
+goto fail;
+}
+
+migrate_set_state(s, MIGRATION_STATUS_ACTIVE, MIGRATION_STATUS_COMPLETED);
+return;
+
+fail:
+migrate_set_state(s, MIGRATION_STATUS_ACTIVE, MIGRATION_STATUS_FAILED);
+}
+
/* migration thread support */
static void *migration_thread(void *opaque)
@@ -943,34 +987,9 @@ static void *migration_thread(void *opaque)
if (pending_size pending_size = max_size) {
qemu_savevm_state_iterate(s-file);
} else {
-int ret;
-
-qemu_mutex_lock_iothread();
-start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
-qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
-old_vm_running = runstate_is_running();
-
-ret = global_state_store();
-if (!ret) {
-ret = vm_stop_force_state(RUN_STATE_FINISH_MIGRATE);
-if (ret = 0) {
-qemu_file_set_rate_limit(s-file, INT64_MAX);
-qemu_savevm_state_complete(s-file);
-}
-}
-qemu_mutex_unlock_iothread();
-
-if (ret 0) {
-migrate_set_state(s, MIGRATION_STATUS_ACTIVE,
- MIGRATION_STATUS_FAILED);
-break;
-}
-
-if (!qemu_file_get_error(s-file)) {
-migrate_set_state(s, MIGRATION_STATUS_ACTIVE,
- MIGRATION_STATUS_COMPLETED);
-break;
-}
+trace_migration_thread_low_pending(pending_size);
+migration_completion(s, old_vm_running, start_time);
+break;
}
}
diff --git a/trace-events b/trace-events
index 94bf3bb..1509e5b 100644
--- a/trace-events
+++ b/trace-events
@@ -1406,6 +1406,8 @@ migrate_transferred(uint64_t tranferred, uint64_t
time_spent, double bandwidth,
migrate_state_too_big(void)
migrate_global_state_post_load(const char *state) loaded state: %s
migrate_global_state_pre_save(const char *state) saved state: %s
+migration_completion_file_err(void)
+migration_thread_low_pending(uint64_t pending) % PRIu64
# migration/rdma.c
qemu_rdma_accept_incoming_migration(void)
[Qemu-devel] [PULL 15/24] pc: Remove redundant arguments from *load_linux()
From: Eduardo Habkost ehabk...@redhat.com
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 5 +
hw/i386/pc.c | 28
hw/i386/pc_piix.c| 6 +-
3 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 94d7afb..c433602 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -180,10 +180,7 @@ void pc_set_legacy_acpi_data_size(void);
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
MemoryRegion *pci_address_space);
-FWCfgState *xen_load_linux(const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- ram_addr_t below_4g_mem_size,
+FWCfgState *xen_load_linux(PCMachineState *pcms,
PcGuestInfo *guest_info);
FWCfgState *pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 081ef83..54b28a3 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -809,11 +809,8 @@ static long get_file_size(FILE *f)
return size;
}
-static void load_linux(FWCfgState *fw_cfg,
- const char *kernel_filename,
- const char *initrd_filename,
- const char *kernel_cmdline,
- hwaddr max_ram_size)
+static void load_linux(PCMachineState *pcms,
+ FWCfgState *fw_cfg)
{
uint16_t protocol;
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
@@ -822,6 +819,10 @@ static void load_linux(FWCfgState *fw_cfg,
hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f;
char *vmode;
+MachineState *machine = MACHINE(pcms);
+const char *kernel_filename = machine-kernel_filename;
+const char *initrd_filename = machine-initrd_filename;
+const char *kernel_cmdline = machine-kernel_cmdline;
/* Align to 16 bytes as a paranoia measure */
cmdline_size = (strlen(kernel_cmdline)+16) ~15;
@@ -886,8 +887,8 @@ static void load_linux(FWCfgState *fw_cfg,
initrd_max = 0x37ff;
}
-if (initrd_max = max_ram_size - acpi_data_size) {
-initrd_max = max_ram_size - acpi_data_size - 1;
+if (initrd_max = pcms-below_4g_mem_size - acpi_data_size) {
+initrd_max = pcms-below_4g_mem_size - acpi_data_size - 1;
}
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
@@ -1263,22 +1264,18 @@ void pc_acpi_init(const char *default_dsdt)
}
}
-FWCfgState *xen_load_linux(const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- ram_addr_t below_4g_mem_size,
+FWCfgState *xen_load_linux(PCMachineState *pcms,
PcGuestInfo *guest_info)
{
int i;
FWCfgState *fw_cfg;
-assert(kernel_filename != NULL);
+assert(MACHINE(pcms)-kernel_filename != NULL);
fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
rom_set_fw(fw_cfg);
-load_linux(fw_cfg, kernel_filename, initrd_filename,
- kernel_cmdline, below_4g_mem_size);
+load_linux(pcms, fw_cfg);
for (i = 0; i nb_option_roms; i++) {
assert(!strcmp(option_rom[i].name, linuxboot.bin) ||
!strcmp(option_rom[i].name, multiboot.bin));
@@ -1400,8 +1397,7 @@ FWCfgState *pc_memory_init(PCMachineState *pcms,
}
if (linux_boot) {
-load_linux(fw_cfg, machine-kernel_filename, machine-initrd_filename,
- machine-kernel_cmdline, below_4g_mem_size);
+load_linux(pcms, fw_cfg);
}
for (i = 0; i nb_option_roms; i++) {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 9364c47..f64f029 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -183,11 +183,7 @@ static void pc_init1(MachineState *machine)
rom_memory, ram_memory, guest_info);
} else if (machine-kernel_filename != NULL) {
/* For xen HVM direct kernel boot, load linux here */
-xen_load_linux(machine-kernel_filename,
- machine-kernel_cmdline,
- machine-initrd_filename,
- pcms-below_4g_mem_size,
- guest_info);
+xen_load_linux(pcms, guest_info);
}
gsi_state = g_malloc0(sizeof(*gsi_state));
--
MST
[Qemu-devel] [PULL 21/24] smbios: extract x86 smbios building code into a function
From: Wei Huang w...@redhat.com
This patch extracts out the procedure of buidling x86 SMBIOS tables
into a dedicated function.
Acked-by: Gabriel Somlo so...@cmu.edu
Tested-by: Gabriel Somlo so...@cmu.edu
Reviewed-by: Laszlo Ersek ler...@redhat.com
Tested-by: Leif Lindholm leif.lindh...@linaro.org
Signed-off-by: Wei Huang w...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/pc.c | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0c828e4..d75a8b4 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -716,11 +716,30 @@ static unsigned int pc_apic_id_limit(unsigned int
max_cpus)
return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
}
-static FWCfgState *bochs_bios_init(void)
+static void pc_build_smbios(FWCfgState *fw_cfg)
{
-FWCfgState *fw_cfg;
uint8_t *smbios_tables, *smbios_anchor;
size_t smbios_tables_len, smbios_anchor_len;
+
+smbios_tables = smbios_get_table_legacy(smbios_tables_len);
+if (smbios_tables) {
+fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_tables, smbios_tables_len);
+}
+
+smbios_get_tables(smbios_tables, smbios_tables_len,
+ smbios_anchor, smbios_anchor_len);
+if (smbios_anchor) {
+fw_cfg_add_file(fw_cfg, etc/smbios/smbios-tables,
+smbios_tables, smbios_tables_len);
+fw_cfg_add_file(fw_cfg, etc/smbios/smbios-anchor,
+smbios_anchor, smbios_anchor_len);
+}
+}
+
+static FWCfgState *bochs_bios_init(void)
+{
+FWCfgState *fw_cfg;
uint64_t *numa_fw_cfg;
int i, j;
unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
@@ -746,20 +765,7 @@ static FWCfgState *bochs_bios_init(void)
acpi_tables, acpi_tables_len);
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
-smbios_tables = smbios_get_table_legacy(smbios_tables_len);
-if (smbios_tables) {
-fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_tables, smbios_tables_len);
-}
-
-smbios_get_tables(smbios_tables, smbios_tables_len,
- smbios_anchor, smbios_anchor_len);
-if (smbios_anchor) {
-fw_cfg_add_file(fw_cfg, etc/smbios/smbios-tables,
-smbios_tables, smbios_tables_len);
-fw_cfg_add_file(fw_cfg, etc/smbios/smbios-anchor,
-smbios_anchor, smbios_anchor_len);
-}
+pc_build_smbios(fw_cfg);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
e820_reserve, sizeof(e820_reserve));
--
MST
Re: [Qemu-devel] [PATCH 4/5] migration: size_t'ify some of qemu-file
On 2015/8/13 18:51, Dr. David Alan Gilbert (git) wrote:
From: Dr. David Alan Gilbert dgilb...@redhat.com
This is a start on using size_t more in qemu-file and friends;
it fixes up QEMUFilePutBufferFunc and QEMUFileGetBufferFunc
to take size_t lengths and return ssize_t return values (like read(2))
and fixes up all the different implementations of them.
Note that I've not yet followed this deeply into bdrv_ implementations.
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
Reviewed-by: zhanghailiang zhang.zhanghaili...@huawei.com
include/migration/qemu-file.h | 8
migration/qemu-file-buf.c | 7 ---
migration/qemu-file-stdio.c | 11 ++-
migration/qemu-file-unix.c| 6 --
migration/rdma.c | 13 +++--
migration/savevm.c| 7 ---
trace-events | 2 +-
7 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/include/migration/qemu-file.h b/include/migration/qemu-file.h
index ea49f33..e1e2bab 100644
--- a/include/migration/qemu-file.h
+++ b/include/migration/qemu-file.h
@@ -31,15 +31,15 @@
* The pos argument can be ignored if the file is only being used for
* streaming. The handler should try to write all of the data it can.
*/
-typedef int (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf,
-int64_t pos, int size);
+typedef ssize_t (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf,
+int64_t pos, size_t size);
/* Read a chunk of data from a file at the given position. The pos argument
* can be ignored if the file is only be used for streaming. The number of
* bytes actually read should be returned.
*/
-typedef int (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf,
-int64_t pos, int size);
+typedef ssize_t (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf,
+int64_t pos, size_t size);
/* Close a file
*
diff --git a/migration/qemu-file-buf.c b/migration/qemu-file-buf.c
index 2de9330..1d9528e 100644
--- a/migration/qemu-file-buf.c
+++ b/migration/qemu-file-buf.c
@@ -372,7 +372,8 @@ typedef struct QEMUBuffer {
bool qsb_allocated;
} QEMUBuffer;
-static int buf_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t buf_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUBuffer *s = opaque;
ssize_t len = qsb_get_length(s-qsb) - pos;
@@ -387,8 +388,8 @@ static int buf_get_buffer(void *opaque, uint8_t *buf,
int64_t pos, int size)
return qsb_get_buffer(s-qsb, pos, len, buf);
}
-static int buf_put_buffer(void *opaque, const uint8_t *buf,
- int64_t pos, int size)
+static ssize_t buf_put_buffer(void *opaque, const uint8_t *buf,
+ int64_t pos, size_t size)
{
QEMUBuffer *s = opaque;
diff --git a/migration/qemu-file-stdio.c b/migration/qemu-file-stdio.c
index 285068b..dc91137 100644
--- a/migration/qemu-file-stdio.c
+++ b/migration/qemu-file-stdio.c
@@ -37,11 +37,11 @@ static int stdio_get_fd(void *opaque)
return fileno(s-stdio_file);
}
-static int stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos,
-int size)
+static ssize_t stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos,
+size_t size)
{
QEMUFileStdio *s = opaque;
-int res;
+size_t res;
res = fwrite(buf, 1, size, s-stdio_file);
@@ -51,11 +51,12 @@ static int stdio_put_buffer(void *opaque, const uint8_t
*buf, int64_t pos,
return res;
}
-static int stdio_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t stdio_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+size_t size)
{
QEMUFileStdio *s = opaque;
FILE *fp = s-stdio_file;
-int bytes;
+ssize_t bytes;
for (;;) {
clearerr(fp);
diff --git a/migration/qemu-file-unix.c b/migration/qemu-file-unix.c
index bfbc086..adfe91a 100644
--- a/migration/qemu-file-unix.c
+++ b/migration/qemu-file-unix.c
@@ -54,7 +54,8 @@ static int socket_get_fd(void *opaque)
return s-fd;
}
-static int socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUFileSocket *s = opaque;
ssize_t len;
@@ -138,7 +139,8 @@ static ssize_t unix_writev_buffer(void *opaque, struct
iovec *iov, int iovcnt,
return total;
}
-static int unix_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size)
+static ssize_t unix_get_buffer(void *opaque, uint8_t *buf, int64_t pos,
+ size_t size)
{
QEMUFileSocket *s = opaque;
ssize_t len;
diff --git
Re: [Qemu-devel] [PATCH 11/10] tcg: comment on which functions have to be called with tb_lock held
On 13/08/2015 14:51, Frederic Konrad wrote:
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 77bbff2..56b1f4d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -285,7 +285,10 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
+
+/* Protected by tb_lock. */
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
This is temporary as a first step?
Yes, I now saw that tb_lock has a huge contention in tb_find_fast. :)
I've now extracted parts of your patch tcg: protect TBContext with
tb_lock into a separate tcg: move tb_find_fast outside the tb_lock
critical section that also applies to user-mode emulation. That way I
get good scalability on Dhrystone, same as with your branch.
Do you agree with the first 10 patches as a first step towards
upstreaming the MTTCG work?
Paolo
+
struct GDBRegisterState *gdb_regs;
int gdb_num_regs;
int gdb_num_g_regs;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 0ae648f..a2cad31 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -590,6 +590,7 @@ static inline bool tcg_op_buf_full(void)
/* pool based memory allocation */
+/* tb_lock must be held for tcg_malloc_internal. */
void *tcg_malloc_internal(TCGContext *s, int size);
void tcg_pool_reset(TCGContext *s);
void tcg_pool_delete(TCGContext *s);
@@ -598,6 +599,7 @@ void tb_lock(void);
void tb_unlock(void);
void tb_lock_reset(void);
+/* Called with tb_lock held. */
static inline void *tcg_malloc(int size)
{
TCGContext *s = tcg_ctx;
diff --git a/translate-all.c b/translate-all.c
index edb9cb1..17d3cd1 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -237,6 +237,7 @@ int cpu_gen_code(CPUArchState *env,
TranslationBlock *tb, int *gen_code_size_ptr
}
/* The cpu state corresponding to 'searched_pc' is restored.
+ * Called with tb_lock held.
*/
static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock
*tb,
uintptr_t searched_pc)
@@ -424,6 +425,7 @@ static void page_init(void)
}
/* If alloc=1:
+ * Called with tb_lock held for system emulation.
* Called with mmap_lock held for user-mode emulation.
*/
static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
@@ -734,8 +736,12 @@ bool tcg_enabled(void)
return tcg_ctx.code_gen_buffer != NULL;
}
-/* Allocate a new translation block. Flush the translation buffer if
- too many translation blocks or too much generated code. */
+/*
+ * Allocate a new translation block. Flush the translation buffer if
+ * too many translation blocks or too much generated code.
+ *
+ * Called with tb_lock held.
+ */
static TranslationBlock *tb_alloc(target_ulong pc)
{
There is the famous tb_flush which needs to be called with tb_lock held
as well.
There are several place where it's called.
TranslationBlock *tb;
@@ -751,6 +757,7 @@ static TranslationBlock *tb_alloc(target_ulong pc)
return tb;
}
+/* Called with tb_lock held. */
void tb_free(TranslationBlock *tb)
{
/* In practice this is mostly used for single use temporary TB
@@ -859,7 +866,10 @@ static void tb_invalidate_check(target_ulong
address)
}
}
-/* verify that all the pages have correct rights for code */
+/* verify that all the pages have correct rights for code
+ *
+ * Called with tb_lock held.
+ */
static void tb_page_check(void)
{
TranslationBlock *tb;
@@ -947,7 +957,10 @@ static inline void tb_reset_jump(TranslationBlock
*tb, int n)
tb_set_jmp_target(tb, n, (uintptr_t)(tb-tc_ptr +
tb-tb_next_offset[n]));
}
-/* invalidate one TB */
+/* invalidate one TB
+ *
+ * Called with tb_lock held.
+ */
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
CPUState *cpu;
@@ -1036,7 +1049,7 @@ static void build_page_bitmap(PageDesc *p)
}
#endif
-/* Called with mmap_lock held for user mode emulation. */
+/* Called with tb_lock held, and mmap_lock too for user mode
emulation. */
TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
@@ -1234,7 +1247,9 @@ void tb_invalidate_phys_page_fast(tb_page_addr_t
start, int len)
}
if (!p-code_bitmap
++p-code_write_count = SMC_BITMAP_USE_THRESHOLD) {
-/* build code bitmap */
+/* build code bitmap. FIXME: writes should be protected by
+ * tb_lock, reads by tb_lock or RCU.
+ */
build_page_bitmap(p);
}
if (p-code_bitmap) {
@@ -1324,6 +1339,7 @@ static void
tb_invalidate_phys_page(tb_page_addr_t addr,
/* add the tb in the target page and protect it if necessary
*
+ * Called with tb_lock held.
* Called with mmap_lock held for user-mode emulation.
*/
static inline void
Re: [Qemu-devel] [PATCH 02/10] cpus: remove tcg_halt_cond global variable.
On 12/08/2015 18:40, Paolo Bonzini wrote:
From: KONRAD Frederic fred.kon...@greensocs.com
This removes tcg_halt_cond global variable.
We need one QemuCond per virtual cpu for multithread TCG.
Signed-off-by: KONRAD Frederic fred.kon...@greensocs.com
Message-Id: 1439220437-23957-9-git-send-email-fred.kon...@greensocs.com
[Keep tcg_halt_cond for bisectability, while making it static. - Paolo]
How does that help bisectability?
Fred
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
cpus.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9224488..8884278 100644
--- a/cpus.c
+++ b/cpus.c
@@ -813,7 +813,6 @@ static unsigned iothread_requesting_mutex;
static QemuThread io_thread;
static QemuThread *tcg_cpu_thread;
-static QemuCond *tcg_halt_cond;
/* cpu creation */
static QemuCond qemu_cpu_cond;
@@ -933,15 +932,13 @@ static void qemu_wait_io_event_common(CPUState *cpu)
cpu-thread_kicked = false;
}
-static void qemu_tcg_wait_io_event(void)
+static void qemu_tcg_wait_io_event(CPUState *cpu)
{
-CPUState *cpu;
-
while (all_cpu_threads_idle()) {
/* Start accounting real time to the virtual clock if the CPUs
are idle. */
qemu_clock_warp(QEMU_CLOCK_VIRTUAL);
-qemu_cond_wait(tcg_halt_cond, qemu_global_mutex);
+qemu_cond_wait(cpu-halt_cond, qemu_global_mutex);
}
while (iothread_requesting_mutex) {
@@ -1067,7 +1064,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
/* wait for initial kick-off after machine start */
while (first_cpu-stopped) {
-qemu_cond_wait(tcg_halt_cond, qemu_global_mutex);
+qemu_cond_wait(first_cpu-halt_cond, qemu_global_mutex);
/* process any pending work */
CPU_FOREACH(cpu) {
@@ -1088,7 +1085,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg)
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
}
}
-qemu_tcg_wait_io_event();
+qemu_tcg_wait_io_event(QTAILQ_FIRST(cpus));
}
return NULL;
@@ -1265,6 +1262,7 @@ void resume_all_vcpus(void)
static void qemu_tcg_init_vcpu(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
+static QemuCond *tcg_halt_cond;
tcg_cpu_address_space_init(cpu, cpu-as);
[Qemu-devel] [PULL 16/24] pc: Remove redundant arguments from pc_cmos_init()
From: Eduardo Habkost ehabk...@redhat.com
Remove arguments that can be found in PCMachineState.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 2 --
hw/i386/pc.c | 16 +++-
hw/i386/pc_piix.c| 5 +
hw/i386/pc_q35.c | 5 +
4 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c433602..a56f70c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -198,8 +198,6 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
uint32 hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(PCMachineState *pcms,
- ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
- const char *boot_device,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 54b28a3..681ea85 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -429,8 +429,6 @@ static void pc_cmos_init_late(void *opaque)
}
void pc_cmos_init(PCMachineState *pcms,
- ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
- const char *boot_device,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
{
@@ -442,12 +440,12 @@ void pc_cmos_init(PCMachineState *pcms,
/* memory size */
/* base memory (first MiB) */
-val = MIN(ram_size / 1024, 640);
+val = MIN(pcms-below_4g_mem_size / 1024, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val 8);
/* extended memory (next 64MiB) */
-if (ram_size 1024 * 1024) {
-val = (ram_size - 1024 * 1024) / 1024;
+if (pcms-below_4g_mem_size 1024 * 1024) {
+val = (pcms-below_4g_mem_size - 1024 * 1024) / 1024;
} else {
val = 0;
}
@@ -458,8 +456,8 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val 8);
/* memory between 16MiB and 4GiB */
-if (ram_size 16 * 1024 * 1024) {
-val = (ram_size - 16 * 1024 * 1024) / 65536;
+if (pcms-below_4g_mem_size 16 * 1024 * 1024) {
+val = (pcms-below_4g_mem_size - 16 * 1024 * 1024) / 65536;
} else {
val = 0;
}
@@ -468,7 +466,7 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val 8);
/* memory above 4GiB */
-val = above_4g_mem_size / 65536;
+val = pcms-above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val 8);
rtc_set_memory(s, 0x5d, val 16);
@@ -484,7 +482,7 @@ void pc_cmos_init(PCMachineState *pcms,
object_property_set_link(OBJECT(pcms), OBJECT(s),
rtc_state, error_abort);
-set_boot_dev(s, boot_device, local_err);
+set_boot_dev(s, MACHINE(pcms)-boot_order, local_err);
if (local_err) {
error_report_err(local_err);
exit(1);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index f64f029..c98635f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -267,10 +267,7 @@ static void pc_init1(MachineState *machine)
}
}
-pc_cmos_init(pcms,
- pcms-below_4g_mem_size, pcms-above_4g_mem_size,
- machine-boot_order,
- idebus[0], idebus[1], rtc_state);
+pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
if (pci_enabled usb_enabled()) {
pci_create_simple(pci_bus, piix3_devfn + 2, piix3-usb-uhci);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index af5fd9f..79e3f9b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -276,10 +276,7 @@ static void pc_q35_init(MachineState *machine)
0xb100),
8, NULL, 0);
-pc_cmos_init(pcms,
- pcms-below_4g_mem_size, pcms-above_4g_mem_size,
- machine-boot_order,
- idebus[0], idebus[1], rtc_state);
+pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
pc_vga_init(isa_bus, host_bus);
--
MST
[Qemu-devel] [PULL 07/24] pc: Rename pc_machine variables to pcms
From: Eduardo Habkost ehabk...@redhat.com
Make the code use the same variable name everywhere. pcms is already
being used in existing code and it's shorter.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
hw/i386/pc.c | 4 ++--
hw/i386/pc_piix.c | 20 ++--
hw/i386/pc_q35.c | 20 ++--
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7c811cd..ad1a861 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -435,7 +435,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t
above_4g_mem_size,
{
int val;
static pc_cmos_init_late_arg arg;
-PCMachineState *pc_machine = PC_MACHINE(machine);
+PCMachineState *pcms = PC_MACHINE(machine);
Error *local_err = NULL;
/* various important CMOS locations needed by PC/Bochs bios */
@@ -478,7 +478,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t
above_4g_mem_size,
object_property_add_link(OBJECT(machine), rtc_state,
TYPE_ISA_DEVICE,
- (Object **)pc_machine-rtc,
+ (Object **)pcms-rtc,
object_property_allow_set_link,
OBJ_PROP_LINK_UNREF_ON_RELEASE, error_abort);
object_property_set_link(OBJECT(machine), OBJECT(s),
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 482555f..c88ed0d 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -78,7 +78,7 @@ static bool kvmclock_enabled = true;
/* PC hardware initialisation */
static void pc_init1(MachineState *machine)
{
-PCMachineState *pc_machine = PC_MACHINE(machine);
+PCMachineState *pcms = PC_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
int i;
@@ -117,13 +117,13 @@ static void pc_init1(MachineState *machine)
/* Handle the machine opt max-ram-below-4g. It is basically doing
* min(qemu limit, user limit).
*/
-if (lowmem pc_machine-max_ram_below_4g) {
-lowmem = pc_machine-max_ram_below_4g;
+if (lowmem pcms-max_ram_below_4g) {
+lowmem = pcms-max_ram_below_4g;
if (machine-ram_size - lowmem lowmem
lowmem ((1ULL 30) - 1)) {
error_report(Warning: Large machine and max_ram_below_4g(%PRIu64
) not a multiple of 1G; possible bad performance.,
- pc_machine-max_ram_below_4g);
+ pcms-max_ram_below_4g);
}
}
@@ -234,14 +234,14 @@ static void pc_init1(MachineState *machine)
pc_vga_init(isa_bus, pci_enabled ? pci_bus : NULL);
-assert(pc_machine-vmport != ON_OFF_AUTO_MAX);
-if (pc_machine-vmport == ON_OFF_AUTO_AUTO) {
-pc_machine-vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
+assert(pcms-vmport != ON_OFF_AUTO_MAX);
+if (pcms-vmport == ON_OFF_AUTO_AUTO) {
+pcms-vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
}
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, rtc_state, true,
- (pc_machine-vmport != ON_OFF_AUTO_ON), 0x4);
+ (pcms-vmport != ON_OFF_AUTO_ON), 0x4);
pc_nic_init(isa_bus, pci_bus);
@@ -286,13 +286,13 @@ static void pc_init1(MachineState *machine)
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
gsi[9], smi_irq,
- pc_machine_is_smm_enabled(pc_machine),
+ pc_machine_is_smm_enabled(pcms),
piix4_pm);
smbus_eeprom_init(smbus, 8, NULL, 0);
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
- (Object **)pc_machine-acpi_dev,
+ (Object **)pcms-acpi_dev,
object_property_allow_set_link,
OBJ_PROP_LINK_UNREF_ON_RELEASE, error_abort);
object_property_set_link(OBJECT(machine), OBJECT(piix4_pm),
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 1da9b3a..d0e4350 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -65,7 +65,7 @@ static bool has_reserved_memory = true;
/* PC hardware initialisation */
static void pc_q35_init(MachineState *machine)
{
-PCMachineState *pc_machine = PC_MACHINE(machine);
+PCMachineState *pcms = PC_MACHINE(machine);
ram_addr_t below_4g_mem_size, above_4g_mem_size;
Q35PCIHost *q35_host;
PCIHostState *phb;
@@ -108,13 +108,13 @@ static void pc_q35_init(MachineState *machine)
/* Handle the machine opt max-ram-below-4g. It is basically doing
* min(qemu limit, user limit).
[Qemu-devel] [PULL 01/24] make: fix where dependency *.d are stored.
From: Victor Kaplansky vict...@redhat.com In rules like bar/%.o: %.c there is a difference between $(*D) and $(@D). $(*D) expands to '.', while $(@D) expands to 'bar'. It is cleaner to generate *.d in the same directory where appropriate *.o resides. This allows precise including of dependency info from .d files. As a hack, we also touch two sources for generated *.hex files. Without this hack, anyone doing git pull; make will not get *.hex rebuilt correctly since the dependency file would be missing. Signed-off-by: Victor Kaplansky vict...@redhat.com Reviewed-by: Michael S. Tsirkin m...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/i386/acpi-dsdt.dsl | 1 - hw/i386/q35-acpi-dsdt.dsl | 1 + rules.mak | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl index a2d84ec..8dba096 100644 --- a/hw/i386/acpi-dsdt.dsl +++ b/hw/i386/acpi-dsdt.dsl @@ -43,7 +43,6 @@ DefinitionBlock ( #include acpi-dsdt-hpet.dsl - / * PIIX4 PM / diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl index 16eaca3..7be7b37 100644 --- a/hw/i386/q35-acpi-dsdt.dsl +++ b/hw/i386/q35-acpi-dsdt.dsl @@ -22,6 +22,7 @@ * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. */ + ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode DefinitionBlock ( diff --git a/rules.mak b/rules.mak index aec27f8..6e35c36 100644 --- a/rules.mak +++ b/rules.mak @@ -17,7 +17,7 @@ MAKEFLAGS += -rR QEMU_CXXFLAGS = -D__STDC_LIMIT_MACROS $(filter-out -Wstrict-prototypes -Wmissing-prototypes -Wnested-externs -Wold-style-declaration -Wold-style-definition -Wredundant-decls, $(QEMU_CFLAGS)) # Flags for dependency generation -QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(*D)/$(*F).d +QEMU_DGFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d # Same as -I$(SRC_PATH) -I., but for the nested source/object directories QEMU_INCLUDES += -I$(D) -I$(@D) -- MST
[Qemu-devel] [PULL 12/24] pc: Use PCMachineState for pc_memory_init() argument
From: Eduardo Habkost ehabk...@redhat.com
pc_memory_init() already expects a PCMachineState object, there's no
point in upcasting it to MachineState before calling the function.
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
Reviewed-by: Michael S. Tsirkin m...@redhat.com
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
include/hw/i386/pc.h | 2 +-
hw/i386/pc.c | 4 ++--
hw/i386/pc_piix.c| 2 +-
hw/i386/pc_q35.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index d8184cd..4fa2b3f 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -185,7 +185,7 @@ FWCfgState *xen_load_linux(const char *kernel_filename,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
PcGuestInfo *guest_info);
-FWCfgState *pc_memory_init(MachineState *machine,
+FWCfgState *pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 255476b..a9a9cf4 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1289,7 +1289,7 @@ FWCfgState *xen_load_linux(const char *kernel_filename,
return fw_cfg;
}
-FWCfgState *pc_memory_init(MachineState *machine,
+FWCfgState *pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
@@ -1301,7 +1301,7 @@ FWCfgState *pc_memory_init(MachineState *machine,
MemoryRegion *ram, *option_rom_mr;
MemoryRegion *ram_below_4g, *ram_above_4g;
FWCfgState *fw_cfg;
-PCMachineState *pcms = PC_MACHINE(machine);
+MachineState *machine = MACHINE(pcms);
assert(machine-ram_size == below_4g_mem_size + above_4g_mem_size);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b975c21..18e9aa5 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -178,7 +178,7 @@ static void pc_init1(MachineState *machine)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
-pc_memory_init(machine, system_memory,
+pc_memory_init(pcms, system_memory,
below_4g_mem_size, above_4g_mem_size,
rom_memory, ram_memory, guest_info);
} else if (machine-kernel_filename != NULL) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 441e9d9..6763f0d 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -170,7 +170,7 @@ static void pc_q35_init(MachineState *machine)
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
-pc_memory_init(machine, get_system_memory(),
+pc_memory_init(pcms, get_system_memory(),
below_4g_mem_size, above_4g_mem_size,
rom_memory, ram_memory, guest_info);
}
--
MST
[Qemu-devel] [PULL 06/24] pc: Use error_abort when registering properties
From: Eduardo Habkost ehabk...@redhat.com No errors should happen when registering the properties, but we shouldn't silently ignore them if they happen. Signed-off-by: Eduardo Habkost ehabk...@redhat.com Reviewed-by: Michael S. Tsirkin m...@redhat.com Signed-off-by: Michael S. Tsirkin m...@redhat.com --- hw/i386/pc.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7661ea9..7c811cd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1886,39 +1886,39 @@ static void pc_machine_initfn(Object *obj) object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, int, pc_machine_get_hotplug_memory_region_size, -NULL, NULL, NULL, NULL); +NULL, NULL, NULL, error_abort); pcms-max_ram_below_4g = 1ULL 32; /* 4G */ object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, size, pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, -NULL, NULL, NULL); +NULL, NULL, error_abort); object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, Maximum ram below the 4G boundary (32bit boundary), -NULL); +error_abort); pcms-smm = ON_OFF_AUTO_AUTO; object_property_add(obj, PC_MACHINE_SMM, OnOffAuto, pc_machine_get_smm, pc_machine_set_smm, -NULL, NULL, NULL); +NULL, NULL, error_abort); object_property_set_description(obj, PC_MACHINE_SMM, Enable SMM (pc q35), -NULL); +error_abort); pcms-vmport = ON_OFF_AUTO_AUTO; object_property_add(obj, PC_MACHINE_VMPORT, OnOffAuto, pc_machine_get_vmport, pc_machine_set_vmport, -NULL, NULL, NULL); +NULL, NULL, error_abort); object_property_set_description(obj, PC_MACHINE_VMPORT, Enable vmport (pc q35), -NULL); +error_abort); pcms-enforce_aligned_dimm = true; object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, pc_machine_get_aligned_dimm, - NULL, NULL); + NULL, error_abort); } static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) -- MST
