Re: [Qemu-devel] Failing QEMU iotest 175
On 03/05/2019 22.21, Eric Blake wrote: > On 5/2/19 11:37 PM, Thomas Huth wrote: >> On 02/05/2019 23.56, Eric Blake wrote: >>> On 4/28/19 10:18 AM, Thomas Huth wrote: QEMU iotest 175 is failing for me when I run it with -raw: == creating image with default preallocation == Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 -size=1048576, blocks=0 +size=1048576, blocks=2 >>> >>> What filesystem? >> >> ext4 > > Hmm, it's passing for me on ext4, but that probably means we have > different configuration parameters. I'm not sure how to easily show what > parameters a particular ext4 partition uses to compare the differences > between your setup and mine (mine is tuned to whatever defaults Fedora's > installer chose on my behalf), so maybe someone else can chime in. $ sudo tune2fs -l /dev/mapper/Home tune2fs 1.42.9 (28-Dec-2013) Filesystem volume name: Last mounted on: /home Filesystem magic number: 0xEF53 Filesystem revision #:1 (dynamic) Filesystem features: has_journal ext_attr dir_index filetype needs_recovery meta_bg extent 64bit flex_bg sparse_super large_file huge_file uninit_bg dir_nlink extra_isize Filesystem flags: signed_directory_hash Default mount options:user_xattr acl Filesystem state: clean Errors behavior: Continue Filesystem OS type: Linux Inode count: 36700160 Block count: 146800640 Reserved block count: 5873663 Free blocks: 56266267 Free inodes: 35403275 First block: 1 Block size: 1024 Fragment size:1024 Group descriptor size:64 Blocks per group: 8192 Fragments per group: 8192 Inodes per group: 2048 Inode blocks per group: 256 First meta block group: 258 Flex block group size:16 Filesystem created: Thu Apr 19 18:34:33 2018 Last mount time: Sat May 4 08:20:36 2019 Last write time: Sat May 4 08:20:36 2019 Mount count: 224 Maximum mount count: -1 Last checked: Thu Apr 19 18:34:33 2018 Check interval: 0 () Lifetime writes: 1826 GB Reserved blocks uid: 0 (user root) Reserved blocks gid: 0 (group root) First inode: 11 Inode size: 128 Journal inode:8 First orphan inode: 11076944 Default directory hash: half_md4 Directory Hash Seed: 08e1be04-c3a3-4c37-a059-cf54af5c4bc0 Journal backup: inode blocks IIRC I talked to stefanha on IRC about this some weeks ago already, and he was able to reproduce the problem when using a certain parameter to create the file system. However, I fail to remember which parameter it was. Maybe Stefan still remembers... Thomas signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PULL 19/19] configure: automatically pick python3 is available
On 03/05/2019 19.04, Philippe Mathieu-Daudé wrote: > On 5/3/19 6:41 PM, Thomas Huth wrote: >> On 03/05/2019 02.41, Eduardo Habkost wrote: >>> From: Daniel P. Berrangé >>> >>> Unless overridden via an env var or configure arg, QEMU will only look >>> for the 'python' binary in $PATH. This is unhelpful on distros which >>> are only shipping Python 3.x (eg Fedora) in their default install as, >>> if they comply with PEP 394, the bare 'python' binary won't exist. >>> >>> This changes configure so that by default it will search for all three >>> common python binaries, preferring to find Python 3.x versions. >>> >>> Signed-off-by: Daniel P. Berrangé >>> Message-Id: <20190327170701.23798-1-berra...@redhat.com> >>> Signed-off-by: Eduardo Habkost >>> --- >>> configure | 18 +++--- >>> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> I haven't bisected it, but I think this patch here broke the gitlab-ci tests: >> >> https://gitlab.com/huth/qemu/-/jobs/206806257 > > What's the easier way to notice that automatically? Maybe Peter could tweak one of his acceptance test environments to use a non-UTF-8 locale? Thomas
Re: [Qemu-devel] [PATCH] Deprecate Python 2 support
On 03/05/2019 21.37, Eduardo Habkost wrote:
> Python 2 will reach end of life in January 1 2020. Declare it as
> deprecated.
>
> Signed-off-by: Eduardo Habkost
> ---
> configure| 8
> qemu-deprecated.texi | 8
> 2 files changed, 16 insertions(+)
>
> diff --git a/configure b/configure
> index 5b183c2e39..50385061ed 100755
> --- a/configure
> +++ b/configure
> @@ -6461,6 +6461,14 @@ if test "$supported_os" = "no"; then
> echo "us upstream at qemu-devel@nongnu.org."
> fi
>
> +# Note that if the Python conditional here evaluates True we will exit
> +# with status 1 which is a shell 'false' value.
> +if ! $python -c 'import sys; sys.exit(sys.version_info < (3,0))'; then
> + echo
> + echo "WARNING: Python 2 support is deprecated" >&2
> + echo "WARNING: Python 3 will be required for building future versions of
> QEMU" >&2
> +fi
> +
> config_host_mak="config-host.mak"
>
> echo "# Automatically generated by configure - do not modify"
> >config-all-disas.mak
> diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
> index 842e71b11d..2f2d9a3e95 100644
> --- a/qemu-deprecated.texi
> +++ b/qemu-deprecated.texi
> @@ -206,3 +206,11 @@ Note that if you are exposing the export via /dev/nbd0,
> it is easier
> to just export the entire image and then mount only /dev/nbd0p1 than
> it is to reinvoke @command{qemu-nbd -c /dev/nbd0} limited to just a
> subset of the image.
> +
> +@section Build system
> +
> +@subsection Python 2 support (since 4.1.0)
> +
> +In the future, QEMU will require Python 3 to be available at
> +build time. Support for Python 2 in scripts shipped with QEMU
> +is deprecated.
Reviewed-by: Thomas Huth
Re: [Qemu-devel] [PATCH] tests/tcg/alpha: add system boot.S
On 5/3/19 10:07 AM, Alex Bennée wrote: > + ldah$sp, $stack_end($gp)!gprelhigh > + lda $sp, $stack_end($gp)!gprellow Bah. $sp As is, this works only because the test case is tiny, and this happens to evaluate to the middle of the stack allocation. r~
[Qemu-devel] [PATCH] tests/docker: Test more components on the Fedora default image
Install optional dependencies of QEMU to get better coverage. The following components are now enabled: $ ./configure ... Multipath support yes VNC SASL support yes RDMA support yes PVRDMA supportyes libiscsi support yes seccomp support yes libpmem support yes libudev yes Note: The udev-devel package is provided by systemd-devel. Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/fedora.docker | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 69d4a7f5d75..afbba29adaa 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -8,6 +8,7 @@ ENV PACKAGES \ bzip2-devel \ ccache \ clang \ +cyrus-sasl-devel \ device-mapper-multipath-devel \ findutils \ flex \ @@ -23,13 +24,17 @@ ENV PACKAGES \ libaio-devel \ libasan \ libattr-devel \ +libblockdev-mpath-devel \ libcap-devel \ libcap-ng-devel \ libcurl-devel \ libfdt-devel \ +libiscsi-devel \ libjpeg-devel \ +libpmem-devel \ libpng-devel \ librbd-devel \ +libseccomp-devel \ libssh2-devel \ libubsan \ libusbx-devel \ @@ -74,10 +79,12 @@ ENV PACKAGES \ pixman-devel \ python3 \ PyYAML \ +rdma-core-devel \ SDL2-devel \ snappy-devel \ sparse \ spice-server-devel \ +systemd-devel \ systemtap-sdt-devel \ tar \ usbredir-devel \ -- 2.20.1
[Qemu-devel] [PATCH v3 31/31] tcg/aarch64: Do not advertise minmax for MO_64
The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 5684b39e1f..e13960711d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2332,16 +2332,16 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: -case INDEX_op_smax_vec: -case INDEX_op_smin_vec: -case INDEX_op_umax_vec: -case INDEX_op_umin_vec: case INDEX_op_shlv_vec: return 1; case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: return -1; case INDEX_op_mul_vec: +case INDEX_op_smax_vec: +case INDEX_op_smin_vec: +case INDEX_op_umax_vec: +case INDEX_op_umin_vec: return vece < MO_64; default: -- 2.17.1
[Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl
From: Philippe Mathieu-Daudé
Reviewed-by: Bastian Koppelmann
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20190423102145.14812-3-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 27 +--
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8f6416144e..06c4485e55 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,
uint32_t n, uint32_t mode)
static inline void gen_abs(TCGv ret, TCGv r1)
{
-TCGv temp = tcg_temp_new();
-TCGv t0 = tcg_const_i32(0);
-
-tcg_gen_neg_tl(temp, r1);
-tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
+tcg_gen_abs_tl(ret, r1);
/* overflow can only happen, if r1 = 0x8000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x8000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
@@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1)
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
-
-tcg_temp_free(temp);
-tcg_temp_free(t0);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
@@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
-tcg_gen_neg_tl(temp, temp3);
-/* use cpu_PSW_AV to compare against 0 */
-tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
-tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
-tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+tcg_gen_abs_tl(temp, temp3);
+tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
@@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
-tcg_gen_neg_tl(temp, temp3);
-/* use cpu_PSW_AV to compare against 0 */
-tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
-tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
-tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+tcg_gen_abs_tl(temp, temp3);
+tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
--
2.17.1
[Qemu-devel] [PATCH v3 28/31] target/s390x: Use tcg_gen_abs_i64
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/translate.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index d4951836ad..e8e8a79b7d 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1407,13 +1407,7 @@ static DisasJumpType help_branch(DisasContext *s,
DisasCompare *c,
static DisasJumpType op_abs(DisasContext *s, DisasOps *o)
{
-TCGv_i64 z, n;
-z = tcg_const_i64(0);
-n = tcg_temp_new_i64();
-tcg_gen_neg_i64(n, o->in2);
-tcg_gen_movcond_i64(TCG_COND_LT, o->out, o->in2, z, n, o->in2);
-tcg_temp_free_i64(n);
-tcg_temp_free_i64(z);
+tcg_gen_abs_i64(o->out, o->in2);
return DISAS_NEXT;
}
--
2.17.1
[Qemu-devel] [PATCH v3 26/31] target/ppc: Use tcg_gen_abs_i32
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20190423102145.14812-2-f4...@amsat.org>
Signed-off-by: Richard Henderson
---
target/ppc/translate/spe-impl.inc.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/target/ppc/translate/spe-impl.inc.c
b/target/ppc/translate/spe-impl.inc.c
index 7ab0a29b5f..36b4d5654d 100644
--- a/target/ppc/translate/spe-impl.inc.c
+++ b/target/ppc/translate/spe-impl.inc.c
@@ -126,19 +126,7 @@ static inline void gen_##name(DisasContext *ctx)
\
tcg_temp_free_i32(t0);\
}
-static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
-{
-TCGLabel *l1 = gen_new_label();
-TCGLabel *l2 = gen_new_label();
-
-tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
-tcg_gen_neg_i32(ret, arg1);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_mov_i32(ret, arg1);
-gen_set_label(l2);
-}
-GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
+GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32);
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
--
2.17.1
[Qemu-devel] [PATCH v3 30/31] target/xtensa: Use tcg_gen_abs_i32
Acked-by: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 301c8e3161..b063fa85f2 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1709,14 +1709,7 @@ void restore_state_to_opc(CPUXtensaState *env,
TranslationBlock *tb,
static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
-TCGv_i32 zero = tcg_const_i32(0);
-TCGv_i32 neg = tcg_temp_new_i32();
-
-tcg_gen_neg_i32(neg, arg[1].in);
-tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out,
-arg[1].in, zero, arg[1].in, neg);
-tcg_temp_free(neg);
-tcg_temp_free(zero);
+tcg_gen_abs_i32(arg[0].out, arg[1].in);
}
static void translate_add(DisasContext *dc, const OpcodeArg arg[],
--
2.17.1
[Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value
Remove a function of the same name from target/arm/.
Use a branchless implementation of abs gleaned from gcc.
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-op.h | 5 +
target/arm/translate.c | 10 --
tcg/tcg-op.c | 20
3 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 472b73cb38..660fe205d0 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -335,6 +335,7 @@ void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32
arg2);
void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
+void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
{
@@ -534,6 +535,7 @@ void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64
arg2);
void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
+void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
#if TCG_TARGET_REG_BITS == 64
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
@@ -973,6 +975,7 @@ void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
TCGv_vec b);
void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
@@ -1019,6 +1022,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg
offset, TCGType t);
#define tcg_gen_addi_tl tcg_gen_addi_i64
#define tcg_gen_sub_tl tcg_gen_sub_i64
#define tcg_gen_neg_tl tcg_gen_neg_i64
+#define tcg_gen_abs_tl tcg_gen_abs_i64
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
#define tcg_gen_subi_tl tcg_gen_subi_i64
#define tcg_gen_and_tl tcg_gen_and_i64
@@ -1131,6 +1135,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg
offset, TCGType t);
#define tcg_gen_addi_tl tcg_gen_addi_i32
#define tcg_gen_sub_tl tcg_gen_sub_i32
#define tcg_gen_neg_tl tcg_gen_neg_i32
+#define tcg_gen_abs_tl tcg_gen_abs_i32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
#define tcg_gen_subi_tl tcg_gen_subi_i32
#define tcg_gen_and_tl tcg_gen_and_i32
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 35bd426a3d..b25781554f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -604,16 +604,6 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32
t1)
tcg_temp_free_i32(tmp1);
}
-static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src)
-{
-TCGv_i32 c0 = tcg_const_i32(0);
-TCGv_i32 tmp = tcg_temp_new_i32();
-tcg_gen_neg_i32(tmp, src);
-tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp);
-tcg_temp_free_i32(c0);
-tcg_temp_free_i32(tmp);
-}
-
static void shifter_out_im(TCGv_i32 var, int shift)
{
if (shift == 0) {
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index a00d1df37e..0ac291f1c4 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1091,6 +1091,16 @@ void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32
b)
tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a);
}
+void tcg_gen_abs_i32(TCGv_i32 ret, TCGv_i32 a)
+{
+TCGv_i32 t = tcg_temp_new_i32();
+
+tcg_gen_sari_i32(t, a, 31);
+tcg_gen_xor_i32(ret, a, t);
+tcg_gen_sub_i32(ret, ret, t);
+tcg_temp_free_i32(t);
+}
+
/* 64-bit ops */
#if TCG_TARGET_REG_BITS == 32
@@ -2548,6 +2558,16 @@ void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64
b)
tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a);
}
+void tcg_gen_abs_i64(TCGv_i64 ret, TCGv_i64 a)
+{
+TCGv_i64 t = tcg_temp_new_i64();
+
+tcg_gen_sari_i64(t, a, 63);
+tcg_gen_xor_i64(ret, a, t);
+tcg_gen_sub_i64(ret, ret, t);
+tcg_temp_free_i64(t);
+}
+
/* Size changing operations. */
void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
--
2.17.1
[Qemu-devel] [PATCH v3 17/31] tcg/aarch64: Support vector variable shift opcodes
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.opc.h | 2 ++
tcg/aarch64/tcg-target.inc.c | 42
3 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ce2bb1f90b..f5640a229b 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -134,7 +134,7 @@ typedef enum {
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h
index 4816a6c3d4..59e1d3f7f7 100644
--- a/tcg/aarch64/tcg-target.opc.h
+++ b/tcg/aarch64/tcg-target.opc.h
@@ -1,3 +1,5 @@
/* Target-specific opcodes for host vector expansion. These will be
emitted by tcg_expand_vec_op. For those familiar with GCC internals,
consider these to be UNSPEC with names. */
+
+DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 15ab35adf7..7d842cad47 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -536,12 +536,14 @@ typedef enum {
I3616_CMEQ = 0x2e208c00,
I3616_SMAX = 0x0e206400,
I3616_SMIN = 0x0e206c00,
+I3616_SSHL = 0x0e204400,
I3616_SQADD = 0x0e200c00,
I3616_SQSUB = 0x0e202c00,
I3616_UMAX = 0x2e206400,
I3616_UMIN = 0x2e206c00,
I3616_UQADD = 0x2e200c00,
I3616_UQSUB = 0x2e202c00,
+I3616_USHL = 0x2e204400,
/* AdvSIMD two-reg misc. */
I3617_CMGT0 = 0x0e208800,
@@ -2256,6 +2258,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sari_vec:
tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
break;
+case INDEX_op_shlv_vec:
+tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
+break;
+case INDEX_op_aa64_sshl_vec:
+tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
+break;
case INDEX_op_cmp_vec:
{
TCGCond cond = args[3];
@@ -2323,7 +2331,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_shlv_vec:
return 1;
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
+return -1;
case INDEX_op_mul_vec:
return vece < MO_64;
@@ -2335,6 +2347,32 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
+va_list va;
+TCGv_vec v0, v1, v2, t1;
+
+va_start(va, a0);
+v0 = temp_tcgv_vec(arg_temp(a0));
+v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+
+switch (opc) {
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
+/* Right shifts are negative left shifts for AArch64. */
+t1 = tcg_temp_new_vec(type);
+tcg_gen_neg_vec(vece, t1, v2);
+opc = (opc == INDEX_op_shrv_vec
+ ? INDEX_op_shlv_vec : INDEX_op_aa64_sshl_vec);
+vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+tcg_temp_free_vec(t1);
+break;
+
+default:
+g_assert_not_reached();
+}
+
+va_end(va);
}
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
@@ -2516,6 +2554,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
+case INDEX_op_aa64_sshl_vec:
return &w_w_w;
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
--
2.17.1
[Qemu-devel] [PATCH v3 25/31] target/cris: Use tcg_gen_abs_tl
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b005a5c20e..31b40a57f9 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -1686,18 +1686,11 @@ static int dec_cmp_r(CPUCRISState *env, DisasContext
*dc)
static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
{
-TCGv t0;
-
LOG_DIS("abs $r%u, $r%u\n",
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
-t0 = tcg_temp_new();
-tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
-tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
-tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
-tcg_temp_free(t0);
-
+tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
--
2.17.1
[Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 68 +++---
1 file changed, 24 insertions(+), 44 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8d08625c33..b5217f632f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5075,40 +5075,26 @@ static void gen_ecowx(DisasContext *ctx)
/* abs - abs. */
static void gen_abs(DisasContext *ctx)
{
-TCGLabel *l1 = gen_new_label();
-TCGLabel *l2 = gen_new_label();
-tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
-tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-gen_set_label(l2);
+TCGv d = cpu_gpr[rD(ctx->opcode)];
+TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+tcg_gen_abs_tl(d, a);
if (unlikely(Rc(ctx->opcode) != 0)) {
-gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+gen_set_Rc0(ctx, d);
}
}
/* abso - abso. */
static void gen_abso(DisasContext *ctx)
{
-TCGLabel *l1 = gen_new_label();
-TCGLabel *l2 = gen_new_label();
-TCGLabel *l3 = gen_new_label();
-/* Start with XER OV disabled, the most likely case */
-tcg_gen_movi_tl(cpu_ov, 0);
-tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
-tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x8000, l1);
-tcg_gen_movi_tl(cpu_ov, 1);
-tcg_gen_movi_tl(cpu_so, 1);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-tcg_gen_br(l3);
-gen_set_label(l2);
-tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-gen_set_label(l3);
+TCGv d = cpu_gpr[rD(ctx->opcode)];
+TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x8000);
+tcg_gen_abs_tl(d, a);
+tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
if (unlikely(Rc(ctx->opcode) != 0)) {
-gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+gen_set_Rc0(ctx, d);
}
}
@@ -5344,34 +5330,28 @@ static void gen_mulo(DisasContext *ctx)
/* nabs - nabs. */
static void gen_nabs(DisasContext *ctx)
{
-TCGLabel *l1 = gen_new_label();
-TCGLabel *l2 = gen_new_label();
-tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
-tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-gen_set_label(l2);
+TCGv d = cpu_gpr[rD(ctx->opcode)];
+TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+tcg_gen_abs_tl(d, a);
+tcg_gen_neg_tl(d, d);
if (unlikely(Rc(ctx->opcode) != 0)) {
-gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+gen_set_Rc0(ctx, d);
}
}
/* nabso - nabso. */
static void gen_nabso(DisasContext *ctx)
{
-TCGLabel *l1 = gen_new_label();
-TCGLabel *l2 = gen_new_label();
-tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
-tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
-gen_set_label(l2);
+TCGv d = cpu_gpr[rD(ctx->opcode)];
+TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+tcg_gen_abs_tl(d, a);
+tcg_gen_neg_tl(d, d);
/* nabs never overflows */
tcg_gen_movi_tl(cpu_ov, 0);
if (unlikely(Rc(ctx->opcode) != 0)) {
-gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+gen_set_Rc0(ctx, d);
}
}
--
2.17.1
[Qemu-devel] [PATCH v3 16/31] tcg/i386: Support vector variable shift opcodes
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 35 +++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 241bf19413..b240633455 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -184,7 +184,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec have_avx2
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 5b33bbd99b..c9448b6d84 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -467,6 +467,11 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
+#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
+#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
+#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
+#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32(0x90)
@@ -2707,6 +2712,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const umax_insn[4] = {
OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
};
+static int const shlv_insn[4] = {
+/* TODO: AVX512 adds support for MO_16. */
+OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
+};
+static int const shrv_insn[4] = {
+/* TODO: AVX512 adds support for MO_16. */
+OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
+};
+static int const sarv_insn[4] = {
+/* TODO: AVX512 adds support for MO_16, MO_64. */
+OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
+};
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
@@ -2759,6 +2776,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_umax_vec:
insn = umax_insn[vece];
goto gen_simd;
+case INDEX_op_shlv_vec:
+insn = shlv_insn[vece];
+goto gen_simd;
+case INDEX_op_shrv_vec:
+insn = shrv_insn[vece];
+goto gen_simd;
+case INDEX_op_sarv_vec:
+insn = sarv_insn[vece];
+goto gen_simd;
case INDEX_op_x86_punpckl_vec:
insn = punpckl_insn[vece];
goto gen_simd;
@@ -3136,6 +3162,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_umin_vec:
case INDEX_op_smax_vec:
case INDEX_op_umax_vec:
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+case INDEX_op_sarv_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
@@ -3193,6 +3222,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
}
return 1;
+case INDEX_op_shlv_vec:
+case INDEX_op_shrv_vec:
+return have_avx2 && vece >= MO_32;
+case INDEX_op_sarv_vec:
+return have_avx2 && vece == MO_32;
+
case INDEX_op_mul_vec:
if (vece == MO_8) {
/* We can expand the operation for MO_8. */
--
2.17.1
[Qemu-devel] [PATCH v3 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 2 --
target/arm/neon_helper.c | 5 -
target/arm/translate-a64.c | 41 +-
target/arm/translate.c | 11 +++---
4 files changed, 8 insertions(+), 51 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 50cb036378..132aa1682e 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -352,8 +352,6 @@ DEF_HELPER_2(neon_ceq_u8, i32, i32, i32)
DEF_HELPER_2(neon_ceq_u16, i32, i32, i32)
DEF_HELPER_2(neon_ceq_u32, i32, i32, i32)
-DEF_HELPER_1(neon_abs_s8, i32, i32)
-DEF_HELPER_1(neon_abs_s16, i32, i32)
DEF_HELPER_1(neon_clz_u8, i32, i32)
DEF_HELPER_1(neon_clz_u16, i32, i32)
DEF_HELPER_1(neon_cls_s8, i32, i32)
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
index ed1c6fc41c..4259056723 100644
--- a/target/arm/neon_helper.c
+++ b/target/arm/neon_helper.c
@@ -1228,11 +1228,6 @@ NEON_VOP(ceq_u16, neon_u16, 2)
NEON_VOP(ceq_u32, neon_u32, 1)
#undef NEON_FN
-#define NEON_FN(dest, src, dummy) dest = (src < 0) ? -src : src
-NEON_VOP1(abs_s8, neon_s8, 4)
-NEON_VOP1(abs_s16, neon_s16, 2)
-#undef NEON_FN
-
/* Count Leading Sign/Zero Bits. */
static inline int do_clz8(uint8_t x)
{
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9dcc5ff3a3..b7c5a928b4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9468,11 +9468,7 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
if (u) {
tcg_gen_neg_i64(tcg_rd, tcg_rn);
} else {
-TCGv_i64 tcg_zero = tcg_const_i64(0);
-tcg_gen_neg_i64(tcg_rd, tcg_rn);
-tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
-tcg_rn, tcg_rd);
-tcg_temp_free_i64(tcg_zero);
+tcg_gen_abs_i64(tcg_rd, tcg_rn);
}
break;
case 0x2f: /* FABS */
@@ -12366,11 +12362,12 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
break;
case 0xb:
-if (u) { /* NEG */
+if (u) { /* ABS, NEG */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
-return;
+} else {
+gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
}
-break;
+return;
}
if (size == 3) {
@@ -12438,17 +12435,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
}
break;
-case 0xb: /* ABS, NEG */
-if (u) {
-tcg_gen_neg_i32(tcg_res, tcg_op);
-} else {
-TCGv_i32 tcg_zero = tcg_const_i32(0);
-tcg_gen_neg_i32(tcg_res, tcg_op);
-tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
-tcg_zero, tcg_op, tcg_res);
-tcg_temp_free_i32(tcg_zero);
-}
-break;
case 0x2f: /* FABS */
gen_helper_vfp_abss(tcg_res, tcg_op);
break;
@@ -12561,23 +12547,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
tcg_temp_free_i32(tcg_zero);
break;
}
-case 0xb: /* ABS, NEG */
-if (u) {
-TCGv_i32 tcg_zero = tcg_const_i32(0);
-if (size) {
-gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
-} else {
-gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
-}
-tcg_temp_free_i32(tcg_zero);
-} else {
-if (size) {
-gen_helper_neon_abs_s16(tcg_res, tcg_op);
-} else {
-gen_helper_neon_abs_s8(tcg_res, tcg_op);
-}
-}
-break;
case 0x4: /* CLS, CLZ */
if (u) {
if (size == 0) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b25781554f..dd053c80d6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8120,6 +8120,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_2RM_VNEG:
tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
break;
+case NEON_2RM_VABS:
+tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size);
+break;
default:
elementwise:
@@ -8225,14 +8228,6
[Qemu-devel] [PATCH v3 23/31] tcg/aarch64: Support vector absolute value
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.inc.c | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 21d06d928c..e43554c3c7 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -132,7 +132,7 @@ typedef enum {
#define TCG_TARGET_HAS_orc_vec 1
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
-#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 7d842cad47..5684b39e1f 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -552,6 +552,7 @@ typedef enum {
I3617_CMGE0 = 0x2e208800,
I3617_CMLE0 = 0x2e20a800,
I3617_NOT = 0x2e205800,
+I3617_ABS = 0x0e20b800,
I3617_NEG = 0x2e20b800,
/* System instructions. */
@@ -2207,6 +2208,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_neg_vec:
tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
break;
+case INDEX_op_abs_vec:
+tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
+break;
case INDEX_op_and_vec:
tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
break;
@@ -2318,6 +2322,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_neg_vec:
+case INDEX_op_abs_vec:
case INDEX_op_not_vec:
case INDEX_op_cmp_vec:
case INDEX_op_shli_vec:
@@ -2561,6 +2566,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
return &w_w_w;
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
+case INDEX_op_abs_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
--
2.17.1
[Qemu-devel] [PATCH] tests/docker: Update the Fedora image to Fedora 30
Fedora 30 got released: https://fedoramagazine.org/announcing-fedora-30/ Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20190408201203.28924-1-marcandre.lur...@redhat.com> qxl: fix -Waddress-of-packed-member Based-on: <20190503112654.4393-1-laur...@vivier.eu> Pull request trivial branch 2019-05-03 --- tests/docker/dockerfiles/fedora.docker | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 69d4a7f5d75..1496b68ba15 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -1,4 +1,4 @@ -FROM fedora:29 +FROM fedora:30 ENV PACKAGES \ bc \ bison \ -- 2.20.1
[Qemu-devel] [PATCH v3 13/31] tcg/aarch64: Implement tcg_out_dupm_vec
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 4a3cfa778a..e8cf4e4044 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -381,6 +381,9 @@ typedef enum {
I3207_BLR = 0xd63f,
I3207_RET = 0xd65f,
+/* AdvSIMD load/store single structure. */
+I3303_LD1R = 0x0d40c000,
+
/* Load literal for loading the address at pc-relative offset */
I3305_LDR = 0x5800,
I3305_LDR_v64 = 0x5c00,
@@ -566,7 +569,14 @@ static inline uint32_t tcg_in32(TCGContext *s)
#define tcg_out_insn(S, FMT, OP, ...) \
glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
-static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19,
TCGReg rt)
+static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rt, TCGReg rn, unsigned size)
+{
+tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
+}
+
+static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
+ int imm19, TCGReg rt)
{
tcg_out32(s, insn | (imm19 & 0x7) << 5 | rt);
}
@@ -825,7 +835,29 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg base, intptr_t offset)
{
-return false;
+if (offset != 0) {
+AArch64Insn add_insn = I3401_ADDI;
+TCGReg temp = TCG_REG_TMP;
+
+if (offset < 0) {
+add_insn = I3401_SUBI;
+offset = -offset;
+}
+if (offset <= 0xfff) {
+tcg_out_insn_3401(s, add_insn, 1, temp, base, offset);
+} else if (offset <= 0xff) {
+tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
+if (offset & 0xfff) {
+tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
+}
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
+tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
+}
+base = temp;
+}
+tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
+return true;
}
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
--
2.17.1
[Qemu-devel] [PATCH v3 21/31] tcg: Add support for vector absolute value
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 5 +++
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op-gvec.h| 2 ++
tcg/tcg-opc.h| 1 +
tcg/tcg.h| 1 +
accel/tcg/tcg-runtime-gvec.c | 48 +++
tcg/tcg-op-gvec.c| 63
tcg/tcg-op-vec.c | 39 ++
tcg/tcg.c| 2 ++
tcg/README | 4 +++
11 files changed, 167 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index ed3ce5fd91..6d73dc2d65 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -225,6 +225,11 @@ DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr,
ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f5640a229b..21d06d928c 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -132,6 +132,7 @@ typedef enum {
#define TCG_TARGET_HAS_orc_vec 1
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 618aa520d2..7445f05885 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -182,6 +182,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 6ee98f3378..52a398c190 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -228,6 +228,8 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs,
uint32_t aofs,
uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4bf71f261f..4a2dd116eb 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -225,6 +225,7 @@ DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
+DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2c7315da25..0e01a70d66 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -176,6 +176,7 @@ typedef uint64_t TCGRegSet;
&& !defined(TCG_TARGET_HAS_v128) \
&& !defined(TCG_TARGET_HAS_v256)
#define TCG_TARGET_MAYBE_vec0
+#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 2152fb6903..0f09e0ef38 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -398,6 +398,54 @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_abs8)(void *d, void *a, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(int8_t)) {
+int8_t aa = *(int8_t *)(a + i);
+*(int8_t *)(d + i) = aa < 0 ? -aa : aa;
+}
+clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_abs16)(void *d, void *a, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(int16_t)) {
+int16_t aa = *(int16_t *)(a + i);
+
[Qemu-devel] [PATCH v3 12/31] tcg/i386: Implement tcg_out_dupm_vec
At the same time, improve tcg_out_dupi_vec wrt broadcast
from the constant pool.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 57 +--
1 file changed, 43 insertions(+), 14 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index f04933bc19..f4bd00e24f 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -358,7 +358,6 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16)
#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16)
-#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2)
#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16)
#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16)
#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3)
@@ -458,6 +457,10 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_UD2 (0x0b | P_EXT)
#define OPC_VPBLENDD(0x02 | P_EXT3A | P_DATA16)
#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16)
+#define OPC_VPINSRB (0x20 | P_EXT3A | P_DATA16)
+#define OPC_VPINSRW (0xc4 | P_EXT | P_DATA16)
+#define OPC_VBROADCASTSS (0x18 | P_EXT38 | P_DATA16)
+#define OPC_VBROADCASTSD (0x19 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
@@ -855,16 +858,17 @@ static bool tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
return true;
}
+static const int avx2_dup_insn[4] = {
+OPC_VPBROADCASTB, OPC_VPBROADCASTW,
+OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
+};
+
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg a)
{
if (have_avx2) {
-static const int dup_insn[4] = {
-OPC_VPBROADCASTB, OPC_VPBROADCASTW,
-OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
-};
int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
-tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a);
+tcg_out_vex_modrm(s, avx2_dup_insn[vece] + vex_l, r, 0, a);
} else {
switch (vece) {
case MO_8:
@@ -894,10 +898,35 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg base, intptr_t offset)
{
-return false;
+if (have_avx2) {
+int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+tcg_out_vex_modrm_offset(s, avx2_dup_insn[vece] + vex_l,
+ r, 0, base, offset);
+} else {
+switch (vece) {
+case MO_64:
+tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSD, r, 0, base, offset);
+break;
+case MO_32:
+tcg_out_vex_modrm_offset(s, OPC_VBROADCASTSS, r, 0, base, offset);
+break;
+case MO_16:
+tcg_out_vex_modrm_offset(s, OPC_VPINSRW, r, r, base, offset);
+tcg_out8(s, 0); /* imm8 */
+tcg_out_dup_vec(s, type, vece, r, r);
+break;
+case MO_8:
+tcg_out_vex_modrm_offset(s, OPC_VPINSRB, r, r, base, offset);
+tcg_out8(s, 0); /* imm8 */
+tcg_out_dup_vec(s, type, vece, r, r);
+break;
+default:
+g_assert_not_reached();
+}
+}
+return true;
}
-
static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
@@ -918,16 +947,16 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
} else if (have_avx2) {
tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
} else {
-tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
+tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD, ret);
}
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
-} else if (have_avx2) {
-tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
-new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
} else {
-tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy, ret);
+if (have_avx2) {
+tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSD + vex_l, ret);
+} else {
+tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+}
new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
-tcg_out_dup_vec(s, type, MO_32, ret, ret);
}
}
--
2.17.1
[Qemu-devel] [PATCH v3 22/31] tcg/i386: Support vector absolute value
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7445f05885..66f16fbe3c 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -182,7 +182,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
-#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 0ba1587da4..aafd01cb49 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -369,6 +369,9 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT)
+#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
+#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
+#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
#define OPC_PACKSSDW(0x6b | P_EXT | P_DATA16)
#define OPC_PACKSSWB(0x63 | P_EXT | P_DATA16)
#define OPC_PACKUSDW(0x2b | P_EXT38 | P_DATA16)
@@ -2741,6 +2744,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const sars_insn[4] = {
OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
};
+static int const abs_insn[4] = {
+/* TODO: AVX512 adds support for MO_64. */
+OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
+};
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
@@ -2829,6 +2836,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = OPC_PUNPCKLDQ;
goto gen_simd;
#endif
+case INDEX_op_abs_vec:
+insn = abs_insn[vece];
+a2 = a1;
+a1 = 0;
+goto gen_simd;
gen_simd:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3206,6 +3218,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_dup2_vec:
#endif
return &x_x_x;
+case INDEX_op_abs_vec:
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
@@ -3283,6 +3296,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_umin_vec:
case INDEX_op_umax_vec:
return vece <= MO_32 ? 1 : -1;
+case INDEX_op_abs_vec:
+return vece <= MO_32;
default:
return 0;
--
2.17.1
[Qemu-devel] [PATCH v3 04/31] tcg: Specify optional vector requirements with a list
Replace the single opcode in .opc with a null-terminated
array in .opt_opc. We still require that all opcodes be
used with the same .vece.
Validate the contents of this list with CONFIG_DEBUG_TCG.
All tcg_gen_*_vec functions will check any list active
during .fniv expansion. Swap the active list in and out
as we expand other opcodes, or take control away from the
front-end function.
Convert all existing vector aware front ends.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.h | 24 +--
tcg/tcg.h | 20 +++
target/arm/translate-sve.c | 9 +-
target/arm/translate.c | 123 +-
target/ppc/translate/vmx-impl.inc.c | 7 +-
tcg/tcg-op-gvec.c | 249
tcg/tcg-op-vec.c| 102
7 files changed, 372 insertions(+), 162 deletions(-)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index c093243c4c..ac744ff7c9 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -91,8 +91,8 @@ typedef struct {
void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_2 *fno;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
@@ -112,8 +112,8 @@ typedef struct {
gen_helper_gvec_2 *fno;
/* Expand out-of-line helper w/descriptor, data as argument. */
gen_helper_gvec_2i *fnoi;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
@@ -131,8 +131,8 @@ typedef struct {
void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_2i *fno;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The data argument to the out-of-line helper. */
uint32_t data;
/* The vector element size, if applicable. */
@@ -152,8 +152,8 @@ typedef struct {
void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_3 *fno;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
@@ -175,8 +175,8 @@ typedef struct {
void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
/* Expand out-of-line helper w/descriptor, data in descriptor. */
gen_helper_gvec_3 *fno;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
@@ -194,8 +194,8 @@ typedef struct {
void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec);
/* Expand out-of-line helper w/descriptor. */
gen_helper_gvec_4 *fno;
-/* The opcode, if any, to which this corresponds. */
-TCGOpcode opc;
+/* The optional opcodes, if any, utilized by .fniv. */
+const TCGOpcode *opt_opc;
/* The data argument to the out-of-line helper. */
int32_t data;
/* The vector element size, if applicable. */
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cfc57110a1..2c7315da25 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -692,6 +692,7 @@ struct TCGContext {
#ifdef CONFIG_DEBUG_TCG
int temps_in_use;
int goto_tb_issue_mask;
+const TCGOpcode *vecop_list;
#endif
/* Code generation. Note that we specifically do not use tcg_insn_unit
@@ -1492,4 +1493,23 @@ void helper_atomic_sto_le_mmu(CPUArchState *env,
target_ulong addr, Int128 val,
void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
TCGMemOpIdx oi, uintptr_t retaddr);
+#ifdef CONFIG_DEBUG_TCG
+void tcg_assert_listed_vecop(TCGOpcode);
+#else
+static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
+#endif
+
+static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
+{
+#ifdef CONFIG_DEBUG_TCG
+const TCGOpcode *o = tcg_ctx->vecop_list;
+tcg_ctx->vecop_list = n;
+return o;
+#else
+return NULL;
+#endif
+}
+
+bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
+
#endif /* TCG_H */
diff --git a/target/arm/translate-sve.c b/target/ar
[Qemu-devel] [PATCH v3 11/31] tcg: Add tcg_out_dupm_vec to the backend interface
Currently stubbed out in all backends that support vectors.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 6 ++
tcg/i386/tcg-target.inc.c| 7 +++
tcg/tcg.c| 19 ++-
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 3cefdd1e43..4a3cfa778a 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -822,6 +822,12 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
return true;
}
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg base, intptr_t offset)
+{
+return false;
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3c8229d413..f04933bc19 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -891,6 +891,13 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
return true;
}
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg base, intptr_t offset)
+{
+return false;
+}
+
+
static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 2b715bf099..b9945794c4 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -111,6 +111,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
#if TCG_TARGET_MAYBE_vec
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src);
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg base, intptr_t offset);
static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg dst, tcg_target_long arg);
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
@@ -122,6 +124,11 @@ static inline bool tcg_out_dup_vec(TCGContext *s, TCGType
type, unsigned vece,
{
g_assert_not_reached();
}
+static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+TCGReg dst, TCGReg base, intptr_t offset)
+{
+g_assert_not_reached();
+}
static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type,
TCGReg dst, tcg_target_long arg)
{
@@ -3422,6 +3429,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp
*op)
TCGRegSet dup_out_regs, dup_in_regs;
TCGTemp *its, *ots;
TCGType itype, vtype;
+intptr_t endian_fixup;
unsigned vece;
bool ok;
@@ -3491,7 +3499,16 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp
*op)
/* fall through */
case TEMP_VAL_MEM:
-/* TODO: dup from memory */
+#ifdef HOST_WORDS_BIGENDIAN
+endian_fixup = itype == TCG_TYPE_I32 ? 4 : 8;
+endian_fixup -= 1 << vece;
+#else
+endian_fixup = 0;
+#endif
+if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg,
+ its->mem_offset + endian_fixup)) {
+goto done;
+}
tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset);
break;
--
2.17.1
[Qemu-devel] [PATCH v3 18/31] tcg: Add gvec expanders for vector shift by scalar
Allow expansion either via shift by scalar or by replicating
the scalar for shift by vector.
Signed-off-by: Richard Henderson
---
v3: Use a private structure for do_gvec_shifts.
---
tcg/tcg-op-gvec.h | 7 ++
tcg/tcg-op.h | 4 +
tcg/tcg-op-gvec.c | 214 ++
tcg/tcg-op-vec.c | 54
4 files changed, 279 insertions(+)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 84a6247b16..6ee98f3378 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -318,6 +318,13 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs,
uint32_t aofs,
void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+
/*
* Perform vector shift by vector element, modulo the element size.
* E.g. D[i] = A[i] << (B[i] % (8 << vece)).
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 833c6330b5..472b73cb38 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec
a, int64_t i);
void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
+void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
+void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
+
void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 061ef329f1..c69c7960b8 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -2555,6 +2555,220 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs,
uint32_t aofs,
}
}
+/*
+ * Specialized generation vector shifts by a non-constant scalar.
+ */
+
+typedef struct {
+void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
+void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
+void (*fniv_s)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32);
+void (*fniv_v)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
+gen_helper_gvec_2 *fno[4];
+TCGOpcode s_list[2];
+TCGOpcode v_list[2];
+} GVecGen2sh;
+
+static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t tysz, TCGType type,
+ TCGv_i32 shift,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_i32))
+{
+TCGv_vec t0 = tcg_temp_new_vec(type);
+uint32_t i;
+
+for (i = 0; i < oprsz; i += tysz) {
+tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+fni(vece, t0, t0, shift);
+tcg_gen_st_vec(t0, cpu_env, dofs + i);
+}
+tcg_temp_free_vec(t0);
+}
+
+static void
+do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g)
+{
+TCGType type;
+uint32_t some;
+
+check_size_align(oprsz, maxsz, dofs | aofs);
+check_overlap_2(dofs, aofs, maxsz);
+
+/* If the backend has a scalar expansion, great. */
+type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64);
+if (type) {
+const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+switch (type) {
+case TCG_TYPE_V256:
+some = QEMU_ALIGN_DOWN(oprsz, 32);
+expand_2sh_vec(vece, dofs, aofs, some, 32,
+ TCG_TYPE_V256, shift, g->fniv_s);
+if (some == oprsz) {
+break;
+}
+dofs += some;
+aofs += some;
+oprsz -= some;
+maxsz -= some;
+/* fallthru */
+case TCG_TYPE_V128:
+expand_2sh_vec(vece, dofs, aofs, oprsz, 16,
+ TCG_TYPE_V128, shift, g->fniv_s);
+break;
+case TCG_TYPE_V64:
+expand_2sh_vec(vece, dofs, aofs, oprsz, 8,
+ TCG_TYPE_V64, shift, g->fniv_s);
+break;
+default:
+g_assert_not_reached();
+}
+tcg_swap_vecop_list(hold_list);
+goto clear_tail;
+}
+
+/* If the backend supports variable vector shifts, also cool. */
+type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64);
+if (type) {
+const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+TCGv_vec v_shift = tcg_temp_new_ve
[Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 35 +++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b240633455..618aa520d2 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -183,7 +183,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_shi_vec 1
-#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index c9448b6d84..0ba1587da4 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -420,6 +420,14 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16)
+#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16)
+#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16)
+#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16)
+#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16)
+#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16)
+#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16)
+#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16)
#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
@@ -2724,6 +2732,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
/* TODO: AVX512 adds support for MO_16, MO_64. */
OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
};
+static int const shls_insn[4] = {
+OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
+};
+static int const shrs_insn[4] = {
+OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ
+};
+static int const sars_insn[4] = {
+OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
+};
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
@@ -2785,6 +2802,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
insn = sarv_insn[vece];
goto gen_simd;
+case INDEX_op_shls_vec:
+insn = shls_insn[vece];
+goto gen_simd;
+case INDEX_op_shrs_vec:
+insn = shrs_insn[vece];
+goto gen_simd;
+case INDEX_op_sars_vec:
+insn = sars_insn[vece];
+goto gen_simd;
case INDEX_op_x86_punpckl_vec:
insn = punpckl_insn[vece];
goto gen_simd;
@@ -3165,6 +3191,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+case INDEX_op_shls_vec:
+case INDEX_op_shrs_vec:
+case INDEX_op_sars_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
@@ -3222,6 +3251,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
}
return 1;
+case INDEX_op_shls_vec:
+case INDEX_op_shrs_vec:
+return vece >= MO_16;
+case INDEX_op_sars_vec:
+return vece >= MO_16 && vece <= MO_32;
+
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
return have_avx2 && vece >= MO_32;
--
2.17.1
[Qemu-devel] [PATCH v3 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov
We have a function that takes an additional condition parameter
over the standard backend interface. It already takes care of
eliding no-op moves.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index abf0c444b4..130b6bef1e 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2267,7 +2267,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType
type, TCGArg val,
static inline void tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
{
-tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
+tcg_out_mov_reg(s, COND_AL, ret, arg);
}
static inline void tcg_out_movi(TCGContext *s, TCGType type,
--
2.17.1
[Qemu-devel] [PATCH v3 07/31] tcg: Return bool success from tcg_out_mov
This patch merely changes the interface, aborting on all failures,
of which there are currently none.
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 5 +++--
tcg/arm/tcg-target.inc.c | 3 ++-
tcg/i386/tcg-target.inc.c| 5 +++--
tcg/mips/tcg-target.inc.c| 3 ++-
tcg/ppc/tcg-target.inc.c | 3 ++-
tcg/riscv/tcg-target.inc.c | 5 +++--
tcg/s390/tcg-target.inc.c| 3 ++-
tcg/sparc/tcg-target.inc.c | 3 ++-
tcg/tcg.c| 14 ++
tcg/tci/tcg-target.inc.c | 3 ++-
10 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index eefa929948..ee89734318 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -938,10 +938,10 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
TCGReg rd,
tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
}
-static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (ret == arg) {
-return;
+return true;
}
switch (type) {
case TCG_TYPE_I32:
@@ -970,6 +970,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg
ret, TCGReg arg)
default:
g_assert_not_reached();
}
+return true;
}
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 130b6bef1e..7316504c9d 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2264,10 +2264,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType
type, TCGArg val,
return false;
}
-static inline void tcg_out_mov(TCGContext *s, TCGType type,
+static inline bool tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
{
tcg_out_mov_reg(s, COND_AL, ret, arg);
+return true;
}
static inline void tcg_out_movi(TCGContext *s, TCGType type,
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index d5ed9f1ffd..1198c76392 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -809,12 +809,12 @@ static inline void tgen_arithr(TCGContext *s, int subop,
int dest, int src)
tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
}
-static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
int rexw = 0;
if (arg == ret) {
-return;
+return true;
}
switch (type) {
case TCG_TYPE_I64:
@@ -852,6 +852,7 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg
ret, TCGReg arg)
default:
g_assert_not_reached();
}
+return true;
}
static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 412cacdcb9..7cafd4a790 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -558,13 +558,14 @@ static inline void tcg_out_dsra(TCGContext *s, TCGReg rd,
TCGReg rt, TCGArg sa)
tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
}
-static inline void tcg_out_mov(TCGContext *s, TCGType type,
+static inline bool tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
}
+return true;
}
static void tcg_out_movi(TCGContext *s, TCGType type,
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 36b4791707..30c095d3d5 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -559,12 +559,13 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
TCGReg base, tcg_target_long offset);
-static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
if (ret != arg) {
tcg_out32(s, OR | SAB(arg, ret, arg));
}
+return true;
}
static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 2932505094..6497a4dab2 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -515,10 +515,10 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
* TCG intrinsics
*/
-static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContex
[Qemu-devel] [PATCH v3 15/31] tcg: Add gvec expanders for variable shift
The gvec expanders perform a modulo on the shift count. If the target
requires alternate behaviour, then it cannot use the generic gvec
expanders anyway, and will have to have its own custom code.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 15 +++
tcg/tcg-op-gvec.h| 11 ++
tcg/tcg-op.h | 4 +
accel/tcg/tcg-runtime-gvec.c | 144 ++
tcg/tcg-op-gvec.c| 195 +++
tcg/tcg-op-vec.c | 15 +++
6 files changed, 384 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index dfe325625c..ed3ce5fd91 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -254,6 +254,21 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void,
ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_shr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_shr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_sar8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index ac744ff7c9..84a6247b16 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -318,6 +318,17 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs,
uint32_t aofs,
void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
+/*
+ * Perform vector shift by vector element, modulo the element size.
+ * E.g. D[i] = A[i] << (B[i] % (8 << vece)).
+ */
+void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
+
void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 9fff9864f6..833c6330b5 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -986,6 +986,10 @@ void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec
a, int64_t i);
void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
+void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
+void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
+void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
+
void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b);
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index e2c6f24262..2152fb6903 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -725,6 +725,150 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+uint8_t sh = *(uint8_t *)(b + i) & 7;
+*(uint8_t *)(d + i) = *(uint8_t *)(a + i) << sh;
+}
+clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl16v)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+intptr_t i;
+
+for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+uint8_t sh = *(uint16_t *)(b + i) & 15;
+*(uint16_t *)(d + i) = *(uint16_t *)(a + i) << sh;
+}
+clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl32v)(void *d, void *a, void *b, uint32_t desc)
+{
+intptr_t oprsz = simd_oprsz(desc);
+in
[Qemu-devel] [PATCH v3 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface
The i386 backend already has these functions, and the aarch64 backend
could easily split out one. Nothing is done with these functions yet,
but this will aid register allocation of INDEX_op_dup_vec in a later patch.
Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 12 ++--
tcg/i386/tcg-target.inc.c| 3 ++-
tcg/tcg.c| 14 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index ee89734318..e443b5df23 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -799,7 +799,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn
insn, TCGType ext,
}
static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg rd, uint64_t v64)
+ TCGReg rd, tcg_target_long v64)
{
int op, cmode, imm8;
@@ -814,6 +814,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
}
}
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+TCGReg rd, TCGReg rs)
+{
+int is_q = type - TCG_TYPE_V64;
+tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);
+return true;
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
@@ -2201,7 +2209,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
case INDEX_op_dup_vec:
-tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0);
+tcg_out_dup_vec(s, type, vece, a0, a1);
break;
case INDEX_op_shli_vec:
tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 1198c76392..0d621670c7 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -855,7 +855,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg
ret, TCGReg arg)
return true;
}
-static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg a)
{
if (have_avx2) {
@@ -888,6 +888,7 @@ static void tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
g_assert_not_reached();
}
}
+return true;
}
static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 68d86361e2..3ef4d3478d 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -109,10 +109,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args);
#if TCG_TARGET_MAYBE_vec
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+TCGReg dst, TCGReg src);
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg dst, tcg_target_long arg);
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
unsigned vece, const TCGArg *args,
const int *const_args);
#else
+static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg src)
+{
+g_assert_not_reached();
+}
+static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+TCGReg dst, tcg_target_long arg)
+{
+g_assert_not_reached();
+}
static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
unsigned vece, const TCGArg *args,
const int *const_args)
--
2.17.1
[Qemu-devel] [PATCH v3 05/31] tcg: Assert fixed_reg is read-only
The only fixed_reg is cpu_env, and it should not be modified
during any TB. Therefore code that tries to special-case moves
into a fixed_reg is dead. Remove it.
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 87 +--
1 file changed, 40 insertions(+), 47 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f7bef51de8..70ca113c26 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3274,11 +3274,8 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp
*ots,
tcg_target_ulong val, TCGLifeData arg_life,
TCGRegSet preferred_regs)
{
-if (ots->fixed_reg) {
-/* For fixed registers, we do not do any constant propagation. */
-tcg_out_movi(s, ots->type, ots->reg, val);
-return;
-}
+/* ENV should not be modified. */
+tcg_debug_assert(!ots->fixed_reg);
/* The movi is not explicitly generated here. */
if (ots->val_type == TEMP_VAL_REG) {
@@ -3314,6 +3311,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
ots = arg_temp(op->args[0]);
ts = arg_temp(op->args[1]);
+/* ENV should not be modified. */
+tcg_debug_assert(!ots->fixed_reg);
+
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
itype = ts->type;
@@ -3338,7 +3338,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
}
tcg_debug_assert(ts->val_type == TEMP_VAL_REG);
-if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
+if (IS_DEAD_ARG(0)) {
/* mov to a non-saved dead register makes no sense (even with
liveness analysis disabled). */
tcg_debug_assert(NEED_SYNC_ARG(0));
@@ -3351,7 +3351,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
}
temp_dead(s, ots);
} else {
-if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
+if (IS_DEAD_ARG(1) && !ts->fixed_reg) {
/* the mov can be suppressed */
if (ots->val_type == TEMP_VAL_REG) {
s->reg_to_temp[ots->reg] = NULL;
@@ -3504,6 +3504,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = arg_temp(arg);
+
+/* ENV should not be modified. */
+tcg_debug_assert(!ts->fixed_reg);
+
if ((arg_ct->ct & TCG_CT_ALIAS)
&& !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
@@ -3512,29 +3516,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
} else {
-/* if fixed register, we try to use it */
-reg = ts->reg;
-if (ts->fixed_reg &&
-tcg_regset_test_reg(arg_ct->u.regs, reg)) {
-goto oarg_end;
-}
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
op->output_pref[k], ts->indirect_base);
}
tcg_regset_set_reg(o_allocated_regs, reg);
-/* if a fixed register is used, then a move will be done
afterwards */
-if (!ts->fixed_reg) {
-if (ts->val_type == TEMP_VAL_REG) {
-s->reg_to_temp[ts->reg] = NULL;
-}
-ts->val_type = TEMP_VAL_REG;
-ts->reg = reg;
-/* temp value is modified, so the value kept in memory is
- potentially not the same */
-ts->mem_coherent = 0;
-s->reg_to_temp[reg] = ts;
+if (ts->val_type == TEMP_VAL_REG) {
+s->reg_to_temp[ts->reg] = NULL;
}
-oarg_end:
+ts->val_type = TEMP_VAL_REG;
+ts->reg = reg;
+/*
+ * Temp value is modified, so the value kept in memory is
+ * potentially not the same.
+ */
+ts->mem_coherent = 0;
+s->reg_to_temp[reg] = ts;
new_args[i] = reg;
}
}
@@ -3550,10 +3546,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
-reg = new_args[i];
-if (ts->fixed_reg && ts->reg != reg) {
-tcg_out_mov(s, ts->type, ts->reg, reg);
-}
+
+/* ENV should not be modified. */
+tcg_debug_assert(!ts->fixed_reg);
+
if (NEED_SYNC_ARG(i)) {
temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i));
} else if (IS_DEAD_ARG(i)) {
@@ -3674,26 +3670,23 @@ static void
[Qemu-devel] [PATCH v3 14/31] tcg: Add INDEX_op_dupm_vec
Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first. This is especially important
if integer/vector register moves do not exist.
Note that officially tcg_out_dupm_vec is allowed to fail.
If it did, we could fix this up relatively easily:
VECE == 32/64:
Load the value into a vector register, then dup.
Both of these must work.
VECE == 8/16:
If the value happens to be at an offset such that an aligned
load would place the desired value in the least significant
end of the register, go ahead and load w/garbage in high bits.
Load the value w/INDEX_op_ld{8,16}_i32.
Attempt a move directly to vector reg, which may fail.
Store the value into the backing store for OTS.
Load the value into the vector reg w/TCG_TYPE_I32, which must work.
Duplicate from the vector reg into itself, which must work.
All of which is well and good, except that all supported
hosts can support dupm for all vece, so all of the failure
paths would be dead code and untestable.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h| 1 +
tcg/aarch64/tcg-target.inc.c | 4 ++
tcg/i386/tcg-target.inc.c| 4 ++
tcg/tcg-op-gvec.c| 89 +++-
tcg/tcg-op-vec.c | 11 +
tcg/tcg.c| 1 +
7 files changed, 70 insertions(+), 41 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 1f1824c30a..9fff9864f6 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -954,6 +954,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv,
TCGv_i64, TCGArg, TCGMemOp);
void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
+void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long);
void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 1bad6e4208..4bf71f261f 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -219,6 +219,7 @@ DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS
== 32))
DEF(ld_vec, 1, 1, 1, IMPLVEC)
DEF(st_vec, 0, 2, 1, IMPLVEC)
+DEF(dupm_vec, 1, 1, 1, IMPLVEC)
DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index e8cf4e4044..15ab35adf7 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2190,6 +2190,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
break;
+case INDEX_op_dupm_vec:
+tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+break;
case INDEX_op_add_vec:
tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
break;
@@ -2522,6 +2525,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
return &w_w;
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
+case INDEX_op_dupm_vec:
return &w_r;
case INDEX_op_dup_vec:
return &w_wr;
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index f4bd00e24f..5b33bbd99b 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2829,6 +2829,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
break;
+case INDEX_op_dupm_vec:
+tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+break;
case INDEX_op_x86_shufps_vec:
insn = OPC_SHUFPS;
@@ -3115,6 +3118,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
+case INDEX_op_dupm_vec:
return &x_r;
case INDEX_op_add_vec:
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 3fcb2352d9..35ebc5a201 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -395,6 +395,41 @@ static TCGType choose_vector_type(const TCGOpcode *list,
unsigned vece,
return 0;
}
+static void do_dup_store(TCGType type, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_vec t_vec)
+{
+uint32_t i = 0;
+
+switch (type) {
+case TCG_TYPE_V256:
+/*
+ * Recall that ARM SVE allows vector sizes that are not a
+ * power of 2, but always a multiple of 16. The intent is
+ * that e.g. size == 80 would be expanded with 2x32 + 1x16.
+ */
+for (; i + 32 <= oprsz; i += 32) {
+tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
+}
+/* fallthru */
+case TCG_TYPE_V128:
+for (; i + 16 <= oprsz; i += 16) {
+tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
+}
+break;
+case TCG_TYPE_V64:
+for (;
[Qemu-devel] [PATCH v3 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported
Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec,
so that we check the type and vece for the actual operation.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 5150c38a25..24faa06260 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -734,9 +734,13 @@ void tcg_optimize(TCGContext *s)
} else if (opc == INDEX_op_sub_i64) {
neg_op = INDEX_op_neg_i64;
have_neg = TCG_TARGET_HAS_neg_i64;
-} else {
+} else if (TCG_TARGET_HAS_neg_vec) {
+TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
+unsigned vece = TCGOP_VECE(op);
neg_op = INDEX_op_neg_vec;
-have_neg = TCG_TARGET_HAS_neg_vec;
+have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
+} else {
+break;
}
if (!have_neg) {
break;
--
2.17.1
[Qemu-devel] [PATCH v3 08/31] tcg: Support cross-class moves without instruction support
PowerPC Altivec does not support direct moves between vector registers
and general registers. So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.
Acked-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8ed7cb8654..68d86361e2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3368,7 +3368,20 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
ots->indirect_base);
}
if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) {
-abort();
+/*
+ * Cross register class move not supported.
+ * Store the source register into the destination slot
+ * and leave the destination temp as TEMP_VAL_MEM.
+ */
+assert(!ots->fixed_reg);
+if (!ts->mem_allocated) {
+temp_allocate_frame(s, ots);
+}
+tcg_out_st(s, ts->type, ts->reg,
+ ots->mem_base->reg, ots->mem_offset);
+ots->mem_coherent = 1;
+temp_free_or_dead(s, ots, -1);
+return;
}
}
ots->val_type = TEMP_VAL_REG;
@@ -3470,7 +3483,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
-abort();
+/*
+ * Cross register class move not supported. Sync the
+ * temp back to its slot and load from there.
+ */
+temp_sync(s, ts, i_allocated_regs, 0, 0);
+tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
new_args[i] = reg;
@@ -3631,7 +3650,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
if (ts->reg != reg) {
tcg_reg_free(s, reg, allocated_regs);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
-abort();
+/*
+ * Cross register class move not supported. Sync the
+ * temp back to its slot and load from there.
+ */
+temp_sync(s, ts, allocated_regs, 0, 0);
+tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
} else {
--
2.17.1
[Qemu-devel] [PATCH v3 10/31] tcg: Manually expand INDEX_op_dup_vec
This case is similar to INDEX_op_mov_* in that we need to do
different things depending on the current location of the source.
Signed-off-by: Richard Henderson
---
v3: Added some commentary to the tcg_reg_alloc_* functions.
---
tcg/aarch64/tcg-target.inc.c | 9 ++-
tcg/i386/tcg-target.inc.c| 8 +--
tcg/tcg.c| 111 +++
3 files changed, 118 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index e443b5df23..3cefdd1e43 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2108,10 +2108,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
-case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
-case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
g_assert_not_reached();
@@ -2208,9 +2206,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
-case INDEX_op_dup_vec:
-tcg_out_dup_vec(s, type, vece, a0, a1);
-break;
case INDEX_op_shli_vec:
tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
break;
@@ -2254,6 +2249,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
}
break;
+
+case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 0d621670c7..3c8229d413 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2603,10 +2603,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
-case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
-case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2795,9 +2793,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
break;
-case INDEX_op_dup_vec:
-tcg_out_dup_vec(s, type, vece, a0, a1);
-break;
case INDEX_op_x86_shufps_vec:
insn = OPC_SHUFPS;
@@ -2839,6 +2834,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out8(s, a2);
break;
+case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3ef4d3478d..2b715bf099 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3284,6 +3284,9 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet
allocated_regs)
save_globals(s, allocated_regs);
}
+/*
+ * Specialized code generation for INDEX_op_movi_*.
+ */
static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
tcg_target_ulong val, TCGLifeData arg_life,
TCGRegSet preferred_regs)
@@ -3313,6 +3316,9 @@ static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp
*op)
tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]);
}
+/*
+ * Specialized code generation for INDEX_op_mov_*.
+ */
static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
{
const TCGLifeData arg_life = op->life;
@@ -3407,6 +3413,108 @@ static void tcg_reg_alloc_mov(TCGContext *s, const
TCGOp *op)
}
}
+/*
+ * Specialized code generation for INDEX_op_dup_vec.
+ */
+static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
+{
+const TCGLifeData arg_life = op->life;
+TCGRegSet dup_out_regs, dup_in_regs;
+TCGTemp *its, *ots;
+TCGType itype, vtype;
+unsigned vece;
+bool ok;
+
+ots = arg_temp(op->args[0]);
+its = arg_temp(op->args[1]);
+
+/* ENV should not be modified. */
+tcg_debug_assert(!ots->fixed_reg);
+
+itype = its->type;
+vece = TCGOP_VECE(op);
+vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
+
+if (its->val_type == TEMP_VAL_CONST) {
+/* Propagate constant via movi -> dupi. */
+tcg_target_ulong val = its->val;
+if (IS_DEAD_ARG(1)) {
+temp_dead(s, its);
+}
+tcg_reg_alloc_do_movi(s, ots, val, arg_life, op->output_pref[0]);
+return;
+}
+
+dup_out_regs = tcg_op_de
[Qemu-devel] [PATCH v3 01/31] tcg: Implement tcg_gen_gvec_3i()
From: David Hildenbrand
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.
Reviewed-by: Alex Bennée
Signed-off-by: David Hildenbrand
Message-Id: <20190416185301.25344-2-da...@redhat.com>
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.h | 24
tcg/tcg-op-gvec.c | 139 ++
2 files changed, 163 insertions(+)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 850da32ded..c093243c4c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -164,6 +164,27 @@ typedef struct {
bool load_dest;
} GVecGen3;
+typedef struct {
+/*
+ * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
+ * non-NULL.
+ */
+void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
+void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
+/* Expand inline with a host vector type. */
+void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
+/* Expand out-of-line helper w/descriptor, data in descriptor. */
+gen_helper_gvec_3 *fno;
+/* The opcode, if any, to which this corresponds. */
+TCGOpcode opc;
+/* The vector element size, if applicable. */
+uint8_t vece;
+/* Prefer i64 to v64. */
+bool prefer_i64;
+/* Load dest as a 3rd source operand. */
+bool load_dest;
+} GVecGen3i;
+
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
@@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t
oprsz,
uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen3i *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 0996ef0812..f831adb4e7 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -663,6 +663,29 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i32(t0);
}
+static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int32_t c, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
+{
+TCGv_i32 t0 = tcg_temp_new_i32();
+TCGv_i32 t1 = tcg_temp_new_i32();
+TCGv_i32 t2 = tcg_temp_new_i32();
+uint32_t i;
+
+for (i = 0; i < oprsz; i += 4) {
+tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+if (load_dest) {
+tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+}
+fni(t2, t0, t1, c);
+tcg_gen_st_i32(t2, cpu_env, dofs + i);
+}
+tcg_temp_free_i32(t0);
+tcg_temp_free_i32(t1);
+tcg_temp_free_i32(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -770,6 +793,29 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i64(t0);
}
+static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int64_t c, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
+{
+TCGv_i64 t0 = tcg_temp_new_i64();
+TCGv_i64 t1 = tcg_temp_new_i64();
+TCGv_i64 t2 = tcg_temp_new_i64();
+uint32_t i;
+
+for (i = 0; i < oprsz; i += 8) {
+tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+if (load_dest) {
+tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+}
+fni(t2, t0, t1, c);
+tcg_gen_st_i64(t2, cpu_env, dofs + i);
+}
+tcg_temp_free_i64(t0);
+tcg_temp_free_i64(t1);
+tcg_temp_free_i64(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -883,6 +929,35 @@ static void expand_3_vec(unsigned vece, uint32_t dofs,
uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/*
+ * Expand OPSZ bytes worth of three-vector operands and an immediate operand
+ * using host vectors.
+ */
+static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t tysz,
+ TCGType type, int64_t c, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCG
[Qemu-devel] [PATCH v3 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
Reviewed-by: Alex Bennée
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 49
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 27f65600c3..cfb18682b1 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -226,16 +226,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o,
TCGType low_type)
vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o);
}
-void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
-{
-vec_gen_op3(INDEX_op_add_vec, vece, r, a, b);
-}
-
-void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
-{
-vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b);
-}
-
void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(INDEX_op_and_vec, 0, r, a, b);
@@ -296,11 +286,30 @@ void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec
a, TCGv_vec b)
tcg_gen_not_vec(0, r, r);
}
+static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
+{
+TCGTemp *rt = tcgv_vec_temp(r);
+TCGTemp *at = tcgv_vec_temp(a);
+TCGArg ri = temp_arg(rt);
+TCGArg ai = temp_arg(at);
+TCGType type = rt->base_type;
+int can;
+
+tcg_debug_assert(at->base_type >= type);
+can = tcg_can_emit_vec_op(opc, type, vece);
+if (can > 0) {
+vec_gen_2(opc, type, vece, ri, ai);
+} else if (can < 0) {
+tcg_expand_vec_op(opc, type, vece, ri, ai);
+} else {
+return false;
+}
+return true;
+}
+
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
{
-if (TCG_TARGET_HAS_not_vec) {
-vec_gen_op2(INDEX_op_not_vec, 0, r, a);
-} else {
+if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
TCGv_vec t = tcg_const_ones_vec_matching(r);
tcg_gen_xor_vec(0, r, a, t);
tcg_temp_free_vec(t);
@@ -309,9 +318,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
{
-if (TCG_TARGET_HAS_neg_vec) {
-vec_gen_op2(INDEX_op_neg_vec, vece, r, a);
-} else {
+if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {
TCGv_vec t = tcg_const_zeros_vec_matching(r);
tcg_gen_sub_vec(vece, r, t, a);
tcg_temp_free_vec(t);
@@ -409,6 +416,16 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
}
}
+void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+do_op3(vece, r, a, b, INDEX_op_add_vec);
+}
+
+void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+do_op3(vece, r, a, b, INDEX_op_sub_vec);
+}
+
void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
do_op3(vece, r, a, b, INDEX_op_mul_vec);
--
2.17.1
[Qemu-devel] [PATCH v3 00/31] tcg vector improvements
Changes since v2 (stsquad review):
* Split out a tcg/arm/ change to tcg_out_mov.
* Add some additional commentary for tcg_reg_alloc_foo.
Patches missing ack/review:
0006-tcg-arm-Use-tcg_out_mov_reg-in-tcg_out_mov.patch (new)
0010-tcg-Manually-expand-INDEX_op_dup_vec.patch
0011-tcg-Add-tcg_out_dupm_vec-to-the-backend-interface.patch
0012-tcg-i386-Implement-tcg_out_dupm_vec.patch
0013-tcg-aarch64-Implement-tcg_out_dupm_vec.patch
0016-tcg-i386-Support-vector-variable-shift-opcodes.patch
0018-tcg-Add-gvec-expanders-for-vector-shift-by-scalar.patch
0019-tcg-i386-Support-vector-scalar-shift-opcodes.patch
0022-tcg-i386-Support-vector-absolute-value.patch
0025-target-cris-Use-tcg_gen_abs_tl.patch
0027-target-ppc-Use-tcg_gen_abs_tl.patch
0031-tcg-aarch64-Do-not-advertise-minmax-for-MO_64.patch (new)
r~
David Hildenbrand (1):
tcg: Implement tcg_gen_gvec_3i()
Philippe Mathieu-Daudé (2):
target/ppc: Use tcg_gen_abs_i32
target/tricore: Use tcg_gen_abs_tl
Richard Henderson (28):
tcg: Do not recreate INDEX_op_neg_vec unless supported
tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
tcg: Specify optional vector requirements with a list
tcg: Assert fixed_reg is read-only
tcg/arm: Use tcg_out_mov_reg in tcg_out_mov
tcg: Return bool success from tcg_out_mov
tcg: Support cross-class moves without instruction support
tcg: Promote tcg_out_{dup,dupi}_vec to backend interface
tcg: Manually expand INDEX_op_dup_vec
tcg: Add tcg_out_dupm_vec to the backend interface
tcg/i386: Implement tcg_out_dupm_vec
tcg/aarch64: Implement tcg_out_dupm_vec
tcg: Add INDEX_op_dupm_vec
tcg: Add gvec expanders for variable shift
tcg/i386: Support vector variable shift opcodes
tcg/aarch64: Support vector variable shift opcodes
tcg: Add gvec expanders for vector shift by scalar
tcg/i386: Support vector scalar shift opcodes
tcg: Add support for integer absolute value
tcg: Add support for vector absolute value
tcg/i386: Support vector absolute value
tcg/aarch64: Support vector absolute value
target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
target/cris: Use tcg_gen_abs_tl
target/ppc: Use tcg_gen_abs_tl
target/s390x: Use tcg_gen_abs_i64
target/xtensa: Use tcg_gen_abs_i32
tcg/aarch64: Do not advertise minmax for MO_64
accel/tcg/tcg-runtime.h | 20 +
target/arm/helper.h | 2 -
tcg/aarch64/tcg-target.h| 3 +-
tcg/aarch64/tcg-target.opc.h| 2 +
tcg/i386/tcg-target.h | 5 +-
tcg/tcg-op-gvec.h | 64 +-
tcg/tcg-op.h| 14 +
tcg/tcg-opc.h | 2 +
tcg/tcg.h | 21 +
accel/tcg/tcg-runtime-gvec.c| 192 ++
target/arm/neon_helper.c| 5 -
target/arm/translate-a64.c | 41 +-
target/arm/translate-sve.c | 9 +-
target/arm/translate.c | 144 +++--
target/cris/translate.c | 9 +-
target/ppc/translate.c | 68 +-
target/ppc/translate/spe-impl.inc.c | 14 +-
target/ppc/translate/vmx-impl.inc.c | 7 +-
target/s390x/translate.c| 8 +-
target/tricore/translate.c | 27 +-
target/xtensa/translate.c | 9 +-
tcg/aarch64/tcg-target.inc.c| 120 +++-
tcg/arm/tcg-target.inc.c| 5 +-
tcg/i386/tcg-target.inc.c | 163 -
tcg/mips/tcg-target.inc.c | 3 +-
tcg/optimize.c | 8 +-
tcg/ppc/tcg-target.inc.c| 3 +-
tcg/riscv/tcg-target.inc.c | 5 +-
tcg/s390/tcg-target.inc.c | 3 +-
tcg/sparc/tcg-target.inc.c | 3 +-
tcg/tcg-op-gvec.c | 945 +++-
tcg/tcg-op-vec.c| 270 +++-
tcg/tcg-op.c| 20 +
tcg/tcg.c | 271 ++--
tcg/tci/tcg-target.inc.c| 3 +-
tcg/README | 4 +
36 files changed, 2019 insertions(+), 473 deletions(-)
--
2.17.1
[Qemu-devel] [PATCH] migration: don't set MIGRATION dirty range for ignored block
The ignored blocks are not migrated and those ranges are not used.
Signed-off-by: Wei Yang
---
exec.c | 4 +++-
include/exec/ram_addr.h | 2 ++
migration/ram.c | 2 +-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 86a38d3b3b..97da155c12 100644
--- a/exec.c
+++ b/exec.c
@@ -2192,6 +2192,8 @@ static void ram_block_add(RAMBlock *new_block, Error
**errp, bool shared)
RAMBlock *last_block = NULL;
ram_addr_t old_ram_size, new_ram_size;
Error *err = NULL;
+uint8_t dirty_memory_clients = ramblock_is_ignored(new_block) ?
+ DIRTY_CLIENTS_NOMIG : DIRTY_CLIENTS_ALL;
old_ram_size = last_ram_page();
@@ -2252,7 +2254,7 @@ static void ram_block_add(RAMBlock *new_block, Error
**errp, bool shared)
cpu_physical_memory_set_dirty_range(new_block->offset,
new_block->used_length,
-DIRTY_CLIENTS_ALL);
+dirty_memory_clients);
if (new_block->host) {
qemu_ram_setup_dump(new_block->host, new_block->max_length);
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index a7c81bdb32..4765435fb8 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -72,6 +72,7 @@ static inline unsigned long int
ramblock_recv_bitmap_offset(void *host_addr,
}
bool ramblock_is_pmem(RAMBlock *rb);
+bool ramblock_is_ignored(RAMBlock *rb);
long qemu_getrampagesize(void);
@@ -117,6 +118,7 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize,
Error **errp);
#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1)
#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE))
+#define DIRTY_CLIENTS_NOMIG (DIRTY_CLIENTS_ALL & ~(1 <<
DIRTY_MEMORY_MIGRATION))
void tb_invalidate_phys_range(ram_addr_t start, ram_addr_t end);
diff --git a/migration/ram.c b/migration/ram.c
index 1def8122e9..44525e3816 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -159,7 +159,7 @@ out:
return ret;
}
-static bool ramblock_is_ignored(RAMBlock *block)
+bool ramblock_is_ignored(RAMBlock *block)
{
return !qemu_ram_is_migratable(block) ||
(migrate_ignore_shared() && qemu_ram_is_shared(block));
--
2.19.1
Re: [Qemu-devel] [PATCH v1 5/5] hw/arm: Add the Netduino Plus 2
On Fri, May 3, 2019 at 9:26 PM Alistair wrote: > > On Thu, May 2, 2019, at 3:06 AM, Peter Maydell wrote: > > On Tue, 30 Apr 2019 at 21:29, Alistair Francis wrote: > > > > > > On Tue, Apr 30, 2019 at 9:02 AM Peter Maydell > > > wrote: > > > > Can you explain the purpose of the reset code? None of the other > > > > v7m boards seem to need to do a manual qemu_register_reset(). > > > > > > The reset code allows the machine to work with the -kernel option. > > > Without the reset override using -kernel results in the guest starting > > > at the wrong address. We can use the -device loader option without the > > > reset code though. > > > > That sounds in line with how -kernel works on the other armv7m > > boards -- the expectation is that your image file includes a > > full vector table and the CPU will read the PC and SP from it > > when it resets. If you want "honour the entry point" you can > > use -device loader, as you say. > > > > Ignoring the entry point for -kernel ELF files is certainly > > a bit confusing, but I think if we want to change this we should > > do it globally, rather than having one board which behaves > > differently to the rest. Changing it does have some awkwardness: > > Hmm... That is a good point. It is confusing having something just for one > board. I'll drop this part and we can re-evaluate later. > > > * possibility of breaking previously working images > > I have no way to test the other boards, so this might be difficult to change. > > > * we can get the initial PC from the ELF entrypoint, but if > > we do this what do we do about the initial SP value ? > > Not sure about this one either. I'm guessing it changes between the different > M cores. Ah, it seems like -device loader doesn't work, it looks like not setting the thumb register causes this core dump: qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1) R00=2000 R01=0574 R02=200015d0 R03=200015d0 R04= R05= R06= R07= R08= R09= R10= R11= R12= R13=ffe0 R14=fff9 R15=0800cba4 XPSR=6103 -ZC- T handler s00= s01= d00= s02= s03= d01= s04= s05= d02= s06= s07= d03= s08= s09= d04= s10= s11= d05= s12= s13= d06= s14= s15= d07= s16= s17= d08= s18= s19= d09= s20= s21= d10= s22= s23= d11= s24= s25= d12= s26= s27= d13= s28= s29= d14= s30= s31= d15= s32= s33= d16= s34= s35= d17= s36= s37= d18= s38= s39= d19= s40= s41= d20= s42= s43= d21= s44= s45= d22= s46= s47= d23= s48= s49= d24= s50= s51= d25= s52= s53= d26= s54= s55= d27= s56= s57= d28= s58= s59= d29= s60= s61= d30= s62= s63= d31= FPSCR: Aborted (core dumped) Alistair > > Alistair > > > > > thanks > > -- PMM > > > > >
Re: [Qemu-devel] [PATCH v2] target/arm: Stop using variable length array in dc_zva
On 5/3/19 2:04 PM, Peter Maydell wrote:
> Currently the dc_zva helper function uses a variable length
> array. In fact we know (as the comment above remarks) that
> the length of this array is bounded because the architecture
> limits the block size and QEMU limits the target page size.
> Use a fixed array size and assert that we don't run off it.
>
> Signed-off-by: Peter Maydell
> ---
> Changes v1->v2:
> * use ARRAY_SIZE() instead of sizeof()
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
> * add a comment to make it a bit clearer that the
>expected size of hostaddr[] is only 2 entries
> ---
> target/arm/helper.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 81a92ab4911..10444d12b18 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1,4 +1,5 @@
> #include "qemu/osdep.h"
> +#include "qemu/units.h"
> #include "target/arm/idau.h"
> #include "trace.h"
> #include "cpu.h"
> @@ -13099,14 +13100,17 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t
> vaddr_in)
> * We know that in fact for any v8 CPU the page size is at least 4K
> * and the block size must be 2K or less, but TARGET_PAGE_SIZE is
> only
> * 1K as an artefact of legacy v5 subpage support being present in
> the
> - * same QEMU executable.
> + * same QEMU executable. So in practice the hostaddr[] array has
> + * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
> */
> int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
> -void *hostaddr[maxidx];
> +void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
> int try, i;
> unsigned mmu_idx = cpu_mmu_index(env, false);
> TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
>
> +assert(maxidx <= ARRAY_SIZE(hostaddr));
> +
> for (try = 0; try < 2; try++) {
>
> for (i = 0; i < maxidx; i++) {
>
Re: [Qemu-devel] [PATCH v1 5/5] hw/arm: Add the Netduino Plus 2
On Thu, May 2, 2019, at 3:06 AM, Peter Maydell wrote: > On Tue, 30 Apr 2019 at 21:29, Alistair Francis wrote: > > > > On Tue, Apr 30, 2019 at 9:02 AM Peter Maydell > > wrote: > > > Can you explain the purpose of the reset code? None of the other > > > v7m boards seem to need to do a manual qemu_register_reset(). > > > > The reset code allows the machine to work with the -kernel option. > > Without the reset override using -kernel results in the guest starting > > at the wrong address. We can use the -device loader option without the > > reset code though. > > That sounds in line with how -kernel works on the other armv7m > boards -- the expectation is that your image file includes a > full vector table and the CPU will read the PC and SP from it > when it resets. If you want "honour the entry point" you can > use -device loader, as you say. > > Ignoring the entry point for -kernel ELF files is certainly > a bit confusing, but I think if we want to change this we should > do it globally, rather than having one board which behaves > differently to the rest. Changing it does have some awkwardness: Hmm... That is a good point. It is confusing having something just for one board. I'll drop this part and we can re-evaluate later. > * possibility of breaking previously working images I have no way to test the other boards, so this might be difficult to change. > * we can get the initial PC from the ELF entrypoint, but if > we do this what do we do about the initial SP value ? Not sure about this one either. I'm guessing it changes between the different M cores. Alistair > > thanks > -- PMM > >
Re: [Qemu-devel] [PATCH 2/2] hw/arm/boot: Honour image size field in AArch64 Image format kernels
On 5/3/19 10:13 AM, Peter Maydell wrote: > Since Linux v3.17, the kernel's Image header includes a field image_size, > which gives the total size of the kernel including unpopulated data > sections such as the BSS). If this is present, then return it from > load_aarch64_image() as the true size of the kernel rather than > just using the size of the Image file itself. This allows the code > which calculates where to put the initrd to avoid putting it in > the kernel's BSS area. > > This means that we should be able to reliably load kernel images > which are larger than 128MB without accidentally putting the > initrd or dtb in locations that clash with the kernel itself. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1823998 > Signed-off-by: Peter Maydell > --- > hw/arm/boot.c | 17 +++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [Qemu-devel] [PATCH for-4.1] block: Use bdrv_unref_child() for all children in bdrv_close()
On 31.03.19 13:17, Alberto Garcia wrote: > bdrv_unref_child() does the following things: > > - Updates the child->bs->inherits_from pointer. > - Calls bdrv_detach_child() to remove the BdrvChild from bs->children. > - Calls bdrv_unref() to unref the child BlockDriverState. > > When bdrv_unref_child() was introduced in commit 33a604075c it was not > used in bdrv_close() because the drivers that had additional children > (like quorum or blkverify) had already called bdrv_unref() on their > children during their own close functions. > > This was changed later (in 0bd6e91a7e for quorum, in 3e586be0b2 for > blkverify) so there's no reason not to use bdrv_unref_child() in > bdrv_close() anymore. > > After this there's also no need to remove bs->backing and bs->file > separately from the rest of the children, so bdrv_close() can be > simplified. > > Signed-off-by: Alberto Garcia > --- > block.c | 16 +++- > 1 file changed, 3 insertions(+), 13 deletions(-) Hm, I’m afraid this breaks make check: $ make -j 4 && make tests/test-bdrv-drain && gtester tests/test-bdrv-drain TEST: tests/test-bdrv-drain... (pid=22321) test-bdrv-drain: block.c:5397: bdrv_unref: Assertion `bs->refcnt > 0' failed. (gdb) bt #0 0x7f15c7ffc57f in raise () from /lib64/libc.so.6 #1 0x7f15c7fe6895 in abort () from /lib64/libc.so.6 #2 0x7f15c7fe6769 in __assert_fail_base.cold.0 () from /lib64/libc.so.6 #3 0x7f15c7ff4a26 in __assert_fail () from /lib64/libc.so.6 #4 0x5562a11b0a00 in bdrv_unref (bs=0x5562a3370c30) at block.c:5397 #5 bdrv_unref (bs=0x5562a3370c30) at block.c:5392 #6 0x5562a11a7f8f in test_detach_indirect (by_parent_cb=) at tests/test-bdrv-drain.c:1442 #7 0x7f15c8766fca in ?? () from /lib64/libglib-2.0.so.0 #8 0x7f15c8766e84 in ?? () from /lib64/libglib-2.0.so.0 #9 0x7f15c8766e84 in ?? () from /lib64/libglib-2.0.so.0 #10 0x7f15c8767282 in g_test_run_suite () from /lib64/libglib-2.0.so.0 #11 0x7f15c87672a5 in g_test_run () from /lib64/libglib-2.0.so.0 #12 0x5562a11a5b77 in main (argc=, argv=) at tests/test-bdrv-drain.c:1617 So I’ll dequeue this patch for now. Max signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH] chardev/char-i2c: Implement Linux I2C character device
On Fri, May 03, 2019 at 03:24:06PM -0500, Eric Blake wrote:
> On 5/3/19 2:31 PM, Ernest Esene wrote:
> > Add support for Linux I2C character device for I2C device passthrough
> > For example:
> > -chardev linux-i2c,address=0x46,path=/dev/i2c-N,id=i2c-chardev
> >
> > Signed-off-by: Ernest Esene
> > ---
>
> Just an interface review:
>
> > +++ b/qapi/char.json
> > @@ -240,6 +240,21 @@
> >'data': { 'device': 'str' },
> >'base': 'ChardevCommon' }
> >
> Missing a 'Since: 4.1' line.
4.1? Oh! I couldn't guess this number, I had to deliberately omit it.
>
> > +{ 'struct': 'ChardevI2c',
> > + 'data': { 'device': 'str',
> > +'address': 'int16'},
> > + 'base': 'ChardevCommon'}
>
> 'if': 'defined(CONFIG_LINUX)'
>
> as part of the usage of this struct, so that introspection will only see
> the struct where it can be used.
>
> > +
> > ##
> > # @ChardevSocket:
> > #
> > @@ -398,6 +413,7 @@
> >'data': { 'file': 'ChardevFile',
> > 'serial': 'ChardevHostdev',
> > 'parallel': 'ChardevHostdev',
> > +'i2c': 'ChardevI2c',
> > 'pipe': 'ChardevHostdev',
> > 'socket': 'ChardevSocket',
> > 'udp': 'ChardevUdp',
> >
>
> --
> Eric Blake, Principal Software Engineer
> Red Hat, Inc. +1-919-301-3226
> Virtualization: qemu.org | libvirt.org
>
Thanks so much for the useful review. I have applied the changes and
will soon send v2 of the patch.
I hope it is OK to update the "MAINTAINERS" file this
Character Devices (Linux I2C)
M: Ernest Esene
S: Maintained
F: chardev/char-i2c.c
-Ernest Esene
signature.asc
Description: PGP signature
Re: [Qemu-devel] [PULL 19/19] configure: automatically pick python3 is available
On Fri, May 03, 2019 at 06:00:11PM -0300, Eduardo Habkost wrote:
> On Fri, May 03, 2019 at 06:41:43PM +0200, Thomas Huth wrote:
> > On 03/05/2019 02.41, Eduardo Habkost wrote:
> > > From: Daniel P. Berrangé
> > >
> > > Unless overridden via an env var or configure arg, QEMU will only look
> > > for the 'python' binary in $PATH. This is unhelpful on distros which
> > > are only shipping Python 3.x (eg Fedora) in their default install as,
> > > if they comply with PEP 394, the bare 'python' binary won't exist.
> > >
> > > This changes configure so that by default it will search for all three
> > > common python binaries, preferring to find Python 3.x versions.
> > >
> > > Signed-off-by: Daniel P. Berrangé
> > > Message-Id: <20190327170701.23798-1-berra...@redhat.com>
> > > Signed-off-by: Eduardo Habkost
> > > ---
> > > configure | 18 +++---
> > > 1 file changed, 15 insertions(+), 3 deletions(-)
> >
> > I haven't bisected it, but I think this patch here broke the gitlab-ci
> > tests:
> >
> > https://gitlab.com/huth/qemu/-/jobs/206806257
> >
> > Seems like the test is now failing when you don't have an UTF-8 locale:
> >
> > LANG=C make check-qapi-schema
>
> I couldn't reproduce it this way, probably because I'm running Python 3.7
> which
> implements PEP 538 ("Coercing the legacy C locale to a UTF-8 based locale").
>
> But I can force it to break using:
>
> PYTHONIOENCODING=ascii make check-qapi-schema
>
> > [...]
> > TESTtests/qapi-schema/union-base-empty.out
> > --- /builds/huth/qemu/tests/qapi-schema/unicode-str.err2019-05-03
> > 15:21:39.0 +
> > +++ - 2019-05-03 15:42:01.561762978 +
> > @@ -1 +1 @@
> > -tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name 'é'
> > +tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name '\xe9'
> > /builds/huth/qemu/tests/Makefile.include:1105: recipe for target
> > 'check-tests/qapi-schema/unicode-str.json' failed
> > make: *** [check-tests/qapi-schema/unicode-str.json] Error 1
> >
> > Any ideas how to fix this?
>
> Probably we just need to specify an explicit encoding at the statement that
> prints the error message to stderr. I will give it a try.
Forcing a specific encoding inside test-qapi.py would very easy
on Python 3.7+ (sys.stderr.reconfigure(...)), but tricky on older
versions. I believe this is the simplest way to fix the problem
on Python 3.5 and 3.6.
Can somebody confirm this really fixes the problem on gitlab-ci?
---
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 7c8b9c84b2..af88ab6f8b 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -1103,7 +1103,7 @@ check-tests/qemu-iotests-quick.sh:
tests/qemu-iotests-quick.sh qemu-img$(EXESUF)
.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y))
$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json:
$(SRC_PATH)/%.json
$(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \
- $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \
+ PYTHONIOENCODING=utf-8 $(PYTHON)
$(SRC_PATH)/tests/qapi-schema/test-qapi.py \
$^ >$*.test.out 2>$*.test.err; \
echo $$? >$*.test.exit, \
"TEST","$*.out")
--
Eduardo
Re: [Qemu-devel] Failing QEMU iotest 175
On Fri, May 3, 2019, 23:21 Eric Blake wrote: > On 5/2/19 11:37 PM, Thomas Huth wrote: > > On 02/05/2019 23.56, Eric Blake wrote: > >> On 4/28/19 10:18 AM, Thomas Huth wrote: > >>> QEMU iotest 175 is failing for me when I run it with -raw: > >>> > >> > >>> == creating image with default preallocation == > >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 > >>> -size=1048576, blocks=0 > >>> +size=1048576, blocks=2 > >> > >> What filesystem? > > > > ext4 > > > > Hmm, it's passing for me on ext4, but that probably means we have > different configuration parameters. I'm not sure how to easily show what > parameters a particular ext4 partition uses to compare the differences > between your setup and mine (mine is tuned to whatever defaults Fedora's > installer chose on my behalf), so maybe someone else can chime in. > > >> It should be fairly obvious that 'stat -c blocks=%b' is > >> file-system dependent (some allocate slightly more or less space, based > >> on granularities and on predictions of future use), so we may need to > >> update the test to apply a filter or otherwise allow a bit of fuzz in > >> the answer. But 0/2 is definitely different than... > >>> > >>> == creating image with preallocation off == > >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 > preallocation=off > >>> -size=1048576, blocks=0 > >>> +size=1048576, blocks=2 > >>> > >>> == creating image with preallocation full == > >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 > preallocation=full > >>> -size=1048576, blocks=2048 > >>> +size=1048576, blocks=2050 > >> > >> 2048/2050, so we DO have some indication of whether the file is sparse > >> or fully allocated. > > > > Maybe we could check that the value after "blocks=" is a single digit in > > the first case, and matches "blocks=20.." in the second case? > > I wonder if 'qemu-img map --output=json $TEST_IMG' might be any more > reliable (at least for ignoring any extra block allocations associated > with the file, if it is some journaling option or xattr or other reason > why your files seem to occupy more disk sectors than just the size of > the file would imply). > I think it should work better and is more correct, testing actual sparsness instead of underlying file system implementation. I can send a fix next week. Nir > -- > Eric Blake, Principal Software Engineer > Red Hat, Inc. +1-919-301-3226 > Virtualization: qemu.org | libvirt.org > >
Re: [Qemu-devel] [PATCH] qcow2: Assert that host cluster offsets fit in L2 table entries
On 5/3/19 4:38 AM, Alberto Garcia wrote: > The standard cluster descriptor in L2 table entries has a field to > store the host cluster offset. When we need to get that offset from an > entry we use L2E_OFFSET_MASK to ensure that we only use the bits that > belong to that field. > > But while that mask is used every time we read from an L2 entry, it > is never used when we write to it. Due to the QCOW_MAX_CLUSTER_OFFSET > limit set in the cluster allocation code QEMU can never produce > offsets that don't fit in that field so any such offset would indicate > a bug in QEMU. Yeah, I'm not seeing where this one could ever overflow. > > Compressed cluster descriptors contain two fields (host cluster offset > and size of the compressed data) and the situation with them is > similar. In this case the masks are not constant but are stored in the > csize_mask and cluster_offset_mask fields of BDRVQcow2State. For this one, we did have a bug in the past where we were overflowing, as evidenced by iotest 220 shortly after we patched the bug (77d6a215). > > Signed-off-by: Alberto Garcia > --- > block/qcow2-cluster.c | 14 -- > 1 file changed, 12 insertions(+), 2 deletions(-) > Adding more assertions shouldn't hurt. Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PULL 19/19] configure: automatically pick python3 is available
On Fri, May 03, 2019 at 06:41:43PM +0200, Thomas Huth wrote:
> On 03/05/2019 02.41, Eduardo Habkost wrote:
> > From: Daniel P. Berrangé
> >
> > Unless overridden via an env var or configure arg, QEMU will only look
> > for the 'python' binary in $PATH. This is unhelpful on distros which
> > are only shipping Python 3.x (eg Fedora) in their default install as,
> > if they comply with PEP 394, the bare 'python' binary won't exist.
> >
> > This changes configure so that by default it will search for all three
> > common python binaries, preferring to find Python 3.x versions.
> >
> > Signed-off-by: Daniel P. Berrangé
> > Message-Id: <20190327170701.23798-1-berra...@redhat.com>
> > Signed-off-by: Eduardo Habkost
> > ---
> > configure | 18 +++---
> > 1 file changed, 15 insertions(+), 3 deletions(-)
>
> I haven't bisected it, but I think this patch here broke the gitlab-ci tests:
>
> https://gitlab.com/huth/qemu/-/jobs/206806257
>
> Seems like the test is now failing when you don't have an UTF-8 locale:
>
> LANG=C make check-qapi-schema
I couldn't reproduce it this way, probably because I'm running Python 3.7 which
implements PEP 538 ("Coercing the legacy C locale to a UTF-8 based locale").
But I can force it to break using:
PYTHONIOENCODING=ascii make check-qapi-schema
> [...]
> TESTtests/qapi-schema/union-base-empty.out
> --- /builds/huth/qemu/tests/qapi-schema/unicode-str.err 2019-05-03
> 15:21:39.0 +
> +++ -2019-05-03 15:42:01.561762978 +
> @@ -1 +1 @@
> -tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name 'é'
> +tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name '\xe9'
> /builds/huth/qemu/tests/Makefile.include:1105: recipe for target
> 'check-tests/qapi-schema/unicode-str.json' failed
> make: *** [check-tests/qapi-schema/unicode-str.json] Error 1
>
> Any ideas how to fix this?
Probably we just need to specify an explicit encoding at the statement that
prints the error message to stderr. I will give it a try.
--
Eduardo
Re: [Qemu-devel] Failing QEMU iotest 221
On 5/2/19 11:43 PM, Thomas Huth wrote:
> On 03/05/2019 00.02, Eric Blake wrote:
>> On 4/28/19 10:21 AM, Thomas Huth wrote:
>>> QEMU iotest 221 is failing for me, too, when I run it with -raw:
>>
>> Which filesystem?
>
> ext4 again.
>
> $ stat -f /home/thuth/tmp/qemu-build/tests/qemu-iotests/
> File: "/home/thuth/tmp/qemu-build/tests/qemu-iotests/"
> ID: 1e68b4a412e09716 Namelen: 255 Type: ext2/ext3
> Block size: 1024 Fundamental block size: 1024
Odd that it is so small; these days, most ext4 systems have a block size
of 4k.
>
> Maybe the "check" script should report the output of "stat -f", too?
Wouldn't hurt, although that doesn't tell us all of the file system
tuning parameters that might be important to reproducing a problem.
>>> +++ /home/thuth/tmp/qemu-build/tests/qemu-iotests/221.out.bad
>>> 2019-04-28 17:18:52.0 +0200
>>> @@ -7,10 +7,10 @@
>>> [{ "start": 0, "length": 43520, "depth": 0, "zero": true, "data": false,
>>> "offset": OFFSET}]
>>> wrote 1/1 bytes at offset 43008
>>> 1 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
>>> -[{ "start": 0, "length": 40960, "depth": 0, "zero": true, "data": false,
>>> "offset": OFFSET},
>>> -{ "start": 40960, "length": 2049, "depth": 0, "zero": false, "data": true,
>>> "offset": OFFSET},
>>> +[{ "start": 0, "length": 43008, "depth": 0, "zero": true, "data": false,
>>> "offset": OFFSET},
>>> +{ "start": 43008, "length": 1, "depth": 0, "zero": false, "data": true,
>>> "offset": OFFSET},
>>
>> Ugh. Hole granularities are file-system specific, so we need to figure
>> out some way to fuzz the input. It might also be possible to pick nicer
>> size numbers - perhaps if the test image is sized at 64k+1 instead of
>> 43009 (84*512, but NOT evenly divisible by 4k), the +1 byte is more
>> likely to be directly one a hole boundary, rather than being somewhere
>> that causes rounding the hole boundary 2k earlier because of 4k or 64k
>> sizing constraints.
>
> Ok ... sounds like that's definitely something I'd like to leave to you
> or one of the block guys to fix.
I can certainly prepare a patch that widens the file to 64k+1 instead of
43008+1, but since I can't (yet) reproduce the failure, I'd be relying
on you to verify that it makes a difference.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
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Re: [Qemu-devel] [PATCH] VirtIO-RNG: Update default entropy source to `/dev/urandom`
On Fri, May 03, 2019 at 04:49:05PM +0100, Daniel P. Berrangé wrote: > On Fri, May 03, 2019 at 05:46:13PM +0200, Kashyap Chamarthy wrote: > > When QEMU exposes a VirtIO-RNG device to the guest, that device needs a > > source of entropy, and that source needs to be "non-blocking", like > > `/dev/urandom`. However, currently QEMU defaults to the problematic > > `/dev/random`, which is "blocking" (as in, it waits until sufficient > > entropy is available). > > > > So change the entropy source to the recommended `/dev/urandom`. > > > > Related discussion in these[1][2] past threads. > > > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-06/msg08335.html > > -- "RNG: Any reason QEMU doesn't default to `/dev/urandom`?" > > [2] https://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg02724.html > > -- "[RFC] Virtio RNG: Consider changing the default entropy source to > >/dev/urandom" > > > > Signed-off-by: Kashyap Chamarthy > > --- > > backends/rng-random.c | 2 +- > > qemu-options.hx | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > Reviewed-by: Daniel P. Berrangé I'm wondering if this needs to be mentioned on a Release Notes wiki somewhere -- because we're changing the default. -- /kashyap
Re: [Qemu-devel] [PATCH] chardev/char-i2c: Implement Linux I2C character device
On 5/3/19 2:31 PM, Ernest Esene wrote:
> Add support for Linux I2C character device for I2C device passthrough
> For example:
> -chardev linux-i2c,address=0x46,path=/dev/i2c-N,id=i2c-chardev
>
> Signed-off-by: Ernest Esene
> ---
Just an interface review:
> +++ b/qapi/char.json
> @@ -240,6 +240,21 @@
>'data': { 'device': 'str' },
>'base': 'ChardevCommon' }
>
> +##
> +# @ChardevI2c:
> +#
> +# Configuration info for i2c chardev (only on linux).
Rather than a parenthetical comment, you could use:
> +#
> +# @device: The name of the special file for the device,
> +# i.e. /dev/i2c-0 on linux
> +# @address: The address of the i2c device on the host.
> +#
> +##
Missing a 'Since: 4.1' line.
> +{ 'struct': 'ChardevI2c',
> + 'data': { 'device': 'str',
> +'address': 'int16'},
> + 'base': 'ChardevCommon'}
'if': 'defined(CONFIG_LINUX)'
as part of the usage of this struct, so that introspection will only see
the struct where it can be used.
> +
> ##
> # @ChardevSocket:
> #
> @@ -398,6 +413,7 @@
>'data': { 'file': 'ChardevFile',
> 'serial': 'ChardevHostdev',
> 'parallel': 'ChardevHostdev',
> +'i2c': 'ChardevI2c',
> 'pipe': 'ChardevHostdev',
> 'socket': 'ChardevSocket',
> 'udp': 'ChardevUdp',
>
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
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Re: [Qemu-devel] [PATCH v2 1/3] q35: set split kernel irqchip as default
On Fri, May 03, 2019 at 04:00:33PM -0400, Michael S. Tsirkin wrote:
> On Mon, Apr 29, 2019 at 11:55:56AM -0300, Eduardo Habkost wrote:
> > irqchip=split and irqchip=kernel aren't guest ABI compatible, are
> > they?
>
> Can you remind me why they aren't?
We have the code introduced by patch 3/3 from this series, but I
don't know if it's the only difference:
hw/i386/x86-iommu.c=static void x86_iommu_realize(DeviceState *dev, Error
**errp)
[...]
hw/i386/x86-iommu.c:bool irq_all_kernel = kvm_irqchip_in_kernel() &&
!kvm_irqchip_is_split();
[...]
hw/i386/x86-iommu.c-/* If the user didn't specify IR, choose a default
value for it */
hw/i386/x86-iommu.c-if (x86_iommu->intr_supported == ON_OFF_AUTO_AUTO) {
hw/i386/x86-iommu.c-x86_iommu->intr_supported = irq_all_kernel ?
hw/i386/x86-iommu.c-ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
hw/i386/x86-iommu.c-}
--
Eduardo
Re: [Qemu-devel] Failing QEMU iotest 175
On 5/2/19 11:37 PM, Thomas Huth wrote: > On 02/05/2019 23.56, Eric Blake wrote: >> On 4/28/19 10:18 AM, Thomas Huth wrote: >>> QEMU iotest 175 is failing for me when I run it with -raw: >>> >> >>> == creating image with default preallocation == >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 >>> -size=1048576, blocks=0 >>> +size=1048576, blocks=2 >> >> What filesystem? > > ext4 > Hmm, it's passing for me on ext4, but that probably means we have different configuration parameters. I'm not sure how to easily show what parameters a particular ext4 partition uses to compare the differences between your setup and mine (mine is tuned to whatever defaults Fedora's installer chose on my behalf), so maybe someone else can chime in. >> It should be fairly obvious that 'stat -c blocks=%b' is >> file-system dependent (some allocate slightly more or less space, based >> on granularities and on predictions of future use), so we may need to >> update the test to apply a filter or otherwise allow a bit of fuzz in >> the answer. But 0/2 is definitely different than... >>> >>> == creating image with preallocation off == >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 preallocation=off >>> -size=1048576, blocks=0 >>> +size=1048576, blocks=2 >>> >>> == creating image with preallocation full == >>> Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 preallocation=full >>> -size=1048576, blocks=2048 >>> +size=1048576, blocks=2050 >> >> 2048/2050, so we DO have some indication of whether the file is sparse >> or fully allocated. > > Maybe we could check that the value after "blocks=" is a single digit in > the first case, and matches "blocks=20.." in the second case? I wonder if 'qemu-img map --output=json $TEST_IMG' might be any more reliable (at least for ignoring any extra block allocations associated with the file, if it is some journaling option or xattr or other reason why your files seem to occupy more disk sectors than just the size of the file would imply). -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v2 1/3] q35: set split kernel irqchip as default
On Mon, Apr 29, 2019 at 11:55:56AM -0300, Eduardo Habkost wrote: > irqchip=split and irqchip=kernel aren't guest ABI compatible, are > they? Can you remind me why they aren't? > -- > Eduardo
[Qemu-devel] [PATCH] Deprecate Python 2 support
Python 2 will reach end of life in January 1 2020. Declare it as
deprecated.
Signed-off-by: Eduardo Habkost
---
configure| 8
qemu-deprecated.texi | 8
2 files changed, 16 insertions(+)
diff --git a/configure b/configure
index 5b183c2e39..50385061ed 100755
--- a/configure
+++ b/configure
@@ -6461,6 +6461,14 @@ if test "$supported_os" = "no"; then
echo "us upstream at qemu-devel@nongnu.org."
fi
+# Note that if the Python conditional here evaluates True we will exit
+# with status 1 which is a shell 'false' value.
+if ! $python -c 'import sys; sys.exit(sys.version_info < (3,0))'; then
+ echo
+ echo "WARNING: Python 2 support is deprecated" >&2
+ echo "WARNING: Python 3 will be required for building future versions of
QEMU" >&2
+fi
+
config_host_mak="config-host.mak"
echo "# Automatically generated by configure - do not modify"
>config-all-disas.mak
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 842e71b11d..2f2d9a3e95 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -206,3 +206,11 @@ Note that if you are exposing the export via /dev/nbd0, it
is easier
to just export the entire image and then mount only /dev/nbd0p1 than
it is to reinvoke @command{qemu-nbd -c /dev/nbd0} limited to just a
subset of the image.
+
+@section Build system
+
+@subsection Python 2 support (since 4.1.0)
+
+In the future, QEMU will require Python 3 to be available at
+build time. Support for Python 2 in scripts shipped with QEMU
+is deprecated.
--
2.18.0.rc1.1.g3f1ff2140
Re: [Qemu-devel] [PATCH v5 00/15] demacro softmmu (plus tests/coverage)
Richard Henderson writes: > On 4/30/19 9:52 AM, Alex Bennée wrote: >> I've also moved the existing system memory test and made it multiarch >> and added the bootstrapping for aarch64 system tests. I would like to >> add support for Big Endian as well but I didn't want to delay the >> posting of the series. It would also be nice to exercise the >> ioread/write paths and other handling but I leave this as an exercise >> for later. > > Somewhere in there you're adding > > -chardev file,path=hello.out,id=output It's in the default runner config in tests/tcg/Makefile > but there's no corresponding use of the chardev. > Which, somehow doesn't seem to matter to your aarch64 > testcase, Argh.. it's because -semihosting is different from -serial and doesn't allow the usual redirection rules you get with a chardev.. > but when I try this for alpha I truly get > no output at all. I needed > > -serial chardev:output or -serial chadev,id=output? > > to populate the file. > > > r~ -- Alex Bennée
[Qemu-devel] [PATCH] chardev/char-i2c: Implement Linux I2C character device
Add support for Linux I2C character device for I2C device passthrough
For example:
-chardev linux-i2c,address=0x46,path=/dev/i2c-N,id=i2c-chardev
Signed-off-by: Ernest Esene
---
chardev/Makefile.objs | 1 +
chardev/char-i2c.c | 142 +
chardev/char.c | 3 ++
include/chardev/char.h | 1 +
qapi/char.json | 16 ++
5 files changed, 163 insertions(+)
create mode 100644 chardev/char-i2c.c
diff --git a/chardev/Makefile.objs b/chardev/Makefile.objs
index d68e1347f9..6c96b9a353 100644
--- a/chardev/Makefile.objs
+++ b/chardev/Makefile.objs
@@ -16,6 +16,7 @@ chardev-obj-y += char-stdio.o
chardev-obj-y += char-udp.o
chardev-obj-$(CONFIG_WIN32) += char-win.o
chardev-obj-$(CONFIG_WIN32) += char-win-stdio.o
+chardev-obj-$(CONFIG_POSIX) +=char-i2c.o
common-obj-y += msmouse.o wctablet.o testdev.o
common-obj-$(CONFIG_BRLAPI) += baum.o
diff --git a/chardev/char-i2c.c b/chardev/char-i2c.c
new file mode 100644
index 00..78cf973bd7
--- /dev/null
+++ b/chardev/char-i2c.c
@@ -0,0 +1,142 @@
+/*
+ * QEMU System Emulator
+ *
+ * Copyright (c) 2019 Ernest Esene
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/option.h"
+#include "qemu-common.h"
+#include "io/channel-file.h"
+
+#include "chardev/char-fd.h"
+#include "chardev/char.h"
+
+#include
+#include
+
+#define CHR_IOCTL_I2C_SET_ADDR 1
+
+#define CHR_I2C_ADDR_10BIT_MAX 1023
+#define CHR_I2C_ADDR_7BIT_MAX 127
+
+void qemu_set_block(int fd);
+
+static int i2c_ioctl(Chardev *chr, int cmd, void *arg)
+{
+FDChardev *fd_chr = FD_CHARDEV(chr);
+QIOChannelFile *floc = QIO_CHANNEL_FILE(fd_chr->ioc_in);
+int fd = floc->fd;
+int addr;
+
+switch (cmd) {
+case CHR_IOCTL_I2C_SET_ADDR:
+addr = (int) (long) arg;
+
+if (addr > CHR_I2C_ADDR_7BIT_MAX) {
+/*TODO: check if adapter support 10-bit addr
+I2C_FUNC_10BIT_ADDR */
+if (ioctl(fd, I2C_TENBIT, addr) < 0) {
+goto err;
+}
+}
+else {
+if (ioctl(fd, I2C_SLAVE, addr) < 0) {
+goto err;
+}
+}
+break;
+
+default:
+return -ENOTSUP;
+
+}
+return 0;
+err:
+return -ENOTSUP;
+}
+
+static void qmp_chardev_open_i2c(Chardev *chr, ChardevBackend *backend,
+ bool *be_opened, Error **errp)
+{
+ChardevI2c *i2c = backend->u.i2c.data;
+void *addr;
+int fd;
+
+fd = qmp_chardev_open_file_source(i2c->device, O_RDWR | O_NONBLOCK,
+ errp);
+if (fd < 0) {
+ return;
+}
+qemu_set_block(fd);
+qemu_chr_open_fd(chr, fd, fd);
+addr = (void *) (long) i2c->address;
+i2c_ioctl(chr, CHR_IOCTL_I2C_SET_ADDR, addr);
+}
+
+static void qemu_chr_parse_i2c(QemuOpts *opts, ChardevBackend *backend, Error
**errp)
+{
+const char *device = qemu_opt_get(opts, "path");
+const char *addr = qemu_opt_get(opts, "address");
+long address;
+ChardevI2c *i2c;
+
+if (device == NULL) {
+error_setg(errp, "chardev: linux-i2c: no device path given");
+return;
+}
+if (addr == NULL) {
+error_setg(errp, "chardev: linux-i2c: no device address given");
+return;
+}
+address = strtol(addr, NULL, 0);
+if (address < 0 || address > CHR_I2C_ADDR_10BIT_MAX) {
+error_setg(errp, "chardev: linux-i2c: invalid device address given");
+return;
+}
+backend->type = CHARDEV_BACKEND_KIND_I2C;
+i2c = backend->u.i2c.data = g_new0(ChardevI2c, 1);
+qemu_chr_parse_common(opts, qapi_ChardevI2c_base(i2c));
+i2c->device = g_strdup(device);
+i2c->address = (int16_t) address;
+}
+
+static void char_i2c_class_init(ObjectClass *oc, void *data)
Re: [Qemu-devel] [PATCH RFC v8 01/12] target/rx: TCG translation
On 5/2/19 7:33 AM, Yoshinori Sato wrote:
> +/* conditional branch helper */
> +static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
> +{
> +DisasCompare dc;
> +TCGLabel *t, *done;
> +
> +switch (cd) {
> +case 0 ... 13:
> +dc.temp = tcg_temp_new();
> +psw_cond(&dc, cd);
> +t = gen_new_label();
> +done = gen_new_label();
> +tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t);
> +gen_goto_tb(ctx, 0, ctx->base.pc_next);
> +tcg_gen_br(done);
> +gen_set_label(t);
> +gen_goto_tb(ctx, 1, ctx->pc + dst);
> +gen_set_label(done);
> +tcg_temp_free(dc.temp);
> +break;
> +case 14:
> +/* always true case */
> +gen_goto_tb(ctx, 0, ctx->pc + dst);
> +break;
> +case 15:
> +/* always false case */
> +/* Nothing do */
> +break;
> +}
> +ctx->base.is_jmp = DISAS_JUMP;
> +}
Do not set is_jmp to DISAS_JUMP here. We have already set is_jmp to
DISAS_NORETURN in gen_goto_tb. For case 15, we do not need to exit the TB in
order to treat the never-taken branch as a nop.
This assignment means that we will emit *another* exit from the TB in
rx_tr_tb_stop, which will be unreachable code.
This is the only bug I see in this revision. Thanks for your patience!
r~
Re: [Qemu-devel] [PATCH v2] mips: Decide to map PAGE_EXEC in map_address
> (ping) > > Is there anything else I can do to help to get this merged? > > https://patchew.org/QEMU/20190423110034.1260142-1-jakub.jer...@kernkonzept.com/ Hello, Jakub. I will be reviewing your patch next week, please be patient. In any case, thanks for your involving in solving this issue! Aleksandar
Re: [Qemu-devel] [PATCH v2 1/3] q35: set split kernel irqchip as default
On Mon, Apr 29, 2019 at 09:22:12AM -0600, Alex Williamson wrote: [...] > > > What's a good 4.0.1 strategy to resolve this? Re-instate KVM irqchip > > > as the Q35 default? I can't see that simply switching to current QEMU > > > handling is a viable option for performance? What about 4.1? We could > > > certainly improve EOI support in QEMU, there's essentially no support > > > currently, but it seems like an uphill battle for an iothread based > > > userspace ioapic to ever compare to KVM handling? Thanks, > > > > irqchip=split and irqchip=kernel aren't guest ABI compatible, are > > they? That would make it impossible to fix this in pc-q35-4.0 > > for a 4.0.1 update. > > I suppose it would require a pc-q35-4.0.1 machine type :-\ Thanks, I wonder if it's possible to untangle this and make the irqchip option stop affecting guest ABI on 4.1+ machine-types? This way QEMU could choose smarter defaults in the future without the compatibility code hassle. -- Eduardo
Re: [Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.
On 5/3/19 8:27 AM, Alex Bennée wrote: > > Yoshinori Sato writes: > >> Some RX peripheral using 8bit and 16bit registers. >> Added 8bit and 16bit APIs. > > Doesn't this mean the build breaks at some point? Features used by other > patches should be introduced first so the build remains bisectable. The only bug I would fix in the ordering is to make the change to configure last, so that the target/rx is not enabled while the patches are staging. r~
Re: [Qemu-devel] [PATCH RFC v8 04/12] target/rx: RX disassembler
On 5/2/19 7:34 AM, Yoshinori Sato wrote:
> +static int32_t li(DisasContext *ctx, int sz)
> +{
> +int32_t addr;
> +bfd_byte buf[4];
> +addr = ctx->addr;
> +
> +switch (sz) {
> +case 1:
> +ctx->addr += 1;
> +ctx->dis->read_memory_func(addr, buf, 1, ctx->dis);
> +return buf[0];
> +case 2:
> +ctx->addr += 2;
> +ctx->dis->read_memory_func(addr, buf, 2, ctx->dis);
> +return buf[1] << 8 | buf[0];
> +case 3:
> +ctx->addr += 3;
> +ctx->dis->read_memory_func(addr, buf, 3, ctx->dis);
> +return buf[2] << 16 | buf[1] << 8 | buf[0];
> +case 0:
> +ctx->addr += 4;
> +ctx->dis->read_memory_func(addr, buf, 4, ctx->dis);
> +return buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0];
> +default:
> +g_assert_not_reached();
> +}
> +}
These should be computing signed values. This is already correct over in
translate.c. Also, we can make use of some endian-specific unaligned load
functions from . So for the 4 cases:
return (int8_t)buf[0];
return ldsw_le_p(buf);
return (int8_t)buf[2] << 16 | buf[1] << 8 | buf[0];
return ldl_le_p(buf);
r~
Re: [Qemu-devel] [PATCH] qom/object: Display more helpful message when an object type is missing
On Sat, Apr 27, 2019 at 03:56:42PM +0200, Philippe Mathieu-Daudé wrote: > When writing a new board, adding device which uses other devices > (container) or simply refactoring, one can discover the hard way > his machine misses some devices. In the case of containers, the > error is not obvious: > > $ qemu-system-microblaze -M xlnx-zynqmp-pmu > ** > ERROR:/source/qemu/qom/object.c:454:object_initialize_with_type: assertion > failed: (type != NULL) > Aborted (core dumped) > > And we have to look at the coredump to figure the error: > > (gdb) bt > #1 0x7f84773cf895 in abort () at /lib64/libc.so.6 > #2 0x7f847961fb53 in () at /lib64/libglib-2.0.so.0 > #3 0x7f847967a4de in g_assertion_message_expr () at > /lib64/libglib-2.0.so.0 > #4 0x55c4bcac6c11 in object_initialize_with_type > (data=data@entry=0x55c4bdf239e0, size=size@entry=2464, type=) > at /source/qemu/qom/object.c:454 > #5 0x55c4bcac6e6d in object_initialize > (data=data@entry=0x55c4bdf239e0, size=size@entry=2464, > typename=typename@entry=0x55c4bcc7c643 "xlnx.zynqmp_ipi") at > /source/qemu/qom/object.c:474 > #6 0x55c4bc9ea474 in xlnx_zynqmp_pmu_init (machine=0x55c4bdd46000) at > /source/qemu/hw/microblaze/xlnx-zynqmp-pmu.c:176 > #7 0x55c4bca3b6cb in machine_run_board_init (machine=0x55c4bdd46000) > at /source/qemu/hw/core/machine.c:1030 > #8 0x55c4bc95f6d2 in main (argc=, argv=, > envp=) at /source/qemu/vl.c:4479 > > Since the caller knows the type name requested, we can simply display it > to ease development. > > With this patch applied we get: > > $ qemu-system-microblaze -M xlnx-zynqmp-pmu > qemu-system-microblaze: missing object type 'xlnx.zynqmp_ipi' > Aborted (core dumped) > > Since the assert(type) check in object_initialize_with_type() is > now impossible, remove it. > > Signed-off-by: Philippe Mathieu-Daudé Queued, thanks! -- Eduardo
Re: [Qemu-devel] [PATCH 1/3] ram-encrypted-notifier: Introduce a RAM block encrypted notifier
On Fri, Apr 26, 2019 at 02:32:51PM +, Janakarajan Natarajan wrote: > On 4/26/19 7:29 AM, Igor Mammedov wrote: [...] > >> diff --git a/numa.c b/numa.c > >> index 3875e1efda..08601366c5 100644 > >> --- a/numa.c > >> +++ b/numa.c > > looks like wrong file to put RAMBlock code in. I though that we should put > > it in exec.c > > > I placed the RAMBlockEncrypted Notifier code along with the RAMBlock > Notifier code. Paolo, Fam, do you remember why was the ram block notifier code added to numa.c instead of memory.c or exec.c? -- Eduardo
Re: [Qemu-devel] [PATCH v3 36/40] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
On 5/2/19 7:10 AM, David Hildenbrand wrote: > Mostly courtesy of Richard H. > > Signed-off-by: David Hildenbrand > --- > target/s390x/insn-data.def | 2 ++ > target/s390x/translate_vx.inc.c | 34 + > 2 files changed, 36 insertions(+) Reviewed-by: Richard Henderson r~
Re: [Qemu-devel] Following up questions related to QEMU and I/O Thread
Hi Paolo, That will be great, I would like to hear more details about the design and implementation once you get those ready. Thanks a lot, Wei On 5/3/19, 11:05 AM, "Paolo Bonzini" wrote: On 03/05/19 10:21, Wei Li wrote: > Got it, thanks Stefan for your clarification! Hi Wei, Stefan and I should be posting a patch to add Linux SCSI driver batching, and an implementation for virtio-scsi. Paolo > Wei > > On 5/1/19, 9:36 AM, "Stefan Hajnoczi" wrote: > > On Mon, Apr 29, 2019 at 10:56:31AM -0700, Wei Li wrote: > >Does this mean the performance could be improved via adding Batch I/O submission support in Guest driver side which will be able to reduce the number of virtqueue kicks? > > Yes, I think so. It's not obvious to me how a Linux SCSI driver is > supposed to implement batching though. The .queuecommand API doesn't > seem to include information relevant to batching. > > Stefan > > > >
Re: [Qemu-devel] Following up questions related to QEMU and I/O Thread
On 03/05/19 10:21, Wei Li wrote: > Got it, thanks Stefan for your clarification! Hi Wei, Stefan and I should be posting a patch to add Linux SCSI driver batching, and an implementation for virtio-scsi. Paolo > Wei > > On 5/1/19, 9:36 AM, "Stefan Hajnoczi" wrote: > > On Mon, Apr 29, 2019 at 10:56:31AM -0700, Wei Li wrote: > >Does this mean the performance could be improved via adding Batch I/O > submission support in Guest driver side which will be able to reduce the > number of virtqueue kicks? > > Yes, I think so. It's not obvious to me how a Linux SCSI driver is > supposed to implement batching though. The .queuecommand API doesn't > seem to include information relevant to batching. > > Stefan > > > >
[Qemu-devel] [PATCH v4 3/5] linux-user: Add support the SIOCIFPFLAGS ioctls for all targets
From: Neng Chen
Add support for getting and setting extended private flags of a
network device via SIOCSIFPFLAGS and SIOCGIFPFLAGS ioctls.
The ioctl numeric values are platform-independent and determined by
the file include/uapi/linux/sockios.h in Linux kernel source code:
#define SIOCSIFPFLAGS 0x8934
#define SIOCGIFPFLAGS 0x8935
These ioctls get (or set) the field ifr_flags of type short in the
structure ifreq. Such functionality is achieved in QEMU by using
MK_STRUCT() and MK_PTR() macros with an appropriate argument, as
it was done for existing similar cases.
Signed-off-by: Neng Chen
Signed-off-by: Aleksandar Markovic
Message-Id: <1554839486-3527-1-git-send-email-aleksandar.marko...@rt-rk.com>
---
linux-user/ioctls.h | 2 ++
linux-user/syscall_defs.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index c37adc5..76375df 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -206,6 +206,8 @@
IOCTL(SIOCADDMULTI, IOC_W, MK_PTR(MK_STRUCT(STRUCT_sockaddr_ifreq)))
IOCTL(SIOCDELMULTI, IOC_W, MK_PTR(MK_STRUCT(STRUCT_sockaddr_ifreq)))
IOCTL(SIOCGIFINDEX, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_int_ifreq)))
+ IOCTL(SIOCSIFPFLAGS, IOC_W, MK_PTR(MK_STRUCT(STRUCT_short_ifreq)))
+ IOCTL(SIOCGIFPFLAGS, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_short_ifreq)))
IOCTL(SIOCSIFLINK, 0, TYPE_NULL)
IOCTL_SPECIAL(SIOCGIFCONF, IOC_W | IOC_R, do_ioctl_ifconf,
MK_PTR(MK_STRUCT(STRUCT_ifconf)))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 2941231..8904d35 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -781,6 +781,8 @@ struct target_pollfd {
#define TARGET_SIOCADDMULTI0x8931 /* Multicast address lists
*/
#define TARGET_SIOCDELMULTI0x8932
#define TARGET_SIOCGIFINDEX0x8933
+#define TARGET_SIOCSIFPFLAGS 0x8934 /* set extended flags
*/
+#define TARGET_SIOCGIFPFLAGS 0x8935 /* get extended flags
*/
/* Bridging control calls */
#define TARGET_SIOCGIFBR 0x8940 /* Bridging support
*/
--
2.7.4
[Qemu-devel] [PATCH v4 4/5] linux-user: Add support for setsockopt() options IPV6__MEMBERSHIP
From: Neng Chen
Add support for options IPV6_ADD_MEMBERSHIP and IPV6_DROP_MEMPEMBERSHIP
of the syscall setsockopt(). These options control membership in
multicast groups. Their argument is a pointer to a struct ipv6_mreq,
which is in turn defined as:
struct ipv6_mreq {
/* IPv6 multicast address of group */
struct in6_addr ipv6mr_multiaddr;
/* local IPv6 address of interface */
int ipv6mr_interface;
};
The in6_addr structure consists of fields that are always big-endian
(on host of any endian), so the ipv6_mreq's field ipv6mr_multiaddr
doesn't need any endian conversion, whereas ipv6mr_interface does.
Signed-off-by: Neng Chen
Signed-off-by: Aleksandar Markovic
---
linux-user/syscall.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 96cd4bf..b7eb4b7 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -1892,6 +1892,25 @@ static abi_long do_setsockopt(int sockfd, int level, int
optname,
&pki, sizeof(pki)));
break;
}
+case IPV6_ADD_MEMBERSHIP:
+case IPV6_DROP_MEMBERSHIP:
+{
+struct ipv6_mreq ipv6mreq;
+
+if (optlen < sizeof(ipv6mreq)) {
+return -TARGET_EINVAL;
+}
+
+if (copy_from_user(&ipv6mreq, optval_addr, sizeof(ipv6mreq))) {
+return -TARGET_EFAULT;
+}
+
+ipv6mreq.ipv6mr_interface = tswap32(ipv6mreq.ipv6mr_interface);
+
+ret = get_errno(setsockopt(sockfd, level, optname,
+ &ipv6mreq, sizeof(ipv6mreq)));
+break;
+}
default:
goto unimplemented;
}
--
2.7.4
[Qemu-devel] [PATCH v4 5/5] linux-user: Sanitize interp_info and, for mips only, init field fp_abi
From: Daniel Santos Sanitize interp_info structure in load_elf_binary() and, for MIPS only, init its field fp_abi to MIPS_ABI_FP_UNKNOWN. This fixes appearances of "Unexpected FPU mode" message in some MIPS use cases. Currently, this bug is a complete stopper for some MIPS binaries. In load_elf_binary(), struct image_info interp_info is used without being properly initialized. One result is that when the ELF's program header doesn't contain an entry for the ABI flags, then the value of the struct image_info's fp_abi field is set to whatever happened to be in stack memory at the time. Backporting to 4.0 and, if possible, to 3.1 is recommended. Fixes: https://bugs.launchpad.net/qemu/+bug/1825002 Signed-off-by: Daniel Santos Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé --- linux-user/elfload.c | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c1a2602..7f09d57 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2698,6 +2698,11 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) char *elf_interpreter = NULL; char *scratch; +memset(&interp_info, 0, sizeof(interp_info)); +#ifdef TARGET_MIPS +interp_info.fp_abi = MIPS_ABI_FP_UNKNOWN; +#endif + info->start_mmap = (abi_ulong)ELF_START_MMAP; load_elf_image(bprm->filename, bprm->fd, info, -- 2.7.4
[Qemu-devel] [PATCH v4 1/5] linux-user: Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa
From: Aleksandar Markovic
Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa by
correcting corresponding macro definition.
Values for TARGET_SIOCATMARK and TARGET_SIOCGPGRP are determined by
Linux kernel. Following relevant lines (obtained by grep) are from
the kernel source tree:
arch/ia64/include/uapi/asm/sockios.h:#define SIOCATMARK0x8905
arch/mips/include/uapi/asm/sockios.h:#define SIOCATMARK_IOR('s', 7, int)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905
arch/sh/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905
include/uapi/asm-generic/sockios.h:#define SIOCATMARK 0x8905
arch/ia64/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904
arch/mips/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904
arch/sh/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCGPGRP_IOR('s', 9, pid_t)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCGPGRP0x8904
include/uapi/asm-generic/sockios.h:#define SIOCGPGRP 0x8904
It is visible from above that xtensa should have the same definitions
as alpha, mips and sh4 already do. This patch brings QEMU to the accurate
state wrt these two ioctls.
Acked-by: Max Filippov
Signed-off-by: Aleksandar Markovic
---
linux-user/syscall_defs.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 12c8407..1e86fb9 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -736,7 +736,8 @@ struct target_pollfd {
#define TARGET_KDSETLED0x4B32 /* set led state [lights, not flags] */
#define TARGET_KDSIGACCEPT 0x4B4E
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) ||
\
+ defined(TARGET_XTENSA)
#define TARGET_SIOCATMARK TARGET_IOR('s', 7, int)
#define TARGET_SIOCGPGRP TARGET_IOR('s', 9, pid_t)
#else
--
2.7.4
[Qemu-devel] [PATCH v4 2/5] linux-user: Add support for the SIOCSPGRP ioctl for all targets
From: Aleksandar Markovic
Add support for setting the process (or process group) to receive SIGIO
or SIGURG signals when I/O becomes possible or urgent data is available,
using SIOCSPGRP ioctl.
The ioctl numeric values for SIOCSPGRP are platform-dependent and are
determined by following files in Linux kernel source tree:
arch/ia64/include/uapi/asm/sockios.h:#define SIOCSPGRP0x8902
arch/mips/include/uapi/asm/sockios.h:#define SIOCSPGRP_IOW('s', 8, pid_t)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902
arch/sh/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902
include/uapi/asm-generic/sockios.h:#define SIOCSPGRP 0x8902
Hence the different definition for alpha, mips, sh4, and xtensa.
Reviewed-by: Max Filippov
Signed-off-by: Aleksandar Markovic
---
linux-user/ioctls.h | 1 +
linux-user/syscall_defs.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index ae89516..c37adc5 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -218,6 +218,7 @@
IOCTL(SIOCSRARP, IOC_W, MK_PTR(MK_STRUCT(STRUCT_arpreq)))
IOCTL(SIOCGRARP, IOC_R, MK_PTR(MK_STRUCT(STRUCT_arpreq)))
IOCTL(SIOCGIWNAME, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_char_ifreq)))
+ IOCTL(SIOCSPGRP, IOC_W, MK_PTR(TYPE_INT)) /* pid_t */
IOCTL(SIOCGPGRP, IOC_R, MK_PTR(TYPE_INT)) /* pid_t */
IOCTL(SIOCGSTAMP, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timeval)))
IOCTL(SIOCGSTAMPNS, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timespec)))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 1e86fb9..2941231 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -739,11 +739,14 @@ struct target_pollfd {
#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) ||
\
defined(TARGET_XTENSA)
#define TARGET_SIOCATMARK TARGET_IOR('s', 7, int)
+#define TARGET_SIOCSPGRP TARGET_IOW('s', 8, pid_t)
#define TARGET_SIOCGPGRP TARGET_IOR('s', 9, pid_t)
#else
#define TARGET_SIOCATMARK 0x8905
+#define TARGET_SIOCSPGRP 0x8902
#define TARGET_SIOCGPGRP 0x8904
#endif
+
#define TARGET_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
#define TARGET_SIOCGSTAMPNS0x8907 /* Get stamp (timespec) */
--
2.7.4
[Qemu-devel] [PATCH v4 0/5] linux-user: A set of miscellaneous patches
From: Aleksandar Markovic This is a collection of misc patches for Linux user that I recently accumulated from variuous sources. All of them originate from problems observed on mips target. However, these changes actually affect and fix problems on multiple targets. v3->v4: - improved commit messages (fixed some typos, improved relevance) v2->v3: - updated and improved commit messages - added IPV6_DROP_MEMBERSHIP support to the patch on setsockopt()'s option v1->v2: - added the patch on setsockopt()'s option IPV6_ADD_MEMBERSHIP - improved the commit message of interp_info sanitizing patch Aleksandar Markovic (2): linux-user: Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa linux-user: Add support for the SIOCSPGRP ioctl for all targets Daniel Santos (1): linux-user: Sanitize interp_info and, for mips only, init field fp_abi Neng Chen (2): linux-user: Add support the SIOCIFPFLAGS ioctls for all targets linux-user: Add support for setsockopt() options IPV6__MEMBERSHIP linux-user/elfload.c | 5 + linux-user/ioctls.h | 3 +++ linux-user/syscall.c | 19 +++ linux-user/syscall_defs.h | 8 +++- 4 files changed, 34 insertions(+), 1 deletion(-) -- 2.7.4
[Qemu-devel] [Bug 1817345] Re: configure script breaks when $source_path contains white spaces
Antonio has submitted a patchset here: https://patchew.org/QEMU/20190503082728.16485-1-...@ao2.it/ ** Changed in: qemu Status: New => In Progress -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1817345 Title: configure script breaks when $source_path contains white spaces Status in QEMU: In Progress Bug description: Hi, I noticed that the configure script breaks when the qemu source directory is in a path containing white spaces, in particular the list of targets is not correctly generated when calling "./configure --help". Steps to reproduce the problem: $ mkdir "dir with spaces" $ cd dir\ with\ spaces/ $ git clone https://git.qemu.org/git/qemu.git $ cd qemu/ $ ./configure --help | grep -A3 target-list Actual result: --target-list=LIST set target list (default: build everything) Available targets: dir with *-softmmu dir with *-linux-user Expected result: --target-list=LIST set target list (default: build everything) Available targets: aarch64-softmmu alpha-softmmu arm-softmmu cris-softmmu hppa-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblaze-softmmu This happens because the $mak_wilds variable uses spaces to separate different paths, maybe newlines may be used, which are less likely to be in directory names. BTW "shellcheck" may help finding some other problems. Qemu version: $ git describe v3.1.0-1960-ga05838cb2a Thanks, Antonio To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1817345/+subscriptions
Re: [Qemu-devel] [PATCH 1/2] hw/arm/boot: Avoid placing the initrd on top of the kernel
On Fri, 3 May 2019 at 18:13, Peter Maydell wrote: > > We currently put the initrd at the smaller of: > * 128MB into RAM > * halfway into the RAM > (with the dtb following it). > > However for large kernels this might mean that the kernel > overlaps the initrd. For some kinds of kernel (self-decompressing > 32-bit kernels, and ELF images with a BSS section at the end) > we don't know the exact size, but even there we have a > minimum size. Put the initrd at least further into RAM than > that. For image formats that can give us an exact kernel size, this > will mean that we definitely avoid overlaying kernel and initrd. > > Signed-off-by: Peter Maydell > --- > hw/arm/boot.c | 34 -- > 1 file changed, 20 insertions(+), 14 deletions(-) > > diff --git a/hw/arm/boot.c b/hw/arm/boot.c > index a830655e1af..7c978fedde4 100644 > --- a/hw/arm/boot.c > +++ b/hw/arm/boot.c > @@ -998,20 +998,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, > if (info->nb_cpus == 0) > info->nb_cpus = 1; > > -/* > - * We want to put the initrd far enough into RAM that when the > - * kernel is uncompressed it will not clobber the initrd. However > - * on boards without much RAM we must ensure that we still leave > - * enough room for a decent sized initrd, and on boards with large > - * amounts of RAM we must avoid the initrd being so far up in RAM > - * that it is outside lowmem and inaccessible to the kernel. > - * So for boards with less than 256MB of RAM we put the initrd > - * halfway into RAM, and for boards with 256MB of RAM or more we put > - * the initrd at 128MB. > - */ > -info->initrd_start = info->loader_start + > -MIN(info->ram_size / 2, 128 * 1024 * 1024); > - > /* Assume that raw images are linux kernels, and ELF images are not. */ > kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, > &elf_high_addr, elf_machine, as); > @@ -1056,6 +1042,26 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, > exit(1); > } > info->entry = entry; > + > +/* > + * We want to put the initrd far enough into RAM that when the > + * kernel is uncompressed it will not clobber the initrd. However > + * on boards without much RAM we must ensure that we still leave > + * enough room for a decent sized initrd, and on boards with large > + * amounts of RAM we must avoid the initrd being so far up in RAM > + * that it is outside lowmem and inaccessible to the kernel. > + * So for boards with less than 256MB of RAM we put the initrd > + * halfway into RAM, and for boards with 256MB of RAM or more we put > + * the initrd at 128MB. > + * We also refuse to put the initrd somewhere that will definitely > + * overlay the kernel we just loaded, though for kernel formats which > + * don't tell us their exact size (eg self-decompressing 32-bit kernels) > + * we might still make a bad choice here. > + */ > +info->initrd_start = info->loader_start + > +MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size); > +info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); > + I belatedly realized that we should probably check here whether this is off the end of the ram, as otherwise following code will get an underflow in "info->ram_size - info->initrd_start" which is unlikely to result in useful behaviour. thanks -- PMM
Re: [Qemu-devel] [PATCH v2] security.rst: add Security Guide to developer docs
On Fri, May 03, 2019 at 10:04:10AM +0100, Alex Bennée wrote: > Stefan Hajnoczi writes: > > +Isolation mechanisms > > + > > +Several isolation mechanisms are available to realize this architecture of > > +guest isolation and the principle of least privilege. With the exception > > of > > +Linux seccomp, these mechanisms are all deployed by management tools that > > +launch QEMU, such as libvirt. They are also platform-specific so they are > > only > > +described briefly for Linux here. > > + > > +The fundamental isolation mechanism is that QEMU processes must run as > > +**unprivileged users**. Sometimes it seems more convenient to launch QEMU > > as > > +root to give it access to host devices (e.g. ``/dev/net/tun``) but this > > poses a > > +huge security risk. File descriptor passing can be used to give an > > otherwise > > +unprivileged QEMU process access to host devices without running QEMU > > as root. > > Should we mention that you can still maintain running as a user and just > make the devices you need available to the user/group rather than > becoming root? For example I generally make /dev/kvm group accessible to > my user account. Sure. I checked that /dev/vhost-* device nodes are root:root on Fedora so at least the distro doesn't expect you to do that. The /dev/kvm device node is root:kvm so it's easy to do it by joining the kvm group there. Stefan signature.asc Description: PGP signature
Re: [Qemu-devel] [PATCH v2] security.rst: add Security Guide to developer docs
On Fri, May 03, 2019 at 11:35:29AM +0100, Daniel P. Berrangé wrote: > On Fri, May 03, 2019 at 11:28:53AM +0100, Peter Maydell wrote: > > On Fri, 3 May 2019 at 11:19, Daniel P. Berrangé wrote: > > > Everything above here is useful to QEMU devs, app devs & end users and > > > should be made part of the main QEMU doc - convert it to texi and @include > > > it from qemu-doc.texi, as we do for other stuff under docs/ > > > > If we convert it to texi we'll have to convert it back again > > as/when we migrate properly from texi to sphinx... (I would > > like to make further moves in that direction during this > > release cycle -- just need to find the time to work on it.) > > Yes, but we're only talking about 100-150 lines of simple text with > minimal markup needs. Won't be a noticable extra burden compared to > the pre-existing 4700 lines of texi markup for qemu-doc.texi and its > includes. I'm happy to split as suggested and do it in texi for now. I am also happy to convert the file back to rst again later. Stefan signature.asc Description: PGP signature
[Qemu-devel] [Bug 1823998] Re: qemu-system-aarch64: support kernels bigger than 128MiB
I've submitted a patchset which I think should fix this, but if you could test that it actually does handle large images correctly that would be great. https://patchew.org/QEMU/20190503171347.13747-1-peter.mayd...@linaro.org/ ** Changed in: qemu Status: New => In Progress -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1823998 Title: qemu-system-aarch64: support kernels bigger than 128MiB Status in QEMU: In Progress Bug description: Presently QEMU reserves up to 128MiB of space for an arm64 Linux kernel, placing the initrd following this, and the dtb following the initrd. This is not sufficient for some debug configurations of the kernel, which can be larger than 128MiB. Depending on the relative size of the kernel Image and unpopulated BSS, the dtb (or kernel) will be clobbered by the other, resulting in a silent boot failure. Since v3.17, the kernel Image header exposes a field called image_size, which describes the entire size of the kernel (including unpopulated sections such as the BSS) as a 64-bit little-endian value. For kernels prior to v3.17, this field is zero. This is documented at: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.txt?h=v5.0#n68 It would be great if QEMU could take the image_size field into account when placing the initrd and dtb to avoid overlap with the kernel. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1823998/+subscriptions
Re: [Qemu-devel] [PATCH] target/arm: Implement NSACR gating of floating point
On 5/3/19 6:13 AM, Peter Maydell wrote: > On Sat, 13 Apr 2019 at 08:07, Richard Henderson >> This one does do the right thing, but better to clear the bits on write to >> NSACR. This lets you avoid the change to fp_exception_el, and the missing >> change to sve_exception_el. > > Hi Richard -- I was just going through the review comments on this > patchset, and I saw this bit. Could you clarify what you mean by > "the missing change to sve_exception_el" ? Since SVE is AArch64 only, > there can't be any configs where we have SVE and EL3 is AArch32, > so I don't think these two features should be able to interact. You're right. I'm going to assume I had been insufficiently caffeinated at the time. r~
Re: [Qemu-devel] [PATCH v2] block/rbd: increase dynamically the image size
On Fri, May 3, 2019 at 12:30 PM Stefano Garzarella wrote:
>
> RBD APIs don't allow us to write more than the size set with
> rbd_create() or rbd_resize().
> In order to support growing images (eg. qcow2), we resize the
> image before write operations that exceed the current size.
>
> Signed-off-by: Stefano Garzarella
> ---
> v2:
> - use bs->total_sectors instead of adding a new field [Kevin]
> - resize the image only during write operation [Kevin]
> for read operation, the bdrv_aligned_preadv() already handles reads
> that exceed the length returned by bdrv_getlength(), so IMHO we can
> avoid to handle it in the rbd driver
> ---
> block/rbd.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/block/rbd.c b/block/rbd.c
> index 0c549c9935..613e8f4982 100644
> --- a/block/rbd.c
> +++ b/block/rbd.c
> @@ -934,13 +934,25 @@ static BlockAIOCB *rbd_start_aio(BlockDriverState *bs,
> }
>
> switch (cmd) {
> -case RBD_AIO_WRITE:
> +case RBD_AIO_WRITE: {
> +/*
> + * RBD APIs don't allow us to write more than actual size, so in
> order
> + * to support growing images, we resize the image before write
> + * operations that exceed the current size.
> + */
> +if (off + size > bs->total_sectors * BDRV_SECTOR_SIZE) {
When will "bs->total_sectors" be refreshed to represent the correct
current size? You wouldn't want a future write whose extent was
greater than the original image size but less then a previous IO that
expanded the image to attempt to shrink the image.
> +r = rbd_resize(s->image, off + size);
> +if (r < 0) {
> +goto failed_completion;
> +}
> +}
> #ifdef LIBRBD_SUPPORTS_IOVEC
> r = rbd_aio_writev(s->image, qiov->iov, qiov->niov, off, c);
> #else
> r = rbd_aio_write(s->image, off, size, rcb->buf, c);
> #endif
> break;
> +}
> case RBD_AIO_READ:
> #ifdef LIBRBD_SUPPORTS_IOVEC
> r = rbd_aio_readv(s->image, qiov->iov, qiov->niov, off, c);
> --
> 2.20.1
>
>
--
Jason
[Qemu-devel] [PATCH v3 1/5] linux-user: Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa
From: Aleksandar Markovic
Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa by
correcting corresponding macro definition.
Values for TARGET_SIOCATMARK and TARGET_SIOCGPGRP are determined by
Linux kernel. Following relevant lines are from kernel source tree:
arch/ia64/include/uapi/asm/sockios.h:#define SIOCATMARK0x8905
arch/mips/include/uapi/asm/sockios.h:#define SIOCATMARK_IOR('s', 7, int)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905
arch/sh/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCATMARK _IOR('s', 7, int)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCATMARK 0x8905
include/uapi/asm-generic/sockios.h:#define SIOCATMARK 0x8905
arch/ia64/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904
arch/mips/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCGPGRP 0x8904
arch/sh/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCGPGRP _IOR('s', 9, pid_t)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCGPGRP_IOR('s', 9, pid_t)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCGPGRP0x8904
include/uapi/asm-generic/sockios.h:#define SIOCGPGRP 0x8904
It is visible that xtensa should have the same definitions as
alpha, mips and sh4 already do. This patch brings that to the
accurate state.
Acked-by: Max Filippov
Signed-off-by: Aleksandar Markovic
---
linux-user/syscall_defs.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 12c8407..1e86fb9 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -736,7 +736,8 @@ struct target_pollfd {
#define TARGET_KDSETLED0x4B32 /* set led state [lights, not flags] */
#define TARGET_KDSIGACCEPT 0x4B4E
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4)
+#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) ||
\
+ defined(TARGET_XTENSA)
#define TARGET_SIOCATMARK TARGET_IOR('s', 7, int)
#define TARGET_SIOCGPGRP TARGET_IOR('s', 9, pid_t)
#else
--
2.7.4
[Qemu-devel] [PATCH 2/2] hw/arm/boot: Honour image size field in AArch64 Image format kernels
Since Linux v3.17, the kernel's Image header includes a field image_size,
which gives the total size of the kernel including unpopulated data
sections such as the BSS). If this is present, then return it from
load_aarch64_image() as the true size of the kernel rather than
just using the size of the Image file itself. This allows the code
which calculates where to put the initrd to avoid putting it in
the kernel's BSS area.
This means that we should be able to reliably load kernel images
which are larger than 128MB without accidentally putting the
initrd or dtb in locations that clash with the kernel itself.
Fixes: https://bugs.launchpad.net/qemu/+bug/1823998
Signed-off-by: Peter Maydell
---
hw/arm/boot.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 7c978fedde4..34bdd151df8 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -910,6 +910,7 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
hwaddr *entry, AddressSpace *as)
{
hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
+uint64_t kernel_size = 0;
uint8_t *buffer;
int size;
@@ -937,7 +938,10 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
* is only valid if the image_size is non-zero.
*/
memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
-if (hdrvals[1] != 0) {
+
+kernel_size = le64_to_cpu(hdrvals[1]);
+
+if (kernel_size != 0) {
kernel_load_offset = le64_to_cpu(hdrvals[0]);
/*
@@ -955,12 +959,21 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
}
}
+/*
+ * Kernels before v3.17 don't populate the image_size field, and
+ * raw images have no header. For those our best guess at the size
+ * is the size of the Image file itself.
+ */
+if (kernel_size == 0) {
+kernel_size = size;
+}
+
*entry = mem_base + kernel_load_offset;
rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
g_free(buffer);
-return size;
+return kernel_size;
}
static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
--
2.20.1
Re: [Qemu-devel] [PATCH v4] hw/virtio/virtio-mmio: Convert DPRINTF to trace and log
Gotcha, thanks for the tip! Best regards, Boxuan Li On Sat, May 4, 2019 at 1:00 AM Alex Bennée wrote: > > LI, BO XUAN writes: > > > Hi Alex, > > > > Sorry about that, I am still trying to get familiar with the patch > > submission process. Since my patch has been changed from your last > review, > > I thought it would be safe to not include the r-b tag from last time. > Will > > take care next time! > > That's ok. As a general rule as long as you haven't substantially > changed a patch it's safe to keep previous r-b tags. You can always > mention it in your cover letter if you are unsure. > > -- > Alex Bennée >
[Qemu-devel] [PATCH 1/2] blockjob: Fix coroutine thread after AioContext change
Commit 463e0be10 ('blockjob: add AioContext attached callback') tried to
make block jobs robust against AioContext changes of their main node,
but it never made sure that the job coroutine actually runs in the new
thread.
Instead of waking up the job coroutine in whatever thread it ran before,
let's always pass the AioContext where it should be running now.
Signed-off-by: Kevin Wolf
---
job.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/job.c b/job.c
index da8e4b7bf2..2167d53717 100644
--- a/job.c
+++ b/job.c
@@ -432,7 +432,7 @@ void job_enter_cond(Job *job, bool(*fn)(Job *job))
timer_del(&job->sleep_timer);
job->busy = true;
job_unlock();
-aio_co_wake(job->co);
+aio_co_enter(job->aio_context, job->co);
}
void job_enter(Job *job)
--
2.20.1
[Qemu-devel] [PATCH v3 4/5] linux-user: Add support for setsockopt() options IPV6__MEMBERSHIP
From: Neng Chen
Add support for options IPV6_ADD_MEMBERSHIP and IPV6_ADD_MEMBERSHIP
of the syscall setsockopt(). These options control membership in
multicast groups. Their argument is a pointer to a struct ipv6_mreq,
which is in turn defined as:
struct ipv6_mreq {
/* IPv6 multicast address of group */
struct in6_addr ipv6mr_multiaddr;
/* local IPv6 address of interface */
int ipv6mr_interface;
};
The in6_addr structure consists of fields that are always big-endian
(on any host), so the ipv6_mreq's field ipv6mr_multiaddr doesn't need
any endian conversion, whereas ipv6mr_interface does.
Signed-off-by: Neng Chen
Signed-off-by: Aleksandar Markovic
---
linux-user/syscall.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 96cd4bf..b7eb4b7 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -1892,6 +1892,25 @@ static abi_long do_setsockopt(int sockfd, int level, int
optname,
&pki, sizeof(pki)));
break;
}
+case IPV6_ADD_MEMBERSHIP:
+case IPV6_DROP_MEMBERSHIP:
+{
+struct ipv6_mreq ipv6mreq;
+
+if (optlen < sizeof(ipv6mreq)) {
+return -TARGET_EINVAL;
+}
+
+if (copy_from_user(&ipv6mreq, optval_addr, sizeof(ipv6mreq))) {
+return -TARGET_EFAULT;
+}
+
+ipv6mreq.ipv6mr_interface = tswap32(ipv6mreq.ipv6mr_interface);
+
+ret = get_errno(setsockopt(sockfd, level, optname,
+ &ipv6mreq, sizeof(ipv6mreq)));
+break;
+}
default:
goto unimplemented;
}
--
2.7.4
[Qemu-devel] [PATCH 0/2] blockjob: Fix coroutine thread after AioContext change
Kevin Wolf (2): blockjob: Fix coroutine thread after AioContext change test-block-iothread: Job coroutine thread after AioContext switch job.c | 2 +- tests/test-block-iothread.c | 107 2 files changed, 108 insertions(+), 1 deletion(-) -- 2.20.1
[Qemu-devel] [PATCH 2/2] test-block-iothread: Job coroutine thread after AioContext switch
This tests that a job coroutine always runs in the right iothread after
the AioContext of its main node has changed.
Signed-off-by: Kevin Wolf
---
tests/test-block-iothread.c | 107
1 file changed, 107 insertions(+)
diff --git a/tests/test-block-iothread.c b/tests/test-block-iothread.c
index 97ac0b159d..036ed9a3b3 100644
--- a/tests/test-block-iothread.c
+++ b/tests/test-block-iothread.c
@@ -354,6 +354,111 @@ static void test_sync_op(const void *opaque)
blk_unref(blk);
}
+typedef struct TestBlockJob {
+BlockJob common;
+bool should_complete;
+int n;
+} TestBlockJob;
+
+static int test_job_prepare(Job *job)
+{
+g_assert(qemu_get_current_aio_context() == qemu_get_aio_context());
+return 0;
+}
+
+static int coroutine_fn test_job_run(Job *job, Error **errp)
+{
+TestBlockJob *s = container_of(job, TestBlockJob, common.job);
+
+job_transition_to_ready(&s->common.job);
+while (!s->should_complete) {
+s->n++;
+g_assert(qemu_get_current_aio_context() == job->aio_context);
+
+/* Avoid job_sleep_ns() because it marks the job as !busy. We want to
+ * emulate some actual activity (probably some I/O) here so that the
+ * drain involved in AioContext switches has to wait for this activity
+ * to stop. */
+qemu_co_sleep_ns(QEMU_CLOCK_REALTIME, 100);
+
+job_pause_point(&s->common.job);
+}
+
+g_assert(qemu_get_current_aio_context() == job->aio_context);
+return 0;
+}
+
+static void test_job_complete(Job *job, Error **errp)
+{
+TestBlockJob *s = container_of(job, TestBlockJob, common.job);
+s->should_complete = true;
+}
+
+BlockJobDriver test_job_driver = {
+.job_driver = {
+.instance_size = sizeof(TestBlockJob),
+.free = block_job_free,
+.user_resume= block_job_user_resume,
+.drain = block_job_drain,
+.run= test_job_run,
+.complete = test_job_complete,
+.prepare= test_job_prepare,
+},
+};
+
+static void test_attach_blockjob(void)
+{
+IOThread *iothread = iothread_new();
+AioContext *ctx = iothread_get_aio_context(iothread);
+BlockBackend *blk;
+BlockDriverState *bs;
+TestBlockJob *tjob;
+
+blk = blk_new(BLK_PERM_ALL, BLK_PERM_ALL);
+bs = bdrv_new_open_driver(&bdrv_test, "base", BDRV_O_RDWR, &error_abort);
+blk_insert_bs(blk, bs, &error_abort);
+
+tjob = block_job_create("job0", &test_job_driver, NULL, bs,
+0, BLK_PERM_ALL,
+0, 0, NULL, NULL, &error_abort);
+job_start(&tjob->common.job);
+
+while (tjob->n == 0) {
+aio_poll(qemu_get_aio_context(), false);
+}
+
+blk_set_aio_context(blk, ctx);
+
+tjob->n = 0;
+while (tjob->n == 0) {
+aio_poll(qemu_get_aio_context(), false);
+}
+
+aio_context_acquire(ctx);
+blk_set_aio_context(blk, qemu_get_aio_context());
+aio_context_release(ctx);
+
+tjob->n = 0;
+while (tjob->n == 0) {
+aio_poll(qemu_get_aio_context(), false);
+}
+
+blk_set_aio_context(blk, ctx);
+
+tjob->n = 0;
+while (tjob->n == 0) {
+aio_poll(qemu_get_aio_context(), false);
+}
+
+aio_context_acquire(ctx);
+job_complete_sync(&tjob->common.job, &error_abort);
+blk_set_aio_context(blk, qemu_get_aio_context());
+aio_context_release(ctx);
+
+bdrv_unref(bs);
+blk_unref(blk);
+}
+
int main(int argc, char **argv)
{
int i;
@@ -368,5 +473,7 @@ int main(int argc, char **argv)
g_test_add_data_func(t->name, t, test_sync_op);
}
+g_test_add_func("/attach/blockjob", test_attach_blockjob);
+
return g_test_run();
}
--
2.20.1
[Qemu-devel] [PATCH 0/2] hw/arm/boot: handle large Images more gracefully
This patchset attempts to fix https://bugs.launchpad.net/qemu/+bug/1823998 which reports that we don't handle kernels larger than 128MB correctly, because we allow the initrd to be placed over the tail end of the kernel. AArch64 kernel Image files (since v3.17) report the total size they require (including any BSS area that isn't in the Image itself), so we can use that to be sure we place the initrd sufficiently far into the RAM. Patch 1 in this series adjusts our "where do we put the initrd" heuristic so that it always places it at least after whatever our best guess at the kernel size is. (This might still not be right for images like self-decompressing 32-bit kernels, where there's no way to know how big the kernel will be after decompression.) Patch 2 makes load_aarch64_image() return the kernel size as indicated in the Image file header, so that for the specific case of AArch64 Image files we will definitely not put the initrd on top of them. I've given this a quick smoke test but I don't have a very large Image kernel to hand, so testing appreciated. thanks -- PMM Peter Maydell (2): hw/arm/boot: Avoid placing the initrd on top of the kernel hw/arm/boot: Honour image size field in AArch64 Image format kernels hw/arm/boot.c | 51 +++ 1 file changed, 35 insertions(+), 16 deletions(-) -- 2.20.1
[Qemu-devel] [PATCH v3 2/5] linux-user: Add support for the SIOCSPGRP ioctl
From: Aleksandar Markovic
Add support for setting the process (or process group) to receive SIGIO
or SIGURG signals when I/O becomes possible or urgent data is available,
using SIOCSPGRP ioctl.
The ioctl numeric values for SIOCSPGRP are platform-dependent and are
determined by following files in Linux kernel source tree:
arch/ia64/include/uapi/asm/sockios.h:#define SIOCSPGRP0x8902
arch/mips/include/uapi/asm/sockios.h:#define SIOCSPGRP_IOW('s', 8, pid_t)
arch/parisc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902
arch/sh/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/xtensa/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/alpha/include/uapi/asm/sockios.h:#define SIOCSPGRP _IOW('s', 8, pid_t)
arch/sparc/include/uapi/asm/sockios.h:#define SIOCSPGRP 0x8902
include/uapi/asm-generic/sockios.h:#define SIOCSPGRP 0x8902
Hence the different definition for alpha, mips, sh4, and xtensa.
Reviewed-by: Max Filippov
Signed-off-by: Aleksandar Markovic
---
linux-user/ioctls.h | 1 +
linux-user/syscall_defs.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index ae89516..c37adc5 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -218,6 +218,7 @@
IOCTL(SIOCSRARP, IOC_W, MK_PTR(MK_STRUCT(STRUCT_arpreq)))
IOCTL(SIOCGRARP, IOC_R, MK_PTR(MK_STRUCT(STRUCT_arpreq)))
IOCTL(SIOCGIWNAME, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_char_ifreq)))
+ IOCTL(SIOCSPGRP, IOC_W, MK_PTR(TYPE_INT)) /* pid_t */
IOCTL(SIOCGPGRP, IOC_R, MK_PTR(TYPE_INT)) /* pid_t */
IOCTL(SIOCGSTAMP, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timeval)))
IOCTL(SIOCGSTAMPNS, IOC_R, MK_PTR(MK_STRUCT(STRUCT_timespec)))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 1e86fb9..2941231 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -739,11 +739,14 @@ struct target_pollfd {
#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) ||
\
defined(TARGET_XTENSA)
#define TARGET_SIOCATMARK TARGET_IOR('s', 7, int)
+#define TARGET_SIOCSPGRP TARGET_IOW('s', 8, pid_t)
#define TARGET_SIOCGPGRP TARGET_IOR('s', 9, pid_t)
#else
#define TARGET_SIOCATMARK 0x8905
+#define TARGET_SIOCSPGRP 0x8902
#define TARGET_SIOCGPGRP 0x8904
#endif
+
#define TARGET_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
#define TARGET_SIOCGSTAMPNS0x8907 /* Get stamp (timespec) */
--
2.7.4
Re: [Qemu-devel] [RFC 0/3] target/m68k: convert to transaction_failed hook
On 10/12/2018 17:56, Peter Maydell wrote: This patchset converts the m68k target from the deprecated unassigned_access hook to the new transaction_failed hook. It's RFC for a couple of reasons: * it's untested, since I don't have an m68k test image * the second patch just makes "bus error while trying to read page tables" be treated as a page fault, when it should probably cause a fault reporting it as a bus error of some kind * I don't understand why the old unassigned_access hook set the ATC bit in the MMU SSW, since the docs I have say this should be set if the fault happened during a table search, but cleared if it's just an ordinary bus-errored data or insn access. Probably this is a pre-existing bug? I think you're right. It must be cleared on bus error. Thanks, Laurent
[Qemu-devel] [PATCH 1/2] hw/arm/boot: Avoid placing the initrd on top of the kernel
We currently put the initrd at the smaller of:
* 128MB into RAM
* halfway into the RAM
(with the dtb following it).
However for large kernels this might mean that the kernel
overlaps the initrd. For some kinds of kernel (self-decompressing
32-bit kernels, and ELF images with a BSS section at the end)
we don't know the exact size, but even there we have a
minimum size. Put the initrd at least further into RAM than
that. For image formats that can give us an exact kernel size, this
will mean that we definitely avoid overlaying kernel and initrd.
Signed-off-by: Peter Maydell
---
hw/arm/boot.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index a830655e1af..7c978fedde4 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -998,20 +998,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
if (info->nb_cpus == 0)
info->nb_cpus = 1;
-/*
- * We want to put the initrd far enough into RAM that when the
- * kernel is uncompressed it will not clobber the initrd. However
- * on boards without much RAM we must ensure that we still leave
- * enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
- */
-info->initrd_start = info->loader_start +
-MIN(info->ram_size / 2, 128 * 1024 * 1024);
-
/* Assume that raw images are linux kernels, and ELF images are not. */
kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
&elf_high_addr, elf_machine, as);
@@ -1056,6 +1042,26 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
exit(1);
}
info->entry = entry;
+
+/*
+ * We want to put the initrd far enough into RAM that when the
+ * kernel is uncompressed it will not clobber the initrd. However
+ * on boards without much RAM we must ensure that we still leave
+ * enough room for a decent sized initrd, and on boards with large
+ * amounts of RAM we must avoid the initrd being so far up in RAM
+ * that it is outside lowmem and inaccessible to the kernel.
+ * So for boards with less than 256MB of RAM we put the initrd
+ * halfway into RAM, and for boards with 256MB of RAM or more we put
+ * the initrd at 128MB.
+ * We also refuse to put the initrd somewhere that will definitely
+ * overlay the kernel we just loaded, though for kernel formats which
+ * don't tell us their exact size (eg self-decompressing 32-bit kernels)
+ * we might still make a bad choice here.
+ */
+info->initrd_start = info->loader_start +
+MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size);
+info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
+
if (is_linux) {
uint32_t fixupcontext[FIXUP_MAX];
--
2.20.1
[Qemu-devel] [PATCH v3 3/5] linux-user: Add support the SIOCSIFPFLAGS and SIOCGIFPFLAGS ioctls
From: Neng Chen
Add support for setting and getting extended (private) flags of a
network device via SIOCSIFPFLAGS and SIOCGIFPFLAGS ioctls.
The ioctl numeric value is platform-independent and determined by
the file include/uapi/linux/sockios.h in Linux kernel source code:
#define SIOCSIFPFLAGS 0x8934
The ioctls set and get field ifr_flags of type short in the structure
ifreq. Such functionality in QEMU is achieved using MK_STRUCT() and
MK_PTR() macros with an appropriate argument.
Signed-off-by: Neng Chen
Signed-off-by: Aleksandar Markovic
Message-Id: <1554839486-3527-1-git-send-email-aleksandar.marko...@rt-rk.com>
---
linux-user/ioctls.h | 2 ++
linux-user/syscall_defs.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index c37adc5..76375df 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -206,6 +206,8 @@
IOCTL(SIOCADDMULTI, IOC_W, MK_PTR(MK_STRUCT(STRUCT_sockaddr_ifreq)))
IOCTL(SIOCDELMULTI, IOC_W, MK_PTR(MK_STRUCT(STRUCT_sockaddr_ifreq)))
IOCTL(SIOCGIFINDEX, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_int_ifreq)))
+ IOCTL(SIOCSIFPFLAGS, IOC_W, MK_PTR(MK_STRUCT(STRUCT_short_ifreq)))
+ IOCTL(SIOCGIFPFLAGS, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_short_ifreq)))
IOCTL(SIOCSIFLINK, 0, TYPE_NULL)
IOCTL_SPECIAL(SIOCGIFCONF, IOC_W | IOC_R, do_ioctl_ifconf,
MK_PTR(MK_STRUCT(STRUCT_ifconf)))
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 2941231..8904d35 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -781,6 +781,8 @@ struct target_pollfd {
#define TARGET_SIOCADDMULTI0x8931 /* Multicast address lists
*/
#define TARGET_SIOCDELMULTI0x8932
#define TARGET_SIOCGIFINDEX0x8933
+#define TARGET_SIOCSIFPFLAGS 0x8934 /* set extended flags
*/
+#define TARGET_SIOCGIFPFLAGS 0x8935 /* get extended flags
*/
/* Bridging control calls */
#define TARGET_SIOCGIFBR 0x8940 /* Bridging support
*/
--
2.7.4
[Qemu-devel] [PATCH v3 0/5] linux-user: A set of miscellaneous patches
From: Aleksandar Markovic This is a collection of misc patches for Linux user that I recently accumulated from variuous sources. All of them originate from problems observed on mips target. However, these changes actually affect and fix problems on multiple targets. v1->v2: - updated and improved commit messages - added IPV6_DROP_MEMBERSHIP support to the patch on setsockopt()'s option v1->v2: - added the patch on setsockopt()'s option IPV6_ADD_MEMBERSHIP - improved the commit message of interp_info sanitizing patch Aleksandar Markovic (2): linux-user: Fix support for the SIOCATMARK and SIOCGPGRP ioctls for xtensa linux-user: Add support for the SIOCSPGRP ioctl Daniel Santos (1): linux-user: Sanitize interp_info and, for mips only, init field fp_abi Neng Chen (2): linux-user: Add support the SIOCSIFPFLAGS and SIOCGIFPFLAGS ioctls linux-user: Add support for setsockopt() options IPV6__MEMBERSHIP linux-user/elfload.c | 5 + linux-user/ioctls.h | 3 +++ linux-user/syscall.c | 19 +++ linux-user/syscall_defs.h | 8 +++- 4 files changed, 34 insertions(+), 1 deletion(-) -- 2.7.4
[Qemu-devel] [PATCH v3 5/5] linux-user: Sanitize interp_info and, for mips only, init field fp_abi
From: Daniel Santos Sanitize interp_info structure in load_elf_binary() and, for MIPS only, init its field fp_abi to MIPS_ABI_FP_UNKNOWN. This fixes appearances of "Unexpected FPU mode" message in some MIPS use cases. Currently, this bug is a complete stopper for some MIPS binaries. In load_elf_binary(), struct image_info interp_info is used without being properly initialized. One result is that when the ELF's program header doesn't contain an entry for the ABI flags, then the value of the struct image_info's fp_abi field is set to whatever happened to be in stack memory at the time. Backporting to 4.0 and, if possible, to 3.1 is recommended. Fixes: https://bugs.launchpad.net/qemu/+bug/1825002 Signed-off-by: Daniel Santos Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé --- linux-user/elfload.c | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c1a2602..7f09d57 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2698,6 +2698,11 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) char *elf_interpreter = NULL; char *scratch; +memset(&interp_info, 0, sizeof(interp_info)); +#ifdef TARGET_MIPS +interp_info.fp_abi = MIPS_ABI_FP_UNKNOWN; +#endif + info->start_mmap = (abi_ulong)ELF_START_MMAP; load_elf_image(bprm->filename, bprm->fd, info, -- 2.7.4
Re: [Qemu-devel] [PATCH] tests/tcg/alpha: add system boot.S
Richard Henderson writes: > This provides the bootstrap and low level helper functions for an > alpha kernel. We use direct access to the DP264 serial port for > test output, and hard machine halt to exit the emulation. Queued to testing/next, thanks. I've also added tests/tcg/alpha/system/ to MAINTAINERS > > Signed-off-by: Richard Henderson > --- > tests/tcg/alpha/Makefile.softmmu-target | 32 ++ > tests/tcg/alpha/system/boot.S | 511 > tests/tcg/alpha/system/kernel.ld| 30 ++ > 3 files changed, 573 insertions(+) > create mode 100644 tests/tcg/alpha/Makefile.softmmu-target > create mode 100644 tests/tcg/alpha/system/boot.S > create mode 100644 tests/tcg/alpha/system/kernel.ld > > diff --git a/tests/tcg/alpha/Makefile.softmmu-target > b/tests/tcg/alpha/Makefile.softmmu-target > new file mode 100644 > index 00..9f4b199258 > --- /dev/null > +++ b/tests/tcg/alpha/Makefile.softmmu-target > @@ -0,0 +1,32 @@ > +# > +# Alpha system tests > +# > + > +ALPHA_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/alpha/system > +VPATH+=$(ALPHA_SYSTEM_SRC) > + > +# These objects provide the basic boot code and helper functions for all > tests > +CRT_OBJS=boot.o > + > +ALPHA_TEST_SRCS=$(wildcard $(ALPHA_SYSTEM_SRC)/*.c) > +ALPHA_TESTS = $(patsubst $(ALPHA_SYSTEM_SRC)/%.c, %, $(ALPHA_TEST_SRCS)) > + > +CRT_PATH=$(ALPHA_SYSTEM_SRC) > +LINK_SCRIPT=$(ALPHA_SYSTEM_SRC)/kernel.ld > +LDFLAGS=-Wl,-T$(LINK_SCRIPT) > +TESTS+=$(ALPHA_TESTS) $(MULTIARCH_TESTS) > +CFLAGS+=-nostdlib -g -O1 -mcpu=ev6 $(MINILIB_INC) > +LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc > + > +# building head blobs > +.PRECIOUS: $(CRT_OBJS) > + > +%.o: $(CRT_PATH)/%.S > + $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ > + > +# Build and link the tests > +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) > + $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) > + > +# Running > +QEMU_OPTS+=-serial chardev:output -kernel > diff --git a/tests/tcg/alpha/system/boot.S b/tests/tcg/alpha/system/boot.S > new file mode 100644 > index 00..6d7fb36e17 > --- /dev/null > +++ b/tests/tcg/alpha/system/boot.S > @@ -0,0 +1,511 @@ > +/* > + * Minimal Alpha system boot code. > + * > + * Copyright Linaro Ltd 2019 > + */ > + > + .setnoat > + .setnomacro > + .arch ev6 > + .text > + > +.macro load_pci_io reg > + /* For typhoon, this is > + * 0xfc00 -- kseg identity map > + * + 0x100 -- typhoon pio base > + * +0x1fc00 -- typhoon pchip0 pci base > + * = 0xfd01fc00 > + */ > + ldah\reg, -3/* ff..fd */ > + lda \reg, 0x1fc(\reg) /* ff..fd01fc */ > + sll \reg, 24, \reg > +.endm > + > +#define com1Rbr 0x3f8 > +#define com1Thr 0x3f8 > +#define com1Ier 0x3f9 > +#define com1Iir 0x3fa > +#define com1Lcr 0x3fb > +#define com1Mcr 0x3fc > +#define com1Lsr 0x3fd > +#define com1Msr 0x3fe > +#define com1Scr 0x3ff > +#define com1Dll 0x3f8 > +#define com1Dlm 0x3f9 > + > +#define PAL_halt0 > +#define PAL_wrent 52 > +#define PAL_wrkgp 55 > + > + .text > + .p2align 4 > + .globl _start > + .ent_start > +_start: > + br $gp, .+4 > + ldah$gp, 0($gp) !gpdisp!1 > + lda $gp, 0($gp) !gpdisp!1 > + > + ldah$sp, $stack_end($gp)!gprelhigh > + lda $sp, $stack_end($gp)!gprellow > + > + /* Install kernel gp for exception handlers. */ > + mov $gp, $16 > + call_pal PAL_wrkgp > + > + /* Install exception handlers. */ > + ldah$16, entInt($gp)!gprelhigh > + lda $16, entInt($16)!gprellow > + lda $17, 0 > + call_pal PAL_wrent > + > + ldah$16, entArith($gp) !gprelhigh > + lda $16, entArith($16) !gprellow > + lda $17, 1 > + call_pal PAL_wrent > + > + ldah$16, entMM($gp) !gprelhigh > + lda $16, entMM($16) !gprellow > + lda $17, 2 > + call_pal PAL_wrent > + > + ldah$16, entIF($gp) !gprelhigh > + lda $16, entIF($16) !gprellow > + lda $17, 3 > + call_pal PAL_wrent > + > + ldah$16, entUna($gp)!gprelhigh > + lda $16, entUna($16)!gprellow > + lda $17, 4 > + call_pal PAL_wrent > + > + ldah$16, entSys($gp)!gprelhigh > + lda $16, entSys($16)!gprellow > + lda $17, 5 > + call_pal PAL_wrent > + > + /* > + * Initialize COM1. > + */ > + load_pci_io $1 > + lda $2, 0x87/* outb(0x87, com1Lcr); */ > + stb $2, com1Lcr($1) > + stb $31, com1Dlm($1)/* outb(0, com1Dlm); */ > + lda $2, 3 /* baudconst 3 => 56000 */ > + stb $2, com1Dll($1) /* outb(baudconst, com1Dll); */ > + lda $2, 0x07 > + stb $2, com1Lcr($1) /* outb(0x07, com1Lcr) */
Re: [Qemu-devel] [PULL 19/19] configure: automatically pick python3 is available
On 5/3/19 6:41 PM, Thomas Huth wrote: > On 03/05/2019 02.41, Eduardo Habkost wrote: >> From: Daniel P. Berrangé >> >> Unless overridden via an env var or configure arg, QEMU will only look >> for the 'python' binary in $PATH. This is unhelpful on distros which >> are only shipping Python 3.x (eg Fedora) in their default install as, >> if they comply with PEP 394, the bare 'python' binary won't exist. >> >> This changes configure so that by default it will search for all three >> common python binaries, preferring to find Python 3.x versions. >> >> Signed-off-by: Daniel P. Berrangé >> Message-Id: <20190327170701.23798-1-berra...@redhat.com> >> Signed-off-by: Eduardo Habkost >> --- >> configure | 18 +++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) > > I haven't bisected it, but I think this patch here broke the gitlab-ci tests: > > https://gitlab.com/huth/qemu/-/jobs/206806257 What's the easier way to notice that automatically? The quicker fix I have is Peter setup'ing a GitLab account mirroring his repo:staging branch, and warn him, but that won't scale much. > Seems like the test is now failing when you don't have an UTF-8 locale: > > LANG=C make check-qapi-schema > [...] > TESTtests/qapi-schema/union-base-empty.out > --- /builds/huth/qemu/tests/qapi-schema/unicode-str.err 2019-05-03 > 15:21:39.0 + > +++ -2019-05-03 15:42:01.561762978 + > @@ -1 +1 @@ > -tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name 'é' > +tests/qapi-schema/unicode-str.json:2: 'command' uses invalid name '\xe9' > /builds/huth/qemu/tests/Makefile.include:1105: recipe for target > 'check-tests/qapi-schema/unicode-str.json' failed > make: *** [check-tests/qapi-schema/unicode-str.json] Error 1 > > Any ideas how to fix this? > > Thomas >
[Qemu-devel] [PATCH] net: avoid to use variable length array in net_client_init()
net_client_init() uses a variable length array to store the prefix
of 'ipv6-net' parameter (e.g. if ipv6-net=fec0::0/64, the prefix
is 'fec0::0').
Since the IPv6 prefix can be at most as long as an IPv6 address,
we can use an array with fixed size equals to INET6_ADDRSTRLEN.
Signed-off-by: Stefano Garzarella
---
net/net.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/net.c b/net/net.c
index f3a3c5444c..2e5f27e121 100644
--- a/net/net.c
+++ b/net/net.c
@@ -1118,7 +1118,7 @@ static int net_client_init(QemuOpts *opts, bool
is_netdev, Error **errp)
const char *ip6_net = qemu_opt_get(opts, "ipv6-net");
if (ip6_net) {
-char buf[strlen(ip6_net) + 1];
+char buf[INET6_ADDRSTRLEN];
if (get_str_sep(buf, sizeof(buf), &ip6_net, '/') < 0) {
/* Default 64bit prefix length. */
--
2.20.1
Re: [Qemu-devel] [PATCH v4] hw/virtio/virtio-mmio: Convert DPRINTF to trace and log
LI, BO XUAN writes: > Hi Alex, > > Sorry about that, I am still trying to get familiar with the patch > submission process. Since my patch has been changed from your last review, > I thought it would be safe to not include the r-b tag from last time. Will > take care next time! That's ok. As a general rule as long as you haven't substantially changed a patch it's safe to keep previous r-b tags. You can always mention it in your cover letter if you are unsure. -- Alex Bennée
Re: [Qemu-devel] [PATCH] tests/docker: add ubuntu 18.04
On 5/3/19 6:42 PM, Alex Bennée wrote:
>
> Gerd Hoffmann writes:
>
>> Based on the ubuntu.docker file.
>> Used to reproduce the build failure Peter was seeing.
>> Others might find this useful too ;)
>>
>> Signed-off-by: Gerd Hoffmann
>> ---
>> tests/docker/dockerfiles/ubuntu1804.docker | 57 ++
>> 1 file changed, 57 insertions(+)
>> create mode 100644 tests/docker/dockerfiles/ubuntu1804.docker
>>
>> diff --git a/tests/docker/dockerfiles/ubuntu1804.docker
>> b/tests/docker/dockerfiles/ubuntu1804.docker
>> new file mode 100644
>> index ..2e2900150b09
>> --- /dev/null
>> +++ b/tests/docker/dockerfiles/ubuntu1804.docker
>> @@ -0,0 +1,57 @@
>> +FROM ubuntu:18.04
>> +ENV PACKAGES flex bison \
>> +ccache \
>> +clang \
>> +gcc \
>> +gettext \
>> +git \
>> +glusterfs-common \
>> +libaio-dev \
>> +libattr1-dev \
>> +libbluetooth-dev \
>> +libbrlapi-dev \
>> +libbz2-dev \
>> +libcacard-dev \
>> +libcap-dev \
>> +libcap-ng-dev \
>> +libcurl4-gnutls-dev \
>> +libdrm-dev \
>> +libepoxy-dev \
>> +libfdt-dev \
>> +libgbm-dev \
>> +libgtk-3-dev \
>> +libibverbs-dev \
>> +libiscsi-dev \
>> +libjemalloc-dev \
>> +libjpeg-turbo8-dev \
>> +liblzo2-dev \
>> +libncurses5-dev \
>> +libncursesw5-dev \
>> +libnfs-dev \
>> +libnss3-dev \
>> +libnuma-dev \
>> +libpixman-1-dev \
>> +librados-dev \
>> +librbd-dev \
>> +librdmacm-dev \
>> +libsasl2-dev \
>> +libsdl2-dev \
>> +libseccomp-dev \
>> +libsnappy-dev \
>> +libspice-protocol-dev \
>> +libspice-server-dev \
>> +libssh2-1-dev \
>> +libusb-1.0-0-dev \
>> +libusbredirhost-dev \
>> +libvdeplug-dev \
>> +libvte-2.91-dev \
>> +libxen-dev \
>> +make \
>> +python-yaml \
>> +sparse \
>> +texinfo \
>> +xfslibs-dev
>> +RUN apt-get update && \
>> +apt-get -y install $PACKAGES
>> +RUN dpkg -l $PACKAGES | sort > /packages.txt
>> +ENV FEATURES clang pyyaml sdl2
>
> Queued to testing/next, thanks.
Just finished builds, so if it's not too late:
Tested-by: Philippe Mathieu-Daudé
I'm not sure whichever {ubuntu1804/ubuntu18.04}.docker is better,
anyway:
Reviewed-by: Philippe Mathieu-Daudé
>
> --
> Alex Bennée
>
