Re: [RFC PATCH 1/2] audio/mixeng: Fix Clang 'int-conversion' warning

[Volker Rümelin]

> Fix by using a 64-bit float for the conversion, before casting
> back to 32-bit float.
>
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  audio/mixeng.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/audio/mixeng.c b/audio/mixeng.c
> index 739a500449..9946bfeaec 100644
> --- a/audio/mixeng.c
> +++ b/audio/mixeng.c
> @@ -271,7 +271,7 @@ f_sample *mixeng_clip[2][2][2][3] = {
>  #define CONV_NATURAL_FLOAT(x) (x)
>  #define CLIP_NATURAL_FLOAT(x) (x)
>  #else
> -static const float float_scale = UINT_MAX / 2.f;
> +static const float float_scale = UINT_MAX / 2.;

I would prefer an explicit cast of UINT_MAX to float. This is what we already 
have in audio/mixeng_template.h in the conf_* and clip_* functions with 
FLOAT_MIXENG defined. I think similar functions should look similar.

>  #define CONV_NATURAL_FLOAT(x) ((x) * float_scale)
>  
>  #ifdef RECIPROCAL

Please don't forget to fix the RECIPROCAL case.


Btw. the problem was reported here:
https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg02270.html

With best regards,
Volker

Re: [PATCH 2/2] arm/acpi: Add the TPM2.0 device under the DSDT

[Michael S. Tsirkin]

On Sat, May 02, 2020 at 10:35:36PM +0200, Eric Auger wrote:
> In case it is dynamically instantiated, add the TPM 2.0 device object
> under the DSDT table in the ACPI namespace. Its HID is MSFT0101
> while its current resource settings (CRS) property is initialized
> with the guest physical address and MMIO size of the device.
> 
> Signed-off-by: Eric Auger 
> ---
>  hw/arm/virt-acpi-build.c | 34 ++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index cc5863eaf2..0cb9cdb2ce 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -45,6 +45,7 @@
>  #include "hw/pci/pcie_host.h"
>  #include "hw/pci/pci.h"
>  #include "hw/arm/virt.h"
> +#include "hw/platform-bus.h"
>  #include "sysemu/numa.h"
>  #include "sysemu/reset.h"
>  #include "sysemu/tpm.h"
> @@ -362,6 +363,38 @@ static void acpi_dsdt_add_power_button(Aml *scope)
>  aml_append(scope, dev);
>  }
>  
> +static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
> +{
> +hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
> +PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
> +MemoryRegion *sbdev_mr;
> +SysBusDevice *sbdev;
> +hwaddr tpm_base;
> +
> +sbdev = (SysBusDevice *)object_dynamic_cast(OBJECT(tpm_find()),
> +TYPE_SYS_BUS_DEVICE);
> +if (!sbdev) {
> +return;
> +}
> +
> +tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> +assert(tpm_base != -1);
> +
> +tpm_base += pbus_base;
> +
> +sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
> +
> +Aml *dev = aml_device("TPM0");
> +aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
> +aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> +Aml *crs = aml_resource_template();
> +aml_append(crs,
> +   aml_memory32_fixed(tpm_base, sbdev_mr->size, AML_READ_WRITE));

I don't think you are supposed to poke at memory region struct internals like
this.


> +aml_append(dev, aml_name_decl("_CRS", crs));
> +aml_append(scope, dev);
> +}
> +
>  static void
>  build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>  {
> @@ -785,6 +818,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, 
> VirtMachineState *vms)
>  }
>  
>  acpi_dsdt_add_power_button(scope);
> +acpi_dsdt_add_tpm(scope, vms);
>  
>  aml_append(dsdt, scope);
>  
> -- 
> 2.20.1

Re: [PATCH v4 0/7] ARM virt: Add NVDIMM support

[Michael S. Tsirkin]

On Tue, Apr 21, 2020 at 01:59:27PM +0100, Shameer Kolothum wrote:
> This series adds NVDIMM support to arm/virt platform.
> The series reuses some of the patches posted by Eric
> in his earlier attempt here[1].
> 
> This series previously had few fixes to qemu in general
> which were discovered while adding nvdimm support to arm/virt.
> Those were sent out seperately[2] and are now part of Qemu.


Mostly ACPI stuff so I can merge it if I get an ack for ARM side.

Alternatively, for ACPI things:

Reviewed-by: Michael S. Tsirkin 



> Patch #1 is another fix to the nvdimm aml issue discussed
> here[3].
> 
> I have done a basic sanity testing of NVDIMM devices
> with Guest booting with ACPI. Further testing is always
> welcome.
> 
> Please let me know your feedback.
> 
> Thanks,
> Shameer
> 
> [1] https://patchwork.kernel.org/cover/10830777/
> [2] https://patchwork.kernel.org/cover/11472501/
> [3] https://patchwork.kernel.org/cover/11174959/#23020961
> 
> v3 --> v4
>  -Removed patches #1 to #3 from v3 as they are now part of Qemu.
>  -Addressed comments from Igor(#6) and Shannon(#4).
>  -Added R-by from Igor(#1,#2,#3).
> 
> v2 --> v3
>  - Added patch #1 and # 2 to fix the inconsistency in acpi
>table memory region sizes during migration. Thanks to
>David H.
>  - The fix for qemu_ram_resize() callback was modified to
>the one in patch #3. Again thanks to David H.
>  - Addressed comments from MST and Eric on tests added.
>  - Addressed comments from Igor/MST on Integer size in patch #4
>  - Added Eric's R-by to patch #7.
> 
> v1 --> v2
>  -Reworked patch #1 and now fix is inside qemu_ram_resize().
>  -Added patch #2 to fix the nvdim aml issue.
>  -Dropped support to DT cold plug.
>  -Updated test_acpi_virt_tcg_memhp() with pc-dimm and nvdimms(patch #7)
> 
> Kwangwoo Lee (2):
>   nvdimm: Use configurable ACPI IO base and size
>   hw/arm/virt: Add nvdimm hot-plug infrastructure
> 
> Shameer Kolothum (5):
>   hw/acpi/nvdimm: Fix for NVDIMM incorrect DSM output buffer length
>   hw/arm/virt: Add nvdimm hotplug support
>   tests: Update ACPI tables list for upcoming arm/virt test changes
>   bios-tables-test: test pc-dimm and nvdimm coldplug for arm/virt
>   tests/acpi: add expected tables for bios-tables-test
> 
>  docs/specs/acpi_hw_reduced_hotplug.rst |   3 +-
>  hw/acpi/generic_event_device.c |  15 +-
>  hw/acpi/nvdimm.c   |  72 -
>  hw/arm/Kconfig |   1 +
>  hw/arm/virt-acpi-build.c   |   6 +++
>  hw/arm/virt.c  |  35 ++--
>  hw/i386/acpi-build.c   |   6 +++
>  hw/i386/acpi-build.h   |   3 ++
>  hw/i386/pc_piix.c  |   2 +
>  hw/i386/pc_q35.c   |   2 +
>  hw/mem/Kconfig |   2 +-
>  include/hw/acpi/generic_event_device.h |   1 +
>  include/hw/arm/virt.h  |   1 +
>  include/hw/mem/nvdimm.h|   3 ++
>  tests/data/acpi/pc/SSDT.dimmpxm| Bin 685 -> 734 bytes
>  tests/data/acpi/q35/SSDT.dimmpxm   | Bin 685 -> 734 bytes
>  tests/data/acpi/virt/DSDT.memhp| Bin 6644 -> 6668 bytes
>  tests/data/acpi/virt/NFIT.memhp| Bin 0 -> 224 bytes
>  tests/data/acpi/virt/SSDT.memhp| Bin 0 -> 736 bytes
>  tests/qtest/bios-tables-test.c |   9 +++-
>  20 files changed, 138 insertions(+), 23 deletions(-)
>  create mode 100644 tests/data/acpi/virt/NFIT.memhp
>  create mode 100644 tests/data/acpi/virt/SSDT.memhp
> 
> -- 
> 2.17.1
> 

Re: [PATCH v1 4/4] .travis.yml: reduce the load on [ppc64] GCC check-tcg

[David Gibson]

On Fri, May 01, 2020 at 01:58:47PM +0100, Alex Bennée wrote:
> 
> Philippe Mathieu-Daudé  writes:
> 
> > On 5/1/20 1:15 PM, Alex Bennée wrote:
> >> This seems to be timing out quite often and occasionally running out
> >> of disk space. Relegate it to light duties.
> >> Signed-off-by: Alex Bennée 
> >> ---
> >>   .travis.yml | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >> diff --git a/.travis.yml b/.travis.yml
> >> index 49267b73b3..fe708792ca 100644
> >> --- a/.travis.yml
> >> +++ b/.travis.yml
> >> @@ -458,7 +458,7 @@ jobs:
> >> - genisoimage
> >> env:
> >>   - TEST_CMD="make check check-tcg V=1"
> >> -- CONFIG="--disable-containers 
> >> --target-list=${MAIN_SOFTMMU_TARGETS},ppc64le-linux-user"
> >> +- CONFIG="--disable-containers 
> >> --target-list=ppc64-softmmu,ppc64le-linux-user"
> >
> > Cc'ing David, since I'm not sure about this one... Maybe split as we
> > did with other jobs?
> 
> We could do but it lengthens the run even more. Having
> ppc64le-linux-user ensures we exercise the majority of the TCG code
> generator so I think the only area we aren't covering is the PPC TCG
> softmmu backend. We could add another softmmu target but I didn't want
> to play favourites.

Hrm.  I'd prefer not to drop this coverage if we can avoid it.  What
we're not testing with the proposed patch is TCG generation for a ppc
host but a non-ppc target.  e.g. if the x86 or ARM target side generates
some pattern of TCG ops that's very rare for the ppc target, and is
buggy in the ppc host side.

I'll grant you, bugs that specific aren't particularly likely.  But,
such a regression would also be very unlikely to be caught by ad-hoc
testing, so it would be good to have at least some coverage in Travis.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH qemu] spapr: Add PVR setting capability

[Alexey Kardashevskiy]

On 17/04/2020 14:11, Alexey Kardashevskiy wrote:
> At the moment the VCPU init sequence includes setting PVR which in case of
> KVM-HV only checks if it matches the hardware PVR mask as PVR cannot be
> virtualized by the hardware. In order to cope with various CPU revisions
> only top 16bit of PVR are checked which works for minor revision updates.
> 
> However in every CPU generation starting POWER7 (at least) there were CPUs
> supporting the (almost) same POWER ISA level but having different top
> 16bits of PVR - POWER7+, POWER8E, POWER8NVL; this time we got POWER9+
> with a new PVR family. We would normally add the PVR mask for the new one
> too, the problem with it is that although the physical machines exist,
> P9+ is not going to be released as a product, and this situation is likely
> to repeat in the future.
> 
> Instead of adding every new CPU family in QEMU, this adds a new sPAPR
> machine capability to force PVR setting/checking. It is "on" by default
> to preserve the existing behavior. When "off", it is the user's
> responsibility to specify the correct CPU.

Ping?



> > Signed-off-by: Alexey Kardashevskiy 
> ---
>  include/hw/ppc/spapr.h |  5 -
>  hw/ppc/spapr.c |  1 +
>  hw/ppc/spapr_caps.c| 18 ++
>  target/ppc/kvm.c   | 16 ++--
>  4 files changed, 37 insertions(+), 3 deletions(-)
> 
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index e579eaf28c05..5ccac4d56871 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -81,8 +81,10 @@ typedef enum {
>  #define SPAPR_CAP_CCF_ASSIST0x09
>  /* Implements PAPR FWNMI option */
>  #define SPAPR_CAP_FWNMI 0x0A
> +/* Implements PAPR PVR option */
> +#define SPAPR_CAP_PVR   0x0B
>  /* Num Caps */
> -#define SPAPR_CAP_NUM   (SPAPR_CAP_FWNMI + 1)
> +#define SPAPR_CAP_NUM   (SPAPR_CAP_PVR + 1)
>  
>  /*
>   * Capability Values
> @@ -912,6 +914,7 @@ extern const VMStateDescription 
> vmstate_spapr_cap_nested_kvm_hv;
>  extern const VMStateDescription vmstate_spapr_cap_large_decr;
>  extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
>  extern const VMStateDescription vmstate_spapr_cap_fwnmi;
> +extern const VMStateDescription vmstate_spapr_cap_pvr;
>  
>  static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
>  {
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 841b5ec59b12..ecc74c182b9f 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -4535,6 +4535,7 @@ static void spapr_machine_class_init(ObjectClass *oc, 
> void *data)
>  smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
>  smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
>  smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
> +smc->default_caps.caps[SPAPR_CAP_PVR] = SPAPR_CAP_ON;
>  spapr_caps_add_properties(smc, _abort);
>  smc->irq = _irq_dual;
>  smc->dr_phb_enabled = true;
> diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
> index eb54f9422722..398b72b77f9f 100644
> --- a/hw/ppc/spapr_caps.c
> +++ b/hw/ppc/spapr_caps.c
> @@ -525,6 +525,14 @@ static void cap_fwnmi_apply(SpaprMachineState *spapr, 
> uint8_t val,
>  }
>  }
>  
> +static void cap_pvr_apply(SpaprMachineState *spapr, uint8_t val, Error 
> **errp)
> +{
> +if (val) {
> +return;
> +}
> +warn_report("If you're uing kvm-hv.ko, only \"-cpu host\" is supported");
> +}
> +
>  SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
>  [SPAPR_CAP_HTM] = {
>  .name = "htm",
> @@ -633,6 +641,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
>  .type = "bool",
>  .apply = cap_fwnmi_apply,
>  },
> +[SPAPR_CAP_PVR] = {
> +.name = "pvr",
> +.description = "Enforce PVR in KVM",
> +.index = SPAPR_CAP_PVR,
> +.get = spapr_cap_get_bool,
> +.set = spapr_cap_set_bool,
> +.type = "bool",
> +.apply = cap_pvr_apply,
> +},
>  };
>  
>  static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
> @@ -773,6 +790,7 @@ SPAPR_CAP_MIG_STATE(nested_kvm_hv, 
> SPAPR_CAP_NESTED_KVM_HV);
>  SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
>  SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
>  SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
> +SPAPR_CAP_MIG_STATE(pvr, SPAPR_CAP_PVR);
>  
>  void spapr_caps_init(SpaprMachineState *spapr)
>  {
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 03d0667e8f94..a4adc29b6522 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -466,15 +466,27 @@ int kvm_arch_init_vcpu(CPUState *cs)
>  PowerPCCPU *cpu = POWERPC_CPU(cs);
>  CPUPPCState *cenv = >env;
>  int ret;
> +SpaprMachineState *spapr;
>  
>  /* Synchronize sregs with kvm */
>  ret = kvm_arch_sync_sregs(cpu);
>  if (ret) {
>  if (ret == -EINVAL) {
>  error_report("Register sync 

Re: [PATCH v2 4/5] vhost: check vring address before calling unmap

[Raphael Norwitz]

On Thu, Apr 30, 2020 at 9:50 AM Dima Stepanov  wrote:
>
> Since disconnect can happen at any time during initialization not all
> vring buffers (for instance used vring) can be intialized successfully.
> If the buffer was not initialized then vhost_memory_unmap call will lead
> to SIGSEGV. Add checks for the vring address value before calling unmap.
> Also add assert() in the vhost_memory_unmap() routine.
>
> Signed-off-by: Dima Stepanov 

Reviewed-by: Raphael Norwitz 

> ---
>  hw/virtio/vhost.c | 27 +--
>  1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
> index ddbdc53..3ee50c4 100644
> --- a/hw/virtio/vhost.c
> +++ b/hw/virtio/vhost.c
> @@ -314,6 +314,8 @@ static void vhost_memory_unmap(struct vhost_dev *dev, 
> void *buffer,
> hwaddr len, int is_write,
> hwaddr access_len)
>  {
> +assert(buffer);
> +
>  if (!vhost_dev_has_iommu(dev)) {
>  cpu_physical_memory_unmap(buffer, len, is_write, access_len);
>  }
> @@ -1132,12 +1134,25 @@ static void vhost_virtqueue_stop(struct vhost_dev 
> *dev,
>  vhost_vq_index);
>  }
>
> -vhost_memory_unmap(dev, vq->used, virtio_queue_get_used_size(vdev, idx),
> -   1, virtio_queue_get_used_size(vdev, idx));
> -vhost_memory_unmap(dev, vq->avail, virtio_queue_get_avail_size(vdev, 
> idx),
> -   0, virtio_queue_get_avail_size(vdev, idx));
> -vhost_memory_unmap(dev, vq->desc, virtio_queue_get_desc_size(vdev, idx),
> -   0, virtio_queue_get_desc_size(vdev, idx));
> +/*
> + * Since the vhost-user disconnect can happen during initialization
> + * check if vring was initialized, before making unmap.
> + */
> +if (vq->used) {
> +vhost_memory_unmap(dev, vq->used,
> +   virtio_queue_get_used_size(vdev, idx),
> +   1, virtio_queue_get_used_size(vdev, idx));
> +}
> +if (vq->avail) {
> +vhost_memory_unmap(dev, vq->avail,
> +   virtio_queue_get_avail_size(vdev, idx),
> +   0, virtio_queue_get_avail_size(vdev, idx));
> +}
> +if (vq->desc) {
> +vhost_memory_unmap(dev, vq->desc,
> +   virtio_queue_get_desc_size(vdev, idx),
> +   0, virtio_queue_get_desc_size(vdev, idx));
> +}
>  }
>
>  static void vhost_eventfd_add(MemoryListener *listener,
> --
> 2.7.4
>
>

Re: [PATCH v2 3/5] vhost-user-blk: add mechanism to track the guest notifiers init state

[Raphael Norwitz]

Apologies for mixing up patches last time. This looks good from a
vhost-user-blk perspective, but I worry that some of these changes
could impact other vhost device types.

I agree with adding notifiers_set to struct vhost_dev, and setting it in
vhost_dev_enable/disable notifiers, but is there any reason notifiers_set
can’t be checked inside vhost-user-blk?

On Thu, Apr 30, 2020 at 9:55 AM Dima Stepanov  wrote:
>
> In case of the vhost-user devices the daemon can be killed at any
> moment. Since QEMU supports the reconnet functionality the guest
> notifiers should be reset and disabled after "disconnect" event. The
> most issues were found if the "disconnect" event happened during vhost
> device initialization step.
> The disconnect event leads to the call of the vhost_dev_cleanup()
> routine. Which memset to 0 a vhost device structure. Because of this, if
> device was not started (dev.started == false) and the connection is
> broken, then the set_guest_notifier method will produce assertion error.
> Also connection can be broken after the dev.started field is set to
> true.
> A new notifiers_set field is added to the vhost_dev structure to track
> the state of the guest notifiers during the initialization process.
>

>From what I can tell this patch does two things:

(1)
In vhost.c you’re adding checks to abort early, while still returning
successfully, from
vhost_dev_drop_guest_notifiers() and vhost_dev_disable_notifiers() if
notifiers have
not been enabled. This new logic will affect all existing vhost devices.

(2)
For vhost-user-blk backend disconnect, you are ensuring that notifiers
are dropped and
disabled if and only if the notifiers are currently enabled.

I completely agree with (2), but I don't think we need all of what
you've done for
(1) to accomplish (2).

Either way, please clarify in your commit message.

> Signed-off-by: Dima Stepanov 
> ---
>  hw/block/vhost-user-blk.c |  8 
>  hw/virtio/vhost.c | 11 +++
>  include/hw/virtio/vhost.h |  1 +
>  3 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c
> index 70d7842..5a3de0f 100644
> --- a/hw/block/vhost-user-blk.c
> +++ b/hw/block/vhost-user-blk.c
> @@ -175,7 +175,9 @@ static void vhost_user_blk_stop(VirtIODevice *vdev)
>  return;
>  }
>
> -vhost_dev_stop(>dev, vdev);
> +if (s->dev.started) {
> +vhost_dev_stop(>dev, vdev);
> +}
>

Couldn't we check if s->dev.notifiers_set here before calling
vhost_dev_drop_guest_notifiers()?

>  ret = vhost_dev_drop_guest_notifiers(>dev, vdev, s->dev.nvqs);
>  if (ret < 0) {
> @@ -337,9 +339,7 @@ static void vhost_user_blk_disconnect(DeviceState *dev)
>  }
>  s->connected = false;
>
> -if (s->dev.started) {
> -vhost_user_blk_stop(vdev);
> -}
> +vhost_user_blk_stop(vdev);
>
>  vhost_dev_cleanup(>dev);
>  }
> diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
> index fa3da9c..ddbdc53 100644
> --- a/hw/virtio/vhost.c
> +++ b/hw/virtio/vhost.c
> @@ -1380,6 +1380,7 @@ int vhost_dev_enable_notifiers(struct vhost_dev *hdev, 
> VirtIODevice *vdev)
>  goto fail_vq;
>  }
>  }
> +hdev->notifiers_set = true;
>
>  return 0;
>  fail_vq:
> @@ -1407,6 +1408,10 @@ void vhost_dev_disable_notifiers(struct vhost_dev 
> *hdev, VirtIODevice *vdev)
>  BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
>  int i, r;
>

I’m a little weary of short circuiting logic like this without at
least propagating an
error up. Couldn’t we leave it to the backends to check notifiers_set
before they
call vhost_dev_disable_notifiers() or vhost_dev_drop_guest_notifiers()?

Then, if anything, maybe make this check an assert?

> +if (!hdev->notifiers_set) {
> +return;
> +}
> +
>  for (i = 0; i < hdev->nvqs; ++i) {
>  r = virtio_bus_set_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + 
> i,
>   false);
> @@ -1417,6 +1422,8 @@ void vhost_dev_disable_notifiers(struct vhost_dev 
> *hdev, VirtIODevice *vdev)
>  virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), hdev->vq_index + 
> i);
>  }
>  virtio_device_release_ioeventfd(vdev);
> +
> +hdev->notifiers_set = false;
>  }
>
>  /*
> @@ -1449,6 +1456,10 @@ int vhost_dev_drop_guest_notifiers(struct vhost_dev 
> *hdev,
>  VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
>  int ret;
>

Same comment as above - I’d prefer vhost-user-blk (and other backends
supporting reconnect)
check before calling the function instead of changing existing API
behavior for other vhost devices.

> +if (!hdev->notifiers_set) {
> +return 0;
> +}
> +
>  ret = k->set_guest_notifiers(qbus->parent, nvqs, false);
>  if (ret < 0) {
>  error_report("Error reset guest notifier: %d", -ret);
> diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
> index 4d0d2e2..e3711a7 100644
> --- 

Re: An first try to improve PPC float simulation, not even compiled. Just ask question.

[Yonggang Luo]

On Mon, May 4, 2020 at 7:40 AM BALATON Zoltan  wrote:

> Hello,
>
> On Mon, 4 May 2020, 罗勇刚(Yonggang Luo) wrote:
> > Hello Richard, Can you have a look at the following patch, and was that
> are
> > the right direction?
>
> Formatting of the patch is broken by your mailer, try sending it with
> something that does not change it otherwise it's a bit hard to read.
>
> Richard suggested to add an assert to check the fp_status is correctly
> cleared in place of helper_reset_fpstatus first for debugging so you could
> change the helper accordingly before deleting it and run a few tests to
> verify it still works. You'll need get some tests and benchmarks working
> to be able to verify your changes that's why I've said that would be step
> 0. If you checked that it still produces the same results and the assert
> does not trigger then you can remove the helper.
>
That's what I need help,
1. How to write a assert to replace helper_reset_fpstatus .
  just directly assert? or something else
2.  a few tests to run
 How to running these tests, and where are these tests.
Do I need to add new tests? Where to start
3.  Benchmarks
Same as 2

>
> Regards,
> BALATON Zoltan
>
> > From b4d6ca1d6376fab1f1be06eb472e10b908887c2b Mon Sep 17 00:00:00 2001
> > From: Yonggang Luo 
> > Date: Sat, 2 May 2020 05:59:25 +0800
> > Subject: [PATCH] [ppc fp] Step 1. Rearrange the fp helpers to eliminate
> > helper_reset_fpstatus(). I've mentioned this before, that it's possible
> to
> > leave the steady-state of env->fp_status.exception_flags == 0, so there's
> > no
> > need for a separate function call.  I suspect this is worth a decent
> > speedup
> > by itself.
> >
> > ---
> > target/ppc/fpu_helper.c| 53 ++
> > target/ppc/helper.h|  1 -
> > target/ppc/translate/fp-impl.inc.c | 23 -
> > 3 files changed, 3 insertions(+), 74 deletions(-)
> >
> > diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> > index d9a8773ee1..4fc5a7ff1c 100644
> > --- a/target/ppc/fpu_helper.c
> > +++ b/target/ppc/fpu_helper.c
> > @@ -821,6 +821,9 @@ static void do_float_check_status(CPUPPCState *env,
> > uintptr_t raddr)
> >env->error_code, raddr);
> > }
> > }
> > +if (status) {
> > +set_float_exception_flags(0, >fp_status);
> > +}
> > }
> >
> > void helper_float_check_status(CPUPPCState *env)
> > @@ -828,11 +831,6 @@ void helper_float_check_status(CPUPPCState *env)
> > do_float_check_status(env, GETPC());
> > }
> >
> > -void helper_reset_fpstatus(CPUPPCState *env)
> > -{
> > -set_float_exception_flags(0, >fp_status);
> > -}
> > -
> > static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
> > uintptr_t retaddr, int classes)
> > {
> > @@ -2110,9 +2108,6 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt,
> >   \
> > {
> >   \
> > ppc_vsr_t t = *xt;
> >  \
> > int i;
> >  \
> > -
> >  \
> > -helper_reset_fpstatus(env);
> >   \
> > -
> >  \
> > for (i = 0; i < nels; i++) {
> >  \
> > float_status tstat = env->fp_status;
> >  \
> > set_float_exception_flags(0, );
> >   \
> > @@ -2152,8 +2147,6 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t
> opcode,
> > ppc_vsr_t t = *xt;
> > float_status tstat;
> >
> > -helper_reset_fpstatus(env);
> > -
> > tstat = env->fp_status;
> > if (unlikely(Rc(opcode) != 0)) {
> > tstat.float_rounding_mode = float_round_to_odd;
> > @@ -2189,9 +2182,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
> >   \
> > {
> >   \
> > ppc_vsr_t t = *xt;
> >  \
> > int i;
> >  \
> > -
> >  \
> > -helper_reset_fpstatus(env);
> >   \
> > -
> >  \
> > for (i = 0; i < nels; i++) {
> >  \
> > float_status tstat = env->fp_status;
> >  \
> > set_float_exception_flags(0, );
> >   \
> > @@ -2228,13 +2218,11 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t
> > opcode,
> > ppc_vsr_t t = *xt;
> > float_status tstat;
> >
> > -helper_reset_fpstatus(env);
> > tstat = env->fp_status;
> > if (unlikely(Rc(opcode) != 0)) {
> > tstat.float_rounding_mode = float_round_to_odd;
> > }
> >
> > -set_float_exception_flags(0, );
> > t.f128 = float128_mul(xa->f128, xb->f128, );
> > env->fp_status.float_exception_flags |= tstat.float_exception_flags;
> >
> > @@ -2263,9 +2251,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
> >\
> > {
> >\
> > ppc_vsr_t t = *xt;
> >   \
> > int i;
> >   \
> > -
> >   \
> > -helper_reset_fpstatus(env);
> >\
> > -
> >   \
> > for (i = 0; i < nels; i++) {
> >   \
> > float_status tstat = env->fp_status;
> >   \
> > set_float_exception_flags(0, );
> >\
> > @@ -2305,7 +2290,6 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t
> opcode,
> > ppc_vsr_t t = *xt;
> > float_status tstat;
> >
> > -

Re: [PATCH v2 2/5] vhost: introduce wrappers to set guest notifiers for virtio device

[Raphael Norwitz]

I’m happy from the vhost, vhost-user-blk and vhost-user-scsi side. For
other device types it looks pretty straightforward, but their maintainers
should probably confirm.

Since you plan to change the behavior of these helpers in subsequent
patches, maybe consider sending the other device types separately
after the rest of the series has been merged? That way the changes to
individual devices will be much easier to review.

On Thu, Apr 30, 2020 at 9:48 AM Dima Stepanov  wrote:
>
> Introduce new wrappers to set/reset guest notifiers for the virtio
> device in the vhost device module:
>   vhost_dev_assign_guest_notifiers
> ->set_guest_notifiers(..., ..., true);
>   vhost_dev_drop_guest_notifiers
> ->set_guest_notifiers(..., ..., false);
> This is a preliminary step to refactor code, so the set_guest_notifiers
> methods could be called based on the vhost device state.
> Update all vhost used devices to use these wrappers instead of direct
> method call.
>
> Signed-off-by: Dima Stepanov 
> ---
>  backends/cryptodev-vhost.c  | 26 +++---
>  backends/vhost-user.c   | 16 +---
>  hw/block/vhost-user-blk.c   | 15 +--
>  hw/net/vhost_net.c  | 30 +-
>  hw/scsi/vhost-scsi-common.c | 15 +--
>  hw/virtio/vhost-user-fs.c   | 17 +++--
>  hw/virtio/vhost-vsock.c | 18 --
>  hw/virtio/vhost.c   | 38 ++
>  hw/virtio/virtio.c  | 13 +
>  include/hw/virtio/vhost.h   |  4 
>  include/hw/virtio/virtio.h  |  1 +
>  11 files changed, 118 insertions(+), 75 deletions(-)
>

Re: An first try to improve PPC float simulation, not even compiled. Just ask question.

[BALATON Zoltan]

Hello,

On Mon, 4 May 2020, 罗勇刚(Yonggang Luo) wrote:

Hello Richard, Can you have a look at the following patch, and was that are
the right direction?


Formatting of the patch is broken by your mailer, try sending it with 
something that does not change it otherwise it's a bit hard to read.


Richard suggested to add an assert to check the fp_status is correctly 
cleared in place of helper_reset_fpstatus first for debugging so you could 
change the helper accordingly before deleting it and run a few tests to 
verify it still works. You'll need get some tests and benchmarks working 
to be able to verify your changes that's why I've said that would be step 
0. If you checked that it still produces the same results and the assert 
does not trigger then you can remove the helper.


Regards,
BALATON Zoltan


From b4d6ca1d6376fab1f1be06eb472e10b908887c2b Mon Sep 17 00:00:00 2001
From: Yonggang Luo 
Date: Sat, 2 May 2020 05:59:25 +0800
Subject: [PATCH] [ppc fp] Step 1. Rearrange the fp helpers to eliminate
helper_reset_fpstatus(). I've mentioned this before, that it's possible to
leave the steady-state of env->fp_status.exception_flags == 0, so there's
no
need for a separate function call.  I suspect this is worth a decent
speedup
by itself.

---
target/ppc/fpu_helper.c| 53 ++
target/ppc/helper.h|  1 -
target/ppc/translate/fp-impl.inc.c | 23 -
3 files changed, 3 insertions(+), 74 deletions(-)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d9a8773ee1..4fc5a7ff1c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -821,6 +821,9 @@ static void do_float_check_status(CPUPPCState *env,
uintptr_t raddr)
   env->error_code, raddr);
}
}
+if (status) {
+set_float_exception_flags(0, >fp_status);
+}
}

void helper_float_check_status(CPUPPCState *env)
@@ -828,11 +831,6 @@ void helper_float_check_status(CPUPPCState *env)
do_float_check_status(env, GETPC());
}

-void helper_reset_fpstatus(CPUPPCState *env)
-{
-set_float_exception_flags(0, >fp_status);
-}
-
static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
uintptr_t retaddr, int classes)
{
@@ -2110,9 +2108,6 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt,
  \
{
  \
ppc_vsr_t t = *xt;
 \
int i;
 \
-
 \
-helper_reset_fpstatus(env);
  \
-
 \
for (i = 0; i < nels; i++) {
 \
float_status tstat = env->fp_status;
 \
set_float_exception_flags(0, );
  \
@@ -2152,8 +2147,6 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t t = *xt;
float_status tstat;

-helper_reset_fpstatus(env);
-
tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
tstat.float_rounding_mode = float_round_to_odd;
@@ -2189,9 +2182,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
  \
{
  \
ppc_vsr_t t = *xt;
 \
int i;
 \
-
 \
-helper_reset_fpstatus(env);
  \
-
 \
for (i = 0; i < nels; i++) {
 \
float_status tstat = env->fp_status;
 \
set_float_exception_flags(0, );
  \
@@ -2228,13 +2218,11 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t
opcode,
ppc_vsr_t t = *xt;
float_status tstat;

-helper_reset_fpstatus(env);
tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
tstat.float_rounding_mode = float_round_to_odd;
}

-set_float_exception_flags(0, );
t.f128 = float128_mul(xa->f128, xb->f128, );
env->fp_status.float_exception_flags |= tstat.float_exception_flags;

@@ -2263,9 +2251,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
   \
{
   \
ppc_vsr_t t = *xt;
  \
int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
for (i = 0; i < nels; i++) {
  \
float_status tstat = env->fp_status;
  \
set_float_exception_flags(0, );
   \
@@ -2305,7 +2290,6 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t t = *xt;
float_status tstat;

-helper_reset_fpstatus(env);
tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
tstat.float_rounding_mode = float_round_to_odd;
@@ -2342,9 +2326,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb)  \
{
   \
ppc_vsr_t t = *xt;
  \
int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
for (i = 0; i < nels; i++) {
  \
if (unlikely(tp##_is_signaling_nan(xb->fld, >fp_status))) {
  \
float_invalid_op_vxsnan(env, GETPC());
  \
@@ -2382,9 +2363,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb) \
{
  \
ppc_vsr_t t = *xt;
 \
int i;
 \
-
 \
-helper_reset_fpstatus(env);
  \
-
 \
for (i = 0; i < nels; i++) {
 \
float_status tstat = env->fp_status;
 \
set_float_exception_flags(0, );
  \
@@ -2430,9 +2408,6 @@ void helper_##op(CPUPPCState 

Re: Configuring onboard devices

[Mark Cave-Ayland]

On 02/05/2020 06:47, Markus Armbruster wrote:

> Mark Cave-Ayland  writes:
> 
>> On 30/04/2020 16:20, Markus Armbruster wrote:
>>
 Ah I see now, these aliases are for individual properties rather than 
 objects. What I
 was trying to ask was if it were possible to have something like this:

 /machine (SS-5-machine)
   /builtin
 /nic0 -> link to "lance" device

 Here nic0 is an alias "published" by the maintainer of the SS-5 machine 
 which is
 configured in the machine init() function using object_property_add_link() 
 or a
 suitable wrapper. Users can then configure these builtin devices from the 
 command
 line using your -machine nic0.netdev=my-netdev-id syntax or similar.
>>>
>>> Got it now, thanks!
>>>
 Having the default devices under /builtin or other known QOM path would 
 enable
 builtin devices to be easily enumerated programatically and/or from the 
 command line
 as required.
>>>
>>> There are three standard containers under /machine/:
>>>
>>> * /machine/peripheral/
>>>
>>>   Devices with a user-specified ID go here, as /machine/peripheral/ID.
>>>   User-specified means -device or device_add.
>>>
>>>   /machine/peripheral/ID is effectively a stable interface.  It's just
>>>   underdocumented (undocumented?).
>>>
>>>   To be useful, the stuff below ID/ needed to be stable and documented,
>>>   too.
>>>
>>> * /machine/peripheral-anon/
>>>
>>>   Same, but user elected not to give an ID.
>>>   /machine/peripheral-anon/device[N], where N counts up from zero in
>>>   creation order.
>>>
>>>   N is obviously not stable, but this is a problem of the user's making.
>>>   If you want to refer to a device, give it an ID.
>>>
>>> * /machine/unattached/
>>>
>>>   The orphanage.  When a device has no parent when its realized, it gets
>>>   put here, as /machine/unattached/device[N], where N counts up from
>>>   zero in realization order.
>>>
>>>   N is obviously not stable, and this time we can't blame the
>>>   victim^Wuser.  You can search for devices of a certain type.
>>>   Sometimes that's good enough.
>>>
>>>   All the onboard devices are here, and much more.  We've fathered a lot
>>>   of unloved red-headed children, it seems...
>>>
>>>   Some of the "much more" is due to sloppy modelling, i.e. neglecting to
>>>   set the proper parent.
>>>
>>>   I figure we could put onboard devices in a nicer place, with nicer
>>>   names.  Need a convention for the place and the names, then make board
>>>   code conform to it.
>>
>> That's good, it seems that this is already fairly close to how it works for 
>> -device
>> at the moment.
>>
>> I don't think that it is possible to come up a single place for on-board 
>> devices to
>> live directly though. Going back to one of my first examples: wiring up a 
>> chardev to
>> a serial port on the macio device. To me it makes sense for that to exist in 
>> QOM
>> under /machine/pci-bus/mac-io/escc. In contrast an in-built NIC could live 
>> under
>> /machine/pci-bus/in-built/nic, and placing one or both of these devices 
>> directly
>> under /machine/foo doesn't feel intuitive.
> 
> I'm not familiar with this machine.  You make me suspect the serial
> thingy is a component of a larger device.
> 
> Properly modelled, a composite device has its components as children.
> These appear below their parent in the QOM composition tree.
> 
> Example: a "serial-isa" device has a "serial" component.  When the
> former is at /machine/unattached/device[28]/, the latter is at
> /machine/unattached/device[28]/serial/.
> 
> I guess that's what you want for macio's serial port.
> 
> Counter-example: a "isa-super-io" device has compoenents of type
> "isa-parallel", "isa-serial", "isa-fdc", "i8042", "isa-ide".
> Nevertheless, these appear next to their parent in /machine/unattached/.
> I'm still too much of a QOM ignoramus to explain why that's so.  Paolo,
> can you?

FWIW the older machines have a lot of calls to qdev_create(NULL, TYPE_FOO) for
devices that are part of the machine because they live within the machine 
address
space but are not specifically attached to a qbus.

>> AFAIK as per your ARM virt example I believe it is only possible to register 
>> an alias
>> for a property rather than for an Object? The ultimate aim would be for
>> object_resolve_path("/machine/builtin/nic0") and
>> object_resolve_path("/machine/pci-bus/in-built/nic") to return the same 
>> Object, and
>> for the aliases on built-in devices to be children of /machine/builtin to 
>> allow easy
>> iteration and introspection.
> 
> Paolo, could link properties achieve that?
> 
> Mark, I guess you want the alias / link from builtin/nic0 to the actual
> place to simplify configuration: the user then needs to know less about
> the board.  Correct?

Correct. In a perfect world I'd love to say that Daniel's suggestion to use QOM 
paths
would work, however from my experience they change far too much. This is one of 
the
reasons that 

Re: target/mips: Enable Hardware page table walker and CMGCR features for P5600

[Aleksandar Markovic]

субота, 25. април 2020.,  је написао/ла:

> Hi,
> I have discovered that MIPS hardware page table walker is not enabled
> for any CPU currently available. In this patch I have enable it (and
> also CMGCR feature) for P5600 which supports both but they are not
> enabled.
>
>
Andrea,

Just wanted to tell you that I didn't forget this patch, I was just swamped
with other tasks for last several weeks. I'll get back to you soon.

I appreciate your submitting this patch!

Aleksandar


> This is my first patch to QEMU, I hope it is well formatted and correct.
>
> Signed-off-by: Andrea Oliveri 
> diff --git a/target/mips/translate_init.inc.c
> b/target/mips/translate_init.inc.c
> index 6d145a905a..482cfe2123 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -366,7 +366,7 @@ const mips_def_t mips_defs[] =
>  },
>  {
>  /* FIXME:
> - * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
> + * Config3: VZ, CTXTC, CDMM, TL
>   * Config4: MMUExtDef
>   * Config5: MRP
>   * FIR(FCR0): Has2008
> @@ -380,10 +380,11 @@ const mips_def_t mips_defs[] =
> (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 <<
> CP0C1_DA) |
> (1 << CP0C1_PC) | (1 << CP0C1_FP),
>  .CP0_Config2 = MIPS_CONFIG2,
> -.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP)
> |
> +.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
> +   (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
> (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 <<
> CP0C3_SC) |
> -   (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 <<
> CP0C3_LPA) |
> -   (1 << CP0C3_VInt),
> +   (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 <<
> CP0C3_RXI) |
> +   (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
>  .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
> (0x1c << CP0C4_KScrExist),
>  .CP0_Config4_rw_bitmask = 0,
>
>

Re: An first try to improve PPC float simulation, not even compiled. Just ask question.

[Yonggang Luo]

Hello Richard, Can you have a look at the following patch, and was that are
the right direction?
>From b4d6ca1d6376fab1f1be06eb472e10b908887c2b Mon Sep 17 00:00:00 2001
From: Yonggang Luo 
Date: Sat, 2 May 2020 05:59:25 +0800
Subject: [PATCH] [ppc fp] Step 1. Rearrange the fp helpers to eliminate
 helper_reset_fpstatus(). I've mentioned this before, that it's possible to
 leave the steady-state of env->fp_status.exception_flags == 0, so there's
no
 need for a separate function call.  I suspect this is worth a decent
speedup
 by itself.

---
 target/ppc/fpu_helper.c| 53 ++
 target/ppc/helper.h|  1 -
 target/ppc/translate/fp-impl.inc.c | 23 -
 3 files changed, 3 insertions(+), 74 deletions(-)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d9a8773ee1..4fc5a7ff1c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -821,6 +821,9 @@ static void do_float_check_status(CPUPPCState *env,
uintptr_t raddr)
env->error_code, raddr);
 }
 }
+if (status) {
+set_float_exception_flags(0, >fp_status);
+}
 }

 void helper_float_check_status(CPUPPCState *env)
@@ -828,11 +831,6 @@ void helper_float_check_status(CPUPPCState *env)
 do_float_check_status(env, GETPC());
 }

-void helper_reset_fpstatus(CPUPPCState *env)
-{
-set_float_exception_flags(0, >fp_status);
-}
-
 static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
 uintptr_t retaddr, int classes)
 {
@@ -2110,9 +2108,6 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt,
   \
 {
   \
 ppc_vsr_t t = *xt;
  \
 int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
 for (i = 0; i < nels; i++) {
  \
 float_status tstat = env->fp_status;
  \
 set_float_exception_flags(0, );
   \
@@ -2152,8 +2147,6 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
 ppc_vsr_t t = *xt;
 float_status tstat;

-helper_reset_fpstatus(env);
-
 tstat = env->fp_status;
 if (unlikely(Rc(opcode) != 0)) {
 tstat.float_rounding_mode = float_round_to_odd;
@@ -2189,9 +2182,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
   \
 {
   \
 ppc_vsr_t t = *xt;
  \
 int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
 for (i = 0; i < nels; i++) {
  \
 float_status tstat = env->fp_status;
  \
 set_float_exception_flags(0, );
   \
@@ -2228,13 +2218,11 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t
opcode,
 ppc_vsr_t t = *xt;
 float_status tstat;

-helper_reset_fpstatus(env);
 tstat = env->fp_status;
 if (unlikely(Rc(opcode) != 0)) {
 tstat.float_rounding_mode = float_round_to_odd;
 }

-set_float_exception_flags(0, );
 t.f128 = float128_mul(xa->f128, xb->f128, );
 env->fp_status.float_exception_flags |= tstat.float_exception_flags;

@@ -2263,9 +2251,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
\
 {
\
 ppc_vsr_t t = *xt;
   \
 int i;
   \
-
   \
-helper_reset_fpstatus(env);
\
-
   \
 for (i = 0; i < nels; i++) {
   \
 float_status tstat = env->fp_status;
   \
 set_float_exception_flags(0, );
\
@@ -2305,7 +2290,6 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
 ppc_vsr_t t = *xt;
 float_status tstat;

-helper_reset_fpstatus(env);
 tstat = env->fp_status;
 if (unlikely(Rc(opcode) != 0)) {
 tstat.float_rounding_mode = float_round_to_odd;
@@ -2342,9 +2326,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb)  \
 {
\
 ppc_vsr_t t = *xt;
   \
 int i;
   \
-
   \
-helper_reset_fpstatus(env);
\
-
   \
 for (i = 0; i < nels; i++) {
   \
 if (unlikely(tp##_is_signaling_nan(xb->fld, >fp_status))) {
   \
 float_invalid_op_vxsnan(env, GETPC());
   \
@@ -2382,9 +2363,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb) \
 {
   \
 ppc_vsr_t t = *xt;
  \
 int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
 for (i = 0; i < nels; i++) {
  \
 float_status tstat = env->fp_status;
  \
 set_float_exception_flags(0, );
   \
@@ -2430,9 +2408,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb) \
 {
   \
 ppc_vsr_t t = *xt;
  \
 int i;
  \
-
  \
-helper_reset_fpstatus(env);
   \
-
  \
 for (i = 0; i < nels; i++) {
  \
 float_status tstat = env->fp_status;
  \
 set_float_exception_flags(0, );
   \
@@ -2592,9 +2567,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
\
 {
\
 ppc_vsr_t t = *xt;
   \
 int i;
   \
-
   \
-helper_reset_fpstatus(env);
\
-
   \
 for (i = 0; i < nels; i++) {
   \
 float_status tstat = env->fp_status;
   \
 

Re: [PATCH v3 00/14] LUKS: encryption slot management using amend interface

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20200503184324.12506-1-mlevi...@redhat.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200503184324.12506-1-mlevi...@redhat.com
Subject: [PATCH v3 00/14] LUKS: encryption slot management using amend interface
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
5d8eee3 iotests: add tests for blockdev-amend
73b4eb1 block/qcow2: implement blockdev-amend
b636b4e block/crypto: implement blockdev-amend
989ac21 block/core: add generic infrastructure for x-blockdev-amend qmp command
905e766 iotests: qemu-img tests for luks key management
63c741f iotests: filter few more luks specific create options
7f3246a block/qcow2: extend qemu-img amend interface with crypto options
2e71af1 block/crypto: implement the encryption key management
e23e157 block/crypto: rename two functions
1d744a7 block/amend: refactor qcow2 amend options
9dfeafe block/amend: separate amend and create options for qemu-img
6abf4af block/amend: add 'force' option
70e39d2 qcrypto/luks: implement encryption key management
3e1975e qcrypto/core: add generic infrastructure for crypto options amendment

=== OUTPUT BEGIN ===
1/14 Checking commit 3e1975eea93f (qcrypto/core: add generic infrastructure for 
crypto options amendment)
2/14 Checking commit 70e39d22b302 (qcrypto/luks: implement encryption key 
management)
3/14 Checking commit 6abf4afc9174 (block/amend: add 'force' option)
4/14 Checking commit 9dfeafe0f584 (block/amend: separate amend and create 
options for qemu-img)
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#31: FILE: block/qcow2.c:5498:
+#define QCOW_COMMON_OPTIONS \
+{   \
+.name = BLOCK_OPT_SIZE, \
+.type = QEMU_OPT_SIZE,  \
+.help = "Virtual disk size" \
+},  \
+{   \
+.name = BLOCK_OPT_COMPAT_LEVEL, \
+.type = QEMU_OPT_STRING,\
+.help = "Compatibility level (v2 [0.10] or v3 [1.1])"   \
+},  \
+{   \
+.name = BLOCK_OPT_BACKING_FILE, \
+.type = QEMU_OPT_STRING,\
+.help = "File name of a base image" \
+},  \
+{   \
+.name = BLOCK_OPT_BACKING_FMT,  \
+.type = QEMU_OPT_STRING,\
+.help = "Image format of the base image"\
+},  \
+{   \
+.name = BLOCK_OPT_DATA_FILE,\
+.type = QEMU_OPT_STRING,\
+.help = "File name of an external data file"\
+},  \
+{   \
+.name = BLOCK_OPT_DATA_FILE_RAW,\
+.type = QEMU_OPT_BOOL,  \
+.help = "The external data file must stay valid "   \
+"as a raw image"\
+},  \
+{   \
+.name = BLOCK_OPT_ENCRYPT,  \
+.type = QEMU_OPT_BOOL,  \
+.help = "Encrypt the image with format 'aes'. (Deprecated " \
+"in favor of " BLOCK_OPT_ENCRYPT_FORMAT "=aes)",\
+},  \
+{   \
+.name = BLOCK_OPT_ENCRYPT_FORMAT,   \
+.type = QEMU_OPT_STRING,\
+.help = "Encrypt the image, format choices: 'aes', 'luks'", \
+},

Re: [RFC PATCH 2/2] linux-user/mmap: Fix Clang 'type-limit-compare' warning

[Aleksandar Markovic]

> +#if TARGET_ABI_BITS < TARGET_LONG_BITS
>  /* Check if address fits target address space */
>  if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {

It would be clearer if "#if  TARGET_LONG_BITS > TARGET_ABI_BITS"
is used, to match the comparison in if() statement.

>  /* Revert mremap() changes */
> @@ -721,6 +722,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
> old_size,
>  errno = ENOMEM;
>  host_addr = MAP_FAILED;
>  }
> +#endif /* TARGET_ABI_BITS < TARGET_LONG_BITS */
>  }
>
>  if (host_addr == MAP_FAILED) {
> --
> 2.21.3
>
>

[PATCH v3 14/14] iotests: add tests for blockdev-amend

[Maxim Levitsky]

This commit adds two tests that cover the
new blockdev-amend functionality of luks and qcow2 driver

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 tests/qemu-iotests/302 | 278 +
 tests/qemu-iotests/302.out |  40 ++
 tests/qemu-iotests/303 | 233 +++
 tests/qemu-iotests/303.out |  33 +
 tests/qemu-iotests/group   |   2 +
 5 files changed, 586 insertions(+)
 create mode 100755 tests/qemu-iotests/302
 create mode 100644 tests/qemu-iotests/302.out
 create mode 100755 tests/qemu-iotests/303
 create mode 100644 tests/qemu-iotests/303.out

diff --git a/tests/qemu-iotests/302 b/tests/qemu-iotests/302
new file mode 100755
index 00..f7b4d13bd2
--- /dev/null
+++ b/tests/qemu-iotests/302
@@ -0,0 +1,278 @@
+#!/usr/bin/env python3
+#
+# Test case QMP's encrypted key management
+#
+# Copyright (C) 2019 Red Hat, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see .
+#
+
+import iotests
+import os
+import time
+import json
+
+test_img = os.path.join(iotests.test_dir, 'test.img')
+
+class Secret:
+def __init__(self, index):
+self._id = "keysec" + str(index)
+# you are not supposed to see the password...
+self._secret = "hunter" + str(index)
+
+def id(self):
+return self._id
+
+def secret(self):
+return self._secret
+
+def to_cmdline_object(self):
+return  [ "secret,id=" + self._id + ",data=" + self._secret]
+
+def to_qmp_object(self):
+return { "qom_type" : "secret", "id": self.id(),
+ "props": { "data": self.secret() } }
+
+
+class EncryptionSetupTestCase(iotests.QMPTestCase):
+
+# test case startup
+def setUp(self):
+# start the VM
+self.vm = iotests.VM()
+self.vm.launch()
+
+# create the secrets and load 'em into the VM
+self.secrets = [ Secret(i) for i in range(0, 6) ]
+for secret in self.secrets:
+result = self.vm.qmp("object-add", **secret.to_qmp_object())
+self.assert_qmp(result, 'return', {})
+
+if iotests.imgfmt == "qcow2":
+self.pfx = "encrypt."
+self.img_opts = [ '-o', "encrypt.format=luks" ]
+else:
+self.pfx = ""
+self.img_opts = []
+
+# test case shutdown
+def tearDown(self):
+# stop the VM
+self.vm.shutdown()
+
+###
+# create the encrypted block device
+def createImg(self, file, secret):
+
+iotests.qemu_img(
+'create',
+'--object', *secret.to_cmdline_object(),
+'-f', iotests.imgfmt,
+'-o', self.pfx + 'key-secret=' + secret.id(),
+'-o', self.pfx + 'iter-time=10',
+*self.img_opts,
+file,
+'1M')
+
+###
+# open an encrypted block device
+def openImageQmp(self, id, file, secret, read_only = False):
+
+encrypt_options = {
+'key-secret' : secret.id()
+}
+
+if iotests.imgfmt == "qcow2":
+encrypt_options = {
+'encrypt': {
+'format':'luks',
+**encrypt_options
+}
+}
+
+result = self.vm.qmp('blockdev-add', **
+{
+'driver': iotests.imgfmt,
+'node-name': id,
+'read-only': read_only,
+
+**encrypt_options,
+
+'file': {
+'driver': 'file',
+'filename': test_img,
+}
+}
+)
+self.assert_qmp(result, 'return', {})
+
+# close the encrypted block device
+def closeImageQmp(self, id):
+result = self.vm.qmp('blockdev-del', **{ 'node-name': id })
+self.assert_qmp(result, 'return', {})
+
+###
+# add a key to an encrypted block device
+def addKeyQmp(self, id, new_secret, secret = None,
+  slot = None, force = False):
+
+crypt_options = {
+'state'  : 'active',
+'new-secret' : 

[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs

[Heiko Sieger]

Here the vm.log with the qemu command line (shortened):

2020-05-03 18:23:38.674+: starting up libvirt version: 5.10.0, qemu
version: 5.0.50v5.0.0-154-g2ef486e76d-dirty, kernel: 5.4.36-1-MANJARO

-machine 
pc-q35-4.2,accel=kvm,usb=off,vmport=off,dump-guest-core=off,kernel_irqchip=on,pflash0=libvirt-pflash0-format,pflash1=libvirt-pflash1-format
 \
-cpu 
host,invtsc=on,hypervisor=on,topoext=on,hv-time,hv-relaxed,hv-vapic,hv-spinlocks=0x1fff,hv-vpindex,hv-synic,hv-stimer,hv-vendor-id=AuthenticAMD,hv-frequencies,hv-crash,kvm=off,host-cache-info=on,l3-cache=off
 \
-m 49152 \
-mem-prealloc \
-mem-path /dev/hugepages/libvirt/qemu/1-win10 \
-overcommit mem-lock=off \
-smp 24,sockets=1,cores=12,threads=2 \
-display none \
-no-user-config \
-nodefaults \
-chardev socket,id=charmonitor,fd=34,server,nowait \
-mon chardev=charmonitor,id=monitor,mode=control \
-rtc base=localtime,driftfix=slew \
-global kvm-pit.lost_tick_policy=delay \
-no-hpet \
-no-shutdown \
-global ICH9-LPC.disable_s3=1 \
-global ICH9-LPC.disable_s4=1 \
-boot menu=off,strict=on \

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1856335

Title:
  Cache Layout wrong on many Zen Arch CPUs

Status in QEMU:
  New

Bug description:
  AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
  to always map Cache ass if it was an 4-Core per CCX CPU, which is
  incorrect, and costs upwards 30% performance (more realistically 10%)
  in L3 Cache Layout aware applications.

  Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):

    
  EPYC-IBPB
  AMD
  

  In windows, coreinfo reports correctly:

    Unified Cache 1, Level 3,8 MB, Assoc  16, LineSize  64
    Unified Cache 6, Level 3,8 MB, Assoc  16, LineSize  64

  On a 3-CCX CPU (3960X /w 6 cores and no SMT):

   
  EPYC-IBPB
  AMD
  

  in windows, coreinfo reports incorrectly:

  --  Unified Cache  1, Level 3,8 MB, Assoc  16, LineSize  64
  **  Unified Cache  6, Level 3,8 MB, Assoc  16, LineSize  64

  Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.

  With newer Qemu there is a fix (that does behave correctly) in using the dies 
parameter:
   

  The problem is that the dies are exposed differently than how AMD does
  it natively, they are exposed to Windows as sockets, which means, that
  if you are nto a business user, you can't ever have a machine with
  more than two CCX (6 cores) as consumer versions of Windows only
  supports two sockets. (Should this be reported as a separate bug?)

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1856335/+subscriptions

[PATCH v3 10/14] iotests: qemu-img tests for luks key management

[Maxim Levitsky]

This commit adds two tests, which test the new amend interface
of both luks raw images and qcow2 luks encrypted images.

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 tests/qemu-iotests/300 | 207 +
 tests/qemu-iotests/300.out |  99 ++
 tests/qemu-iotests/301 |  90 
 tests/qemu-iotests/301.out |  30 ++
 tests/qemu-iotests/group   |   3 +
 5 files changed, 429 insertions(+)
 create mode 100755 tests/qemu-iotests/300
 create mode 100644 tests/qemu-iotests/300.out
 create mode 100755 tests/qemu-iotests/301
 create mode 100644 tests/qemu-iotests/301.out

diff --git a/tests/qemu-iotests/300 b/tests/qemu-iotests/300
new file mode 100755
index 00..aa1a77690f
--- /dev/null
+++ b/tests/qemu-iotests/300
@@ -0,0 +1,207 @@
+#!/usr/bin/env bash
+#
+# Test encryption key management with luks
+# Based on 134
+#
+# Copyright (C) 2019 Red Hat, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see .
+#
+
+# creator
+owner=mlevi...@redhat.com
+
+seq=`basename $0`
+echo "QA output created by $seq"
+
+status=1   # failure is the default!
+
+_cleanup()
+{
+   _cleanup_test_img
+}
+trap "_cleanup; exit \$status" 0 1 2 3 15
+
+# get standard environment, filters and checks
+. ./common.rc
+. ./common.filter
+
+_supported_fmt qcow2 luks
+_supported_proto file #TODO
+
+QEMU_IO_OPTIONS=$QEMU_IO_OPTIONS_NO_FMT
+
+if [ "$IMGFMT" = "qcow2" ] ; then
+   PR="encrypt."
+   EXTRA_IMG_ARGS="-o encrypt.format=luks"
+fi
+
+
+# secrets: you are supposed to see the password as ***, see :-)
+S0="--object secret,id=sec0,data=hunter0"
+S1="--object secret,id=sec1,data=hunter1"
+S2="--object secret,id=sec2,data=hunter2"
+S3="--object secret,id=sec3,data=hunter3"
+S4="--object secret,id=sec4,data=hunter4"
+SECRETS="$S0 $S1 $S2 $S3 $S4"
+
+# image with given secret
+IMGS0="--image-opts 
driver=$IMGFMT,file.filename=$TEST_IMG,${PR}key-secret=sec0"
+IMGS1="--image-opts 
driver=$IMGFMT,file.filename=$TEST_IMG,${PR}key-secret=sec1"
+IMGS2="--image-opts 
driver=$IMGFMT,file.filename=$TEST_IMG,${PR}key-secret=sec2"
+IMGS3="--image-opts 
driver=$IMGFMT,file.filename=$TEST_IMG,${PR}key-secret=sec3"
+IMGS4="--image-opts 
driver=$IMGFMT,file.filename=$TEST_IMG,${PR}key-secret=sec4"
+
+
+echo "== creating a test image =="
+_make_test_img $S0 $EXTRA_IMG_ARGS -o ${PR}key-secret=sec0,${PR}iter-time=10 
32M
+
+echo
+echo "== test that key 0 opens the image =="
+$QEMU_IO $S0 -c "read 0 4096" $IMGS0 | _filter_qemu_io | _filter_testdir
+
+echo
+echo "== adding a password to slot 4 =="
+$QEMU_IMG amend $SECRETS $IMGS0 -o 
${PR}state=active,${PR}new-secret=sec4,${PR}iter-time=10,${PR}keyslot=4
+echo "== adding a password to slot 1 =="
+$QEMU_IMG amend $SECRETS $IMGS0 -o 
${PR}state=active,${PR}new-secret=sec1,${PR}iter-time=10
+echo "== adding a password to slot 3 =="
+$QEMU_IMG amend $SECRETS $IMGS1 -o 
${PR}state=active,${PR}new-secret=sec3,${PR}iter-time=10,${PR}keyslot=3
+
+echo "== adding a password to slot 2 =="
+$QEMU_IMG amend $SECRETS $IMGS3 -o 
${PR}state=active,${PR}new-secret=sec2,${PR}iter-time=10
+
+
+echo "== erase slot 4 =="
+$QEMU_IMG amend $SECRETS $IMGS1 -o ${PR}state=inactive,${PR}keyslot=4 | 
_filter_img_create
+
+
+echo
+echo "== all secrets should work =="
+for IMG in "$IMGS0" "$IMGS1" "$IMGS2" "$IMGS3"; do
+   $QEMU_IO $SECRETS -c "read 0 4096" $IMG | _filter_qemu_io | 
_filter_testdir
+done
+
+echo
+echo "== erase slot 0 and try it =="
+$QEMU_IMG amend $SECRETS $IMGS1 -o ${PR}state=inactive,${PR}old-secret=sec0 | 
_filter_img_create
+$QEMU_IO $SECRETS -c "read 0 4096" $IMGS0 | _filter_qemu_io | _filter_testdir
+
+echo
+echo "== erase slot 2 and try it =="
+$QEMU_IMG amend $SECRETS $IMGS1 -o ${PR}state=inactive,${PR}keyslot=2 | 
_filter_img_create
+$QEMU_IO $SECRETS -c "read 0 4096" $IMGS2 | _filter_qemu_io | _filter_testdir
+
+
+# at this point slots 1 and 3 should be active
+
+echo
+echo "== filling  4 slots with secret 2 =="
+for i in $(seq 0 3) ; do
+   $QEMU_IMG amend $SECRETS $IMGS3 -o 
${PR}state=active,${PR}new-secret=sec2,${PR}iter-time=10
+done
+
+echo
+echo "== adding secret 0 =="
+   $QEMU_IMG amend $SECRETS $IMGS3 -o 
${PR}state=active,${PR}new-secret=sec0,${PR}iter-time=10
+
+echo
+echo "== adding secret 3 (last slot) =="
+   $QEMU_IMG amend $SECRETS $IMGS3 -o 

[PATCH v3 12/14] block/crypto: implement blockdev-amend

[Maxim Levitsky]

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/crypto.c   | 72 
 qapi/block-core.json | 14 -
 2 files changed, 66 insertions(+), 20 deletions(-)

diff --git a/block/crypto.c b/block/crypto.c
index b71e57f777..d7725df79e 100644
--- a/block/crypto.c
+++ b/block/crypto.c
@@ -775,32 +775,21 @@ block_crypto_get_specific_info_luks(BlockDriverState *bs, 
Error **errp)
 }
 
 static int
-block_crypto_amend_options_luks(BlockDriverState *bs,
-QemuOpts *opts,
-BlockDriverAmendStatusCB *status_cb,
-void *cb_opaque,
-bool force,
-Error **errp)
+block_crypto_amend_options_generic_luks(BlockDriverState *bs,
+QCryptoBlockAmendOptions 
*amend_options,
+bool force,
+Error **errp)
 {
 BlockCrypto *crypto = bs->opaque;
-QDict *cryptoopts = NULL;
-QCryptoBlockAmendOptions *amend_options = NULL;
 int ret;
 
 assert(crypto);
 assert(crypto->block);
-crypto->updating_keys = true;
 
+/* apply for exclusive read/write permissions to the underlying file*/
+crypto->updating_keys = true;
 ret = bdrv_child_refresh_perms(bs, bs->file, errp);
-if (ret < 0) {
-goto cleanup;
-}
-
-cryptoopts = qemu_opts_to_qdict(opts, NULL);
-qdict_put_str(cryptoopts, "format", "luks");
-amend_options = block_crypto_amend_opts_init(cryptoopts, errp);
-if (!amend_options) {
-ret = -EINVAL;
+if (ret) {
 goto cleanup;
 }
 
@@ -812,13 +801,57 @@ block_crypto_amend_options_luks(BlockDriverState *bs,
   force,
   errp);
 cleanup:
+/* release exclusive read/write permissions to the underlying file*/
 crypto->updating_keys = false;
 bdrv_child_refresh_perms(bs, bs->file, errp);
-qapi_free_QCryptoBlockAmendOptions(amend_options);
+return ret;
+}
+
+static int
+block_crypto_amend_options_luks(BlockDriverState *bs,
+QemuOpts *opts,
+BlockDriverAmendStatusCB *status_cb,
+void *cb_opaque,
+bool force,
+Error **errp)
+{
+BlockCrypto *crypto = bs->opaque;
+QDict *cryptoopts = NULL;
+QCryptoBlockAmendOptions *amend_options = NULL;
+int ret = -EINVAL;
+
+assert(crypto);
+assert(crypto->block);
+
+cryptoopts = qemu_opts_to_qdict(opts, NULL);
+qdict_put_str(cryptoopts, "format", "luks");
+amend_options = block_crypto_amend_opts_init(cryptoopts, errp);
 qobject_unref(cryptoopts);
+if (!amend_options) {
+goto cleanup;
+}
+ret = block_crypto_amend_options_generic_luks(bs, amend_options,
+  force, errp);
+cleanup:
+qapi_free_QCryptoBlockAmendOptions(amend_options);
 return ret;
 }
 
+static int
+coroutine_fn block_crypto_co_amend_luks(BlockDriverState *bs,
+BlockdevAmendOptions *opts,
+bool force,
+Error **errp)
+{
+QCryptoBlockAmendOptions amend_opts;
+
+amend_opts = (QCryptoBlockAmendOptions) {
+.format = Q_CRYPTO_BLOCK_FORMAT_LUKS,
+.u.luks = *qapi_BlockdevAmendOptionsLUKS_base(>u.luks),
+};
+return block_crypto_amend_options_generic_luks(bs, _opts,
+   force, errp);
+}
 
 static void
 block_crypto_child_perms(BlockDriverState *bs, BdrvChild *c,
@@ -891,6 +924,7 @@ static BlockDriver bdrv_crypto_luks = {
 .bdrv_get_info  = block_crypto_get_info_luks,
 .bdrv_get_specific_info = block_crypto_get_specific_info_luks,
 .bdrv_amend_options = block_crypto_amend_options_luks,
+.bdrv_co_amend  = block_crypto_co_amend_luks,
 
 .strong_runtime_opts = block_crypto_strong_runtime_opts,
 };
diff --git a/qapi/block-core.json b/qapi/block-core.json
index 5b9123c15f..a5f679ac17 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -4649,6 +4649,18 @@
   'data': { 'job-id': 'str',
 'options': 'BlockdevCreateOptions' } }
 
+##
+# @BlockdevAmendOptionsLUKS:
+#
+# Driver specific image amend options for LUKS.
+#
+# Since: 5.0
+##
+{ 'struct': 'BlockdevAmendOptionsLUKS',
+  'base': 'QCryptoBlockAmendOptionsLUKS',
+  'data': { }
+}
+
 ##
 # @BlockdevAmendOptions:
 #
@@ -4663,7 +4675,7 @@
   'driver': 'BlockdevDriver' },
   'discriminator': 'driver',
   'data': {
-  } }
+  'luks':   'BlockdevAmendOptionsLUKS' } }
 
 ##
 # @x-blockdev-amend:
-- 
2.17.2

[PATCH v3 06/14] block/crypto: rename two functions

[Maxim Levitsky]

rename the write_func to create_write_func, and init_func to create_init_func.
This is preparation for other write_func that will be used to update the 
encryption keys.

No functional changes

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/crypto.c | 25 -
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/block/crypto.c b/block/crypto.c
index d379e39efb..13ca1ad891 100644
--- a/block/crypto.c
+++ b/block/crypto.c
@@ -79,12 +79,12 @@ struct BlockCryptoCreateData {
 };
 
 
-static ssize_t block_crypto_write_func(QCryptoBlock *block,
-   size_t offset,
-   const uint8_t *buf,
-   size_t buflen,
-   void *opaque,
-   Error **errp)
+static ssize_t block_crypto_create_write_func(QCryptoBlock *block,
+  size_t offset,
+  const uint8_t *buf,
+  size_t buflen,
+  void *opaque,
+  Error **errp)
 {
 struct BlockCryptoCreateData *data = opaque;
 ssize_t ret;
@@ -97,11 +97,10 @@ static ssize_t block_crypto_write_func(QCryptoBlock *block,
 return ret;
 }
 
-
-static ssize_t block_crypto_init_func(QCryptoBlock *block,
-  size_t headerlen,
-  void *opaque,
-  Error **errp)
+static ssize_t block_crypto_create_init_func(QCryptoBlock *block,
+ size_t headerlen,
+ void *opaque,
+ Error **errp)
 {
 struct BlockCryptoCreateData *data = opaque;
 
@@ -297,8 +296,8 @@ static int block_crypto_co_create_generic(BlockDriverState 
*bs,
 };
 
 crypto = qcrypto_block_create(opts, NULL,
-  block_crypto_init_func,
-  block_crypto_write_func,
+  block_crypto_create_init_func,
+  block_crypto_create_write_func,
   ,
   errp);
 
-- 
2.17.2

[PATCH v3 09/14] iotests: filter few more luks specific create options

[Maxim Levitsky]

This allows more tests to be able to have same output on both qcow2 luks 
encrypted images
and raw luks images

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 tests/qemu-iotests/087.out   |  6 ++---
 tests/qemu-iotests/134.out   |  2 +-
 tests/qemu-iotests/158.out   |  4 +--
 tests/qemu-iotests/188.out   |  2 +-
 tests/qemu-iotests/189.out   |  4 +--
 tests/qemu-iotests/198.out   |  4 +--
 tests/qemu-iotests/263.out   |  4 +--
 tests/qemu-iotests/274.out   | 46 
 tests/qemu-iotests/284.out   |  6 ++---
 tests/qemu-iotests/common.filter |  6 +++--
 10 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/tests/qemu-iotests/087.out b/tests/qemu-iotests/087.out
index f23bffbbf1..d5ff53302e 100644
--- a/tests/qemu-iotests/087.out
+++ b/tests/qemu-iotests/087.out
@@ -34,7 +34,7 @@ QMP_VERSION
 
 === Encrypted image QCow ===
 
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on 
encrypt.key-secret=sec0 size=134217728
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on size=134217728
 Testing:
 QMP_VERSION
 {"return": {}}
@@ -46,7 +46,7 @@ QMP_VERSION
 
 === Encrypted image LUKS ===
 
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encrypt.format=luks 
encrypt.key-secret=sec0 size=134217728
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728
 Testing:
 QMP_VERSION
 {"return": {}}
@@ -58,7 +58,7 @@ QMP_VERSION
 
 === Missing driver ===
 
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on 
encrypt.key-secret=sec0 size=134217728
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on size=134217728
 Testing: -S
 QMP_VERSION
 {"return": {}}
diff --git a/tests/qemu-iotests/134.out b/tests/qemu-iotests/134.out
index f2878f5f3a..e4733c0b81 100644
--- a/tests/qemu-iotests/134.out
+++ b/tests/qemu-iotests/134.out
@@ -1,5 +1,5 @@
 QA output created by 134
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on 
encrypt.key-secret=sec0 size=134217728
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on size=134217728
 
 == reading whole image ==
 read 134217728/134217728 bytes at offset 0
diff --git a/tests/qemu-iotests/158.out b/tests/qemu-iotests/158.out
index fa2294bb85..52ea9a488f 100644
--- a/tests/qemu-iotests/158.out
+++ b/tests/qemu-iotests/158.out
@@ -1,6 +1,6 @@
 QA output created by 158
 == create base ==
-Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT encryption=on 
encrypt.key-secret=sec0 size=134217728
+Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT encryption=on size=134217728
 
 == writing whole image ==
 wrote 134217728/134217728 bytes at offset 0
@@ -10,7 +10,7 @@ wrote 134217728/134217728 bytes at offset 0
 read 134217728/134217728 bytes at offset 0
 128 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
 == create overlay ==
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on 
encrypt.key-secret=sec0 size=134217728 backing_file=TEST_DIR/t.IMGFMT.base
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encryption=on size=134217728 
backing_file=TEST_DIR/t.IMGFMT.base
 
 == writing part of a cluster ==
 wrote 1024/1024 bytes at offset 0
diff --git a/tests/qemu-iotests/188.out b/tests/qemu-iotests/188.out
index 4b9aadd51c..5426861b18 100644
--- a/tests/qemu-iotests/188.out
+++ b/tests/qemu-iotests/188.out
@@ -1,5 +1,5 @@
 QA output created by 188
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encrypt.format=luks 
encrypt.key-secret=sec0 encrypt.iter-time=10 size=16777216
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=16777216
 
 == reading whole image ==
 read 16777216/16777216 bytes at offset 0
diff --git a/tests/qemu-iotests/189.out b/tests/qemu-iotests/189.out
index e536d95d53..bc213cbe14 100644
--- a/tests/qemu-iotests/189.out
+++ b/tests/qemu-iotests/189.out
@@ -1,6 +1,6 @@
 QA output created by 189
 == create base ==
-Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT encrypt.format=luks 
encrypt.key-secret=sec0 encrypt.iter-time=10 size=16777216
+Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=16777216
 
 == writing whole image ==
 wrote 16777216/16777216 bytes at offset 0
@@ -10,7 +10,7 @@ wrote 16777216/16777216 bytes at offset 0
 read 16777216/16777216 bytes at offset 0
 16 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
 == create overlay ==
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT encrypt.format=luks 
encrypt.key-secret=sec1 encrypt.iter-time=10 size=16777216 
backing_file=TEST_DIR/t.IMGFMT.base
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=16777216 
backing_file=TEST_DIR/t.IMGFMT.base
 
 == writing part of a cluster ==
 wrote 1024/1024 bytes at offset 0
diff --git a/tests/qemu-iotests/198.out b/tests/qemu-iotests/198.out
index b0f2d417af..acfdf96b0c 100644
--- a/tests/qemu-iotests/198.out
+++ b/tests/qemu-iotests/198.out
@@ -1,12 +1,12 @@
 QA output created by 198
 == create base ==
-Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT encrypt.format=luks 
encrypt.key-secret=sec0 encrypt.iter-time=10 size=16777216
+Formatting 'TEST_DIR/t.IMGFMT.base', 

[PATCH v3 11/14] block/core: add generic infrastructure for x-blockdev-amend qmp command

[Maxim Levitsky]

blockdev-amend will be used similiar to blockdev-create
to allow on the fly changes of the structure of the format based block devices.

Current plan is to first support encryption keyslot management for luks
based formats (raw and embedded in qcow2)

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/Makefile.objs   |   2 +-
 block/amend.c | 108 ++
 include/block/block_int.h |  21 +---
 qapi/block-core.json  |  42 +++
 qapi/job.json |   4 +-
 5 files changed, 169 insertions(+), 8 deletions(-)
 create mode 100644 block/amend.c

diff --git a/block/Makefile.objs b/block/Makefile.objs
index 3635b6b4c1..a0988638d5 100644
--- a/block/Makefile.objs
+++ b/block/Makefile.objs
@@ -19,7 +19,7 @@ block-obj-$(CONFIG_WIN32) += file-win32.o win32-aio.o
 block-obj-$(CONFIG_POSIX) += file-posix.o
 block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o
 block-obj-$(CONFIG_LINUX_IO_URING) += io_uring.o
-block-obj-y += null.o mirror.o commit.o io.o create.o
+block-obj-y += null.o mirror.o commit.o io.o create.o amend.o
 block-obj-y += throttle-groups.o
 block-obj-$(CONFIG_LINUX) += nvme.o
 
diff --git a/block/amend.c b/block/amend.c
new file mode 100644
index 00..2db7b1eafc
--- /dev/null
+++ b/block/amend.c
@@ -0,0 +1,108 @@
+/*
+ * Block layer code related to image options amend
+ *
+ * Copyright (c) 2018 Kevin Wolf 
+ * Copyright (c) 2019 Maxim Levitsky 
+ *
+ * Heavily based on create.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "block/block_int.h"
+#include "qemu/job.h"
+#include "qemu/main-loop.h"
+#include "qapi/qapi-commands-block-core.h"
+#include "qapi/qapi-visit-block-core.h"
+#include "qapi/clone-visitor.h"
+#include "qapi/error.h"
+
+typedef struct BlockdevAmendJob {
+Job common;
+BlockdevAmendOptions *opts;
+BlockDriverState *bs;
+bool force;
+} BlockdevAmendJob;
+
+static int coroutine_fn blockdev_amend_run(Job *job, Error **errp)
+{
+BlockdevAmendJob *s = container_of(job, BlockdevAmendJob, common);
+int ret;
+
+job_progress_set_remaining(>common, 1);
+ret = s->bs->drv->bdrv_co_amend(s->bs, s->opts, s->force, errp);
+job_progress_update(>common, 1);
+qapi_free_BlockdevAmendOptions(s->opts);
+return ret;
+}
+
+static const JobDriver blockdev_amend_job_driver = {
+.instance_size = sizeof(BlockdevAmendJob),
+.job_type  = JOB_TYPE_AMEND,
+.run   = blockdev_amend_run,
+};
+
+void qmp_x_blockdev_amend(const char *job_id,
+  const char *node_name,
+  BlockdevAmendOptions *options,
+  bool has_force,
+  bool force,
+  Error **errp)
+{
+BlockdevAmendJob *s;
+const char *fmt = BlockdevDriver_str(options->driver);
+BlockDriver *drv = bdrv_find_format(fmt);
+BlockDriverState *bs = bdrv_find_node(node_name);
+
+/*
+ * If the driver is in the schema, we know that it exists. But it may not
+ * be whitelisted.
+ */
+assert(drv);
+if (bdrv_uses_whitelist() && !bdrv_is_whitelisted(drv, false)) {
+error_setg(errp, "Driver is not whitelisted");
+return;
+}
+
+if (bs->drv != drv) {
+error_setg(errp,
+   "x-blockdev-amend doesn't support changing the block 
driver");
+return;
+}
+
+/* Error out if the driver doesn't support .bdrv_co_amend */
+if (!drv->bdrv_co_amend) {
+error_setg(errp, "Driver does not support x-blockdev-amend");
+return;
+}
+
+/* Create the block job */
+s = job_create(job_id, _amend_job_driver, NULL,
+   bdrv_get_aio_context(bs), JOB_DEFAULT | JOB_MANUAL_DISMISS,
+   NULL, NULL, errp);
+if (!s) {
+return;
+}
+
+s->bs = bs,
+s->opts = 

[PATCH v3 05/14] block/amend: refactor qcow2 amend options

[Maxim Levitsky]

Some qcow2 create options can't be used for amend.
Remove them from the qcow2 create options and add generic logic to detect
such options in qemu-img

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/qcow2.c  | 108 ++---
 qemu-img.c |  18 +++-
 tests/qemu-iotests/049.out | 102 ++--
 tests/qemu-iotests/061.out |  12 ++-
 tests/qemu-iotests/079.out |  18 ++--
 tests/qemu-iotests/082.out | 149 
 tests/qemu-iotests/085.out |  38 
 tests/qemu-iotests/087.out |   6 +-
 tests/qemu-iotests/115.out |   2 +-
 tests/qemu-iotests/121.out |   4 +-
 tests/qemu-iotests/125.out | 192 ++---
 tests/qemu-iotests/134.out |   2 +-
 tests/qemu-iotests/144.out |   4 +-
 tests/qemu-iotests/158.out |   4 +-
 tests/qemu-iotests/182.out |   2 +-
 tests/qemu-iotests/185.out |   8 +-
 tests/qemu-iotests/188.out |   2 +-
 tests/qemu-iotests/189.out |   4 +-
 tests/qemu-iotests/198.out |   4 +-
 tests/qemu-iotests/243.out |  16 ++--
 tests/qemu-iotests/250.out |   2 +-
 tests/qemu-iotests/255.out |   8 +-
 tests/qemu-iotests/263.out |   4 +-
 tests/qemu-iotests/280.out |   2 +-
 24 files changed, 283 insertions(+), 428 deletions(-)

diff --git a/block/qcow2.c b/block/qcow2.c
index 13780b0278..e6c4d0b0b4 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -2971,17 +2971,6 @@ static int qcow2_change_backing_file(BlockDriverState 
*bs,
 return qcow2_update_header(bs);
 }
 
-static int qcow2_crypt_method_from_format(const char *encryptfmt)
-{
-if (g_str_equal(encryptfmt, "luks")) {
-return QCOW_CRYPT_LUKS;
-} else if (g_str_equal(encryptfmt, "aes")) {
-return QCOW_CRYPT_AES;
-} else {
-return -EINVAL;
-}
-}
-
 static int qcow2_set_up_encryption(BlockDriverState *bs,
QCryptoBlockCreateOptions *cryptoopts,
Error **errp)
@@ -5210,9 +5199,6 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 bool lazy_refcounts = s->use_lazy_refcounts;
 bool data_file_raw = data_file_is_raw(bs);
 const char *compat = NULL;
-uint64_t cluster_size = s->cluster_size;
-bool encrypt;
-int encformat;
 int refcount_bits = s->refcount_bits;
 int ret;
 QemuOptDesc *desc = opts->list->desc;
@@ -5237,44 +5223,12 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 error_setg(errp, "Unknown compatibility level %s", compat);
 return -EINVAL;
 }
-} else if (!strcmp(desc->name, BLOCK_OPT_PREALLOC)) {
-error_setg(errp, "Cannot change preallocation mode");
-return -ENOTSUP;
 } else if (!strcmp(desc->name, BLOCK_OPT_SIZE)) {
 new_size = qemu_opt_get_size(opts, BLOCK_OPT_SIZE, 0);
 } else if (!strcmp(desc->name, BLOCK_OPT_BACKING_FILE)) {
 backing_file = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE);
 } else if (!strcmp(desc->name, BLOCK_OPT_BACKING_FMT)) {
 backing_format = qemu_opt_get(opts, BLOCK_OPT_BACKING_FMT);
-} else if (!strcmp(desc->name, BLOCK_OPT_ENCRYPT)) {
-encrypt = qemu_opt_get_bool(opts, BLOCK_OPT_ENCRYPT,
-!!s->crypto);
-
-if (encrypt != !!s->crypto) {
-error_setg(errp,
-   "Changing the encryption flag is not supported");
-return -ENOTSUP;
-}
-} else if (!strcmp(desc->name, BLOCK_OPT_ENCRYPT_FORMAT)) {
-encformat = qcow2_crypt_method_from_format(
-qemu_opt_get(opts, BLOCK_OPT_ENCRYPT_FORMAT));
-
-if (encformat != s->crypt_method_header) {
-error_setg(errp,
-   "Changing the encryption format is not supported");
-return -ENOTSUP;
-}
-} else if (g_str_has_prefix(desc->name, "encrypt.")) {
-error_setg(errp,
-   "Changing the encryption parameters is not supported");
-return -ENOTSUP;
-} else if (!strcmp(desc->name, BLOCK_OPT_CLUSTER_SIZE)) {
-cluster_size = qemu_opt_get_size(opts, BLOCK_OPT_CLUSTER_SIZE,
- cluster_size);
-if (cluster_size != s->cluster_size) {
-error_setg(errp, "Changing the cluster size is not supported");
-return -ENOTSUP;
-}
 } else if (!strcmp(desc->name, BLOCK_OPT_LAZY_REFCOUNTS)) {
 lazy_refcounts = qemu_opt_get_bool(opts, BLOCK_OPT_LAZY_REFCOUNTS,
lazy_refcounts);
@@ -5527,37 +5481,6 @@ void qcow2_signal_corruption(BlockDriverState *bs, bool 
fatal, int64_t offset,
 .help = "The external data file must stay valid "   \
 "as a raw image"

[PATCH v3 13/14] block/qcow2: implement blockdev-amend

[Maxim Levitsky]

Currently the implementation only supports amending the encryption
options, unlike the qemu-img version

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/qcow2.c| 39 +++
 qapi/block-core.json | 16 +++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/block/qcow2.c b/block/qcow2.c
index ce1e25f341..a770b88a8f 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -5448,6 +5448,44 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 return 0;
 }
 
+static int coroutine_fn qcow2_co_amend(BlockDriverState *bs,
+   BlockdevAmendOptions *opts,
+   bool force,
+   Error **errp)
+{
+BlockdevAmendOptionsQcow2 *qopts = >u.qcow2;
+BDRVQcow2State *s = bs->opaque;
+int ret = 0;
+
+if (qopts->has_encrypt) {
+if (!s->crypto) {
+error_setg(errp, "image is not encrypted, can't amend");
+return -EOPNOTSUPP;
+}
+
+if (qopts->encrypt->format != Q_CRYPTO_BLOCK_FORMAT_LUKS) {
+error_setg(errp,
+   "Amend can't be used to change the qcow2 encryption 
format");
+return -EOPNOTSUPP;
+}
+
+if (s->crypt_method_header != QCOW_CRYPT_LUKS) {
+error_setg(errp,
+   "Only LUKS encryption options can be amended for qcow2 
with blockdev-amend");
+return -EOPNOTSUPP;
+}
+
+ret = qcrypto_block_amend_options(s->crypto,
+  qcow2_crypto_hdr_read_func,
+  qcow2_crypto_hdr_write_func,
+  bs,
+  qopts->encrypt,
+  force,
+  errp);
+}
+return ret;
+}
+
 /*
  * If offset or size are negative, respectively, they will not be included in
  * the BLOCK_IMAGE_CORRUPTED event emitted.
@@ -5658,6 +5696,7 @@ BlockDriver bdrv_qcow2 = {
 .mutable_opts= mutable_opts,
 .bdrv_co_check   = qcow2_co_check,
 .bdrv_amend_options  = qcow2_amend_options,
+.bdrv_co_amend   = qcow2_co_amend,
 
 .bdrv_detach_aio_context  = qcow2_detach_aio_context,
 .bdrv_attach_aio_context  = qcow2_attach_aio_context,
diff --git a/qapi/block-core.json b/qapi/block-core.json
index a5f679ac17..0ffdc1c3d4 100644
--- a/qapi/block-core.json
+++ b/qapi/block-core.json
@@ -4661,6 +4661,19 @@
   'data': { }
 }
 
+##
+# @BlockdevAmendOptionsQcow2:
+#
+# Driver specific image amend options for qcow2.
+# For now, only encryption options can be amended
+#
+# @encrypt  Encryption options to be amended
+#
+# Since: 5.0
+##
+{ 'struct': 'BlockdevAmendOptionsQcow2',
+  'data': { '*encrypt': 'QCryptoBlockAmendOptions' } }
+
 ##
 # @BlockdevAmendOptions:
 #
@@ -4675,7 +4688,8 @@
   'driver': 'BlockdevDriver' },
   'discriminator': 'driver',
   'data': {
-  'luks':   'BlockdevAmendOptionsLUKS' } }
+  'luks':   'BlockdevAmendOptionsLUKS',
+  'qcow2':  'BlockdevAmendOptionsQcow2' } }
 
 ##
 # @x-blockdev-amend:
-- 
2.17.2

[PATCH v3 08/14] block/qcow2: extend qemu-img amend interface with crypto options

[Maxim Levitsky]

Now that we have all the infrastructure in place,
wire it in the qcow2 driver and expose this to the user.

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/qcow2.c  | 72 +-
 tests/qemu-iotests/082.out | 45 
 2 files changed, 108 insertions(+), 9 deletions(-)

diff --git a/block/qcow2.c b/block/qcow2.c
index e6c4d0b0b4..ce1e25f341 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -176,6 +176,19 @@ static ssize_t qcow2_crypto_hdr_write_func(QCryptoBlock 
*block, size_t offset,
 return ret;
 }
 
+static QDict*
+qcow2_extract_crypto_opts(QemuOpts *opts, const char *fmt, Error **errp)
+{
+QDict *cryptoopts_qdict;
+QDict *opts_qdict;
+
+/* Extract "encrypt." options into a qdict */
+opts_qdict = qemu_opts_to_qdict(opts, NULL);
+qdict_extract_subqdict(opts_qdict, _qdict, "encrypt.");
+qobject_unref(opts_qdict);
+qdict_put_str(cryptoopts_qdict, "format", fmt);
+return cryptoopts_qdict;
+}
 
 /*
  * read qcow2 extension and fill bs
@@ -4733,17 +4746,11 @@ static BlockMeasureInfo *qcow2_measure(QemuOpts *opts, 
BlockDriverState *in_bs,
 g_free(optstr);
 
 if (has_luks) {
+
 g_autoptr(QCryptoBlockCreateOptions) create_opts = NULL;
-QDict *opts_qdict;
-QDict *cryptoopts;
+QDict *cryptoopts = qcow2_extract_crypto_opts(opts, "luks", errp);
 size_t headerlen;
 
-opts_qdict = qemu_opts_to_qdict(opts, NULL);
-qdict_extract_subqdict(opts_qdict, , "encrypt.");
-qobject_unref(opts_qdict);
-
-qdict_put_str(cryptoopts, "format", "luks");
-
 create_opts = block_crypto_create_opts_init(cryptoopts, errp);
 qobject_unref(cryptoopts);
 if (!create_opts) {
@@ -5122,6 +5129,7 @@ typedef enum Qcow2AmendOperation {
 QCOW2_NO_OPERATION = 0,
 
 QCOW2_UPGRADING,
+QCOW2_UPDATING_ENCRYPTION,
 QCOW2_CHANGING_REFCOUNT_ORDER,
 QCOW2_DOWNGRADING,
 } Qcow2AmendOperation;
@@ -5203,6 +5211,7 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 int ret;
 QemuOptDesc *desc = opts->list->desc;
 Qcow2AmendHelperCBInfo helper_cb_info;
+bool encryption_update = false;
 
 while (desc && desc->name) {
 if (!qemu_opt_find(opts, desc->name)) {
@@ -5229,6 +5238,18 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 backing_file = qemu_opt_get(opts, BLOCK_OPT_BACKING_FILE);
 } else if (!strcmp(desc->name, BLOCK_OPT_BACKING_FMT)) {
 backing_format = qemu_opt_get(opts, BLOCK_OPT_BACKING_FMT);
+} else if (g_str_has_prefix(desc->name, "encrypt.")) {
+if (!s->crypto) {
+error_setg(errp,
+   "Can't amend encryption options - encryption not 
present");
+return -EINVAL;
+}
+if (s->crypt_method_header != QCOW_CRYPT_LUKS) {
+error_setg(errp,
+   "Only LUKS encryption options can be amended");
+return -ENOTSUP;
+}
+encryption_update = true;
 } else if (!strcmp(desc->name, BLOCK_OPT_LAZY_REFCOUNTS)) {
 lazy_refcounts = qemu_opt_get_bool(opts, BLOCK_OPT_LAZY_REFCOUNTS,
lazy_refcounts);
@@ -5271,7 +5292,8 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 .original_status_cb = status_cb,
 .original_cb_opaque = cb_opaque,
 .total_operations = (new_version != old_version)
-  + (s->refcount_bits != refcount_bits)
+  + (s->refcount_bits != refcount_bits) +
+(encryption_update == true)
 };
 
 /* Upgrade first (some features may require compat=1.1) */
@@ -5284,6 +5306,33 @@ static int qcow2_amend_options(BlockDriverState *bs, 
QemuOpts *opts,
 }
 }
 
+if (encryption_update) {
+QDict *amend_opts_dict;
+QCryptoBlockAmendOptions *amend_opts;
+
+helper_cb_info.current_operation = QCOW2_UPDATING_ENCRYPTION;
+amend_opts_dict = qcow2_extract_crypto_opts(opts, "luks", errp);
+if (!amend_opts_dict) {
+return -EINVAL;
+}
+amend_opts = block_crypto_amend_opts_init(amend_opts_dict, errp);
+qobject_unref(amend_opts_dict);
+if (!amend_opts) {
+return -EINVAL;
+}
+ret = qcrypto_block_amend_options(s->crypto,
+  qcow2_crypto_hdr_read_func,
+  qcow2_crypto_hdr_write_func,
+  bs,
+  amend_opts,
+  force,
+  errp);
+qapi_free_QCryptoBlockAmendOptions(amend_opts);
+if (ret < 0) {
+

[PATCH v3 02/14] qcrypto/luks: implement encryption key management

[Maxim Levitsky]

Next few patches will expose that functionality
to the user.

Signed-off-by: Maxim Levitsky 
---
 crypto/block-luks.c | 406 +++-
 qapi/crypto.json|  61 ++-
 2 files changed, 463 insertions(+), 4 deletions(-)

diff --git a/crypto/block-luks.c b/crypto/block-luks.c
index 4861db810c..26a05d30d4 100644
--- a/crypto/block-luks.c
+++ b/crypto/block-luks.c
@@ -32,6 +32,7 @@
 #include "qemu/uuid.h"
 
 #include "qemu/coroutine.h"
+#include "qemu/bitmap.h"
 
 /*
  * Reference for the LUKS format implemented here is
@@ -70,6 +71,9 @@ typedef struct QCryptoBlockLUKSKeySlot 
QCryptoBlockLUKSKeySlot;
 
 #define QCRYPTO_BLOCK_LUKS_SECTOR_SIZE 512LL
 
+#define QCRYPTO_BLOCK_LUKS_DEFAULT_ITER_TIME_MS 2000
+#define QCRYPTO_BLOCK_LUKS_ERASE_ITERATIONS 40
+
 static const char qcrypto_block_luks_magic[QCRYPTO_BLOCK_LUKS_MAGIC_LEN] = {
 'L', 'U', 'K', 'S', 0xBA, 0xBE
 };
@@ -219,6 +223,9 @@ struct QCryptoBlockLUKS {
 
 /* Hash algorithm used in pbkdf2 function */
 QCryptoHashAlgorithm hash_alg;
+
+/* Name of the secret that was used to open the image */
+char *secret;
 };
 
 
@@ -1069,6 +1076,119 @@ qcrypto_block_luks_find_key(QCryptoBlock *block,
 return -1;
 }
 
+/*
+ * Returns true if a slot i is marked as active
+ * (contains encrypted copy of the master key)
+ */
+static bool
+qcrypto_block_luks_slot_active(const QCryptoBlockLUKS *luks,
+   unsigned int slot_idx)
+{
+uint32_t val = luks->header.key_slots[slot_idx].active;
+return val ==  QCRYPTO_BLOCK_LUKS_KEY_SLOT_ENABLED;
+}
+
+/*
+ * Returns the number of slots that are marked as active
+ * (slots that contain encrypted copy of the master key)
+ */
+static unsigned int
+qcrypto_block_luks_count_active_slots(const QCryptoBlockLUKS *luks)
+{
+size_t i = 0;
+unsigned int ret = 0;
+
+for (i = 0; i < QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS; i++) {
+if (qcrypto_block_luks_slot_active(luks, i)) {
+ret++;
+}
+}
+return ret;
+}
+
+/*
+ * Finds first key slot which is not active
+ * Returns the key slot index, or -1 if it doesn't exist
+ */
+static int
+qcrypto_block_luks_find_free_keyslot(const QCryptoBlockLUKS *luks)
+{
+size_t i;
+
+for (i = 0; i < QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS; i++) {
+if (!qcrypto_block_luks_slot_active(luks, i)) {
+return i;
+}
+}
+return -1;
+}
+
+/*
+ * Erases an keyslot given its index
+ * Returns:
+ *0 if the keyslot was erased successfully
+ *   -1 if a error occurred while erasing the keyslot
+ *
+ */
+static int
+qcrypto_block_luks_erase_key(QCryptoBlock *block,
+ unsigned int slot_idx,
+ QCryptoBlockWriteFunc writefunc,
+ void *opaque,
+ Error **errp)
+{
+QCryptoBlockLUKS *luks = block->opaque;
+QCryptoBlockLUKSKeySlot *slot = >header.key_slots[slot_idx];
+g_autofree uint8_t *garbagesplitkey = NULL;
+size_t splitkeylen = luks->header.master_key_len * slot->stripes;
+size_t i;
+Error *local_err = NULL;
+int ret;
+
+assert(slot_idx < QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS);
+assert(splitkeylen > 0);
+garbagesplitkey = g_new0(uint8_t, splitkeylen);
+
+/* Reset the key slot header */
+memset(slot->salt, 0, QCRYPTO_BLOCK_LUKS_SALT_LEN);
+slot->iterations = 0;
+slot->active = QCRYPTO_BLOCK_LUKS_KEY_SLOT_DISABLED;
+
+ret = qcrypto_block_luks_store_header(block,  writefunc,
+  opaque, _err);
+
+if (ret) {
+error_propagate(errp, local_err);
+}
+/*
+ * Now try to erase the key material, even if the header
+ * update failed
+ */
+for (i = 0; i < QCRYPTO_BLOCK_LUKS_ERASE_ITERATIONS; i++) {
+if (qcrypto_random_bytes(garbagesplitkey,
+ splitkeylen, _err) < 0) {
+/*
+ * If we failed to get the random data, still write
+ * at least zeros to the key slot at least once
+ */
+error_propagate(errp, local_err);
+
+if (i > 0) {
+return -1;
+}
+}
+if (writefunc(block,
+  slot->key_offset_sector * QCRYPTO_BLOCK_LUKS_SECTOR_SIZE,
+  garbagesplitkey,
+  splitkeylen,
+  opaque,
+  _err) != splitkeylen) {
+error_propagate(errp, local_err);
+return -1;
+}
+}
+return 0;
+}
 
 static int
 qcrypto_block_luks_open(QCryptoBlock *block,
@@ -1099,6 +1219,7 @@ qcrypto_block_luks_open(QCryptoBlock *block,
 
 luks = g_new0(QCryptoBlockLUKS, 1);
 block->opaque = luks;
+luks->secret = g_strdup(options->u.luks.key_secret);
 
 if (qcrypto_block_luks_load_header(block, readfunc, opaque, errp) < 0) {
 goto fail;
@@ -1164,6 +1285,7 @@ 

[PATCH v3 01/14] qcrypto/core: add generic infrastructure for crypto options amendment

[Maxim Levitsky]

This will be used first to implement luks keyslot management.

block_crypto_amend_opts_init will be used to convert
qemu-img cmdline to QCryptoBlockAmendOptions

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/crypto.c | 17 +
 block/crypto.h |  3 +++
 crypto/block.c | 29 +
 crypto/blockpriv.h |  8 
 include/crypto/block.h | 22 ++
 qapi/crypto.json   | 16 
 6 files changed, 95 insertions(+)

diff --git a/block/crypto.c b/block/crypto.c
index e02f343590..d379e39efb 100644
--- a/block/crypto.c
+++ b/block/crypto.c
@@ -185,6 +185,23 @@ block_crypto_create_opts_init(QDict *opts, Error **errp)
 return ret;
 }
 
+QCryptoBlockAmendOptions *
+block_crypto_amend_opts_init(QDict *opts, Error **errp)
+{
+Visitor *v;
+QCryptoBlockAmendOptions *ret;
+
+v = qobject_input_visitor_new_flat_confused(opts, errp);
+if (!v) {
+return NULL;
+}
+
+visit_type_QCryptoBlockAmendOptions(v, NULL, , errp);
+
+visit_free(v);
+return ret;
+}
+
 
 static int block_crypto_open_generic(QCryptoBlockFormat format,
  QemuOptsList *opts_spec,
diff --git a/block/crypto.h b/block/crypto.h
index b935695e79..06e044c9be 100644
--- a/block/crypto.h
+++ b/block/crypto.h
@@ -91,6 +91,9 @@
 QCryptoBlockCreateOptions *
 block_crypto_create_opts_init(QDict *opts, Error **errp);
 
+QCryptoBlockAmendOptions *
+block_crypto_amend_opts_init(QDict *opts, Error **errp);
+
 QCryptoBlockOpenOptions *
 block_crypto_open_opts_init(QDict *opts, Error **errp);
 
diff --git a/crypto/block.c b/crypto/block.c
index 6f42b32f1e..eb057948b5 100644
--- a/crypto/block.c
+++ b/crypto/block.c
@@ -150,6 +150,35 @@ 
qcrypto_block_calculate_payload_offset(QCryptoBlockCreateOptions *create_opts,
 return crypto != NULL;
 }
 
+int qcrypto_block_amend_options(QCryptoBlock *block,
+QCryptoBlockReadFunc readfunc,
+QCryptoBlockWriteFunc writefunc,
+void *opaque,
+QCryptoBlockAmendOptions *options,
+bool force,
+Error **errp)
+{
+if (options->format != block->format) {
+error_setg(errp,
+   "Cannot amend encryption format");
+return -1;
+}
+
+if (!block->driver->amend) {
+error_setg(errp,
+   "Crypto format %s doesn't support format options amendment",
+   QCryptoBlockFormat_str(block->format));
+return -1;
+}
+
+return block->driver->amend(block,
+readfunc,
+writefunc,
+opaque,
+options,
+force,
+errp);
+}
 
 QCryptoBlockInfo *qcrypto_block_get_info(QCryptoBlock *block,
  Error **errp)
diff --git a/crypto/blockpriv.h b/crypto/blockpriv.h
index 71c59cb542..3c7ccea504 100644
--- a/crypto/blockpriv.h
+++ b/crypto/blockpriv.h
@@ -62,6 +62,14 @@ struct QCryptoBlockDriver {
   void *opaque,
   Error **errp);
 
+int (*amend)(QCryptoBlock *block,
+ QCryptoBlockReadFunc readfunc,
+ QCryptoBlockWriteFunc writefunc,
+ void *opaque,
+ QCryptoBlockAmendOptions *options,
+ bool force,
+ Error **errp);
+
 int (*get_info)(QCryptoBlock *block,
 QCryptoBlockInfo *info,
 Error **errp);
diff --git a/include/crypto/block.h b/include/crypto/block.h
index c77ccaf9c0..d274819791 100644
--- a/include/crypto/block.h
+++ b/include/crypto/block.h
@@ -144,6 +144,28 @@ QCryptoBlock 
*qcrypto_block_create(QCryptoBlockCreateOptions *options,
void *opaque,
Error **errp);
 
+/**
+ * qcrypto_block_amend_options:
+ * @block: the block encryption object
+ *
+ * @readfunc: callback for reading data from the volume header
+ * @writefunc: callback for writing data to the volume header
+ * @opaque: data to pass to @readfunc and @writefunc
+ * @options: the new/amended encryption options
+ * @force: hint for the driver to allow unsafe operation
+ * @errp: error pointer
+ *
+ * Changes the crypto options of the encryption format
+ *
+ */
+int qcrypto_block_amend_options(QCryptoBlock *block,
+QCryptoBlockReadFunc readfunc,
+QCryptoBlockWriteFunc writefunc,
+void *opaque,
+QCryptoBlockAmendOptions *options,
+bool force,
+Error **errp);
+
 
 /**
  * 

[PATCH v3 07/14] block/crypto: implement the encryption key management

[Maxim Levitsky]

This implements the encryption key management using the generic code in
qcrypto layer and exposes it to the user via qemu-img

This code adds another 'write_func' because the initialization
write_func works directly on the underlying file, and amend
works on instance of luks device.

This commit also adds a 'hack/workaround' I and Kevin Wolf (thanks)
made to make the driver both support write sharing (to avoid breaking the 
users),
and be safe against concurrent  metadata update (the keyslots)

Eventually the write sharing for luks driver will be deprecated
and removed together with this hack.

The hack is that we ask (as a format driver) for BLK_PERM_CONSISTENT_READ
and then when we want to update the keys, we unshare that permission.
So if someone else has the image open, even readonly, encryption
key update will fail gracefully.

Also thanks to Daniel Berrange for the idea of
unsharing read, rather that write permission which allows
to avoid cases when the other user had opened the image read-only.

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/crypto.c | 127 +++--
 block/crypto.h |  34 +
 2 files changed, 158 insertions(+), 3 deletions(-)

diff --git a/block/crypto.c b/block/crypto.c
index 13ca1ad891..b71e57f777 100644
--- a/block/crypto.c
+++ b/block/crypto.c
@@ -37,6 +37,7 @@ typedef struct BlockCrypto BlockCrypto;
 
 struct BlockCrypto {
 QCryptoBlock *block;
+bool updating_keys;
 };
 
 
@@ -71,6 +72,24 @@ static ssize_t block_crypto_read_func(QCryptoBlock *block,
 return ret;
 }
 
+static ssize_t block_crypto_write_func(QCryptoBlock *block,
+   size_t offset,
+   const uint8_t *buf,
+   size_t buflen,
+   void *opaque,
+   Error **errp)
+{
+BlockDriverState *bs = opaque;
+ssize_t ret;
+
+ret = bdrv_pwrite(bs->file, offset, buf, buflen);
+if (ret < 0) {
+error_setg_errno(errp, -ret, "Could not write encryption header");
+return ret;
+}
+return ret;
+}
+
 
 struct BlockCryptoCreateData {
 BlockBackend *blk;
@@ -149,6 +168,19 @@ static QemuOptsList block_crypto_create_opts_luks = {
 };
 
 
+static QemuOptsList block_crypto_amend_opts_luks = {
+.name = "crypto",
+.head = QTAILQ_HEAD_INITIALIZER(block_crypto_create_opts_luks.head),
+.desc = {
+BLOCK_CRYPTO_OPT_DEF_LUKS_STATE(""),
+BLOCK_CRYPTO_OPT_DEF_LUKS_KEYSLOT(""),
+BLOCK_CRYPTO_OPT_DEF_LUKS_OLD_SECRET(""),
+BLOCK_CRYPTO_OPT_DEF_LUKS_NEW_SECRET(""),
+BLOCK_CRYPTO_OPT_DEF_LUKS_ITER_TIME(""),
+{ /* end of list */ }
+},
+};
+
 QCryptoBlockOpenOptions *
 block_crypto_open_opts_init(QDict *opts, Error **errp)
 {
@@ -742,6 +774,95 @@ block_crypto_get_specific_info_luks(BlockDriverState *bs, 
Error **errp)
 return spec_info;
 }
 
+static int
+block_crypto_amend_options_luks(BlockDriverState *bs,
+QemuOpts *opts,
+BlockDriverAmendStatusCB *status_cb,
+void *cb_opaque,
+bool force,
+Error **errp)
+{
+BlockCrypto *crypto = bs->opaque;
+QDict *cryptoopts = NULL;
+QCryptoBlockAmendOptions *amend_options = NULL;
+int ret;
+
+assert(crypto);
+assert(crypto->block);
+crypto->updating_keys = true;
+
+ret = bdrv_child_refresh_perms(bs, bs->file, errp);
+if (ret < 0) {
+goto cleanup;
+}
+
+cryptoopts = qemu_opts_to_qdict(opts, NULL);
+qdict_put_str(cryptoopts, "format", "luks");
+amend_options = block_crypto_amend_opts_init(cryptoopts, errp);
+if (!amend_options) {
+ret = -EINVAL;
+goto cleanup;
+}
+
+ret = qcrypto_block_amend_options(crypto->block,
+  block_crypto_read_func,
+  block_crypto_write_func,
+  bs,
+  amend_options,
+  force,
+  errp);
+cleanup:
+crypto->updating_keys = false;
+bdrv_child_refresh_perms(bs, bs->file, errp);
+qapi_free_QCryptoBlockAmendOptions(amend_options);
+qobject_unref(cryptoopts);
+return ret;
+}
+
+
+static void
+block_crypto_child_perms(BlockDriverState *bs, BdrvChild *c,
+ const BdrvChildRole *role,
+ BlockReopenQueue *reopen_queue,
+ uint64_t perm, uint64_t shared,
+ uint64_t *nperm, uint64_t *nshared)
+{
+
+BlockCrypto *crypto = bs->opaque;
+
+bdrv_filter_default_perms(bs, c, role, reopen_queue,
+perm, shared, nperm, nshared);
+/*
+ * Ask for 

[PATCH v3 00/14] LUKS: encryption slot management using amend interface

[Maxim Levitsky]

Hi!
Here is the updated series of my patches, incorporating all the feedback I 
received.

This implements the API interface that we agreed upon except that I merged the
LUKSKeyslotActive/LUKSKeyslotInactive union into a struct because otherwise
I need nested unions which are not supported currently by QAPI parser.
This didn't change the API and thus once support for nested unions is there,
it can always be implemented in backward compatible way.

I hope that this series will finally be considered for merging, since I am 
somewhat running
out of time to finish this task.

Patches are strictly divided by topic to 3 groups, and each group depends on 
former groups.

* Patches 1,2 implement qcrypto generic amend interface, including definition
  of structs used in crypto.json and implement this in luks crypto driver
  Nothing is exposed to the user at this stage

* Patches 3-9 use the code from patches 1,2 to implement qemu-img amend based 
encryption slot management
  for luks and for qcow2, and add a bunch of iotests to cover that.

* Patches 10-13 add x-blockdev-amend (I'll drop the -x prefix if you like), and 
wire it
  to luks and qcow2 driver to implement qmp based encryption slot management 
also using
  the code from patches 1,2, and also add a bunch of iotests to cover this.

Tested with -raw,-qcow2 and -luks iotests and 'make check'

V3: rebased, addressed most of the review feedback.
For now I kept the slot bitmap code since I am not sure that replacing it will 
be better.

Best regards,
Maxim Levitsky

clone of "luks-keymgmnt-v2"

Maxim Levitsky (14):
  qcrypto/core: add generic infrastructure for crypto options amendment
  qcrypto/luks: implement encryption key management
  block/amend: add 'force' option
  block/amend: separate amend and create options for qemu-img
  block/amend: refactor qcow2 amend options
  block/crypto: rename two functions
  block/crypto: implement the encryption key management
  block/qcow2: extend qemu-img amend interface with crypto options
  iotests: filter few more luks specific create options
  iotests: qemu-img tests for luks key management
  block/core: add generic infrastructure for x-blockdev-amend qmp
command
  block/crypto: implement blockdev-amend
  block/qcow2: implement blockdev-amend
  iotests: add tests for blockdev-amend

 block.c  |   4 +-
 block/Makefile.objs  |   2 +-
 block/amend.c| 108 
 block/crypto.c   | 203 ++--
 block/crypto.h   |  37 +++
 block/qcow2.c| 306 +--
 crypto/block-luks.c  | 406 ++-
 crypto/block.c   |  29 +++
 crypto/blockpriv.h   |   8 +
 docs/tools/qemu-img.rst  |   5 +-
 include/block/block.h|   1 +
 include/block/block_int.h|  24 +-
 include/crypto/block.h   |  22 ++
 qapi/block-core.json |  68 ++
 qapi/crypto.json |  75 +-
 qapi/job.json|   4 +-
 qemu-img-cmds.hx |   4 +-
 qemu-img.c   |  44 +++-
 tests/qemu-iotests/049.out   | 102 
 tests/qemu-iotests/061.out   |  12 +-
 tests/qemu-iotests/079.out   |  18 +-
 tests/qemu-iotests/082.out   | 176 --
 tests/qemu-iotests/085.out   |  38 +--
 tests/qemu-iotests/087.out   |   6 +-
 tests/qemu-iotests/115.out   |   2 +-
 tests/qemu-iotests/121.out   |   4 +-
 tests/qemu-iotests/125.out   | 192 +++
 tests/qemu-iotests/134.out   |   2 +-
 tests/qemu-iotests/144.out   |   4 +-
 tests/qemu-iotests/158.out   |   4 +-
 tests/qemu-iotests/182.out   |   2 +-
 tests/qemu-iotests/185.out   |   8 +-
 tests/qemu-iotests/188.out   |   2 +-
 tests/qemu-iotests/189.out   |   4 +-
 tests/qemu-iotests/198.out   |   4 +-
 tests/qemu-iotests/243.out   |  16 +-
 tests/qemu-iotests/250.out   |   2 +-
 tests/qemu-iotests/255.out   |   8 +-
 tests/qemu-iotests/263.out   |   4 +-
 tests/qemu-iotests/274.out   |  46 ++--
 tests/qemu-iotests/280.out   |   2 +-
 tests/qemu-iotests/284.out   |   6 +-
 tests/qemu-iotests/300   | 207 
 tests/qemu-iotests/300.out   |  99 
 tests/qemu-iotests/301   |  90 +++
 tests/qemu-iotests/301.out   |  30 +++
 tests/qemu-iotests/302   | 278 +
 tests/qemu-iotests/302.out   |  40 +++
 tests/qemu-iotests/303   | 233 ++
 tests/qemu-iotests/303.out   |  33 +++
 tests/qemu-iotests/common.filter |   6 +-
 tests/qemu-iotests/group |   5 +
 52 files changed, 2503 insertions(+), 532 deletions(-)
 create mode 100644 block/amend.c
 create mode 100755 tests/qemu-iotests/300
 create mode 100644 tests/qemu-iotests/300.out
 create mode 100755 tests/qemu-iotests/301
 create mode 100644 

[PATCH v3 04/14] block/amend: separate amend and create options for qemu-img

[Maxim Levitsky]

Some options are only useful for creation
(or hard to be amended, like cluster size for qcow2), while some other
options are only useful for amend, like upcoming keyslot management
options for luks

Since currently only qcow2 supports amend, move all its options
to a common macro and then include it in each action option list.

In future it might be useful to remove some options which are
not supported anyway from amend list, which currently
cause an error message if amended.

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block/qcow2.c | 160 +-
 include/block/block_int.h |   4 +
 qemu-img.c|  18 ++---
 3 files changed, 100 insertions(+), 82 deletions(-)

diff --git a/block/qcow2.c b/block/qcow2.c
index ffb6b22e2d..13780b0278 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -5495,83 +5495,96 @@ void qcow2_signal_corruption(BlockDriverState *bs, bool 
fatal, int64_t offset,
 s->signaled_corruption = true;
 }
 
+#define QCOW_COMMON_OPTIONS \
+{   \
+.name = BLOCK_OPT_SIZE, \
+.type = QEMU_OPT_SIZE,  \
+.help = "Virtual disk size" \
+},  \
+{   \
+.name = BLOCK_OPT_COMPAT_LEVEL, \
+.type = QEMU_OPT_STRING,\
+.help = "Compatibility level (v2 [0.10] or v3 [1.1])"   \
+},  \
+{   \
+.name = BLOCK_OPT_BACKING_FILE, \
+.type = QEMU_OPT_STRING,\
+.help = "File name of a base image" \
+},  \
+{   \
+.name = BLOCK_OPT_BACKING_FMT,  \
+.type = QEMU_OPT_STRING,\
+.help = "Image format of the base image"\
+},  \
+{   \
+.name = BLOCK_OPT_DATA_FILE,\
+.type = QEMU_OPT_STRING,\
+.help = "File name of an external data file"\
+},  \
+{   \
+.name = BLOCK_OPT_DATA_FILE_RAW,\
+.type = QEMU_OPT_BOOL,  \
+.help = "The external data file must stay valid "   \
+"as a raw image"\
+},  \
+{   \
+.name = BLOCK_OPT_ENCRYPT,  \
+.type = QEMU_OPT_BOOL,  \
+.help = "Encrypt the image with format 'aes'. (Deprecated " \
+"in favor of " BLOCK_OPT_ENCRYPT_FORMAT "=aes)",\
+},  \
+{   \
+.name = BLOCK_OPT_ENCRYPT_FORMAT,   \
+.type = QEMU_OPT_STRING,\
+.help = "Encrypt the image, format choices: 'aes', 'luks'", \
+},  \
+BLOCK_CRYPTO_OPT_DEF_KEY_SECRET("encrypt.", \
+"ID of secret providing qcow AES key or LUKS passphrase"),  \
+BLOCK_CRYPTO_OPT_DEF_LUKS_CIPHER_ALG("encrypt."),   \
+BLOCK_CRYPTO_OPT_DEF_LUKS_CIPHER_MODE("encrypt."),  \
+BLOCK_CRYPTO_OPT_DEF_LUKS_IVGEN_ALG("encrypt."),\
+BLOCK_CRYPTO_OPT_DEF_LUKS_IVGEN_HASH_ALG("encrypt."),   \
+BLOCK_CRYPTO_OPT_DEF_LUKS_HASH_ALG("encrypt."), \
+BLOCK_CRYPTO_OPT_DEF_LUKS_ITER_TIME("encrypt."),\
+{   \
+.name = BLOCK_OPT_CLUSTER_SIZE, \
+.type = QEMU_OPT_SIZE,  \
+.help = "qcow2 cluster size",   \
+.def_value_str = stringify(DEFAULT_CLUSTER_SIZE)\
+},  

[PATCH v3 03/14] block/amend: add 'force' option

[Maxim Levitsky]

'force' option will be used for some unsafe amend operations.

This includes things like erasing last keyslot in luks based formats
(which destroys the data, unless the master key is backed up
by external means), but that _might_ be desired result.

Signed-off-by: Maxim Levitsky 
Reviewed-by: Daniel P. Berrangé 
---
 block.c   | 4 +++-
 block/qcow2.c | 1 +
 docs/tools/qemu-img.rst   | 5 -
 include/block/block.h | 1 +
 include/block/block_int.h | 1 +
 qemu-img-cmds.hx  | 4 ++--
 qemu-img.c| 8 +++-
 7 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/block.c b/block.c
index 301ec588bd..fe692202a9 100644
--- a/block.c
+++ b/block.c
@@ -6377,6 +6377,7 @@ void bdrv_remove_aio_context_notifier(BlockDriverState 
*bs,
 
 int bdrv_amend_options(BlockDriverState *bs, QemuOpts *opts,
BlockDriverAmendStatusCB *status_cb, void *cb_opaque,
+   bool force,
Error **errp)
 {
 if (!bs->drv) {
@@ -6388,7 +6389,8 @@ int bdrv_amend_options(BlockDriverState *bs, QemuOpts 
*opts,
bs->drv->format_name);
 return -ENOTSUP;
 }
-return bs->drv->bdrv_amend_options(bs, opts, status_cb, cb_opaque, errp);
+return bs->drv->bdrv_amend_options(bs, opts, status_cb,
+   cb_opaque, force, errp);
 }
 
 /*
diff --git a/block/qcow2.c b/block/qcow2.c
index 2ba0b17c39..ffb6b22e2d 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -5200,6 +5200,7 @@ static void qcow2_amend_helper_cb(BlockDriverState *bs,
 static int qcow2_amend_options(BlockDriverState *bs, QemuOpts *opts,
BlockDriverAmendStatusCB *status_cb,
void *cb_opaque,
+   bool force,
Error **errp)
 {
 BDRVQcow2State *s = bs->opaque;
diff --git a/docs/tools/qemu-img.rst b/docs/tools/qemu-img.rst
index 0080f83a76..fc2dca6649 100644
--- a/docs/tools/qemu-img.rst
+++ b/docs/tools/qemu-img.rst
@@ -249,11 +249,14 @@ Command description:
 
 .. program:: qemu-img-commands
 
-.. option:: amend [--object OBJECTDEF] [--image-opts] [-p] [-q] [-f FMT] [-t 
CACHE] -o OPTIONS FILENAME
+.. option:: amend [--object OBJECTDEF] [--image-opts] [-p] [-q] [-f FMT] [-t 
CACHE] [--force] -o OPTIONS FILENAME
 
   Amends the image format specific *OPTIONS* for the image file
   *FILENAME*. Not all file formats support this operation.
 
+  --force allows some unsafe operations. Currently for -f luks, it allows to
+  erase last encryption key, and to overwrite an active encryption key.
+
 .. option:: bench [-c COUNT] [-d DEPTH] [-f FMT] 
[--flush-interval=FLUSH_INTERVAL] [-i AIO] [-n] [--no-drain] [-o OFFSET] 
[--pattern=PATTERN] [-q] [-s BUFFER_SIZE] [-S STEP_SIZE] [-t CACHE] [-w] [-U] 
FILENAME
 
   Run a simple sequential I/O benchmark on the specified image. If ``-w`` is
diff --git a/include/block/block.h b/include/block/block.h
index 8b62429aa4..0ca53b5598 100644
--- a/include/block/block.h
+++ b/include/block/block.h
@@ -392,6 +392,7 @@ typedef void BlockDriverAmendStatusCB(BlockDriverState *bs, 
int64_t offset,
   int64_t total_work_size, void *opaque);
 int bdrv_amend_options(BlockDriverState *bs_new, QemuOpts *opts,
BlockDriverAmendStatusCB *status_cb, void *cb_opaque,
+   bool force,
Error **errp);
 
 /* check if a named node can be replaced when doing drive-mirror */
diff --git a/include/block/block_int.h b/include/block/block_int.h
index 92335f33c7..98671ecdf6 100644
--- a/include/block/block_int.h
+++ b/include/block/block_int.h
@@ -432,6 +432,7 @@ struct BlockDriver {
 int (*bdrv_amend_options)(BlockDriverState *bs, QemuOpts *opts,
   BlockDriverAmendStatusCB *status_cb,
   void *cb_opaque,
+  bool force,
   Error **errp);
 
 void (*bdrv_debug_event)(BlockDriverState *bs, BlkdebugEvent event);
diff --git a/qemu-img-cmds.hx b/qemu-img-cmds.hx
index c9c54de1df..9920f1f9d4 100644
--- a/qemu-img-cmds.hx
+++ b/qemu-img-cmds.hx
@@ -10,9 +10,9 @@ HXCOMM When amending the rST sections, please remember to 
copy the usage
 HXCOMM over to the per-command sections in qemu-img.texi.
 
 DEF("amend", img_amend,
-"amend [--object objectdef] [--image-opts] [-p] [-q] [-f fmt] [-t cache] 
-o options filename")
+"amend [--object objectdef] [--image-opts] [-p] [-q] [-f fmt] [-t cache] 
[--force] -o options filename")
 SRST
-.. option:: amend [--object OBJECTDEF] [--image-opts] [-p] [-q] [-f FMT] [-t 
CACHE] -o OPTIONS FILENAME
+.. option:: amend [--object OBJECTDEF] [--image-opts] [-p] [-q] [-f FMT] [-t 
CACHE] [--force] -o OPTIONS FILENAME
 ERST
 
 DEF("bench", img_bench,
diff --git a/qemu-img.c b/qemu-img.c
index 6a4327aaba..ef422d5471 100644
--- 

[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs

[Heiko Sieger]

Finally installed QEMU 5.0.0.154 - still the same. QEMU doesn't
recognize the L3 caches and still lists 3 L3 caches instead of 4 with 3
cores/6 threads.

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https://bugs.launchpad.net/bugs/1856335

Title:
  Cache Layout wrong on many Zen Arch CPUs

Status in QEMU:
  New

Bug description:
  AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
  to always map Cache ass if it was an 4-Core per CCX CPU, which is
  incorrect, and costs upwards 30% performance (more realistically 10%)
  in L3 Cache Layout aware applications.

  Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):

    
  EPYC-IBPB
  AMD
  

  In windows, coreinfo reports correctly:

    Unified Cache 1, Level 3,8 MB, Assoc  16, LineSize  64
    Unified Cache 6, Level 3,8 MB, Assoc  16, LineSize  64

  On a 3-CCX CPU (3960X /w 6 cores and no SMT):

   
  EPYC-IBPB
  AMD
  

  in windows, coreinfo reports incorrectly:

  --  Unified Cache  1, Level 3,8 MB, Assoc  16, LineSize  64
  **  Unified Cache  6, Level 3,8 MB, Assoc  16, LineSize  64

  Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.

  With newer Qemu there is a fix (that does behave correctly) in using the dies 
parameter:
   

  The problem is that the dies are exposed differently than how AMD does
  it natively, they are exposed to Windows as sockets, which means, that
  if you are nto a business user, you can't ever have a machine with
  more than two CCX (6 cores) as consumer versions of Windows only
  supports two sockets. (Should this be reported as a separate bug?)

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[Bug 1862986] Re: qemu-s390x segfaults

[Marco]

This still happens on qemu 5.0

Steps to reproduce:

# install packages
dpkg --add-architecture s390x
apt update
apt install qemu-user libc6:s390x libstdc++6:s390x libfontconfig1:s390x 
libxcb1:s390x
apt install g++-s390x-linux-gnu

# create dummy binary
echo 'int main(){}'| s390x-linux-gnu-g++ -x c++ -

# run dummy binary
qemu-s390x ./a.out
Segmentation fault (core dumped)

** Summary changed:

- qemu-s390x crashes when run on aarch64
+ qemu-s390x segfaults

** Changed in: qemu
   Status: Expired => New

-- 
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https://bugs.launchpad.net/bugs/1862986

Title:
  qemu-s390x segfaults

Status in QEMU:
  New

Bug description:
  All tested versions (2.11 and 4.2) qemu-s390x crashes with a segfault
  when run on an aarch64 odroid Ubuntu.


  Steps to reproduce:

  root@odroid:~/workspace/bitcoin-core# /usr/local/bin/qemu-s390x 
"/root/workspace/bitcoin-core/build/bitcoin-s390x-linux-gnu/src/test/test_bitcoin_orig"
  Segmentation fault (core dumped)
  root@odroid:~/workspace/bitcoin-core# /usr/local/bin/qemu-s390x --version
  qemu-s390x version 4.2.0
  Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers
  root@odroid:~/workspace/bitcoin-core# /usr/bin/qemu-s390x 
"/root/workspace/bitcoin-core/build/bitcoin-s390x-linux-gnu/src/test/test_bitcoin_orig"
  Segmentation fault (core dumped)
  root@odroid:~/workspace/bitcoin-core# /usr/bin/qemu-s390x --version
  qemu-s390x version 2.11.1(Debian 1:2.11+dfsg-1ubuntu7.22)
  Copyright (c) 2003-2017 Fabrice Bellard and the QEMU Project developers

  qemu-arm does work on the same machine:

  root@odroid:~/workspace/bitcoin-core# /usr/bin/qemu-arm 
bitcoin-0.19.0.1-armhf/bin/test_bitcoin -t amount_tests
  Running 4 test cases...

  *** No errors detected
  root@odroid:~/workspace/bitcoin-core# /usr/local/bin/qemu-arm 
bitcoin-0.19.0.1-armhf/bin/test_bitcoin -t amount_tests
  Running 4 test cases...

  *** No errors detected


  
  What kind of debug information would be helpful for this issue report?
  GDB for the self-compiled latest release is not particularly helpful:

  (gdb) run
  Starting program: /usr/local/bin/qemu-s390x 
/root/workspace/bitcoin-core/build/bitcoin-s390x-linux-gnu/src/test/test_bitcoin_orig
  [Thread debugging using libthread_db enabled]
  Using host libthread_db library "/lib/aarch64-linux-gnu/libthread_db.so.1".
  [New Thread 0x7fb7a2a140 (LWP 28264)]

  Thread 1 "qemu-s390x" received signal SIGSEGV, Segmentation fault.
  0x0096b218 in __bss_start__ ()
  (gdb) bt
  #0  0x0096b218 in __bss_start__ ()
  #1  0x006120a8 in ?? ()
  #2  0x0055579904b0 in ?? ()
  Backtrace stopped: previous frame inner to this frame (corrupt stack?)


  
  A bit more information is available in the version shipped by Ubuntu:

  (gdb) run
  Starting program: /usr/bin/qemu-s390x 
/root/workspace/bitcoin-core/build/bitcoin-s390x-linux-gnu/src/test/test_bitcoin_orig
  [Thread debugging using libthread_db enabled]
  Using host libthread_db library "/lib/aarch64-linux-gnu/libthread_db.so.1".
  [New Thread 0x7fb7a01180 (LWP 28271)]

  Thread 1 "qemu-s390x" received signal SIGSEGV, Segmentation fault.
  0x00738f98 in code_gen_buffer ()
  (gdb) bt
  #0  0x00738f98 in code_gen_buffer ()
  #1  0x005e96c8 in cpu_exec ()
  #2  0x005ee430 in cpu_loop ()
  #3  0x005c3328 in main ()

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Re: [RFC PATCH 2/2] linux-user/mmap: Fix Clang 'type-limit-compare' warning

[Richard Henderson]

On 5/3/20 5:49 AM, Aleksandar Markovic wrote:
> нед, 3. мај 2020. у 13:33 Philippe Mathieu-Daudé  је
> написао/ла:
>>
>> When building with Clang 10 on Fedora 32, we get:
>>
>> CC  linux-user/mmap.o
>>   linux-user/mmap.c:720:49: error: result of comparison 'unsigned long' > 
>> 18446744073709551615 is always false 
>> [-Werror,-Wtautological-type-limit-compare]
>>   if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
>>   ~~~ ^ ~
>>
>> Fix by restricting the check for when target sizeof(abi_ulong) is
>> smaller than target sizeof(unsigned long).
>>
>> Signed-off-by: Philippe Mathieu-Daudé 
>> ---
>>  linux-user/mmap.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/linux-user/mmap.c b/linux-user/mmap.c
>> index e378033797..b14652d894 100644
>> --- a/linux-user/mmap.c
>> +++ b/linux-user/mmap.c
>> @@ -714,6 +714,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
>> old_size,
>>  errno = ENOMEM;
>>  host_addr = MAP_FAILED;
>>  }
>> +#if TARGET_ABI_BITS < TARGET_LONG_BITS
>>  /* Check if address fits target address space */
>>  if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
>>  /* Revert mremap() changes */
>> @@ -721,6 +722,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
>> old_size,
>>  errno = ENOMEM;
>>  host_addr = MAP_FAILED;
>>  }
>> +#endif /* TARGET_ABI_BITS < TARGET_LONG_BITS */
> 
> Hm, Philippe, this will silence the clang error, but is this the right
> thing to do?
> 
> Why do you think the case:
> 
> TARGET_ABI_BITS < TARGET_LONG_BITS
> 
> doesn't need this check?

I think that's quite obvious from the clang warning -- the test is always false
due to type limits.

That said, this is at minimum the second occurrence of having to add ifdefs to
work around this particular new warning, because there does not seem to be any
other way to suppress the warning, and I'm not keen on that.

I would prefer that we disable the warning on the compiler command line in
configure.


r~

Re: [RFC PATCH 1/2] audio/mixeng: Fix Clang 'int-conversion' warning

[Richard Henderson]

On 5/3/20 4:32 AM, Philippe Mathieu-Daudé wrote:
> When building with Clang 10 on Fedora 32, we get:
> 
> CC  audio/mixeng.o
>   audio/mixeng.c:274:34: error: implicit conversion from 'unsigned int' to 
> 'float' changes value from 4294967295 to 4294967296 
> [-Werror,-Wimplicit-int-float-conversion]
>   static const float float_scale = UINT_MAX / 2.f;
>^~~~ ~
>   /usr/lib64/clang/10.0.0/include/limits.h:56:37: note: expanded from macro 
> 'UINT_MAX'
>   #define UINT_MAX  (__INT_MAX__  *2U +1U)
>  ~^~~
> 
> Fix by using a 64-bit float for the conversion, before casting
> back to 32-bit float.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  audio/mixeng.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

No, this should be fixed properly.

First, the warning is in the !FLOAT_MIXENG branch.  IMO that means we should
not be using floating point at all, and this should be a simple integral
multiply/shift.

I had a brief look at this before the 5.0 release.  The arithmetic all through
audio looks confused to me.  There's a combination of shifting and masking
(implying a scale by 1<<32), and multiplication and division by UINT32_MAX.

I'm reasonably certain that every appearance of UINT32_MAX in this code is an
off-by-one bug, or a misuse of the constant.


r~

[PATCH] Fix iotest 153

[Maxim Levitsky]

Commit f62514b3def5fb2acbef64d0e053c0c31fa45aff made qemu-img reject -o "" but 
this test uses it

Since this test only tries to do a dry-run run of qemu-img amend, replace the 
-o "" with
dummy -o "size=0" since due to the nature of the test, it is not going
to reach the actual amend operation anyway

Fixes: f62514b3def5fb2acbef64d0e053c0c31fa45aff

Signed-off-by: Maxim Levitsky 
---
 tests/qemu-iotests/153 |  2 +-
 tests/qemu-iotests/153.out | 12 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/qemu-iotests/153 b/tests/qemu-iotests/153
index 2b13111768..3f5029dd8f 100755
--- a/tests/qemu-iotests/153
+++ b/tests/qemu-iotests/153
@@ -122,7 +122,7 @@ for opts1 in "" "read-only=on" 
"read-only=on,force-share=on"; do
 _run_cmd $QEMU_IMG check   $L "${TEST_IMG}"
 _run_cmd $QEMU_IMG compare $L "${TEST_IMG}" "${TEST_IMG}"
 _run_cmd $QEMU_IMG map $L "${TEST_IMG}"
-_run_cmd $QEMU_IMG amend -o "" $L "${TEST_IMG}"
+_run_cmd $QEMU_IMG amend -o "size=0" $L "${TEST_IMG}"
 _run_cmd $QEMU_IMG commit  $L "${TEST_IMG}"
 _run_cmd $QEMU_IMG resize  $L "${TEST_IMG}" $size
 _run_cmd $QEMU_IMG rebase  $L "${TEST_IMG}" -b "${TEST_IMG}.base"
diff --git a/tests/qemu-iotests/153.out b/tests/qemu-iotests/153.out
index f7464dd8d3..9c01b750e0 100644
--- a/tests/qemu-iotests/153.out
+++ b/tests/qemu-iotests/153.out
@@ -56,7 +56,7 @@ _qemu_img_wrapper map TEST_DIR/t.qcow2
 qemu-img: Could not open 'TEST_DIR/t.qcow2': Failed to get shared "write" lock
 Is another process using the image [TEST_DIR/t.qcow2]?
 
-_qemu_img_wrapper amend -o  TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 TEST_DIR/t.qcow2
 qemu-img: Could not open 'TEST_DIR/t.qcow2': Failed to get "write" lock
 Is another process using the image [TEST_DIR/t.qcow2]?
 
@@ -118,7 +118,7 @@ _qemu_img_wrapper compare -U TEST_DIR/t.qcow2 
TEST_DIR/t.qcow2
 
 _qemu_img_wrapper map -U TEST_DIR/t.qcow2
 
-_qemu_img_wrapper amend -o  -U TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 -U TEST_DIR/t.qcow2
 qemu-img: unrecognized option '-U'
 Try 'qemu-img --help' for more information
 
@@ -187,7 +187,7 @@ _qemu_img_wrapper compare TEST_DIR/t.qcow2 TEST_DIR/t.qcow2
 
 _qemu_img_wrapper map TEST_DIR/t.qcow2
 
-_qemu_img_wrapper amend -o  TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 TEST_DIR/t.qcow2
 qemu-img: Could not open 'TEST_DIR/t.qcow2': Failed to get "write" lock
 Is another process using the image [TEST_DIR/t.qcow2]?
 
@@ -241,7 +241,7 @@ _qemu_img_wrapper compare -U TEST_DIR/t.qcow2 
TEST_DIR/t.qcow2
 
 _qemu_img_wrapper map -U TEST_DIR/t.qcow2
 
-_qemu_img_wrapper amend -o  -U TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 -U TEST_DIR/t.qcow2
 qemu-img: unrecognized option '-U'
 Try 'qemu-img --help' for more information
 
@@ -303,7 +303,7 @@ _qemu_img_wrapper compare TEST_DIR/t.qcow2 TEST_DIR/t.qcow2
 
 _qemu_img_wrapper map TEST_DIR/t.qcow2
 
-_qemu_img_wrapper amend -o  TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 TEST_DIR/t.qcow2
 
 _qemu_img_wrapper commit TEST_DIR/t.qcow2
 
@@ -345,7 +345,7 @@ _qemu_img_wrapper compare -U TEST_DIR/t.qcow2 
TEST_DIR/t.qcow2
 
 _qemu_img_wrapper map -U TEST_DIR/t.qcow2
 
-_qemu_img_wrapper amend -o  -U TEST_DIR/t.qcow2
+_qemu_img_wrapper amend -o size=0 -U TEST_DIR/t.qcow2
 qemu-img: unrecognized option '-U'
 Try 'qemu-img --help' for more information
 
-- 
2.17.2

Re: [PATCH 2/2] arm/acpi: Add the TPM2.0 device under the DSDT

[Stefan Berger]

On 5/2/20 4:35 PM, Eric Auger wrote:

In case it is dynamically instantiated, add the TPM 2.0 device object
under the DSDT table in the ACPI namespace. Its HID is MSFT0101
while its current resource settings (CRS) property is initialized
with the guest physical address and MMIO size of the device.

Signed-off-by: Eric Auger 
---
  hw/arm/virt-acpi-build.c | 34 ++
  1 file changed, 34 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index cc5863eaf2..0cb9cdb2ce 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -45,6 +45,7 @@
  #include "hw/pci/pcie_host.h"
  #include "hw/pci/pci.h"
  #include "hw/arm/virt.h"
+#include "hw/platform-bus.h"
  #include "sysemu/numa.h"
  #include "sysemu/reset.h"
  #include "sysemu/tpm.h"
@@ -362,6 +363,38 @@ static void acpi_dsdt_add_power_button(Aml *scope)
  aml_append(scope, dev);
  }
  
+static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)

+{
+hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
+PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+MemoryRegion *sbdev_mr;
+SysBusDevice *sbdev;
+hwaddr tpm_base;
+
+sbdev = (SysBusDevice *)object_dynamic_cast(OBJECT(tpm_find()),
+TYPE_SYS_BUS_DEVICE);
+if (!sbdev) {
+return;
+}
+
+tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+assert(tpm_base != -1);
+
+tpm_base += pbus_base;
+
+sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
+
+Aml *dev = aml_device("TPM0");
+aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs,
+   aml_memory32_fixed(tpm_base, sbdev_mr->size, AML_READ_WRITE));
+aml_append(dev, aml_name_decl("_CRS", crs));
+aml_append(scope, dev);
+}
+
  static void
  build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
  {
@@ -785,6 +818,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, 
VirtMachineState *vms)
  }
  
  acpi_dsdt_add_power_button(scope);

+acpi_dsdt_add_tpm(scope, vms);
  
  aml_append(dsdt, scope);
  


Reviewed-by: Stefan Berger 

Re: [PATCH 1/2] arm/acpi: TPM2 ACPI table support

[Stefan Berger]

On 5/2/20 4:35 PM, Eric Auger wrote:

Add a TPM2 ACPI table if a TPM2.0 sysbus device has been
dynamically instantiated.

Signed-off-by: Eric Auger 
---
  include/sysemu/tpm.h |  2 ++
  hw/arm/virt-acpi-build.c | 36 
  2 files changed, 38 insertions(+)

diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h
index f37851b1aa..03fb25941c 100644
--- a/include/sysemu/tpm.h
+++ b/include/sysemu/tpm.h
@@ -50,6 +50,8 @@ typedef struct TPMIfClass {
  
  #define TPM_IS_TIS_ISA(chr) \

  object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_ISA)
+#define TPM_IS_TIS_SYSBUS(chr)  \
+object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS_SYSBUS)
  #define TPM_IS_CRB(chr) \
  object_dynamic_cast(OBJECT(chr), TYPE_TPM_CRB)
  #define TPM_IS_SPAPR(chr)   \
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 81d41a3990..cc5863eaf2 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -41,11 +41,13 @@
  #include "hw/acpi/pci.h"
  #include "hw/acpi/memory_hotplug.h"
  #include "hw/acpi/generic_event_device.h"
+#include "hw/acpi/tpm.h"
  #include "hw/pci/pcie_host.h"
  #include "hw/pci/pci.h"
  #include "hw/arm/virt.h"
  #include "sysemu/numa.h"
  #include "sysemu/reset.h"
+#include "sysemu/tpm.h"
  #include "kvm_arm.h"
  #include "migration/vmstate.h"
  
@@ -704,6 +706,35 @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,

  build_fadt(table_data, linker, , NULL, NULL);
  }
  
+static void

+build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
+{
+Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
+unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
+unsigned log_addr_offset =
+(char *)_ptr->log_area_start_address - table_data->data;
+
+tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
+if (TPM_IS_TIS_SYSBUS(tpm_find())) {
+tpm2_ptr->control_area_address = cpu_to_le64(0);
+tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
+} else {
+g_warn_if_reached();
+}
+
+tpm2_ptr->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
+acpi_data_push(tcpalog, le32_to_cpu(tpm2_ptr->log_area_minimum_length));
+
+/* log area start address to be filled by Guest linker */
+bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE,
+ tcpalog, 1, false);
+bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+   log_addr_offset, log_addr_size,
+   ACPI_BUILD_TPMLOG_FILE, 0);
+build_header(linker, table_data,
+ (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
+}
+
  /* DSDT */
  static void
  build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
@@ -831,6 +862,11 @@ void virt_acpi_build(VirtMachineState *vms, 
AcpiBuildTables *tables)
  build_iort(tables_blob, tables->linker, vms);
  }
  
+if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {

+acpi_add_table(table_offsets, tables_blob);
+build_tpm2(tables_blob, tables->linker, tables->tcpalog);
+}
+
  /* XSDT is pointed to by RSDP */
  xsdt = tables_blob->len;
  build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);


Reviewed-by: Stefan Berger 

Re: [Qemu-devel] [PULL 0/1] RDMA queue

[Peter Maydell]

On Sat, 2 May 2020 at 20:18, Marcel Apfelbaum
 wrote:
>
> The following changes since commit 1c47613588ccff44422d4bdeea0dc36a0a308ec7:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
> (2020-04-30 19:25:41 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/marcel-apf/qemu tags/rdma-pull-request
>
> for you to fetch changes up to a5cde048e865da81fdc9077f3af28a43bff78d35:
>
>   hw/rdma: Destroy list mutex when list is destroyed (2020-05-02 21:31:17 
> +0300)
>
> 
> RDMA queue
>
> * hw/rdma: Destroy list mutex when list is destroyed
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM

Re: [PULL 0/6] virtiofs queue

[Peter Maydell]

On Fri, 1 May 2020 at 20:16, Dr. David Alan Gilbert (git)
 wrote:
>
> From: "Dr. David Alan Gilbert" 
>
> The following changes since commit 1c47613588ccff44422d4bdeea0dc36a0a308ec7:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
> (2020-04-30 19:25:41 +0100)
>
> are available in the Git repository at:
>
>   https://gitlab.com/dagrh/qemu.git tags/pull-virtiofs-20200501
>
> for you to fetch changes up to 66502bbca37ca7a3bfa57e82cfc03b89a7a11eae:
>
>   virtiofsd: drop all capabilities in the wait parent process (2020-05-01 
> 20:05:37 +0100)
>
> 
> virtiofsd: Pull 2020-05-01 (includes CVE fix)
>
> This set includes a security fix, other fixes and improvements.
>
> Security fix:
> The security fix is for CVE-2020-10717 where, on low RAM hosts,
> the guest can potentially exceed the maximum fd limit.
> This fix adds some more configuration so that the user
> can explicitly set the limit.
> Thank you to Yuval Avrahami for reporting this.
>
> Fixes:
>
> Recursive mounting of the exported directory is now used in
> the sandbox, such that if there was a mount underneath present at
> the time the virtiofsd was started, that mount is also
> visible to the guest; in the existing code, only mounts that
> happened after startup were visible.
>
> Security improvements:
>
> The jailing for /proc/self/fd is improved - but it's something
> that shouldn't be accessible anyway.
>
> Most capabilities are now dropped at startup; again this shouldn't
> change any behaviour but is extra protection.
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

I notice you didn't include the usual Cc: qemu-sta...@nongnu.org
lines in the commits to be backported, but I think the stable
branch maintainers can deal with the occasional manual notification.

thanks
-- PMM

Re: [RFC PATCH 2/2] linux-user/mmap: Fix Clang 'type-limit-compare' warning

[Aleksandar Markovic]

нед, 3. мај 2020. у 14:49 Aleksandar Markovic
 је написао/ла:
>
> нед, 3. мај 2020. у 13:33 Philippe Mathieu-Daudé  је
> написао/ла:
> >
> > When building with Clang 10 on Fedora 32, we get:
> >
> > CC  linux-user/mmap.o
> >   linux-user/mmap.c:720:49: error: result of comparison 'unsigned long' > 
> > 18446744073709551615 is always false 
> > [-Werror,-Wtautological-type-limit-compare]
> >   if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
> >   ~~~ ^ ~
> >
> > Fix by restricting the check for when target sizeof(abi_ulong) is
> > smaller than target sizeof(unsigned long).
> >
> > Signed-off-by: Philippe Mathieu-Daudé 
> > ---
> >  linux-user/mmap.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/linux-user/mmap.c b/linux-user/mmap.c
> > index e378033797..b14652d894 100644
> > --- a/linux-user/mmap.c
> > +++ b/linux-user/mmap.c
> > @@ -714,6 +714,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
> > old_size,
> >  errno = ENOMEM;
> >  host_addr = MAP_FAILED;
> >  }
> > +#if TARGET_ABI_BITS < TARGET_LONG_BITS

Or, for that matter, a comment should be inserted before this
line with explanation why the check is not needed for this case.

I think QEMU is too full with unexplained "ifdefs", which, of
course, doesn't help readibility.

> >  /* Check if address fits target address space */
> >  if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
> >  /* Revert mremap() changes */
> > @@ -721,6 +722,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
> > old_size,
> >  errno = ENOMEM;
> >  host_addr = MAP_FAILED;
> >  }
> > +#endif /* TARGET_ABI_BITS < TARGET_LONG_BITS */
>
> Hm, Philippe, this will silence the clang error, but is this the right
> thing to do?
>
> Why do you think the case:
>
> TARGET_ABI_BITS < TARGET_LONG_BITS
>
> doesn't need this check? In any case, for clarity, the reason should
> be mentioned in the commit message.
>
> Regards,
> Aleksandar
>
>
> >  }
> >
> >  if (host_addr == MAP_FAILED) {
> > --
> > 2.21.3
> >
> >

Re: [RFC PATCH 1/2] audio/mixeng: Fix Clang 'int-conversion' warning

[BALATON Zoltan]

On Sun, 3 May 2020, Philippe Mathieu-Daudé wrote:

When building with Clang 10 on Fedora 32, we get:

   CC  audio/mixeng.o
 audio/mixeng.c:274:34: error: implicit conversion from 'unsigned int' to 
'float' changes value from 4294967295 to 4294967296 
[-Werror,-Wimplicit-int-float-conversion]
 static const float float_scale = UINT_MAX / 2.f;
  ^~~~ ~
 /usr/lib64/clang/10.0.0/include/limits.h:56:37: note: expanded from macro 
'UINT_MAX'
 #define UINT_MAX  (__INT_MAX__  *2U +1U)
~^~~

Fix by using a 64-bit float for the conversion, before casting
back to 32-bit float.

Signed-off-by: Philippe Mathieu-Daudé 
---
audio/mixeng.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/audio/mixeng.c b/audio/mixeng.c
index 739a500449..9946bfeaec 100644
--- a/audio/mixeng.c
+++ b/audio/mixeng.c
@@ -271,7 +271,7 @@ f_sample *mixeng_clip[2][2][2][3] = {
#define CONV_NATURAL_FLOAT(x) (x)
#define CLIP_NATURAL_FLOAT(x) (x)
#else
-static const float float_scale = UINT_MAX / 2.f;
+static const float float_scale = UINT_MAX / 2.;


Maybe writing it as 2.0 is easier to read and looks nicer.

Regards,
BALATON Zoltan

Re: [RFC PATCH 2/2] linux-user/mmap: Fix Clang 'type-limit-compare' warning

[Aleksandar Markovic]

нед, 3. мај 2020. у 13:33 Philippe Mathieu-Daudé  је
написао/ла:
>
> When building with Clang 10 on Fedora 32, we get:
>
> CC  linux-user/mmap.o
>   linux-user/mmap.c:720:49: error: result of comparison 'unsigned long' > 
> 18446744073709551615 is always false 
> [-Werror,-Wtautological-type-limit-compare]
>   if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
>   ~~~ ^ ~
>
> Fix by restricting the check for when target sizeof(abi_ulong) is
> smaller than target sizeof(unsigned long).
>
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  linux-user/mmap.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/linux-user/mmap.c b/linux-user/mmap.c
> index e378033797..b14652d894 100644
> --- a/linux-user/mmap.c
> +++ b/linux-user/mmap.c
> @@ -714,6 +714,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
> old_size,
>  errno = ENOMEM;
>  host_addr = MAP_FAILED;
>  }
> +#if TARGET_ABI_BITS < TARGET_LONG_BITS
>  /* Check if address fits target address space */
>  if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
>  /* Revert mremap() changes */
> @@ -721,6 +722,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
> old_size,
>  errno = ENOMEM;
>  host_addr = MAP_FAILED;
>  }
> +#endif /* TARGET_ABI_BITS < TARGET_LONG_BITS */

Hm, Philippe, this will silence the clang error, but is this the right
thing to do?

Why do you think the case:

TARGET_ABI_BITS < TARGET_LONG_BITS

doesn't need this check? In any case, for clarity, the reason should
be mentioned in the commit message.

Regards,
Aleksandar


>  }
>
>  if (host_addr == MAP_FAILED) {
> --
> 2.21.3
>
>

[Query] VM CPU scheduling

[Ramesh B]

Hi All,

I started recently using QEMU for OS virtualization.
Want to know/understand about scheduling.

Environment:
Host OS: Ubuntu 18.4 + KVM enable
QEMU: 4.2
Workstation/Desktop: x86_64

Would like to understand,

1. How CPU scheduling works.
2. Tools/commands to monitor.
3. Tuning parameter/API

Could you please suggest good reference or books or pointers.

Thanks,
Babu

[RFC PATCH 0/2] misc: fix Clang10 warnings

[Philippe Mathieu-Daudé]

Fix 2 warnings when building with Clang on Fedora32.

Philippe Mathieu-Daudé (2):
  audio/mixeng: Fix Clang 'int-conversion' warning
  linux-user/mmap: Fix Clang 'type-limit-compare' warning

 audio/mixeng.c| 2 +-
 linux-user/mmap.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

-- 
2.21.3

[RFC PATCH 2/2] linux-user/mmap: Fix Clang 'type-limit-compare' warning

[Philippe Mathieu-Daudé]

When building with Clang 10 on Fedora 32, we get:

CC  linux-user/mmap.o
  linux-user/mmap.c:720:49: error: result of comparison 'unsigned long' > 
18446744073709551615 is always false [-Werror,-Wtautological-type-limit-compare]
  if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
  ~~~ ^ ~

Fix by restricting the check for when target sizeof(abi_ulong) is
smaller than target sizeof(unsigned long).

Signed-off-by: Philippe Mathieu-Daudé 
---
 linux-user/mmap.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index e378033797..b14652d894 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -714,6 +714,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
old_size,
 errno = ENOMEM;
 host_addr = MAP_FAILED;
 }
+#if TARGET_ABI_BITS < TARGET_LONG_BITS
 /* Check if address fits target address space */
 if ((unsigned long)host_addr + new_size > (abi_ulong)-1) {
 /* Revert mremap() changes */
@@ -721,6 +722,7 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong 
old_size,
 errno = ENOMEM;
 host_addr = MAP_FAILED;
 }
+#endif /* TARGET_ABI_BITS < TARGET_LONG_BITS */
 }
 
 if (host_addr == MAP_FAILED) {
-- 
2.21.3

[RFC PATCH 1/2] audio/mixeng: Fix Clang 'int-conversion' warning

[Philippe Mathieu-Daudé]

When building with Clang 10 on Fedora 32, we get:

CC  audio/mixeng.o
  audio/mixeng.c:274:34: error: implicit conversion from 'unsigned int' to 
'float' changes value from 4294967295 to 4294967296 
[-Werror,-Wimplicit-int-float-conversion]
  static const float float_scale = UINT_MAX / 2.f;
   ^~~~ ~
  /usr/lib64/clang/10.0.0/include/limits.h:56:37: note: expanded from macro 
'UINT_MAX'
  #define UINT_MAX  (__INT_MAX__  *2U +1U)
 ~^~~

Fix by using a 64-bit float for the conversion, before casting
back to 32-bit float.

Signed-off-by: Philippe Mathieu-Daudé 
---
 audio/mixeng.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/audio/mixeng.c b/audio/mixeng.c
index 739a500449..9946bfeaec 100644
--- a/audio/mixeng.c
+++ b/audio/mixeng.c
@@ -271,7 +271,7 @@ f_sample *mixeng_clip[2][2][2][3] = {
 #define CONV_NATURAL_FLOAT(x) (x)
 #define CLIP_NATURAL_FLOAT(x) (x)
 #else
-static const float float_scale = UINT_MAX / 2.f;
+static const float float_scale = UINT_MAX / 2.;
 #define CONV_NATURAL_FLOAT(x) ((x) * float_scale)
 
 #ifdef RECIPROCAL
-- 
2.21.3

[Bug 1876568] [NEW] "semtimedop" implementation missing in qemu?

[Manuel Reimer]

Public bug reported:

I was trying to do an ARMv6 cross compile with qemu-user-static when I
ran into this:

https://travis-ci.com/github/VDR4Arch/vdr4arch/jobs/326884620#L1596

I was close to giving up when I found the following:

https://github.com/osrf/multiarch-docker-image-generation/issues/36

Most important comment may be this one:

https://github.com/osrf/multiarch-docker-image-
generation/issues/36#issuecomment-610626796

> The "correct" way to fix this does seem to be to implement semtimedop
in qemu.

I don't know how much involved the people, discussing there, are in the
qemu development but I thought it may be a good idea to bring this to
your attention. If this is already fixed (I haven't found any bug about
"semtimedop"), then please just close this one and tell me in which
version the fix will be included.

** Affects: qemu
 Importance: Undecided
 Status: New

-- 
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https://bugs.launchpad.net/bugs/1876568

Title:
  "semtimedop" implementation missing in qemu?

Status in QEMU:
  New

Bug description:
  I was trying to do an ARMv6 cross compile with qemu-user-static when I
  ran into this:

  https://travis-ci.com/github/VDR4Arch/vdr4arch/jobs/326884620#L1596

  I was close to giving up when I found the following:

  https://github.com/osrf/multiarch-docker-image-generation/issues/36

  Most important comment may be this one:

  https://github.com/osrf/multiarch-docker-image-
  generation/issues/36#issuecomment-610626796

  > The "correct" way to fix this does seem to be to implement
  semtimedop in qemu.

  I don't know how much involved the people, discussing there, are in
  the qemu development but I thought it may be a good idea to bring this
  to your attention. If this is already fixed (I haven't found any bug
  about "semtimedop"), then please just close this one and tell me in
  which version the fix will be included.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1876568/+subscriptions

Re: [PATCH for-5.1 V3 0/7] mips: Add Loongson-3 machine support (with KVM)

[Aleksandar Markovic]

нед, 3. мај 2020. у 12:21 Huacai Chen  је написао/ла:
>
> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
> Loongson-3A R4 is the newest and its ISA is almost the superset of all
> others. To reduce complexity, in QEMU we just define two CPU types:
>
> 1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
>suitable for TCG because Loongson-3A R1 has fewest ASE.
> 2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
>suitable for KVM because Loongson-3A R4 has the VZ ASE.
>

Huacai, thanks for putting together v3, which is a little better than v2, and
thanks for addressing my previous suggestions.

Now, give us some time to digest new data on Loongson3.  We will
respond, but it won't happen immediately, which is, you'd agree,
reasonable. Just be patient.

But again, in general, I salute your efforts very much!

Yours, Aleksandar

> Loongson-3 lacks English documents. I've tried to translated them with
> translate.google.com, and the machine translated documents (together
> with their original Chinese versions) are available here.
>
> Loongson-3A R1 (Loongson-3A1000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf 
> (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf 
> (Chinese Version)
>
> Loongson-3A R2 (Loongson-3A2000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)
>
> Loongson-3A R3 (Loongson-3A3000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf (Chinese 
> Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf (Chinese 
> Version)
>
> Loongson-3A R4 (Loongson-3A4000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
> http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
> User Manual Part 2:
> I'm sorry that it is unavailable now.
>
> We are preparing to add QEMU's Loongson-3 support. MIPS VZ extension is
> fully supported in Loongson-3A R4+, so we at first add QEMU/KVM support
> in this series. And the next series will add QEMU/TCG support (it will
> emulate Loongson-3A R1).
>
> We already have a full functional Linux kernel (based on Linux-5.4.x LTS
> but not upstream yet) here:
>
> https://github.com/chenhuacai/linux
>
> How to use QEMU/Loongson-3?
> 1, Download kernel source from the above URL;
> 2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
> 3, Boot a Loongson-3A4000 host with this kernel;
> 4, Build QEMU-5.0.0 with this patchset;
> 5, modprobe kvm;
> 6, Use QEMU with TCG (available in future):
>qemu-system-mips64el -M loongson3,accel=tcg -cpu Loongson-3A1000 
> -kernel  -append ...
>Use QEMU with KVM (available at present):
>qemu-system-mips64el -M loongson3,accel=kvm -cpu Loongson-3A4000 
> -kernel  -append ...
>
>The "-cpu" parameter can be omitted here and QEMU will use the correct 
> type for TCG/KVM automatically.
>
> V1 -> V2:
> 1, Add a cover letter;
> 2, Improve CPU definitions;
> 3, Remove LS7A-related things (Use GPEX instead);
> 4, Add a description of how to run QEMU/Loongson-3.
>
> V2 -> V3:
> 1, Fix all possible checkpatch.pl errors and warnings.
>
> Huacai Chen(7):
>  configure: Add KVM target support for MIPS64
>  hw/mips: Implement the kvm_type() hook in MachineClass
>  hw/mips: Add CPU IRQ3 delivery for KVM
>  target/mips: Add Loongson-3 CPU definition
>  target/mips: Add more CP0 register for save/restor
>  hw/mips: Add Loongson-3 machine support (with KVM)
>  MAINTAINERS: Add myself as Loongson-3 maintainer
>
> Signed-off-by: Huacai Chen 
> ---
>  MAINTAINERS  |   5 +
>  configure|   2 +-
>  default-configs/mips64el-softmmu.mak |   1 +
>  hw/core/Makefile.objs|   2 +-
>  hw/core/null-machine.c   |   4 +
>  hw/mips/Kconfig  |  10 +
>  hw/mips/Makefile.objs|   3 +-
>  hw/mips/common.c |  31 ++
>  hw/mips/mips_int.c   |   4 +-
>  hw/mips/mips_loongson3.c | 901 
> +++
>  include/hw/mips/mips.h   |   3 +
>  target/mips/cpu.h|  28 ++
>  target/mips/internal.h   |   2 +
>  target/mips/kvm.c| 212 +
>  target/mips/machine.c|   6 +-
>  target/mips/mips-defs.h  

Re: [PATCH for-5.1 V3 0/7] mips: Add Loongson-3 machine support (with KVM)

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/1588501221-1205-1-git-send-email-che...@lemote.com/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

Not run: 259
Failures: 192
Failed 1 of 117 iotests
make: *** [check-tests/check-block.sh] Error 1
make: *** Waiting for unfinished jobs
  TESTcheck-qtest-aarch64: tests/qtest/test-hmp
  TESTcheck-qtest-aarch64: tests/qtest/qos-test
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', 
'--label', 'com.qemu.instance.uuid=8950e4c4713746e191eb1884fd629535', '-u', 
'1001', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', 
'-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 
'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', 
'/home/patchew/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', 
'/var/tmp/patchew-tester-tmp-x9_nmvq4/src/docker-src.2020-05-03-06.33.44.10861:/var/tmp/qemu:z,ro',
 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit 
status 2.
filter=--filter=label=com.qemu.instance.uuid=8950e4c4713746e191eb1884fd629535
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-x9_nmvq4/src'
make: *** [docker-run-test-quick@centos7] Error 2

real15m24.568s
user0m8.657s


The full log is available at
http://patchew.org/logs/1588501221-1205-1-git-send-email-che...@lemote.com/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [PATCH for-5.1 V3 0/7] mips: Add Loongson-3 machine support (with KVM)

[Yonggang Luo]

The english version of the reference document is hard to head.
I suggest first convert the chinese version into markdown or alternative
format and
place them at github.
And we then translate the document with google translate.

On Sun, May 3, 2020 at 6:22 PM Huacai Chen  wrote:

> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
> Loongson-3A R4 is the newest and its ISA is almost the superset of all
> others. To reduce complexity, in QEMU we just define two CPU types:
>
> 1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
>suitable for TCG because Loongson-3A R1 has fewest ASE.
> 2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
>suitable for KVM because Loongson-3A R4 has the VZ ASE.
>
> Loongson-3 lacks English documents. I've tried to translated them with
> translate.google.com, and the machine translated documents (together
> with their original Chinese versions) are available here.
>
> Loongson-3A R1 (Loongson-3A1000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf
> (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf
> (Chinese Version)
>
> Loongson-3A R2 (Loongson-3A2000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)
>
> Loongson-3A R3 (Loongson-3A3000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf
> (Chinese Version)
> User Manual Part 2:
> http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
> http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf
> (Chinese Version)
>
> Loongson-3A R4 (Loongson-3A4000)
> User Manual Part 1:
> http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
> http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
> User Manual Part 2:
> I'm sorry that it is unavailable now.
>
> We are preparing to add QEMU's Loongson-3 support. MIPS VZ extension is
> fully supported in Loongson-3A R4+, so we at first add QEMU/KVM support
> in this series. And the next series will add QEMU/TCG support (it will
> emulate Loongson-3A R1).
>
> We already have a full functional Linux kernel (based on Linux-5.4.x LTS
> but not upstream yet) here:
>
> https://github.com/chenhuacai/linux
>
> How to use QEMU/Loongson-3?
> 1, Download kernel source from the above URL;
> 2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
> 3, Boot a Loongson-3A4000 host with this kernel;
> 4, Build QEMU-5.0.0 with this patchset;
> 5, modprobe kvm;
> 6, Use QEMU with TCG (available in future):
>qemu-system-mips64el -M loongson3,accel=tcg -cpu Loongson-3A1000
> -kernel  -append ...
>Use QEMU with KVM (available at present):
>qemu-system-mips64el -M loongson3,accel=kvm -cpu Loongson-3A4000
> -kernel  -append ...
>
>The "-cpu" parameter can be omitted here and QEMU will use the correct
> type for TCG/KVM automatically.
>
> V1 -> V2:
> 1, Add a cover letter;
> 2, Improve CPU definitions;
> 3, Remove LS7A-related things (Use GPEX instead);
> 4, Add a description of how to run QEMU/Loongson-3.
>
> V2 -> V3:
> 1, Fix all possible checkpatch.pl errors and warnings.
>
> Huacai Chen(7):
>  configure: Add KVM target support for MIPS64
>  hw/mips: Implement the kvm_type() hook in MachineClass
>  hw/mips: Add CPU IRQ3 delivery for KVM
>  target/mips: Add Loongson-3 CPU definition
>  target/mips: Add more CP0 register for save/restor
>  hw/mips: Add Loongson-3 machine support (with KVM)
>  MAINTAINERS: Add myself as Loongson-3 maintainer
>
> Signed-off-by: Huacai Chen 
> ---
>  MAINTAINERS  |   5 +
>  configure|   2 +-
>  default-configs/mips64el-softmmu.mak |   1 +
>  hw/core/Makefile.objs|   2 +-
>  hw/core/null-machine.c   |   4 +
>  hw/mips/Kconfig  |  10 +
>  hw/mips/Makefile.objs|   3 +-
>  hw/mips/common.c |  31 ++
>  hw/mips/mips_int.c   |   4 +-
>  hw/mips/mips_loongson3.c | 901
> +++
>  include/hw/mips/mips.h   |   3 +
>  target/mips/cpu.h|  28 ++
>  target/mips/internal.h   |   2 +
>  target/mips/kvm.c| 212 +
>  target/mips/machine.c|   6 +-
>  target/mips/mips-defs.h  |   7 +-
>  target/mips/translate.c  |   2 +
>  target/mips/translate_init.inc.c |  86 
>  18 files changed, 1300 

[PATCH for-5.1 V3 5/7] target/mips: Add more CP0 register for save/restore

[Huacai Chen]

Add more CP0 register for save/restore, including: EBase, XContext,
PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 target/mips/kvm.c | 212 ++
 target/mips/machine.c |   6 +-
 2 files changed, 216 insertions(+), 2 deletions(-)

diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index de3e26e..96cfa10 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int 
level)
 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
 
 #define KVM_REG_MIPS_CP0_INDEX  MIPS_CP0_32(0, 0)
+#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0)
 #define KVM_REG_MIPS_CP0_CONTEXTMIPS_CP0_64(4, 0)
 #define KVM_REG_MIPS_CP0_USERLOCAL  MIPS_CP0_64(4, 2)
 #define KVM_REG_MIPS_CP0_PAGEMASK   MIPS_CP0_32(5, 0)
+#define KVM_REG_MIPS_CP0_PAGEGRAIN  MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5)
+#define KVM_REG_MIPS_CP0_PWFIELDMIPS_CP0_64(5, 6)
+#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7)
 #define KVM_REG_MIPS_CP0_WIRED  MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_PWCTL  MIPS_CP0_32(6, 6)
 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
 #define KVM_REG_MIPS_CP0_BADVADDR   MIPS_CP0_64(8, 0)
 #define KVM_REG_MIPS_CP0_COUNT  MIPS_CP0_32(9, 0)
@@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int 
level)
 #define KVM_REG_MIPS_CP0_CAUSE  MIPS_CP0_32(13, 0)
 #define KVM_REG_MIPS_CP0_EPCMIPS_CP0_64(14, 0)
 #define KVM_REG_MIPS_CP0_PRID   MIPS_CP0_32(15, 0)
+#define KVM_REG_MIPS_CP0_EBASE  MIPS_CP0_64(15, 1)
 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
 #define KVM_REG_MIPS_CP0_CONFIG1MIPS_CP0_32(16, 1)
 #define KVM_REG_MIPS_CP0_CONFIG2MIPS_CP0_32(16, 2)
 #define KVM_REG_MIPS_CP0_CONFIG3MIPS_CP0_32(16, 3)
 #define KVM_REG_MIPS_CP0_CONFIG4MIPS_CP0_32(16, 4)
 #define KVM_REG_MIPS_CP0_CONFIG5MIPS_CP0_32(16, 5)
+#define KVM_REG_MIPS_CP0_CONFIG6MIPS_CP0_32(16, 6)
+#define KVM_REG_MIPS_CP0_XCONTEXT   MIPS_CP0_64(20, 0)
 #define KVM_REG_MIPS_CP0_ERROREPC   MIPS_CP0_64(30, 0)
+#define KVM_REG_MIPS_CP0_KSCRATCH1  MIPS_CP0_64(31, 2)
+#define KVM_REG_MIPS_CP0_KSCRATCH2  MIPS_CP0_64(31, 3)
+#define KVM_REG_MIPS_CP0_KSCRATCH3  MIPS_CP0_64(31, 4)
+#define KVM_REG_MIPS_CP0_KSCRATCH4  MIPS_CP0_64(31, 5)
+#define KVM_REG_MIPS_CP0_KSCRATCH5  MIPS_CP0_64(31, 6)
+#define KVM_REG_MIPS_CP0_KSCRATCH6  MIPS_CP0_64(31, 7)
 
 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
int32_t *addr)
@@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, 
uint64_t reg_id,
  (1U << CP0C5_UFE) | \
  (1U << CP0C5_FRE) | \
  (1U << CP0C5_UFR))
+#define KVM_REG_MIPS_CP0_CONFIG6_MASK   ((1U << CP0C6_BPPASS) | \
+ (0x3fU << CP0C6_KPOS) | \
+ (1U << CP0C6_KE) | \
+ (1U << CP0C6_VTLBONLY) | \
+ (1U << CP0C6_LASX) | \
+ (1U << CP0C6_SSEN) | \
+ (1U << CP0C6_DISDRTIME) | \
+ (1U << CP0C6_PIXNUEN) | \
+ (1U << CP0C6_SCRAND) | \
+ (1U << CP0C6_LLEXCEN) | \
+ (1U << CP0C6_DISVC) | \
+ (1U << CP0C6_VCLRU) | \
+ (1U << CP0C6_DCLRU) | \
+ (1U << CP0C6_PIXUEN) | \
+ (1U << CP0C6_DISBLKLYEN) | \
+ (1U << CP0C6_UMEMUALEN) | \
+ (1U << CP0C6_SFBEN) | \
+ (1U << CP0C6_FLTINT) | \
+ (1U << CP0C6_VLTINT) | \
+ (1U << CP0C6_DISBTB) | \
+ (3U << CP0C6_STPREFCTL) | \
+ (1U << CP0C6_INSTPREF) | \
+ (1U << CP0C6_DATAPREF))
 
 static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id,
   int32_t *addr, int32_t mask)
@@ -729,6 +767,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int 
level)
 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 ret = err;
 }
+  

[PATCH for-5.1 V3 7/7] MAINTAINERS: Add myself as Loongson-3 maintainer

[Huacai Chen]

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 MAINTAINERS | 5 +
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fc3d1b0..8d5cfec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1084,6 +1084,11 @@ F: hw/isa/vt82c686.c
 F: hw/pci-host/bonito.c
 F: include/hw/isa/vt82c686.h
 
+Loongson-3
+M: Huacai Chen 
+S: Maintained
+F: hw/mips/mips_loongson3.c
+
 Boston
 M: Paul Burton 
 R: Aleksandar Rikalo 
-- 
2.7.0

[PATCH for-5.1 V3 4/7] target/mips: Add Loongson-3 CPU definition

[Huacai Chen]

Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:
1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 target/mips/cpu.h| 28 +
 target/mips/internal.h   |  2 +
 target/mips/mips-defs.h  |  7 +++-
 target/mips/translate.c  |  2 +
 target/mips/translate_init.inc.c | 86 
 5 files changed, 123 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 94d01ea..0b3c987 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -940,7 +940,35 @@ struct CPUMIPSState {
 #define CP0C5_UFR  2
 #define CP0C5_NFExists 0
 int32_t CP0_Config6;
+int32_t CP0_Config6_rw_bitmask;
+#define CP0C6_BPPASS  31
+#define CP0C6_KPOS24
+#define CP0C6_KE  23
+#define CP0C6_VTLBONLY22
+#define CP0C6_LASX21
+#define CP0C6_SSEN20
+#define CP0C6_DISDRTIME   19
+#define CP0C6_PIXNUEN 18
+#define CP0C6_SCRAND  17
+#define CP0C6_LLEXCEN 16
+#define CP0C6_DISVC   15
+#define CP0C6_VCLRU   14
+#define CP0C6_DCLRU   13
+#define CP0C6_PIXUEN  12
+#define CP0C6_DISBLKLYEN  11
+#define CP0C6_UMEMUALEN   10
+#define CP0C6_SFBEN   8
+#define CP0C6_FLTINT  7
+#define CP0C6_VLTINT  6
+#define CP0C6_DISBTB  5
+#define CP0C6_STPREFCTL   2
+#define CP0C6_INSTPREF1
+#define CP0C6_DATAPREF0
 int32_t CP0_Config7;
+int64_t CP0_Config7_rw_bitmask;
+#define CP0C7_NAPCGEN   2
+#define CP0C7_UNIMUEN   1
+#define CP0C7_VFPUCGEN  0
 uint64_t CP0_LLAddr;
 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 int32_t CP0_MAARI;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1bf274b..7853cb1 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -36,7 +36,9 @@ struct mips_def_t {
 int32_t CP0_Config5;
 int32_t CP0_Config5_rw_bitmask;
 int32_t CP0_Config6;
+int32_t CP0_Config6_rw_bitmask;
 int32_t CP0_Config7;
+int32_t CP0_Config7_rw_bitmask;
 target_ulong CP0_LLAddr_rw_bitmask;
 int CP0_LLAddr_shift;
 int32_t SYNCI_Step;
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a831bb4..c2c96db 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -51,8 +51,9 @@
  */
 #define INSN_LOONGSON2E   0x0001ULL
 #define INSN_LOONGSON2F   0x0002ULL
-#define INSN_VR54XX   0x0004ULL
-#define INSN_R59000x0008ULL
+#define INSN_LOONGSON3A   0x0004ULL
+#define INSN_VR54XX   0x0008ULL
+#define INSN_R59000x0010ULL
 /*
  *   bits 56-63: vendor-specific ASEs
  */
@@ -94,6 +95,8 @@
 /* Wave Computing: "nanoMIPS" */
 #define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)
 
+#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A)
+
 /*
  * Strictly follow the architecture standard:
  * - Disallow "special" instruction handling for PMON/SPIM.
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25b595a..2caf4cb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env)
 env->CP0_Config5 = env->cpu_model->CP0_Config5;
 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
 env->CP0_Config6 = env->cpu_model->CP0_Config6;
+env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
 env->CP0_Config7 = env->cpu_model->CP0_Config7;
+env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
  << env->cpu_model->CP0_LLAddr_shift;
 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 6d145a9..a31f229 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -802,6 +802,92 @@ const mips_def_t mips_defs[] =
 .mmu_type = MMU_TYPE_R4000,
 },
 {
+.name = "Loongson-3A1000",
+.CP0_PRid = 0x6305,
+/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+   (MMU_TYPE_R4000 << CP0C0_MT),
+   

[PATCH for-5.1 V3 6/7] hw/mips: Add Loongson-3 machine support (with KVM)

[Huacai Chen]

Add Loongson-3 based machine support, it use i8259 as the interrupt
controler and use GPEX as the pci controller. Currently it can only
work with KVM, but we will add TCG support in future.

We already have a full functional Linux kernel (based on Linux-5.4.x LTS
but not upstream yet) here:

https://github.com/chenhuacai/linux

How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
3, Boot the a Loongson-3A4000 host with this kernel;
4, Build QEMU-5.0.0 with this patchset;
5, modprobe kvm;
6, Use QEMU with TCG (available in future):
   qemu-system-mips64el -M loongson3,accel=tcg -cpu Loongson-3A1000 -kernel 
 -append ...
   Use QEMU with KVM (available at present):
   qemu-system-mips64el -M loongson3,accel=kvm -cpu Loongson-3A4000 -kernel 
 -append ...

   The "-cpu" parameter can be omitted here and QEMU will use the correct type 
for TCG/KVM automatically.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 default-configs/mips64el-softmmu.mak |   1 +
 hw/mips/Kconfig  |  10 +
 hw/mips/Makefile.objs|   1 +
 hw/mips/mips_loongson3.c | 901 +++
 4 files changed, 913 insertions(+)
 create mode 100644 hw/mips/mips_loongson3.c

diff --git a/default-configs/mips64el-softmmu.mak 
b/default-configs/mips64el-softmmu.mak
index 8b0c9b1..fc798e4 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -3,6 +3,7 @@
 include mips-softmmu-common.mak
 CONFIG_IDE_VIA=y
 CONFIG_FULONG=y
+CONFIG_LOONGSON3=y
 CONFIG_ATI_VGA=y
 CONFIG_RTL8139_PCI=y
 CONFIG_JAZZ=y
diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig
index 2c2adbc..6f16b16 100644
--- a/hw/mips/Kconfig
+++ b/hw/mips/Kconfig
@@ -44,6 +44,16 @@ config JAZZ
 config FULONG
 bool
 
+config LOONGSON3
+bool
+select PCKBD
+select SERIAL
+select ISA_BUS
+select PCI_EXPRESS_GENERIC_BRIDGE
+select VIRTIO_VGA
+select QXL if SPICE
+select MSI_NONBROKEN
+
 config MIPS_CPS
 bool
 select PTIMER
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 2f7795b..f9bc8f5 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -4,5 +4,6 @@ obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o
 obj-$(CONFIG_MIPSSIM) += mips_mipssim.o
 obj-$(CONFIG_JAZZ) += mips_jazz.o
 obj-$(CONFIG_FULONG) += mips_fulong2e.o
+obj-$(CONFIG_LOONGSON3) += mips_loongson3.o
 obj-$(CONFIG_MIPS_CPS) += cps.o
 obj-$(CONFIG_MIPS_BOSTON) += boston.o
diff --git a/hw/mips/mips_loongson3.c b/hw/mips/mips_loongson3.c
new file mode 100644
index 000..3294a67
--- /dev/null
+++ b/hw/mips/mips_loongson3.c
@@ -0,0 +1,901 @@
+/*
+ * Generic Loongson-3 Platform support
+ *
+ * Copyright (c) 2015-2020 Huacai Chen (che...@lemote.com)
+ * This code is licensed under the GNU GPL v2.
+ *
+ * Contributions are licensed under the terms of the GNU GPL,
+ * version 2 or (at your option) any later version.
+ */
+
+/*
+ * Generic PC Platform based on Loongson-3 CPU (MIPS64R2 with extensions,
+ * 800~2000MHz)
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "elf.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+#include "hw/intc/i8259.h"
+#include "hw/loader.h"
+#include "hw/ide.h"
+#include "hw/isa/superio.h"
+#include "hw/pci/msi.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/rtc/mc146818rtc.h"
+#include "net/net.h"
+#include "exec/address-spaces.h"
+#include "sysemu/kvm.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+
+#define INITRD_OFFSET 0x0400
+#define BOOTPARAM_ADDR0x8ff0
+#define BOOTPARAM_PHYADDR 0x0ff0
+#define CFG_ADDR  0x0f10
+#define FW_CONF_ADDR  0x0fff
+#define PM_MMIO_ADDR  0x1008
+#define PM_MMIO_SIZE  0x100
+#define PM_CNTL_MODE  0x10
+
+#define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fff)
+
+/* Loongson-3 has a 2MB flash rom */
+#define BIOS_SIZE   (2 * MiB)
+#define LOONGSON_MAX_VCPUS  16
+
+#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
+
+#define PCIE_IRQ_BASE   3
+
+#define VIRT_PCI_IO_BASE0x1800ul
+#define VIRT_PCI_IO_SIZE0x000cul
+#define VIRT_PCI_MEM_BASE   0x4000ul
+#define VIRT_PCI_MEM_SIZE   0x4000ul
+#define VIRT_PCI_ECAM_BASE  0x1a00ul
+#define VIRT_PCI_ECAM_SIZE  0x0200ul
+
+#define align(x) (((x) + 63) & ~63)
+
+/* LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structrues
+ * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux 
kernel
+ */
+struct efi_memory_map_loongson {
+uint16_t vers;   /* version of efi_memory_map */
+

[PATCH for-5.1 V3 3/7] hw/mips: Add CPU IRQ3 delivery for KVM

[Huacai Chen]

Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 hw/mips/mips_int.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 796730b..982ce34 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -48,14 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, int 
level)
 if (level) {
 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
 
-if (kvm_enabled() && irq == 2) {
+if (kvm_enabled() && (irq == 2 || irq == 3)) {
 kvm_mips_set_interrupt(cpu, irq, level);
 }
 
 } else {
 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
 
-if (kvm_enabled() && irq == 2) {
+if (kvm_enabled() && (irq == 2 || irq == 3)) {
 kvm_mips_set_interrupt(cpu, irq, level);
 }
 }
-- 
2.7.0

[PATCH for-5.1 V3 2/7] hw/mips: Implement the kvm_type() hook in MachineClass

[Huacai Chen]

MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we
can't create a VZ guest in QEMU because it lacks the kvm_type() hook in
MachineClass. Besides, libvirt uses a null-machine to detect the kvm
capability, so by default it will return "KVM not supported" on a VZ
platform. Thus, null-machine also need the kvm_type() hook.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 hw/core/Makefile.objs  |  2 +-
 hw/core/null-machine.c |  4 
 hw/mips/Makefile.objs  |  2 +-
 hw/mips/common.c   | 31 +++
 include/hw/mips/mips.h |  3 +++
 5 files changed, 40 insertions(+), 2 deletions(-)
 create mode 100644 hw/mips/common.c

diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 1d540ed..b5672f4 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -17,11 +17,11 @@ common-obj-$(CONFIG_SOFTMMU) += vm-change-state-handler.o
 common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
 common-obj-$(CONFIG_SOFTMMU) += sysbus.o
 common-obj-$(CONFIG_SOFTMMU) += machine.o
-common-obj-$(CONFIG_SOFTMMU) += null-machine.o
 common-obj-$(CONFIG_SOFTMMU) += loader.o
 common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o
 common-obj-$(CONFIG_SOFTMMU) += numa.o
 common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o
+obj-$(CONFIG_SOFTMMU) += null-machine.o
 obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o
 
 common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index cb47d9d..94a36f9 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -17,6 +17,7 @@
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 #include "hw/core/cpu.h"
+#include "hw/mips/mips.h"
 
 static void machine_none_init(MachineState *mch)
 {
@@ -50,6 +51,9 @@ static void machine_none_machine_init(MachineClass *mc)
 mc->max_cpus = 1;
 mc->default_ram_size = 0;
 mc->default_ram_id = "ram";
+#ifdef TARGET_MIPS
+mc->kvm_type = mips_kvm_type;
+#endif
 }
 
 DEFINE_MACHINE("none", machine_none_machine_init)
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 525809a..2f7795b 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += addr.o mips_int.o
+obj-y += addr.o common.o mips_int.o
 obj-$(CONFIG_R4K) += mips_r4k.o
 obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o
 obj-$(CONFIG_MIPSSIM) += mips_mipssim.o
diff --git a/hw/mips/common.c b/hw/mips/common.c
new file mode 100644
index 000..0e33bd0
--- /dev/null
+++ b/hw/mips/common.c
@@ -0,0 +1,31 @@
+/*
+ * Common MIPS routines
+ *
+ * Copyright (c) 2020 Huacai Chen (che...@lemote.com)
+ * This code is licensed under the GNU GPL v2.
+ */
+
+#include 
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/boards.h"
+#include "hw/mips/mips.h"
+#include "sysemu/kvm_int.h"
+
+int mips_kvm_type(MachineState *machine, const char *vm_type)
+{
+int r;
+KVMState *s = KVM_STATE(machine->accelerator);
+
+r = kvm_check_extension(s, KVM_CAP_MIPS_VZ);
+if (r > 0) {
+return KVM_VM_MIPS_VZ;
+}
+
+r = kvm_check_extension(s, KVM_CAP_MIPS_TE);
+if (r > 0) {
+return KVM_VM_MIPS_TE;
+}
+
+return -1;
+}
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index 0af4c3d..2ac0580 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -20,4 +20,7 @@ void rc4030_dma_write(void *dma, uint8_t *buf, int len);
 
 DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr);
 
+/* common.c */
+int mips_kvm_type(MachineState *machine, const char *vm_type);
+
 #endif
-- 
2.7.0

[PATCH for-5.1 V3 1/7] configure: Add KVM target support for MIPS64

[Huacai Chen]

Preparing for Loongson-3 virtualization, add KVM target support for
MIPS64 in configure script.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 configure | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configure b/configure
index 23b5e93..7581e65 100755
--- a/configure
+++ b/configure
@@ -198,7 +198,7 @@ supported_kvm_target() {
 arm:arm | aarch64:aarch64 | \
 i386:i386 | i386:x86_64 | i386:x32 | \
 x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
-mips:mips | mipsel:mips | \
+mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \
 ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \
 s390x:s390x)
 return 0
-- 
2.7.0

[PATCH for-5.1 V3 0/7] mips: Add Loongson-3 machine support (with KVM)

[Huacai Chen]

Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, in QEMU we just define two CPU types:

1, "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2, "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3 lacks English documents. I've tried to translated them with
translate.google.com, and the machine translated documents (together
with their original Chinese versions) are available here.

Loongson-3A R1 (Loongson-3A1000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A1000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P1.pdf 
(Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A1000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A1000_processor_user_manual_P2.pdf 
(Chinese Version)

Loongson-3A R2 (Loongson-3A2000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A2000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user1.pdf (Chinese Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A2000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A2000_user2.pdf (Chinese Version)

Loongson-3A R3 (Loongson-3A3000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A3000_p1.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual1.pdf (Chinese 
Version)
User Manual Part 2:
http://ftp.godson.ac.cn/lemote/3A3000_p2.pdf
http://ftp.godson.ac.cn/lemote/Loongson3A3000_3B3000usermanual2.pdf (Chinese 
Version)

Loongson-3A R4 (Loongson-3A4000)
User Manual Part 1:
http://ftp.godson.ac.cn/lemote/3A4000_p1.pdf
http://ftp.godson.ac.cn/lemote/3A4000user.pdf (Chinese Version)
User Manual Part 2:
I'm sorry that it is unavailable now.

We are preparing to add QEMU's Loongson-3 support. MIPS VZ extension is
fully supported in Loongson-3A R4+, so we at first add QEMU/KVM support
in this series. And the next series will add QEMU/TCG support (it will
emulate Loongson-3A R1).

We already have a full functional Linux kernel (based on Linux-5.4.x LTS
but not upstream yet) here:

https://github.com/chenhuacai/linux

How to use QEMU/Loongson-3?
1, Download kernel source from the above URL;
2, Build a kernel with arch/mips/configs/loongson3_{def,hpc}config;
3, Boot a Loongson-3A4000 host with this kernel;
4, Build QEMU-5.0.0 with this patchset;
5, modprobe kvm;
6, Use QEMU with TCG (available in future):
   qemu-system-mips64el -M loongson3,accel=tcg -cpu Loongson-3A1000 -kernel 
 -append ... 
   Use QEMU with KVM (available at present): 
   qemu-system-mips64el -M loongson3,accel=kvm -cpu Loongson-3A4000 -kernel 
 -append ... 

   The "-cpu" parameter can be omitted here and QEMU will use the correct type 
for TCG/KVM automatically.

V1 -> V2:
1, Add a cover letter;
2, Improve CPU definitions;
3, Remove LS7A-related things (Use GPEX instead);
4, Add a description of how to run QEMU/Loongson-3.

V2 -> V3:
1, Fix all possible checkpatch.pl errors and warnings.

Huacai Chen(7):
 configure: Add KVM target support for MIPS64
 hw/mips: Implement the kvm_type() hook in MachineClass
 hw/mips: Add CPU IRQ3 delivery for KVM
 target/mips: Add Loongson-3 CPU definition
 target/mips: Add more CP0 register for save/restor
 hw/mips: Add Loongson-3 machine support (with KVM)
 MAINTAINERS: Add myself as Loongson-3 maintainer

Signed-off-by: Huacai Chen 
---
 MAINTAINERS  |   5 +
 configure|   2 +-
 default-configs/mips64el-softmmu.mak |   1 +
 hw/core/Makefile.objs|   2 +-
 hw/core/null-machine.c   |   4 +
 hw/mips/Kconfig  |  10 +
 hw/mips/Makefile.objs|   3 +-
 hw/mips/common.c |  31 ++
 hw/mips/mips_int.c   |   4 +-
 hw/mips/mips_loongson3.c | 901 +++
 include/hw/mips/mips.h   |   3 +
 target/mips/cpu.h|  28 ++
 target/mips/internal.h   |   2 +
 target/mips/kvm.c| 212 +
 target/mips/machine.c|   6 +-
 target/mips/mips-defs.h  |   7 +-
 target/mips/translate.c  |   2 +
 target/mips/translate_init.inc.c |  86 
 18 files changed, 1300 insertions(+), 9 deletions(-)
 create mode 100644 hw/mips/common.c
 create mode 100644 hw/mips/mips_loongson3.c
--
2.7.0

[PATCH V3 13/14] KVM: MIPS: Add more MMIO load/store instructions emulation

[Huacai Chen]

This patch add more MMIO load/store instructions emulation, which can
be observed in QXL and some other device drivers:

1, LWL, LWR, LDW, LDR, SWL, SWR, SDL and SDR for all MIPS;
2, GSLBX, GSLHX, GSLWX, GSLDX, GSSBX, GSSHX, GSSWX and GSSDX for
   Loongson-3.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/emulate.c | 480 +++-
 1 file changed, 470 insertions(+), 10 deletions(-)

diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index 3946499..71316fa 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -1604,6 +1604,7 @@ enum emulation_result kvm_mips_emulate_store(union 
mips_instruction inst,
enum emulation_result er;
u32 rt;
void *data = run->mmio.data;
+   unsigned int imme;
unsigned long curr_pc;
 
/*
@@ -1661,6 +1662,211 @@ enum emulation_result kvm_mips_emulate_store(union 
mips_instruction inst,
  vcpu->arch.gprs[rt], *(u8 *)data);
break;
 
+   case swl_op:
+   run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
+   vcpu->arch.host_cp0_badvaddr) & (~0x3);
+   run->mmio.len = 4;
+   imme = vcpu->arch.host_cp0_badvaddr & 0x3;
+   switch (imme) {
+   case 0:
+   *(u32 *)data = ((*(u32 *)data) & 0xff00) |
+   (vcpu->arch.gprs[rt] >> 24);
+   break;
+   case 1:
+   *(u32 *)data = ((*(u32 *)data) & 0x) |
+   (vcpu->arch.gprs[rt] >> 16);
+   break;
+   case 2:
+   *(u32 *)data = ((*(u32 *)data) & 0xff00) |
+   (vcpu->arch.gprs[rt] >> 8);
+   break;
+   case 3:
+   *(u32 *)data = vcpu->arch.gprs[rt];
+   break;
+   default:
+   break;
+   }
+
+   kvm_debug("[%#lx] OP_SWL: eaddr: %#lx, gpr: %#lx, data: %#x\n",
+ vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
+ vcpu->arch.gprs[rt], *(u32 *)data);
+   break;
+
+   case swr_op:
+   run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
+   vcpu->arch.host_cp0_badvaddr) & (~0x3);
+   run->mmio.len = 4;
+   imme = vcpu->arch.host_cp0_badvaddr & 0x3;
+   switch (imme) {
+   case 0:
+   *(u32 *)data = vcpu->arch.gprs[rt];
+   break;
+   case 1:
+   *(u32 *)data = ((*(u32 *)data) & 0xff) |
+   (vcpu->arch.gprs[rt] << 8);
+   break;
+   case 2:
+   *(u32 *)data = ((*(u32 *)data) & 0x) |
+   (vcpu->arch.gprs[rt] << 16);
+   break;
+   case 3:
+   *(u32 *)data = ((*(u32 *)data) & 0xff) |
+   (vcpu->arch.gprs[rt] << 24);
+   break;
+   default:
+   break;
+   }
+
+   kvm_debug("[%#lx] OP_SWR: eaddr: %#lx, gpr: %#lx, data: %#x\n",
+ vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
+ vcpu->arch.gprs[rt], *(u32 *)data);
+   break;
+
+   case sdl_op:
+   run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
+   vcpu->arch.host_cp0_badvaddr) & (~0x7);
+
+   run->mmio.len = 8;
+   imme = vcpu->arch.host_cp0_badvaddr & 0x7;
+   switch (imme) {
+   case 0:
+   *(u64 *)data = ((*(u64 *)data) & 0xff00) |
+   ((vcpu->arch.gprs[rt] >> 56) & 0xff);
+   break;
+   case 1:
+   *(u64 *)data = ((*(u64 *)data) & 0x) |
+   ((vcpu->arch.gprs[rt] >> 48) & 0x);
+   break;
+   case 2:
+   *(u64 *)data = ((*(u64 *)data) & 0xff00) |
+   ((vcpu->arch.gprs[rt] >> 40) & 
0xff);
+   break;
+   case 3:
+   *(u64 *)data = ((*(u64 *)data) & 0x) |
+   ((vcpu->arch.gprs[rt] >> 32) & 
0x);
+   break;
+   case 4:
+   *(u64 *)data = ((*(u64 *)data) & 0xff00) |
+   ((vcpu->arch.gprs[rt] >> 24) & 

[PATCH V3 14/14] KVM: MIPS: Enable KVM support for Loongson-3

[Huacai Chen]

This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but
only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors
are incomplete). Besides, Loongson-3 support SMP guests, so we clear the
linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more
than one VCPUs.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/Kconfig| 1 +
 arch/mips/kernel/cpu-probe.c | 1 +
 arch/mips/kvm/vz.c   | 2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9f15539..9c4bdac 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1470,6 +1470,7 @@ config CPU_LOONGSON64
select MIPS_L1_CACHE_SHIFT_6
select GPIOLIB
select SWIOTLB
+   select HAVE_KVM
help
The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of 
processor
cores implements the MIPS64R2 instruction set with many 
extensions,
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index be1b556..4432442 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2008,6 +2008,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips 
*c, unsigned int cpu)
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
+   c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is 
incomplete */
break;
case PRID_IMP_LOONGSON_64G:
c->cputype = CPU_LOONGSON64;
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index fc0f8d5..5f877a9 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -2695,7 +2695,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int 
cpu)
 * prevents a SC on the next VCPU from succeeding by matching a LL on
 * the previous VCPU.
 */
-   if (cpu_guest_has_rw_llb)
+   if (vcpu->kvm->created_vcpus > 1)
write_gc0_lladdr(0);
 
return 0;
-- 
2.7.0

[PATCH V3 12/14] KVM: MIPS: Add CONFIG6 and DIAG registers emulation

[Huacai Chen]

Loongson-3 has CONFIG6 and DIAG registers which need to be emulate.
CONFIG6 is mostly used to enable/disable FTLB and SFB, while DIAG is
mostly used to flush BTB, ITLB, DTLB, VTLB and FTLB.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/include/asm/kvm_host.h |  7 +
 arch/mips/include/asm/mipsregs.h |  7 +
 arch/mips/kvm/tlb.c  | 41 ++
 arch/mips/kvm/vz.c   | 62 +++-
 4 files changed, 116 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 3fd2f1c..30b5e33 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -68,9 +68,11 @@
 #define KVM_REG_MIPS_CP0_CONFIG3   MIPS_CP0_32(16, 3)
 #define KVM_REG_MIPS_CP0_CONFIG4   MIPS_CP0_32(16, 4)
 #define KVM_REG_MIPS_CP0_CONFIG5   MIPS_CP0_32(16, 5)
+#define KVM_REG_MIPS_CP0_CONFIG6   MIPS_CP0_32(16, 6)
 #define KVM_REG_MIPS_CP0_CONFIG7   MIPS_CP0_32(16, 7)
 #define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2)
 #define KVM_REG_MIPS_CP0_XCONTEXT  MIPS_CP0_64(20, 0)
+#define KVM_REG_MIPS_CP0_DIAG  MIPS_CP0_32(22, 0)
 #define KVM_REG_MIPS_CP0_ERROREPC  MIPS_CP0_64(30, 0)
 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
@@ -256,6 +258,7 @@ struct mips_coproc {
 #define MIPS_CP0_WATCH_LO  18
 #define MIPS_CP0_WATCH_HI  19
 #define MIPS_CP0_TLB_XCONTEXT  20
+#define MIPS_CP0_DIAG  22
 #define MIPS_CP0_ECC   26
 #define MIPS_CP0_CACHE_ERR 27
 #define MIPS_CP0_TAG_LO28
@@ -927,6 +930,10 @@ void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, 
unsigned int index,
  unsigned int count);
 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
  unsigned int count);
+#ifdef CONFIG_CPU_LOONGSON64
+void kvm_loongson_clear_guest_vtlb(void);
+void kvm_loongson_clear_guest_ftlb(void);
+#endif
 #endif
 
 void kvm_mips_suspend_mm(int cpu);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 796fe47..ce40fbf 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -674,6 +674,9 @@
 #define MIPS_CONF5_CV  (_ULCAST_(1) << 29)
 #define MIPS_CONF5_K   (_ULCAST_(1) << 30)
 
+#define MIPS_CONF6_INTIMER (_ULCAST_(1) << 6)
+#define MIPS_CONF6_EXTIMER (_ULCAST_(1) << 7)
+#define MIPS_CONF6_SFBEN   (_ULCAST_(1) << 8)
 #define MIPS_CONF6_SYND(_ULCAST_(1) << 13)
 /* proAptiv FTLB on/off bit */
 #define MIPS_CONF6_FTLBEN  (_ULCAST_(1) << 15)
@@ -993,6 +996,8 @@
 /* Disable Branch Return Cache */
 #define R10K_DIAG_D_BRC(_ULCAST_(1) << 22)
 
+/* Flush BTB */
+#define LOONGSON_DIAG_BTB  (_ULCAST_(1) << 1)
 /* Flush ITLB */
 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
 /* Flush DTLB */
@@ -2825,7 +2830,9 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(config5)
+__BUILD_SET_C0(config6)
 __BUILD_SET_C0(config7)
+__BUILD_SET_C0(diag)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
diff --git a/arch/mips/kvm/tlb.c b/arch/mips/kvm/tlb.c
index 7cd9216..1418715 100644
--- a/arch/mips/kvm/tlb.c
+++ b/arch/mips/kvm/tlb.c
@@ -20,6 +20,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -622,6 +623,46 @@ void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, 
unsigned int index,
 }
 EXPORT_SYMBOL_GPL(kvm_vz_load_guesttlb);
 
+#ifdef CONFIG_CPU_LOONGSON64
+void kvm_loongson_clear_guest_vtlb(void)
+{
+   int idx = read_gc0_index();
+
+   /* Set root GuestID for root probe and write of guest TLB entry */
+   set_root_gid_to_guest_gid();
+
+   write_gc0_index(0);
+   guest_tlbinvf();
+   write_gc0_index(idx);
+
+   clear_root_gid();
+   set_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
+}
+EXPORT_SYMBOL_GPL(kvm_loongson_clear_guest_vtlb);
+
+void kvm_loongson_clear_guest_ftlb(void)
+{
+   int i;
+   int idx = read_gc0_index();
+
+   /* Set root GuestID for root probe and write of guest TLB entry */
+   set_root_gid_to_guest_gid();
+
+   for (i = current_cpu_data.tlbsizevtlb;
+i < (current_cpu_data.tlbsizevtlb +
+current_cpu_data.tlbsizeftlbsets);
+i++) {
+   write_gc0_index(i);
+   guest_tlbinvf();
+   }
+   write_gc0_index(idx);
+
+   clear_root_gid();
+   set_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
+}
+EXPORT_SYMBOL_GPL(kvm_loongson_clear_guest_ftlb);
+#endif
+
 #endif
 
 /**
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index e5c751b..fc0f8d5 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -127,6 +127,11 @@ static inline unsigned int 
kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)

[PATCH V3 11/14] KVM: MIPS: Add CPUCFG emulation for Loongson-3

[Huacai Chen]

Loongson-3 overrides lwc2 instructions to implement CPUCFG and CSR
read/write functions. These instructions all cause guest exit so CSR
doesn't benifit KVM guest (and there are always legacy methods to
provide the same functions as CSR). So, we only emulate CPUCFG and let
it return a reduced feature list (which means the virtual CPU doesn't
have any other advanced features, including CSR) in KVM.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/include/asm/kvm_host.h  |  3 ++
 arch/mips/include/uapi/asm/inst.h | 11 ++
 arch/mips/kvm/mips.c  |  3 ++
 arch/mips/kvm/vz.c| 75 +++
 4 files changed, 92 insertions(+)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index f165902..3fd2f1c 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -173,6 +173,9 @@ struct kvm_vcpu_stat {
u64 vz_ghfc_exits;
u64 vz_gpa_exits;
u64 vz_resvd_exits;
+#ifdef CONFIG_CPU_LOONGSON64
+   u64 vz_cpucfg_exits;
+#endif
 #endif
u64 halt_successful_poll;
u64 halt_attempted_poll;
diff --git a/arch/mips/include/uapi/asm/inst.h 
b/arch/mips/include/uapi/asm/inst.h
index 98f97c8..43d1faa 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -1012,6 +1012,16 @@ struct loongson3_lsdc2_format {  /* Loongson-3 
overridden ldc2/sdc2 Load/Store fo
;))
 };
 
+struct loongson3_lscsr_format {/* Loongson-3 CPUCFG read/write 
format */
+   __BITFIELD_FIELD(unsigned int opcode : 6,
+   __BITFIELD_FIELD(unsigned int rs : 5,
+   __BITFIELD_FIELD(unsigned int fr : 5,
+   __BITFIELD_FIELD(unsigned int rd : 5,
+   __BITFIELD_FIELD(unsigned int fd : 5,
+   __BITFIELD_FIELD(unsigned int func : 6,
+   ;))
+};
+
 /*
  * MIPS16e instruction formats (16-bit length)
  */
@@ -1114,6 +1124,7 @@ union mips_instruction {
struct mm16_r5_format mm16_r5_format;
struct loongson3_lswc2_format loongson3_lswc2_format;
struct loongson3_lsdc2_format loongson3_lsdc2_format;
+   struct loongson3_lscsr_format loongson3_lscsr_format;
 };
 
 union mips16e_instruction {
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index ed989ef..9362769 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -68,6 +68,9 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
{ "vz_ghfc",  VCPU_STAT(vz_ghfc_exits),  KVM_STAT_VCPU },
{ "vz_gpa",   VCPU_STAT(vz_gpa_exits),   KVM_STAT_VCPU },
{ "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU },
+#ifdef CONFIG_CPU_LOONGSON64
+   { "vz_cpucfg",VCPU_STAT(vz_cpucfg_exits),KVM_STAT_VCPU },
+#endif
 #endif
{ "halt_successful_poll", VCPU_STAT(halt_successful_poll), 
KVM_STAT_VCPU },
{ "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU 
},
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 63d5b35..e5c751b 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -29,6 +29,7 @@
 #include 
 
 #include "interrupt.h"
+#include "loongson_regs.h"
 
 #include "trace.h"
 
@@ -1092,6 +1093,75 @@ static enum emulation_result kvm_vz_gpsi_cache(union 
mips_instruction inst,
return EMULATE_FAIL;
 }
 
+#ifdef CONFIG_CPU_LOONGSON64
+static enum emulation_result kvm_vz_gpsi_lwc2(union mips_instruction inst,
+ u32 *opc, u32 cause,
+ struct kvm_run *run,
+ struct kvm_vcpu *vcpu)
+{
+   unsigned int rs, rd;
+   unsigned int hostcfg;
+   unsigned long curr_pc;
+   enum emulation_result er = EMULATE_DONE;
+
+   /*
+* Update PC and hold onto current PC in case there is
+* an error and we want to rollback the PC
+*/
+   curr_pc = vcpu->arch.pc;
+   er = update_pc(vcpu, cause);
+   if (er == EMULATE_FAIL)
+   return er;
+
+   rs = inst.loongson3_lscsr_format.rs;
+   rd = inst.loongson3_lscsr_format.rd;
+   switch (inst.loongson3_lscsr_format.fr) {
+   case 0x8:  /* Read CPUCFG */
+   ++vcpu->stat.vz_cpucfg_exits;
+   hostcfg = read_cpucfg(vcpu->arch.gprs[rs]);
+
+   switch (vcpu->arch.gprs[rs]) {
+   case LOONGSON_CFG1:
+   hostcfg &= (LOONGSON_CFG1_FP | LOONGSON_CFG1_MMI |
+   LOONGSON_CFG1_MSA1 | LOONGSON_CFG1_MSA2 |
+   LOONGSON_CFG1_SFBP);
+   vcpu->arch.gprs[rd] = hostcfg;
+   break;
+   case LOONGSON_CFG2:
+   hostcfg &= (LOONGSON_CFG2_LEXT1 | LOONGSON_CFG2_LEXT2 |
+   LOONGSON_CFG2_LEXT3 | LOONGSON_CFG2_LSPW);
+   vcpu->arch.gprs[rd] = hostcfg;
+ 

[PATCH V3 09/14] KVM: MIPS: Add more types of virtual interrupts

[Huacai Chen]

In current implementation, MIPS KVM uses IP2, IP3, IP4 and IP7 for
external interrupt, two kinds of IPIs and timer interrupt respectively,
but Loongson-3 based machines prefer to use IP2, IP3, IP6 and IP7 for
two kinds of external interrupts, IPI and timer interrupt. So we define
two priority-irq mapping tables: kvm_loongson3_priority_to_irq[] for
Loongson-3, and kvm_default_priority_to_irq[] for others. The virtual
interrupt infrastructure is updated to deliver all types of interrupts
from IP2, IP3, IP4, IP6 and IP7.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/interrupt.c | 93 +++
 arch/mips/kvm/interrupt.h | 14 ---
 arch/mips/kvm/mips.c  | 40 ++--
 arch/mips/kvm/vz.c| 53 ---
 4 files changed, 67 insertions(+), 133 deletions(-)

diff --git a/arch/mips/kvm/interrupt.c b/arch/mips/kvm/interrupt.c
index 7257e8b6..d28c2c9c 100644
--- a/arch/mips/kvm/interrupt.c
+++ b/arch/mips/kvm/interrupt.c
@@ -61,27 +61,8 @@ void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
 * the EXC code will be set when we are actually
 * delivering the interrupt:
 */
-   switch (intr) {
-   case 2:
-   kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
-   /* Queue up an INT exception for the core */
-   kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IO);
-   break;
-
-   case 3:
-   kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
-   kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
-   break;
-
-   case 4:
-   kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
-   kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
-   break;
-
-   default:
-   break;
-   }
-
+   kvm_set_c0_guest_cause(vcpu->arch.cop0, 1 << (intr + 8));
+   kvm_mips_queue_irq(vcpu, kvm_irq_to_priority(intr));
 }
 
 void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
@@ -89,26 +70,8 @@ void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
 {
int intr = (int)irq->irq;
 
-   switch (intr) {
-   case -2:
-   kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
-   kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
-   break;
-
-   case -3:
-   kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
-   kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
-   break;
-
-   case -4:
-   kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
-   kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
-   break;
-
-   default:
-   break;
-   }
-
+   kvm_clear_c0_guest_cause(vcpu->arch.cop0, 1 << (-intr + 8));
+   kvm_mips_dequeue_irq(vcpu, kvm_irq_to_priority(-intr));
 }
 
 /* Deliver the interrupt of the corresponding priority, if possible. */
@@ -116,50 +79,20 @@ int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, 
unsigned int priority,
u32 cause)
 {
int allowed = 0;
-   u32 exccode;
+   u32 exccode, ie;
 
struct kvm_vcpu_arch *arch = >arch;
struct mips_coproc *cop0 = vcpu->arch.cop0;
 
-   switch (priority) {
-   case MIPS_EXC_INT_TIMER:
-   if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
-   && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
-   && (kvm_read_c0_guest_status(cop0) & IE_IRQ5)) {
-   allowed = 1;
-   exccode = EXCCODE_INT;
-   }
-   break;
-
-   case MIPS_EXC_INT_IO:
-   if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
-   && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
-   && (kvm_read_c0_guest_status(cop0) & IE_IRQ0)) {
-   allowed = 1;
-   exccode = EXCCODE_INT;
-   }
-   break;
-
-   case MIPS_EXC_INT_IPI_1:
-   if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
-   && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
-   && (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) {
-   allowed = 1;
-   exccode = EXCCODE_INT;
-   }
-   break;
-
-   case MIPS_EXC_INT_IPI_2:
-   if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
-   && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
-   && (kvm_read_c0_guest_status(cop0) & IE_IRQ2)) {
-   allowed = 1;
-   exccode = EXCCODE_INT;
-   }
-   break;
+   if (priority == MIPS_EXC_MAX)
+   return 0;
 
-   default:
-   break;
+   ie = 1 << (kvm_priority_to_irq[priority] + 8);
+   if ((kvm_read_c0_guest_status(cop0) & 

[PATCH V3 10/14] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support

[Huacai Chen]

This patch add Loongson-3 Virtual IPI interrupt support in the kernel,
because emulate it in QEMU is too expensive for performance.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/include/asm/kvm_host.h |  32 ++
 arch/mips/kvm/Makefile   |   3 +
 arch/mips/kvm/emulate.c  |  23 -
 arch/mips/kvm/loongson_ipi.c | 214 +++
 arch/mips/kvm/mips.c |   6 ++
 5 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/kvm/loongson_ipi.c

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index a7758c0..f165902 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -23,6 +23,8 @@
 #include 
 #include 
 
+#include 
+
 /* MIPS KVM register ids */
 #define MIPS_CP0_32(_R, _S)\
(KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
@@ -181,11 +183,39 @@ struct kvm_vcpu_stat {
 struct kvm_arch_memory_slot {
 };
 
+#ifdef CONFIG_CPU_LOONGSON64
+struct ipi_state {
+   uint32_t status;
+   uint32_t en;
+   uint32_t set;
+   uint32_t clear;
+   uint64_t buf[4];
+};
+
+struct loongson_kvm_ipi;
+
+struct ipi_io_device {
+   int node_id;
+   struct loongson_kvm_ipi *ipi;
+   struct kvm_io_device device;
+};
+
+struct loongson_kvm_ipi {
+   spinlock_t lock;
+   struct kvm *kvm;
+   struct ipi_state ipistate[16];
+   struct ipi_io_device dev_ipi[4];
+};
+#endif
+
 struct kvm_arch {
/* Guest physical mm */
struct mm_struct gpa_mm;
/* Mask of CPUs needing GPA ASID flush */
cpumask_t asid_flush_mask;
+#ifdef CONFIG_CPU_LOONGSON64
+   struct loongson_kvm_ipi ipi;
+#endif
 };
 
 #define N_MIPS_COPROC_REGS 32
@@ -1133,6 +1163,8 @@ extern int kvm_mips_trans_mtc0(union mips_instruction 
inst, u32 *opc,
 /* Misc */
 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
+extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
+struct kvm_mips_interrupt *irq);
 
 static inline void kvm_arch_hardware_unsetup(void) {}
 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile
index 0a3cef6..506c4ac 100644
--- a/arch/mips/kvm/Makefile
+++ b/arch/mips/kvm/Makefile
@@ -13,6 +13,9 @@ kvm-objs := $(common-objs-y) mips.o emulate.o entry.o \
fpu.o
 kvm-objs += hypcall.o
 kvm-objs += mmu.o
+ifdef CONFIG_CPU_LOONGSON64
+kvm-objs += loongson_ipi.o
+endif
 
 ifdef CONFIG_KVM_MIPS_VZ
 kvm-objs   += vz.o
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index 754094b..3946499 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -1600,6 +1600,7 @@ enum emulation_result kvm_mips_emulate_store(union 
mips_instruction inst,
 struct kvm_run *run,
 struct kvm_vcpu *vcpu)
 {
+   int r;
enum emulation_result er;
u32 rt;
void *data = run->mmio.data;
@@ -1666,9 +1667,18 @@ enum emulation_result kvm_mips_emulate_store(union 
mips_instruction inst,
goto out_fail;
}
 
-   run->mmio.is_write = 1;
vcpu->mmio_needed = 1;
+   run->mmio.is_write = 1;
vcpu->mmio_is_write = 1;
+
+   r = kvm_io_bus_write(vcpu, KVM_MMIO_BUS,
+   run->mmio.phys_addr, run->mmio.len, data);
+
+   if (!r) {
+   vcpu->mmio_needed = 0;
+   return EMULATE_DONE;
+   }
+
return EMULATE_DO_MMIO;
 
 out_fail:
@@ -1681,6 +1691,7 @@ enum emulation_result kvm_mips_emulate_load(union 
mips_instruction inst,
u32 cause, struct kvm_run *run,
struct kvm_vcpu *vcpu)
 {
+   int r;
enum emulation_result er;
unsigned long curr_pc;
u32 op, rt;
@@ -1745,6 +1756,16 @@ enum emulation_result kvm_mips_emulate_load(union 
mips_instruction inst,
 
run->mmio.is_write = 0;
vcpu->mmio_is_write = 0;
+
+   r = kvm_io_bus_read(vcpu, KVM_MMIO_BUS,
+   run->mmio.phys_addr, run->mmio.len, run->mmio.data);
+
+   if (!r) {
+   kvm_mips_complete_mmio_load(vcpu, run);
+   vcpu->mmio_needed = 0;
+   return EMULATE_DONE;
+   }
+
return EMULATE_DO_MMIO;
 }
 
diff --git a/arch/mips/kvm/loongson_ipi.c b/arch/mips/kvm/loongson_ipi.c
new file mode 100644
index ..3681fc8
--- /dev/null
+++ b/arch/mips/kvm/loongson_ipi.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Loongson-3 Virtual IPI interrupt support.
+ *
+ * Copyright (C) 2019  Loongson Technologies, Inc.  All rights reserved.
+ *
+ * Authors: Chen Zhu 
+ * Authors: Huacai Chen 
+ */
+
+#include 
+
+#define 

[PATCH V3 08/14] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3

[Huacai Chen]

Loongson-3's indexed cache operations need a node-id in the address,
but in KVM guest the node-id may be incorrect. So, let indexed cache
operations cause guest exit on Loongson-3.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/vz.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index f9fbbc16..ab320f0 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -2853,8 +2853,12 @@ static int kvm_vz_hardware_enable(void)
write_c0_guestctl0(MIPS_GCTL0_CP0 |
   (MIPS_GCTL0_AT_GUEST << MIPS_GCTL0_AT_SHIFT) |
   MIPS_GCTL0_CG | MIPS_GCTL0_CF);
-   if (cpu_has_guestctl0ext)
-   set_c0_guestctl0ext(MIPS_GCTL0EXT_CGI);
+   if (cpu_has_guestctl0ext) {
+   if (current_cpu_type() != CPU_LOONGSON64)
+   set_c0_guestctl0ext(MIPS_GCTL0EXT_CGI);
+   else
+   clear_c0_guestctl0ext(MIPS_GCTL0EXT_CGI);
+   }
 
if (cpu_has_guestid) {
write_c0_guestctl1(0);
-- 
2.7.0

[PATCH V3 07/14] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3

[Huacai Chen]

KVM guest has two levels of address translation: guest tlb translates
GVA to GPA, and root tlb translates GPA to HPA. By default guest's CCA
is controlled by guest tlb, but Loongson-3 maintains all cache coherency
by hardware (including multi-core coherency and I/O DMA coherency) so it
prefers all guest mappings be cacheable mappings. Thus, we use root tlb
to control guest's CCA for Loongson-3.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/vz.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 422cd06..f9fbbc16 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -2871,6 +2871,12 @@ static int kvm_vz_hardware_enable(void)
if (cpu_has_guestctl2)
clear_c0_guestctl2(0x3f << 10);
 
+#ifdef CONFIG_CPU_LOONGSON64
+   /* Control guest CCA attribute */
+   if (cpu_has_csr())
+   csr_writel(csr_readl(0xffec) | 0x1, 0xffec);
+#endif
+
return 0;
 }
 
-- 
2.7.0

[PATCH V3 06/14] KVM: MIPS: Introduce and use cpu_guest_has_ldpte

[Huacai Chen]

Loongson-3 has lddir/ldpte instructions and their related CP0 registers
are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use
it to indicate whether we need to save/restore HTW related CP0 registers
(PWBase, PWSize, PWField and PWCtl).

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/include/asm/cpu-features.h |  3 +++
 arch/mips/kernel/cpu-probe.c |  1 +
 arch/mips/kvm/vz.c   | 26 +-
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index 400b123..e127495 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -659,6 +659,9 @@
 #ifndef cpu_guest_has_htw
 #define cpu_guest_has_htw  (cpu_data[0].guest.options & MIPS_CPU_HTW)
 #endif
+#ifndef cpu_guest_has_ldpte
+#define cpu_guest_has_ldpte(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
+#endif
 #ifndef cpu_guest_has_mvh
 #define cpu_guest_has_mvh  (cpu_data[0].guest.options & MIPS_CPU_MVH)
 #endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ca2e6f1..be1b556 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2004,6 +2004,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips 
*c, unsigned int cpu)
 * register, we correct it here.
 */
c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+   c->guest.options |= MIPS_CPU_LDPTE;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 17932ab..422cd06 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1706,7 +1706,7 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu 
*vcpu)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
if (cpu_guest_has_segments)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
-   if (cpu_guest_has_htw)
+   if (cpu_guest_has_htw || cpu_guest_has_ldpte)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)
ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
@@ -1755,7 +1755,7 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, 
u64 __user *indices)
return -EFAULT;
indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
}
-   if (cpu_guest_has_htw) {
+   if (cpu_guest_has_htw || cpu_guest_has_ldpte) {
if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
 sizeof(kvm_vz_get_one_regs_htw)))
return -EFAULT;
@@ -1878,17 +1878,17 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
*v = read_gc0_segctl2();
break;
case KVM_REG_MIPS_CP0_PWBASE:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwbase();
break;
case KVM_REG_MIPS_CP0_PWFIELD:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwfield();
break;
case KVM_REG_MIPS_CP0_PWSIZE:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwsize();
break;
@@ -1896,7 +1896,7 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
*v = (long)read_gc0_wired();
break;
case KVM_REG_MIPS_CP0_PWCTL:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwctl();
break;
@@ -2101,17 +2101,17 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
write_gc0_segctl2(v);
break;
case KVM_REG_MIPS_CP0_PWBASE:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwbase(v);
break;
case KVM_REG_MIPS_CP0_PWFIELD:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwfield(v);
break;
case KVM_REG_MIPS_CP0_PWSIZE:
-   if (!cpu_guest_has_htw)
+   if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;

[PATCH V3 05/14] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd

[Huacai Chen]

Loongson-3 can use lddir/ldpte instuctions to accelerate page table
walking, so use them to lookup gpa_mm.pgd.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/entry.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kvm/entry.c b/arch/mips/kvm/entry.c
index 16e1c93..fd71694 100644
--- a/arch/mips/kvm/entry.c
+++ b/arch/mips/kvm/entry.c
@@ -56,6 +56,7 @@
 #define C0_BADVADDR8, 0
 #define C0_BADINSTR8, 1
 #define C0_BADINSTRP   8, 2
+#define C0_PGD 9, 7
 #define C0_ENTRYHI 10, 0
 #define C0_GUESTCTL1   10, 4
 #define C0_STATUS  12, 0
@@ -307,7 +308,10 @@ static void *kvm_mips_build_enter_guest(void *addr)
 
 #ifdef CONFIG_KVM_MIPS_VZ
/* Save normal linux process pgd (VZ guarantees pgd_reg is set) */
-   UASM_i_MFC0(, K0, c0_kscratch(), pgd_reg);
+   if (cpu_has_ldpte)
+   UASM_i_MFC0(, K0, C0_PWBASE);
+   else
+   UASM_i_MFC0(, K0, c0_kscratch(), pgd_reg);
UASM_i_SW(, K0, offsetof(struct kvm_vcpu_arch, host_pgd), K1);
 
/*
@@ -469,8 +473,10 @@ void *kvm_mips_build_tlb_refill_exception(void *addr, void 
*handler)
u32 *p = addr;
struct uasm_label labels[2];
struct uasm_reloc relocs[2];
+#ifndef CONFIG_CPU_LOONGSON64
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
+#endif
 
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
@@ -490,6 +496,16 @@ void *kvm_mips_build_tlb_refill_exception(void *addr, void 
*handler)
 */
preempt_disable();
 
+#ifdef CONFIG_CPU_LOONGSON64
+   UASM_i_MFC0(, K1, C0_PGD);
+   uasm_i_lddir(, K0, K1, 3);  /* global page dir */
+#ifndef __PAGETABLE_PMD_FOLDED
+   uasm_i_lddir(, K1, K0, 1);  /* middle page dir */
+#endif
+   uasm_i_ldpte(, K1, 0);  /* even */
+   uasm_i_ldpte(, K1, 1);  /* odd */
+   uasm_i_tlbwr();
+#else
/*
 * Now for the actual refill bit. A lot of this can be common with the
 * Linux TLB refill handler, however we don't need to handle so many
@@ -512,6 +528,7 @@ void *kvm_mips_build_tlb_refill_exception(void *addr, void 
*handler)
build_get_ptep(, K0, K1);
build_update_entries(, K0, K1);
build_tlb_write_entry(, , , tlb_random);
+#endif
 
preempt_enable();
 
-- 
2.7.0

[PATCH V3 04/14] KVM: MIPS: Add EVENTFD support which is needed by VHOST

[Huacai Chen]

Add EVENTFD support for KVM/MIPS, which is needed by VHOST. Tested on
Loongson-3 platform.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/kvm/Kconfig | 1 +
 arch/mips/kvm/Makefile| 2 +-
 arch/mips/kvm/trap_emul.c | 3 +++
 arch/mips/kvm/vz.c| 3 +++
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kvm/Kconfig b/arch/mips/kvm/Kconfig
index b91d145..d697752 100644
--- a/arch/mips/kvm/Kconfig
+++ b/arch/mips/kvm/Kconfig
@@ -22,6 +22,7 @@ config KVM
select EXPORT_UASM
select PREEMPT_NOTIFIERS
select KVM_GENERIC_DIRTYLOG_READ_PROTECT
+   select HAVE_KVM_EVENTFD
select HAVE_KVM_VCPU_ASYNC_IOCTL
select KVM_MMIO
select MMU_NOTIFIER
diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile
index 01affc1..0a3cef6 100644
--- a/arch/mips/kvm/Makefile
+++ b/arch/mips/kvm/Makefile
@@ -2,7 +2,7 @@
 # Makefile for KVM support for MIPS
 #
 
-common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o 
eventfd.o)
 
 EXTRA_CFLAGS += -Ivirt/kvm -Iarch/mips/kvm
 
diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c
index 5a11e83..f464506b 100644
--- a/arch/mips/kvm/trap_emul.c
+++ b/arch/mips/kvm/trap_emul.c
@@ -529,6 +529,9 @@ static int kvm_trap_emul_check_extension(struct kvm *kvm, 
long ext)
case KVM_CAP_MIPS_TE:
r = 1;
break;
+   case KVM_CAP_IOEVENTFD:
+   r = 1;
+   break;
default:
r = 0;
break;
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index dde2088..17932ab 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -2927,6 +2927,9 @@ static int kvm_vz_check_extension(struct kvm *kvm, long 
ext)
r = 2;
break;
 #endif
+   case KVM_CAP_IOEVENTFD:
+   r = 1;
+   break;
default:
r = 0;
break;
-- 
2.7.0

[PATCH V3 01/14] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(_cpu_data)

[Huacai Chen]

From: Xing Li 

The code in decode_config4() of arch/mips/kernel/cpu-probe.c

asid_mask = MIPS_ENTRYHI_ASID;
if (config4 & MIPS_CONF4_AE)
asid_mask |= MIPS_ENTRYHI_ASIDX;
set_cpu_asid_mask(c, asid_mask);

set asid_mask to cpuinfo->asid_mask.

So in order to support variable ASID_MASK, KVM_ENTRYHI_ASID should also
be changed to cpu_asid_mask(_cpu_data).

Cc: sta...@vger.kernel.org
Signed-off-by: Xing Li 
[Huacai: Change current_cpu_data to boot_cpu_data for optimization]
Signed-off-by: Huacai Chen 
---
 arch/mips/include/asm/kvm_host.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 2c343c3..a01cee9 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -275,7 +275,7 @@ enum emulation_result {
 #define MIPS3_PG_FRAME 0x3fc0
 
 #define VPN2_MASK  0xe000
-#define KVM_ENTRYHI_ASID   MIPS_ENTRYHI_ASID
+#define KVM_ENTRYHI_ASID   cpu_asid_mask(_cpu_data)
 #define TLB_IS_GLOBAL(x)   ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 #define TLB_VPN2(x)((x).tlb_hi & VPN2_MASK)
 #define TLB_ASID(x)((x).tlb_hi & KVM_ENTRYHI_ASID)
-- 
2.7.0

[PATCH V3 03/14] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16

[Huacai Chen]

Loongson-3 based machines can have as many as 16 CPUs, and so does
memory slots, so increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16.

Signed-off-by: Huacai Chen 
Co-developed-by: Jiaxun Yang 
---
 arch/mips/include/asm/kvm_host.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index caa2b936..a7758c0 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -78,8 +78,8 @@
 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
 
 
-#define KVM_MAX_VCPUS  8
-#define KVM_USER_MEM_SLOTS 8
+#define KVM_MAX_VCPUS  16
+#define KVM_USER_MEM_SLOTS 16
 /* memory slots that does not exposed to userspace */
 #define KVM_PRIVATE_MEM_SLOTS  0
 
-- 
2.7.0

[PATCH V3 02/14] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

[Huacai Chen]

From: Xing Li 

If a CPU support more than 32bit vmbits (which is true for 64bit CPUs),
VPN2_MASK set to fixed 0xe000 will lead to a wrong EntryHi in some
functions such as _kvm_mips_host_tlb_inv().

The cpu_vmbits definition of 32bit CPU in cpu-features.h is 31, so we
still use the old definition.

Cc: sta...@vger.kernel.org
Signed-off-by: Xing Li 
[Huacai: Improve commit messages]
Signed-off-by: Huacai Chen 
---
 arch/mips/include/asm/kvm_host.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index a01cee9..caa2b936 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -274,7 +274,11 @@ enum emulation_result {
 #define MIPS3_PG_SHIFT 6
 #define MIPS3_PG_FRAME 0x3fc0
 
+#if defined(CONFIG_64BIT)
+#define VPN2_MASK  GENMASK(cpu_vmbits - 1, 13)
+#else
 #define VPN2_MASK  0xe000
+#endif
 #define KVM_ENTRYHI_ASID   cpu_asid_mask(_cpu_data)
 #define TLB_IS_GLOBAL(x)   ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
 #define TLB_VPN2(x)((x).tlb_hi & VPN2_MASK)
-- 
2.7.0

[PATCH V3 00/14] KVM: MIPS: Add Loongson-3 support (Host Side)

[Huacai Chen]

We are preparing to add KVM support for Loongson-3. VZ extension is
fully supported in Loongson-3A R4+, and we will not care about old CPUs
(at least now). We already have a full functional Linux kernel (based
on Linux-5.4.x LTS) and QEMU (based on 5.0.0-rc2) and their git
repositories are here:

QEMU: https://github.com/chenhuacai/qemu
Kernel: https://github.com/chenhuacai/linux

Of course these two repositories need to be rework and not suitable for
upstream (especially the commits need to be splitted). We show them here
is just to tell others what we have done, and how KVM/Loongson will look
like.

Our plan is make the KVM host side be upstream first, and after that,
we will make the KVM guest side and QEMU emulator be upstream.

V1 -> V2:
1, Remove "mips: define pud_index() regardless of page table folding"
   because it has been applied.
2, Make Loongson-specific code be guarded by CONFIG_CPU_LOONGSON64.

V2 -> V3:
1, Emulate a reduced feature list of CPUCFG.
2, Fix all possible checkpatch.pl errors and warnings.

Xing Li(2):
 KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(_cpu_data)
 KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits

Huacai Chen(12):
 KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16
 KVM: MIPS: Add EVENTFD support which is needed by VHOST
 KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd
 KVM: MIPS: Introduce and use cpu_guest_has_ldpte
 KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3
 KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3
 KVM: MIPS: Add more types of virtual interrupts
 KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support
 KVM: MIPS: Add CPUCFG emulation for Loongson-3
 KVM: MIPS: Add CONFIG6 and DIAG registers emulation
 KVM: MIPS: Add more MMIO load/store instructions emulation
 KVM: MIPS: Enable KVM support for Loongson-3

Signed-off-by: Huacai Chen 
---
 arch/mips/Kconfig|   1 +
 arch/mips/include/asm/cpu-features.h |   3 +
 arch/mips/include/asm/kvm_host.h |  52 +++-
 arch/mips/include/asm/mipsregs.h |   7 +
 arch/mips/include/uapi/asm/inst.h|  11 +
 arch/mips/kernel/cpu-probe.c |   2 +
 arch/mips/kvm/Kconfig|   1 +
 arch/mips/kvm/Makefile   |   5 +-
 arch/mips/kvm/emulate.c  | 503 ++-
 arch/mips/kvm/entry.c|  19 +-
 arch/mips/kvm/interrupt.c|  93 +--
 arch/mips/kvm/interrupt.h|  14 +-
 arch/mips/kvm/loongson_ipi.c | 214 +++
 arch/mips/kvm/mips.c |  49 +++-
 arch/mips/kvm/tlb.c  |  41 +++
 arch/mips/kvm/trap_emul.c|   3 +
 arch/mips/kvm/vz.c   | 235 +++-
 17 files changed, 1087 insertions(+), 166 deletions(-)
 create mode 100644 arch/mips/kvm/loongson_ipi.c
--
2.7.0

Re: [PATCH v2 02/14] qcrypto/luks: implement encryption key management

[Maxim Levitsky]

On Tue, 2020-04-28 at 14:16 +0100, Daniel P. Berrangé wrote:
> On Sun, Mar 08, 2020 at 05:18:51PM +0200, Maxim Levitsky wrote:
> > Next few patches will expose that functionality
> > to the user.
> > 
> > Signed-off-by: Maxim Levitsky 
> > ---
> >  crypto/block-luks.c | 398 +++-
> >  qapi/crypto.json|  61 ++-
> >  2 files changed, 455 insertions(+), 4 deletions(-)
> > 
> > diff --git a/crypto/block-luks.c b/crypto/block-luks.c
> > index 4861db810c..b11ee08c6d 100644
> > --- a/crypto/block-luks.c
> > +++ b/crypto/block-luks.c
> > +/*
> > + * Erases an keyslot given its index
> > + * Returns:
> > + *0 if the keyslot was erased successfully
> > + *   -1 if a error occurred while erasing the keyslot
> > + *
> > + */
> > +static int
> > +qcrypto_block_luks_erase_key(QCryptoBlock *block,
> > + unsigned int slot_idx,
> > + QCryptoBlockWriteFunc writefunc,
> > + void *opaque,
> > + Error **errp)
> > +{
> > +QCryptoBlockLUKS *luks = block->opaque;
> > +QCryptoBlockLUKSKeySlot *slot = >header.key_slots[slot_idx];
> > +g_autofree uint8_t *garbagesplitkey = NULL;
> > +size_t splitkeylen = luks->header.master_key_len * slot->stripes;
> > +size_t i;
> > +
> > +assert(slot_idx < QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS);
> > +assert(splitkeylen > 0);
> > +garbagesplitkey = g_new0(uint8_t, splitkeylen);
> > +
> > +/* Reset the key slot header */
> > +memset(slot->salt, 0, QCRYPTO_BLOCK_LUKS_SALT_LEN);
> > +slot->iterations = 0;
> > +slot->active = QCRYPTO_BLOCK_LUKS_KEY_SLOT_DISABLED;
> > +
> > +qcrypto_block_luks_store_header(block,  writefunc, opaque, errp);
> 
> This may set  errp and we don't return immediately, so
> 
> > +/*
> > + * Now try to erase the key material, even if the header
> > + * update failed
> > + */
> > +for (i = 0; i < QCRYPTO_BLOCK_LUKS_ERASE_ITERATIONS; i++) {
> > +if (qcrypto_random_bytes(garbagesplitkey, splitkeylen, errp) < 0) {
> 
> ...this may then set errp a second time, which is not permitted.
> 
> This call needs to use a "local_err", and error_propagate(errp, local_err).
> The latter is a no-op if errp is already set.

Fixed! Thanks for pointing this out!

> 
> > +/*
> > + * If we failed to get the random data, still write
> > + * at least zeros to the key slot at least once
> > + */
> > +if (i > 0) {
> > +return -1;
> > +}
> > +}
> > +if (writefunc(block,
> > +  slot->key_offset_sector * 
> > QCRYPTO_BLOCK_LUKS_SECTOR_SIZE,
> > +  garbagesplitkey,
> > +  splitkeylen,
> > +  opaque,
> > +  errp) != splitkeylen) {
> 
> same issue with errp here too.

Fixed too of course
> 
> > +return -1;
> > +}
> > +}
> > +return 0;
> > +}
> 
> 
> > +/*
> > + * Given LUKSKeyslotUpdate command, set @slots_bitmap with all slots
> > + * that will be updated with new password (or erased)
> > + * returns 0 on success, and -1 on failure
> > + */
> > +static int
> > +qcrypto_block_luks_get_update_bitmap(QCryptoBlock *block,
> > + QCryptoBlockReadFunc readfunc,
> > + void *opaque,
> > + const QCryptoBlockAmendOptionsLUKS 
> > *opts,
> > + unsigned long *slots_bitmap,
> > + Error **errp)
> > +{
> > +const QCryptoBlockLUKS *luks = block->opaque;
> > +size_t i;
> > +
> > +bitmap_zero(slots_bitmap, QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS);
> > +
> > +if (opts->has_keyslot) {
> > +/* keyslot set, select only this keyslot */
> > +int keyslot = opts->keyslot;
> > +
> > +if (keyslot < 0 || keyslot >= QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS) {
> > +error_setg(errp,
> > +   "Invalid slot %u specified, must be between 0 and 
> > %u",
> > +   keyslot, QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS - 1);
> > +return -1;
> > +}
> > +bitmap_set(slots_bitmap, keyslot, 1);
> > +
> > +} else if (opts->has_old_secret) {
> > +/* initially select all active keyslots */
> > +for (i = 0; i < QCRYPTO_BLOCK_LUKS_NUM_KEY_SLOTS; i++) {
> > +if (qcrypto_block_luks_slot_active(luks, i)) {
> > +bitmap_set(slots_bitmap, i, 1);
> > +}
> > +}
> > +} else {
> > +/* find a free keyslot */
> > +int slot = qcrypto_block_luks_find_free_keyslot(luks);
> > +
> > +if (slot == -1) {
> > +error_setg(errp,
> > +   "Can't add a keyslot - all key slots are in use");
> > +return -1;
> > +

Re: [PATCH v2 2/2] hw/pci/pcie: Replace PCI_DEVICE() casts with existing variable

[Marcel Apfelbaum]

On 4/27/20 9:24 PM, Julia Suvorova wrote:

A little cleanup is possible because of hotplug_pdev introduction.

Signed-off-by: Julia Suvorova 
---
  hw/pci/pcie.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 6b48d04d2c..abc99b6eff 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -449,7 +449,7 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, 
DeviceState *dev,
  pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
 PCI_EXP_LNKSTA_DLLLA);
  }
-pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
+pcie_cap_slot_event(hotplug_pdev,
  PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
  }
  }
@@ -490,7 +490,7 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
*hotplug_dev,
  return;
  }
  
-pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, _err);

+pcie_cap_slot_plug_common(hotplug_pdev, dev, _err);
  if (local_err) {
  error_propagate(errp, local_err);
  return;
@@ -509,7 +509,7 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
*hotplug_dev,
  return;
  }
  
-pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));

+pcie_cap_slot_push_attention_button(hotplug_pdev);
  }
  
  /* pci express slot for pci express root/downstream port


Reviewed-by: Marcel Apfelbaum 

Thanks,
Marcel

Re: [PATCH v2 1/2] hw/pci/pcie: Forbid hot-plug if it's disabled on the slot

[Marcel Apfelbaum]

On 4/27/20 9:24 PM, Julia Suvorova wrote:

Raise an error when trying to hot-plug/unplug a device through QMP to a device
with disabled hot-plug capability. This makes the device behaviour more
consistent and provides an explanation of the failure in the case of
asynchronous unplug.

Signed-off-by: Julia Suvorova 
---
v2:
 * Change error text [Igor, Michael]
 * Move cleanup to a separate patch [Marcel]

  hw/pci/pcie.c | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 0eb3a2a5d2..6b48d04d2c 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -415,6 +415,7 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, 
DeviceState *dev,
  {
  PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
  uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
+uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
  PCIDevice *pci_dev = PCI_DEVICE(dev);
  
  /* Don't send event when device is enabled during qemu machine creation:

@@ -430,6 +431,13 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, 
DeviceState *dev,
  return;
  }
  
+/* Check if hot-plug is disabled on the slot */

+if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
+error_setg(errp, "Hot-plug failed: unsupported by the port device 
'%s'",
+ DEVICE(hotplug_pdev)->id);
+return;
+}
+
  /* To enable multifunction hot-plug, we just ensure the function
   * 0 added last. When function 0 is added, we set the sltsta and
   * inform OS via event notification.
@@ -470,6 +478,17 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler 
*hotplug_dev,
  Error *local_err = NULL;
  PCIDevice *pci_dev = PCI_DEVICE(dev);
  PCIBus *bus = pci_get_bus(pci_dev);
+PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev);
+uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap;
+uint32_t sltcap = pci_get_word(exp_cap + PCI_EXP_SLTCAP);
+
+/* Check if hot-unplug is disabled on the slot */
+if ((sltcap & PCI_EXP_SLTCAP_HPC) == 0) {
+error_setg(errp, "Hot-unplug failed: "
+ "unsupported by the port device '%s'",
+ DEVICE(hotplug_pdev)->id);
+return;
+}
  
  pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev), dev, _err);

  if (local_err) {


Reviewed-by: Marcel Apfelbaum 

Thanks,
Marcel

Re: [INFO] Some preliminary performance data

[Ahmed Karaman]

Thanks Mr. Aleksandar for the introduction.
I'm really looking forward to working with the QEMU developers community
this summer.
Wishing all of you health and safety.


On Sun, May 3, 2020, 1:25 AM Aleksandar Markovic <
aleksandar.qemu.de...@gmail.com> wrote:

> [correcting some email addresses]
>
> нед, 3. мај 2020. у 01:20 Aleksandar Markovic <
> aleksandar.qemu.de...@gmail.com> је написао/ла:
>
>> Hi, all.
>>
>> I just want to share with you some bits and pieces of data that I got
>> while doing some preliminary experimentation for the GSoC project "TCG
>> Continuous Benchmarking", that Ahmed Karaman, a student of the fourth final
>> year of Electical Engineering Faculty in Cairo, will execute.
>>
>> *User Mode*
>>
>>* As expected, for any program dealing with any substantional
>> floating-point calculation, softfloat library will be the the heaviest CPU
>> cycles consumer.
>>* We plan to examine the performance behaviour of non-FP programs
>> (integer arithmetic), or even non-numeric programs (sorting strings, for
>> example).
>>
>> *System Mode*
>>
>>* I did profiling of booting several machines using a tool called
>> callgrind (a part of valgrind). The tool offers pletora of information,
>> however it looks it is little confused by usage of coroutines, and that
>> makes some of its reports look very illogical, or plain ugly. Still, it
>> seems valid data can be extracted from it. Without going into details, here
>> is what it says for one machine (bear in mind that results may vary to a
>> great extent between machines):
>>  ** The booting involved six threads, one for display handling, one
>> for emulations, and four more. The last four did almost nothing during
>> boot, just almost entire time siting idle, waiting for something. As far as
>> "Total Instruction Fetch Count" (this is the main measure used in
>> callgrind), they were distributed in proportion 1:3 between display thread
>> and emulation thread (the rest of threads were negligible) (but,
>> interestingly enough, for another machine that proportion was 1:20).
>>  ** The display thread is dominated by vga_update_display() function
>> (21.5% "self" time, and 51.6% "self + callees" time, called almost 4
>> times). Other functions worth mentioning are
>> cpu_physical_memory_snapshot_get_dirty() and
>> memory_region_snapshot_get_dirty(), which are very small functions, but are
>> both invoked over 26 000 000 times, and contribute with over 20% of display
>> thread instruction fetch count together.
>>  ** Focusing now on emulation thread, "Total Instruction Fetch
>> Counts" were roughly distributed this way:
>>- 15.7% is execution of GIT-ed code from translation block
>> buffer
>>- 39.9% is execution of helpers
>>- 44.4% is code translation stage, including some coroutine
>> activities
>> Top two among helpers:
>>   - helper_le_stl_memory()
>>   - helper_lookup_tb_ptr() (this one is invoked whopping 36 000
>> 000 times)
>> Single largest instruction consumer of code translation:
>>   - liveness_pass_1(), that constitutes 21.5% of the entire
>> "emulation thread" consumption, or, in other way, almost half of code
>> translation stage (that sits at 44.4%)
>>
>> Please take all this with a little grain of salt, since these results are
>> just of preliminary nature.
>>
>> I would like to use this opportunity to welcome Ahmed Karaman, a talented
>> young man from Egypt, into QEMU development community, that'll work on "TCG
>> Continuous Benchmarking" project this summer. Please do help them in his
>> first steps as our colleague. Best luck to Ahmed!
>>
>> Thanks,
>> Aleksandar
>>
>>