Re: [PATCH v2] hw/usb/host-libusb.c: fix build with kernel < 5.0

[Gerd Hoffmann]

On Sun, Dec 13, 2020 at 10:30:16PM +0100, Fabrice Fontaine wrote:
> USBDEVFS_GET_SPEED is used since version 5.2.0 and
> https://gitlab.com/qemu-project/qemu/-/commit/202d69a715a4b1824dcd7ec1683d027ed2bae6d3
> resulting in the following build failure with kernel < 5.0:
> 
> ../hw/usb/host-libusb.c: In function 'usb_host_open':
> ../hw/usb/host-libusb.c:953:32: error: 'USBDEVFS_GET_SPEED' undeclared (first 
> use in this function); did you mean 'USBDEVFS_GETDRIVER'?
>  int rc = ioctl(hostfd, USBDEVFS_GET_SPEED, NULL);
> ^~
> USBDEVFS_GETDRIVER
> 
> A tentative was made to fix this build failure with
> https://gitlab.com/qemu-project/qemu/-/commit/4969e697c15ac536d5c0700381d5d026ef7f0588
> 
> However, the assumption that distros with old kernels also have old
> libusb is just wrong so also add a check for defined(USBDEVFS_GET_SPEED)
> 
> Signed-off-by: Fabrice Fontaine 

Added to usb queue.

thanks,
  Gerd

Re: [PATCH] kvm: Take into account the unaligned section size when preparing bitmap

[Zenghui Yu]

Hi Keqian, Peter,

On 2020/12/15 15:23, zhukeqian wrote:


On 2020/12/14 23:36, Peter Xu wrote:

On Mon, Dec 14, 2020 at 10:14:11AM +0800, zhukeqian wrote:

[...]


Though indeed I must confess I don't know how it worked in general when host
page size != target page size, at least for migration.  For example, I believe
kvm dirty logging is host page size based, though migration should be migrating
pages in guest page size granule when it spots a dirty bit set.


[1]


Hi Peter,


Keqian,


OTOH I'm more worried on the other question on how we handle guest psize !=
host psize case for migration now...

I think it does not matter when guest_psize != host_psize, as we only need to 
interact with
stage2 page tables during migration. Stage2 is enough to tracking guest dirty 
memory, and even
if guest close stage1, we also can do a successful migration.


I don't know why 2-stage matters here, since I believe KVM can track dirty
pages either using two dimentional paging or shadowing, however it's always
done in host small page size.  The question I'm confused is there seems to have
a size mismatch between qemu migration and what kvm does [1].  For example, how
migration works on ARM64 where host has psize==4K while guest has psize=64K.


Hi Peter,

OK, I got it ;-) Do you mean qemu_real_host_page_size != TARGET_PAGE_SIZE?
After my analysis, I see that when qemu_real_host_page_size != TARGET_PAGE_SIZE,
there are some problems indeed. I have send out some patches, please check 
whether they solve this
problem, thanks!


Now I see what your concern is :) Thanks both for the explanation and
the further fix!


Zenghui

RE: [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

[Jiangyifei]

> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:30 AM
> To: Jiangyifei 
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; Bastian Koppelmann
> ; Anup Patel ;
> yinyipeng ; Alistair Francis
> ; kvm-ri...@lists.infradead.org; Palmer Dabbelt
> ; dengkai (A) ; Wubin (H)
> ; Zhanghailiang 
> Subject: Re: [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by
> KVM when kvm enabled
> 
> On Thu, Dec 3, 2020 at 4:47 AM Yifei Jiang  wrote:
> >
> > Only support supervisor external interrupt currently.
> >
> > Signed-off-by: Yifei Jiang 
> > Signed-off-by: Yipeng Yin 
> > ---
> >  hw/intc/sifive_plic.c| 31 ++-
> >  target/riscv/kvm.c   | 19 +++
> >  target/riscv/kvm_riscv.h |  1 +
> >  3 files changed, 42 insertions(+), 9 deletions(-)
> >
> > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index
> > 97a1a27a9a..a419ca3a3c 100644
> > --- a/hw/intc/sifive_plic.c
> > +++ b/hw/intc/sifive_plic.c
> > @@ -31,6 +31,8 @@
> >  #include "target/riscv/cpu.h"
> >  #include "sysemu/sysemu.h"
> >  #include "migration/vmstate.h"
> > +#include "sysemu/kvm.h"
> > +#include "kvm_riscv.h"
> >
> >  #define RISCV_DEBUG_PLIC 0
> >
> > @@ -147,15 +149,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
> >  continue;
> >  }
> >  int level = sifive_plic_irqs_pending(plic, addrid);
> > -switch (mode) {
> > -case PLICMode_M:
> > -riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
> BOOL_TO_MASK(level));
> > -break;
> > -case PLICMode_S:
> > -riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
> BOOL_TO_MASK(level));
> > -break;
> > -default:
> > -break;
> > +if (kvm_enabled()) {
> > +if (mode == PLICMode_M) {
> > +continue;
> > +}
> > +#ifdef CONFIG_KVM
> > +kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
> > +#endif
> 
> What if kvm_enalbed() is true, but CONFIG_KVM isn't defined?
> 
> Alistair
> 

Impossible. It will cause compilation failure without CONFIG_KVM. We also
introduce kvm-stub.c to solve the compilation failure like other architectures.

We will introduce kvm-stub.c in next series.

Yifei

> > +} else {
> > +switch (mode) {
> > +case PLICMode_M:
> > +riscv_cpu_update_mip(RISCV_CPU(cpu),
> > + MIP_MEIP,
> BOOL_TO_MASK(level));
> > +break;
> > +case PLICMode_S:
> > +riscv_cpu_update_mip(RISCV_CPU(cpu),
> > + MIP_SEIP,
> BOOL_TO_MASK(level));
> > +break;
> > +default:
> > +break;
> > +}
> >  }
> >  }
> >
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > 6250ca0c7d..b01ff0754c 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -454,3 +454,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> >  env->satp = 0;
> >  }
> >
> > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) {
> > +int ret;
> > +unsigned virq = level ? KVM_INTERRUPT_SET :
> KVM_INTERRUPT_UNSET;
> > +
> > +if (irq != IRQ_S_EXT) {
> > +return;
> > +}
> > +
> > +if (!kvm_enabled()) {
> > +return;
> > +}
> > +
> > +ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, );
> > +if (ret < 0) {
> > +perror("Set irq failed");
> > +abort();
> > +}
> > +}
> > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index
> > f38c82bf59..ed281bdce0 100644
> > --- a/target/riscv/kvm_riscv.h
> > +++ b/target/riscv/kvm_riscv.h
> > @@ -20,5 +20,6 @@
> >  #define QEMU_KVM_RISCV_H
> >
> >  void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> >
> >  #endif
> > --
> > 2.19.1
> >
> >

RE: [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine

[Jiangyifei]

> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:26 AM
> To: Jiangyifei 
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; Bastian Koppelmann
> ; Anup Patel ;
> yinyipeng ; Alistair Francis
> ; kvm-ri...@lists.infradead.org; Palmer Dabbelt
> ; dengkai (A) ; Wubin (H)
> ; Zhanghailiang 
> Subject: Re: [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time
> frequency for virt machine
> 
> On Thu, Dec 3, 2020 at 4:57 AM Yifei Jiang  wrote:
> >
> > Currently, time base frequency was fixed as SIFIVE_CLINT_TIMEBASE_FREQ.
> > Here introduce "time-frequency" property to set time base frequency
> > dynamically of which default value is still
> > SIFIVE_CLINT_TIMEBASE_FREQ. The virt machine uses frequency of the first
> cpu to create clint and fdt.
> >
> > Signed-off-by: Yifei Jiang 
> > Signed-off-by: Yipeng Yin 
> > ---
> >  hw/riscv/virt.c| 18 ++
> >  target/riscv/cpu.c |  3 +++
> >  target/riscv/cpu.h |  2 ++
> >  3 files changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index
> > 47b7018193..788a7237b6 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -178,7 +178,7 @@ static void create_pcie_irq_map(void *fdt, char
> > *nodename,  }
> >
> >  static void create_fdt(RISCVVirtState *s, const struct MemmapEntry
> *memmap,
> > -uint64_t mem_size, const char *cmdline)
> > +uint64_t mem_size, const char *cmdline, uint64_t
> > + timebase_frequency)
> >  {
> >  void *fdt;
> >  int i, cpu, socket;
> > @@ -225,7 +225,7 @@ static void create_fdt(RISCVVirtState *s, const
> > struct MemmapEntry *memmap,
> >
> >  qemu_fdt_add_subnode(fdt, "/cpus");
> >  qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
> > -  SIFIVE_CLINT_TIMEBASE_FREQ);
> > +  timebase_frequency);
> >  qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
> >  qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
> >  qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); @@ -510,6 +510,7
> @@
> > static void virt_machine_init(MachineState *machine)
> >  target_ulong firmware_end_addr, kernel_start_addr;
> >  uint32_t fdt_load_addr;
> >  uint64_t kernel_entry;
> > +uint64_t timebase_frequency = 0;
> >  DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
> >  int i, j, base_hartid, hart_count;
> >  CPUState *cs;
> > @@ -553,12 +554,20 @@ static void virt_machine_init(MachineState
> *machine)
> >  hart_count, _abort);
> >  sysbus_realize(SYS_BUS_DEVICE(>soc[i]), _abort);
> >
> > +if (!timebase_frequency) {
> > +timebase_frequency = RISCV_CPU(first_cpu)->env.frequency;
> > +}
> > +/* If vcpu's time frequency is not specified, we use default
> frequency */
> > +if (!timebase_frequency) {
> > +timebase_frequency = SIFIVE_CLINT_TIMEBASE_FREQ;
> > +}
> > +
> >  /* Per-socket CLINT */
> >  sifive_clint_create(
> >  memmap[VIRT_CLINT].base + i *
> memmap[VIRT_CLINT].size,
> >  memmap[VIRT_CLINT].size, base_hartid, hart_count,
> >  SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE,
> SIFIVE_TIME_BASE,
> > -SIFIVE_CLINT_TIMEBASE_FREQ, true);
> > +timebase_frequency, true);
> >
> >  /* Per-socket PLIC hart topology configuration string */
> >  plic_hart_config_len =
> > @@ -610,7 +619,8 @@ static void virt_machine_init(MachineState
> *machine)
> >  main_mem);
> >
> >  /* create device tree */
> > -create_fdt(s, memmap, machine->ram_size,
> machine->kernel_cmdline);
> > +create_fdt(s, memmap, machine->ram_size,
> machine->kernel_cmdline,
> > +   timebase_frequency);
> >
> >  /* boot rom */
> >  memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index
> > 439dc89ee7..66f35bcbbf 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -494,6 +494,8 @@ static void riscv_cpu_realize(DeviceState *dev,
> > Error **errp)
> >
> >  riscv_cpu_register_gdb_regs_for_features(cs);
> >
> > +env->user_frequency = env->frequency;
> > +
> >  qemu_init_vcpu(cs);
> >  cpu_reset(cs);
> >
> > @@ -531,6 +533,7 @@ static Property riscv_cpu_properties[] = {
> >  DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> >  DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> >  DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec,
> > DEFAULT_RSTVEC),
> > +DEFINE_PROP_UINT64("time-frequency", RISCVCPU, env.frequency, 0),
> 
> Why not set the default to SIFIVE_CLINT_TIMEBASE_FREQ?
> 

When the time frequency is not specified, it will follow the host or the 
migration
source. And we define 0 as 

Re: [PATCH v3 00/18] Support Multifd for RDMA migration

[Zheng Chuan]

Hi, Dave.

Since qemu 6.0 is open and some patches of this series have been reviewed, 
might you have time to continue reviewing rest of them ?

On 2020/10/25 10:29, Zheng Chuan wrote:
> 
> 
> On 2020/10/24 3:02, Dr. David Alan Gilbert wrote:
>> * Zheng Chuan (zhengch...@huawei.com) wrote:
>>>
>>>
>>> On 2020/10/21 17:25, Zhanghailiang wrote:
 Hi zhengchuan,

> -Original Message-
> From: zhengchuan
> Sent: Saturday, October 17, 2020 12:26 PM
> To: quint...@redhat.com; dgilb...@redhat.com
> Cc: Zhanghailiang ; Chenzhendong (alex)
> ; Xiexiangyou ; wanghao
> (O) ; yubihong ;
> fengzhim...@huawei.com; qemu-devel@nongnu.org
> Subject: [PATCH v3 00/18] Support Multifd for RDMA migration
>
> Now I continue to support multifd for RDMA migration based on my colleague
> zhiming's work:)
>
> The previous RFC patches is listed below:
> v1:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg669455.html
> v2:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg679188.html
>
> As descried in previous RFC, the RDMA bandwidth is not fully utilized for 
> over
> 25Gigabit NIC because of single channel for RDMA migration.
> This patch series is going to support multifd for RDMA migration based on 
> multifd
> framework.
>
> Comparsion is between origion and multifd RDMA migration is re-tested for 
> v3.
> The VM specifications for migration are as follows:
> - VM use 4k page;
> - the number of VCPU is 4;
> - the total memory is 16Gigabit;
> - use 'mempress' tool to pressurize VM(mempress 8000 500);
> - use 25Gigabit network card to migrate;
>
> For origin RDMA and MultiRDMA migration, the total migration times of VM 
> are
> as follows:
> +
> | | NOT rdma-pin-all | rdma-pin-all |
> +
> | origin RDMA |   26 s   | 29 s |
> -
> |  MultiRDMA  |   16 s   | 17 s |
> +
>
> Test the multifd RDMA migration like this:
> virsh migrate --live --multiFd --migrateuri

 There is no option '--multiFd' for virsh commands, It seems that, we added 
 this private option for internal usage.
 It's better to provide testing method by using qemu commands.


>>> Hi, Hailiang
>>> Yes, it should be, will update in V4.
>>>
>>> Also, Ping.
>>>
>>> Dave, Juan.
>>>
>>> Any suggestion and comment about this series? Hope this feature could catch 
>>> up with qemu 5.2.
>>
>> It's a bit close; I'm not sure if I'll have time to review it on Monday
>> before the pull.
>>
>> Dave
>>
> Yes, it is.
> Then we may wait for next merge window after fully review:)
> 
 Thanks.

> rdma://192.168.1.100 [VM] --listen-address 0.0.0.0
> qemu+tcp://192.168.1.100/system --verbose
>
> v2 -> v3:
> create multifd ops for both tcp and rdma
> do not export rdma to avoid multifd code in mess
> fix build issue for non-rdma
> fix some codestyle and buggy code
>
> Chuan Zheng (18):
>   migration/rdma: add the 'migrate_use_rdma_pin_all' function
>   migration/rdma: judge whether or not the RDMA is used for migration
>   migration/rdma: create multifd_setup_ops for Tx/Rx thread
>   migration/rdma: add multifd_setup_ops for rdma
>   migration/rdma: do not need sync main for rdma
>   migration/rdma: export MultiFDSendParams/MultiFDRecvParams
>   migration/rdma: add rdma field into multifd send/recv param
>   migration/rdma: export getQIOChannel to get QIOchannel in rdma
>   migration/rdma: add multifd_rdma_load_setup() to setup multifd rdma
>   migration/rdma: Create the multifd recv channels for RDMA
>   migration/rdma: record host_port for multifd RDMA
>   migration/rdma: Create the multifd send channels for RDMA
>   migration/rdma: Add the function for dynamic page registration
>   migration/rdma: register memory for multifd RDMA channels
>   migration/rdma: only register the memory for multifd channels
>   migration/rdma: add rdma_channel into Migrationstate field
>   migration/rdma: send data for both rdma-pin-all and NOT rdma-pin-all
> mode
>   migration/rdma: RDMA cleanup for multifd migration
>
>  migration/migration.c |  24 +++
>  migration/migration.h |  11 ++
>  migration/multifd.c   |  97 +-
>  migration/multifd.h   |  24 +++
>  migration/qemu-file.c |   5 +
>  migration/qemu-file.h |   1 +
>  migration/rdma.c  | 503
> +-
>  7 files changed, 653 insertions(+), 12 deletions(-)
>
> --
> 1.8.3.1

 .

>>>
>>> -- 
>>> Regards.
>>> Chuan
>>>
> 

-- 

Re: [PATCH] kvm: Take into account the unaligned section size when preparing bitmap

[zhukeqian]

On 2020/12/14 23:36, Peter Xu wrote:
> On Mon, Dec 14, 2020 at 10:14:11AM +0800, zhukeqian wrote:
> 
> [...]
> 
> Though indeed I must confess I don't know how it worked in general when 
> host
> page size != target page size, at least for migration.  For example, I 
> believe
> kvm dirty logging is host page size based, though migration should be 
> migrating
> pages in guest page size granule when it spots a dirty bit set.
> 
> [1]
> 
>> Hi Peter,
> 
> Keqian,
> 
>>> OTOH I'm more worried on the other question on how we handle guest psize !=
>>> host psize case for migration now...
>> I think it does not matter when guest_psize != host_psize, as we only need 
>> to interact with
>> stage2 page tables during migration. Stage2 is enough to tracking guest 
>> dirty memory, and even
>> if guest close stage1, we also can do a successful migration.
> 
> I don't know why 2-stage matters here, since I believe KVM can track dirty
> pages either using two dimentional paging or shadowing, however it's always
> done in host small page size.  The question I'm confused is there seems to 
> have
> a size mismatch between qemu migration and what kvm does [1].  For example, 
> how
> migration works on ARM64 where host has psize==4K while guest has psize=64K.
> 
Hi Peter,

OK, I got it ;-) Do you mean qemu_real_host_page_size != TARGET_PAGE_SIZE?
After my analysis, I see that when qemu_real_host_page_size != TARGET_PAGE_SIZE,
there are some problems indeed. I have send out some patches, please check 
whether they solve this
problem, thanks!

Keqian.

> Thanks,
> 

[PATCH 0/2] accel: kvm: Some bugfixes for kvm dirty log

[Keqian Zhu]

Keqian Zhu (2):
  accel: kvm: Fix memory waste under mismatch page size
  accel: kvm: Add aligment check for kvm_log_clear_one_slot

 accel/kvm/kvm-all.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

-- 
2.23.0

[PATCH 2/2] accel: kvm: Add aligment check for kvm_log_clear_one_slot

[Keqian Zhu]

The parameters start and size are transfered from QEMU memory
emulation layer. It can promise that they are TARGET_PAGE_SIZE
aligned. However, KVM needs they are qemu_real_page_size aligned.

Though no caller breaks this aligned requirement currently, we'd
better add an explicit check to avoid future breaking.

Signed-off-by: Keqian Zhu 
---
 accel/kvm/kvm-all.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index c5e06288eb..3d0e3aa872 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -701,6 +701,11 @@ static int kvm_log_clear_one_slot(KVMSlot *mem, int as_id, 
uint64_t start,
 unsigned long *bmap_clear = NULL, psize = qemu_real_host_page_size;
 int ret;
 
+/* Make sure start and size are psize aligned */
+if (!QEMU_IS_ALIGNED(start, psize) || !QEMU_IS_ALIGNED(size, psize)) {
+return -EINVAL;
+}
+
 /*
  * We need to extend either the start or the size or both to
  * satisfy the KVM interface requirement.  Firstly, do the start
-- 
2.23.0

RE: [PATCH RFC v4 09/15] target/riscv: Add host cpu type

[Jiangyifei]

> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:22 AM
> To: Jiangyifei 
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; Bastian Koppelmann
> ; Anup Patel ;
> yinyipeng ; Alistair Francis
> ; kvm-ri...@lists.infradead.org; Palmer Dabbelt
> ; dengkai (A) ; Wubin (H)
> ; Zhanghailiang 
> Subject: Re: [PATCH RFC v4 09/15] target/riscv: Add host cpu type
> 
> On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang  wrote:
> >
> > Currently, host cpu is inherited simply.
> >
> > Signed-off-by: Yifei Jiang 
> > Signed-off-by: Yipeng Yin 
> > ---
> >  target/riscv/cpu.c | 6 ++
> >  target/riscv/cpu.h | 1 +
> >  2 files changed, 7 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index
> > faee98a58c..439dc89ee7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -186,6 +186,10 @@ static void rv32_imafcu_nommu_cpu_init(Object
> > *obj)
> >
> >  #endif
> >
> > +static void riscv_host_cpu_init(Object *obj) { }
> > +
> >  static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)  {
> >  ObjectClass *oc;
> > @@ -641,10 +645,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> >  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,
> rvxx_sifive_e_cpu_init),
> >  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,
> rv32_imafcu_nommu_cpu_init),
> >  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> rvxx_sifive_u_cpu_init),
> > +DEFINE_CPU(TYPE_RISCV_CPU_HOST,
> riscv_host_cpu_init),
> >  #elif defined(TARGET_RISCV64)
> >  DEFINE_CPU(TYPE_RISCV_CPU_BASE64,
> riscv_base_cpu_init),
> >  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,
> rvxx_sifive_e_cpu_init),
> >  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,
> rvxx_sifive_u_cpu_init),
> > +DEFINE_CPU(TYPE_RISCV_CPU_HOST,
> riscv_host_cpu_init),
> 
> Shouldn't this only be included if KVM is configured? Also it should be shared
> between RV32 and RV64.
> 
> Alistair
> 

Yes, It should be included by CONFIG_KVM and be shared between RV32 and RV64.

Yifei

> >  #endif
> >  };
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index
> > ad1c90f798..4288898019 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -43,6 +43,7 @@
> >  #define TYPE_RISCV_CPU_SIFIVE_E51
> RISCV_CPU_TYPE_NAME("sifive-e51")
> >  #define TYPE_RISCV_CPU_SIFIVE_U34
> RISCV_CPU_TYPE_NAME("sifive-u34")
> >  #define TYPE_RISCV_CPU_SIFIVE_U54
> RISCV_CPU_TYPE_NAME("sifive-u54")
> > +#define TYPE_RISCV_CPU_HOST
> RISCV_CPU_TYPE_NAME("host")
> >
> >  #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))  #define
> > RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> > --
> > 2.19.1
> >
> >

RE: [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM

[Jiangyifei]

> -Original Message-
> From: Alistair Francis [mailto:alistai...@gmail.com]
> Sent: Wednesday, December 9, 2020 6:19 AM
> To: Jiangyifei 
> Cc: qemu-devel@nongnu.org Developers ; open
> list:RISC-V ; Zhangxiaofeng (F)
> ; Sagar Karandikar
> ; open list:Overall ;
> libvir-l...@redhat.com; Bastian Koppelmann
> ; Anup Patel ;
> yinyipeng ; Alistair Francis
> ; kvm-ri...@lists.infradead.org; Palmer Dabbelt
> ; dengkai (A) ; Wubin (H)
> ; Zhanghailiang 
> Subject: Re: [PATCH RFC v4 06/15] target/riscv: Support start kernel directly 
> by
> KVM
> 
> On Thu, Dec 3, 2020 at 4:58 AM Yifei Jiang  wrote:
> >
> > Get kernel and fdt start address in virt.c, and pass them to KVM when
> > cpu reset. In addition, add kvm_riscv.h to place riscv specific
> > interface.
> 
> This doesn't seem right. Why do we need to do this? Other architectures don't
> seem to do this.
> 
> Writing to the CPU from the board like this looks fishy and probably breaks
> some QOM rules.
> 
> Alistair
> 

Sorry for the delayed reply.

We need to set the starting address of the kernel and fdt to vcpu, which is 
implemented
by firmware bootloader under other architectures and RISC-V emulators. However, 
the
RISC-V virtual machine does not have bootloader, so we boot the kernel directly.
In the future, we will support firmware loading.

Before supporting the firmware bootloader, we can add a public interface 
instead of
modifying the CPU instance directly to comply with the QOM rules.

Yifei

> >
> > Signed-off-by: Yifei Jiang 
> > Signed-off-by: Yipeng Yin 
> > ---
> >  hw/riscv/virt.c  |  8 
> >  target/riscv/cpu.c   |  4 
> >  target/riscv/cpu.h   |  3 +++
> >  target/riscv/kvm.c   | 15 +++
> >  target/riscv/kvm_riscv.h | 24 
> >  5 files changed, 54 insertions(+)
> >  create mode 100644 target/riscv/kvm_riscv.h
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index
> > 25cea7aa67..47b7018193 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -42,6 +42,7 @@
> >  #include "sysemu/sysemu.h"
> >  #include "hw/pci/pci.h"
> >  #include "hw/pci-host/gpex.h"
> > +#include "sysemu/kvm.h"
> >
> >  #if defined(TARGET_RISCV32)
> >  # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin"
> > @@ -511,6 +512,7 @@ static void virt_machine_init(MachineState
> *machine)
> >  uint64_t kernel_entry;
> >  DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
> >  int i, j, base_hartid, hart_count;
> > +CPUState *cs;
> >
> >  /* Check socket count limit */
> >  if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { @@ -660,6
> > +662,12 @@ static void virt_machine_init(MachineState *machine)
> >virt_memmap[VIRT_MROM].size,
> kernel_entry,
> >fdt_load_addr, s->fdt);
> >
> > +for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
> > +RISCVCPU *riscv_cpu = RISCV_CPU(cs);
> > +riscv_cpu->env.kernel_addr = kernel_entry;
> > +riscv_cpu->env.fdt_addr = fdt_load_addr;
> > +}
> > +
> >  /* SiFive Test MMIO device */
> >  sifive_test_create(memmap[VIRT_TEST].base);
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index
> > 6a0264fc6b..faee98a58c 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -29,6 +29,7 @@
> >  #include "hw/qdev-properties.h"
> >  #include "migration/vmstate.h"
> >  #include "fpu/softfloat-helpers.h"
> > +#include "kvm_riscv.h"
> >
> >  /* RISC-V CPU definitions */
> >
> > @@ -330,6 +331,9 @@ static void riscv_cpu_reset(DeviceState *dev)
> >  cs->exception_index = EXCP_NONE;
> >  env->load_res = -1;
> >  set_default_nan_mode(1, >fp_status);
> > +#ifdef CONFIG_KVM
> > +kvm_riscv_reset_vcpu(cpu);
> > +#endif
> >  }
> >
> >  static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info
> > *info) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index
> > c0a326c843..ad1c90f798 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -233,6 +233,9 @@ struct CPURISCVState {
> >
> >  /* Fields from here on are preserved across CPU reset. */
> >  QEMUTimer *timer; /* Internal timer */
> > +
> > +hwaddr kernel_addr;
> > +hwaddr fdt_addr;
> >  };
> >
> >  OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, diff --git
> > a/target/riscv/kvm.c b/target/riscv/kvm.c index 8b206ce99c..6250ca0c7d
> > 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -37,6 +37,7 @@
> >  #include "hw/irq.h"
> >  #include "qemu/log.h"
> >  #include "hw/loader.h"
> > +#include "kvm_riscv.h"
> >
> >  static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)  { @@ -439,3
> > +440,17 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
> > {
> >  return 0;
> >  }
> > +
> > +void kvm_riscv_reset_vcpu(RISCVCPU *cpu) {
> > +CPURISCVState *env = >env;
> > +
> > +if (!kvm_enabled()) {
> > +return;
> > +}
> > +env->pc = cpu->env.kernel_addr;
> > + 

[PATCH 1/2] accel: kvm: Fix memory waste under mismatch page size

[Keqian Zhu]

When handle dirty log, we face qemu_real_host_page_size and
TARGET_PAGE_SIZE. The first one is the granule of KVM dirty
bitmap, and the second one is the granule of QEMU dirty bitmap.

Generally speaking, qemu_real_host_page_size >= TARGET_PAGE_SIZE,
so misuse TARGET_PAGE_SIZE to init kvmslot dirty_bmap may waste
memory. For example, when qemu_real_host_page_size is 64K and
TARGET_PAGE_SIZE is 4K, this bugfix can save 93.75% memory.

Signed-off-by: Keqian Zhu 
---
 accel/kvm/kvm-all.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index baaa54249d..c5e06288eb 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -620,8 +620,12 @@ static void kvm_memslot_init_dirty_bitmap(KVMSlot *mem)
  * too, in most cases).
  * So for now, let's align to 64 instead of HOST_LONG_BITS here, in
  * a hope that sizeof(long) won't become >8 any time soon.
+ *
+ * Note: the granule of kvm dirty log is qemu_real_host_page_size.
+ * And mem->memory_size is aligned to it (otherwise this mem can't
+ * be registered to KVM).
  */
-hwaddr bitmap_size = ALIGN(((mem->memory_size) >> TARGET_PAGE_BITS),
+hwaddr bitmap_size = ALIGN(mem->memory_size / qemu_real_host_page_size,
 /*HOST_LONG_BITS*/ 64) / 8;
 mem->dirty_bmap = g_malloc0(bitmap_size);
 }
-- 
2.23.0

[PATCH v4] file-posix: detect the lock using the real file

[Li Feng]

This patch addresses this issue:
When accessing a volume on an NFS filesystem without supporting the file lock,
tools, like qemu-img, will complain "Failed to lock byte 100".

In the original code, the qemu_has_ofd_lock will test the lock on the
"/dev/null" pseudo-file. Actually, the file.locking is per-drive property,
which depends on the underlay filesystem.

In this patch, add a new 'qemu_has_file_lock' to detect whether the
file supports the file lock. And disable the lock when the underlay file
system doesn't support locks.

Signed-off-by: Li Feng 
---
v4: use the fd as the qemu_has_file_lock argument.
v3: don't call the qemu_has_ofd_lock, use a new function instead.
v2: remove the refactoring.
---
 block/file-posix.c   | 66 +---
 include/qemu/osdep.h |  1 +
 util/osdep.c | 19 +
 3 files changed, 58 insertions(+), 28 deletions(-)

diff --git a/block/file-posix.c b/block/file-posix.c
index 806764f7e3..9708212f01 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -584,6 +584,21 @@ static int raw_open_common(BlockDriverState *bs, QDict 
*options,
 s->use_linux_io_uring = (aio == BLOCKDEV_AIO_OPTIONS_IO_URING);
 #endif
 
+s->open_flags = open_flags;
+raw_parse_flags(bdrv_flags, >open_flags, false);
+
+s->fd = -1;
+fd = qemu_open(filename, s->open_flags, errp);
+ret = fd < 0 ? -errno : 0;
+
+if (ret < 0) {
+if (ret == -EROFS) {
+ret = -EACCES;
+}
+goto fail;
+}
+s->fd = fd;
+
 locking = qapi_enum_parse(_lookup,
   qemu_opt_get(opts, "locking"),
   ON_OFF_AUTO_AUTO, _err);
@@ -607,6 +622,13 @@ static int raw_open_common(BlockDriverState *bs, QDict 
*options,
 break;
 case ON_OFF_AUTO_AUTO:
 s->use_lock = qemu_has_ofd_lock();
+if (s->use_lock && !qemu_has_file_lock(s->fd)) {
+/*
+ * When the os supports the OFD lock, but the filesystem doesn't
+ * support, just disable the file lock.
+ */
+s->use_lock = false;
+}
 break;
 default:
 abort();
@@ -625,22 +647,6 @@ static int raw_open_common(BlockDriverState *bs, QDict 
*options,
 s->drop_cache = qemu_opt_get_bool(opts, "drop-cache", true);
 s->check_cache_dropped = qemu_opt_get_bool(opts, "x-check-cache-dropped",
false);
-
-s->open_flags = open_flags;
-raw_parse_flags(bdrv_flags, >open_flags, false);
-
-s->fd = -1;
-fd = qemu_open(filename, s->open_flags, errp);
-ret = fd < 0 ? -errno : 0;
-
-if (ret < 0) {
-if (ret == -EROFS) {
-ret = -EACCES;
-}
-goto fail;
-}
-s->fd = fd;
-
 /* Check s->open_flags rather than bdrv_flags due to auto-read-only */
 if (s->open_flags & O_RDWR) {
 ret = check_hdev_writable(s->fd);
@@ -2388,6 +2394,7 @@ raw_co_create(BlockdevCreateOptions *options, Error 
**errp)
 int fd;
 uint64_t perm, shared;
 int result = 0;
+bool use_lock;
 
 /* Validate options and set default values */
 assert(options->driver == BLOCKDEV_DRIVER_FILE);
@@ -2428,19 +2435,22 @@ raw_co_create(BlockdevCreateOptions *options, Error 
**errp)
 perm = BLK_PERM_WRITE | BLK_PERM_RESIZE;
 shared = BLK_PERM_ALL & ~BLK_PERM_RESIZE;
 
-/* Step one: Take locks */
-result = raw_apply_lock_bytes(NULL, fd, perm, ~shared, false, errp);
-if (result < 0) {
-goto out_close;
-}
+use_lock = qemu_has_file_lock(fd);
+if (use_lock) {
+/* Step one: Take locks */
+result = raw_apply_lock_bytes(NULL, fd, perm, ~shared, false, errp);
+if (result < 0) {
+goto out_close;
+}
 
-/* Step two: Check that nobody else has taken conflicting locks */
-result = raw_check_lock_bytes(fd, perm, shared, errp);
-if (result < 0) {
-error_append_hint(errp,
-  "Is another process using the image [%s]?\n",
-  file_opts->filename);
-goto out_unlock;
+/* Step two: Check that nobody else has taken conflicting locks */
+result = raw_check_lock_bytes(fd, perm, shared, errp);
+if (result < 0) {
+error_append_hint(errp,
+  "Is another process using the image [%s]?\n",
+  file_opts->filename);
+goto out_unlock;
+}
 }
 
 /* Clear the file by truncating it to 0 */
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index f9ec8c84e9..c7587be99d 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -513,6 +513,7 @@ int qemu_lock_fd(int fd, int64_t start, int64_t len, bool 
exclusive);
 int qemu_unlock_fd(int fd, int64_t start, int64_t len);
 int qemu_lock_fd_test(int fd, int64_t start, int64_t len, bool exclusive);
 bool qemu_has_ofd_lock(void);
+bool 

[PATCH v2 5/8] hw/mips: Use bl_gen_kernel_jump to generate bootloaders

[Jiaxun Yang]

Replace embedded binary with generated code.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/boston.c| 17 ++---
 hw/mips/fuloong2e.c | 28 
 hw/mips/malta.c | 41 ++---
 3 files changed, 16 insertions(+), 70 deletions(-)

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index c3b94c68e1..b62c7d 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -27,6 +27,7 @@
 #include "hw/ide/ahci.h"
 #include "hw/loader.h"
 #include "hw/loader-fit.h"
+#include "hw/mips/bootloader.h"
 #include "hw/mips/cps.h"
 #include "hw/pci-host/xilinx-pcie.h"
 #include "hw/qdev-clock.h"
@@ -324,21 +325,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, 
hwaddr fdt_addr,
  * a2/$6 = 0
  * a3/$7 = 0
  */
-stl_p(p++, 0x2404fffe); /* li   $4, -2 */
-/* lui  $5, hi(fdt_addr) */
-stl_p(p++, 0x3c05 | ((fdt_addr >> 16) & 0x));
-if (fdt_addr & 0x) {/* ori  $5, lo(fdt_addr) */
-stl_p(p++, 0x34a5 | (fdt_addr & 0x));
-}
-stl_p(p++, 0x3406); /* li   $6, 0 */
-stl_p(p++, 0x3407); /* li   $7, 0 */
-
-/* Load kernel entry address & jump to it */
-/* lui  $25, hi(kernel_entry) 
*/
-stl_p(p++, 0x3c19 | ((kernel_entry >> 16) & 0x));
-/* ori  $25, lo(kernel_entry) 
*/
-stl_p(p++, 0x3739 | (kernel_entry & 0x));
-stl_p(p++, 0x0329); /* jr   $25 */
+bl_gen_jump_kernel(, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
 }
 
 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 64cd4b98ca..9b0eb8a314 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -33,6 +33,7 @@
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/block/flash.h"
 #include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
 #include "hw/mips/cpudevs.h"
 #include "hw/pci/pci.h"
 #include "qemu/log.h"
@@ -195,30 +196,9 @@ static void write_bootloader(CPUMIPSState *env, uint8_t 
*base,
 /* Second part of the bootloader */
 p = (uint32_t *)(base + 0x040);
 
-/* lui a0, 0 */
-stl_p(p++, 0x3c04);
-/* ori a0, a0, 2 */
-stl_p(p++, 0x34840002);
-/* lui a1, high(ENVP_VADDR) */
-stl_p(p++, 0x3c05 | ((ENVP_VADDR >> 16) & 0x));
-/* ori a1, a0, low(ENVP_VADDR) */
-stl_p(p++, 0x34a5 | (ENVP_VADDR & 0x));
-/* lui a2, high(ENVP_VADDR + 8) */
-stl_p(p++, 0x3c06 | (((ENVP_VADDR + 8) >> 16) & 0x));
-/* ori a2, a2, low(ENVP_VADDR + 8) */
-stl_p(p++, 0x34c6 | ((ENVP_VADDR + 8) & 0x));
-/* lui a3, high(env->ram_size) */
-stl_p(p++, 0x3c07 | (loaderparams.ram_size >> 16));
-/* ori a3, a3, low(env->ram_size) */
-stl_p(p++, 0x34e7 | (loaderparams.ram_size & 0x));
-/* lui ra, high(kernel_addr) */
-stl_p(p++, 0x3c1f | ((kernel_addr >> 16) & 0x));
-/* ori ra, ra, low(kernel_addr) */
-stl_p(p++, 0x37ff | (kernel_addr & 0x));
-/* jr ra */
-stl_p(p++, 0x03e8);
-/* nop */
-stl_p(p++, 0x);
+bl_gen_jump_kernel(, ENVP_VADDR - 64, 2, ENVP_VADDR,
+   ENVP_VADDR + 8, loaderparams.ram_size,
+   kernel_addr);
 }
 
 static void main_cpu_reset(void *opaque)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9afc0b427b..ffd67b8293 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -37,6 +37,7 @@
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/block/flash.h"
 #include "hw/mips/mips.h"
+#include "hw/mips/bootloader.h"
 #include "hw/mips/cpudevs.h"
 #include "hw/pci/pci.h"
 #include "sysemu/sysemu.h"
@@ -844,6 +845,7 @@ static void write_bootloader_nanomips(uint8_t *base, 
uint64_t run_addr,
 static void write_bootloader(uint8_t *base, uint64_t run_addr,
  uint64_t kernel_entry)
 {
+target_ulong a0;
 uint32_t *p;
 
 /* Small bootloader */
@@ -872,30 +874,6 @@ static void write_bootloader(uint8_t *base, uint64_t 
run_addr,
 /* Second part of the bootloader */
 p = (uint32_t *) (base + 0x580);
 
-if (semihosting_get_argc()) {
-/* Preserve a0 content as arguments have been passed */
-stl_p(p++, 0x);  /* nop */
-} else {
-stl_p(p++, 0x24040002);  /* addiu a0, zero, 2 */
-}
-
-/* lui sp, high(ENVP_VADDR) */
-stl_p(p++, 0x3c1d | (((ENVP_VADDR - 64) >> 16) & 0x));
-/* ori sp, sp, low(ENVP_VADDR) */
-stl_p(p++, 0x37bd | ((ENVP_VADDR - 64) & 0x));
-/* lui a1, high(ENVP_VADDR) */
-stl_p(p++, 0x3c05 | ((ENVP_VADDR >> 16) & 0x));
-/* ori a1, a1, low(ENVP_VADDR) */
-stl_p(p++, 0x34a5 | (ENVP_VADDR & 0x));
-/* lui 

[PATCH v2 6/8] target/mips/addr: Add translation helpers for KSEG1

[Jiaxun Yang]

It's useful for bootloader to do IO opreations.

Signed-off-by: Jiaxun Yang 
---
 target/mips/addr.c | 10 ++
 target/mips/cpu.h  |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/target/mips/addr.c b/target/mips/addr.c
index 27a6036c45..86f1c129c9 100644
--- a/target/mips/addr.c
+++ b/target/mips/addr.c
@@ -40,6 +40,16 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, 
uint64_t addr)
 return addr | 0x4000ll;
 }
 
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr)
+{
+return addr & 0x1fffll;
+}
+
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr)
+{
+return (addr & 0x1fffll) | 0xa000ll;
+}
+
 bool mips_um_ksegs_enabled(void)
 {
 return mips_um_ksegs;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3ac21d0e9c..0bb1218a57 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1303,6 +1303,8 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t 
addr);
 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
 
 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
+uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr);
+uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
 bool mips_um_ksegs_enabled(void);
 void mips_um_ksegs_enable(void);
 
-- 
2.29.2

[PATCH v2 8/8] hw/mips/boston: Use bootloader helper to set GCRs

[Jiaxun Yang]

Translate embedded assembly into IO writes which is more
readable.

Also hardcode cm_base at boot time instead of reading from CP0.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/boston.c | 45 -
 1 file changed, 12 insertions(+), 33 deletions(-)

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index b62c7d..9f08aa7285 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr 
kernel_entry, hwaddr fdt_addr,
 const uint32_t gic_base = 0x1612;
 const uint32_t cpc_base = 0x1620;
 
-/* Move CM GCRs */
 if (is_64b) {
-stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
-stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
+bl_gen_write_u64(, cm_base,
+cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + 
GCR_BASE_OFS));
+bl_gen_write_u64(, gic_base | GCR_GIC_BASE_GICEN_MSK,
+cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+bl_gen_write_u64(, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
 } else {
-stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
-stl_p(p++, 0x00084100); /* sll  $8, $8, 4 */
+bl_gen_write_u32(, cm_base,
+cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + 
GCR_BASE_OFS));
+bl_gen_write_u32(, gic_base | GCR_GIC_BASE_GICEN_MSK,
+cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+bl_gen_write_u32(, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
 }
-stl_p(p++, 0x3c09a000); /* lui  $9, 0xa000 */
-stl_p(p++, 0x01094025); /* or   $8, $9 */
-stl_p(p++, 0x3c0a | (cm_base >> 16));   /* lui  $10, cm_base >> 16 */
-if (is_64b) {
-stl_p(p++, 0xfd0a0008); /* sd   $10, 0x8($8) */
-} else {
-stl_p(p++, 0xad0a0008); /* sw   $10, 0x8($8) */
-}
-stl_p(p++, 0x012a4025); /* or   $8, $10 */
-
-/* Move & enable GIC GCRs */
-stl_p(p++, 0x3c09 | (gic_base >> 16));  /* lui  $9, gic_base >> 16 */
-stl_p(p++, 0x35290001); /* ori  $9, 0x1 */
-if (is_64b) {
-stl_p(p++, 0xfd090080); /* sd   $9, 0x80($8) */
-} else {
-stl_p(p++, 0xad090080); /* sw   $9, 0x80($8) */
-}
-
-/* Move & enable CPC GCRs */
-stl_p(p++, 0x3c09 | (cpc_base >> 16));  /* lui  $9, cpc_base >> 16 */
-stl_p(p++, 0x35290001); /* ori  $9, 0x1 */
-if (is_64b) {
-stl_p(p++, 0xfd090088); /* sd   $9, 0x88($8) */
-} else {
-stl_p(p++, 0xad090088); /* sw   $9, 0x88($8) */
-}
-
 /*
  * Setup argument registers to follow the UHI boot protocol:
  *
-- 
2.29.2

[PATCH v2 7/8] hw/mips/malta: Use bootloader helper to set BAR resgiters

[Jiaxun Yang]

Translate embedded assembly into IO writes which is more
readable.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/malta.c | 68 ++---
 1 file changed, 19 insertions(+), 49 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ffd67b8293..2799bc36c7 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -875,55 +875,25 @@ static void write_bootloader(uint8_t *base, uint64_t 
run_addr,
 p = (uint32_t *) (base + 0x580);
 
 /* Load BAR registers as done by YAMON */
-stl_p(p++, 0x3c09b400);  /* lui t1, 0xb400 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c08df00);  /* lui t0, 0xdf00 */
-#else
-stl_p(p++, 0x340800df);  /* ori t0, r0, 0x00df */
-#endif
-stl_p(p++, 0xad280068);  /* sw t0, 0x0068(t1) */
-
-stl_p(p++, 0x3c09bbe0);  /* lui t1, 0xbbe0 */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c08c000);  /* lui t0, 0xc000 */
-#else
-stl_p(p++, 0x340800c0);  /* ori t0, r0, 0x00c0 */
-#endif
-stl_p(p++, 0xad280048);  /* sw t0, 0x0048(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c084000);  /* lui t0, 0x4000 */
-#else
-stl_p(p++, 0x34080040);  /* ori t0, r0, 0x0040 */
-#endif
-stl_p(p++, 0xad280050);  /* sw t0, 0x0050(t1) */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c088000);  /* lui t0, 0x8000 */
-#else
-stl_p(p++, 0x34080080);  /* ori t0, r0, 0x0080 */
-#endif
-stl_p(p++, 0xad280058);  /* sw t0, 0x0058(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c083f00);  /* lui t0, 0x3f00 */
-#else
-stl_p(p++, 0x3408003f);  /* ori t0, r0, 0x003f */
-#endif
-stl_p(p++, 0xad280060);  /* sw t0, 0x0060(t1) */
-
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c08c100);  /* lui t0, 0xc100 */
-#else
-stl_p(p++, 0x340800c1);  /* ori t0, r0, 0x00c1 */
-#endif
-stl_p(p++, 0xad280080);  /* sw t0, 0x0080(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
-stl_p(p++, 0x3c085e00);  /* lui t0, 0x5e00 */
-#else
-stl_p(p++, 0x3408005e);  /* ori t0, r0, 0x005e */
-#endif
-stl_p(p++, 0xad280088);  /* sw t0, 0x0088(t1) */
+/* move GT64120 registers from 0x1400 to 0x1be0 */
+bl_gen_write_u32(, cpu_to_be32(0xdf00),
+cpu_mips_phys_to_kseg1(NULL, 0x1468));
+
+/* setup MEM-to-PCI0 mapping */
+/* setup PCI0 io window to 0x1800-0x181f */
+bl_gen_write_u32(, cpu_to_be32(0xc000),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00048));
+bl_gen_write_u32(, cpu_to_be32(0x4000),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00050));
+/* setup PCI0 mem windows */
+bl_gen_write_u32(, cpu_to_be32(0x8000),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00058));
+bl_gen_write_u32(, cpu_to_be32(0x3f00),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00060));
+bl_gen_write_u32(, cpu_to_be32(0xc100),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00080));
+bl_gen_write_u32(, cpu_to_be32(0x5e00),
+cpu_mips_phys_to_kseg1(NULL, 0x1be00088));
 
 if (semihosting_get_argc()) {
 a0 = 0;
-- 
2.29.2

[PATCH v2 4/8] hw/mips: Add a bootloader helper

[Jiaxun Yang]

Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/bootloader.c | 157 +++
 hw/mips/meson.build  |   2 +-
 include/hw/mips/bootloader.h |  48 +++
 3 files changed, 206 insertions(+), 1 deletion(-)
 create mode 100644 hw/mips/bootloader.c
 create mode 100644 include/hw/mips/bootloader.h

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
new file mode 100644
index 00..97916ffd24
--- /dev/null
+++ b/hw/mips/bootloader.c
@@ -0,0 +1,157 @@
+/*
+ * Utility for QEMU MIPS to generate it's simple bootloader
+ *
+ * Instructions used here are carefully selected to keep compatibility with
+ * MIPS Release 6.
+ *
+ * Copyright (C) 2020 Jiaxun Yang 
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+#include "hw/mips/bootloader.h"
+
+/* Base types */
+static void bl_gen_nop(uint32_t **p)
+{
+stl_p(*p, 0);
+*p = *p + 1;
+}
+
+static void bl_gen_r_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt,
+bl_reg rd, uint8_t shift, uint8_t funct)
+{
+uint32_t insn = 0;
+
+insn = deposit32(insn, 26, 6, opcode);
+insn = deposit32(insn, 21, 5, rs);
+insn = deposit32(insn, 16, 5, rt);
+insn = deposit32(insn, 11, 5, rd);
+insn = deposit32(insn, 6, 5, shift);
+insn = deposit32(insn, 0, 6, funct);
+
+stl_p(*p, insn);
+*p = *p + 1;
+}
+
+static void bl_gen_i_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt,
+uint16_t imm)
+{
+uint32_t insn = 0;
+
+insn = deposit32(insn, 26, 6, opcode);
+insn = deposit32(insn, 21, 5, rs);
+insn = deposit32(insn, 16, 5, rt);
+insn = deposit32(insn, 0, 16, imm);
+
+stl_p(*p, insn);
+*p = *p + 1;
+}
+
+static bool bootcpu_supports_isa(uint64_t isa_mask)
+{
+return cpu_supports_isa(_CPU(first_cpu)->env, isa_mask);
+}
+
+/* Single instructions */
+static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
+{
+if (bootcpu_supports_isa(ISA_MIPS3)) {
+bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
+} else {
+g_assert_not_reached(); /* unsupported */
+}
+}
+
+static void bl_gen_jalr(uint32_t **p, bl_reg rs)
+{
+bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x9);
+}
+
+static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
+{
+/* R6: It's a alias of AUI with RS = 0 */
+bl_gen_i_type(p, 0xf, 0, rt, imm);
+}
+
+static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
+{
+bl_gen_i_type(p, 0xd, rs, rt, imm);
+}
+
+static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+{
+bl_gen_i_type(p, 0x2b, base, rt, offset);
+}
+
+static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
+{
+if (bootcpu_supports_isa(ISA_MIPS3)) {
+bl_gen_i_type(p, 0x3f, base, rt, offset);
+} else {
+g_assert_not_reached(); /* unsupported */
+}
+}
+
+/* Pseudo instructions */
+static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
+{
+bl_gen_lui(p, rt, extract32(imm, 16, 16));
+bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
+}
+
+static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
+{
+bl_gen_li(p, rt, extract64(imm, 32, 32));
+bl_gen_dsll(p, rt, rt, 16);
+bl_gen_ori(p, rt, rt, extract64(imm, 16, 16));
+bl_gen_dsll(p, rt, rt, 16);
+bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
+}
+
+static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
+{
+if (bootcpu_supports_isa(ISA_MIPS3)) {
+bl_gen_dli(p, rt, imm); /* 64bit */
+} else {
+bl_gen_li(p, rt, imm); /* 32bit */
+}
+}
+
+/* Helpers */
+void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
+{
+bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
+bl_gen_jalr(p, BL_REG_T9);
+bl_gen_nop(p); /* delay slot */
+}
+
+void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0,
+target_ulong a1, target_ulong a2, target_ulong a3,
+target_ulong kernel_addr)
+{
+bl_gen_load_ulong(p, BL_REG_SP, sp);
+bl_gen_load_ulong(p, BL_REG_A0, a0);
+bl_gen_load_ulong(p, BL_REG_A1, a1);
+bl_gen_load_ulong(p, BL_REG_A2, a2);
+bl_gen_load_ulong(p, BL_REG_A3, a3);
+
+bl_gen_jump_to(p, kernel_addr);
+}
+
+void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr)
+{
+bl_gen_li(p, BL_REG_K0, val);
+bl_gen_load_ulong(p, BL_REG_K1, addr);
+bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
+}
+
+void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr)
+{
+bl_gen_dli(p, BL_REG_K0, val);
+bl_gen_load_ulong(p, BL_REG_K1, addr);
+bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
+}
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 

[PATCH v2 3/8] hw/mips: Use address translation helper to handle ENVP_ADDR

[Jiaxun Yang]

It will signed extend vaddr properly.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/fuloong2e.c | 24 +-
 hw/mips/malta.c | 62 ++---
 2 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index fc4d7f21ed..64cd4b98ca 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -49,7 +49,8 @@
 
 #define DEBUG_FULOONG2E_INIT
 
-#define ENVP_ADDR   0x80002000l
+#define ENVP_PADDR  0x2000
+#define ENVP_VADDR  cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
 #define ENVP_NB_ENTRIES 16
 #define ENVP_ENTRY_SIZE 256
 
@@ -100,7 +101,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, 
int index,
 }
 
 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
-prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
+prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
 
 va_start(ap, string);
 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
@@ -172,8 +173,7 @@ static uint64_t load_kernel(CPUMIPSState *env)
 prom_set(prom_buf, index++, "modetty0=38400n8r");
 prom_set(prom_buf, index++, NULL);
 
-rom_add_blob_fixed("prom", prom_buf, prom_size,
-   cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
+rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
 
 g_free(prom_buf);
 return kernel_entry;
@@ -199,14 +199,14 @@ static void write_bootloader(CPUMIPSState *env, uint8_t 
*base,
 stl_p(p++, 0x3c04);
 /* ori a0, a0, 2 */
 stl_p(p++, 0x34840002);
-/* lui a1, high(ENVP_ADDR) */
-stl_p(p++, 0x3c05 | ((ENVP_ADDR >> 16) & 0x));
-/* ori a1, a0, low(ENVP_ADDR) */
-stl_p(p++, 0x34a5 | (ENVP_ADDR & 0x));
-/* lui a2, high(ENVP_ADDR + 8) */
-stl_p(p++, 0x3c06 | (((ENVP_ADDR + 8) >> 16) & 0x));
-/* ori a2, a2, low(ENVP_ADDR + 8) */
-stl_p(p++, 0x34c6 | ((ENVP_ADDR + 8) & 0x));
+/* lui a1, high(ENVP_VADDR) */
+stl_p(p++, 0x3c05 | ((ENVP_VADDR >> 16) & 0x));
+/* ori a1, a0, low(ENVP_VADDR) */
+stl_p(p++, 0x34a5 | (ENVP_VADDR & 0x));
+/* lui a2, high(ENVP_VADDR + 8) */
+stl_p(p++, 0x3c06 | (((ENVP_VADDR + 8) >> 16) & 0x));
+/* ori a2, a2, low(ENVP_VADDR + 8) */
+stl_p(p++, 0x34c6 | ((ENVP_VADDR + 8) & 0x));
 /* lui a3, high(env->ram_size) */
 stl_p(p++, 0x3c07 | (loaderparams.ram_size >> 16));
 /* ori a3, a3, low(env->ram_size) */
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 1fbb8a3220..9afc0b427b 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -62,7 +62,8 @@
 #include "hw/mips/cps.h"
 #include "hw/qdev-clock.h"
 
-#define ENVP_ADDR   0x80002000l
+#define ENVP_PADDR  0x2000
+#define ENVP_VADDR  cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
 #define ENVP_NB_ENTRIES 16
 #define ENVP_ENTRY_SIZE 256
 
@@ -656,29 +657,29 @@ static void write_bootloader_nanomips(uint8_t *base, 
uint64_t run_addr,
 /* li a0,2  */
 }
 
-stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
+stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
 
-stw_p(p++, NM_HI2(ENVP_ADDR - 64));
-/* lui sp,%hi(ENVP_ADDR - 64)   */
+stw_p(p++, NM_HI2(ENVP_VADDR - 64));
+/* lui sp,%hi(ENVP_VADDR - 64)   */
 
-stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
-/* ori sp,sp,%lo(ENVP_ADDR - 64) */
+stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
+/* ori sp,sp,%lo(ENVP_VADDR - 64) */
 
-stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
+stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
 
-stw_p(p++, NM_HI2(ENVP_ADDR));
-/* lui a1,%hi(ENVP_ADDR)*/
+stw_p(p++, NM_HI2(ENVP_VADDR));
+/* lui a1,%hi(ENVP_VADDR)*/
 
-stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
-/* ori a1,a1,%lo(ENVP_ADDR) */
+stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
+/* ori a1,a1,%lo(ENVP_VADDR) */
 
-stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
+stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
 
-stw_p(p++, NM_HI2(ENVP_ADDR + 8));
-/* lui a2,%hi(ENVP_ADDR + 8)*/
+stw_p(p++, NM_HI2(ENVP_VADDR + 8));
+/* lui a2,%hi(ENVP_VADDR + 8)*/
 
-stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
-/* ori a2,a2,%lo(ENVP_ADDR + 8) */
+stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
+/* ori a2,a2,%lo(ENVP_VADDR + 8) */
 
 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
 
@@ -878,18 +879,18 @@ static void write_bootloader(uint8_t 

[PATCH v2 2/8] hw/mips/malta: Use address translation helper to calculate bootloader_run_addr

[Jiaxun Yang]

So it will sign extend adresses properly.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/malta.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 7db009a3e9..1fbb8a3220 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1302,9 +1302,9 @@ void mips_malta_init(MachineState *machine)
 /* For KVM we reserve 1MB of RAM for running bootloader */
 if (kvm_enabled()) {
 ram_low_size -= 0x10;
-bootloader_run_addr = 0x4000 + ram_low_size;
+bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, 
ram_low_size);
 } else {
-bootloader_run_addr = 0xbfc0;
+bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
 }
 
 /* Write a small bootloader to the flash location. */
-- 
2.29.2

[PATCH v2 1/8] hw/mips: Make bootloader addresses unsgined

[Jiaxun Yang]

Address should be unsigned anyway, otherwise it may carry
calculations wrongly.

Signed-off-by: Jiaxun Yang 
---
 hw/mips/fuloong2e.c | 12 ++--
 hw/mips/malta.c | 22 +++---
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 45c596f4fe..fc4d7f21ed 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -107,9 +107,9 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, 
int index,
 va_end(ap);
 }
 
-static int64_t load_kernel(CPUMIPSState *env)
+static uint64_t load_kernel(CPUMIPSState *env)
 {
-int64_t kernel_entry, kernel_high, initrd_size;
+uint64_t kernel_entry, kernel_high, initrd_size;
 int index = 0;
 long kernel_size;
 ram_addr_t initrd_offset;
@@ -118,8 +118,8 @@ static int64_t load_kernel(CPUMIPSState *env)
 
 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL,
-   (uint64_t *)_entry, NULL,
-   (uint64_t *)_high, NULL,
+   _entry, NULL,
+   _high, NULL,
0, EM_MIPS, 1, 0);
 if (kernel_size < 0) {
 error_report("could not load kernel '%s': %s",
@@ -180,7 +180,7 @@ static int64_t load_kernel(CPUMIPSState *env)
 }
 
 static void write_bootloader(CPUMIPSState *env, uint8_t *base,
- int64_t kernel_addr)
+ uint64_t kernel_addr)
 {
 uint32_t *p;
 
@@ -294,7 +294,7 @@ static void mips_fuloong2e_init(MachineState *machine)
 MemoryRegion *bios = g_new(MemoryRegion, 1);
 long bios_size;
 uint8_t *spd_data;
-int64_t kernel_entry;
+uint64_t kernel_entry;
 PCIDevice *pci_dev;
 PCIBus *pci_bus;
 ISABus *isa_bus;
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 366f4fdfcd..7db009a3e9 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -616,8 +616,8 @@ static void network_init(PCIBus *pci_bus)
 }
 }
 
-static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
-  int64_t kernel_entry)
+static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
+  uint64_t kernel_entry)
 {
 uint16_t *p;
 
@@ -840,8 +840,8 @@ static void write_bootloader_nanomips(uint8_t *base, 
int64_t run_addr,
  *   a2 - 32-bit address of the environment variables table
  *   a3 - RAM size in bytes
  */
-static void write_bootloader(uint8_t *base, int64_t run_addr,
- int64_t kernel_entry)
+static void write_bootloader(uint8_t *base, uint64_t run_addr,
+ uint64_t kernel_entry)
 {
 uint32_t *p;
 
@@ -1003,7 +1003,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t 
*prom_buf, int index,
 const char *string, ...)
 {
 va_list ap;
-int32_t table_addr;
+uint32_t table_addr;
 
 if (index >= ENVP_NB_ENTRIES) {
 return;
@@ -1014,7 +1014,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t 
*prom_buf, int index,
 return;
 }
 
-table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
+table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
 prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
 
 va_start(ap, string);
@@ -1023,9 +1023,9 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t 
*prom_buf, int index,
 }
 
 /* Kernel */
-static int64_t load_kernel(void)
+static uint64_t load_kernel(void)
 {
-int64_t kernel_entry, kernel_high, initrd_size;
+uint64_t kernel_entry, kernel_high, initrd_size;
 long kernel_size;
 ram_addr_t initrd_offset;
 int big_endian;
@@ -1042,8 +1042,8 @@ static int64_t load_kernel(void)
 
 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
cpu_mips_kseg0_to_phys, NULL,
-   (uint64_t *)_entry, NULL,
-   (uint64_t *)_high, NULL, big_endian, EM_MIPS,
+   _entry, NULL,
+   _high, NULL, big_endian, EM_MIPS,
1, 0);
 if (kernel_size < 0) {
 error_report("could not load kernel '%s': %s",
@@ -1234,7 +1234,7 @@ void mips_malta_init(MachineState *machine)
 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
 const size_t smbus_eeprom_size = 8 * 256;
 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
-int64_t kernel_entry, bootloader_run_addr;
+uint64_t kernel_entry, bootloader_run_addr;
 PCIBus *pci_bus;
 ISABus *isa_bus;
 qemu_irq cbus_irq, i8259_irq;
-- 
2.29.2

[PATCH v2 0/8] MIPS Bootloader helper

[Jiaxun Yang]

v2:
A big reconstruction. rewrite helpers with CPU feature and sepreate
changesets.

Jiaxun Yang (8):
  hw/mips: Make bootloader addresses unsgined
  hw/mips/malta: Use address translation helper to calculate
bootloader_run_addr
  hw/mips: Use address translation helper to handle ENVP_ADDR
  hw/mips: Add a bootloader helper
  hw/mips: Use bl_gen_kernel_jump to generate bootloaders
  target/mips/addr: Add translation helpers for KSEG1
  hw/mips/malta: Use bootloader helper to set BAR resgiters
  hw/mips/boston: Use bootloader helper to set GCRs

 hw/mips/bootloader.c | 157 
 hw/mips/boston.c |  62 +++--
 hw/mips/fuloong2e.c  |  48 +++---
 hw/mips/malta.c  | 171 ---
 hw/mips/meson.build  |   2 +-
 include/hw/mips/bootloader.h |  48 ++
 target/mips/addr.c   |  10 ++
 target/mips/cpu.h|   2 +
 8 files changed, 306 insertions(+), 194 deletions(-)
 create mode 100644 hw/mips/bootloader.c
 create mode 100644 include/hw/mips/bootloader.h

-- 
2.29.2

[Bug 1818937] Re: Crash with HV_ERROR on macOS host

[Tianyun Zhang]

Same here on macOS 11.0.1 when specifying accel=hvf. Crash report is
attached.

$ qemu-system-x86_64 -machine accel=hvf -smp 2 -m 2G -hda current.qcow -boot d 
-cdrom ubuntu-18.04.5-desktop-amd64.iso  
qemu-system-x86_64: Error: HV_ERROR
[1]2912 abort  qemu-system-x86_64 -machine accel=hvf -smp 2 -m 2G -hda  
-boot d -cdrom

$ qemu-system-x86_64 --version
QEMU emulator version 5.1.0
Copyright (c) 2003-2020 Fabrice Bellard and the QEMU Project developers

$ sysctl -a | grep machdep.cpu.brand_string
machdep.cpu.brand_string: Intel(R) Core(TM) i7-1068NG7 CPU @ 2.30GH

** Attachment added: "qemu-system-x86_64_2020-12-15-142030.crash"
   
https://bugs.launchpad.net/qemu/+bug/1818937/+attachment/5443711/+files/qemu-system-x86_64_2020-12-15-142030.crash

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1818937

Title:
  Crash with HV_ERROR on macOS host

Status in QEMU:
  Fix Released

Bug description:
  On macOS host running Windows 10 guest, qemu crashed with error
  message: Error: HV_ERROR.

  Host: macOS Mojave 10.14.3 (18D109) Late 2014 Mac mini presumably Core i5 
4278U.
  QEMU: git commit a3e3b0a7bd5de211a62cdf2d6c12b96d3c403560
  QEMU parameter: qemu-system-x86_64 -m 3000 -drive 
file=disk.img,if=virtio,discard=unmap -accel hvf -soundhw hda -smp 3

  thread list
  Process 56054 stopped
thread #1: tid = 0x2ffec8, 0x7fff48d0805a vImage`vLookupTable_Planar16 
+ 970, queue = 'com.apple.main-thread'
thread #2: tid = 0x2ffecc, 0x7fff79d6d7de 
libsystem_kernel.dylib`__psynch_cvwait + 10
thread #3: tid = 0x2ffecd, 0x7fff79d715aa 
libsystem_kernel.dylib`__select + 10
thread #4: tid = 0x2ffece, 0x7fff79d71d9a 
libsystem_kernel.dylib`__sigwait + 10
  * thread #6: tid = 0x2ffed0, 0x7fff79d7023e 
libsystem_kernel.dylib`__pthread_kill + 10, stop reason = signal SIGABRT
thread #7: tid = 0x2ffed1, 0x7fff79d6d7de 
libsystem_kernel.dylib`__psynch_cvwait + 10
thread #8: tid = 0x2ffed2, 0x7fff79d6d7de 
libsystem_kernel.dylib`__psynch_cvwait + 10
thread #11: tid = 0x2fff34, 0x7fff79d6a17a 
libsystem_kernel.dylib`mach_msg_trap + 10, name = 'com.apple.NSEventThread'
thread #30: tid = 0x300c04, 0x7fff79e233f8 
libsystem_pthread.dylib`start_wqthread
thread #31: tid = 0x300c16, 0x7fff79e233f8 
libsystem_pthread.dylib`start_wqthread
thread #32: tid = 0x300c17, 0x
thread #33: tid = 0x300c93, 0x7fff79d6d7de 
libsystem_kernel.dylib`__psynch_cvwait + 10

  
  Crashed thread:

  * thread #6, stop reason = signal SIGABRT
* frame #0: 0x7fff79d7023e libsystem_kernel.dylib`__pthread_kill + 10
  frame #1: 0x7fff79e26c1c libsystem_pthread.dylib`pthread_kill + 285
  frame #2: 0x7fff79cd91c9 libsystem_c.dylib`abort + 127
  frame #3: 0x00010baa476d 
qemu-system-x86_64`assert_hvf_ok(ret=) at hvf.c:106 [opt]
  frame #4: 0x00010baa4c8f 
qemu-system-x86_64`hvf_vcpu_exec(cpu=0x7f8e5283de00) at hvf.c:681 [opt]
  frame #5: 0x00010b988423 
qemu-system-x86_64`qemu_hvf_cpu_thread_fn(arg=0x7f8e5283de00) at 
cpus.c:1636 [opt]
  frame #6: 0x00010bd9dfce 
qemu-system-x86_64`qemu_thread_start(args=) at 
qemu-thread-posix.c:502 [opt]
  frame #7: 0x7fff79e24305 libsystem_pthread.dylib`_pthread_body + 126
  frame #8: 0x7fff79e2726f libsystem_pthread.dylib`_pthread_start + 70
  frame #9: 0x7fff79e23415 libsystem_pthread.dylib`thread_start + 13

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Re: [PATCH v3] file-posix: detect the lock using the real file

[Feng Li]

Hi, Daniel
Thanks for your reply.
I have just ended my trip, sorry for my late response.
I will send out the v4.

Daniel P. Berrangé  于2020年12月11日周五 上午12:55写道：
>
> On Fri, Dec 11, 2020 at 12:38:19AM +0800, Li Feng wrote:
> > This patch addresses this issue:
> > When accessing a volume on an NFS filesystem without supporting the file 
> > lock,
> > tools, like qemu-img, will complain "Failed to lock byte 100".
> >
> > Add a new function 'qemu_has_file_lock' to detect if the filesystem 
> > supports locks
> > or not.
> > And when the drive is auto mode, use the 'qemu_has_file_lock' to set the 
> > toggle.
> >
> > Signed-off-by: Li Feng 
> > ---
> > v3: don't call the qemu_has_ofd_lock, use a new function instead.
> > v2: remove the refactoring.
> > ---
> >  block/file-posix.c   | 30 +-
> >  include/qemu/osdep.h |  1 +
> >  util/osdep.c | 29 +
> >  3 files changed, 47 insertions(+), 13 deletions(-)
> >
> > diff --git a/block/file-posix.c b/block/file-posix.c
> > index 806764f7e3..48f9a32de2 100644
> > --- a/block/file-posix.c
> > +++ b/block/file-posix.c
> > @@ -606,7 +606,7 @@ static int raw_open_common(BlockDriverState *bs, QDict 
> > *options,
> >  s->use_lock = false;
> >  break;
> >  case ON_OFF_AUTO_AUTO:
> > -s->use_lock = qemu_has_ofd_lock();
> > +s->use_lock = qemu_has_file_lock(filename);
>
> This is not good - it causes us to always use locks by default, where
> as previously we only used them if OFD was available. It neds to test
> both here, except opening + closing filename to test for fnctl support
> risks releasing any locks QEMU already holds on filename if OFD is not
> supported.
Yes, check the qemu_has_ofd_lock and qemu_has_file_lock both, and
set the use_lock to false when the os supports the OFD lock, but the
filesystem doesn't support.

>
> >  break;
> >  default:
> >  abort();
> > @@ -2388,6 +2388,7 @@ raw_co_create(BlockdevCreateOptions *options, Error 
> > **errp)
> >  int fd;
> >  uint64_t perm, shared;
> >  int result = 0;
> > +bool use_lock;
> >
> >  /* Validate options and set default values */
> >  assert(options->driver == BLOCKDEV_DRIVER_FILE);
> > @@ -2428,19 +2429,22 @@ raw_co_create(BlockdevCreateOptions *options, Error 
> > **errp)
> >  perm = BLK_PERM_WRITE | BLK_PERM_RESIZE;
> >  shared = BLK_PERM_ALL & ~BLK_PERM_RESIZE;
> >
> > -/* Step one: Take locks */
> > -result = raw_apply_lock_bytes(NULL, fd, perm, ~shared, false, errp);
> > -if (result < 0) {
> > -goto out_close;
> > -}
> > +use_lock = qemu_has_file_lock(file_opts->filename);
>
> This cause QEMU to open and close filename. If another thread
> already had filename open, and OFD is not support, we've just
> lock the locks we held. We need to use 'fd' which is already
> open.
Acked.

>
> > +if (use_lock) {
> > +/* Step one: Take locks */
> > +result = raw_apply_lock_bytes(NULL, fd, perm, ~shared, false, 
> > errp);
> > +if (result < 0) {
> > +goto out_close;
> > +}
> >
> > -/* Step two: Check that nobody else has taken conflicting locks */
> > -result = raw_check_lock_bytes(fd, perm, shared, errp);
> > -if (result < 0) {
> > -error_append_hint(errp,
> > -  "Is another process using the image [%s]?\n",
> > -  file_opts->filename);
> > -goto out_unlock;
> > +/* Step two: Check that nobody else has taken conflicting locks */
> > +result = raw_check_lock_bytes(fd, perm, shared, errp);
> > +if (result < 0) {
> > +error_append_hint(errp,
> > +  "Is another process using the image [%s]?\n",
> > +  file_opts->filename);
> > +goto out_unlock;
> > +}
> >  }
> >
> >  /* Clear the file by truncating it to 0 */
>
>
> > +bool qemu_has_file_lock(const char *filename)
>
> IMO thisshould just accept a pre-opened 'int fd'
Acked.

>
> > +{
> > +#ifdef F_OFD_SETLK
> > +int cmd = F_OFD_GETLK;
> > +#else
> > +int cmd = F_GETLK;
> > +#endif
> > +int fd;
> > +int ret;
> > +struct flock fl = {
> > +.l_whence = SEEK_SET,
> > +.l_start  = 0,
> > +.l_len= 0,
> > +.l_type   = F_WRLCK,
> > +};
> > +
> > +fd = open(filename, O_RDWR);
> > +if (fd < 0) {
> > +fprintf(stderr,
> > +"Failed to open %s for OFD lock probing: %s\n",
> > +filename,
> > +strerror(errno));
> > +return false;
> > +}
> > +ret = fcntl(fd, cmd, );
> > +close(fd);
> > +return ret == 0;
> > +}
> > +
> >  bool qemu_has_ofd_lock(void)
> >  {
> >  qemu_probe_lock_ops();
>
> Regards,
> Daniel
> --
> |: https://berrange.com  -o-

Re: [PATCH V17 4/6] hw/mips: Add Loongson-3 boot parameter helpers

[Huacai Chen]

Hi, Philippe,

On Mon, Dec 14, 2020 at 9:49 PM Philippe Mathieu-Daudé  wrote:
>
> On 12/14/20 3:37 AM, Huacai Chen wrote:
> > Hi, Philippe,
> >
> > On Mon, Dec 14, 2020 at 7:09 AM Philippe Mathieu-Daudé  
> > wrote:
> >>
> >> On 12/13/20 11:17 PM, Philippe Mathieu-Daudé wrote:
> >>> On 12/11/20 12:32 PM, Philippe Mathieu-Daudé wrote:
>  On 12/11/20 3:46 AM, Huacai Chen wrote:
> > Hi, Rechard and Peter,
> >
> > On Wed, Dec 2, 2020 at 5:32 PM Philippe Mathieu-Daudé  
> > wrote:
> >>
> >> On 12/2/20 2:14 AM, Huacai Chen wrote:
> >>> Hi, Phillippe,
> >>>
> >>> On Tue, Nov 24, 2020 at 6:25 AM Philippe Mathieu-Daudé 
> >>>  wrote:
> 
>  On 11/6/20 5:21 AM, Huacai Chen wrote:
> > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI 
> > (a
> > UEFI-like interface for BIOS-Kernel boot parameters) helpers first.
> >
> > Reviewed-by: Philippe Mathieu-Daudé 
> > Signed-off-by: Huacai Chen 
> > Co-developed-by: Jiaxun Yang 
> > Signed-off-by: Jiaxun Yang 
> > ---
> >  hw/mips/loongson3_bootp.c | 165 +++
> >  hw/mips/loongson3_bootp.h | 241 
> > ++
> >  hw/mips/meson.build   |   1 +
> >  3 files changed, 407 insertions(+)
> >  create mode 100644 hw/mips/loongson3_bootp.c
> >  create mode 100644 hw/mips/loongson3_bootp.h
> >
> > diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
> > new file mode 100644
> > index 000..3a16081
> > --- /dev/null
> > +++ b/hw/mips/loongson3_bootp.c
> > @@ -0,0 +1,165 @@
> > +/*
> > + * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) 
> > helpers
> > + *
> > + * Copyright (c) 2018-2020 Huacai Chen (che...@lemote.com)
> > + * Copyright (c) 2018-2020 Jiaxun Yang 
> > + *
> > + * This program is free software: you can redistribute it and/or 
> > modify
> > + * it under the terms of the GNU General Public License as 
> > published by
> > + * the Free Software Foundation, either version 2 of the License, 
> > or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public 
> > License
> > + * along with this program. If not, see 
> > .
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/units.h"
> > +#include "qemu/cutils.h"
> > +#include "cpu.h"
> > +#include "hw/boards.h"
> > +#include "hw/mips/loongson3_bootp.h"
> > +
> > +#define LOONGSON3_CORE_PER_NODE 4
> > +
> > +static struct efi_cpuinfo_loongson *init_cpu_info(void *g_cpuinfo, 
> > uint64_t cpu_freq)
> > +{
> > +struct efi_cpuinfo_loongson *c = g_cpuinfo;
> > +
> > +stl_le_p(>cputype, Loongson_3A);
> > +stl_le_p(>processor_id, MIPS_CPU(first_cpu)->env.CP0_PRid);
> 
>  Build failing with Clang:
> 
>  FAILED: libqemu-mips64el-softmmu.fa.p/hw_mips_loongson3_bootp.c.o
>  hw/mips/loongson3_bootp.c:35:15: error: taking address of packed 
>  member
>  'processor_id' of class or structure 'efi_cpuinfo_loongson' may 
>  result
>  in an unaligned pointer value [-Werror,-Waddress-of-packed-member]
>  stl_le_p(>processor_id, MIPS_CPU(first_cpu)->env.CP0_PRid);
>    ^~~
>  1 error generated.
> >>> We cannot reproduce it on X86/MIPS with clang...
> >>
> >> You can reproduce running the Clang job on Gitlab-CI:
> >>
> >> https://wiki.qemu.org/Testing/CI/GitLabCI
> >>
> >>> And I found that
> >>> stl_le_p() will be __builtin_memcpy(), I don't think memcpy() will
> >>> cause unaligned access. So, any suggestions?
> 
>  My understanding is the compiler is complaining for the argument
>  passed to the caller, with no knowledge of the callee implementation.
> 
>  Which makes me wonder if these functions are really inlined...
> 
>  Do we need to use QEMU_ALWAYS_INLINE for these LDST helpers?
> >>>
> >>> No, this doesn't work neither.
> >>
> >> Well, this works:
> >>
> >> -- >8 --
> >> @@ -32,7 +32,7 @@ static struct efi_cpuinfo_loongson *init_cpu_info(void
> >> *g_cpuinfo, uint64_t cpu_
> >>  struct 

Re: [PATCH v5 3/4] hmp: Use QMP query-netdev in hmp_info_network

[Jason Wang]

- Original Message -
> Hi!
> 
> 07.12.2020, 08:52, "Jason Wang" :
> > On 2020/11/9 上午7:59, Alexey Kirillov wrote:
> >>  +#ifdef CONFIG_SLIRP
> >>  + case NET_BACKEND_USER: {
> >>  + size_t len = strchr(ni->u.user.net, '/') - ni->u.user.net;
> >>  + char *net = g_strndup(ni->u.user.net, len);
> >>  +
> >>  + info_str = g_strdup_printf("net=%s,restrict=%s",
> >>  + net,
> >>  + ni->u.user.q_restrict ? "on" : "off");
> >>  + g_free(net);
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_SLIRP */
> >>  + case NET_BACKEND_TAP: {
> >>  +#ifndef _WIN32
> >>  + if (ni->u.tap.has_fds) {
> >>  + char **fds = g_strsplit(ni->u.tap.fds, ":", -1);
> >>  +
> >>  + info_str = g_strdup_printf("fd=%s", fds[nc->queue_index]);
> >>  + g_strfreev(fds);
> >>  + } else if (ni->u.tap.has_helper) {
> >>  + info_str = g_strdup_printf("helper=%s", ni->u.tap.helper);
> >>  + } else {
> >>  + info_str = g_strdup_printf("ifname=%s,script=%s,downscript=%s",
> >>  + ni->u.tap.ifname,
> >>  + nc->queue_index == 0 ? ni->u.tap.script : "no",
> >>  + nc->queue_index == 0 ? ni->u.tap.downscript : "no");
> >>  + }
> >>  +#else
> >>  + info_str = g_strdup_printf("tap: ifname=%s", ni->u.tap.ifname);
> >>  +#endif /* _WIN32 */
> >>  + break;
> >>  + }
> >>  +#ifdef CONFIG_L2TPV3
> >>  + case NET_BACKEND_L2TPV3: {
> >>  + info_str = g_strdup_printf("l2tpv3: connected");
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_L2TPV3 */
> >>  + case NET_BACKEND_SOCKET: {
> >>  + if (ni->u.socket.has_listen) {
> >>  + if (ni->u.socket.has_fd) {
> >>  + info_str = g_strdup_printf("socket: connection from %s",
> >>  + ni->u.socket.listen);
> >>  + } else {
> >>  + info_str = g_strdup_printf("socket: wait from %s",
> >>  + ni->u.socket.listen);
> >>  + }
> >>  + } else if (ni->u.socket.has_connect && ni->u.socket.has_fd) {
> >>  + info_str = g_strdup_printf("socket: connect to %s",
> >>  + ni->u.socket.connect);
> >>  + } else if (ni->u.socket.has_mcast && ni->u.socket.has_fd) {
> >>  + info_str = g_strdup_printf("socket: mcast=%s",
> >>  + ni->u.socket.mcast);
> >>  + } else if (ni->u.socket.has_udp && ni->u.socket.has_fd) {
> >>  + info_str = g_strdup_printf("socket: udp=%s", ni->u.socket.udp);
> >>  + } else {
> >>  + g_assert(ni->u.socket.has_fd);
> >>  + int so_type = -1;
> >>  + int optlen = sizeof(so_type);
> >>  + int fd = atoi(ni->u.socket.fd);
> >>  +
> >>  + getsockopt(fd, SOL_SOCKET, SO_TYPE, (char *)_type,
> >>  + (socklen_t *));
> >>  + if (so_type == SOCK_STREAM) {
> >>  + info_str = g_strdup_printf("socket: fd=%s",
> >>  + ni->u.socket.fd);
> >>  + } else {
> >>  + if (ni->u.socket.has_mcast) {
> >>  + /*
> >>  + * This branch is unreachable, according to how it is in
> >>  + * net/socket.c at this moment
> >>  + */
> >>  + info_str = g_strdup_printf("socket: fd=%s "
> >>  + "(cloned mcast=%s)",
> >>  + ni->u.socket.fd,
> >>  + ni->u.socket.mcast);
> >>  + } else {
> >>  + SocketAddress *sa = socket_local_address(fd, NULL);
> >>  +
> >>  + info_str = g_strdup_printf("socket: fd=%s %s",
> >>  + ni->u.socket.fd,
> >>  + SocketAddressType_str(sa->type));
> >>  + qapi_free_SocketAddress(sa);
> >>  + }
> >>  + }
> >>  + }
> >>  + break;
> >>  + }
> >>  +#ifdef CONFIG_VDE
> >>  + case NET_BACKEND_VDE: {
> >>  + info_str = g_strdup_printf("sock=%s,fd=%d",
> >>  + ni->u.vde.sock,
> >>  + net_vde_get_fd(nc));
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_VDE */
> >>  +#ifdef CONFIG_NET_BRIDGE
> >>  + case NET_BACKEND_BRIDGE: {
> >>  + info_str = g_strdup_printf("helper=%s,br=%s",
> >>  + ni->u.bridge.helper,
> >>  + ni->u.bridge.br);
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_NET_BRIDGE */
> >>  +#ifdef CONFIG_NETMAP
> >>  + case NET_BACKEND_NETMAP: {
> >>  + info_str = g_strdup_printf("netmap: ifname=%s",
> >>  + ni->u.netmap.ifname);
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_NETMAP */
> >>  +#ifdef CONFIG_VHOST_NET_USER
> >>  + case NET_BACKEND_VHOST_USER: {
> >>  + info_str = g_strdup_printf("vhost-user%d to %s",
> >>  + nc->queue_index,
> >>  + ni->u.vhost_user.chardev);
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_VHOST_NET_USER */
> >>  +#ifdef CONFIG_VHOST_NET_VDPA
> >>  + case NET_BACKEND_VHOST_VDPA: {
> >>  + info_str = g_strdup("vhost-vdpa");
> >>  + break;
> >>  + }
> >>  +#endif /* CONFIG_VHOST_NET_VDPA */
> >
> > This will introduce burdens for new netdevs or new attributes since
> > people can easily forget to add the routine here.
> >
> > I think at least we need introduce callbacks for this.
> 
> Thanks for pointing. I can't remember why exactly I chose to not do it.
> So it's definitely better to split this chunk to several callbacks.
> I'll do it in the next version of series.
> 
> > One more stupid question, instead of generating the string via hard
> > codes, is there any method (dict?) to iterate all the key/values
> > automatically?
> >
> > Thanks
> 
> Oh yes, that the point.
> Now there are no common format for info_str.
> This patch is aimed to keep old HMP command mostly untouched.
> But if we can 

RE: [PATCH 1/7] allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks

[ganqixin]

> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Tuesday, December 15, 2020 12:20 AM
> To: ganqixin 
> Cc: qemu-arm ; QEMU Developers
> ; Chenqun (kuhn)
> ; Zhanghailiang
> ; Euler Robot
> ; Beniamino Galvani 
> Subject: Re: [PATCH 1/7] allwinner-a10-pit: Use ptimer_free() in the
> finalize function to avoid memleaks
> 
> On Mon, 14 Dec 2020 at 16:02, Peter Maydell 
> wrote:
> >
> > On Fri, 27 Nov 2020 at 07:19, Gan Qixin  wrote:
> > >
> > > When running device-introspect-test, a memory leak occurred in the
> > > a10_pit_init function, so use ptimer_free() in the finalize function to
> avoid it.
> > >
> > > ASAN shows memory leak stack:
> > >
> > > Indirect leak of 288 byte(s) in 6 object(s) allocated from:
> > > #0 0xab97e1f0 in __interceptor_calloc
> (/lib64/libasan.so.5+0xee1f0)
> > > #1 0xab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
> > > #2 0xaaabf555db84 in timer_new_full
> /qemu/include/qemu/timer.h:523
> > > #3 0xaaabf555db84 in timer_new
> /qemu/include/qemu/timer.h:544
> > > #4 0xaaabf555db84 in timer_new_ns
> /qemu/include/qemu/timer.h:562
> > > #5 0xaaabf555db84 in ptimer_init /qemu/hw/core/ptimer.c:433
> > > #6 0xaaabf57415e8 in a10_pit_init
> /qemu/hw/timer/allwinner-a10-pit.c:278
> > > #7 0xaaabf6339f6c in object_initialize_with_type
> /qemu/qom/object.c:515
> > > #8 0xaaabf633ca04 in object_initialize_child_with_propsv
> /qemu/qom/object.c:564
> > > #9 0xaaabf633cc08 in object_initialize_child_with_props
> /qemu/qom/object.c:547
> > > #10 0xaaabf5b94680 in aw_a10_init
> /qemu/hw/arm/allwinner-a10.c:49
> > > #11 0xaaabf6339f6c in object_initialize_with_type
> /qemu/qom/object.c:515
> > > #12 0xaaabf633a1e0 in object_new_with_type
> > > /qemu/qom/object.c:729
> > >
> > > Reported-by: Euler Robot 
> > > Signed-off-by: Gan Qixin 
> > > ---
> > > Cc: Beniamino Galvani 
> > > ---
> > >  hw/timer/allwinner-a10-pit.c | 21 -
> > >  1 file changed, 16 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/hw/timer/allwinner-a10-pit.c
> > > b/hw/timer/allwinner-a10-pit.c index f84fc0ea25..be211983b0
> 100644
> > > --- a/hw/timer/allwinner-a10-pit.c
> > > +++ b/hw/timer/allwinner-a10-pit.c
> > > @@ -279,6 +279,16 @@ static void a10_pit_init(Object *obj)
> > >  }
> > >  }
> > >
> > > +static void a10_pit_finalize(Object *obj) {
> > > +AwA10PITState *s = AW_A10_PIT(obj);
> > > +int i;
> > > +
> > > +for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
> > > +ptimer_free(s->timer[i]);
> > > +}
> > > +}
> > > +
> > >  static void a10_pit_class_init(ObjectClass *klass, void *data)  {
> > >  DeviceClass *dc = DEVICE_CLASS(klass); @@ -290,11 +300,12
> @@
> > > static void a10_pit_class_init(ObjectClass *klass, void *data)  }
> > >
> > >  static const TypeInfo a10_pit_info = {
> > > -.name = TYPE_AW_A10_PIT,
> > > -.parent = TYPE_SYS_BUS_DEVICE,
> > > -.instance_size = sizeof(AwA10PITState),
> > > -.instance_init = a10_pit_init,
> > > -.class_init = a10_pit_class_init,
> > > +.name  = TYPE_AW_A10_PIT,
> > > +.parent= TYPE_SYS_BUS_DEVICE,
> > > +.instance_size = sizeof(AwA10PITState),
> > > +.instance_init = a10_pit_init,
> > > +.instance_finalize = a10_pit_finalize,
> > > +.class_init= a10_pit_class_init,
> > >  };
> >
> > Please don't make unrelated whitespace changes like this in a patch.
> > We don't line up the assignments in this sort of struct -- this is
> > deliberate, so that if a new line is added whose field name happens to
> > be longer than those used already, the patch does not have to touch
> > all the lines in the struct to maintain the formatting.
> > Instead you get a readable diff where only the new line changes, not
> > all the others.
> 
> Hmm. Having said that I see that the other 6 devices touched by this series
> did use the line-up-the-assignments style.
> Anyway, the style this device was using is the right one.

Thanks for your reply, I will resend this patch. By the way, do we need to keep
the other 6 devices in the same style as this device?

Gan Qixin

Re: [PATCH v4 17/43] tcg: Add --accel tcg,split-wx property

[Joelle van Dyne]

Should qemu-options.hx be updated?

-j

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> Plumb the value through to alloc_code_gen_buffer.  This is not
> supported by any os or tcg backend, so for now enabling it will
> result in an error.
>
> Signed-off-by: Richard Henderson 
> ---
>  include/sysemu/tcg.h  |  3 ++-
>  tcg/aarch64/tcg-target.h  |  1 +
>  tcg/arm/tcg-target.h  |  1 +
>  tcg/i386/tcg-target.h |  1 +
>  tcg/mips/tcg-target.h |  1 +
>  tcg/ppc/tcg-target.h  |  1 +
>  tcg/riscv/tcg-target.h|  1 +
>  tcg/s390/tcg-target.h |  1 +
>  tcg/sparc/tcg-target.h|  1 +
>  tcg/tci/tcg-target.h  |  1 +
>  accel/tcg/tcg-all.c   | 26 +-
>  accel/tcg/translate-all.c | 35 +++
>  bsd-user/main.c   |  2 +-
>  linux-user/main.c |  2 +-
>  14 files changed, 65 insertions(+), 12 deletions(-)
>
> diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h
> index d9d3ca8559..00349fb18a 100644
> --- a/include/sysemu/tcg.h
> +++ b/include/sysemu/tcg.h
> @@ -8,7 +8,8 @@
>  #ifndef SYSEMU_TCG_H
>  #define SYSEMU_TCG_H
>
> -void tcg_exec_init(unsigned long tb_size);
> +void tcg_exec_init(unsigned long tb_size, int splitwx);
> +
>  #ifdef CONFIG_TCG
>  extern bool tcg_allowed;
>  #define tcg_enabled() (tcg_allowed)
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 6ba248f447..92aefc32d3 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -154,5 +154,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
> uintptr_t, uintptr_t);
>  #define TCG_TARGET_NEED_LDST_LABELS
>  #endif
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif /* AARCH64_TCG_TARGET_H */
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 6ca4537ca6..7e04755428 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -141,5 +141,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
> uintptr_t, uintptr_t);
>  #define TCG_TARGET_NEED_LDST_LABELS
>  #endif
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 0dcaed7fe6..04eefbfb90 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -231,5 +231,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
> tc_ptr, uintptr_t jmp_rx,
>  #define TCG_TARGET_NEED_LDST_LABELS
>  #endif
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index d23baf7cda..d6dff897bf 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -200,6 +200,7 @@ extern bool use_mips32r2_instructions;
>
>  #define TCG_TARGET_DEFAULT_MO (0)
>  #define TCG_TARGET_HAS_MEMORY_BSWAP 1
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
>
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index c41d10142b..8fc2672bf0 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -184,5 +184,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
> uintptr_t, uintptr_t);
>  #define TCG_TARGET_NEED_LDST_LABELS
>  #endif
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 3d0745c70c..785fe37f9b 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -170,5 +170,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
> uintptr_t, uintptr_t);
>  #define TCG_TARGET_NEED_POOL_LABELS
>
>  #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 3750952598..fed3329e51 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -158,5 +158,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
> tc_ptr, uintptr_t jmp_rx,
>  #define TCG_TARGET_NEED_LDST_LABELS
>  #endif
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index 9c15c91d39..21e7e2f56f 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -171,5 +171,6 @@ extern bool use_vis3_instructions;
>  void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
>
>  #define TCG_TARGET_NEED_POOL_LABELS
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  #endif
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index fcec2e70db..768153fd02 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -197,6 +197,7 @@ void tci_disas(uint8_t opc);
>  #define TCG_TARGET_DEFAULT_MO  (0)
>
>  #define TCG_TARGET_HAS_MEMORY_BSWAP 1
> +#define TCG_TARGET_SUPPORT_MIRROR   0
>
>  static inline void 

[PATCH v1 1/1] riscv/opentitan: Update the OpenTitan memory layout

[Alistair Francis]

OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.

Signed-off-by: Alistair Francis 
---
 include/hw/riscv/opentitan.h | 23 +++---
 hw/riscv/opentitan.c | 81 +---
 2 files changed, 74 insertions(+), 30 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 5ff0c0f85e..a5ea3a5e4e 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -55,19 +55,30 @@ enum {
 IBEX_DEV_UART,
 IBEX_DEV_GPIO,
 IBEX_DEV_SPI,
-IBEX_DEV_FLASH_CTRL,
+IBEX_DEV_I2C,
+IBEX_DEV_PATTGEN,
 IBEX_DEV_RV_TIMER,
-IBEX_DEV_AES,
-IBEX_DEV_HMAC,
-IBEX_DEV_PLIC,
+IBEX_DEV_SENSOR_CTRL,
+IBEX_DEV_OTP_CTRL,
 IBEX_DEV_PWRMGR,
 IBEX_DEV_RSTMGR,
 IBEX_DEV_CLKMGR,
 IBEX_DEV_PINMUX,
+IBEX_DEV_PADCTRL,
+IBEX_DEV_USBDEV,
+IBEX_DEV_FLASH_CTRL,
+IBEX_DEV_PLIC,
+IBEX_DEV_AES,
+IBEX_DEV_HMAC,
+IBEX_DEV_KMAC,
+IBEX_DEV_KEYMGR,
+IBEX_DEV_CSRNG,
+IBEX_DEV_ENTROPY,
+IBEX_DEV_EDNO,
+IBEX_DEV_EDN1,
 IBEX_DEV_ALERT_HANDLER,
 IBEX_DEV_NMI_GEN,
-IBEX_DEV_USBDEV,
-IBEX_DEV_PADCTRL,
+IBEX_DEV_OTBN,
 };
 
 enum {
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index cc758b78b8..af3456932f 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -35,22 +35,33 @@ static const struct MemmapEntry {
 [IBEX_DEV_ROM] ={  0x8000, 16 * KiB },
 [IBEX_DEV_RAM] ={  0x1000,  0x1 },
 [IBEX_DEV_FLASH] =  {  0x2000,  0x8 },
-[IBEX_DEV_UART] =   {  0x4000,  0x1 },
-[IBEX_DEV_GPIO] =   {  0x4001,  0x1 },
-[IBEX_DEV_SPI] ={  0x4002,  0x1 },
-[IBEX_DEV_FLASH_CTRL] = {  0x4003,  0x1 },
-[IBEX_DEV_PINMUX] = {  0x4007,  0x1 },
-[IBEX_DEV_RV_TIMER] =   {  0x4008,  0x1 },
-[IBEX_DEV_PLIC] =   {  0x4009,  0x1 },
-[IBEX_DEV_PWRMGR] = {  0x400A,  0x1 },
-[IBEX_DEV_RSTMGR] = {  0x400B,  0x1 },
-[IBEX_DEV_CLKMGR] = {  0x400C,  0x1 },
-[IBEX_DEV_AES] ={  0x4011,  0x1 },
-[IBEX_DEV_HMAC] =   {  0x4012,  0x1 },
-[IBEX_DEV_ALERT_HANDLER] =  {  0x4013,  0x1 },
-[IBEX_DEV_NMI_GEN] ={  0x4014,  0x1 },
-[IBEX_DEV_USBDEV] = {  0x4015,  0x1 },
-[IBEX_DEV_PADCTRL] ={  0x4016,  0x1 }
+[IBEX_DEV_UART] =   {  0x4000,  0x1000  },
+[IBEX_DEV_GPIO] =   {  0x4004,  0x1000  },
+[IBEX_DEV_SPI] ={  0x4005,  0x1000  },
+[IBEX_DEV_I2C] ={  0x4008,  0x1000  },
+[IBEX_DEV_PATTGEN] ={  0x400e,  0x1000  },
+[IBEX_DEV_RV_TIMER] =   {  0x4010,  0x1000  },
+[IBEX_DEV_SENSOR_CTRL] ={  0x4011,  0x1000  },
+[IBEX_DEV_OTP_CTRL] =   {  0x4013,  0x4000  },
+[IBEX_DEV_PWRMGR] = {  0x4040,  0x1000  },
+[IBEX_DEV_RSTMGR] = {  0x4041,  0x1000  },
+[IBEX_DEV_CLKMGR] = {  0x4042,  0x1000  },
+[IBEX_DEV_PINMUX] = {  0x4046,  0x1000  },
+[IBEX_DEV_PADCTRL] ={  0x4047,  0x1000  },
+[IBEX_DEV_USBDEV] = {  0x4050,  0x1000  },
+[IBEX_DEV_FLASH_CTRL] = {  0x4100,  0x1000  },
+[IBEX_DEV_PLIC] =   {  0x4101,  0x1000  },
+[IBEX_DEV_AES] ={  0x4110,  0x1000  },
+[IBEX_DEV_HMAC] =   {  0x4111,  0x1000  },
+[IBEX_DEV_KMAC] =   {  0x4112,  0x1000  },
+[IBEX_DEV_KEYMGR] = {  0x4113,  0x1000  },
+[IBEX_DEV_CSRNG] =  {  0x4115,  0x1000  },
+[IBEX_DEV_ENTROPY] ={  0x4116,  0x1000  },
+[IBEX_DEV_EDNO] =   {  0x4117,  0x1000  },
+[IBEX_DEV_EDN1] =   {  0x4118,  0x1000  },
+[IBEX_DEV_ALERT_HANDLER] =  {  0x411b,  0x1000  },
+[IBEX_DEV_NMI_GEN] ={  0x411c,  0x1000  },
+[IBEX_DEV_OTBN] =   {  0x411d,  0x1 },
 };
 
 static void opentitan_board_init(MachineState *machine)
@@ -156,30 +167,52 @@ static void lowrisc_ibex_soc_realize(DeviceState 
*dev_soc, Error **errp)
 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
 create_unimplemented_device("riscv.lowrisc.ibex.spi",
 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
-create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
-memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
+create_unimplemented_device("riscv.lowrisc.ibex.i2c",
+memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
+create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
+memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
  

Re: [PATCH v4 06/43] tcg: Move tcg epilogue pointer out of TCGContext

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
>
> Signed-off-by: Richard Henderson 
> ---
>  include/tcg/tcg.h| 2 +-
>  accel/tcg/tcg-runtime.c  | 2 +-
>  tcg/tcg.c| 3 ++-
>  tcg/aarch64/tcg-target.c.inc | 4 ++--
>  tcg/arm/tcg-target.c.inc | 2 +-
>  tcg/i386/tcg-target.c.inc| 4 ++--
>  tcg/mips/tcg-target.c.inc| 2 +-
>  tcg/ppc/tcg-target.c.inc | 2 +-
>  tcg/riscv/tcg-target.c.inc   | 4 ++--
>  tcg/s390/tcg-target.c.inc| 4 ++--
>  tcg/sparc/tcg-target.c.inc   | 2 +-
>  11 files changed, 16 insertions(+), 15 deletions(-)

Reviewed-by: Joelle van Dyne 

Re: [PATCH v4 05/43] tcg: Move tcg prologue pointer out of TCGContext

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
>
> Use the correct function pointer type, and name the variable
> tcg_qemu_tb_exec, which means that we are able to remove the
> macro that does the casting.
>
> Replace HAVE_TCG_QEMU_TB_EXEC with CONFIG_TCG_INTERPRETER,
> as this is somewhat clearer in intent.
>
> Reviewed-by: Alex Bennée 
> Signed-off-by: Richard Henderson 
> ---
>  include/tcg/tcg.h | 9 -
>  tcg/tcg.c | 9 -
>  tcg/tci.c | 3 ++-
>  3 files changed, 14 insertions(+), 7 deletions(-)

Reviewed-by: Joelle van Dyne 

Re: [PATCH v4 04/43] util: Specialize flush_idcache_range for aarch64

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:03 AM Richard Henderson
 wrote:
>
> For darwin, the CTR_EL0 register is not accessible, but there
> are system routines that we can use.
>
> For other hosts, copy the single pointer implementation from
> libgcc and modify it to support the double pointer interface
> we require.  This halves the number of cache operations required
> when split-rwx is enabled.
>
> Cc: Joelle van Dyne 
> Signed-off-by: Richard Henderson 

Reviewed-by: Joelle van Dyne 

Re: [PATCH v4 03/43] util: Enhance flush_icache_range with separate data pointer

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> We are shortly going to have a split rw/rx jit buffer.  Depending
> on the host, we need to flush the dcache at the rw data pointer and
> flush the icache at the rx code pointer.
>
> For now, the two passed pointers are identical, so there is no
> effective change in behaviour.
>
> Reviewed-by: Alex Bennée 
> Signed-off-by: Richard Henderson 

Reviewed-by: Joelle van Dyne 

Re: [PATCH v4 02/43] util: Extract flush_icache_range to cacheflush.c

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> This has been a tcg-specific function, but is also in use
> by hardware accelerators via physmem.c.  This can cause
> link errors when tcg is disabled.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Joelle van Dyne 

Re: [raw] Guest stuck during live live-migration

[Wei Wang]

On 11/23/2020 05:36 PM, Quentin Grolleau wrote:

Hello,

In our company, we are hosting a large number of Vm, hosted behind 
Openstack (so libvirt/qemu).
A large majority of our Vms are runnign with local data only, stored 
on NVME, and most of them are RAW disks.


With Qemu 4.0(can be even with older version)we see strange 
live-migrationcomportement:

- some Vms live migrate at very high speed without issue (> 6 Gbps)
- some Vms are running correctly, but migrating at a strange low 
speed (3Gbps)
- some Vms are migrating at a very low speed (1Gbps, sometime 
less) and during the migration the guest is completely I/O stuck
When this issue happen the VM is completly block, iostat in the Vm 
show us a latency of 30 secs


First we thought it was related to an hardware issuewe check it, we 
comparing different hardware, but no issue where found there


So one of my colleague had the idea to limit with "tc" the bandwidth 
on the interface the migration was done, and it worked the VM didn't 
lose any ping nor being  I/O stuck
Important point : Once the Vm have been migrate (with the limitation ) 
one time, if we migrate it again right after, the migration will be 
done at full speed (8-9Gb/s) without freezing the Vm


It only happen on existing VM, we tried to replicate with a fresh 
instance with exactly the same spec and nothing was happening


We tried to replicate the workload inside the VM but there was no way 
to replicate the case. So it was not related to the workload nor to 
the server that hosts the Vm


So we thought about the disk of the instance : the raw file.

We also tried to strace -c the process during the live-migration and 
it was doing a lot of "lseek"


and we found this :
https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg00462.html


So i rebuilt Qemu with this patch and the live-migration went well, at 
high speedand with no VM freeze

( https://github.com/qemu/qemu/blob/master/block/file-posix.c#L2601)

Do you have a way to avoid the "lseek" mechanism as it consumes more 
resources to find the holes in the disk and don't let any for the VM ?



Server hosting the VM :
- Bi-Xeon hosts With NVME storage and 10 Go Network card
- Qemu 4.0 And Libvirt 5.4
- Kernel 4.18.0.25

Guest having the issue :
- raw image with Debian 8

Here the qemu img on the disk :
> qemu-img info disk
image: disk
file format: raw
virtual size: 400G (429496729600 bytes)
disk size: 400G



Could you share the migration options that you use and "info migrate" 
for both stuck and non-stuck cases?


Best,
Wei

Re: [PATCH v2 07/11] qapi/introspect.py: Unify return type of _make_tree()

[John Snow]

On 11/7/20 12:08 AM, Cleber Rosa wrote:

And this seems like another change.

- Cleber.


Fair enough.

Re: [PATCH v3 2/5] hw/timer: Refactor NPCM7XX Timer to use CLK clock

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> This patch makes NPCM7XX Timer to use a the timer clock generated by the
> CLK module instead of the magic number TIMER_REF_HZ.
>
> Reviewed-by: Havard Skinnemoen 
> Reviewed-by: Tyrone Ting 
> Signed-off-by: Hao Wu 
> ---
>  hw/arm/npcm7xx.c |  5 +
>  hw/timer/npcm7xx_timer.c | 23 +--
>  include/hw/misc/npcm7xx_clk.h|  6 --
>  include/hw/timer/npcm7xx_timer.h |  1 +
>  4 files changed, 19 insertions(+), 16 deletions(-)
>
> diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> index 47e2b6fc40..fabfb1697b 100644
> --- a/hw/arm/npcm7xx.c
> +++ b/hw/arm/npcm7xx.c
> @@ -22,6 +22,7 @@
>  #include "hw/char/serial.h"
>  #include "hw/loader.h"
>  #include "hw/misc/unimp.h"
> +#include "hw/qdev-clock.h"
>  #include "hw/qdev-properties.h"
>  #include "qapi/error.h"
>  #include "qemu/units.h"
> @@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error
> **errp)
>  int first_irq;
>  int j;
>
> +/* Connect the timer clock. */
> +qdev_connect_clock_in(DEVICE(>tim[i]), "clock",
> qdev_get_clock_out(
> +DEVICE(>clk), "timer-clock"));
> +
>  sysbus_realize(sbd, _abort);
>  sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
>
> diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
> index d24445bd6e..8147b53000 100644
> --- a/hw/timer/npcm7xx_timer.c
> +++ b/hw/timer/npcm7xx_timer.c
> @@ -17,8 +17,8 @@
>  #include "qemu/osdep.h"
>
>  #include "hw/irq.h"
> +#include "hw/qdev-clock.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/misc/npcm7xx_clk.h"
>  #include "hw/timer/npcm7xx_timer.h"
>  #include "migration/vmstate.h"
>  #include "qemu/bitops.h"
> @@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer
> *t, uint32_t count)
>  {
>  int64_t ns = count;
>
> -ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
> +ns *= clock_get_ns(t->ctrl->clock);
>  ns *= npcm7xx_tcsr_prescaler(t->tcsr);
>
>  return ns;
> @@ -141,7 +141,7 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer
> *t, int64_t ns)
>  {
>  int64_t count;
>
> -count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
> +count = ns / clock_get_ns(t->ctrl->clock);
>  count /= npcm7xx_tcsr_prescaler(t->tcsr);
>
>  return count;
> @@ -167,7 +167,7 @@ static void
> npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
>  int64_t cycles)
>  {
>  uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
> -int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
> +int64_t ns = clock_get_ns(t->ctrl->clock) * cycles;
>
>  /*
>   * The reset function always clears the current timer. The caller of
> the
> @@ -606,10 +606,11 @@ static void npcm7xx_timer_hold_reset(Object *obj)
>  qemu_irq_lower(s->watchdog_timer.irq);
>  }
>
> -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
> +static void npcm7xx_timer_init(Object *obj)
>  {
> -NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
> +NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
>  SysBusDevice *sbd = >parent;
> +DeviceState *dev = DEVICE(obj);
>  int i;
>  NPCM7xxWatchdogTimer *w;
>
> @@ -627,11 +628,12 @@ static void npcm7xx_timer_realize(DeviceState *dev,
> Error **errp)
>  npcm7xx_watchdog_timer_expired, w);
>  sysbus_init_irq(sbd, >irq);
>
> -memory_region_init_io(>iomem, OBJECT(s), _timer_ops, s,
> +memory_region_init_io(>iomem, obj, _timer_ops, s,
>TYPE_NPCM7XX_TIMER, 4 * KiB);
>  sysbus_init_mmio(sbd, >iomem);
>  qdev_init_gpio_out_named(dev, >reset_signal,
>  NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
> +s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
>  }
>
>  static const VMStateDescription vmstate_npcm7xx_base_timer = {
> @@ -675,10 +677,11 @@ static const VMStateDescription
> vmstate_npcm7xx_watchdog_timer = {
>
>  static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
>  .name = "npcm7xx-timer-ctrl",
> -.version_id = 1,
> -.minimum_version_id = 1,
> +.version_id = 2,
> +.minimum_version_id = 2,
>  .fields = (VMStateField[]) {
>  VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
> +VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
>  VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
>   NPCM7XX_TIMERS_PER_CTRL, 0,
> vmstate_npcm7xx_timer,
>   NPCM7xxTimer),
> @@ -697,7 +700,6 @@ static void npcm7xx_timer_class_init(ObjectClass
> *klass, void *data)
>  QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
>
>  dc->desc = "NPCM7xx Timer Controller";
> -dc->realize = npcm7xx_timer_realize;
>  dc->vmsd = _npcm7xx_timer_ctrl;
>  rc->phases.enter = npcm7xx_timer_enter_reset;
>  rc->phases.hold = npcm7xx_timer_hold_reset;
> @@ -708,6 +710,7 @@ static 

Re: [PATCH v2 00/15] RISC-V: Start to remove xlen preprocess

[Palmer Dabbelt]

On Tue, 08 Dec 2020 14:56:08 PST (-0800), Alistair Francis wrote:

The RISC-V QEMU port currently has lot of preprocessor directives that
check if we are targetting a 32-bit or 64-bit CPU. This means that the
64-bit RISC-V target can not run 32-bit CPUs. This is different to most
other QEMU architectures and doesn't allow us to mix xlens (such as when
running Hypervisors with different xlen guests).
This series is a step toward removing some of those to allow us to use
32-bit CPUs on 64-bit RISC-V targets.
v2:
 - Rebase on the latest RISC-V tree

Alistair Francis (15):
  hw/riscv: Expand the is 32-bit check to support more CPUs
  target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
  riscv: spike: Remove target macro conditionals
  riscv: virt: Remove target macro conditionals
  hw/riscv: boot: Remove compile time XLEN checks
  hw/riscv: virt: Remove compile time XLEN checks
  hw/riscv: spike: Remove compile time XLEN checks
  hw/riscv: sifive_u: Remove compile time XLEN checks
  target/riscv: fpu_helper: Match function defs in HELPER macros
  target/riscv: Add a riscv_cpu_is_32bit() helper function
  target/riscv: Specify the XLEN for CPUs
  target/riscv: cpu: Remove compile time XLEN checks
  target/riscv: cpu_helper: Remove compile time XLEN checks
  target/riscv: csr: Remove compile time XLEN checks
  target/riscv: cpu: Set XLEN independently from target

 include/hw/riscv/boot.h   |   8 +-
 include/hw/riscv/spike.h  |   6 --
 include/hw/riscv/virt.h   |   6 --
 target/riscv/cpu.h|   8 ++
 target/riscv/cpu_bits.h   |   4 +-
 hw/riscv/boot.c   |  69 +--
 hw/riscv/sifive_u.c   |  57 ++--
 hw/riscv/spike.c  |  50 ++-
 hw/riscv/virt.c   |  36 
 target/riscv/cpu.c|  84 --
 target/riscv/cpu_helper.c |  12 +--
 target/riscv/csr.c| 182 --
 target/riscv/fpu_helper.c |  16 ++--
 13 files changed, 302 insertions(+), 236 deletions(-)


Thanks, this is awesome!  That's always been one of the headaches floating
around the port that I was hoping to have some time to sort out :).  I just
gave it a quick look, but

Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

as it certainly seems better than before.

Re: [PATCH v3 3/5] hw/adc: Add an ADC module for NPCM7XX

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> The ADC is part of NPCM7XX Module. Its behavior is controled by the
> ADC_CON register. It converts one of the eight analog inputs into a
> digital input and stores it in the ADC_DATA register when enabled.
>
> Users can alter input value by using qom-set QMP command.
>
> Reviewed-by: Havard Skinnemoen 
> Reviewed-by: Tyrone Ting 
> Signed-off-by: Hao Wu 
> ---
>  docs/system/arm/nuvoton.rst|   2 +-
>  hw/adc/meson.build |   1 +
>  hw/adc/npcm7xx_adc.c   | 321 ++
>  hw/adc/trace-events|   5 +
>  hw/arm/npcm7xx.c   |  24 +-
>  include/hw/adc/npcm7xx_adc.h   |  72 ++
>  include/hw/arm/npcm7xx.h   |   2 +
>  meson.build|   1 +
>  tests/qtest/meson.build|   3 +-
>  tests/qtest/npcm7xx_adc-test.c | 400 +
>  10 files changed, 828 insertions(+), 3 deletions(-)
>  create mode 100644 hw/adc/npcm7xx_adc.c
>  create mode 100644 hw/adc/trace-events
>  create mode 100644 include/hw/adc/npcm7xx_adc.h
>  create mode 100644 tests/qtest/npcm7xx_adc-test.c
>
> diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
> index b00d405d52..35829f8d0b 100644
> --- a/docs/system/arm/nuvoton.rst
> +++ b/docs/system/arm/nuvoton.rst
> @@ -41,6 +41,7 @@ Supported devices
>   * Random Number Generator (RNG)
>   * USB host (USBH)
>   * GPIO controller
> + * Analog to Digital Converter (ADC)
>
>  Missing devices
>  ---
> @@ -58,7 +59,6 @@ Missing devices
>   * USB device (USBD)
>   * SMBus controller (SMBF)
>   * Peripheral SPI controller (PSPI)
> - * Analog to Digital Converter (ADC)
>   * SD/MMC host
>   * PECI interface
>   * Pulse Width Modulation (PWM)
> diff --git a/hw/adc/meson.build b/hw/adc/meson.build
> index 0d62ae96ae..6ddee23813 100644
> --- a/hw/adc/meson.build
> +++ b/hw/adc/meson.build
> @@ -1 +1,2 @@
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true:
> files('stm32f2xx_adc.c'))
> +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
> diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
> new file mode 100644
> index 00..c2c4819d3f
> --- /dev/null
> +++ b/hw/adc/npcm7xx_adc.c
> @@ -0,0 +1,321 @@
> +/*
> + * Nuvoton NPCM7xx ADC Module
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "hw/adc/npcm7xx_adc.h"
> +#include "hw/qdev-clock.h"
> +#include "hw/qdev-properties.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "qemu/timer.h"
> +#include "qemu/units.h"
> +#include "trace.h"
> +
> +/* 32-bit register indices. */
> +enum NPCM7xxADCRegisters {
> +NPCM7XX_ADC_CON,
> +NPCM7XX_ADC_DATA,
> +NPCM7XX_ADC_REGS_END,
> +};
> +
> +/* Register field definitions. */
> +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
> +#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
> +#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
> +#define NPCM7XX_ADC_CON_INT BIT(18)
> +#define NPCM7XX_ADC_CON_EN  BIT(17)
> +#define NPCM7XX_ADC_CON_RST BIT(16)
> +#define NPCM7XX_ADC_CON_CONVBIT(14)
> +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
> +
> +#define NPCM7XX_ADC_MAX_RESULT  1023
> +#define NPCM7XX_ADC_DEFAULT_IREF200
> +#define NPCM7XX_ADC_CONV_CYCLES 20
> +#define NPCM7XX_ADC_RESET_CYCLES10
> +#define NPCM7XX_ADC_R0_INPUT50
> +#define NPCM7XX_ADC_R1_INPUT150
> +
> +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
> +{
> +timer_del(>conv_timer);
> +timer_del(>reset_timer);
> +s->con = 0x000c0001;
> +s->data = 0x;
> +}
> +
> +static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
> +{
> +uint32_t result;
> +
> +result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
> +if (result > NPCM7XX_ADC_MAX_RESULT) {
> +result = NPCM7XX_ADC_MAX_RESULT;
> +}
> +
> +return result;
> +}
> +
> +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
> +{
> +return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
> +}
> +
> +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
> +uint32_t cycles, uint32_t prescaler)
> +{
> +int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> +int64_t freq = clock_get_hz(clk);
> +int64_t ns;
> +
> +ns = (NANOSECONDS_PER_SECOND * cycles * prescaler / freq);
> +ns += now;
> +timer_mod(timer, ns);
> +}
> +
> +static void 

Re: [PATCH v3 5/5] hw/misc: Add QTest for NPCM7XX PWM Module

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> We add a qtest for the PWM in the previous patch. It proves it works as
> expected.
>
> Reviewed-by: Havard Skinnemoen 
> Reviewed-by: Tyrone Ting 
> Signed-off-by: Hao Wu 
> ---
>  tests/qtest/meson.build|   1 +
>  tests/qtest/npcm7xx_pwm-test.c | 490 +
>  2 files changed, 491 insertions(+)
>  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 955710d1c5..0b5467f084 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -136,6 +136,7 @@ qtests_sparc64 = \
>  qtests_npcm7xx = \
>['npcm7xx_adc-test',
> 'npcm7xx_gpio-test',
> +   'npcm7xx_pwm-test',
> 'npcm7xx_rng-test',
> 'npcm7xx_timer-test',
> 'npcm7xx_watchdog_timer-test']
> diff --git a/tests/qtest/npcm7xx_pwm-test.c
> b/tests/qtest/npcm7xx_pwm-test.c
> new file mode 100644
> index 00..33fbdf5f54
> --- /dev/null
> +++ b/tests/qtest/npcm7xx_pwm-test.c
> @@ -0,0 +1,490 @@
> +/*
> + * QTests for Nuvoton NPCM7xx PWM Modules.
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but
> WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "libqos/libqtest.h"
> +#include "qapi/qmp/qdict.h"
> +#include "qapi/qmp/qnum.h"
> +
> +#define REF_HZ  2500
> +
> +/* Register field definitions. */
> +#define CH_EN   BIT(0)
> +#define CH_INV  BIT(2)
> +#define CH_MOD  BIT(3)
> +
> +/* Registers shared between all PWMs in a module */
> +#define PPR 0x00
> +#define CSR 0x04
> +#define PCR 0x08
> +#define PIER0x3c
> +#define PIIR0x40
> +
> +/* CLK module related */
> +#define CLK_BA  0xf0801000
> +#define CLKSEL  0x04
> +#define CLKDIV1 0x08
> +#define CLKDIV2 0x2c
> +#define PLLCON0 0x0c
> +#define PLLCON1 0x10
> +#define PLL_INDV(rv)extract32((rv), 0, 6)
> +#define PLL_FBDV(rv)extract32((rv), 16, 12)
> +#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
> +#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
> +#define APB3CKDIV(rv)   extract32((rv), 28, 2)
> +#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
> +#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
> +#define CPUCKSEL(rv)extract32((rv), 0, 2)
> +
> +#define MAX_DUTY100
> +
> +typedef struct PWMModule {
> +int irq;
> +uint64_t base_addr;
> +} PWMModule;
> +
> +typedef struct PWM {
> +uint32_t cnr_offset;
> +uint32_t cmr_offset;
> +uint32_t pdr_offset;
> +uint32_t pwdr_offset;
> +} PWM;
> +
> +typedef struct TestData {
> +const PWMModule *module;
> +const PWM *pwm;
> +} TestData;
> +
> +static const PWMModule pwm_module_list[] = {
> +{
> +.irq= 93,
> +.base_addr  = 0xf0103000
> +},
> +{
> +.irq= 94,
> +.base_addr  = 0xf0104000
> +}
> +};
> +
> +static const PWM pwm_list[] = {
> +{
> +.cnr_offset = 0x0c,
> +.cmr_offset = 0x10,
> +.pdr_offset = 0x14,
> +.pwdr_offset= 0x44,
> +},
> +{
> +.cnr_offset = 0x18,
> +.cmr_offset = 0x1c,
> +.pdr_offset = 0x20,
> +.pwdr_offset= 0x48,
> +},
> +{
> +.cnr_offset = 0x24,
> +.cmr_offset = 0x28,
> +.pdr_offset = 0x2c,
> +.pwdr_offset= 0x4c,
> +},
> +{
> +.cnr_offset = 0x30,
> +.cmr_offset = 0x34,
> +.pdr_offset = 0x38,
> +.pwdr_offset= 0x50,
> +},
> +};
> +
> +static const int ppr_base[] = { 0, 0, 8, 8 };
> +static const int csr_base[] = { 0, 4, 8, 12 };
> +static const int pcr_base[] = { 0, 8, 12, 16 };
> +
> +static const uint32_t ppr_list[] = {
> +0,
> +1,
> +10,
> +100,
> +255, /* Max possible value. */
> +};
> +
> +static const uint32_t csr_list[] = {
> +0,
> +1,
> +2,
> +3,
> +4, /* Max possible value. */
> +};
> +
> +static const uint32_t cnr_list[] = {
> +0,
> +1,
> +50,
> +100,
> +150,
> +200,
> +1000,
> +1,
> +65535, /* Max possible value. */
> +};
> +
> +static const uint32_t cmr_list[] = {
> +0,
> +1,
> +10,
> +50,
> +100,
> +150,
> +200,
> +1000,
> +1,
> +65535, /* Max possible value. */
> +};
> +
> +/* Returns the index of the PWM module. */
> 

Re: [PATCH v3 0/5] Additional NPCM7xx devices

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> This patch series include a few more NPCM7XX devices including
>
> - Analog Digital Converter (ADC)
> - Pulse Width Modulation (PWM)
>
> We also modified the CLK module to generate clock values using qdev_clock.
> These clocks are used to determine various clocks in NPCM7XX devices.
>
> Thank you for your review.
>
> Changes since v2:
> - Split PWM test into a separate patch in the patch set
> - Add trace events for PWM's update_freq/update_duty
> - Add trace events for ioread/iowrite in ADC and PWM
> - Use timer_get_ns in hw/timer/npcm7xx_timer.c
> - Update commit message in ADC/PWM to mention qom-get/set method for usage
> - Fix typos
>
> Changes since v1:
> - We removed the IPMI and KCS related code from this patch set.
>
> Hao Wu (5):
>   hw/misc: Add clock converter in NPCM7XX CLK module
>   hw/timer: Refactor NPCM7XX Timer to use CLK clock
>   hw/adc: Add an ADC module for NPCM7XX
>   hw/misc: Add a PWM module for NPCM7XX
>   hw/misc: Add QTest for NPCM7XX PWM Module
>
>  docs/system/arm/nuvoton.rst  |   4 +-
>  hw/adc/meson.build   |   1 +
>  hw/adc/npcm7xx_adc.c | 321 +
>  hw/adc/trace-events  |   5 +
>  hw/arm/npcm7xx.c |  55 ++-
>  hw/misc/meson.build  |   1 +
>  hw/misc/npcm7xx_clk.c| 795 ++-
>  hw/misc/npcm7xx_pwm.c| 559 ++
>  hw/misc/trace-events |   6 +
>  hw/timer/npcm7xx_timer.c |  23 +-
>  include/hw/adc/npcm7xx_adc.h |  72 +++
>  include/hw/arm/npcm7xx.h |   4 +
>  include/hw/misc/npcm7xx_clk.h| 146 +-
>  include/hw/misc/npcm7xx_pwm.h| 106 +
>  include/hw/timer/npcm7xx_timer.h |   1 +
>  meson.build  |   1 +
>  tests/qtest/meson.build  |   4 +-
>  tests/qtest/npcm7xx_adc-test.c   | 400 
>  tests/qtest/npcm7xx_pwm-test.c   | 490 +++
>  19 files changed, 2964 insertions(+), 30 deletions(-)
>  create mode 100644 hw/adc/npcm7xx_adc.c
>  create mode 100644 hw/adc/trace-events
>  create mode 100644 hw/misc/npcm7xx_pwm.c
>  create mode 100644 include/hw/adc/npcm7xx_adc.h
>  create mode 100644 include/hw/misc/npcm7xx_pwm.h
>  create mode 100644 tests/qtest/npcm7xx_adc-test.c
>  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
>
> --
> 2.29.2.684.gfbc64c5ab5-goog
>
>

Re: [PATCH v3 4/5] hw/misc: Add a PWM module for NPCM7XX

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
> identical PWM modules. Each module contains 4 PWM entries. Each PWM has
> two outputs: frequency and duty_cycle. Both are computed using inputs
> from software side.
>
> This module does not model detail pulse signals since it is expensive.
> It also does not model interrupts and watchdogs that are dependant on
> the detail models. The interfaces for these are left in the module so
> that anyone in need for these functionalities can implement on their
> own.
>
> The user can read the duty cycle and frequency using qom-get command.
>
> Reviewed-by: Havard Skinnemoen 
> Reviewed-by: Tyrone Ting 
> Signed-off-by: Hao Wu 
> ---
>  docs/system/arm/nuvoton.rst   |   2 +-
>  hw/arm/npcm7xx.c  |  26 +-
>  hw/misc/meson.build   |   1 +
>  hw/misc/npcm7xx_pwm.c | 559 ++
>  hw/misc/trace-events  |   6 +
>  include/hw/arm/npcm7xx.h  |   2 +
>  include/hw/misc/npcm7xx_pwm.h | 106 +++
>  7 files changed, 699 insertions(+), 3 deletions(-)
>  create mode 100644 hw/misc/npcm7xx_pwm.c
>  create mode 100644 include/hw/misc/npcm7xx_pwm.h
>
> diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
> index 35829f8d0b..a1786342e2 100644
> --- a/docs/system/arm/nuvoton.rst
> +++ b/docs/system/arm/nuvoton.rst
> @@ -42,6 +42,7 @@ Supported devices
>   * USB host (USBH)
>   * GPIO controller
>   * Analog to Digital Converter (ADC)
> + * Pulse Width Modulation (PWM)
>
>  Missing devices
>  ---
> @@ -61,7 +62,6 @@ Missing devices
>   * Peripheral SPI controller (PSPI)
>   * SD/MMC host
>   * PECI interface
> - * Pulse Width Modulation (PWM)
>   * Tachometer
>   * PCI and PCIe root complex and bridges
>   * VDM and MCTP support
> diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> index b22a8c966d..72040d4079 100644
> --- a/hw/arm/npcm7xx.c
> +++ b/hw/arm/npcm7xx.c
> @@ -102,6 +102,8 @@ enum NPCM7xxInterrupt {
>  NPCM7XX_WDG2_IRQ,   /* Timer Module 2 Watchdog */
>  NPCM7XX_EHCI_IRQ= 61,
>  NPCM7XX_OHCI_IRQ= 62,
> +NPCM7XX_PWM0_IRQ= 93,   /* PWM module 0 */
> +NPCM7XX_PWM1_IRQ,   /* PWM module 1 */
>  NPCM7XX_GPIO0_IRQ   = 116,
>  NPCM7XX_GPIO1_IRQ,
>  NPCM7XX_GPIO2_IRQ,
> @@ -144,6 +146,12 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
>  0xb800, /* CS3 */
>  };
>
> +/* Register base address for each PWM Module */
> +static const hwaddr npcm7xx_pwm_addr[] = {
> +0xf0103000,
> +0xf0104000,
> +};
> +
>  static const struct {
>  hwaddr regs_addr;
>  uint32_t unconnected_pins;
> @@ -353,6 +361,10 @@ static void npcm7xx_init(Object *obj)
>  object_initialize_child(obj, npcm7xx_fiu[i].name, >fiu[i],
>  TYPE_NPCM7XX_FIU);
>  }
> +
> +for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
> +object_initialize_child(obj, "pwm[*]", >pwm[i],
> TYPE_NPCM7XX_PWM);
> +}
>  }
>
>  static void npcm7xx_realize(DeviceState *dev, Error **errp)
> @@ -513,6 +525,18 @@ static void npcm7xx_realize(DeviceState *dev, Error
> **errp)
>  sysbus_connect_irq(SYS_BUS_DEVICE(>ohci), 0,
> npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
>
> +/* PWM Modules. Cannot fail. */
> +QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
> +for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
> +SysBusDevice *sbd = SYS_BUS_DEVICE(>pwm[i]);
> +
> +qdev_connect_clock_in(DEVICE(>pwm[i]), "clock",
> qdev_get_clock_out(
> +DEVICE(>clk), "apb3-clock"));
> +sysbus_realize(sbd, _abort);
> +sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
> +sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
> +}
> +
>  /*
>   * Flash Interface Unit (FIU). Can fail if incorrect number of chip
> selects
>   * specified, but this is a programming error.
> @@ -580,8 +604,6 @@ static void npcm7xx_realize(DeviceState *dev, Error
> **errp)
>  create_unimplemented_device("npcm7xx.peci", 0xf010,   4 *
> KiB);
>  create_unimplemented_device("npcm7xx.siox[1]",  0xf0101000,   4 *
> KiB);
>  create_unimplemented_device("npcm7xx.siox[2]",  0xf0102000,   4 *
> KiB);
> -create_unimplemented_device("npcm7xx.pwm[0]",   0xf0103000,   4 *
> KiB);
> -create_unimplemented_device("npcm7xx.pwm[1]",   0xf0104000,   4 *
> KiB);
>  create_unimplemented_device("npcm7xx.mft[0]",   0xf018,   4 *
> KiB);
>  create_unimplemented_device("npcm7xx.mft[1]",   0xf0181000,   4 *
> KiB);
>  create_unimplemented_device("npcm7xx.mft[2]",   0xf0182000,   4 *
> KiB);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index ce15ffceb9..607cd38a21 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -64,6 +64,7 @@ 

[PATCH v3 3/5] hw/adc: Add an ADC module for NPCM7XX

[Hao Wu via]

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen 
Reviewed-by: Tyrone Ting 
Signed-off-by: Hao Wu 
---
 docs/system/arm/nuvoton.rst|   2 +-
 hw/adc/meson.build |   1 +
 hw/adc/npcm7xx_adc.c   | 321 ++
 hw/adc/trace-events|   5 +
 hw/arm/npcm7xx.c   |  24 +-
 include/hw/adc/npcm7xx_adc.h   |  72 ++
 include/hw/arm/npcm7xx.h   |   2 +
 meson.build|   1 +
 tests/qtest/meson.build|   3 +-
 tests/qtest/npcm7xx_adc-test.c | 400 +
 10 files changed, 828 insertions(+), 3 deletions(-)
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/adc/trace-events
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 tests/qtest/npcm7xx_adc-test.c

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index b00d405d52..35829f8d0b 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -41,6 +41,7 @@ Supported devices
  * Random Number Generator (RNG)
  * USB host (USBH)
  * GPIO controller
+ * Analog to Digital Converter (ADC)
 
 Missing devices
 ---
@@ -58,7 +59,6 @@ Missing devices
  * USB device (USBD)
  * SMBus controller (SMBF)
  * Peripheral SPI controller (PSPI)
- * Analog to Digital Converter (ADC)
  * SD/MMC host
  * PECI interface
  * Pulse Width Modulation (PWM)
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
index 0d62ae96ae..6ddee23813 100644
--- a/hw/adc/meson.build
+++ b/hw/adc/meson.build
@@ -1 +1,2 @@
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
new file mode 100644
index 00..c2c4819d3f
--- /dev/null
+++ b/hw/adc/npcm7xx_adc.c
@@ -0,0 +1,321 @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+/* 32-bit register indices. */
+enum NPCM7xxADCRegisters {
+NPCM7XX_ADC_CON,
+NPCM7XX_ADC_DATA,
+NPCM7XX_ADC_REGS_END,
+};
+
+/* Register field definitions. */
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
+#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
+#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
+#define NPCM7XX_ADC_CON_INT BIT(18)
+#define NPCM7XX_ADC_CON_EN  BIT(17)
+#define NPCM7XX_ADC_CON_RST BIT(16)
+#define NPCM7XX_ADC_CON_CONVBIT(14)
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
+
+#define NPCM7XX_ADC_MAX_RESULT  1023
+#define NPCM7XX_ADC_DEFAULT_IREF200
+#define NPCM7XX_ADC_CONV_CYCLES 20
+#define NPCM7XX_ADC_RESET_CYCLES10
+#define NPCM7XX_ADC_R0_INPUT50
+#define NPCM7XX_ADC_R1_INPUT150
+
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
+{
+timer_del(>conv_timer);
+timer_del(>reset_timer);
+s->con = 0x000c0001;
+s->data = 0x;
+}
+
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
+{
+uint32_t result;
+
+result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
+if (result > NPCM7XX_ADC_MAX_RESULT) {
+result = NPCM7XX_ADC_MAX_RESULT;
+}
+
+return result;
+}
+
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
+{
+return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
+}
+
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
+uint32_t cycles, uint32_t prescaler)
+{
+int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+int64_t freq = clock_get_hz(clk);
+int64_t ns;
+
+ns = (NANOSECONDS_PER_SECOND * cycles * prescaler / freq);
+ns += now;
+timer_mod(timer, ns);
+}
+
+static void npcm7xx_adc_start_reset(NPCM7xxADCState *s)
+{
+uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+npcm7xx_adc_start_timer(s->clock, >reset_timer, 
NPCM7XX_ADC_RESET_CYCLES,
+prescaler);
+}
+
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
+{
+uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+

Re: [PATCH v3 1/5] hw/misc: Add clock converter in NPCM7XX CLK module

[Hao Wu via]

On Mon, Dec 14, 2020 at 4:13 PM Hao Wu  wrote:

> This patch allows NPCM7XX CLK module to compute clocks that are used by
> other NPCM7XX modules.
>
> Add a new struct NPCM7xxClockConverterState which represents a
> single converter.  Each clock converter in CLK module represents one
> converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
> takes one or more input clocks and converts them into one output clock.
> They form a clock hierarchy in the CLK module and are responsible for
> outputing clocks for various other modules in an NPCM7XX SoC.
>
> Each converter has a function pointer called "convert" which represents
> the unique logic for that converter.
>
> The clock contains two initialization information: ConverterInitInfo and
> ConverterConnectionInfo. They represent the vertices and edges in the
> clock diagram respectively.
>
> Reviewed-by: Havard Skinnemoen 
> Reviewed-by: Tyrone Ting 
> Signed-off-by: Hao Wu 
> ---
>  hw/misc/npcm7xx_clk.c | 795 +-
>  include/hw/misc/npcm7xx_clk.h | 140 +-
>  2 files changed, 927 insertions(+), 8 deletions(-)
>
> diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
> index 6732437fe2..48bc9bdda5 100644
> --- a/hw/misc/npcm7xx_clk.c
> +++ b/hw/misc/npcm7xx_clk.c
> @@ -18,6 +18,7 @@
>
>  #include "hw/misc/npcm7xx_clk.h"
>  #include "hw/timer/npcm7xx_timer.h"
> +#include "hw/qdev-clock.h"
>  #include "migration/vmstate.h"
>  #include "qemu/error-report.h"
>  #include "qemu/log.h"
> @@ -27,9 +28,22 @@
>  #include "trace.h"
>  #include "sysemu/watchdog.h"
>
> +/*
> + * The reference clock hz, and the SECCNT and CNTR25M registers in this
> module,
> + * is always 25 MHz.
> + */
> +#define NPCM7XX_CLOCK_REF_HZ(2500)
> +
> +/* Register Field Definitions */
> +#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
> +
>  #define PLLCON_LOKI BIT(31)
>  #define PLLCON_LOKS BIT(30)
>  #define PLLCON_PWDENBIT(12)
> +#define PLLCON_FBDV(con) extract32((con), 16, 12)
> +#define PLLCON_OTDV2(con) extract32((con), 13, 3)
> +#define PLLCON_OTDV1(con) extract32((con), 8, 3)
> +#define PLLCON_INDV(con) extract32((con), 0, 6)
>
>  enum NPCM7xxCLKRegisters {
>  NPCM7XX_CLK_CLKEN1,
> @@ -89,12 +103,609 @@ static const uint32_t
> cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
>  [NPCM7XX_CLK_AHBCKFI]   = 0x00c8,
>  };
>
> -/* Register Field Definitions */
> -#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
> -
>  /* The number of watchdogs that can trigger a reset. */
>  #define NPCM7XX_NR_WATCHDOGS(3)
>
> +/* Clock converter functions */
> +
> +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
> +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
> +(obj), TYPE_NPCM7XX_CLOCK_PLL)
> +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
> +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
> +(obj), TYPE_NPCM7XX_CLOCK_SEL)
> +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
> +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState,
> \
> +(obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
> +
> +static void npcm7xx_clk_update_pll(void *opaque)
> +{
> +NPCM7xxClockPLLState *s = opaque;
> +uint32_t con = s->clk->regs[s->reg];
> +uint64_t freq;
> +
> +/* The PLL is grounded if it is not locked yet. */
> +if (con & PLLCON_LOKI) {
> +freq = clock_get_hz(s->clock_in);
> +freq *= PLLCON_FBDV(con);
> +freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
> +} else {
> +freq = 0;
> +}
> +
> +clock_update_hz(s->clock_out, freq);
> +}
> +
> +static void npcm7xx_clk_update_sel(void *opaque)
> +{
> +NPCM7xxClockSELState *s = opaque;
> +uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL],
> s->offset,
> +s->len);
> +
> +if (index >= s->input_size) {
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "%s: SEL index: %u out of range\n",
> +  __func__, index);
> +index = 0;
> +}
> +clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
> +}
> +
> +static void npcm7xx_clk_update_divider(void *opaque)
> +{
> +NPCM7xxClockDividerState *s = opaque;
> +uint32_t freq;
> +
> +freq = s->divide(s);
> +clock_update_hz(s->clock_out, freq);
> +}
> +
> +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
> +{
> +return clock_get_hz(s->clock_in) / s->divisor;
> +}
> +
> +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
> +{
> +return clock_get_hz(s->clock_in) /
> +(extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
> +}
> +
> +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
> +{
> +return divide_by_reg_divisor(s) / 2;
> +}
> +
> +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
> +{
> +return clock_get_hz(s->clock_in) >>
> +

[PATCH v3 4/5] hw/misc: Add a PWM module for NPCM7XX

[Hao Wu via]

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

Reviewed-by: Havard Skinnemoen 
Reviewed-by: Tyrone Ting 
Signed-off-by: Hao Wu 
---
 docs/system/arm/nuvoton.rst   |   2 +-
 hw/arm/npcm7xx.c  |  26 +-
 hw/misc/meson.build   |   1 +
 hw/misc/npcm7xx_pwm.c | 559 ++
 hw/misc/trace-events  |   6 +
 include/hw/arm/npcm7xx.h  |   2 +
 include/hw/misc/npcm7xx_pwm.h | 106 +++
 7 files changed, 699 insertions(+), 3 deletions(-)
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 include/hw/misc/npcm7xx_pwm.h

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index 35829f8d0b..a1786342e2 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -42,6 +42,7 @@ Supported devices
  * USB host (USBH)
  * GPIO controller
  * Analog to Digital Converter (ADC)
+ * Pulse Width Modulation (PWM)
 
 Missing devices
 ---
@@ -61,7 +62,6 @@ Missing devices
  * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
- * Pulse Width Modulation (PWM)
  * Tachometer
  * PCI and PCIe root complex and bridges
  * VDM and MCTP support
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index b22a8c966d..72040d4079 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -102,6 +102,8 @@ enum NPCM7xxInterrupt {
 NPCM7XX_WDG2_IRQ,   /* Timer Module 2 Watchdog */
 NPCM7XX_EHCI_IRQ= 61,
 NPCM7XX_OHCI_IRQ= 62,
+NPCM7XX_PWM0_IRQ= 93,   /* PWM module 0 */
+NPCM7XX_PWM1_IRQ,   /* PWM module 1 */
 NPCM7XX_GPIO0_IRQ   = 116,
 NPCM7XX_GPIO1_IRQ,
 NPCM7XX_GPIO2_IRQ,
@@ -144,6 +146,12 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 0xb800, /* CS3 */
 };
 
+/* Register base address for each PWM Module */
+static const hwaddr npcm7xx_pwm_addr[] = {
+0xf0103000,
+0xf0104000,
+};
+
 static const struct {
 hwaddr regs_addr;
 uint32_t unconnected_pins;
@@ -353,6 +361,10 @@ static void npcm7xx_init(Object *obj)
 object_initialize_child(obj, npcm7xx_fiu[i].name, >fiu[i],
 TYPE_NPCM7XX_FIU);
 }
+
+for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+object_initialize_child(obj, "pwm[*]", >pwm[i], TYPE_NPCM7XX_PWM);
+}
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -513,6 +525,18 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
 sysbus_connect_irq(SYS_BUS_DEVICE(>ohci), 0,
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 
+/* PWM Modules. Cannot fail. */
+QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+SysBusDevice *sbd = SYS_BUS_DEVICE(>pwm[i]);
+
+qdev_connect_clock_in(DEVICE(>pwm[i]), "clock", qdev_get_clock_out(
+DEVICE(>clk), "apb3-clock"));
+sysbus_realize(sbd, _abort);
+sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+}
+
 /*
  * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
  * specified, but this is a programming error.
@@ -580,8 +604,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
 create_unimplemented_device("npcm7xx.peci", 0xf010,   4 * KiB);
 create_unimplemented_device("npcm7xx.siox[1]",  0xf0101000,   4 * KiB);
 create_unimplemented_device("npcm7xx.siox[2]",  0xf0102000,   4 * KiB);
-create_unimplemented_device("npcm7xx.pwm[0]",   0xf0103000,   4 * KiB);
-create_unimplemented_device("npcm7xx.pwm[1]",   0xf0104000,   4 * KiB);
 create_unimplemented_device("npcm7xx.mft[0]",   0xf018,   4 * KiB);
 create_unimplemented_device("npcm7xx.mft[1]",   0xf0181000,   4 * KiB);
 create_unimplemented_device("npcm7xx.mft[2]",   0xf0182000,   4 * KiB);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index ce15ffceb9..607cd38a21 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -64,6 +64,7 @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: 
files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
   'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
+  'npcm7xx_pwm.c',
   'npcm7xx_rng.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/npcm7xx_pwm.c 

[PATCH v3 2/5] hw/timer: Refactor NPCM7XX Timer to use CLK clock

[Hao Wu via]

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen 
Reviewed-by: Tyrone Ting 
Signed-off-by: Hao Wu 
---
 hw/arm/npcm7xx.c |  5 +
 hw/timer/npcm7xx_timer.c | 23 +--
 include/hw/misc/npcm7xx_clk.h|  6 --
 include/hw/timer/npcm7xx_timer.h |  1 +
 4 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 47e2b6fc40..fabfb1697b 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -22,6 +22,7 @@
 #include "hw/char/serial.h"
 #include "hw/loader.h"
 #include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu/units.h"
@@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
 int first_irq;
 int j;
 
+/* Connect the timer clock. */
+qdev_connect_clock_in(DEVICE(>tim[i]), "clock", qdev_get_clock_out(
+DEVICE(>clk), "timer-clock"));
+
 sysbus_realize(sbd, _abort);
 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index d24445bd6e..8147b53000 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -17,8 +17,8 @@
 #include "qemu/osdep.h"
 
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "migration/vmstate.h"
 #include "qemu/bitops.h"
@@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, 
uint32_t count)
 {
 int64_t ns = count;
 
-ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
+ns *= clock_get_ns(t->ctrl->clock);
 ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 
 return ns;
@@ -141,7 +141,7 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, 
int64_t ns)
 {
 int64_t count;
 
-count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
+count = ns / clock_get_ns(t->ctrl->clock);
 count /= npcm7xx_tcsr_prescaler(t->tcsr);
 
 return count;
@@ -167,7 +167,7 @@ static void 
npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
 int64_t cycles)
 {
 uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+int64_t ns = clock_get_ns(t->ctrl->clock) * cycles;
 
 /*
  * The reset function always clears the current timer. The caller of the
@@ -606,10 +606,11 @@ static void npcm7xx_timer_hold_reset(Object *obj)
 qemu_irq_lower(s->watchdog_timer.irq);
 }
 
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
 {
-NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
+NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
 SysBusDevice *sbd = >parent;
+DeviceState *dev = DEVICE(obj);
 int i;
 NPCM7xxWatchdogTimer *w;
 
@@ -627,11 +628,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, Error 
**errp)
 npcm7xx_watchdog_timer_expired, w);
 sysbus_init_irq(sbd, >irq);
 
-memory_region_init_io(>iomem, OBJECT(s), _timer_ops, s,
+memory_region_init_io(>iomem, obj, _timer_ops, s,
   TYPE_NPCM7XX_TIMER, 4 * KiB);
 sysbus_init_mmio(sbd, >iomem);
 qdev_init_gpio_out_named(dev, >reset_signal,
 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
+s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
 }
 
 static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -675,10 +677,11 @@ static const VMStateDescription 
vmstate_npcm7xx_watchdog_timer = {
 
 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
 .name = "npcm7xx-timer-ctrl",
-.version_id = 1,
-.minimum_version_id = 1,
+.version_id = 2,
+.minimum_version_id = 2,
 .fields = (VMStateField[]) {
 VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
 VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
  NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
  NPCM7xxTimer),
@@ -697,7 +700,6 @@ static void npcm7xx_timer_class_init(ObjectClass *klass, 
void *data)
 QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 
 dc->desc = "NPCM7xx Timer Controller";
-dc->realize = npcm7xx_timer_realize;
 dc->vmsd = _npcm7xx_timer_ctrl;
 rc->phases.enter = npcm7xx_timer_enter_reset;
 rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -708,6 +710,7 @@ static const TypeInfo npcm7xx_timer_info = {
 .parent = TYPE_SYS_BUS_DEVICE,
 .instance_size  = sizeof(NPCM7xxTimerCtrlState),
 .class_init = npcm7xx_timer_class_init,
+.instance_init  = npcm7xx_timer_init,
 };
 
 static void 

[PATCH v3 5/5] hw/misc: Add QTest for NPCM7XX PWM Module

[Hao Wu via]

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen 
Reviewed-by: Tyrone Ting 
Signed-off-by: Hao Wu 
---
 tests/qtest/meson.build|   1 +
 tests/qtest/npcm7xx_pwm-test.c | 490 +
 2 files changed, 491 insertions(+)
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 955710d1c5..0b5467f084 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -136,6 +136,7 @@ qtests_sparc64 = \
 qtests_npcm7xx = \
   ['npcm7xx_adc-test',
'npcm7xx_gpio-test',
+   'npcm7xx_pwm-test',
'npcm7xx_rng-test',
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test']
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
new file mode 100644
index 00..33fbdf5f54
--- /dev/null
+++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -0,0 +1,490 @@
+/*
+ * QTests for Nuvoton NPCM7xx PWM Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qnum.h"
+
+#define REF_HZ  2500
+
+/* Register field definitions. */
+#define CH_EN   BIT(0)
+#define CH_INV  BIT(2)
+#define CH_MOD  BIT(3)
+
+/* Registers shared between all PWMs in a module */
+#define PPR 0x00
+#define CSR 0x04
+#define PCR 0x08
+#define PIER0x3c
+#define PIIR0x40
+
+/* CLK module related */
+#define CLK_BA  0xf0801000
+#define CLKSEL  0x04
+#define CLKDIV1 0x08
+#define CLKDIV2 0x2c
+#define PLLCON0 0x0c
+#define PLLCON1 0x10
+#define PLL_INDV(rv)extract32((rv), 0, 6)
+#define PLL_FBDV(rv)extract32((rv), 16, 12)
+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+#define CPUCKSEL(rv)extract32((rv), 0, 2)
+
+#define MAX_DUTY100
+
+typedef struct PWMModule {
+int irq;
+uint64_t base_addr;
+} PWMModule;
+
+typedef struct PWM {
+uint32_t cnr_offset;
+uint32_t cmr_offset;
+uint32_t pdr_offset;
+uint32_t pwdr_offset;
+} PWM;
+
+typedef struct TestData {
+const PWMModule *module;
+const PWM *pwm;
+} TestData;
+
+static const PWMModule pwm_module_list[] = {
+{
+.irq= 93,
+.base_addr  = 0xf0103000
+},
+{
+.irq= 94,
+.base_addr  = 0xf0104000
+}
+};
+
+static const PWM pwm_list[] = {
+{
+.cnr_offset = 0x0c,
+.cmr_offset = 0x10,
+.pdr_offset = 0x14,
+.pwdr_offset= 0x44,
+},
+{
+.cnr_offset = 0x18,
+.cmr_offset = 0x1c,
+.pdr_offset = 0x20,
+.pwdr_offset= 0x48,
+},
+{
+.cnr_offset = 0x24,
+.cmr_offset = 0x28,
+.pdr_offset = 0x2c,
+.pwdr_offset= 0x4c,
+},
+{
+.cnr_offset = 0x30,
+.cmr_offset = 0x34,
+.pdr_offset = 0x38,
+.pwdr_offset= 0x50,
+},
+};
+
+static const int ppr_base[] = { 0, 0, 8, 8 };
+static const int csr_base[] = { 0, 4, 8, 12 };
+static const int pcr_base[] = { 0, 8, 12, 16 };
+
+static const uint32_t ppr_list[] = {
+0,
+1,
+10,
+100,
+255, /* Max possible value. */
+};
+
+static const uint32_t csr_list[] = {
+0,
+1,
+2,
+3,
+4, /* Max possible value. */
+};
+
+static const uint32_t cnr_list[] = {
+0,
+1,
+50,
+100,
+150,
+200,
+1000,
+1,
+65535, /* Max possible value. */
+};
+
+static const uint32_t cmr_list[] = {
+0,
+1,
+10,
+50,
+100,
+150,
+200,
+1000,
+1,
+65535, /* Max possible value. */
+};
+
+/* Returns the index of the PWM module. */
+static int pwm_module_index(const PWMModule *module)
+{
+ptrdiff_t diff = module - pwm_module_list;
+
+g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
+
+return diff;
+}
+
+/* Returns the index of the PWM entry. */
+static int pwm_index(const PWM *pwm)
+{
+ptrdiff_t diff = pwm - pwm_list;
+
+g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
+
+return diff;
+}
+
+static 

[PATCH v3 1/5] hw/misc: Add clock converter in NPCM7XX CLK module

[Hao Wu via]

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen 
Reviewed-by: Tyrone Ting 
Signed-off-by: Hao Wu 
---
 hw/misc/npcm7xx_clk.c | 795 +-
 include/hw/misc/npcm7xx_clk.h | 140 +-
 2 files changed, 927 insertions(+), 8 deletions(-)

diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index 6732437fe2..48bc9bdda5 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -18,6 +18,7 @@
 
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/qdev-clock.h"
 #include "migration/vmstate.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -27,9 +28,22 @@
 #include "trace.h"
 #include "sysemu/watchdog.h"
 
+/*
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
+ * is always 25 MHz.
+ */
+#define NPCM7XX_CLOCK_REF_HZ(2500)
+
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
+
 #define PLLCON_LOKI BIT(31)
 #define PLLCON_LOKS BIT(30)
 #define PLLCON_PWDENBIT(12)
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+#define PLLCON_INDV(con) extract32((con), 0, 6)
 
 enum NPCM7xxCLKRegisters {
 NPCM7XX_CLK_CLKEN1,
@@ -89,12 +103,609 @@ static const uint32_t 
cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
 [NPCM7XX_CLK_AHBCKFI]   = 0x00c8,
 };
 
-/* Register Field Definitions */
-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-
 /* The number of watchdogs that can trigger a reset. */
 #define NPCM7XX_NR_WATCHDOGS(3)
 
+/* Clock converter functions */
+
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
+(obj), TYPE_NPCM7XX_CLOCK_PLL)
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
+(obj), TYPE_NPCM7XX_CLOCK_SEL)
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
+(obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
+
+static void npcm7xx_clk_update_pll(void *opaque)
+{
+NPCM7xxClockPLLState *s = opaque;
+uint32_t con = s->clk->regs[s->reg];
+uint64_t freq;
+
+/* The PLL is grounded if it is not locked yet. */
+if (con & PLLCON_LOKI) {
+freq = clock_get_hz(s->clock_in);
+freq *= PLLCON_FBDV(con);
+freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
+} else {
+freq = 0;
+}
+
+clock_update_hz(s->clock_out, freq);
+}
+
+static void npcm7xx_clk_update_sel(void *opaque)
+{
+NPCM7xxClockSELState *s = opaque;
+uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
+s->len);
+
+if (index >= s->input_size) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: SEL index: %u out of range\n",
+  __func__, index);
+index = 0;
+}
+clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
+}
+
+static void npcm7xx_clk_update_divider(void *opaque)
+{
+NPCM7xxClockDividerState *s = opaque;
+uint32_t freq;
+
+freq = s->divide(s);
+clock_update_hz(s->clock_out, freq);
+}
+
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
+{
+return clock_get_hz(s->clock_in) / s->divisor;
+}
+
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+return clock_get_hz(s->clock_in) /
+(extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
+}
+
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
+{
+return divide_by_reg_divisor(s) / 2;
+}
+
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+return clock_get_hz(s->clock_in) >>
+extract32(s->clk->regs[s->reg], s->offset, s->len);
+}
+
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
+{
+switch (reg) {
+case NPCM7XX_CLK_PLLCON0:
+return NPCM7XX_CLOCK_PLL0;
+case NPCM7XX_CLK_PLLCON1:
+return NPCM7XX_CLOCK_PLL1;
+case NPCM7XX_CLK_PLLCON2:
+return 

[PATCH v3 0/5] Additional NPCM7xx devices

[Hao Wu via]

This patch series include a few more NPCM7XX devices including

- Analog Digital Converter (ADC)
- Pulse Width Modulation (PWM)

We also modified the CLK module to generate clock values using qdev_clock.
These clocks are used to determine various clocks in NPCM7XX devices.

Thank you for your review.

Changes since v2:
- Split PWM test into a separate patch in the patch set
- Add trace events for PWM's update_freq/update_duty
- Add trace events for ioread/iowrite in ADC and PWM
- Use timer_get_ns in hw/timer/npcm7xx_timer.c
- Update commit message in ADC/PWM to mention qom-get/set method for usage
- Fix typos

Changes since v1:
- We removed the IPMI and KCS related code from this patch set.

Hao Wu (5):
  hw/misc: Add clock converter in NPCM7XX CLK module
  hw/timer: Refactor NPCM7XX Timer to use CLK clock
  hw/adc: Add an ADC module for NPCM7XX
  hw/misc: Add a PWM module for NPCM7XX
  hw/misc: Add QTest for NPCM7XX PWM Module

 docs/system/arm/nuvoton.rst  |   4 +-
 hw/adc/meson.build   |   1 +
 hw/adc/npcm7xx_adc.c | 321 +
 hw/adc/trace-events  |   5 +
 hw/arm/npcm7xx.c |  55 ++-
 hw/misc/meson.build  |   1 +
 hw/misc/npcm7xx_clk.c| 795 ++-
 hw/misc/npcm7xx_pwm.c| 559 ++
 hw/misc/trace-events |   6 +
 hw/timer/npcm7xx_timer.c |  23 +-
 include/hw/adc/npcm7xx_adc.h |  72 +++
 include/hw/arm/npcm7xx.h |   4 +
 include/hw/misc/npcm7xx_clk.h| 146 +-
 include/hw/misc/npcm7xx_pwm.h| 106 +
 include/hw/timer/npcm7xx_timer.h |   1 +
 meson.build  |   1 +
 tests/qtest/meson.build  |   4 +-
 tests/qtest/npcm7xx_adc-test.c   | 400 
 tests/qtest/npcm7xx_pwm-test.c   | 490 +++
 19 files changed, 2964 insertions(+), 30 deletions(-)
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/adc/trace-events
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

-- 
2.29.2.684.gfbc64c5ab5-goog

Re: [PATCH 3/3] Remove superfluous timer_del() calls

[Corey Minyard]

On Mon, Dec 14, 2020 at 08:30:50PM +, Peter Maydell wrote:
> This commit is the result of running the timer-del-timer-free.cocci
> script on the whole source tree.

For the ipmi portion:

Acked-by: Corey Minyard 

> 
> Signed-off-by: Peter Maydell 
> ---
> I could split this up into multiple patches -- is that worth while ?
> ---
>  block/iscsi.c  | 2 --
>  block/nbd.c| 1 -
>  block/qcow2.c  | 1 -
>  hw/block/nvme.c| 2 --
>  hw/char/serial.c   | 2 --
>  hw/char/virtio-serial-bus.c| 2 --
>  hw/ide/core.c  | 1 -
>  hw/input/hid.c | 1 -
>  hw/intc/apic.c | 1 -
>  hw/intc/ioapic.c   | 1 -
>  hw/ipmi/ipmi_bmc_extern.c  | 1 -
>  hw/net/e1000.c | 3 ---
>  hw/net/e1000e_core.c   | 8 
>  hw/net/pcnet-pci.c | 1 -
>  hw/net/rtl8139.c   | 1 -
>  hw/net/spapr_llan.c| 1 -
>  hw/net/virtio-net.c| 2 --
>  hw/s390x/s390-pci-inst.c   | 1 -
>  hw/sd/sd.c | 1 -
>  hw/sd/sdhci.c  | 2 --
>  hw/usb/dev-hub.c   | 1 -
>  hw/usb/hcd-ehci.c  | 1 -
>  hw/usb/hcd-ohci-pci.c  | 1 -
>  hw/usb/hcd-uhci.c  | 1 -
>  hw/usb/hcd-xhci.c  | 1 -
>  hw/usb/redirect.c  | 1 -
>  hw/vfio/display.c  | 1 -
>  hw/virtio/vhost-vsock-common.c | 1 -
>  hw/virtio/virtio-balloon.c | 1 -
>  hw/virtio/virtio-rng.c | 1 -
>  hw/watchdog/wdt_diag288.c  | 1 -
>  hw/watchdog/wdt_i6300esb.c | 1 -
>  migration/colo.c   | 1 -
>  monitor/hmp-cmds.c | 1 -
>  net/announce.c | 1 -
>  net/colo-compare.c | 1 -
>  net/slirp.c| 1 -
>  replay/replay-debugging.c  | 1 -
>  target/s390x/cpu.c | 2 --
>  ui/console.c   | 1 -
>  ui/spice-core.c| 1 -
>  util/throttle.c| 1 -
>  42 files changed, 58 deletions(-)
> 
> diff --git a/block/iscsi.c b/block/iscsi.c
> index 7d4b3b56d5c..4d2a416ce77 100644
> --- a/block/iscsi.c
> +++ b/block/iscsi.c
> @@ -1524,12 +1524,10 @@ static void iscsi_detach_aio_context(BlockDriverState 
> *bs)
>  iscsilun->events = 0;
>  
>  if (iscsilun->nop_timer) {
> -timer_del(iscsilun->nop_timer);
>  timer_free(iscsilun->nop_timer);
>  iscsilun->nop_timer = NULL;
>  }
>  if (iscsilun->event_timer) {
> -timer_del(iscsilun->event_timer);
>  timer_free(iscsilun->event_timer);
>  iscsilun->event_timer = NULL;
>  }
> diff --git a/block/nbd.c b/block/nbd.c
> index 42536702b6f..242a258f3a5 100644
> --- a/block/nbd.c
> +++ b/block/nbd.c
> @@ -194,7 +194,6 @@ static void nbd_recv_coroutines_wake_all(BDRVNBDState *s)
>  static void reconnect_delay_timer_del(BDRVNBDState *s)
>  {
>  if (s->reconnect_delay_timer) {
> -timer_del(s->reconnect_delay_timer);
>  timer_free(s->reconnect_delay_timer);
>  s->reconnect_delay_timer = NULL;
>  }
> diff --git a/block/qcow2.c b/block/qcow2.c
> index 3a90ef27868..5d94f45be95 100644
> --- a/block/qcow2.c
> +++ b/block/qcow2.c
> @@ -852,7 +852,6 @@ static void cache_clean_timer_del(BlockDriverState *bs)
>  {
>  BDRVQcow2State *s = bs->opaque;
>  if (s->cache_clean_timer) {
> -timer_del(s->cache_clean_timer);
>  timer_free(s->cache_clean_timer);
>  s->cache_clean_timer = NULL;
>  }
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index 01b657b1c5e..27d2c72716e 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -1052,7 +1052,6 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest 
> *req)
>  static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
>  {
>  n->sq[sq->sqid] = NULL;
> -timer_del(sq->timer);
>  timer_free(sq->timer);
>  g_free(sq->io_req);
>  if (sq->sqid) {
> @@ -1334,7 +1333,6 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest 
> *req)
>  static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
>  {
>  n->cq[cq->cqid] = NULL;
> -timer_del(cq->timer);
>  timer_free(cq->timer);
>  msix_vector_unuse(>parent_obj, cq->vector);
>  if (cq->cqid) {
> diff --git a/hw/char/serial.c b/hw/char/serial.c
> index 62c627f486f..b8d5a1e9972 100644
> --- a/hw/char/serial.c
> +++ b/hw/char/serial.c
> @@ -940,10 +940,8 @@ static void serial_unrealize(DeviceState *dev)
>  
>  qemu_chr_fe_deinit(>chr, false);
>  
> -timer_del(s->modem_status_poll);
>  timer_free(s->modem_status_poll);
>  
> -timer_del(s->fifo_timeout_timer);
>  timer_free(s->fifo_timeout_timer);
>  
>  fifo8_destroy(>recv_fifo);
> diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
> index cf08ef97281..b20038991a6 100644
> --- a/hw/char/virtio-serial-bus.c
> +++ b/hw/char/virtio-serial-bus.c
> @@ -741,7 +741,6 @@ static void 

[PATCH 11/12] qapi/schema: Name the builtin module "" instead of None

[John Snow]

Instead of using None as the built-in module filename, use an empty
string instead. This allows us to clarify the type of various interfaces
dealing with module names as always taking a string, which saves us from
having to use Optional[str] everywhere.

Signed-off-by: John Snow 
---
 scripts/qapi/gen.py  |  6 +++---
 scripts/qapi/schema.py   | 12 ++--
 scripts/qapi/types.py|  2 +-
 scripts/qapi/visit.py|  2 +-
 tests/qapi-schema/comments.out   |  2 +-
 tests/qapi-schema/doc-good.out   |  2 +-
 tests/qapi-schema/empty.out  |  2 +-
 tests/qapi-schema/event-case.out |  2 +-
 tests/qapi-schema/include-repetition.out |  2 +-
 tests/qapi-schema/include-simple.out |  2 +-
 tests/qapi-schema/indented-expr.out  |  2 +-
 tests/qapi-schema/qapi-schema-test.out   |  2 +-
 12 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index b2c89213d838..a577a4a7f002 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -309,14 +309,14 @@ def write(self, output_dir: str, opt_builtins: bool = 
False) -> None:
 genc.write(output_dir)
 genh.write(output_dir)
 
-def _begin_system_module(self, name: None) -> None:
+def _begin_system_module(self, name: str) -> None:
 pass
 
 def _begin_user_module(self, name: str) -> None:
 pass
 
-def visit_module(self, name: Optional[str]) -> None:
-if name is None:
+def visit_module(self, name: str) -> None:
+if not name:
 if self._builtin_blurb:
 self._add_system_module('builtin', self._builtin_blurb)
 self._begin_system_module(name)
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
index d5f19732b516..8d8b8758f65e 100644
--- a/scripts/qapi/schema.py
+++ b/scripts/qapi/schema.py
@@ -69,7 +69,7 @@ def check_doc(self):
 
 def _set_module(self, schema, info):
 assert self._checked
-self._module = schema.module_by_fname(info and info.fname)
+self._module = schema.module_by_fname(info.fname)
 self._module.add_entity(self)
 
 def set_module(self, schema):
@@ -826,7 +826,7 @@ def __init__(self, fname):
 self._entity_dict = {}
 self._module_dict = OrderedDict()
 self._schema_dir = os.path.dirname(fname)
-self._make_module(None)  # built-ins
+self._make_module(QAPISourceInfo.builtin().fname)  # built-ins
 self._make_module(fname)
 self._predefining = True
 self._def_predefineds()
@@ -871,10 +871,10 @@ def resolve_type(self, name, info, what):
 info, "%s uses unknown type '%s'" % (what, name))
 return typ
 
-def _module_name(self, fname):
-if not fname:
-return None
-return os.path.relpath(fname, self._schema_dir)
+def _module_name(self, fname: str) -> str:
+if fname:
+return os.path.relpath(fname, self._schema_dir)
+return fname
 
 def _make_module(self, fname):
 name = self._module_name(fname)
diff --git a/scripts/qapi/types.py b/scripts/qapi/types.py
index a3a16284006b..12eeea3aaffe 100644
--- a/scripts/qapi/types.py
+++ b/scripts/qapi/types.py
@@ -272,7 +272,7 @@ def __init__(self, prefix: str):
 prefix, 'qapi-types', ' * Schema-defined QAPI types',
 ' * Built-in QAPI types', __doc__)
 
-def _begin_system_module(self, name: None) -> None:
+def _begin_system_module(self, name: str) -> None:
 self._genc.preamble_add(mcgen('''
 #include "qemu/osdep.h"
 #include "qapi/dealloc-visitor.h"
diff --git a/scripts/qapi/visit.py b/scripts/qapi/visit.py
index 3f49c307c566..76e34ee7f02e 100644
--- a/scripts/qapi/visit.py
+++ b/scripts/qapi/visit.py
@@ -305,7 +305,7 @@ def __init__(self, prefix: str):
 prefix, 'qapi-visit', ' * Schema-defined QAPI visitors',
 ' * Built-in QAPI visitors', __doc__)
 
-def _begin_system_module(self, name: None) -> None:
+def _begin_system_module(self, name: str) -> None:
 self._genc.preamble_add(mcgen('''
 #include "qemu/osdep.h"
 #include "qapi/error.h"
diff --git a/tests/qapi-schema/comments.out b/tests/qapi-schema/comments.out
index 08aba8354e2a..02000c06e5e0 100644
--- a/tests/qapi-schema/comments.out
+++ b/tests/qapi-schema/comments.out
@@ -1,4 +1,4 @@
-module "None"
+module ""
 object q_empty
 enum QType
 prefix QTYPE
diff --git a/tests/qapi-schema/doc-good.out b/tests/qapi-schema/doc-good.out
index 83a3d9bd69b5..494533d74793 100644
--- a/tests/qapi-schema/doc-good.out
+++ b/tests/qapi-schema/doc-good.out
@@ -1,4 +1,4 @@
-module "None"
+module ""
 object q_empty
 enum QType
 prefix QTYPE
diff --git a/tests/qapi-schema/empty.out b/tests/qapi-schema/empty.out
index 0dac23c80c15..059caa4e1d2a 100644
--- a/tests/qapi-schema/empty.out
+++ b/tests/qapi-schema/empty.out
@@ -1,4 +1,4 

[PATCH 08/12] qapi/schema: make QAPISourceInfo mandatory

[John Snow]

--

events.py had an info to route, was it by choice that it wasn't before?
Signed-off-by: John Snow 
---
 scripts/qapi/events.py |  2 +-
 scripts/qapi/schema.py | 23 +--
 scripts/qapi/types.py  |  9 +
 scripts/qapi/visit.py  |  6 +++---
 4 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/scripts/qapi/events.py b/scripts/qapi/events.py
index 9851653b9d11..9ba4f109028d 100644
--- a/scripts/qapi/events.py
+++ b/scripts/qapi/events.py
@@ -225,7 +225,7 @@ def visit_event(self,
   self._event_emit_name))
 # Note: we generate the enum member regardless of @ifcond, to
 # keep the enumeration usable in target-independent code.
-self._event_enum_members.append(QAPISchemaEnumMember(name, None))
+self._event_enum_members.append(QAPISchemaEnumMember(name, info))
 
 
 def gen_events(schema: QAPISchema,
diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
index 720449feee4d..d5f19732b516 100644
--- a/scripts/qapi/schema.py
+++ b/scripts/qapi/schema.py
@@ -23,6 +23,7 @@
 from .error import QAPIError, QAPISemError
 from .expr import check_exprs
 from .parser import QAPISchemaParser
+from .source import QAPISourceInfo
 
 
 class QAPISchemaEntity:
@@ -36,10 +37,10 @@ def __init__(self, name, info, doc, ifcond=None, 
features=None):
 self.name = name
 self._module = None
 # For explicitly defined entities, info points to the (explicit)
-# definition.  For builtins (and their arrays), info is None.
-# For implicitly defined entities, info points to a place that
-# triggered the implicit definition (there may be more than one
-# such place).
+# definition.  For builtins (and their arrays), info is a null-object
+# sentinel that evaluates to False. For implicitly defined entities,
+# info points to a place that triggered the implicit definition
+# (there may be more than one such place).
 self.info = info
 self.doc = doc
 self._ifcond = ifcond or []
@@ -209,7 +210,7 @@ class QAPISchemaBuiltinType(QAPISchemaType):
 meta = 'built-in'
 
 def __init__(self, name, json_type, c_type):
-super().__init__(name, None, None)
+super().__init__(name, QAPISourceInfo.builtin(), None)
 assert not c_type or isinstance(c_type, str)
 assert json_type in ('string', 'number', 'int', 'boolean', 'null',
  'value')
@@ -871,7 +872,7 @@ def resolve_type(self, name, info, what):
 return typ
 
 def _module_name(self, fname):
-if fname is None:
+if not fname:
 return None
 return os.path.relpath(fname, self._schema_dir)
 
@@ -897,9 +898,11 @@ def _def_builtin_type(self, name, json_type, c_type):
 # be nice, but we can't as long as their generated code
 # (qapi-builtin-types.[ch]) may be shared by some other
 # schema.
-self._make_array_type(name, None)
+self._make_array_type(name, QAPISourceInfo.builtin())
 
 def _def_predefineds(self):
+info = QAPISourceInfo.builtin()
+
 for t in [('str','string',  'char' + POINTER_SUFFIX),
   ('number', 'number',  'double'),
   ('int','int', 'int64_t'),
@@ -917,15 +920,15 @@ def _def_predefineds(self):
   ('null',   'null','QNull' + POINTER_SUFFIX)]:
 self._def_builtin_type(*t)
 self.the_empty_object_type = QAPISchemaObjectType(
-'q_empty', None, None, None, None, None, [], None)
+'q_empty', info, None, None, None, None, [], None)
 self._def_entity(self.the_empty_object_type)
 
 qtypes = ['none', 'qnull', 'qnum', 'qstring', 'qdict', 'qlist',
   'qbool']
 qtype_values = self._make_enum_members(
-[{'name': n} for n in qtypes], None)
+[{'name': n} for n in qtypes], info)
 
-self._def_entity(QAPISchemaEnumType('QType', None, None, None, None,
+self._def_entity(QAPISchemaEnumType('QType', info, None, None, None,
 qtype_values, 'QTYPE'))
 
 def _make_features(self, features, info):
diff --git a/scripts/qapi/types.py b/scripts/qapi/types.py
index 2b4916cdaa1b..a3a16284006b 100644
--- a/scripts/qapi/types.py
+++ b/scripts/qapi/types.py
@@ -71,7 +71,8 @@ def gen_enum(name: str,
  members: List[QAPISchemaEnumMember],
  prefix: Optional[str] = None) -> str:
 # append automatically generated _MAX value
-enum_members = members + [QAPISchemaEnumMember('_MAX', None)]
+enum_members = members + [
+QAPISchemaEnumMember('_MAX', QAPISourceInfo.builtin())]
 
 ret = mcgen('''
 
@@ -306,7 +307,7 @@ def _gen_type_cleanup(self, name: str) -> None:
 
 def visit_enum_type(self,
 name: str,
-info: 

[PATCH 10/12] tests/qapi-schema: Add quotes to module name in test output

[John Snow]

A forthcoming patch is going to allow the empty string as a name for the
builtin module, and quotes will help us see that in test output. Without
this, git will be upset about trailing empty spaces in test output, so
the quotes are necessary.

Signed-off-by: John Snow 
---
 tests/qapi-schema/comments.out   | 4 ++--
 tests/qapi-schema/doc-good.out   | 4 ++--
 tests/qapi-schema/empty.out  | 4 ++--
 tests/qapi-schema/event-case.out | 4 ++--
 tests/qapi-schema/include-repetition.out | 8 
 tests/qapi-schema/include-simple.out | 6 +++---
 tests/qapi-schema/indented-expr.out  | 4 ++--
 tests/qapi-schema/qapi-schema-test.out   | 8 
 tests/qapi-schema/test-qapi.py   | 2 +-
 9 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/tests/qapi-schema/comments.out b/tests/qapi-schema/comments.out
index 273f0f54e16c..08aba8354e2a 100644
--- a/tests/qapi-schema/comments.out
+++ b/tests/qapi-schema/comments.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,7 +9,7 @@ enum QType
 member qdict
 member qlist
 member qbool
-module comments.json
+module "comments.json"
 enum Status
 member good
 member bad
diff --git a/tests/qapi-schema/doc-good.out b/tests/qapi-schema/doc-good.out
index 419284dae29b..83a3d9bd69b5 100644
--- a/tests/qapi-schema/doc-good.out
+++ b/tests/qapi-schema/doc-good.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,7 +9,7 @@ enum QType
 member qdict
 member qlist
 member qbool
-module doc-good.json
+module "doc-good.json"
 enum Enum
 member one
 if ['defined(IFONE)']
diff --git a/tests/qapi-schema/empty.out b/tests/qapi-schema/empty.out
index 69666c39ad2d..0dac23c80c15 100644
--- a/tests/qapi-schema/empty.out
+++ b/tests/qapi-schema/empty.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,4 +9,4 @@ enum QType
 member qdict
 member qlist
 member qbool
-module empty.json
+module "empty.json"
diff --git a/tests/qapi-schema/event-case.out b/tests/qapi-schema/event-case.out
index 42ae519656dc..ace511ba5a96 100644
--- a/tests/qapi-schema/event-case.out
+++ b/tests/qapi-schema/event-case.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,6 +9,6 @@ enum QType
 member qdict
 member qlist
 member qbool
-module event-case.json
+module "event-case.json"
 event oops None
 boxed=False
diff --git a/tests/qapi-schema/include-repetition.out 
b/tests/qapi-schema/include-repetition.out
index 0b654ddebb6a..f7ab4987943c 100644
--- a/tests/qapi-schema/include-repetition.out
+++ b/tests/qapi-schema/include-repetition.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,15 +9,15 @@ enum QType
 member qdict
 member qlist
 member qbool
-module include-repetition.json
+module "include-repetition.json"
 include comments.json
 include include-repetition-sub.json
 include comments.json
-module comments.json
+module "comments.json"
 enum Status
 member good
 member bad
 member ugly
-module include-repetition-sub.json
+module "include-repetition-sub.json"
 include comments.json
 include comments.json
diff --git a/tests/qapi-schema/include-simple.out 
b/tests/qapi-schema/include-simple.out
index 061f81e50904..81bdeb887b66 100644
--- a/tests/qapi-schema/include-simple.out
+++ b/tests/qapi-schema/include-simple.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,9 +9,9 @@ enum QType
 member qdict
 member qlist
 member qbool
-module include-simple.json
+module "include-simple.json"
 include include-simple-sub.json
-module include-simple-sub.json
+module "include-simple-sub.json"
 enum Status
 member good
 member bad
diff --git a/tests/qapi-schema/indented-expr.out 
b/tests/qapi-schema/indented-expr.out
index 04356775cd16..361a58185e67 100644
--- a/tests/qapi-schema/indented-expr.out
+++ b/tests/qapi-schema/indented-expr.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,7 +9,7 @@ enum QType
 member qdict
 member qlist
 member qbool
-module indented-expr.json
+module "indented-expr.json"
 command eins None -> None
 gen=True success_response=True boxed=False oob=False preconfig=False
 command zwei None -> None
diff --git a/tests/qapi-schema/qapi-schema-test.out 
b/tests/qapi-schema/qapi-schema-test.out
index 8868ca0dca9e..4f5ab9fd596c 100644
--- a/tests/qapi-schema/qapi-schema-test.out
+++ b/tests/qapi-schema/qapi-schema-test.out
@@ -1,4 +1,4 @@
-module None
+module "None"
 object q_empty
 enum QType
 prefix QTYPE
@@ -9,7 +9,7 @@ enum QType
 member qdict
 member qlist
 member qbool
-module qapi-schema-test.json
+module "qapi-schema-test.json"
 object TestStruct
 member integer: int 

[PATCH 12/12] qapi: enable strict-optional checks

[John Snow]

In the modules that we are checking so far, we can be stricter about the
difference between Optional[T] and T types. Enable that check.

Enabling it now will assist review on further typing and cleanup work.

Signed-off-by: John Snow 
---
 scripts/qapi/mypy.ini | 1 -
 1 file changed, 1 deletion(-)

diff --git a/scripts/qapi/mypy.ini b/scripts/qapi/mypy.ini
index 74fc6c82153e..04bd5db5278d 100644
--- a/scripts/qapi/mypy.ini
+++ b/scripts/qapi/mypy.ini
@@ -1,6 +1,5 @@
 [mypy]
 strict = True
-strict_optional = False
 disallow_untyped_calls = False
 python_version = 3.6
 
-- 
2.26.2

[PATCH 09/12] qapi/gen: move write method to QAPIGenC, make fname a str

[John Snow]

QAPIGenC and QAPIGenH in particular depend on fname being defined, but
we have a usage of QAPIGenCCode that isn't intended to be associated
with a particular file.

No problem, move the write method down to the class that actually needs
it, and keep QAPIGenCCode more abstract.

Signed-off-by: John Snow 
---
 scripts/qapi/commands.py |  2 +-
 scripts/qapi/gen.py  | 54 
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/scripts/qapi/commands.py b/scripts/qapi/commands.py
index 71744f48a353..b346676d15a0 100644
--- a/scripts/qapi/commands.py
+++ b/scripts/qapi/commands.py
@@ -258,7 +258,7 @@ def __init__(self, prefix: str):
 super().__init__(
 prefix, 'qapi-commands',
 ' * Schema-defined QAPI/QMP commands', None, __doc__)
-self._regy = QAPIGenCCode(None)
+self._regy = QAPIGenCCode()
 self._visited_ret_types: Dict[QAPIGenC, Set[QAPISchemaType]] = {}
 
 def _begin_user_module(self, name: str) -> None:
diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index 17ae9f4af703..b2c89213d838 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -36,8 +36,7 @@
 
 
 class QAPIGen:
-def __init__(self, fname: Optional[str]):
-self.fname = fname
+def __init__(self) -> None:
 self._preamble = ''
 self._body = ''
 
@@ -58,28 +57,6 @@ def _bottom(self) -> str:
 # pylint: disable=no-self-use
 return ''
 
-def write(self, output_dir: str) -> None:
-# Include paths starting with ../ are used to reuse modules of the main
-# schema in specialised schemas. Don't overwrite the files that are
-# already generated for the main schema.
-if self.fname.startswith('../'):
-return
-pathname = os.path.join(output_dir, self.fname)
-odir = os.path.dirname(pathname)
-
-if odir:
-os.makedirs(odir, exist_ok=True)
-
-# use os.open for O_CREAT to create and read a non-existant file
-fd = os.open(pathname, os.O_RDWR | os.O_CREAT, 0o666)
-with os.fdopen(fd, 'r+', encoding='utf-8') as fp:
-text = self.get_content()
-oldtext = fp.read(len(text) + 1)
-if text != oldtext:
-fp.seek(0)
-fp.truncate(0)
-fp.write(text)
-
 
 def _wrap_ifcond(ifcond: List[str], before: str, after: str) -> str:
 if before == after:
@@ -121,8 +98,8 @@ def build_params(arg_type: Optional[QAPISchemaObjectType],
 
 
 class QAPIGenCCode(QAPIGen):
-def __init__(self, fname: Optional[str]):
-super().__init__(fname)
+def __init__(self) -> None:
+super().__init__()
 self._start_if: Optional[Tuple[List[str], str, str]] = None
 
 def start_if(self, ifcond: List[str]) -> None:
@@ -147,11 +124,34 @@ def get_content(self) -> str:
 
 class QAPIGenC(QAPIGenCCode):
 def __init__(self, fname: str, blurb: str, pydoc: str):
-super().__init__(fname)
+super().__init__()
+self.fname = fname
 self._blurb = blurb
 self._copyright = '\n * '.join(re.findall(r'^Copyright .*', pydoc,
   re.MULTILINE))
 
+def write(self, output_dir: str) -> None:
+# Include paths starting with ../ are used to reuse modules of the main
+# schema in specialised schemas. Don't overwrite the files that are
+# already generated for the main schema.
+if self.fname.startswith('../'):
+return
+pathname = os.path.join(output_dir, self.fname)
+odir = os.path.dirname(pathname)
+
+if odir:
+os.makedirs(odir, exist_ok=True)
+
+# use os.open for O_CREAT to create and read a non-existant file
+fd = os.open(pathname, os.O_RDWR | os.O_CREAT, 0o666)
+with os.fdopen(fd, 'r+', encoding='utf-8') as fp:
+text = self.get_content()
+oldtext = fp.read(len(text) + 1)
+if text != oldtext:
+fp.seek(0)
+fp.truncate(0)
+fp.write(text)
+
 def _top(self) -> str:
 return mcgen('''
 /* AUTOMATICALLY GENERATED, DO NOT MODIFY */
-- 
2.26.2

[PATCH 07/12] qapi/gen: write _genc/_genh access shims

[John Snow]

Many places assume they can access these fields without checking them
first to ensure they are defined. Eliminating the _genc and _genh fields
and replacing them with functional properties that check for correct
state can ease the typing overhead by eliminating the Optional[T] return
type.

Signed-off-by: John Snow 
---
 scripts/qapi/gen.py | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index 0c5d1fee6088..17ae9f4af703 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -243,11 +243,20 @@ def __init__(self,
 self._user_blurb = user_blurb
 self._builtin_blurb = builtin_blurb
 self._pydoc = pydoc
-self._genc: Optional[QAPIGenC] = None
-self._genh: Optional[QAPIGenH] = None
+self._current_module: Optional[str] = None
 self._module: Dict[str, Tuple[QAPIGenC, QAPIGenH]] = {}
 self._main_module: Optional[str] = None
 
+@property
+def _genc(self) -> QAPIGenC:
+assert self._current_module is not None
+return self._module[self._current_module][0]
+
+@property
+def _genh(self) -> QAPIGenH:
+assert self._current_module is not None
+return self._module[self._current_module][1]
+
 @staticmethod
 def _is_user_module(name: str) -> bool:
 return not name.startswith('./')
@@ -281,7 +290,7 @@ def _add_module(self, name: str, blurb: str) -> None:
 genc = QAPIGenC(basename + '.c', blurb, self._pydoc)
 genh = QAPIGenH(basename + '.h', blurb, self._pydoc)
 self._module[name] = (genc, genh)
-self._genc, self._genh = self._module[name]
+self._current_module = name
 
 def _add_user_module(self, name: str, blurb: str) -> None:
 assert self._is_user_module(name)
@@ -314,8 +323,7 @@ def visit_module(self, name: Optional[str]) -> None:
 else:
 # The built-in module has not been created.  No code may
 # be generated.
-self._genc = None
-self._genh = None
+self._current_module = None
 else:
 self._add_user_module(name, self._user_blurb)
 self._begin_user_module(name)
-- 
2.26.2

[PATCH 04/12] qapi/gen: assert that _start_if is not None in _wrap_ifcond

[John Snow]

We already assert this in end_if, but that's opaque to mypy. Do it in
_wrap_ifcond instead. Same effect at runtime, but mypy can now infer
the type in _wrap_ifcond's body.

Signed-off-by: John Snow 
---
 scripts/qapi/gen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index b40f18eee3cd..a6dc991b1d03 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -130,11 +130,11 @@ def start_if(self, ifcond: List[str]) -> None:
 self._start_if = (ifcond, self._body, self._preamble)
 
 def end_if(self) -> None:
-assert self._start_if
 self._wrap_ifcond()
 self._start_if = None
 
 def _wrap_ifcond(self) -> None:
+assert self._start_if
 self._body = _wrap_ifcond(self._start_if[0],
   self._start_if[1], self._body)
 self._preamble = _wrap_ifcond(self._start_if[0],
-- 
2.26.2

[PATCH 06/12] qapi/source: Add builtin null-object sentinel

[John Snow]

We use None to represent an object that has no source information
because it's a builtin. This complicates interface typing, since many
interfaces expect that there is an info object available to print errors
with.

Introduce a special QAPISourceInfo that represents these built-ins so
that if an error should so happen to occur relating to one of these
builtins that we will be able to print its information, and interface
typing becomes simpler: you will always have a source info object.

This object will evaluate as False, so "if info" is a valid idiomatic
construct.

NB: It was intentional to not allow empty constructors or similar to
create "empty" source info objects; callers must explicitly invoke
'builtin()' to pro-actively opt into using the sentinel. This should
prevent use-by-accident.

Signed-off-by: John Snow 
---
 scripts/qapi/source.py | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/scripts/qapi/source.py b/scripts/qapi/source.py
index d7a79a9b8aee..64af7318cb67 100644
--- a/scripts/qapi/source.py
+++ b/scripts/qapi/source.py
@@ -11,7 +11,12 @@
 
 import copy
 import sys
-from typing import List, Optional, TypeVar
+from typing import (
+List,
+Optional,
+Type,
+TypeVar,
+)
 
 
 class QAPISchemaPragma:
@@ -41,6 +46,17 @@ def __init__(self, fname: str, line: int,
 self.defn_meta: Optional[str] = None
 self.defn_name: Optional[str] = None
 
+@classmethod
+def builtin(cls: Type[T]) -> T:
+"""
+Create a SourceInfo object corresponding to a builtin definition.
+"""
+return cls('', -1, None)
+
+def __bool__(self) -> bool:
+# "if info: ..." is false if info is the builtin sentinel.
+return bool(self.fname)
+
 def set_defn(self, meta: str, name: str) -> None:
 self.defn_meta = meta
 self.defn_name = name
@@ -73,4 +89,6 @@ def include_path(self) -> str:
 return ret
 
 def __str__(self) -> str:
+if not bool(self):
+return '[builtin]'
 return self.include_path() + self.in_defn() + self.loc()
-- 
2.26.2

[PATCH 05/12] qapi/gen: use './builtin' for the built-in module name

[John Snow]

Use this in preference to 'None', which helps remove some edge cases in
the typing.

Signed-off-by: John Snow 
---
 scripts/qapi/gen.py | 27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/scripts/qapi/gen.py b/scripts/qapi/gen.py
index a6dc991b1d03..0c5d1fee6088 100644
--- a/scripts/qapi/gen.py
+++ b/scripts/qapi/gen.py
@@ -245,23 +245,23 @@ def __init__(self,
 self._pydoc = pydoc
 self._genc: Optional[QAPIGenC] = None
 self._genh: Optional[QAPIGenH] = None
-self._module: Dict[Optional[str], Tuple[QAPIGenC, QAPIGenH]] = {}
+self._module: Dict[str, Tuple[QAPIGenC, QAPIGenH]] = {}
 self._main_module: Optional[str] = None
 
 @staticmethod
-def _is_user_module(name: Optional[str]) -> bool:
-return bool(name and not name.startswith('./'))
+def _is_user_module(name: str) -> bool:
+return not name.startswith('./')
 
 @staticmethod
-def _is_builtin_module(name: Optional[str]) -> bool:
-return not name
+def _is_builtin_module(name: str) -> bool:
+return name == './builtin'
 
-def _module_dirname(self, name: Optional[str]) -> str:
+def _module_dirname(self, name: str) -> str:
 if self._is_user_module(name):
 return os.path.dirname(name)
 return ''
 
-def _module_basename(self, what: str, name: Optional[str]) -> str:
+def _module_basename(self, what: str, name: str) -> str:
 ret = '' if self._is_builtin_module(name) else self._prefix
 if self._is_user_module(name):
 basename = os.path.basename(name)
@@ -269,15 +269,14 @@ def _module_basename(self, what: str, name: 
Optional[str]) -> str:
 if name != self._main_module:
 ret += '-' + os.path.splitext(basename)[0]
 else:
-name = name[2:] if name else 'builtin'
-ret += re.sub(r'-', '-' + name + '-', what)
+ret += re.sub(r'-', '-' + name[2:] + '-', what)
 return ret
 
-def _module_filename(self, what: str, name: Optional[str]) -> str:
+def _module_filename(self, what: str, name: str) -> str:
 return os.path.join(self._module_dirname(name),
 self._module_basename(what, name))
 
-def _add_module(self, name: Optional[str], blurb: str) -> None:
+def _add_module(self, name: str, blurb: str) -> None:
 basename = self._module_filename(self._what, name)
 genc = QAPIGenC(basename + '.c', blurb, self._pydoc)
 genh = QAPIGenH(basename + '.h', blurb, self._pydoc)
@@ -290,8 +289,8 @@ def _add_user_module(self, name: str, blurb: str) -> None:
 self._main_module = name
 self._add_module(name, blurb)
 
-def _add_system_module(self, name: Optional[str], blurb: str) -> None:
-self._add_module(name and './' + name, blurb)
+def _add_system_module(self, name: str, blurb: str) -> None:
+self._add_module(f"./{name}", blurb)
 
 def write(self, output_dir: str, opt_builtins: bool = False) -> None:
 for name in self._module:
@@ -310,7 +309,7 @@ def _begin_user_module(self, name: str) -> None:
 def visit_module(self, name: Optional[str]) -> None:
 if name is None:
 if self._builtin_blurb:
-self._add_system_module(None, self._builtin_blurb)
+self._add_system_module('builtin', self._builtin_blurb)
 self._begin_system_module(name)
 else:
 # The built-in module has not been created.  No code may
-- 
2.26.2

[PATCH 03/12] qapi/main: handle theoretical None-return from re.match()

[John Snow]

Mypy cannot understand that this match can never be None, so help it
along.

Signed-off-by: John Snow 
---
 scripts/qapi/main.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/qapi/main.py b/scripts/qapi/main.py
index 42517210b805..271d9e84da94 100644
--- a/scripts/qapi/main.py
+++ b/scripts/qapi/main.py
@@ -23,7 +23,8 @@
 
 def invalid_prefix_char(prefix: str) -> Optional[str]:
 match = re.match(r'([A-Za-z_.-][A-Za-z0-9_.-]*)?', prefix)
-if match.end() != len(prefix):
+# match cannot be None, but mypy cannot infer that.
+if match and match.end() != len(prefix):
 return prefix[match.end()]
 return None
 
-- 
2.26.2

[PATCH 02/12] qapi/events: fix visit_event typing

[John Snow]

Actually, the arg_type can indeed be Optional.

Signed-off-by: John Snow 
---
 scripts/qapi/events.py | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/scripts/qapi/events.py b/scripts/qapi/events.py
index 599f3d1f564b..9851653b9d11 100644
--- a/scripts/qapi/events.py
+++ b/scripts/qapi/events.py
@@ -12,7 +12,7 @@
 See the COPYING file in the top-level directory.
 """
 
-from typing import List
+from typing import List, Optional
 
 from .common import c_enum_const, c_name, mcgen
 from .gen import QAPISchemaModularCVisitor, build_params, ifcontext
@@ -27,7 +27,7 @@
 
 
 def build_event_send_proto(name: str,
-   arg_type: QAPISchemaObjectType,
+   arg_type: Optional[QAPISchemaObjectType],
boxed: bool) -> str:
 return 'void qapi_event_send_%(c_name)s(%(param)s)' % {
 'c_name': c_name(name.lower()),
@@ -35,7 +35,7 @@ def build_event_send_proto(name: str,
 
 
 def gen_event_send_decl(name: str,
-arg_type: QAPISchemaObjectType,
+arg_type: Optional[QAPISchemaObjectType],
 boxed: bool) -> str:
 return mcgen('''
 
@@ -78,7 +78,7 @@ def gen_param_var(typ: QAPISchemaObjectType) -> str:
 
 
 def gen_event_send(name: str,
-   arg_type: QAPISchemaObjectType,
+   arg_type: Optional[QAPISchemaObjectType],
boxed: bool,
event_enum_name: str,
event_emit: str) -> str:
@@ -99,6 +99,7 @@ def gen_event_send(name: str,
 proto=build_event_send_proto(name, arg_type, boxed))
 
 if have_args:
+assert arg_type is not None
 ret += mcgen('''
 QObject *obj;
 Visitor *v;
@@ -114,6 +115,7 @@ def gen_event_send(name: str,
  name=name)
 
 if have_args:
+assert arg_type is not None
 ret += mcgen('''
 v = qobject_output_visitor_new();
 ''')
@@ -214,7 +216,7 @@ def visit_event(self,
 info: QAPISourceInfo,
 ifcond: List[str],
 features: List[QAPISchemaFeature],
-arg_type: QAPISchemaObjectType,
+arg_type: Optional[QAPISchemaObjectType],
 boxed: bool) -> None:
 with ifcontext(ifcond, self._genh, self._genc):
 self._genh.add(gen_event_send_decl(name, arg_type, boxed))
-- 
2.26.2

[PATCH 01/12] qapi/commands: assert arg_type is not None

[John Snow]

when boxed is true, expr.py asserts that we must have
arguments. Ultimately, this should mean that if boxed is True, that
arg_type should be defined. Mypy cannot infer this, and does not support
'stateful' type inference, e.g.:

```
if x:
assert y is not None

...

if x:
y.etc()
```

does not work, because mypy does not statefully remember the conditional
assertion in the second block. Help mypy out by creating a new local
that it can track more easily.

Signed-off-by: John Snow 
---
 scripts/qapi/commands.py | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/scripts/qapi/commands.py b/scripts/qapi/commands.py
index 50978090b440..71744f48a353 100644
--- a/scripts/qapi/commands.py
+++ b/scripts/qapi/commands.py
@@ -126,6 +126,9 @@ def gen_marshal(name: str,
 boxed: bool,
 ret_type: Optional[QAPISchemaType]) -> str:
 have_args = boxed or (arg_type and not arg_type.is_empty())
+if have_args:
+assert arg_type is not None
+arg_type_c_name = arg_type.c_name()
 
 ret = mcgen('''
 
@@ -147,7 +150,7 @@ def gen_marshal(name: str,
 ret += mcgen('''
 %(c_name)s arg = {0};
 ''',
- c_name=arg_type.c_name())
+ c_name=arg_type_c_name)
 
 ret += mcgen('''
 
@@ -163,7 +166,7 @@ def gen_marshal(name: str,
 ok = visit_check_struct(v, errp);
 }
 ''',
- c_arg_type=arg_type.c_name())
+ c_arg_type=arg_type_c_name)
 else:
 ret += mcgen('''
 ok = visit_check_struct(v, errp);
@@ -193,7 +196,7 @@ def gen_marshal(name: str,
 ret += mcgen('''
 visit_type_%(c_arg_type)s_members(v, , NULL);
 ''',
- c_arg_type=arg_type.c_name())
+ c_arg_type=arg_type_c_name)
 
 ret += mcgen('''
 visit_end_struct(v, NULL);
-- 
2.26.2

[PATCH 00/12] qapi: static typing conversion, pt1.5

[John Snow]

Hi, this patchset enables strict optional checking in mypy for
everything we have typed so far.

In general, this patchset seeks to eliminate Optional[T] in favor of T
wherever possible. Optional types used for object properties,
function/method parameters and return values where we expect, in most
cases, to be non-None is troublesome as it requires peppering the code
with assertions about state. If and whenever possible, prefer using
non-Optional types.

Ironing out these issues allows us to be even stricter with our type
checking, which improves consistency in subclass interface types and
should make review a little nicer.

This series is based on (but does not require) the 'qapi: sphinx-autodoc
for qapi module' series.

John Snow (12):
  qapi/commands: assert arg_type is not None
  qapi/events: fix visit_event typing
  qapi/main: handle theoretical None-return from re.match()
  qapi/gen: assert that _start_if is not None in _wrap_ifcond
  qapi/gen: use './builtin' for the built-in module name
  qapi/source: Add builtin null-object sentinel
  qapi/gen: write _genc/_genh access shims
  qapi/schema: make QAPISourceInfo mandatory
  qapi/gen: move write method to QAPIGenC, make fname a str
  tests/qapi-schema: Add quotes to module name in test output
  qapi/schema: Name the builtin module "" instead of None
  qapi: enable strict-optional checks

 scripts/qapi/commands.py |  11 ++-
 scripts/qapi/events.py   |  14 +--
 scripts/qapi/gen.py  | 107 ---
 scripts/qapi/main.py |   3 +-
 scripts/qapi/mypy.ini|   1 -
 scripts/qapi/schema.py   |  33 +++
 scripts/qapi/source.py   |  20 -
 scripts/qapi/types.py|  11 +--
 scripts/qapi/visit.py|   8 +-
 tests/qapi-schema/comments.out   |   4 +-
 tests/qapi-schema/doc-good.out   |   4 +-
 tests/qapi-schema/empty.out  |   4 +-
 tests/qapi-schema/event-case.out |   4 +-
 tests/qapi-schema/include-repetition.out |   8 +-
 tests/qapi-schema/include-simple.out |   6 +-
 tests/qapi-schema/indented-expr.out  |   4 +-
 tests/qapi-schema/qapi-schema-test.out   |   8 +-
 tests/qapi-schema/test-qapi.py   |   2 +-
 18 files changed, 143 insertions(+), 109 deletions(-)

-- 
2.26.2

Re: [PATCH v13 00/19] Initial support for multi-process Qemu

[Jag Raman]

Hi,

In this series, we have incorporated the changes Marc-Andre proposed to
improve the code in v12. Following is a changelog that outlines the
differences between v12 and v13.

CHANGELOG:


[PATCH v13 02/19] multi-process: add configure and usage information
  - Dropped “tests/multiprocess/multiprocess-lsi53c895a.py” based on
feedback. We are working on acceptance tests instead.

[PATCH v13 03/19] memory: alloc RAM from file at offset
  - Changed the name of argument “start” to “map_offset”

[PATCH v13 05/19] multi-process: setup PCI host bridge for remote device
  - Renamed MULTIPROCESS_HOST as REMOTE_PCIHOST
  - Also renamed TYPE_REMOTE_HOST_DEVICE and
REMOTE_HOST_DEVICE as TYPE_REMOTE_PCIHOST and
REMOTE_PCIHOST respectively

[PATCH v13 06/19] multi-process: setup a machine object for remote device
  process
  - Renamed “remote-device” as “remote-pcihost”
  - Set a description for the machine class

[PATCH v13 07/19] multi-process: add qio channel function to transmit data
  and fds
  - Refactored qio_channel_writev_all() and qio_channel_writev_full_all()
to avoid logic duplication

[PATCH v13 08/19] multi-process: define MPQemuMsg format and transmission
  functions
  - Introduced qemu_in_iothread() helper function
  - Using ERRP_GUARD to handle input errp parameter
  - Addressed redundant typecasts to “void”
  - mpqemu_msg_send() and mpqemu_msg_send() returns true/false to
indicate success/failure
  - Added a comment to explain that the messaging protocol used would eventually
be replaced by vfio-user
  - Prefixed the command enums with “MPQEMU_CMD_”.
  - Skip calling mpqemu_read() if msg->size is zero.

[PATCH v13 09/19] multi-process: Initialize message handler in remote device
  - Check for NULL IOChannel converted to an assert, and moved outside for loop
  - Moved error handling outside for loop
  - Shutdown with SHUTDOWN_CAUSE_HOST_ERROR with error in case of failure
  - Moved exit condition into the for loop statement

[PATCH v13 10/19] multi-process: Associate fd of a PCIDevice with its object
  - Removed a separate header file and merged it into the “.c” file
  - Replaced Object properties with Object Class properties
  - Accept the file descriptor as an integer property, and check if it is a
valid socket using fd_is_socket()
  - Replaced runtime/dynamic property with a DeviceListener
  - Added a comment to explain the temporary limitation for one device per
remote process

[PATCH v13 11/19] multi-process: setup memory manager for remote device
  - Dropped the calls to memory_region_transaction_begin() and
memory_region_transaction_commit()
  - Using ERRP_GUARD to handle input errp parameter
  - Using g_autofree to automatically allocate the “name” variable
  - Moved RET_MSG command definition to the patch that starts to use it

[PATCH v13 12/19] multi-process: introduce proxy object
  - device class property is defined just above the class_init function
  - Using ERRP_GUARD to handle input errp parameter
  - Check if IOChannel is NULL before closing in the exit function, to avoid
crash
  - Early return if fd is not set
  - dev->migration_blocker is free’d by the exit function alone

[PATCH v13 13/19] multi-process: add proxy communication functions
  - Asset that mpqemu_msg_send_and_await_reply() thread is not in co-routine
context
  - Using ERRP_GUARD to handle input errp parameter

[PATCH v13 14/19] multi-process: Forward PCI config space acceses to the
  remote process
  - process_config_write() & process_config_read() take an Error** argument to
return error
  - Use FMT_pid to format messages with PID
  - Use error_prepend to avoid leak of Error*
  - Check if return value from remote indicates failure in config_op_send()
  - Dropped typecasting return values of config_op_send to void as it’s not
necessary

[PATCH v13 16/19] multi-process: Synchronize remote memory
  - Renamed RemoteMemSync as ProxyMemoryListener
  - Prefixed all related functions with “proxy_memory_listener_” for consistency
  - Simplify logic in proxy_mrs_can_merge() to return efficiently and avoid
unnecessary definition of local variable.

[PATCH v13 17/19] multi-process: create IOHUB object to handle irq
  - Replace calls to qemu_mutex_lock() and qemu_mutex_unlock() with
QEMU_LOCK_GUARD

Thank you very much!

> On Dec 14, 2020, at 12:14 AM, Jagannathan Raman  wrote:
> 
> Hello,
> 
> This is the v13 of the patchset. Thank you very much for reviewing v12 and
> sharing your feedback.
> 
> We have addressed all the comments from the v12 review except for the
> following two items, which we will be addressing in subsequent patches:
> - Prefix log messages with PID in the logging subsystem.
> - Refactor vfio-user and multi-process code to avoid logic duplication.
> 
> To touch upon the history of this project, we posted the Proof Of Concept
> patches before the BoF session in 2018. 

[PATCH 3/3] [DO-NOT-MERGE] docs: enable sphinx-autodoc for scripts/qapi

[John Snow]

This is just POC to prove that the docstrings, where they are written,
are correct to some minimum standard. It is included here for
reviewing/testing convenience.

Signed-off-by: John Snow 
---
 docs/conf.py  |  3 ++-
 docs/devel/index.rst  |  1 +
 docs/devel/python/index.rst   |  7 +++
 docs/devel/python/qapi.commands.rst   |  7 +++
 docs/devel/python/qapi.common.rst |  7 +++
 docs/devel/python/qapi.error.rst  |  7 +++
 docs/devel/python/qapi.events.rst |  7 +++
 docs/devel/python/qapi.expr.rst   |  7 +++
 docs/devel/python/qapi.gen.rst|  7 +++
 docs/devel/python/qapi.introspect.rst |  7 +++
 docs/devel/python/qapi.main.rst   |  7 +++
 docs/devel/python/qapi.parser.rst |  8 
 docs/devel/python/qapi.rst| 26 ++
 docs/devel/python/qapi.schema.rst |  7 +++
 docs/devel/python/qapi.source.rst |  7 +++
 docs/devel/python/qapi.types.rst  |  7 +++
 docs/devel/python/qapi.visit.rst  |  7 +++
 17 files changed, 128 insertions(+), 1 deletion(-)
 create mode 100644 docs/devel/python/index.rst
 create mode 100644 docs/devel/python/qapi.commands.rst
 create mode 100644 docs/devel/python/qapi.common.rst
 create mode 100644 docs/devel/python/qapi.error.rst
 create mode 100644 docs/devel/python/qapi.events.rst
 create mode 100644 docs/devel/python/qapi.expr.rst
 create mode 100644 docs/devel/python/qapi.gen.rst
 create mode 100644 docs/devel/python/qapi.introspect.rst
 create mode 100644 docs/devel/python/qapi.main.rst
 create mode 100644 docs/devel/python/qapi.parser.rst
 create mode 100644 docs/devel/python/qapi.rst
 create mode 100644 docs/devel/python/qapi.schema.rst
 create mode 100644 docs/devel/python/qapi.source.rst
 create mode 100644 docs/devel/python/qapi.types.rst
 create mode 100644 docs/devel/python/qapi.visit.rst

diff --git a/docs/conf.py b/docs/conf.py
index d0a8f78f6ead..f39d417db2ff 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -70,7 +70,8 @@
 # Add any Sphinx extension module names here, as strings. They can be
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
 # ones.
-extensions = ['kerneldoc', 'qmp_lexer', 'hxtool', 'depfile', 'qapidoc']
+extensions = ['kerneldoc', 'qmp_lexer', 'hxtool',
+  'depfile', 'qapidoc', 'sphinx.ext.autodoc']
 
 # Add any paths that contain templates here, relative to this directory.
 templates_path = ['_templates']
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
index f10ed77e4c09..fffc49c8cb95 100644
--- a/docs/devel/index.rst
+++ b/docs/devel/index.rst
@@ -35,3 +35,4 @@ Contents:
clocks
qom
block-coroutine-wrapper
+   python/index
diff --git a/docs/devel/python/index.rst b/docs/devel/python/index.rst
new file mode 100644
index ..31c470154b33
--- /dev/null
+++ b/docs/devel/python/index.rst
@@ -0,0 +1,7 @@
+qapi
+
+
+.. toctree::
+   :maxdepth: 4
+
+   qapi
diff --git a/docs/devel/python/qapi.commands.rst 
b/docs/devel/python/qapi.commands.rst
new file mode 100644
index ..018f7b08a9c0
--- /dev/null
+++ b/docs/devel/python/qapi.commands.rst
@@ -0,0 +1,7 @@
+qapi.commands module
+
+
+.. automodule:: qapi.commands
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/docs/devel/python/qapi.common.rst 
b/docs/devel/python/qapi.common.rst
new file mode 100644
index ..128a90d74be6
--- /dev/null
+++ b/docs/devel/python/qapi.common.rst
@@ -0,0 +1,7 @@
+qapi.common module
+==
+
+.. automodule:: qapi.common
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/docs/devel/python/qapi.error.rst b/docs/devel/python/qapi.error.rst
new file mode 100644
index ..980e32b63de2
--- /dev/null
+++ b/docs/devel/python/qapi.error.rst
@@ -0,0 +1,7 @@
+qapi.error module
+=
+
+.. automodule:: qapi.error
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/docs/devel/python/qapi.events.rst 
b/docs/devel/python/qapi.events.rst
new file mode 100644
index ..1fce85b044ef
--- /dev/null
+++ b/docs/devel/python/qapi.events.rst
@@ -0,0 +1,7 @@
+qapi.events module
+==
+
+.. automodule:: qapi.events
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/docs/devel/python/qapi.expr.rst b/docs/devel/python/qapi.expr.rst
new file mode 100644
index ..0660270629cd
--- /dev/null
+++ b/docs/devel/python/qapi.expr.rst
@@ -0,0 +1,7 @@
+qapi.expr module
+
+
+.. automodule:: qapi.expr
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/docs/devel/python/qapi.gen.rst b/docs/devel/python/qapi.gen.rst
new file mode 100644
index ..7b495fd4bf22
--- /dev/null
+++ b/docs/devel/python/qapi.gen.rst
@@ -0,0 +1,7 @@
+qapi.gen module
+===
+
+.. automodule:: qapi.gen
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff 

[PATCH 2/3] [DO-NOT-MERGE] docs/sphinx: change default role to "any"

[John Snow]

This interprets single-backtick syntax in all of our Sphinx docs as a
cross-reference to *something*, including Python symbols.

Signed-off-by: John Snow 
---
 docs/conf.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/conf.py b/docs/conf.py
index d40d8ff37bab..d0a8f78f6ead 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -84,6 +84,9 @@
 # The master toctree document.
 master_doc = 'index'
 
+# Interpret `this` to be a cross-reference to "anything".
+default_role = 'any'
+
 # General information about the project.
 project = u'QEMU'
 copyright = u'2020, The QEMU Project Developers'
-- 
2.26.2

[PATCH 0/3] qapi: sphinx-autodoc for qapi module

[John Snow]

Merely a testing pre-requisite to prove consistency for docstrings in
QAPI refactors, not intended for review or merge.

John Snow (3):
  [DO-NOT-MERGE] docs: replace single backtick (`) with double-backtick
(``)
  [DO-NOT-MERGE] docs/sphinx: change default role to "any"
  [DO-NOT-MERGE] docs: enable sphinx-autodoc for scripts/qapi

 docs/conf.py   |   6 +-
 docs/devel/build-system.rst| 148 -
 docs/devel/index.rst   |   1 +
 docs/devel/migration.rst   |  59 +-
 docs/devel/python/index.rst|   7 ++
 docs/devel/python/qapi.commands.rst|   7 ++
 docs/devel/python/qapi.common.rst  |   7 ++
 docs/devel/python/qapi.error.rst   |   7 ++
 docs/devel/python/qapi.events.rst  |   7 ++
 docs/devel/python/qapi.expr.rst|   7 ++
 docs/devel/python/qapi.gen.rst |   7 ++
 docs/devel/python/qapi.introspect.rst  |   7 ++
 docs/devel/python/qapi.main.rst|   7 ++
 docs/devel/python/qapi.parser.rst  |   8 ++
 docs/devel/python/qapi.rst |  26 +
 docs/devel/python/qapi.schema.rst  |   7 ++
 docs/devel/python/qapi.source.rst  |   7 ++
 docs/devel/python/qapi.types.rst   |   7 ++
 docs/devel/python/qapi.visit.rst   |   7 ++
 docs/devel/tcg-plugins.rst |  14 +--
 docs/devel/testing.rst |   2 +-
 docs/interop/live-block-operations.rst |   4 +-
 docs/system/arm/cpu-features.rst   | 110 +-
 docs/system/arm/nuvoton.rst|   2 +-
 docs/system/arm/sbsa.rst   |   4 +-
 docs/system/cpu-hotplug.rst|   2 +-
 docs/system/s390x/protvirt.rst |  10 +-
 qapi/block-core.json   |   4 +-
 28 files changed, 312 insertions(+), 179 deletions(-)
 create mode 100644 docs/devel/python/index.rst
 create mode 100644 docs/devel/python/qapi.commands.rst
 create mode 100644 docs/devel/python/qapi.common.rst
 create mode 100644 docs/devel/python/qapi.error.rst
 create mode 100644 docs/devel/python/qapi.events.rst
 create mode 100644 docs/devel/python/qapi.expr.rst
 create mode 100644 docs/devel/python/qapi.gen.rst
 create mode 100644 docs/devel/python/qapi.introspect.rst
 create mode 100644 docs/devel/python/qapi.main.rst
 create mode 100644 docs/devel/python/qapi.parser.rst
 create mode 100644 docs/devel/python/qapi.rst
 create mode 100644 docs/devel/python/qapi.schema.rst
 create mode 100644 docs/devel/python/qapi.source.rst
 create mode 100644 docs/devel/python/qapi.types.rst
 create mode 100644 docs/devel/python/qapi.visit.rst

-- 
2.26.2

[PATCH 1/3] [DO-NOT-MERGE] docs: replace single backtick (`) with double-backtick (``)

[John Snow]

The single backtick in ReST is the "default role". Currently, Sphinx's
default role is called "content". Sphinx suggests you can use the "Any"
role instead to turn any single-backtick enclosed item into a
cross-reference.

Before we do that, though, we'll need to turn all existing usages of the
"content" role to inline verbatim markup by using double backticks
instead.

Signed-off-by: John Snow 
---
 docs/devel/build-system.rst| 148 -
 docs/devel/migration.rst   |  59 +-
 docs/devel/tcg-plugins.rst |  14 +--
 docs/devel/testing.rst |   2 +-
 docs/interop/live-block-operations.rst |   4 +-
 docs/system/arm/cpu-features.rst   | 110 +-
 docs/system/arm/nuvoton.rst|   2 +-
 docs/system/arm/sbsa.rst   |   4 +-
 docs/system/cpu-hotplug.rst|   2 +-
 docs/system/s390x/protvirt.rst |  10 +-
 qapi/block-core.json   |   4 +-
 11 files changed, 181 insertions(+), 178 deletions(-)

diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst
index 31f4dced2a08..a4e006ff4804 100644
--- a/docs/devel/build-system.rst
+++ b/docs/devel/build-system.rst
@@ -53,14 +53,14 @@ following tasks:
  - Add a Meson build option to meson_options.txt.
 
  - Add support to the command line arg parser to handle any new
-   `--enable-XXX`/`--disable-XXX` flags required by the feature.
+   ``--enable-XXX``/``--disable-XXX`` flags required by the feature.
 
  - Add information to the help output message to report on the new
feature flag.
 
  - Add code to perform the actual feature check.
 
- - Add code to include the feature status in `config-host.h`
+ - Add code to include the feature status in ``config-host.h``
 
  - Add code to print out the feature status in the configure summary
upon completion.
@@ -116,51 +116,51 @@ Helper functions
 The configure script provides a variety of helper functions to assist
 developers in checking for system features:
 
-`do_cc $ARGS...`
+``do_cc $ARGS...``
Attempt to run the system C compiler passing it $ARGS...
 
-`do_cxx $ARGS...`
+``do_cxx $ARGS...``
Attempt to run the system C++ compiler passing it $ARGS...
 
-`compile_object $CFLAGS`
+``compile_object $CFLAGS``
Attempt to compile a test program with the system C compiler using
$CFLAGS. The test program must have been previously written to a file
-   called $TMPC.  The replacement in Meson is the compiler object `cc`,
-   which has methods such as `cc.compiles()`,
-   `cc.check_header()`, `cc.has_function()`.
+   called $TMPC.  The replacement in Meson is the compiler object ``cc``,
+   which has methods such as ``cc.compiles()``,
+   ``cc.check_header()``, ``cc.has_function()``.
 
-`compile_prog $CFLAGS $LDFLAGS`
+``compile_prog $CFLAGS $LDFLAGS``
Attempt to compile a test program with the system C compiler using
$CFLAGS and link it with the system linker using $LDFLAGS. The test
program must have been previously written to a file called $TMPC.
-   The replacement in Meson is `cc.find_library()` and `cc.links()`.
+   The replacement in Meson is ``cc.find_library()`` and ``cc.links()``.
 
-`has $COMMAND`
+``has $COMMAND``
Determine if $COMMAND exists in the current environment, either as a
shell builtin, or executable binary, returning 0 on success.  The
-   replacement in Meson is `find_program()`.
+   replacement in Meson is ``find_program()``.
 
-`check_define $NAME`
+``check_define $NAME``
Determine if the macro $NAME is defined by the system C compiler
 
-`check_include $NAME`
+``check_include $NAME``
Determine if the include $NAME file is available to the system C
-   compiler.  The replacement in Meson is `cc.has_header()`.
+   compiler.  The replacement in Meson is ``cc.has_header()``.
 
-`write_c_skeleton`
+``write_c_skeleton``
Write a minimal C program main() function to the temporary file
indicated by $TMPC
 
-`feature_not_found $NAME $REMEDY`
+``feature_not_found $NAME $REMEDY``
Print a message to stderr that the feature $NAME was not available
on the system, suggesting the user try $REMEDY to address the
problem.
 
-`error_exit $MESSAGE $MORE...`
+``error_exit $MESSAGE $MORE...``
Print $MESSAGE to stderr, followed by $MORE... and then exit from the
configure script with non-zero status
 
-`query_pkg_config $ARGS...`
+``query_pkg_config $ARGS...``
Run pkg-config passing it $ARGS. If QEMU is doing a static build,
then --static will be automatically added to $ARGS
 
@@ -187,7 +187,7 @@ process for:
 
 4) other data files, such as icons or desktop files
 
-All executables are built by default, except for some `contrib/`
+All executables are built by default, except for some ``contrib/``
 binaries that are known to fail to build on some platforms (for example
 32-bit or big-endian platforms).  Tests are also built by default,
 though that might change in the future.
@@ -195,14 +195,14 

Re: [PATCH v1 1/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

[Philippe Mathieu-Daudé]

On 12/14/20 11:21 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" 
> 
> Correct the indexing into s->cpu_ctlr for vCPUs.
> 

Fixes: cbe1282b568 ("intc/arm_gic: Implement gic_update_virt() function")

LGTM but better double-check with GIC specialist ;)
Reviewed-by: Philippe Mathieu-Daudé 

> Signed-off-by: Edgar E. Iglesias 
> ---
>  hw/intc/arm_gic.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index c60dc6b5e6..af41e2fb44 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -141,6 +141,8 @@ static inline void gic_get_best_virq(GICState *s, int cpu,
>  static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
>  int group_mask)
>  {
> +int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
> +
>  if (!virt && !(s->ctlr & group_mask)) {
>  return false;
>  }
> @@ -149,7 +151,7 @@ static inline bool gic_irq_signaling_enabled(GICState *s, 
> int cpu, bool virt,
>  return false;
>  }
>  
> -if (!(s->cpu_ctlr[cpu] & group_mask)) {
> +if (!(s->cpu_ctlr[cpu_iface] & group_mask)) {
>  return false;
>  }
>  
> 

[PATCH v1 1/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" 

Correct the indexing into s->cpu_ctlr for vCPUs.

Signed-off-by: Edgar E. Iglesias 
---
 hw/intc/arm_gic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c60dc6b5e6..af41e2fb44 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -141,6 +141,8 @@ static inline void gic_get_best_virq(GICState *s, int cpu,
 static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
 int group_mask)
 {
+int cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
+
 if (!virt && !(s->ctlr & group_mask)) {
 return false;
 }
@@ -149,7 +151,7 @@ static inline bool gic_irq_signaling_enabled(GICState *s, 
int cpu, bool virt,
 return false;
 }
 
-if (!(s->cpu_ctlr[cpu] & group_mask)) {
+if (!(s->cpu_ctlr[cpu_iface] & group_mask)) {
 return false;
 }
 
-- 
2.25.1

Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops

[Eduardo Habkost]

On Mon, Dec 14, 2020 at 10:56:13PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Claudio, Eduardo.
> 
> On 12/14/20 8:10 PM, Eduardo Habkost wrote:
> > On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote:
> >> From: Eduardo Habkost 
> >>
> >> since tcg_cpu_ops.h is only included in cpu.h,
> >> and as a standalone header it is not really useful,
> >> as tcg_cpu_ops.h starts requiring cpu.h defines,
> >> enums, etc, as well as (later on in the series),
> >> additional definitions coming from memattr.h.
> >>
> >> Therefore rename it to tcg_cpu_ops.h.inc, to warn
> >> any potential user that this file is not a standalone
> >> header, but rather a partition of cpu.h that is
> >> included conditionally if CONFIG_TCG is true.
> > 
> > What's the benefit of moving definitions to a separate file, if
> > the new file is not a standalone header?
> 
> Claudio, I haven't been following every respin. If you did that
> change just to please me then the circular dependency remarked by
> Richard, then if it simplify the series I'm OK if you have to
> remove the includes.
> 
> Eduardo, if you are happy with patches 1-8 (x86 specific), maybe
> you can queue them already. The rest is more TCG generic and
> will likely go via Richard/Paolo trees IMO.

Patches 01-06 are queued.  Patches 07 and 08 need review.

-- 
Eduardo

[PATCH v1 0/1] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" 

Hi,

Found this while debugging an issue with lockups during boot of
Linux on Xen.

In the particular setup, I'm running without EL3 firmware so group0
interrupts are disabled on the physical interface and enabled on the
virtual interface.

Looks like we're checking the wrong CPU_CTLR reg for vCPUs. This fixes
the problem on my side.

Cheers,
Edgar

Edgar E. Iglesias (1):
  intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

 hw/intc/arm_gic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

-- 
2.25.1

Re: [PATCH v4 11/43] tcg: Adjust tcg_out_label for const

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> Simplify the arguments to always use s->code_ptr instead of
> take it as an argument.  That makes it easy to ensure that
> the value_ptr is always the rx version.
> 
> Signed-off-by: Richard Henderson 
> ---
>  tcg/tcg.c |  6 +++---
>  tcg/i386/tcg-target.c.inc | 10 +-
>  2 files changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v4 15/43] tcg: Make tb arg to synchronize_from_tb const

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
> 
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/hw/core/cpu.h   | 3 ++-
>  target/arm/cpu.c| 3 ++-
>  target/avr/cpu.c| 3 ++-
>  target/hppa/cpu.c   | 3 ++-
>  target/i386/cpu.c   | 3 ++-
>  target/microblaze/cpu.c | 3 ++-
>  target/mips/cpu.c   | 3 ++-
>  target/riscv/cpu.c  | 3 ++-
>  target/rx/cpu.c | 3 ++-
>  target/sh4/cpu.c| 3 ++-
>  target/sparc/cpu.c  | 3 ++-
>  target/tricore/cpu.c| 2 +-
>  12 files changed, 23 insertions(+), 12 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

[PATCH v3 4/4] target/s390x: Improve SUB LOGICAL WITH BORROW

[Richard Henderson]

Now that SUB LOGICAL outputs borrow, we can use that as input directly.
It also means we can re-use CC_OP_SUBU and produce an output borrow
directly from SUB LOGICAL WITH BORROW.

Reviewed-by: David Hildenbrand 
Signed-off-by: Richard Henderson 
---
 target/s390x/internal.h|  2 -
 target/s390x/cc_helper.c   | 32 
 target/s390x/helper.c  |  2 -
 target/s390x/translate.c   | 76 +-
 target/s390x/insn-data.def |  8 ++--
 5 files changed, 46 insertions(+), 74 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 4077047494..11515bb617 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -172,14 +172,12 @@ enum cc_op {
 
 CC_OP_ADD_64,   /* overflow on add (64bit) */
 CC_OP_SUB_64,   /* overflow on subtraction (64bit) */
-CC_OP_SUBB_64,  /* overflow on unsigned sub-borrow (64bit) */
 CC_OP_ABS_64,   /* sign eval on abs (64bit) */
 CC_OP_NABS_64,  /* sign eval on nabs (64bit) */
 CC_OP_MULS_64,  /* overflow on signed multiply (64bit) */
 
 CC_OP_ADD_32,   /* overflow on add (32bit) */
 CC_OP_SUB_32,   /* overflow on subtraction (32bit) */
-CC_OP_SUBB_32,  /* overflow on unsigned sub-borrow (32bit) */
 CC_OP_ABS_32,   /* sign eval on abs (64bit) */
 CC_OP_NABS_32,  /* sign eval on nabs (64bit) */
 CC_OP_MULS_32,  /* overflow on signed multiply (32bit) */
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index c7728d1225..e7039d0d18 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -164,19 +164,6 @@ static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2, 
int64_t ar)
 }
 }
 
-static uint32_t cc_calc_subb_64(uint64_t a1, uint64_t a2, uint64_t ar)
-{
-int borrow_out;
-
-if (ar != a1 - a2) {   /* difference means borrow-in */
-borrow_out = (a2 >= a1);
-} else {
-borrow_out = (a2 > a1);
-}
-
-return (ar != 0) + 2 * !borrow_out;
-}
-
 static uint32_t cc_calc_abs_64(int64_t dst)
 {
 if ((uint64_t)dst == 0x8000ULL) {
@@ -237,19 +224,6 @@ static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2, 
int32_t ar)
 }
 }
 
-static uint32_t cc_calc_subb_32(uint32_t a1, uint32_t a2, uint32_t ar)
-{
-int borrow_out;
-
-if (ar != a1 - a2) {   /* difference means borrow-in */
-borrow_out = (a2 >= a1);
-} else {
-borrow_out = (a2 > a1);
-}
-
-return (ar != 0) + 2 * !borrow_out;
-}
-
 static uint32_t cc_calc_abs_32(int32_t dst)
 {
 if ((uint32_t)dst == 0x8000UL) {
@@ -450,9 +424,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_SUB_64:
 r =  cc_calc_sub_64(src, dst, vr);
 break;
-case CC_OP_SUBB_64:
-r =  cc_calc_subb_64(src, dst, vr);
-break;
 case CC_OP_ABS_64:
 r =  cc_calc_abs_64(dst);
 break;
@@ -472,9 +443,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_SUB_32:
 r =  cc_calc_sub_32(src, dst, vr);
 break;
-case CC_OP_SUBB_32:
-r =  cc_calc_subb_32(src, dst, vr);
-break;
 case CC_OP_ABS_32:
 r =  cc_calc_abs_32(dst);
 break;
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index fa3aa500e5..7678994feb 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -405,12 +405,10 @@ const char *cc_name(enum cc_op cc_op)
 [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 [CC_OP_ADD_64]= "CC_OP_ADD_64",
 [CC_OP_SUB_64]= "CC_OP_SUB_64",
-[CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 [CC_OP_ABS_64]= "CC_OP_ABS_64",
 [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 [CC_OP_ADD_32]= "CC_OP_ADD_32",
 [CC_OP_SUB_32]= "CC_OP_SUB_32",
-[CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 [CC_OP_ABS_32]= "CC_OP_ABS_32",
 [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 [CC_OP_COMP_32]   = "CC_OP_COMP_32",
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 40add1df1f..3d5c0d6106 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -601,10 +601,8 @@ static void gen_op_calc_cc(DisasContext *s)
 /* FALLTHRU */
 case CC_OP_ADD_64:
 case CC_OP_SUB_64:
-case CC_OP_SUBB_64:
 case CC_OP_ADD_32:
 case CC_OP_SUB_32:
-case CC_OP_SUBB_32:
 local_cc_op = tcg_const_i32(s->cc_op);
 break;
 case CC_OP_CONST0:
@@ -663,10 +661,8 @@ static void gen_op_calc_cc(DisasContext *s)
 break;
 case CC_OP_ADD_64:
 case CC_OP_SUB_64:
-case CC_OP_SUBB_64:
 case CC_OP_ADD_32:
 case CC_OP_SUB_32:
-case CC_OP_SUBB_32:
 /* 3 arguments */
 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
 break;
@@ -4746,29 +4742,51 @@ 

[PATCH v3 3/4] target/s390x: Improve cc computation for SUBTRACT LOGICAL

[Richard Henderson]

The resulting cc is only dependent on the result and the carry-out.
Carry-out and borrow-out are inverses, so are trivially converted.
With tcg ops, it is easier to compute borrow-out than carry-out, so
save result and borrow-out rather than the inputs.

Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly
into cc_src.  Borrow-out for 32-bit inputs is had via extraction
from a normal 64-bit sub (with zero-extended inputs).

Reviewed-by: David Hildenbrand 
Signed-off-by: Richard Henderson 
---
 target/s390x/internal.h|  3 +--
 target/s390x/cc_helper.c   | 40 ++-
 target/s390x/helper.c  |  3 +--
 target/s390x/translate.c   | 55 +++---
 target/s390x/insn-data.def | 24 -
 5 files changed, 43 insertions(+), 82 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index f5f3ae063e..4077047494 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -161,6 +161,7 @@ enum cc_op {
 
 CC_OP_NZ,   /* env->cc_dst != 0 */
 CC_OP_ADDU, /* dst != 0, src = carry out (0,1) */
+CC_OP_SUBU, /* dst != 0, src = borrow out (0,-1) */
 
 CC_OP_LTGT_32,  /* signed less/greater than (32bit) */
 CC_OP_LTGT_64,  /* signed less/greater than (64bit) */
@@ -171,7 +172,6 @@ enum cc_op {
 
 CC_OP_ADD_64,   /* overflow on add (64bit) */
 CC_OP_SUB_64,   /* overflow on subtraction (64bit) */
-CC_OP_SUBU_64,  /* overflow on unsigned subtraction (64bit) */
 CC_OP_SUBB_64,  /* overflow on unsigned sub-borrow (64bit) */
 CC_OP_ABS_64,   /* sign eval on abs (64bit) */
 CC_OP_NABS_64,  /* sign eval on nabs (64bit) */
@@ -179,7 +179,6 @@ enum cc_op {
 
 CC_OP_ADD_32,   /* overflow on add (32bit) */
 CC_OP_SUB_32,   /* overflow on subtraction (32bit) */
-CC_OP_SUBU_32,  /* overflow on unsigned subtraction (32bit) */
 CC_OP_SUBB_32,  /* overflow on unsigned sub-borrow (32bit) */
 CC_OP_ABS_32,   /* sign eval on abs (64bit) */
 CC_OP_NABS_32,  /* sign eval on nabs (64bit) */
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index cd2c5c4b39..c7728d1225 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -129,6 +129,11 @@ static uint32_t cc_calc_addu(uint64_t carry_out, uint64_t 
result)
 return (result != 0) + 2 * carry_out;
 }
 
+static uint32_t cc_calc_subu(uint64_t borrow_out, uint64_t result)
+{
+return cc_calc_addu(borrow_out + 1, result);
+}
+
 static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, int64_t ar)
 {
 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@@ -159,19 +164,6 @@ static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2, 
int64_t ar)
 }
 }
 
-static uint32_t cc_calc_subu_64(uint64_t a1, uint64_t a2, uint64_t ar)
-{
-if (ar == 0) {
-return 2;
-} else {
-if (a2 > a1) {
-return 1;
-} else {
-return 3;
-}
-}
-}
-
 static uint32_t cc_calc_subb_64(uint64_t a1, uint64_t a2, uint64_t ar)
 {
 int borrow_out;
@@ -245,19 +237,6 @@ static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2, 
int32_t ar)
 }
 }
 
-static uint32_t cc_calc_subu_32(uint32_t a1, uint32_t a2, uint32_t ar)
-{
-if (ar == 0) {
-return 2;
-} else {
-if (a2 > a1) {
-return 1;
-} else {
-return 3;
-}
-}
-}
-
 static uint32_t cc_calc_subb_32(uint32_t a1, uint32_t a2, uint32_t ar)
 {
 int borrow_out;
@@ -462,15 +441,15 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_ADDU:
 r = cc_calc_addu(src, dst);
 break;
+case CC_OP_SUBU:
+r = cc_calc_subu(src, dst);
+break;
 case CC_OP_ADD_64:
 r =  cc_calc_add_64(src, dst, vr);
 break;
 case CC_OP_SUB_64:
 r =  cc_calc_sub_64(src, dst, vr);
 break;
-case CC_OP_SUBU_64:
-r =  cc_calc_subu_64(src, dst, vr);
-break;
 case CC_OP_SUBB_64:
 r =  cc_calc_subb_64(src, dst, vr);
 break;
@@ -493,9 +472,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_SUB_32:
 r =  cc_calc_sub_32(src, dst, vr);
 break;
-case CC_OP_SUBU_32:
-r =  cc_calc_subu_32(src, dst, vr);
-break;
 case CC_OP_SUBB_32:
 r =  cc_calc_subb_32(src, dst, vr);
 break;
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 4f4561bc64..fa3aa500e5 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -396,6 +396,7 @@ const char *cc_name(enum cc_op cc_op)
 [CC_OP_STATIC]= "CC_OP_STATIC",
 [CC_OP_NZ]= "CC_OP_NZ",
 [CC_OP_ADDU]  = "CC_OP_ADDU",
+[CC_OP_SUBU]  

Re: [PATCH v4 10/43] tcg: Adjust tcg_out_call for const

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> We must change all targets at once, since all must match
> the declaration in tcg.c.
> 
> Signed-off-by: Richard Henderson 
> ---
>  tcg/tcg.c| 2 +-
>  tcg/aarch64/tcg-target.c.inc | 2 +-
>  tcg/arm/tcg-target.c.inc | 2 +-
>  tcg/i386/tcg-target.c.inc| 4 ++--
>  tcg/mips/tcg-target.c.inc| 6 +++---
>  tcg/ppc/tcg-target.c.inc | 8 
>  tcg/riscv/tcg-target.c.inc   | 6 +++---
>  tcg/s390/tcg-target.c.inc| 2 +-
>  tcg/sparc/tcg-target.c.inc   | 4 ++--
>  tcg/tci/tcg-target.c.inc | 2 +-
>  10 files changed, 19 insertions(+), 19 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

[PATCH v3 1/4] target/s390x: Improve cc computation for ADD LOGICAL

[Richard Henderson]

The resulting cc is only dependent on the result and the
carry-out.  So save those things rather than the inputs.

Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly
into cc_src.  Carry-out for 32-bit inputs is had via extraction
from a normal 64-bit add (with zero-extended inputs).

Reviewed-by: David Hildenbrand 
Signed-off-by: Richard Henderson 
---
 target/s390x/internal.h|   4 +-
 target/s390x/cc_helper.c   |  25 -
 target/s390x/helper.c  |   3 +-
 target/s390x/translate.c   | 103 -
 target/s390x/insn-data.def |  36 ++---
 5 files changed, 97 insertions(+), 74 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 64602660ae..55c5442102 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -160,6 +160,8 @@ enum cc_op {
 CC_OP_STATIC,   /* CC value is env->cc_op */
 
 CC_OP_NZ,   /* env->cc_dst != 0 */
+CC_OP_ADDU, /* dst != 0, src = carry out (0,1) */
+
 CC_OP_LTGT_32,  /* signed less/greater than (32bit) */
 CC_OP_LTGT_64,  /* signed less/greater than (64bit) */
 CC_OP_LTUGTU_32,/* unsigned less/greater than (32bit) */
@@ -168,7 +170,6 @@ enum cc_op {
 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
 
 CC_OP_ADD_64,   /* overflow on add (64bit) */
-CC_OP_ADDU_64,  /* overflow on unsigned add (64bit) */
 CC_OP_ADDC_64,  /* overflow on unsigned add-carry (64bit) */
 CC_OP_SUB_64,   /* overflow on subtraction (64bit) */
 CC_OP_SUBU_64,  /* overflow on unsigned subtraction (64bit) */
@@ -178,7 +179,6 @@ enum cc_op {
 CC_OP_MULS_64,  /* overflow on signed multiply (64bit) */
 
 CC_OP_ADD_32,   /* overflow on add (32bit) */
-CC_OP_ADDU_32,  /* overflow on unsigned add (32bit) */
 CC_OP_ADDC_32,  /* overflow on unsigned add-carry (32bit) */
 CC_OP_SUB_32,   /* overflow on subtraction (32bit) */
 CC_OP_SUBU_32,  /* overflow on unsigned subtraction (32bit) */
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 5432aeeed4..59da4d1cc2 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -123,6 +123,12 @@ static uint32_t cc_calc_nz(uint64_t dst)
 return !!dst;
 }
 
+static uint32_t cc_calc_addu(uint64_t carry_out, uint64_t result)
+{
+g_assert(carry_out <= 1);
+return (result != 0) + 2 * carry_out;
+}
+
 static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, int64_t ar)
 {
 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) {
@@ -138,11 +144,6 @@ static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, 
int64_t ar)
 }
 }
 
-static uint32_t cc_calc_addu_64(uint64_t a1, uint64_t a2, uint64_t ar)
-{
-return (ar != 0) + 2 * (ar < a1);
-}
-
 static uint32_t cc_calc_addc_64(uint64_t a1, uint64_t a2, uint64_t ar)
 {
 /* Recover a2 + carry_in.  */
@@ -239,11 +240,6 @@ static uint32_t cc_calc_add_32(int32_t a1, int32_t a2, 
int32_t ar)
 }
 }
 
-static uint32_t cc_calc_addu_32(uint32_t a1, uint32_t a2, uint32_t ar)
-{
-return (ar != 0) + 2 * (ar < a1);
-}
-
 static uint32_t cc_calc_addc_32(uint32_t a1, uint32_t a2, uint32_t ar)
 {
 /* Recover a2 + carry_in.  */
@@ -483,12 +479,12 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_NZ:
 r =  cc_calc_nz(dst);
 break;
+case CC_OP_ADDU:
+r = cc_calc_addu(src, dst);
+break;
 case CC_OP_ADD_64:
 r =  cc_calc_add_64(src, dst, vr);
 break;
-case CC_OP_ADDU_64:
-r =  cc_calc_addu_64(src, dst, vr);
-break;
 case CC_OP_ADDC_64:
 r =  cc_calc_addc_64(src, dst, vr);
 break;
@@ -517,9 +513,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_ADD_32:
 r =  cc_calc_add_32(src, dst, vr);
 break;
-case CC_OP_ADDU_32:
-r =  cc_calc_addu_32(src, dst, vr);
-break;
 case CC_OP_ADDC_32:
 r =  cc_calc_addc_32(src, dst, vr);
 break;
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index b877690845..db87a62a57 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -395,6 +395,7 @@ const char *cc_name(enum cc_op cc_op)
 [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 [CC_OP_STATIC]= "CC_OP_STATIC",
 [CC_OP_NZ]= "CC_OP_NZ",
+[CC_OP_ADDU]  = "CC_OP_ADDU",
 [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
@@ -402,7 +403,6 @@ const char *cc_name(enum cc_op cc_op)
 [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 [CC_OP_ADD_64]= "CC_OP_ADD_64",
-[CC_OP_ADDU_64]   = 

Re: [PATCH v4 14/43] tcg: Make DisasContextBase.tb const

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> There is nothing within the translators that ought to be
> changing the TranslationBlock data, so make it const.
> 
> This does not actually use the read-only copy of the
> data structure that exists within the rx region.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/exec/gen-icount.h  | 4 ++--
>  include/exec/translator.h  | 2 +-
>  include/tcg/tcg-op.h   | 2 +-
>  accel/tcg/translator.c | 4 ++--
>  target/arm/translate-a64.c | 2 +-
>  tcg/tcg-op.c   | 2 +-
>  6 files changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

[PATCH v3 2/4] target/s390x: Improve ADD LOGICAL WITH CARRY

[Richard Henderson]

Now that ADD LOGICAL outputs carry, we can use that as input directly.
It also means we can re-use CC_OP_ADDU and produce an output carry
directly from ADD LOGICAL WITH CARRY.

Reviewed-by: David Hildenbrand 
Signed-off-by: Richard Henderson 
---
 target/s390x/internal.h|  2 --
 target/s390x/cc_helper.c   | 26 ---
 target/s390x/helper.c  |  2 --
 target/s390x/translate.c   | 67 ++
 target/s390x/insn-data.def |  8 ++---
 5 files changed, 36 insertions(+), 69 deletions(-)

diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 55c5442102..f5f3ae063e 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -170,7 +170,6 @@ enum cc_op {
 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
 
 CC_OP_ADD_64,   /* overflow on add (64bit) */
-CC_OP_ADDC_64,  /* overflow on unsigned add-carry (64bit) */
 CC_OP_SUB_64,   /* overflow on subtraction (64bit) */
 CC_OP_SUBU_64,  /* overflow on unsigned subtraction (64bit) */
 CC_OP_SUBB_64,  /* overflow on unsigned sub-borrow (64bit) */
@@ -179,7 +178,6 @@ enum cc_op {
 CC_OP_MULS_64,  /* overflow on signed multiply (64bit) */
 
 CC_OP_ADD_32,   /* overflow on add (32bit) */
-CC_OP_ADDC_32,  /* overflow on unsigned add-carry (32bit) */
 CC_OP_SUB_32,   /* overflow on subtraction (32bit) */
 CC_OP_SUBU_32,  /* overflow on unsigned subtraction (32bit) */
 CC_OP_SUBB_32,  /* overflow on unsigned sub-borrow (32bit) */
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 59da4d1cc2..cd2c5c4b39 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -144,16 +144,6 @@ static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, 
int64_t ar)
 }
 }
 
-static uint32_t cc_calc_addc_64(uint64_t a1, uint64_t a2, uint64_t ar)
-{
-/* Recover a2 + carry_in.  */
-uint64_t a2c = ar - a1;
-/* Check for a2+carry_in overflow, then a1+a2c overflow.  */
-int carry_out = (a2c < a2) || (ar < a1);
-
-return (ar != 0) + 2 * carry_out;
-}
-
 static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2, int64_t ar)
 {
 if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@@ -240,16 +230,6 @@ static uint32_t cc_calc_add_32(int32_t a1, int32_t a2, 
int32_t ar)
 }
 }
 
-static uint32_t cc_calc_addc_32(uint32_t a1, uint32_t a2, uint32_t ar)
-{
-/* Recover a2 + carry_in.  */
-uint32_t a2c = ar - a1;
-/* Check for a2+carry_in overflow, then a1+a2c overflow.  */
-int carry_out = (a2c < a2) || (ar < a1);
-
-return (ar != 0) + 2 * carry_out;
-}
-
 static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2, int32_t ar)
 {
 if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) {
@@ -485,9 +465,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_ADD_64:
 r =  cc_calc_add_64(src, dst, vr);
 break;
-case CC_OP_ADDC_64:
-r =  cc_calc_addc_64(src, dst, vr);
-break;
 case CC_OP_SUB_64:
 r =  cc_calc_sub_64(src, dst, vr);
 break;
@@ -513,9 +490,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t 
cc_op,
 case CC_OP_ADD_32:
 r =  cc_calc_add_32(src, dst, vr);
 break;
-case CC_OP_ADDC_32:
-r =  cc_calc_addc_32(src, dst, vr);
-break;
 case CC_OP_SUB_32:
 r =  cc_calc_sub_32(src, dst, vr);
 break;
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index db87a62a57..4f4561bc64 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -403,14 +403,12 @@ const char *cc_name(enum cc_op cc_op)
 [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 [CC_OP_ADD_64]= "CC_OP_ADD_64",
-[CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 [CC_OP_SUB_64]= "CC_OP_SUB_64",
 [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 [CC_OP_ABS_64]= "CC_OP_ABS_64",
 [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 [CC_OP_ADD_32]= "CC_OP_ADD_32",
-[CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 [CC_OP_SUB_32]= "CC_OP_SUB_32",
 [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index b473233edf..d1d97e4696 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -600,12 +600,10 @@ static void gen_op_calc_cc(DisasContext *s)
 dummy = tcg_const_i64(0);
 /* FALLTHRU */
 case CC_OP_ADD_64:
-case CC_OP_ADDC_64:
 case CC_OP_SUB_64:
 case CC_OP_SUBU_64:
 case CC_OP_SUBB_64:
 case CC_OP_ADD_32:
-case CC_OP_ADDC_32:
 case CC_OP_SUB_32:
 case CC_OP_SUBU_32:
 case CC_OP_SUBB_32:
@@ -665,12 +663,10 @@ static void 

[PATCH v3 0/4] target/s390x: Improve carry computation

[Richard Henderson]

While testing the float128_muladd changes for s390x host,
emulating under x86_64 of course, I noticed that the code
we generate for strings of ALCGR and SLBGR is pretty awful.

I realized that we were missing a trick: the output cc is
based only on the output (result and carry) and so we don't
need to save the inputs.  And once we do that, we can use
the output carry as a direct input to the next insn.

Changes for v3:
  * Rebased.
Changes for v2:
  * Add a few more comments, and enhance the patch descriptions.


r~

Richard Henderson (4):
  target/s390x: Improve cc computation for ADD LOGICAL
  target/s390x: Improve ADD LOGICAL WITH CARRY
  target/s390x: Improve cc computation for SUBTRACT LOGICAL
  target/s390x: Improve SUB LOGICAL WITH BORROW

 target/s390x/internal.h|  11 +-
 target/s390x/cc_helper.c   | 123 +++-
 target/s390x/helper.c  |  10 +-
 target/s390x/translate.c   | 289 -
 target/s390x/insn-data.def |  76 +-
 5 files changed, 216 insertions(+), 293 deletions(-)

-- 
2.25.1

Re: [PATCH v4 24/43] disas: Push const down through host disasassembly

[Philippe Mathieu-Daudé]

Typo "disassembly" in subject?

On 12/14/20 3:02 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson 
> ---
>  include/disas/dis-asm.h | 4 ++--
>  disas.c | 4 +---
>  disas/capstone.c| 2 +-
>  3 files changed, 4 insertions(+), 6 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v4 07/43] tcg: Add in_code_gen_buffer

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> Create a function to determine if a pointer is within the buffer.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/tcg/tcg.h |  6 ++
>  accel/tcg/translate-all.c | 26 --
>  2 files changed, 14 insertions(+), 18 deletions(-)
> 
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index bb1e97b13b..e4d0ace44b 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -680,6 +680,12 @@ extern __thread TCGContext *tcg_ctx;
>  extern void *tcg_code_gen_epilogue;
>  extern TCGv_env cpu_env;
>  
> +static inline bool in_code_gen_buffer(const void *p)
> +{
> +const TCGContext *s = _init_ctx;
> +return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size;

If 'p == s->code_gen_buffer + s->code_gen_buffer_size',
is it really "in" the buffer?

> +}
> +
>  static inline size_t temp_idx(TCGTemp *ts)
>  {
>  ptrdiff_t n = ts - tcg_ctx->temps;
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 4572b4901f..744f97a717 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -392,27 +392,18 @@ void tb_destroy(TranslationBlock *tb)
>  
>  bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit)
>  {
> -TranslationBlock *tb;
> -bool r = false;
> -uintptr_t check_offset;
> -
> -/* The host_pc has to be in the region of current code buffer. If
> - * it is not we will not be able to resolve it here. The two cases
> - * where host_pc will not be correct are:
> +/*
> + * The host_pc has to be in the region of the code buffer.
> + * If it is not we will not be able to resolve it here.
> + * The two cases where host_pc will not be correct are:
>   *
>   *  - fault during translation (instruction fetch)
>   *  - fault from helper (not using GETPC() macro)
>   *
>   * Either way we need return early as we can't resolve it here.
> - *
> - * We are using unsigned arithmetic so if host_pc <
> - * tcg_init_ctx.code_gen_buffer check_offset will wrap to way
> - * above the code_gen_buffer_size
>   */
> -check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer;
> -
> -if (check_offset < tcg_init_ctx.code_gen_buffer_size) {
> -tb = tcg_tb_lookup(host_pc);
> +if (in_code_gen_buffer((const void *)host_pc)) {
> +TranslationBlock *tb = tcg_tb_lookup(host_pc);
>  if (tb) {
>  cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit);
>  if (tb_cflags(tb) & CF_NOCACHE) {
> @@ -421,11 +412,10 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t 
> host_pc, bool will_exit)
>  tcg_tb_remove(tb);
>  tb_destroy(tb);
>  }
> -r = true;
> +return true;
>  }
>  }
> -
> -return r;
> +return false;
>  }
>  
>  static void page_init(void)
> 

Re: [PATCH v4 05/43] tcg: Move tcg prologue pointer out of TCGContext

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> This value is constant across all thread-local copies of TCGContext,
> so we might as well move it out of thread-local storage.
> 
> Use the correct function pointer type, and name the variable
> tcg_qemu_tb_exec, which means that we are able to remove the
> macro that does the casting.
> 
> Replace HAVE_TCG_QEMU_TB_EXEC with CONFIG_TCG_INTERPRETER,
> as this is somewhat clearer in intent.
> 
> Reviewed-by: Alex Bennée 
> Signed-off-by: Richard Henderson 
> ---
>  include/tcg/tcg.h | 9 -
>  tcg/tcg.c | 9 -
>  tcg/tci.c | 3 ++-
>  3 files changed, 14 insertions(+), 7 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

> 
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index 8ff9dad4ef..9cc412f90c 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -621,7 +621,6 @@ struct TCGContext {
> here, because there's too much arithmetic throughout that relies
> on addition and subtraction working on bytes.  Rely on the GCC
> extension that allows arithmetic on void*.  */
> -void *code_gen_prologue;
>  void *code_gen_epilogue;
>  void *code_gen_buffer;
>  size_t code_gen_buffer_size;
> @@ -1222,11 +1221,11 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi)
>  #define TB_EXIT_IDXMAX1
>  #define TB_EXIT_REQUESTED 3
>  
> -#ifdef HAVE_TCG_QEMU_TB_EXEC
> -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
> +#ifdef CONFIG_TCG_INTERPRETER
> +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *tb_ptr);
>  #else
> -# define tcg_qemu_tb_exec(env, tb_ptr) \
> -((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
> +typedef uintptr_t tcg_prologue_fn(CPUArchState *env, void *tb_ptr);
> +extern tcg_prologue_fn *tcg_qemu_tb_exec;
>  #endif
>  
>  void tcg_register_jit(void *buf, size_t buf_size);
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 675334e844..67065c2ede 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -162,6 +162,10 @@ static TCGContext **tcg_ctxs;
>  static unsigned int n_tcg_ctxs;
>  TCGv_env cpu_env = 0;
>  
> +#ifndef CONFIG_TCG_INTERPRETER
> +tcg_prologue_fn *tcg_qemu_tb_exec;
> +#endif
> +
>  struct tcg_region_tree {
>  QemuMutex lock;
>  GTree *tree;
> @@ -1055,7 +1059,10 @@ void tcg_prologue_init(TCGContext *s)
>  s->code_ptr = buf0;
>  s->code_buf = buf0;
>  s->data_gen_ptr = NULL;
> -s->code_gen_prologue = buf0;
> +
> +#ifndef CONFIG_TCG_INTERPRETER
> +tcg_qemu_tb_exec = (tcg_prologue_fn *)buf0;
> +#endif
>  
>  /* Compute a high-water mark, at which we voluntarily flush the buffer
> and start over.  The size here is arbitrary, significantly larger
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 82039fd163..d996eb7cf8 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -475,8 +475,9 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, 
> TCGCond condition)
>  #endif
>  
>  /* Interpret pseudo code in tb. */
> -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
> +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *v_tb_ptr)
>  {
> +uint8_t *tb_ptr = v_tb_ptr;
>  tcg_target_ulong regs[TCG_TARGET_NB_REGS];
>  long tcg_temps[CPU_TEMP_BUF_NLONGS];
>  uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
> 

Re: [PATCH v4 02/43] util: Extract flush_icache_range to cacheflush.c

[Philippe Mathieu-Daudé]

On 12/14/20 3:02 PM, Richard Henderson wrote:
> This has been a tcg-specific function, but is also in use
> by hardware accelerators via physmem.c.  This can cause
> link errors when tcg is disabled.
> 
> Signed-off-by: Richard Henderson 
> ---
>  include/qemu/cacheflush.h | 24 +
>  tcg/aarch64/tcg-target.h  |  5 ---
>  tcg/arm/tcg-target.h  |  5 ---
>  tcg/i386/tcg-target.h |  4 ---
>  tcg/mips/tcg-target.h | 11 --
>  tcg/ppc/tcg-target.h  |  1 -
>  tcg/riscv/tcg-target.h|  5 ---
>  tcg/s390/tcg-target.h |  4 ---
>  tcg/sparc/tcg-target.h|  8 -
>  tcg/tci/tcg-target.h  |  4 ---
>  softmmu/physmem.c |  1 +
>  tcg/tcg.c |  1 +
>  util/cacheflush.c | 71 +++
>  MAINTAINERS   |  2 ++
>  tcg/ppc/tcg-target.c.inc  | 22 
>  util/meson.build  |  2 +-
>  16 files changed, 100 insertions(+), 70 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops

[Philippe Mathieu-Daudé]

Hi Claudio, Eduardo.

On 12/14/20 8:10 PM, Eduardo Habkost wrote:
> On Sat, Dec 12, 2020 at 04:55:23PM +0100, Claudio Fontana wrote:
>> From: Eduardo Habkost 
>>
>> since tcg_cpu_ops.h is only included in cpu.h,
>> and as a standalone header it is not really useful,
>> as tcg_cpu_ops.h starts requiring cpu.h defines,
>> enums, etc, as well as (later on in the series),
>> additional definitions coming from memattr.h.
>>
>> Therefore rename it to tcg_cpu_ops.h.inc, to warn
>> any potential user that this file is not a standalone
>> header, but rather a partition of cpu.h that is
>> included conditionally if CONFIG_TCG is true.
> 
> What's the benefit of moving definitions to a separate file, if
> the new file is not a standalone header?

Claudio, I haven't been following every respin. If you did that
change just to please me then the circular dependency remarked by
Richard, then if it simplify the series I'm OK if you have to
remove the includes.

Eduardo, if you are happy with patches 1-8 (x86 specific), maybe
you can queue them already. The rest is more TCG generic and
will likely go via Richard/Paolo trees IMO.

> 
> If moving the definitions to a separate header is going to
> require too much work, it's completely OK to keep them in cpu.h
> by now, and try to move them later.
> 
> I'm worried that the scope of this series is growing too much,
> and discussion/review of additional changes in each new version
> is preventing us from merging the original changes where we
> already had some consensus.

RE: [PATCH v5 0/4] hw/block/m25p80: Numonyx: Fix dummy cycles and check for SPI mode on cmds

[Joe Komlodi]

Hi Peter,

This series has been reviewed, but it looks like it slipped through the cracks.
Is it possible it could be merged through your tree, assuming it looks good?

Thanks!
Joe

-Original Message-
From: Qemu-devel  On Behalf 
Of Joe Komlodi
Sent: Monday, November 16, 2020 3:11 PM
To: qemu-devel@nongnu.org
Cc: Francisco Eduardo Iglesias ; alist...@alistair23.me; 
philippe.mathieu.da...@gmail.com; qemu-bl...@nongnu.org; mre...@redhat.com
Subject: [PATCH v5 0/4] hw/block/m25p80: Numonyx: Fix dummy cycles and check 
for SPI mode on cmds

Changelog:
v4 -> v5
 - 3/4: Simplify logic when changing state and checking mode.
 - 3/4: numonyx_get_mode -> numonyx_mode
 - 4/4: Reword commit message to include QIO mode.

v3 -> v4
 - 1/4: Patch changed to change names of register fields to be more accurate.
 - 1/4: Revert polarity change from v3.
 - 2/4: Added, fixes polarity of VCFG XIP mode when copied from NVCFG.
 - 3/4: Removed check_cmd_mode function, each command check is done in 
decode_new_cmd instead.
 - 3/4: Add guest error print if JEDEC read is executed in QIO or DIO mode.
 - 3/4: Don't check PP and PP4, they work regardless of mode. PP4_4 is left as 
is.
 - 3/4: Simplify get_mode function.
 - 4/4: Simplify extract_cfg_num_dummies function.
 - 4/4: Use switch statement instead of table for cycle retrieving.

v2 -> v3
 - 1/3: Added, Fixes NVCFG polarity for DIO/QIO.
 - 2/3: Added, Checks if we can execute the current command in standard/DIO/QIO 
mode.
 - 3/3: Was 1/1 in v2.  Added cycle counts for DIO/QIO mode.

v1 -> v2
 - 1/2: Change function name to be more accurate
 - 2/2: Dropped

Hi all,

The series fixes the behavior of the dummy cycle register for Numonyx flashes 
so it's closer to how hardware behaves.
It also checks if a command can be executed in the current SPI mode (standard, 
DIO, or QIO) before extracting dummy cycles for the command.

On hardware, the dummy cycles for fast read commands are set to a specific value
(8 or 10) if the register is all 0s or 1s.
If the register value isn't all 0s or 1s, then the flash expects the amount of 
cycles sent to be equal to the count in the register.

Thanks!
Joe

Joe Komlodi (4):
  hw/block/m25p80: Make Numonyx config field names more accurate
  hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx
  hw/block/m25p80: Check SPI mode before running some Numonyx commands
  hw/block/m25p80: Fix Numonyx fast read dummy cycle count

 hw/block/m25p80.c | 158 --
 1 file changed, 129 insertions(+), 29 deletions(-)

--
2.7.4

Re: [for-6.0 v5 01/13] qom: Allow optional sugar props

[Eduardo Habkost]

On Fri, Dec 04, 2020 at 04:44:03PM +1100, David Gibson wrote:
> From: Greg Kurz 
> 
> Global properties have an @optional field, which allows to apply a given
> property to a given type even if one of its subclasses doesn't support
> it. This is especially used in the compat code when dealing with the
> "disable-modern" and "disable-legacy" properties and the "virtio-pci"
> type.
> 
> Allow object_register_sugar_prop() to set this field as well.
> 
> Signed-off-by: Greg Kurz 
> Message-Id: <159738953558.377274.16617742952571083440.st...@bahia.lan>
> Signed-off-by: David Gibson 

Reviewed-by: Eduardo Habkost 

-- 
Eduardo

[PATCH] MAINTAINERS: Update my git repository URLs

[Eduardo Habkost]

I'm moving my git repositories to gitlab.com, update MAINTAINERS
to point to the correct URL.

Signed-off-by: Eduardo Habkost 
---
 MAINTAINERS | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4663c143c3..6714257cf7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -344,7 +344,7 @@ F: tests/tcg/x86_64/
 F: hw/i386/
 F: disas/i386.c
 F: docs/system/cpu-models-x86.rst.inc
-T: git https://github.com/ehabkost/qemu.git x86-next
+T: git https://gitlab.com/ehabkost/qemu.git x86-next
 
 Xtensa TCG CPUs
 M: Max Filippov 
@@ -1557,7 +1557,7 @@ F: include/hw/boards.h
 F: include/hw/core/cpu.h
 F: include/hw/cpu/cluster.h
 F: include/sysemu/numa.h
-T: git https://github.com/ehabkost/qemu.git machine-next
+T: git https://gitlab.com/ehabkost/qemu.git machine-next
 
 Xtensa Machines
 ---
@@ -2412,7 +2412,7 @@ M: Igor Mammedov 
 S: Maintained
 F: backends/hostmem*.c
 F: include/sysemu/hostmem.h
-T: git https://github.com/ehabkost/qemu.git machine-next
+T: git https://gitlab.com/ehabkost/qemu.git machine-next
 
 Cryptodev Backends
 M: Gonglei 
-- 
2.28.0

Re: [PATCH v4 01/43] tcg: Do not flush icache for interpreter

[Joelle van Dyne]

On Mon, Dec 14, 2020 at 6:02 AM Richard Henderson
 wrote:
>
> This is currently a no-op within tci/tcg-target.h, but
> is about to be moved to a more generic location.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Joelle van Dyne 

Re: [PATCH v12 00/23] i386 cleanup PART 1

[Eduardo Habkost]

On Sat, Dec 12, 2020 at 04:55:07PM +0100, Claudio Fontana wrote:
[...]
> Claudio Fontana (14):
>   i386: move kvm accel files into kvm/
>   i386: move whpx accel files into whpx/
>   i386: move hax accel files into hax/
>   i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
>   i386: move TCG accel files into tcg/
>   i386: move cpu dump out of helper.c into cpu-dump.c

I'm queueing patches 01-06 on x86-next.  Thanks!

-- 
Eduardo

Re: [PATCH] libvhost-user: add a link-static option

[Paolo Bonzini]

Il lun 14 dic 2020, 21:48 Marc-André Lureau  ha
scritto:

> Adding:
>  meson.override_dependency('glib-2.0', dependency('glib-2.0', static:
> enable_static))
>
> just before the "vhost_user = not_found..." works. Is that what you had in
> mind?
>

Why not "meson.override_dependency('glib-2.0', glib)", either there before
the vhost_user assignmeny or in meson.build where glib is assigned to?

Thanks,

Paolo

>
>
>> --
>> Marc-André Lureau
>>
>
>
> --
> Marc-André Lureau
>

Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops

[Eduardo Habkost]

On Sat, Dec 12, 2020 at 11:00:03AM +0100, Claudio Fontana wrote:
> On 12/11/20 9:02 PM, Eduardo Habkost wrote:
> > On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
> >> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
> >>> On 12/11/20 7:22 PM, Richard Henderson wrote:
>  On 12/11/20 12:15 PM, Claudio Fontana wrote:
> > Should I return this file to the original state (without the extra 
> > #includes that pretend it to be a standalone header file,
> > and call it
> >
> > tcg-cpu-ops.h.inc
> >
> > ?
> 
>  If this header can work with qemu/typedefs.h, then no, because the 
>  circularity
>  has been resolved.  Otherwise, yes.
> >>>
> >>> My editor got confused with TranslationBlock, which is why I asked
> >>> to include its declaration.
> >>>
> >>> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
> >>>
> >>> Regards,
> >>>
> >>> Phil.
> >>>
> >>
> >> Hello Philippe,
> >>
> >> ok you propose to move the existing fwd declaration of TranslationBlock 
> >> from cpu.h to qemu/typedefs.h .
> > 
> > It seems simpler to just add a
> > 
> > typedef struct TranslationBlock TranslationBlock;
> > 
> > line to tcg-cpu-ops.h.
> > 
> > Or, an even simpler solution: just use `struct TranslationBlock`
> > instead of `TranslationBlock` in the declarations being moved to
> > tcg-cpu-ops.h.
> > 
> > We don't need to move declarations to typedefs.h anymore, because
> > now the compilers we support don't warn about typedef
> > redefinitions:
> > https://lore.kernel.org/qemu-devel/20200914134636.gz1618...@habkost.net/
> > 
> > 
> >>
> >> And what about #include "exec/memattrs.h"?
> >>
> >> I assume you propose to put struct MemTxAttrs there as a fwd declaration 
> >> too,
> > 
> > This can't be done, because MemTxAttrs can't be an incomplete
> > type in the code you are moving (the methods get a MemTxAttrs
> > value, not a pointer).
> 
> 
> 
> I'm confused now on what we are trying to do: if we want the
> file to be a "proper header" or just a TCG-ops-only convenience
> split of cpu.h.

Personally, I don't see the point of creating a new header if
it's not a proper header.

> 
> I thought that we were only solving a highlighting issue in some editor 
> (Philippe),
> and I wonder if these changes in qemu/typedef.h help with that?
> 
> I tried adding both to qemu/typedef.h, and since cpu.h is the only user of 
> the file, and it already includes memattrs.h, everything is fine.
> 
> But here maybe you are proposing to make it a regular header, and include 
> this instead of just hw/core/cpu.h in the targets?
> 
> I am thinking whether it is the case to scrap this whole mess, make TCGCPUOps 
> a pointer in CPUClass, and in the targets say for example:
> 
> #include "tcg-cpu-ops.h"
> 
> ...
> 
> +static struct TCGCPUOps cris_tcg_ops = {
> +.initialize = cris_initialize_tcg,
> +};
> +
>  static void cris_cpu_class_init(ObjectClass *oc, void *data)
>  {
>  DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -284,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void 
> *data)
>  cc->gdb_stop_before_watchpoint = true;
>  
>  cc->disas_set_info = cris_disas_set_info;
> -cc->tcg_ops.initialize = cris_initialize_tcg;
> +cc->tcg_ops = _tcg_ops;
>  }
> 
> 
> What do you all think of this?

Making tcg_ops a pointer may make a lot of sense, but (as
mentioned in my reply to v12) I'm worried by the scope of this
series growing too much.

I suggest doing this refactor in smaller steps, to let us focus
in a single issue at a time.  Instead of splitting the struct and
creating a new header file in a single patch, you can first
create the new struct in the same header, and worry about moving
it to a separate header later (in the same series, or in another
series).

-- 
Eduardo

Re: [PATCH v4 00/43] Mirror map JIT memory for TCG

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20201214140314.18544-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201214140314.18544-1-richard.hender...@linaro.org
Subject: [PATCH v4 00/43] Mirror map JIT memory for TCG

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   37f04b7..aa14de0  master -> master
 - [tag update]  patchew/20201211220529.2290218-1-ehabk...@redhat.com -> 
patchew/20201211220529.2290218-1-ehabk...@redhat.com
 * [new tag] 
patchew/20201214140314.18544-1-richard.hender...@linaro.org -> 
patchew/20201214140314.18544-1-richard.hender...@linaro.org
 * [new tag] patchew/20201214155733.207430-1-laur...@vivier.eu -> 
patchew/20201214155733.207430-1-laur...@vivier.eu
 * [new tag] patchew/20201214200713.3886611-1-kei...@keithp.com -> 
patchew/20201214200713.3886611-1-kei...@keithp.com
Switched to a new branch 'test'
5861ba1 tcg: Constify TCGLabelQemuLdst.raddr
8b66138 tcg: Constify tcg_code_gen_epilogue
b60ae50 tcg: Remove TCG_TARGET_SUPPORT_MIRROR
ceb2ae8 tcg/arm: Support split-wx code generation
ddb32ce tcg/mips: Support split-wx code generation
d286278 tcg/mips: Do not assert on relocation overflow
c6603c2 accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd
f472d2a tcg/riscv: Support split-wx code generation
c7b4c9e tcg/riscv: Remove branch-over-branch fallback
5a73605 tcg/riscv: Fix branch range checks
b07237d tcg/s390: Support split-wx code generation
1b609a5 tcg/s390: Use tcg_tbrel_diff
ab6c76a tcg/sparc: Support split-wx code generation
eeb9f35 tcg/sparc: Use tcg_tbrel_diff
5d2fb73 tcg/ppc: Support split-wx code generation
54626b4 tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB
a810384 tcg/ppc: Use tcg_tbrel_diff
4327613 tcg: Introduce tcg_tbrel_diff
b5817c5 tcg/tci: Push const down through bytecode reading
3a0b856 disas: Push const down through host disasassembly
875346c tcg/aarch64: Support split-wx code generation
d8fca0b tcg/aarch64: Use B not BL for tcg_out_goto_long
5c1da59 tcg/i386: Support split-wx code generation
cf974dc tcg: Return the TB pointer from the rx region from exit_tb
4e63180 accel/tcg: Support split-wx for darwin/iOS with vm_remap
2acd41d accel/tcg: Support split-wx for linux with memfd
43dc2fc tcg: Add --accel tcg,split-wx property
a93d787 tcg: Use Error with alloc_code_gen_buffer
14f4dae tcg: Make tb arg to synchronize_from_tb const
6d2cbe3 tcg: Make DisasContextBase.tb const
1ff4e38 tcg: Adjust tb_target_set_jmp_target for split-wx
9163383 tcg: Adjust tcg_register_jit for const
ef98b3c tcg: Adjust tcg_out_label for const
ff58797 tcg: Adjust tcg_out_call for const
204f5dd tcg: Adjust TCGLabel for const
3a0629b tcg: Introduce tcg_splitwx_to_{rx,rw}
e69b13a tcg: Add in_code_gen_buffer
0c55fbc tcg: Move tcg epilogue pointer out of TCGContext
5b1eb71 tcg: Move tcg prologue pointer out of TCGContext
22fc3b0 util: Specialize flush_idcache_range for aarch64
4a47d91 util: Enhance flush_icache_range with separate data pointer
722b23b util: Extract flush_icache_range to cacheflush.c
2a3aaed tcg: Do not flush icache for interpreter

=== OUTPUT BEGIN ===
1/43 Checking commit 2a3aaedef170 (tcg: Do not flush icache for interpreter)
2/43 Checking commit 722b23b5bb81 (util: Extract flush_icache_range to 
cacheflush.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#43: FILE: include/qemu/cacheflush.h:11:
+#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)

WARNING: architecture specific defines should be avoided
#277: FILE: util/cacheflush.c:12:
+#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)

WARNING: architecture specific defines should be avoided
#283: FILE: util/cacheflush.c:18:
+#ifdef __OpenBSD__

total: 0 errors, 4 warnings, 232 lines checked

Patch 2/43 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/43 Checking commit 4a47d9160cc1 (util: Enhance flush_icache_range with 
separate data pointer)
4/43 Checking commit 22fc3b028090 (util: Specialize flush_idcache_range for 
aarch64)
ERROR: externs should be avoided in .c files
#38: FILE: util/cacheflush.c:21:
+extern void sys_icache_invalidate(void *start, size_t len);

ERROR: externs should be avoided in .c files
#39: FILE: util/cacheflush.c:22:
+extern void sys_dcache_flush(void *start, size_t len);

total: 2 errors, 0 warnings, 81 lines checked

Patch 4/43 has style problems, please review.  If any of these errors
are false 

Re: [PATCH 2/3] gitlab-ci: Refactor code that show logs of failed acceptances

[Willian Rampazzo]

On 12/11/20 3:38 PM, Wainer dos Santos Moschetta wrote:

Replace the code (python) on after_script of the acceptance jobs that
is currently used to show the logs of failed tests. Instead it is used
the Avocado's testlogs plug-in which works likewise.

Signed-off-by: Wainer dos Santos Moschetta 
---
  .gitlab-ci.yml | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)



Reviewed-by: Willian Rampazzo 

[PATCH v2 3/3] hw/i386: expose a "smbios-ep" PC machine property

[Eduardo Habkost]

From: Daniel P. Berrangé 

The i440fx and Q35 machine types are both hardcoded to use the legacy
SMBIOS 2.1 entry point. This is a sensible conservative choice because
SeaBIOS only supports SMBIOS 2.1

EDK2, however, can also support SMBIOS 3.0 and QEMU already uses this on
the ARM virt machine type.

This adds a property to allow the choice of SMBIOS entry point versions
For example to opt in to version 3.0

   $QEMU -machine q35,smbios-ep=3_0

Signed-off-by: Daniel P. Berrangé 
Signed-off-by: Eduardo Habkost 
---
This is patch was previously submitted at:
https://lore.kernel.org/qemu-devel/20200908165438.1008942-6-berra...@redhat.com

Changes from v1:
* Include qapi-visit-smbios.h instead of qapi-visit-machine.h
* Commit message fix: s/smbios_ep/smbios-ep/
---
 include/hw/i386/pc.h |  3 +++
 hw/i386/pc.c | 26 ++
 hw/i386/pc_piix.c|  2 +-
 hw/i386/pc_q35.c |  2 +-
 4 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 2aa8797c6e..2075093b32 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -11,6 +11,7 @@
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/hotplug.h"
 #include "qom/object.h"
+#include "hw/firmware/smbios.h"
 
 #define HPET_INTCAP "hpet-intcap"
 
@@ -38,6 +39,7 @@ typedef struct PCMachineState {
 /* Configuration options: */
 uint64_t max_ram_below_4g;
 OnOffAuto vmport;
+SmbiosEntryPointType smbios_ep;
 
 bool acpi_build_enabled;
 bool smbus_enabled;
@@ -62,6 +64,7 @@ typedef struct PCMachineState {
 #define PC_MACHINE_SATA "sata"
 #define PC_MACHINE_PIT  "pit"
 #define PC_MACHINE_MAX_FW_SIZE  "max-fw-size"
+#define PC_MACHINE_SMBIOS_EP"smbios-ep"
 
 /**
  * PCMachineClass:
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 640fb5b0b7..3cc559e0d9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -81,6 +81,7 @@
 #include "hw/mem/nvdimm.h"
 #include "qapi/error.h"
 #include "qapi/qapi-visit-common.h"
+#include "qapi/qapi-visit-smbios.h"
 #include "qapi/visitor.h"
 #include "hw/core/cpu.h"
 #include "hw/usb.h"
@@ -1532,6 +1533,23 @@ static void pc_machine_set_hpet(Object *obj, bool value, 
Error **errp)
 pcms->hpet_enabled = value;
 }
 
+static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+PCMachineState *pcms = PC_MACHINE(obj);
+SmbiosEntryPointType smbios_ep = pcms->smbios_ep;
+
+visit_type_SmbiosEntryPointType(v, name, _ep, errp);
+}
+
+static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+PCMachineState *pcms = PC_MACHINE(obj);
+
+visit_type_SmbiosEntryPointType(v, name, >smbios_ep, errp);
+}
+
 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
 const char *name, void *opaque,
 Error **errp)
@@ -1621,6 +1639,8 @@ static void pc_machine_initfn(Object *obj)
 pcms->vmport = ON_OFF_AUTO_OFF;
 #endif /* CONFIG_VMPORT */
 pcms->max_ram_below_4g = 0; /* use default */
+pcms->smbios_ep = SMBIOS_ENTRY_POINT_TYPE_2_1;
+
 /* acpi build is enabled by default if machine supports it */
 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
 pcms->smbus_enabled = true;
@@ -1759,6 +1779,12 @@ static void pc_machine_class_init(ObjectClass *oc, void 
*data)
 NULL, NULL);
 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
 "Maximum combined firmware size");
+
+object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
+pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
+NULL, NULL);
+object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
+"SMBIOS Entry Point version [v2_1, v3_0]");
 }
 
 static const TypeInfo pc_machine_info = {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 08b82df4d1..30ae7f27af 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -179,7 +179,7 @@ static void pc_init1(MachineState *machine,
 smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
 mc->name, pcmc->smbios_legacy_mode,
 pcmc->smbios_uuid_encoded,
-SMBIOS_ENTRY_POINT_TYPE_2_1);
+pcms->smbios_ep);
 }
 
 /* allocate ram and load rom/bios */
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index f71b1e2dcf..9974426806 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -198,7 +198,7 @@ static void pc_q35_init(MachineState *machine)
 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 mc->name, pcmc->smbios_legacy_mode,
 pcmc->smbios_uuid_encoded,
-

[PATCH v2 2/3] hw/smbios: Use qapi for SmbiosEntryPointType

[Eduardo Habkost]

This prepares for exposing the SMBIOS entry point type as a
machine property on x86.

Based on a patch from Daniel P. Berrangé.

Signed-off-by: Daniel P. Berrangé 
Signed-off-by: Eduardo Habkost 
---
First version of this code was submitted at:
https://lore.kernel.org/qemu-devel/20200908165438.1008942-5-berra...@redhat.com

Changes from v1:
* Patch was split in two
* Declarations were moved to qapi/smbios.json
* Documentation was updated to use the same terminology used in
  SMBIOS documentation
* Documentation was updated to "Since: 6.0"
---
 qapi/qapi-schema.json|  1 +
 qapi/smbios.json | 11 +++
 include/hw/firmware/smbios.h | 10 ++
 qapi/meson.build |  1 +
 4 files changed, 15 insertions(+), 8 deletions(-)
 create mode 100644 qapi/smbios.json

diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json
index 0b444b76d2..87a183fb13 100644
--- a/qapi/qapi-schema.json
+++ b/qapi/qapi-schema.json
@@ -86,6 +86,7 @@
 { 'include': 'machine.json' }
 { 'include': 'machine-target.json' }
 { 'include': 'replay.json' }
+{ 'include': 'smbios.json' }
 { 'include': 'misc.json' }
 { 'include': 'misc-target.json' }
 { 'include': 'audio.json' }
diff --git a/qapi/smbios.json b/qapi/smbios.json
new file mode 100644
index 00..55b3bd2e83
--- /dev/null
+++ b/qapi/smbios.json
@@ -0,0 +1,11 @@
+##
+# @SmbiosEntryPointType:
+#
+# @2_1: SMBIOS version 2.1 (32-bit) Entry Point
+#
+# @3_0: SMBIOS version 3.0 (64-bit) Entry Point
+#
+# Since: 6.0
+##
+{ 'enum': 'SmbiosEntryPointType',
+  'data': [ '2_1', '3_0' ] }
diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h
index 5467ecec78..b3beef1606 100644
--- a/include/hw/firmware/smbios.h
+++ b/include/hw/firmware/smbios.h
@@ -1,6 +1,8 @@
 #ifndef QEMU_SMBIOS_H
 #define QEMU_SMBIOS_H
 
+#include "qapi/qapi-types-smbios.h"
+
 /*
  * SMBIOS Support
  *
@@ -23,14 +25,6 @@ struct smbios_phys_mem_area {
 uint64_t length;
 };
 
-/*
- * SMBIOS spec defined tables
- */
-typedef enum SmbiosEntryPointType {
-SMBIOS_ENTRY_POINT_TYPE_2_1,
-SMBIOS_ENTRY_POINT_TYPE_3_0,
-} SmbiosEntryPointType;
-
 /* SMBIOS Entry Point
  * There are two types of entry points defined in the SMBIOS specification
  * (see below). BIOS must place the entry point(s) at a 16-byte-aligned
diff --git a/qapi/meson.build b/qapi/meson.build
index 0e98146f1f..f7fb73d41b 100644
--- a/qapi/meson.build
+++ b/qapi/meson.build
@@ -42,6 +42,7 @@ qapi_all_modules = [
   'replay',
   'rocker',
   'run-state',
+  'smbios',
   'sockets',
   'tpm',
   'trace',
-- 
2.28.0

Re: [PATCH 1/3] tests/acceptance: Bump avocado requirements to 83.0

[Willian Rampazzo]

On Fri, Dec 11, 2020 at 3:38 PM Wainer dos Santos Moschetta
 wrote:
>
> To use Avocado's testlogs plug-in on CI it is required to use
> its 83.0 or greater version.
>
> Signed-off-by: Wainer dos Santos Moschetta 
> ---
>  tests/requirements.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Willian Rampazzo 

[PATCH v2 0/3] pc: Support configuration of SMBIOS entry point type

[Eduardo Habkost]

This includes code previously submitted[1] by Daniel P. Berrangé
to add a "smbios-ep" machine property on PC.

SMBIOS 3.0 is necessary to support more than ~720 VCPUs, as a
large number of VCPUs can easily hit the table size limit of
SMBIOS 2.1 entry points.

[1] 
https://lore.kernel.org/qemu-devel/20200908165438.1008942-5-berra...@redhat.com

https://lore.kernel.org/qemu-devel/20200908165438.1008942-6-berra...@redhat.com

Daniel P. Berrangé (1):
  hw/i386: expose a "smbios-ep" PC machine property

Eduardo Habkost (2):
  smbios: Rename SMBIOS_ENTRY_POINT_* enums
  hw/smbios: Use qapi for SmbiosEntryPointType

 qapi/qapi-schema.json|  1 +
 qapi/smbios.json | 11 +++
 include/hw/firmware/smbios.h | 10 ++
 include/hw/i386/pc.h |  3 +++
 hw/arm/virt.c|  2 +-
 hw/i386/pc.c | 26 ++
 hw/i386/pc_piix.c|  2 +-
 hw/i386/pc_q35.c |  2 +-
 hw/smbios/smbios.c   |  8 
 qapi/meson.build |  1 +
 10 files changed, 51 insertions(+), 15 deletions(-)
 create mode 100644 qapi/smbios.json

-- 
2.28.0

[PATCH v2 1/3] smbios: Rename SMBIOS_ENTRY_POINT_* enums

[Eduardo Habkost]

Rename the enums to match the naming style used by QAPI.  This
will allow us to more easily move the enum to the QAPI schema
later.

Based on portions of a patch submitted by Daniel P. Berrangé.

Signed-off-by: Daniel P. Berrangé 
Signed-off-by: Eduardo Habkost 
---
First version of this code was submitted at:
https://lore.kernel.org/qemu-devel/20200908165438.1008942-5-berra...@redhat.com

Changes from v1:
* Patch was split in two
* Hunks included this patch are not changed from v1
---
 include/hw/firmware/smbios.h | 4 ++--
 hw/arm/virt.c| 2 +-
 hw/i386/pc_piix.c| 2 +-
 hw/i386/pc_q35.c | 2 +-
 hw/smbios/smbios.c   | 8 
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h
index 02a0ced0a0..5467ecec78 100644
--- a/include/hw/firmware/smbios.h
+++ b/include/hw/firmware/smbios.h
@@ -27,8 +27,8 @@ struct smbios_phys_mem_area {
  * SMBIOS spec defined tables
  */
 typedef enum SmbiosEntryPointType {
-SMBIOS_ENTRY_POINT_21,
-SMBIOS_ENTRY_POINT_30,
+SMBIOS_ENTRY_POINT_TYPE_2_1,
+SMBIOS_ENTRY_POINT_TYPE_3_0,
 } SmbiosEntryPointType;
 
 /* SMBIOS Entry Point
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 556592012e..af53e09d1e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1445,7 +1445,7 @@ static void virt_build_smbios(VirtMachineState *vms)
 
 smbios_set_defaults("QEMU", product,
 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
-true, SMBIOS_ENTRY_POINT_30);
+true, SMBIOS_ENTRY_POINT_TYPE_3_0);
 
 smbios_get_tables(MACHINE(vms), NULL, 0, _tables, 
_tables_len,
   _anchor, _anchor_len);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6188c3e97e..08b82df4d1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -179,7 +179,7 @@ static void pc_init1(MachineState *machine,
 smbios_set_defaults("QEMU", "Standard PC (i440FX + PIIX, 1996)",
 mc->name, pcmc->smbios_legacy_mode,
 pcmc->smbios_uuid_encoded,
-SMBIOS_ENTRY_POINT_21);
+SMBIOS_ENTRY_POINT_TYPE_2_1);
 }
 
 /* allocate ram and load rom/bios */
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 0a212443aa..f71b1e2dcf 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -198,7 +198,7 @@ static void pc_q35_init(MachineState *machine)
 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 mc->name, pcmc->smbios_legacy_mode,
 pcmc->smbios_uuid_encoded,
-SMBIOS_ENTRY_POINT_21);
+SMBIOS_ENTRY_POINT_TYPE_2_1);
 }
 
 /* allocate ram and load rom/bios */
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index f22c4f5b73..930cf52c6b 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -61,7 +61,7 @@ uint8_t *smbios_tables;
 size_t smbios_tables_len;
 unsigned smbios_table_max;
 unsigned smbios_table_cnt;
-static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_21;
+static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_2_1;
 
 static SmbiosEntryPoint ep;
 
@@ -383,7 +383,7 @@ static void smbios_validate_table(MachineState *ms)
 exit(1);
 }
 
-if (smbios_ep_type == SMBIOS_ENTRY_POINT_21 &&
+if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_2_1 &&
 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) {
 error_report("SMBIOS 2.1 table length %zu exceeds %d",
  smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN);
@@ -831,7 +831,7 @@ void smbios_set_defaults(const char *manufacturer, const 
char *product,
 static void smbios_entry_point_setup(void)
 {
 switch (smbios_ep_type) {
-case SMBIOS_ENTRY_POINT_21:
+case SMBIOS_ENTRY_POINT_TYPE_2_1:
 memcpy(ep.ep21.anchor_string, "_SM_", 4);
 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5);
 ep.ep21.length = sizeof(struct smbios_21_entry_point);
@@ -854,7 +854,7 @@ static void smbios_entry_point_setup(void)
 ep.ep21.structure_table_address = cpu_to_le32(0);
 
 break;
-case SMBIOS_ENTRY_POINT_30:
+case SMBIOS_ENTRY_POINT_TYPE_3_0:
 memcpy(ep.ep30.anchor_string, "_SM3_", 5);
 ep.ep30.length = sizeof(struct smbios_30_entry_point);
 ep.ep30.entry_point_revision = 1;
-- 
2.28.0

Re: [PATCH] libvhost-user: add a link-static option

[Marc-André Lureau]

On Mon, Dec 14, 2020 at 9:07 PM Marc-André Lureau <
marcandre.lur...@gmail.com> wrote:

>
>
> On Mon, Dec 14, 2020 at 8:23 PM Paolo Bonzini  wrote:
>
>> On 12/12/20 10:08, marcandre.lur...@redhat.com wrote:
>> > From: Marc-André Lureau 
>> >
>> > Fix linking vhost-user binaries with with ./configure -static.
>> >
>> > Fixes: 0df750e9d3a5fea5e1 ("libvhost-user: make it a meson subproject")
>> > Reported-by: Peter Maydell 
>> > Signed-off-by: Marc-André Lureau 
>> > ---
>> >   configure   | 1 +
>> >   subprojects/libvhost-user/meson.build   | 3 ++-
>> >   subprojects/libvhost-user/meson_options.txt | 5 +
>> >   3 files changed, 8 insertions(+), 1 deletion(-)
>> >   create mode 100644 subprojects/libvhost-user/meson_options.txt
>> >
>> > diff --git a/configure b/configure
>> > index 18c26e0389..465f7bb150 100755
>> > --- a/configure
>> > +++ b/configure
>> > @@ -7014,6 +7014,7 @@ NINJA=$ninja $meson setup \
>> >   -Diconv=$iconv -Dcurses=$curses -Dlibudev=$libudev\
>> >   -Ddocs=$docs -Dsphinx_build=$sphinx_build
>> -Dinstall_blobs=$blobs \
>> >   -Dvhost_user_blk_server=$vhost_user_blk_server \
>> > +-Dlibvhost-user:link-static=$(if test "$static" = yes; then
>> echo true; else echo false; fi) \
>> >   $cross_arg \
>> >   "$PWD" "$source_path"
>> >
>> > diff --git a/subprojects/libvhost-user/meson.build
>> b/subprojects/libvhost-user/meson.build
>> > index c5d85c11d7..5a9cc8675e 100644
>> > --- a/subprojects/libvhost-user/meson.build
>> > +++ b/subprojects/libvhost-user/meson.build
>> > @@ -2,7 +2,8 @@ project('libvhost-user', 'c',
>> >   license: 'GPL-2.0-or-later',
>> >   default_options: ['c_std=gnu99'])
>> >
>> > -glib = dependency('glib-2.0')
>> > +link_static = get_option('link-static')
>> > +glib = dependency('glib-2.0', static: link_static)
>> >   inc = include_directories('../../include', '../../linux-headers')
>> >
>> >   vhost_user = static_library('vhost-user',
>> > diff --git a/subprojects/libvhost-user/meson_options.txt
>> b/subprojects/libvhost-user/meson_options.txt
>> > new file mode 100644
>> > index 00..03fe088e36
>> > --- /dev/null
>> > +++ b/subprojects/libvhost-user/meson_options.txt
>> > @@ -0,0 +1,5 @@
>> > +option('link-static',
>> > +  type: 'boolean',
>> > +  value: false,
>> > +)
>> > +
>>
>> No, this is wrong.  We need to use the results of the configure test
>> uniformly until we can move it to meson.build.
>>
>> Ask yourself if you'd like to have this option in a standalone project,
>>
>
> I took the option from a meson test case:
>
> https://github.com/mesonbuild/meson/blob/master/test%20cases/frameworks/15%20llvm/meson.build
>
> the answer most likely is no...  Can you use override_dependency from
>> the toplevel meson.build instead?  It's usually meant for
>> sub->superproject, but we can use it in this case as well I think.
>>
>>
> ok I'll try
>
>
Adding:
 meson.override_dependency('glib-2.0', dependency('glib-2.0', static:
enable_static))

just before the "vhost_user = not_found..." works. Is that what you had in
mind?


> --
> Marc-André Lureau
>


-- 
Marc-André Lureau