Re: [PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs

[Stefan Weil]

Am 30.01.21 um 07:47 schrieb Richard Henderson:


On 1/29/21 1:16 PM, Peter Maydell wrote:

On Fri, 29 Jan 2021 at 20:13, Richard Henderson
 wrote:

The opcodes always exist, regardless of whether or not they
are enabled.  Remove the unnecessary ifdefs.

Signed-off-by: Richard Henderson 
---
  tcg/tci/tcg-target.c.inc | 82 
  1 file changed, 82 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9c45f5f88f..b62e14d5ce 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -71,70 +71,42 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
  { INDEX_op_add_i32, { R, RI, RI } },
  { INDEX_op_sub_i32, { R, RI, RI } },
  { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
  { INDEX_op_div_i32, { R, R, R } },
  { INDEX_op_divu_i32, { R, R, R } },
  { INDEX_op_rem_i32, { R, R, R } },
  { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
-{ INDEX_op_div2_i32, { R, R, "0", "1", R } },
-{ INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
-#if TCG_TARGET_HAS_div_i64
  { INDEX_op_div_i64, { R, R, R } },
  { INDEX_op_divu_i64, { R, R, R } },
  { INDEX_op_rem_i64, { R, R, R } },
  { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
-{ INDEX_op_div2_i64, { R, R, "0", "1", R } },
-{ INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif

Why are div2/divu2 special cases such that their entries
get deleted rather than unconditionally included ?

Because div/div2 are mutually exclusive.



Yes, that's correct, but as you wrote, "the opcodes always exist, 
regardless of whether or not they are enabled." The old code already 
shows that both cases are mutually exclusive.


If someone decides to use TCG_TARGET_HAS_div2_i64 instead of 
TCG_TARGET_HAS_div_i64 with TCI, that lines (in addition to the 
implementation of the opcodes) would be needed again.


Regards,

Stefan

Re: [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions

[Richard Henderson]

On 1/29/21 1:20 PM, Peter Maydell wrote:
> On Fri, 29 Jan 2021 at 20:14, Richard Henderson
>  wrote:
>>
>> Create symbolic constants for all low-byte-addressable
>> and second-byte-addressable registers.  Create a symbol
>> for the registers that need reserving for softmmu.
>>
>> There is no functional change for 's', as this letter is
>> only used for i386.  The BYTEL name is correct for the
>> action we wish from the constraint.
>>
>> Signed-off-by: Richard Henderson 
>> ---
>>  tcg/i386/tcg-target.c.inc | 40 +++
>>  1 file changed, 20 insertions(+), 20 deletions(-)
>>
>> @@ -226,11 +234,11 @@ static const char 
>> *target_parse_constraint(TCGArgConstraint *ct,
>>  break;
>>  case 'q':
>>  /* A register that can be used as a byte operand.  */
>> -ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xf;
>> +ct->regs |= ALL_BYTEL_REGS;
>>  break;
>>  case 'Q':
>>  /* A register with an addressable second byte (e.g. %ah).  */
>> -ct->regs = 0xf;
>> +ct->regs |= ALL_BYTEH_REGS;
>>  break;
>>  case 'r':
>>  /* A general register.  */
>> @@ -247,19 +255,11 @@ static const char 
>> *target_parse_constraint(TCGArgConstraint *ct,
>>
>>  case 'L':
>>  /* qemu_ld/st data+address constraint */
>> -ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xff;
>> -#ifdef CONFIG_SOFTMMU
>> -tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
>> -tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
>> -#endif
>> +ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
>>  break;
>>  case 's':
>>  /* qemu_st8_i32 data constraint */
>> -ct->regs = 0xf;
>> -#ifdef CONFIG_SOFTMMU
>> -tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
>> -tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
>> -#endif
>> +ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
>>  break;
> 
> Should these cases really be ORing in these expressions
> rather than just using '=' the way the old code was?
> 
> Otherwise
> Reviewed-by: Peter Maydell 

All of the cases should always have been ORd.
In theory, one can combine register constraints,
just like one can combine constant constraints.
Not that it would really make sense for this
specific case.

r~

Re: [PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs

[Richard Henderson]

On 1/29/21 1:16 PM, Peter Maydell wrote:
> On Fri, 29 Jan 2021 at 20:13, Richard Henderson
>  wrote:
>>
>> The opcodes always exist, regardless of whether or not they
>> are enabled.  Remove the unnecessary ifdefs.
>>
>> Signed-off-by: Richard Henderson 
>> ---
>>  tcg/tci/tcg-target.c.inc | 82 
>>  1 file changed, 82 deletions(-)
>>
>> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
>> index 9c45f5f88f..b62e14d5ce 100644
>> --- a/tcg/tci/tcg-target.c.inc
>> +++ b/tcg/tci/tcg-target.c.inc
>> @@ -71,70 +71,42 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
>>  { INDEX_op_add_i32, { R, RI, RI } },
>>  { INDEX_op_sub_i32, { R, RI, RI } },
>>  { INDEX_op_mul_i32, { R, RI, RI } },
>> -#if TCG_TARGET_HAS_div_i32
>>  { INDEX_op_div_i32, { R, R, R } },
>>  { INDEX_op_divu_i32, { R, R, R } },
>>  { INDEX_op_rem_i32, { R, R, R } },
>>  { INDEX_op_remu_i32, { R, R, R } },
>> -#elif TCG_TARGET_HAS_div2_i32
>> -{ INDEX_op_div2_i32, { R, R, "0", "1", R } },
>> -{ INDEX_op_divu2_i32, { R, R, "0", "1", R } },
>> -#endif
> 
>> -#if TCG_TARGET_HAS_div_i64
>>  { INDEX_op_div_i64, { R, R, R } },
>>  { INDEX_op_divu_i64, { R, R, R } },
>>  { INDEX_op_rem_i64, { R, R, R } },
>>  { INDEX_op_remu_i64, { R, R, R } },
>> -#elif TCG_TARGET_HAS_div2_i64
>> -{ INDEX_op_div2_i64, { R, R, "0", "1", R } },
>> -{ INDEX_op_divu2_i64, { R, R, "0", "1", R } },
>> -#endif
> 
> Why are div2/divu2 special cases such that their entries
> get deleted rather than unconditionally included ?

Because div/div2 are mutually exclusive.


r~

Re: [PATCH] vfio/migrate: Move switch of dirty tracking into vfio_memory_listener

[Keqian Zhu]

Hi Kirti,

On 2021/1/28 5:03, Kirti Wankhede wrote:
> 
> 
> On 1/11/2021 1:04 PM, Keqian Zhu wrote:
>> For now the switch of vfio dirty page tracking is integrated into
>> the vfio_save_handler, it causes some problems [1].
>>
> 
> Sorry, I missed [1] mail, somehow it didn't landed in my inbox.
> 
>> The object of dirty tracking is guest memory, but the object of
>> the vfio_save_handler is device state. This mixed logic produces
>> unnecessary coupling and conflicts:
>>
>> 1. Coupling: Their saving granule is different (perVM vs perDevice).
>> vfio will enable dirty_page_tracking for each devices, actually
>> once is enough.
> 
> That's correct, enabling dirty page tracking once is enough. But log_start 
> and log_stop gets called on address space update transaction, region_add() or 
> region_del(), at this point migration may not be active. We don't want to 
> allocate bitmap memory in kernel for lifetime of VM, without knowing 
> migration will be happen or not. vfio_iommu_type1 module should allocate 
> bitmap memory only while migration is active.
> 
Yeah, we can use global start/stop callbacks as suggested by Paolo, which 
solves this problem.

> Paolo's suggestion here to use log_global_start and log_global_stop callbacks 
> seems correct here. But at this point vfio device state is not yet changed to 
> |_SAVING as you had identified it in [1]. May be we can start tracking bitmap 
> in iommu_type1 module while device is not yet _SAVING, but getting dirty 
> bitmap while device is yet not in _SAVING|_RUNNING state doesn't seem optimal 
> solution.
> 
> Pasting here your question from [1]
> 
>> Before start dirty tracking, we will check and ensure that the device
>>  is at _SAVING state and return error otherwise.  But the question is
>>  that what is the rationale?  Why does the VFIO_IOMMU_DIRTY_PAGES
>> ioctl have something to do with the device state?
> 
> Lets walk through the types of devices we are supporting:
> 1. mdev devices without IOMMU backed device
> Vendor driver pins pages as and when required during runtime. We can say 
> that vendor driver is smart which identifies the pages to pin. We are good 
> here.
> 
> 2. mdev device with IOMMU backed device
> This is similar to vfio-pci, direct assigned device, where all pages are 
> pinned at VM bootup. Vendor driver is not smart, so bitmap query will report 
> all pages dirty always. If --auto-converge is not set, VM stucks infinitely 
> in pre-copy phase. This is known to us.
> 
little question here ;-) . Why auto-converge (slow down vCPU) helps to ease the 
case of full dirty?

> 3. mdev device with IOMMU backed device with smart vendor driver
> In this case as well all pages are pinned at VM bootup, but vendor driver 
> is smart to identify the pages and pin them explicitly.
> Pages can be pinned anytime, i.e. during normal VM runtime or on setting 
> _SAVING flag (entering pre-copy phase) or while in iterative pre-copy phase. 
> There is no restriction based on these phases for calling vfio_pin_pages(). 
> Vendor driver can start pinning pages based on its device state when _SAVING 
> flag is set. In that case, if dirty bitmap is queried before that then it 
> will report all sysmem as dirty with an unnecessary copy of sysmem.
> As an optimal solution, I think its better to query bitmap only after all 
> vfio devices are in pre-copy phase, i.e. after _SAVING flag is set.
OK, I get your idea. But Qemu assumes all pages are dirty initially, this seems 
not a problem.
Let's assume we have a device of type 3, and this device starts to pin pages on 
setting _SAVING flag.

Before this patch, the work flow is:
{
ram_save_setup()
memory_global_dirty_log_start():  start dirty tracking excludes vfio part.
migration_bitmap_sync_precopy():  try to sync dirty log from kvm, vhost 
etc, including vfio (as all device saving is not satisfied, fail to get log 
from vfio). The result is that bitmap of ramblock is all dirty.

vfio_save_setup() of this device
vfio_migration_set_state(): Add SAVING state to this device, and vfio 
starts to log dirty page of this device.

first round (i.e. bulk stage) of ram saving: only handle dirty log which is 
collected from the first call of migration_bitmap_sync_precopy().

iterative stage of ram saving: when the remaining dirty log is less than 
threshold, call migration_bitmap_sync_precopy() again. At this stage, all 
device is saving, so success to get log from vfio.
}

With this patch, the work flow is:
{
ram_save_setup()
memory_global_dirty_log_start():  start dirty tracking includes vfio part.
migration_bitmap_sync_precopy():  try to sync dirty log from kvm, vhost 
etc, including vfio (as all device saving is not checked, success to get full 
dirty log from vfio). The result is that bitmap of ramblock is all dirty.
vfio_save_setup() of this device
vfio_migration_set_state(): Add SAVING state to this device, and vfio 
starts to log dirty page of this device.

first 

Re: [PATCH v3] tcg: Fix execution on Apple Silicon

[Richard Henderson]

On 1/29/21 10:50 AM, Roman Bolshakov wrote:
> On Fri, Jan 29, 2021 at 10:18:58AM -1000, Richard Henderson wrote:
>> On 1/21/21 8:34 AM, Richard Henderson wrote:
>>> On 1/12/21 5:28 PM, Roman Bolshakov wrote:
 @@ -1083,6 +1083,12 @@ static bool alloc_code_gen_buffer_anon(size_t size, 
 int prot,
  {
  void *buf;
  
 +#if defined(MAC_OS_VERSION_11_0) && \
 +MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
 +if (__builtin_available(macOS 11.0, *)) {
 +flags |= MAP_JIT;
 +}
 +#endif
>>>
>>> This hunk should be in alloc_code_gen_buffer, where we do the other flags
>>> manipulation.
>>>
>>> I'll drop this hunk and apply the rest, which is exclusively related to
>>> toggling the jit bit.
>>
>> Ping on this?
>>
> Hi Richard,
> 
>> I would imagine that the patch would look something like
>>
>> --- a/accel/tcg/translate-all.c
>> +++ b/accel/tcg/translate-all.c
>> @@ -1296,6 +1296,11 @@ static bool alloc_code_gen_buffer
>>  #ifdef CONFIG_TCG_INTERPRETER
>>  /* The tcg interpreter does not need execute permission. */
>>  prot = PROT_READ | PROT_WRITE;
>> +#elif defined(MAC_OS_VERSION_11_0) && \
>> +MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
>> +if (__builtin_available(macOS 11.0, *)) {
>> +flags |= MAP_JIT;
>> +}
>>  #elif defined(CONFIG_DARWIN)
>>  /* Applicable to both iOS and macOS (Apple Silicon). */
>>  if (!splitwx) {
>>
>> But I don't know how CONFIG_DARWIN, iOS, and MAC_OS_VERSION interact, and I'm
>> not able to even compile-test the patch.
>> Certainly the final comment there looks suspicious, given the preceding 
>> MAC_OS
>> stanza...
>>
> 
> I thought you already added MAP_JIT in 6f70ddee19e. It's getting enabled
> on my M1 laptop. Was it intended or not?
> 
> /* Applicable to both iOS and macOS (Apple Silicon). */
> if (!splitwx) {
> flags |= MAP_JIT;
> }
> 
> TCG from master branch of QEMU works fine on M1. I'm not sure why do we
> need to duplicate it.

I thought there was something about abi/api build issues.  If there's nothing
that needs doing, great!


r~

[PATCH v2] hw/arm/smmuv3: Fix addr_mask for range-based invalidation

[Zenghui Yu]

When handling guest range-based IOTLB invalidation, we should decode the TG
field into the corresponding translation granule size so that we can pass
the correct invalidation range to backend. Set @granule to (tg * 2 + 10) to
properly emulate the architecture.

Fixes: d52915616c05 ("hw/arm/smmuv3: Get prepared for range invalidation")
Signed-off-by: Zenghui Yu 
---
* From v1:
  - Fix the compilation error

 hw/arm/smmuv3.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index bbca0e9f20..98b99d4fe8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -801,7 +801,7 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
 {
 SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
 IOMMUTLBEvent event;
-uint8_t granule = tg;
+uint8_t granule;
 
 if (!tg) {
 SMMUEventInfo event = {.inval_ste_allowed = true};
@@ -821,6 +821,8 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
 return;
 }
 granule = tt->granule_sz;
+} else {
+granule = tg * 2 + 10;
 }
 
 event.type = IOMMU_NOTIFIER_UNMAP;
-- 
2.19.1

Detecting Faulting Instructions From Plugins

[Aaron Lindsay]

Hello,

I appear to be seeing that if I register a callback for an instruction
via `qemu_plugin_register_vcpu_insn_exec_cb` I receive a callback even
if the instruction faults. For example, if an instruction attempts to
load memory from a page which isn't currently mapped by the OS, I
receive two calls for that instruction - one before the page fault, and
one afterwards when the load succeeds.

Two questions:
1. Is this considered a bug or a "feature"?
2.a. If a bug, is there a good way to detect this from inside the
 tcg/plugin infrastructure and avoid calling the callback for the
 faulting execution of the instruction?
2.b. If a "feature", is there a good way to detect this from my plugin?

Thanks!

-Aaron

[PATCH 1/3] hw/arm/Kconfig: Add missing dependency STM32F405 -> OR_IRQ

[Philippe Mathieu-Daudé]

The STM32F405 SoC uses an OR gate on its ADC IRQs.

Fixes: 529fc5fd3e1 ("hw/arm: Add the STM32F4xx SoC")
Signed-off-by: Philippe Mathieu-Daudé 
---
Cc: alist...@alistair23.me
---
 hw/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 13cc42dcc84..a320a124855 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -336,6 +336,7 @@ config STM32F205_SOC
 config STM32F405_SOC
 bool
 select ARM_V7M
+select OR_IRQ
 select STM32F4XX_SYSCFG
 select STM32F4XX_EXTI
 
-- 
2.26.2

[PATCH 3/3] hw/arm: Display CPU type in machine description

[Philippe Mathieu-Daudé]

Most of ARM machines display their CPU when QEMU list the available
machines (-M help). Some machines do not. Fix to unify the help
output.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/arm/digic_boards.c  | 2 +-
 hw/arm/microbit.c  | 2 +-
 hw/arm/netduino2.c | 2 +-
 hw/arm/netduinoplus2.c | 2 +-
 hw/arm/orangepi.c  | 2 +-
 hw/arm/stellaris.c | 4 ++--
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index be12873673b..6cdc1d83fca 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -142,7 +142,7 @@ static void canon_a1100_init(MachineState *machine)
 
 static void canon_a1100_machine_init(MachineClass *mc)
 {
-mc->desc = "Canon PowerShot A1100 IS";
+mc->desc = "Canon PowerShot A1100 IS (ARM946)";
 mc->init = _a1100_init;
 mc->ignore_memory_transaction_failures = true;
 mc->default_ram_size = 64 * MiB;
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 0947491cb97..e9494334ce7 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -64,7 +64,7 @@ static void microbit_machine_class_init(ObjectClass *oc, void 
*data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
 
-mc->desc = "BBC micro:bit";
+mc->desc = "BBC micro:bit (Cortex-M0)";
 mc->init = microbit_init;
 mc->max_cpus = 1;
 }
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 8f103341443..1733b71507c 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -54,7 +54,7 @@ static void netduino2_init(MachineState *machine)
 
 static void netduino2_machine_init(MachineClass *mc)
 {
-mc->desc = "Netduino 2 Machine";
+mc->desc = "Netduino 2 Machine (Cortex-M3)";
 mc->init = netduino2_init;
 mc->ignore_memory_transaction_failures = true;
 }
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 68abd3ec69d..d3ad7a2b675 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -55,7 +55,7 @@ static void netduinoplus2_init(MachineState *machine)
 
 static void netduinoplus2_machine_init(MachineClass *mc)
 {
-mc->desc = "Netduino Plus 2 Machine";
+mc->desc = "Netduino Plus 2 Machine (Cortex-M4)";
 mc->init = netduinoplus2_init;
 }
 
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d6306dfddae..40cdb5c6d2c 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -113,7 +113,7 @@ static void orangepi_init(MachineState *machine)
 
 static void orangepi_machine_init(MachineClass *mc)
 {
-mc->desc = "Orange Pi PC";
+mc->desc = "Orange Pi PC (Cortex-A7)";
 mc->init = orangepi_init;
 mc->block_default_type = IF_SD;
 mc->units_per_default_bus = 1;
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index ad72c0959f1..27292ec4113 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1538,7 +1538,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void 
*data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
 
-mc->desc = "Stellaris LM3S811EVB";
+mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
 mc->init = lm3s811evb_init;
 mc->ignore_memory_transaction_failures = true;
 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
@@ -1554,7 +1554,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void 
*data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
 
-mc->desc = "Stellaris LM3S6965EVB";
+mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
 mc->init = lm3s6965evb_init;
 mc->ignore_memory_transaction_failures = true;
 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
-- 
2.26.2

[PATCH 0/3] hw/arm: Misc trivial fixes/cleanups

[Philippe Mathieu-Daudé]

A pair of bugfixes and cleanup patches noticed while
rebasing my "Support disabling TCG on ARM (part 2)" series.

Philippe Mathieu-Daudé (3):
  hw/arm/Kconfig: Add missing dependency STM32F405 -> OR_IRQ
  hw/arm/Kconfig: Add missing dependency EXYNOS4210 -> OR_IRQ
  hw/arm: Display CPU type in machine description

 hw/arm/digic_boards.c  | 2 +-
 hw/arm/microbit.c  | 2 +-
 hw/arm/netduino2.c | 2 +-
 hw/arm/netduinoplus2.c | 2 +-
 hw/arm/orangepi.c  | 2 +-
 hw/arm/stellaris.c | 4 ++--
 hw/arm/Kconfig | 2 ++
 7 files changed, 9 insertions(+), 7 deletions(-)

-- 
2.26.2

[PATCH v5 10/11] target/arm: Do not build TCG objects when TCG is off

[Philippe Mathieu-Daudé]

From: Samuel Ortiz 

We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.

Signed-off-by: Samuel Ortiz 
[PMD: Heavily rebased during more than 2 years then finally rewritten]
Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/arm/meson.build | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/arm/meson.build b/target/arm/meson.build
index aac9a383a61..11b7c0e18fe 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -27,7 +27,8 @@
   'gdbstub64.c',
 ))
 
-arm_ss.add(files(
+arm_tcg_ss = ss.source_set()
+arm_tcg_ss.add(files(
   'crypto_helper.c',
   'debug_helper.c',
   'iwmmxt_helper.c',
@@ -38,12 +39,12 @@
   'vec_helper.c',
   'cpu_tcg.c',
 ))
-arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: 
files('m_helper-stub.c'))
+arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: 
files('m_helper-stub.c'))
 arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
 
 arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: 
files('kvm-stub.c'))
 
-arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'helper-a64.c',
   'mte_helper.c',
   'pauth_helper.c',
@@ -52,14 +53,16 @@
   'translate-sve.c',
 ))
 
+arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss)
+
 arm_softmmu_ss = ss.source_set()
 arm_softmmu_ss.add(files(
   'arch_dump.c',
   'arm-powerctl.c',
   'machine.c',
   'monitor.c',
-  'psci.c',
 ))
+arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c'))
 
 target_arch += {'arm': arm_ss}
 target_softmmu_arch += {'arm': arm_softmmu_ss}
-- 
2.26.2

[PATCH v5 11/11] .travis.yml: Add a KVM-only Aarch64 job

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.

We explicitly modify default-configs/aarch64-softmmu.mak to
only select the 'virt' and 'SBSA-REF' machines.

Signed-off-by: Philippe Mathieu-Daudé 
---
Job ran for 7 min 30 sec
https://travis-ci.org/github/philmd/qemu/jobs/731428859
---
 .travis.yml | 32 
 1 file changed, 32 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 5f1dea873ec..4f1d662b5fc 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -264,6 +264,38 @@ jobs:
 - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
 - UNRELIABLE=true
 
+- name: "[aarch64] GCC (disable-tcg)"
+  arch: arm64
+  dist: focal
+  addons:
+apt_packages:
+  - libaio-dev
+  - libattr1-dev
+  - libbrlapi-dev
+  - libcap-ng-dev
+  - libgcrypt20-dev
+  - libgnutls28-dev
+  - libgtk-3-dev
+  - libiscsi-dev
+  - liblttng-ust-dev
+  - libncurses5-dev
+  - libnfs-dev
+  - libnss3-dev
+  - libpixman-1-dev
+  - libpng-dev
+  - librados-dev
+  - libsdl2-dev
+  - libseccomp-dev
+  - liburcu-dev
+  - libusb-1.0-0-dev
+  - libvdeplug-dev
+  - libvte-2.91-dev
+  - ninja-build
+  env:
+- CONFIG="--disable-containers --disable-tcg --enable-kvm 
--disable-xen --disable-tools --disable-docs"
+- TEST_CMD="make check-unit"
+- CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64"
+
 - name: "[ppc64] GCC check-tcg"
   arch: ppc64le
   dist: focal
-- 
2.26.2

[PATCH v5 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel

[Philippe Mathieu-Daudé]

A KVM-only build won't be able to run M-profile cpus.

Only enable the following ARMv7 M-Profile CPUs when TCG is available:

  - Cortex-M0
  - Cortex-M3
  - Cortex-M4
  - Cortex-M33

The following machines are no more built when TCG is disabled:

  - emcraft-sf2  SmartFusion2 SOM kit from Emcraft (M2S010)
  - highbank Calxeda Highbank (ECX-1000)
  - lm3s6965evb  Stellaris LM3S6965EVB
  - lm3s811evb   Stellaris LM3S811EVB
  - midway   Calxeda Midway (ECX-2000)
  - mps2-an385   ARM MPS2 with AN385 FPGA image for Cortex-M3
  - mps2-an386   ARM MPS2 with AN386 FPGA image for Cortex-M4
  - mps2-an500   ARM MPS2 with AN500 FPGA image for Cortex-M7
  - mps2-an505   ARM MPS2 with AN505 FPGA image for Cortex-M33
  - mps2-an511   ARM MPS2 with AN511 DesignStart FPGA image for 
Cortex-M3
  - mps2-an521   ARM MPS2 with AN521 FPGA image for dual Cortex-M33
  - musca-a  ARM Musca-A board (dual Cortex-M33)
  - musca-b1 ARM Musca-B1 board (dual Cortex-M33)
  - netduino2Netduino 2 Machine
  - netduinoplus2Netduino Plus 2 Machine

We don't need to enforce CONFIG_ARM_V7M in default-configs anymore.

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/arm-softmmu.mak | 11 ---
 hw/arm/Kconfig  | 17 +
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/default-configs/devices/arm-softmmu.mak 
b/default-configs/devices/arm-softmmu.mak
index ee80bf15150..b72926b8fce 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -1,28 +1,17 @@
 # Default configuration for arm-softmmu
 
-# TODO: ARM_V7M is currently always required - make this more flexible!
-CONFIG_ARM_V7M=y
-
 # CONFIG_PCI_DEVICES=n
 # CONFIG_TEST_DEVICES=n
 
 CONFIG_ARM_VIRT=y
 CONFIG_CUBIEBOARD=y
 CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
 CONFIG_REALVIEW=y
 CONFIG_VEXPRESS=y
 CONFIG_ZYNQ=y
 CONFIG_NPCM7XX=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
 CONFIG_RASPI=y
 CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
 CONFIG_FSL_IMX7=y
 CONFIG_FSL_IMX6UL=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 320428bf97e..f56c05c00a8 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -16,6 +16,12 @@ config ARM_V7R
 depends on TCG
 select ARM_COMPATIBLE_SEMIHOSTING
 
+config ARM_V7M
+bool
+depends on TCG
+select ARM_COMPATIBLE_SEMIHOSTING
+select PTIMER
+
 config ARM_VIRT
 bool
 imply PCI_DEVICES
@@ -78,6 +84,7 @@ config EXYNOS4
 
 config HIGHBANK
 bool
+default y if TCG
 select A9MPCORE
 select A15MPCORE
 select AHCI
@@ -113,6 +120,7 @@ config MAINSTONE
 
 config MUSCA
 bool
+default y if TCG
 select ARMSSE
 select PL011
 select PL031
@@ -133,10 +141,12 @@ config MUSICPAL
 
 config NETDUINO2
 bool
+default y if TCG
 select STM32F205_SOC
 
 config NETDUINOPLUS2
 bool
+default y if TCG
 select STM32F405_SOC
 
 config NSERIES
@@ -258,6 +268,7 @@ config SABRELITE
 
 config STELLARIS
 bool
+default y if TCG
 select ARM_V7M
 select CMSDK_APB_WATCHDOG
 select I2C
@@ -331,10 +342,6 @@ config ZYNQ
 select XILINX_SPIPS
 select ZYNQ_DEVCFG
 
-config ARM_V7M
-bool
-select PTIMER
-
 config ALLWINNER_A10
 bool
 select AHCI
@@ -463,6 +470,7 @@ config ASPEED_SOC
 
 config MPS2
 bool
+default y if TCG
 select ARMSSE
 select LAN9118
 select MPS2_FPGAIO
@@ -516,6 +524,7 @@ config NRF51_SOC
 
 config EMCRAFT_SF2
 bool
+default y if TCG
 select MSF2
 select SSI_M25P80
 
-- 
2.26.2

[PATCH v5 04/11] target/arm: Restrict ARMv5 cpus to TCG accel

[Philippe Mathieu-Daudé]

KVM requires a cpu based on (at least) the ARMv7 architecture.

Only enable the following ARMv5 CPUs when TCG is available:

  - ARM926
  - ARM946
  - ARM1026
  - XScale (PXA250/255/260/261/262/270)

The following machines are no more built when TCG is disabled:

  - akitaSharp SL-C1000 (Akita) PDA (PXA270)
  - ast2500-evb  Aspeed AST2500 EVB (ARM1176)
  - ast2600-evb  Aspeed AST2600 EVB (Cortex A7)
  - borzoi   Sharp SL-C3100 (Borzoi) PDA (PXA270)
  - canon-a1100  Canon PowerShot A1100 IS
  - collie   Sharp SL-5500 (Collie) PDA (SA-1110)
  - connex   Gumstix Connex (PXA255)
  - g220a-bmcBytedance G220A BMC (ARM1176)
  - imx25-pdkARM i.MX25 PDK board (ARM926)
  - integratorcp ARM Integrator/CP (ARM926EJ-S)
  - mainstoneMainstone II (PXA27x)
  - musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S)
  - palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S)
  - realview-eb  ARM RealView Emulation Baseboard (ARM926EJ-S)
  - romulus-bmc  OpenPOWER Romulus BMC (ARM1176)
  - sonorapass-bmc   OCP SonoraPass BMC (ARM1176)
  - spitzSharp SL-C3000 (Spitz) PDA (PXA270)
  - supermicrox11-bmcSupermicro X11 BMC (ARM926EJ-S)
  - swift-bmcOpenPOWER Swift BMC (ARM1176)
  - tacoma-bmc   OpenPOWER Tacoma BMC (Cortex A7)
  - terrier  Sharp SL-C3200 (Terrier) PDA (PXA270)
  - tosa Sharp SL-6000 (Tosa) PDA (PXA255)
  - verdex   Gumstix Verdex (PXA270)
  - versatileab  ARM Versatile/AB (ARM926EJ-S)
  - versatilepb  ARM Versatile/PB (ARM926EJ-S)
  - witherspoon-bmc  OpenPOWER Witherspoon BMC (ARM1176)
  - z2   Zipit Z2 (PXA27x)

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/arm-softmmu.mak | 12 
 hw/arm/realview.c   |  5 -
 hw/arm/Kconfig  | 23 +++
 3 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/default-configs/devices/arm-softmmu.mak 
b/default-configs/devices/arm-softmmu.mak
index 8a53e637d23..5b25fafc9ab 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y
 CONFIG_CUBIEBOARD=y
 CONFIG_EXYNOS4=y
 CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
 CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
 CONFIG_MUSCA=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
 CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
 CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
 CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
 CONFIG_NETDUINO2=y
 CONFIG_NETDUINOPLUS2=y
 CONFIG_MPS2=y
 CONFIG_RASPI=y
-CONFIG_DIGIC=y
 CONFIG_SABRELITE=y
 CONFIG_EMCRAFT_SF2=y
 CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
 CONFIG_FSL_IMX7=y
 CONFIG_FSL_IMX6UL=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 0831159d158..cd37b501287 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -18,6 +18,7 @@
 #include "hw/pci/pci.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
 #include "hw/boards.h"
 #include "hw/i2c/i2c.h"
 #include "exec/address-spaces.h"
@@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = {
 
 static void realview_machine_init(void)
 {
-type_register_static(_eb_type);
+if (tcg_enabled()) {
+type_register_static(_eb_type);
+}
 type_register_static(_eb_mpcore_type);
 type_register_static(_pb_a8_type);
 type_register_static(_pbx_a9_type);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7126d82f6ce..bdb8c63af7b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -2,6 +2,10 @@ config ARM_V4
 bool
 depends on TCG
 
+config ARM_V5
+bool
+depends on TCG
+
 config ARM_VIRT
 bool
 imply PCI_DEVICES
@@ -46,6 +50,8 @@ config CUBIEBOARD
 
 config DIGIC
 bool
+default y if TCG
+select ARM_V5
 select PTIMER
 select PFLASH_CFI02
 
@@ -76,6 +82,8 @@ config HIGHBANK
 
 config INTEGRATOR
 bool
+default y if TCG
+select ARM_V5
 select ARM_TIMER
 select INTEGRATOR_DEBUG
 select PL011 # UART
@@ -88,6 +96,7 @@ config INTEGRATOR
 
 config MAINSTONE
 bool
+default y if TCG
 select PXA2XX
 select PFLASH_CFI01
 select SMC91C111
@@ -102,6 +111,8 @@ config MUSCA
 
 config MUSICPAL
 bool
+default y if TCG
+select ARM_V5
 select OR_IRQ
 select BITBANG_I2C
 select MARVELL_88W8618
@@ -142,6 +153,7 @@ config OMAP
 
 config PXA2XX
 bool
+select ARM_V5
 select FRAMEBUFFER
 select I2C
 select SERIAL
@@ -151,12 +163,14 @@ config PXA2XX
 
 config GUMSTIX
 bool
+default y if TCG
 select PFLASH_CFI01
 select SMC91C111
 select PXA2XX
 
 config TOSA
 bool
+default y if TCG
 select ZAURUS  # scoop
 select MICRODRIVE
 select 

[PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel

[Philippe Mathieu-Daudé]

A KVM-only build won't be able to run R-profile cpus.

Only enable the following ARMv7 R-Profile CPUs when TCG is available:

  - Cortex-R5
  - Cortex-R5F

The following machine is no more built when TCG is disabled:

  - xlnx-zcu102  Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/aarch64-softmmu.mak | 1 -
 hw/arm/Kconfig  | 7 +++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/default-configs/devices/aarch64-softmmu.mak 
b/default-configs/devices/aarch64-softmmu.mak
index 958b1e08e40..a4202f56817 100644
--- a/default-configs/devices/aarch64-softmmu.mak
+++ b/default-configs/devices/aarch64-softmmu.mak
@@ -3,6 +3,5 @@
 # We support all the 32 bit boards so need all their config
 include arm-softmmu.mak
 
-CONFIG_XLNX_ZYNQMP_ARM=y
 CONFIG_XLNX_VERSAL=y
 CONFIG_SBSA_REF=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index daab7081994..320428bf97e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -11,6 +11,11 @@ config ARM_V6
 depends on TCG
 select ARM_COMPATIBLE_SEMIHOSTING
 
+config ARM_V7R
+bool
+depends on TCG
+select ARM_COMPATIBLE_SEMIHOSTING
+
 config ARM_VIRT
 bool
 imply PCI_DEVICES
@@ -377,8 +382,10 @@ config STM32F405_SOC
 
 config XLNX_ZYNQMP_ARM
 bool
+default y if TCG
 select AHCI
 select ARM_GIC
+select ARM_V7R
 select CADENCE
 select DDC
 select DPCD
-- 
2.26.2

[PATCH v5 02/11] default-configs: Remove unnecessary SEMIHOSTING selection

[Philippe Mathieu-Daudé]

Commit 56b5170c87e ("semihosting: Move ARM semihosting code to
shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which
already selects SEMIHOSTING. No need to select it again.

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/arm-softmmu.mak | 1 -
 1 file changed, 1 deletion(-)

diff --git a/default-configs/devices/arm-softmmu.mak 
b/default-configs/devices/arm-softmmu.mak
index 0500156a0c7..341d439de6f 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -41,6 +41,5 @@ CONFIG_MICROBIT=y
 CONFIG_FSL_IMX25=y
 CONFIG_FSL_IMX7=y
 CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
 CONFIG_ALLWINNER_H3=y
-- 
2.26.2

[PATCH 2/3] hw/arm/Kconfig: Add missing dependency EXYNOS4210 -> OR_IRQ

[Philippe Mathieu-Daudé]

The Exynos4210 SoC uses an OR gate on the PL330 IRQ lines.

Fixes: dab15fbe2ab ("hw/arm/exynos4210: Fix DMA initialization")
Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index a320a124855..223016bb4e8 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -52,6 +52,7 @@ config EXYNOS4
 select PTIMER
 select SDHCI
 select USB_EHCI_SYSBUS
+select OR_IRQ
 
 config HIGHBANK
 bool
-- 
2.26.2

[PATCH v5 05/11] target/arm: Restrict ARMv6 cpus to TCG accel

[Philippe Mathieu-Daudé]

KVM requires a cpu based on (at least) the ARMv7 architecture.

Only enable the following ARMv6 CPUs when TCG is available:

  - ARM1136
  - ARM1176
  - ARM11MPCore
  - Cortex-M0

The following machines are no more built when TCG is disabled:

  - kzm  ARM KZM Emulation Baseboard (ARM1136)
  - microbit BBC micro:bit (Cortex-M0)
  - n800 Nokia N800 tablet aka. RX-34 (OMAP2420)
  - n810 Nokia N810 tablet aka. RX-44 (OMAP2420)
  - realview-eb-mpcore   ARM RealView Emulation Baseboard (ARM11MPCore)

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/arm-softmmu.mak |  2 --
 hw/arm/realview.c   |  2 +-
 hw/arm/Kconfig  | 11 +++
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/default-configs/devices/arm-softmmu.mak 
b/default-configs/devices/arm-softmmu.mak
index 5b25fafc9ab..ee80bf15150 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y
 CONFIG_CUBIEBOARD=y
 CONFIG_EXYNOS4=y
 CONFIG_HIGHBANK=y
-CONFIG_FSL_IMX31=y
 CONFIG_MUSCA=y
-CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
 CONFIG_REALVIEW=y
 CONFIG_VEXPRESS=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index cd37b501287..57a37608e39 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -463,8 +463,8 @@ static void realview_machine_init(void)
 {
 if (tcg_enabled()) {
 type_register_static(_eb_type);
+type_register_static(_eb_mpcore_type);
 }
-type_register_static(_eb_mpcore_type);
 type_register_static(_pb_a8_type);
 type_register_static(_pbx_a9_type);
 }
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index bdb8c63af7b..daab7081994 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -6,6 +6,11 @@ config ARM_V5
 bool
 depends on TCG
 
+config ARM_V6
+bool
+depends on TCG
+select ARM_COMPATIBLE_SEMIHOSTING
+
 config ARM_VIRT
 bool
 imply PCI_DEVICES
@@ -131,6 +136,8 @@ config NETDUINOPLUS2
 
 config NSERIES
 bool
+default y if TCG
+select ARM_V6
 select OMAP
 select TMP105   # tempature sensor
 select BLIZZARD # LCD/TV controller
@@ -411,6 +418,8 @@ config FSL_IMX25
 
 config FSL_IMX31
 bool
+default y if TCG
+select ARM_V6
 select SERIAL
 select IMX
 select IMX_I2C
@@ -488,11 +497,13 @@ config FSL_IMX6UL
 
 config MICROBIT
 bool
+default y if TCG
 select NRF51_SOC
 
 config NRF51_SOC
 bool
 select I2C
+select ARM_V6
 select ARM_V7M
 select UNIMP
 
-- 
2.26.2

[PATCH v5 01/11] exec: Restrict TCG specific headers

[Philippe Mathieu-Daudé]

Fixes when building with --disable-tcg:

  In file included from target/arm/helper.c:16:
  include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file 
or directory
 42 | #include "tcg-runtime.h"
|  ^~~

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/exec/helper-proto.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index 659f9298e8f..740bff3bb4d 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), 
dh_ctype(t3), \
 
 #include "helper.h"
 #include "trace/generated-helpers.h"
+#ifdef CONFIG_TCG
 #include "tcg-runtime.h"
 #include "plugin-helpers.h"
+#endif /* CONFIG_TCG */
 
 #undef IN_HELPER_PROTO
 
-- 
2.26.2

[PATCH v5 09/11] target/arm: Reorder meson.build rules

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

Reorder the rules to make this file easier to modify.
No logical change introduced in this commit.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/arm/meson.build | 19 ---
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6c6081966cd..aac9a383a61 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -14,31 +14,36 @@
 
 arm_ss = ss.source_set()
 arm_ss.add(gen)
+arm_ss.add(zlib)
 arm_ss.add(files(
   'cpu.c',
-  'crypto_helper.c',
-  'debug_helper.c',
   'gdbstub.c',
   'helper.c',
+  'vfp_helper.c',
+))
+
+arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+  'cpu64.c',
+  'gdbstub64.c',
+))
+
+arm_ss.add(files(
+  'crypto_helper.c',
+  'debug_helper.c',
   'iwmmxt_helper.c',
   'neon_helper.c',
   'op_helper.c',
   'tlb_helper.c',
   'translate.c',
   'vec_helper.c',
-  'vfp_helper.c',
   'cpu_tcg.c',
 ))
-arm_ss.add(zlib)
-
 arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: 
files('m_helper-stub.c'))
 arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
 
 arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: 
files('kvm-stub.c'))
 
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
-  'cpu64.c',
-  'gdbstub64.c',
   'helper-a64.c',
   'mte_helper.c',
   'pauth_helper.c',
-- 
2.26.2

[PATCH v5 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M

[Philippe Mathieu-Daudé]

From: Thomas Huth 

We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other code without CONFIG_ARM_V7M.

Signed-off-by: Thomas Huth 
Message-Id: <20190903154810.27365-4-th...@redhat.com>
[PMD: Keep m_helper-stub.c but extend it, rewrite the rest]
Signed-off-by: Philippe Mathieu-Daudé 
---
Rewrite since v3, therefore removed Richard R-b tag.
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/arm/cpu.h   | 12 ---
 target/arm/cpu_tcg.c   |  4 ++-
 target/arm/helper.c|  7 
 target/arm/m_helper-stub.c | 73 ++
 target/arm/meson.build |  4 ++-
 5 files changed, 79 insertions(+), 21 deletions(-)
 create mode 100644 target/arm/m_helper-stub.c

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d080239863c..0bd0e51e498 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t 
excp_idx,
 /* Interface between CPU and Interrupt controller.  */
 #ifndef CONFIG_USER_ONLY
 bool armv7m_nvic_can_take_pending_exception(void *opaque);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
-{
-return true;
-}
-#endif
 /**
  * armv7m_nvic_set_pending: mark the specified exception as pending
  * @opaque: the NVIC
@@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque);
  * @secure: the security state to test
  * This corresponds to the pseudocode IsReqExecPriNeg().
  */
-#ifndef CONFIG_USER_ONLY
 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
-{
-return false;
-}
 #endif
 
 /* Interface for defining coprocessor registers.
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98544db2df3..3e1c9b40353 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 
+#ifndef CONFIG_USER_ONLY
 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
 CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
 }
 return ret;
 }
+#endif /* CONFIG_USER_ONLY */
 
 static void arm926_initfn(Object *obj)
 {
@@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 acc->info = data;
 #ifndef CONFIG_USER_ONLY
 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 #endif
 
-cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 cc->gdb_core_xml_file = "arm-m-profile.xml";
 }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 47e266d7e64..fe3d0291f9c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
 }
 }
 
-#ifndef CONFIG_TCG
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
-g_assert_not_reached();
-}
-#endif
-
 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
 {
 ARMMMUIdx idx;
diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c
new file mode 100644
index 000..6d751424e86
--- /dev/null
+++ b/target/arm/m_helper-stub.c
@@ -0,0 +1,73 @@
+/*
+ * ARM V7M related stubs.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "internals.h"
+
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+{
+g_assert_not_reached();
+}
+
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+{
+g_assert_not_reached();
+}
+
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+{
+g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+{
+g_assert_not_reached();
+}
+
+void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
+{
+g_assert_not_reached();
+}
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+g_assert_not_reached();
+}
+
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+g_assert_not_reached();
+}
+
+void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
+{
+g_assert_not_reached();
+}
+
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+g_assert_not_reached();
+}
+
+#ifndef CONFIG_USER_ONLY
+
+bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+g_assert_not_reached();
+}
+
+void arm_v7m_cpu_do_interrupt(CPUState *cs)
+{
+g_assert_not_reached();
+}
+
+#endif /* CONFIG_USER_ONLY */
diff --git 

[PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel

[Philippe Mathieu-Daudé]

KVM requires a cpu based on (at least) the ARMv7 architecture.

Only enable the following ARMv4 CPUs when TCG is available:

  - StrongARM (SA1100/1110)
  - OMAP1510 (TI925T)

The following machines are no more built when TCG is disabled:

  - cheetah  Palm Tungsten|E aka. Cheetah PDA (OMAP310)
  - sx1  Siemens SX1 (OMAP310) V2
  - sx1-v1   Siemens SX1 (OMAP310) V1

Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/devices/arm-softmmu.mak | 2 --
 hw/arm/Kconfig  | 8 
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/default-configs/devices/arm-softmmu.mak 
b/default-configs/devices/arm-softmmu.mak
index 341d439de6f..8a53e637d23 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y
 CONFIG_FSL_IMX31=y
 CONFIG_MUSICPAL=y
 CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
 CONFIG_REALVIEW=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 223016bb4e8..7126d82f6ce 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,3 +1,7 @@
+config ARM_V4
+bool
+depends on TCG
+
 config ARM_VIRT
 bool
 imply PCI_DEVICES
@@ -31,6 +35,8 @@ config ARM_VIRT
 
 config CHEETAH
 bool
+default y if TCG
+select ARM_V4
 select OMAP
 select TSC210X
 
@@ -249,6 +255,8 @@ config COLLIE
 
 config SX1
 bool
+default y if TCG
+select ARM_V4
 select OMAP
 
 config VERSATILE
-- 
2.26.2

[PATCH v5 00/11] Support disabling TCG on ARM (part 2)

[Philippe Mathieu-Daudé]

Cover from Samuel Ortiz from (part 1) [1]:

  This patchset allows for building and running ARM targets with TCG
  disabled. [...]

  The rationale behind this work comes from the NEMU project where we're
  trying to only support x86 and ARM 64-bit architectures, without
  including the TCG code base. We can only do so if we can build and run
  ARM binaries with TCG disabled.

v5:
- addressed Paolo/Richard/Thomas review comments from v4 [5].

v4 almost 2 years later... [2]:
- Rebased on Meson
- Addressed Richard review comments
- Addressed Claudio review comments

v3 almost 18 months later [3]:
- Rebased
- Addressed Thomas review comments
- Added Travis-CI job to keep building --disable-tcg on ARM

v2 [4]:
- Addressed review comments from Richard and Thomas from v1 [1]

Regards,

Phil.

[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
[2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html
[3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
[4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
[5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html

Philippe Mathieu-Daudé (9):
  exec: Restrict TCG specific headers
  default-configs: Remove unnecessary SEMIHOSTING selection
  target/arm: Restrict ARMv4 cpus to TCG accel
  target/arm: Restrict ARMv5 cpus to TCG accel
  target/arm: Restrict ARMv6 cpus to TCG accel
  target/arm: Restrict ARMv7 R-profile cpus to TCG accel
  target/arm: Restrict ARMv7 M-profile cpus to TCG accel
  target/arm: Reorder meson.build rules
  .travis.yml: Add a KVM-only Aarch64 job

Samuel Ortiz (1):
  target/arm: Do not build TCG objects when TCG is off

Thomas Huth (1):
  target/arm: Make m_helper.c optional via CONFIG_ARM_V7M

 default-configs/devices/aarch64-softmmu.mak |  1 -
 default-configs/devices/arm-softmmu.mak | 28 
 include/exec/helper-proto.h |  2 +
 target/arm/cpu.h| 12 
 hw/arm/realview.c   |  7 +-
 target/arm/cpu_tcg.c|  4 +-
 target/arm/helper.c |  7 --
 target/arm/m_helper-stub.c  | 73 +
 .travis.yml | 32 +
 hw/arm/Kconfig  | 66 +--
 target/arm/meson.build  | 28 +---
 11 files changed, 196 insertions(+), 64 deletions(-)
 create mode 100644 target/arm/m_helper-stub.c

-- 
2.26.2

Re: [PATCH v3 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:26, Richard Henderson
 wrote:
>
> This requires finishing the conversion to tcg_target_op_def.
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/tci/tcg-target-con-set.h |  25 
>  tcg/tci/tcg-target.h |   2 +
>  tcg/tci/tcg-target.c.inc | 279 +--
>  3 files changed, 161 insertions(+), 145 deletions(-)
>  create mode 100644 tcg/tci/tcg-target-con-set.h
>
Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v3 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:25, Richard Henderson
 wrote:
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/sparc/tcg-target-con-str.h | 23 ++
>  tcg/sparc/tcg-target.h |  5 +--
>  tcg/sparc/tcg-target.c.inc | 81 +-
>  3 files changed, 55 insertions(+), 54 deletions(-)
>  create mode 100644 tcg/sparc/tcg-target-con-str.h

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v3 11/24] tcg/riscv: Split out target constraints to tcg-target-con-str.h

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:23, Richard Henderson
 wrote:
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/riscv/tcg-target-con-str.h | 21 ++
>  tcg/riscv/tcg-target.h |  1 +
>  tcg/riscv/tcg-target.c.inc | 52 +-
>  3 files changed, 35 insertions(+), 39 deletions(-)
>  create mode 100644 tcg/riscv/tcg-target-con-str.h
>

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v3 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:17, Richard Henderson
 wrote:
>
> This eliminates the target-specific function target_parse_constraint
> and folds it into the single caller, process_op_defs.  Since this is
> done directly into the switch statement, duplicates are compilation
> errors rather than silently ignored at runtime.
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/i386/tcg-target-con-str.h | 33 +
>  tcg/i386/tcg-target.h |  1 +
>  tcg/tcg.c | 33 ++---
>  tcg/i386/tcg-target.c.inc | 69 ---
>  4 files changed, 62 insertions(+), 74 deletions(-)
>  create mode 100644 tcg/i386/tcg-target-con-str.h

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v3 04/24] tcg/i386: Tidy register constraint definitions

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:14, Richard Henderson
 wrote:
>
> Create symbolic constants for all low-byte-addressable
> and second-byte-addressable registers.  Create a symbol
> for the registers that need reserving for softmmu.
>
> There is no functional change for 's', as this letter is
> only used for i386.  The BYTEL name is correct for the
> action we wish from the constraint.
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/i386/tcg-target.c.inc | 40 +++
>  1 file changed, 20 insertions(+), 20 deletions(-)
>
> @@ -226,11 +234,11 @@ static const char 
> *target_parse_constraint(TCGArgConstraint *ct,
>  break;
>  case 'q':
>  /* A register that can be used as a byte operand.  */
> -ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xf;
> +ct->regs |= ALL_BYTEL_REGS;
>  break;
>  case 'Q':
>  /* A register with an addressable second byte (e.g. %ah).  */
> -ct->regs = 0xf;
> +ct->regs |= ALL_BYTEH_REGS;
>  break;
>  case 'r':
>  /* A general register.  */
> @@ -247,19 +255,11 @@ static const char 
> *target_parse_constraint(TCGArgConstraint *ct,
>
>  case 'L':
>  /* qemu_ld/st data+address constraint */
> -ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xff;
> -#ifdef CONFIG_SOFTMMU
> -tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
> -tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
> -#endif
> +ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
>  break;
>  case 's':
>  /* qemu_st8_i32 data constraint */
> -ct->regs = 0xf;
> -#ifdef CONFIG_SOFTMMU
> -tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
> -tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
> -#endif
> +ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
>  break;

Should these cases really be ORing in these expressions
rather than just using '=' the way the old code was?

Otherwise
Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:13, Richard Henderson
 wrote:
>
> The opcodes always exist, regardless of whether or not they
> are enabled.  Remove the unnecessary ifdefs.
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/tci/tcg-target.c.inc | 82 
>  1 file changed, 82 deletions(-)
>
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 9c45f5f88f..b62e14d5ce 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -71,70 +71,42 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
>  { INDEX_op_add_i32, { R, RI, RI } },
>  { INDEX_op_sub_i32, { R, RI, RI } },
>  { INDEX_op_mul_i32, { R, RI, RI } },
> -#if TCG_TARGET_HAS_div_i32
>  { INDEX_op_div_i32, { R, R, R } },
>  { INDEX_op_divu_i32, { R, R, R } },
>  { INDEX_op_rem_i32, { R, R, R } },
>  { INDEX_op_remu_i32, { R, R, R } },
> -#elif TCG_TARGET_HAS_div2_i32
> -{ INDEX_op_div2_i32, { R, R, "0", "1", R } },
> -{ INDEX_op_divu2_i32, { R, R, "0", "1", R } },
> -#endif

> -#if TCG_TARGET_HAS_div_i64
>  { INDEX_op_div_i64, { R, R, R } },
>  { INDEX_op_divu_i64, { R, R, R } },
>  { INDEX_op_rem_i64, { R, R, R } },
>  { INDEX_op_remu_i64, { R, R, R } },
> -#elif TCG_TARGET_HAS_div2_i64
> -{ INDEX_op_div2_i64, { R, R, "0", "1", R } },
> -{ INDEX_op_divu2_i64, { R, R, "0", "1", R } },
> -#endif

Why are div2/divu2 special cases such that their entries
get deleted rather than unconditionally included ?

thanks
-- PMM

Re: [PATCH v3 03/24] tcg/i386: Move constraint type check to tcg_target_const_match

[Peter Maydell]

On Fri, 29 Jan 2021 at 20:13, Richard Henderson
 wrote:
>
> Rather than check the type when filling in the constraint,
> check it when matching the constant.  This removes the only
> use of the type argument to target_parse_constraint.
>
> Signed-off-by: Richard Henderson 
> ---
>  tcg/i386/tcg-target.c.inc | 28 +---

Reviewed-by: Peter Maydell 

thanks
-- PMM

RE: [PATCH v7 12/35] Hexagon (target/hexagon) instruction attributes

[Taylor Simpson]

> -Original Message-
> From: Philippe Mathieu-Daudé  On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Monday, January 25, 2021 10:21 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org;
> Paolo Bonzini 
> Cc: a...@rev.ng; alex.ben...@linaro.org; richard.hender...@linaro.org;
> laur...@vivier.eu; Brian Cain 
> Subject: Re: [PATCH v7 12/35] Hexagon (target/hexagon) instruction
> attributes
>
> >> On 1/20/21 4:28 AM, Taylor Simpson wrote:
> >>> Signed-off-by: Taylor Simpson 
> >>> ---
> >>>  target/hexagon/attribs.h | 30 ++
> >>>  target/hexagon/attribs_def.h | 95
> >> 
> >>>  2 files changed, 125 insertions(+)
> >>>  create mode 100644 target/hexagon/attribs.h
> >>>  create mode 100644 target/hexagon/attribs_def.h
> >>>
> >>> diff --git a/target/hexagon/attribs.h b/target/hexagon/attribs.h
> >>> new file mode 100644
> >>> index 000..e88e5eb
> >>> --- /dev/null
> >>> +++ b/target/hexagon/attribs.h
> >>> @@ -0,0 +1,30 @@
> >>> +
> >>> +enum {
> >>> +#define DEF_ATTRIB(NAME, ...) A_##NAME,
> >>> +#include "attribs_def.h"
> >>
> >> Per QEMU conventions, this file has to be named "attribs_def.h.inc".
> >
> > Didn't know that.  Which files should end in .inc?
>
> Oh you are right, it is not documented in CODING_STYLE.rst.
>
> You can see the rationale in commits:139c1837db7 and 0979ed017f0:
>
>   meson: rename included C source files to .c.inc
>
>   With Makefiles that have automatically generated dependencies, you
>   generated includes are set as dependencies of the Makefile, so that they
>   are built before everything else and they are available when first
>   building the .c files.
>
>   Alternatively you can use a fine-grained dependency, e.g.
>
>   target/arm/translate.o: target/arm/decode-neon-shared.inc.c
>
>   With Meson you have only one choice and it is a third option, namely
>   "build at the beginning of the corresponding target"; the way you
>   express it is to list the includes in the sources of that target.
>
>   The problem is that Meson decides if something is a source vs. a
>   generated include by looking at the extension: '.c', '.cc', '.m', '.C'
>   are sources, while everything else is considered an include---including
>   '.inc.c'.
>
>   Use '.c.inc' to avoid this, as it is consistent with our other convention
>   of using '.rst.inc' for included reStructuredText files.  The editorconfig
>   file is adjusted.

OK, I understand why it's better to have files end .[ch].inc than .inc.[ch].

However, I need some confirmation on which files need .inc instead of simply 
ending in .h.  From what I can tell these are the guidelines
- If a file is intended to be included in the middle of another file (as 
opposed to the top), it should end in .inc.
- If a .inc file is intended to be included in a .h file, it should end in 
.h.inc.
- If a .inc file is intended to be included in a .c file, it should end in 
.c.inc.
- The above applies to both human-written and generated files.

Thanks,
Taylor

Re: [PULL 00/13] Misc patches

[Peter Maydell]

On Fri, 29 Jan 2021 at 17:27, Daniel P. Berrangé  wrote:
>
> The following changes since commit 5101d00d2f1138a73344dc4833587f76d7a5fa5c:
>
>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-p=
> ull-request' into staging (2021-01-29 10:10:43 +)
>
> are available in the Git repository at:
>
>   https://gitlab.com/berrange/qemu tags/misc-fixes-pull-request
>
> for you to fetch changes up to ecb98f5c7589ba8ecd15c8b1baa2ec7192e47c75:
>
>   tests: Replace deprecated ASN1 code (2021-01-29 17:07:53 +)
>
> 
> * Replace --enable/disable-git-update with --with-git-submodules
>   to allow improved control over use of git submodules
> * Deprecate the -enable-fips option
> * Ensure docs use prefer format for bool options
> * Clarify platform support rules
> * Misc fixes to keymap conversions
> * Fix misc problems on macOS
>
> 



Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Re: [PATCH v2 1/2] pci: reject too large ROMs

[Peter Xu]

On Fri, Jan 29, 2021 at 08:28:37PM +0100, Paolo Bonzini wrote:
> get_image_size() returns an int64_t, which pci_add_option_rom() assigns
> to an "int" without any range checking.  A 32-bit BAR could be up to
> 2 GiB in size, so reject anything above it.  In order to accomodate
> a rounded-up size of 2 GiB, change pci_patch_ids's size argument
> to unsigned.
> 
> Signed-off-by: Paolo Bonzini 

Reviewed-by: Peter Xu 

-- 
Peter Xu

[RFC 09/10] vhost: Route guest->host notification through shadow virtqueue

[Eugenio Pérez]

Shadow virtqueue notifications forwarding is disabled when vhost_dev
stops.

Signed-off-by: Eugenio Pérez 
---
 hw/virtio/vhost-shadow-virtqueue.h |   5 ++
 include/hw/virtio/vhost.h  |   4 +
 hw/virtio/vhost-shadow-virtqueue.c | 123 +-
 hw/virtio/vhost.c  | 135 -
 4 files changed, 264 insertions(+), 3 deletions(-)

diff --git a/hw/virtio/vhost-shadow-virtqueue.h 
b/hw/virtio/vhost-shadow-virtqueue.h
index 6cc18d6acb..466f8ae595 100644
--- a/hw/virtio/vhost-shadow-virtqueue.h
+++ b/hw/virtio/vhost-shadow-virtqueue.h
@@ -17,6 +17,11 @@
 
 typedef struct VhostShadowVirtqueue VhostShadowVirtqueue;
 
+bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
+   VhostShadowVirtqueue *svq);
+void vhost_shadow_vq_stop_rcu(struct vhost_dev *dev,
+  VhostShadowVirtqueue *svq);
+
 VhostShadowVirtqueue *vhost_shadow_vq_new(struct vhost_dev *dev, int idx);
 
 void vhost_shadow_vq_free(VhostShadowVirtqueue *vq);
diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 2be782cefd..732a4b2a2b 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -55,6 +55,8 @@ struct vhost_iommu {
 QLIST_ENTRY(vhost_iommu) iommu_next;
 };
 
+typedef struct VhostShadowVirtqueue VhostShadowVirtqueue;
+
 typedef struct VhostDevConfigOps {
 /* Vhost device config space changed callback
  */
@@ -83,7 +85,9 @@ struct vhost_dev {
 uint64_t backend_cap;
 bool started;
 bool log_enabled;
+bool sw_lm_enabled;
 uint64_t log_size;
+VhostShadowVirtqueue **shadow_vqs;
 Error *migration_blocker;
 const VhostOps *vhost_ops;
 void *opaque;
diff --git a/hw/virtio/vhost-shadow-virtqueue.c 
b/hw/virtio/vhost-shadow-virtqueue.c
index c0c967a7c5..908c36c66d 100644
--- a/hw/virtio/vhost-shadow-virtqueue.c
+++ b/hw/virtio/vhost-shadow-virtqueue.c
@@ -8,15 +8,129 @@
  */
 
 #include "hw/virtio/vhost-shadow-virtqueue.h"
+#include "hw/virtio/vhost.h"
+#include "hw/virtio/virtio-access.h"
+
+#include "standard-headers/linux/vhost_types.h"
+#include "standard-headers/linux/virtio_ring.h"
 
 #include "qemu/error-report.h"
-#include "qemu/event_notifier.h"
+#include "qemu/main-loop.h"
 
 typedef struct VhostShadowVirtqueue {
 EventNotifier kick_notifier;
 EventNotifier call_notifier;
+const struct vhost_virtqueue *hvq;
+VirtIODevice *vdev;
+VirtQueue *vq;
 } VhostShadowVirtqueue;
 
+static uint16_t vhost_shadow_vring_used_flags(VhostShadowVirtqueue *svq)
+{
+const struct vring_used *used = svq->hvq->used;
+return virtio_tswap16(svq->vdev, used->flags);
+}
+
+static bool vhost_shadow_vring_should_kick(VhostShadowVirtqueue *vq)
+{
+return !(vhost_shadow_vring_used_flags(vq) & VRING_USED_F_NO_NOTIFY);
+}
+
+static void vhost_shadow_vring_kick(VhostShadowVirtqueue *vq)
+{
+if (vhost_shadow_vring_should_kick(vq)) {
+event_notifier_set(>kick_notifier);
+}
+}
+
+static void handle_shadow_vq(VirtIODevice *vdev, VirtQueue *vq)
+{
+struct vhost_dev *hdev = vhost_dev_from_virtio(vdev);
+uint16_t idx = virtio_get_queue_index(vq);
+
+VhostShadowVirtqueue *svq = hdev->shadow_vqs[idx];
+
+vhost_shadow_vring_kick(svq);
+}
+
+/*
+ * Start shadow virtqueue operation.
+ * @dev vhost device
+ * @svq Shadow Virtqueue
+ *
+ * Run in RCU context
+ */
+bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
+   VhostShadowVirtqueue *svq)
+{
+const VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(dev->vdev);
+EventNotifier *vq_host_notifier = virtio_queue_get_host_notifier(svq->vq);
+unsigned idx = virtio_queue_get_idx(svq->vdev, svq->vq);
+struct vhost_vring_file kick_file = {
+.index = idx,
+.fd = event_notifier_get_fd(>kick_notifier),
+};
+int r;
+bool ok;
+
+/* Check that notifications are still going directly to vhost dev */
+assert(virtio_queue_host_notifier_status(svq->vq));
+
+ok = k->set_vq_handler(dev->vdev, idx, handle_shadow_vq);
+if (!ok) {
+error_report("Couldn't set the vq handler");
+goto err_set_kick_handler;
+}
+
+r = dev->vhost_ops->vhost_set_vring_kick(dev, _file);
+if (r != 0) {
+error_report("Couldn't set kick fd: %s", strerror(errno));
+goto err_set_vring_kick;
+}
+
+event_notifier_set_handler(vq_host_notifier,
+   virtio_queue_host_notifier_read);
+virtio_queue_set_host_notifier_enabled(svq->vq, false);
+virtio_queue_host_notifier_read(vq_host_notifier);
+
+return true;
+
+err_set_vring_kick:
+k->set_vq_handler(dev->vdev, idx, NULL);
+
+err_set_kick_handler:
+return false;
+}
+
+/*
+ * Stop shadow virtqueue operation.
+ * @dev vhost device
+ * @svq Shadow Virtqueue
+ *
+ * Run in RCU context
+ */
+void vhost_shadow_vq_stop_rcu(struct vhost_dev *dev,
+  VhostShadowVirtqueue *svq)
+{
+

[RFC 08/10] vhost: Add x-vhost-enable-shadow-vq qmp

[Eugenio Pérez]

Command to enable shadow virtqueue looks like:

{ "execute": "x-vhost-enable-shadow-vq", "arguments": { "name": "dev0", 
"enable": true } }

Signed-off-by: Eugenio Pérez 
---
 qapi/net.json | 23 +++
 hw/virtio/vhost.c |  6 ++
 2 files changed, 29 insertions(+)

diff --git a/qapi/net.json b/qapi/net.json
index c31748c87f..6170d69798 100644
--- a/qapi/net.json
+++ b/qapi/net.json
@@ -77,6 +77,29 @@
 ##
 { 'command': 'netdev_del', 'data': {'id': 'str'} }
 
+##
+# @x-vhost-enable-shadow-vq:
+#
+# Use vhost shadow virtqueue.
+#
+# @name: the device name of the virtual network adapter
+#
+# @enable: true to use he alternate shadow VQ notification path
+#
+# Returns: Error if failure, or 'no error' for success
+#
+# Since: 5.3
+#
+# Example:
+#
+# -> { "execute": "x-vhost_enable_shadow_vq", "arguments": {"enable": true} }
+# <- { "return": { "enabled" : true } }
+#
+##
+{ 'command': 'x-vhost-enable-shadow-vq',
+  'data': {'name': 'str', 'enable': 'bool'},
+  'if': 'defined(CONFIG_VHOST_KERNEL)' }
+
 ##
 # @NetLegacyNicOptions:
 #
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 040f68ff2e..42836e45f3 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -15,6 +15,7 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "qapi/qapi-commands-net.h"
 #include "hw/virtio/vhost.h"
 #include "qemu/atomic.h"
 #include "qemu/range.h"
@@ -1841,3 +1842,8 @@ int vhost_net_set_backend(struct vhost_dev *hdev,
 
 return -1;
 }
+
+void qmp_x_vhost_enable_shadow_vq(const char *name, bool enable, Error **errp)
+{
+error_setg(errp, "Shadow virtqueue still not implemented.");
+}
-- 
2.27.0

[RFC 06/10] vhost: Save masked_notifier state

[Eugenio Pérez]

It will be used to recover call eventfd.

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/vhost.h | 1 +
 hw/virtio/vhost.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index fca076e3f0..2be782cefd 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -28,6 +28,7 @@ struct vhost_virtqueue {
 unsigned avail_size;
 unsigned long long used_phys;
 unsigned used_size;
+bool notifier_is_masked;
 EventNotifier masked_notifier;
 struct vhost_dev *dev;
 };
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 8683d507f5..040f68ff2e 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -1526,6 +1526,8 @@ void vhost_virtqueue_mask(struct vhost_dev *hdev, 
VirtIODevice *vdev, int n,
 /* should only be called after backend is connected */
 assert(hdev->vhost_ops);
 
+hdev->vqs[index].notifier_is_masked = mask;
+
 if (mask) {
 assert(vdev->use_guest_notifier_mask);
 file.fd = event_notifier_get_fd(>vqs[index].masked_notifier);
-- 
2.27.0

[RFC 04/10] virtio: Add virtio_queue_host_notifier_status

[Eugenio Pérez]

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/virtio.h | 1 +
 hw/virtio/virtio.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index 9013c03424..c5fcd9b169 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -321,6 +321,7 @@ void virtio_device_release_ioeventfd(VirtIODevice *vdev);
 bool virtio_device_ioeventfd_enabled(VirtIODevice *vdev);
 EventNotifier *virtio_queue_get_host_notifier(VirtQueue *vq);
 void virtio_queue_set_host_notifier_enabled(VirtQueue *vq, bool enabled);
+bool virtio_queue_host_notifier_status(const VirtQueue *vq);
 void virtio_queue_host_notifier_read(EventNotifier *n);
 void virtio_queue_aio_set_host_notifier_handler(VirtQueue *vq, AioContext *ctx,
 VirtIOHandleAIOOutput 
handle_output);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 3d14b0ef74..fdf37d8e48 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -3613,6 +3613,11 @@ EventNotifier *virtio_queue_get_host_notifier(VirtQueue 
*vq)
 return >host_notifier;
 }
 
+bool virtio_queue_host_notifier_status(const VirtQueue *vq)
+{
+return vq->host_notifier_enabled;
+}
+
 void virtio_queue_set_host_notifier_enabled(VirtQueue *vq, bool enabled)
 {
 vq->host_notifier_enabled = enabled;
-- 
2.27.0

[RFC 10/10] vhost: Route host->guest notification through shadow virtqueue

[Eugenio Pérez]

Signed-off-by: Eugenio Pérez 
---
 hw/virtio/vhost-shadow-virtqueue.h |  2 ++
 hw/virtio/vhost-shadow-virtqueue.c | 55 ++
 hw/virtio/vhost.c  |  5 ++-
 3 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/hw/virtio/vhost-shadow-virtqueue.h 
b/hw/virtio/vhost-shadow-virtqueue.h
index 466f8ae595..99a4e011fd 100644
--- a/hw/virtio/vhost-shadow-virtqueue.h
+++ b/hw/virtio/vhost-shadow-virtqueue.h
@@ -17,6 +17,8 @@
 
 typedef struct VhostShadowVirtqueue VhostShadowVirtqueue;
 
+EventNotifier *vhost_shadow_vq_get_call_notifier(VhostShadowVirtqueue *vq);
+
 bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
VhostShadowVirtqueue *svq);
 void vhost_shadow_vq_stop_rcu(struct vhost_dev *dev,
diff --git a/hw/virtio/vhost-shadow-virtqueue.c 
b/hw/virtio/vhost-shadow-virtqueue.c
index 908c36c66d..e2e0bfe325 100644
--- a/hw/virtio/vhost-shadow-virtqueue.c
+++ b/hw/virtio/vhost-shadow-virtqueue.c
@@ -53,6 +53,34 @@ static void handle_shadow_vq(VirtIODevice *vdev, VirtQueue 
*vq)
 vhost_shadow_vring_kick(svq);
 }
 
+static void vhost_handle_call(EventNotifier *n)
+{
+VhostShadowVirtqueue *svq = container_of(n, VhostShadowVirtqueue,
+ call_notifier);
+
+if (event_notifier_test_and_clear(n)) {
+unsigned idx = virtio_queue_get_idx(svq->vdev, svq->vq);
+
+/*
+ * Since QEMU has not add any descriptors, virtqueue code thinks its
+ * not needed to signal used. QEMU shadow virtqueue will take
+ * descriptor forwarding soon, so just invalidate used cache for now.
+ */
+virtio_queue_invalidate_signalled_used(svq->vdev, idx);
+virtio_notify_irqfd(svq->vdev, svq->vq);
+}
+}
+
+/*
+ * Get the vhost call notifier of the shadow vq
+ * @vq Shadow virtqueue
+ */
+EventNotifier *vhost_shadow_vq_get_call_notifier(VhostShadowVirtqueue *vq)
+{
+return >call_notifier;
+}
+
+
 /*
  * Start shadow virtqueue operation.
  * @dev vhost device
@@ -70,6 +98,10 @@ bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
 .index = idx,
 .fd = event_notifier_get_fd(>kick_notifier),
 };
+struct vhost_vring_file call_file = {
+.index = idx,
+.fd = event_notifier_get_fd(>call_notifier),
+};
 int r;
 bool ok;
 
@@ -88,6 +120,12 @@ bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
 goto err_set_vring_kick;
 }
 
+r = dev->vhost_ops->vhost_set_vring_call(dev, _file);
+if (r != 0) {
+error_report("Couldn't set call fd: %s", strerror(errno));
+goto err_set_vring_call;
+}
+
 event_notifier_set_handler(vq_host_notifier,
virtio_queue_host_notifier_read);
 virtio_queue_set_host_notifier_enabled(svq->vq, false);
@@ -95,6 +133,11 @@ bool vhost_shadow_vq_start_rcu(struct vhost_dev *dev,
 
 return true;
 
+err_set_vring_call:
+kick_file.fd = event_notifier_get_fd(vq_host_notifier);
+r = dev->vhost_ops->vhost_set_vring_kick(dev, _file);
+assert(r == 0);
+
 err_set_vring_kick:
 k->set_vq_handler(dev->vdev, idx, NULL);
 
@@ -129,6 +172,17 @@ void vhost_shadow_vq_stop_rcu(struct vhost_dev *dev,
 event_notifier_set_handler(vq_host_notifier, NULL);
 virtio_queue_set_host_notifier_enabled(svq->vq, true);
 k->set_vq_handler(svq->vdev, idx, NULL);
+
+if (!dev->vqs[idx].notifier_is_masked) {
+EventNotifier *e = vhost_shadow_vq_get_call_notifier(svq);
+
+/* Restore vhost call */
+vhost_virtqueue_mask(dev, svq->vdev, idx, false);
+if (event_notifier_test_and_clear(e)) {
+virtio_queue_invalidate_signalled_used(svq->vdev, idx);
+virtio_notify_irqfd(svq->vdev, svq->vq);
+}
+}
 }
 
 /*
@@ -159,6 +213,7 @@ VhostShadowVirtqueue *vhost_shadow_vq_new(struct vhost_dev 
*dev, int idx)
 goto err_init_call_notifier;
 }
 
+event_notifier_set_handler(>call_notifier, vhost_handle_call);
 return g_steal_pointer();
 
 err_init_call_notifier:
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index bde688f278..5ad0990509 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -984,7 +984,6 @@ static int vhost_sw_live_migration_start(struct vhost_dev 
*dev)
 int stop_idx = idx;
 bool ok = vhost_shadow_vq_start_rcu(dev,
 dev->shadow_vqs[idx]);
-
 if (!ok) {
 while (--stop_idx >= 0) {
 vhost_shadow_vq_stop_rcu(dev, dev->shadow_vqs[stop_idx]);
@@ -1610,6 +1609,10 @@ void vhost_virtqueue_mask(struct vhost_dev *hdev, 
VirtIODevice *vdev, int n,
 if (mask) {
 assert(vdev->use_guest_notifier_mask);
 file.fd = event_notifier_get_fd(>vqs[index].masked_notifier);
+} else if (hdev->sw_lm_enabled) {
+VhostShadowVirtqueue *svq = hdev->shadow_vqs[n];
+EventNotifier *e = 

[RFC 07/10] vhost: Add VhostShadowVirtqueue

[Eugenio Pérez]

Vhost shadow virtqueue is an intermediate jump for virtqueue
notifications and buffers, allowing qemu to track them.

Signed-off-by: Eugenio Pérez 
---
 hw/virtio/vhost-shadow-virtqueue.h | 24 
 hw/virtio/vhost-shadow-virtqueue.c | 60 ++
 hw/virtio/meson.build  |  2 +-
 3 files changed, 85 insertions(+), 1 deletion(-)
 create mode 100644 hw/virtio/vhost-shadow-virtqueue.h
 create mode 100644 hw/virtio/vhost-shadow-virtqueue.c

diff --git a/hw/virtio/vhost-shadow-virtqueue.h 
b/hw/virtio/vhost-shadow-virtqueue.h
new file mode 100644
index 00..6cc18d6acb
--- /dev/null
+++ b/hw/virtio/vhost-shadow-virtqueue.h
@@ -0,0 +1,24 @@
+/*
+ * vhost software live migration ring
+ *
+ * SPDX-FileCopyrightText: Red Hat, Inc. 2021
+ * SPDX-FileContributor: Author: Eugenio Pérez 
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef VHOST_SHADOW_VIRTQUEUE_H
+#define VHOST_SHADOW_VIRTQUEUE_H
+
+#include "qemu/osdep.h"
+
+#include "hw/virtio/virtio.h"
+#include "hw/virtio/vhost.h"
+
+typedef struct VhostShadowVirtqueue VhostShadowVirtqueue;
+
+VhostShadowVirtqueue *vhost_shadow_vq_new(struct vhost_dev *dev, int idx);
+
+void vhost_shadow_vq_free(VhostShadowVirtqueue *vq);
+
+#endif
diff --git a/hw/virtio/vhost-shadow-virtqueue.c 
b/hw/virtio/vhost-shadow-virtqueue.c
new file mode 100644
index 00..c0c967a7c5
--- /dev/null
+++ b/hw/virtio/vhost-shadow-virtqueue.c
@@ -0,0 +1,60 @@
+/*
+ * vhost software live migration ring
+ *
+ * SPDX-FileCopyrightText: Red Hat, Inc. 2021
+ * SPDX-FileContributor: Author: Eugenio Pérez 
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "hw/virtio/vhost-shadow-virtqueue.h"
+
+#include "qemu/error-report.h"
+#include "qemu/event_notifier.h"
+
+typedef struct VhostShadowVirtqueue {
+EventNotifier kick_notifier;
+EventNotifier call_notifier;
+} VhostShadowVirtqueue;
+
+/*
+ * Creates vhost shadow virtqueue, and instruct vhost device to use the shadow
+ * methods and file descriptors.
+ */
+VhostShadowVirtqueue *vhost_shadow_vq_new(struct vhost_dev *dev, int idx)
+{
+g_autofree VhostShadowVirtqueue *svq = g_new0(VhostShadowVirtqueue, 1);
+int r;
+
+r = event_notifier_init(>kick_notifier, 0);
+if (r != 0) {
+error_report("Couldn't create kick event notifier: %s",
+ strerror(errno));
+goto err_init_kick_notifier;
+}
+
+r = event_notifier_init(>call_notifier, 0);
+if (r != 0) {
+error_report("Couldn't create call event notifier: %s",
+ strerror(errno));
+goto err_init_call_notifier;
+}
+
+return svq;
+
+err_init_call_notifier:
+event_notifier_cleanup(>kick_notifier);
+
+err_init_kick_notifier:
+return NULL;
+}
+
+/*
+ * Free the resources of the shadow virtqueue.
+ */
+void vhost_shadow_vq_free(VhostShadowVirtqueue *vq)
+{
+event_notifier_cleanup(>kick_notifier);
+event_notifier_cleanup(>call_notifier);
+g_free(vq);
+}
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index fbff9bc9d4..8b5a0225fe 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -11,7 +11,7 @@ softmmu_ss.add(when: 'CONFIG_ALL', if_true: 
files('vhost-stub.c'))
 
 virtio_ss = ss.source_set()
 virtio_ss.add(files('virtio.c'))
-virtio_ss.add(when: 'CONFIG_VHOST', if_true: files('vhost.c', 
'vhost-backend.c'))
+virtio_ss.add(when: 'CONFIG_VHOST', if_true: files('vhost.c', 
'vhost-backend.c', 'vhost-shadow-virtqueue.c'))
 virtio_ss.add(when: 'CONFIG_VHOST_USER', if_true: files('vhost-user.c'))
 virtio_ss.add(when: 'CONFIG_VHOST_VDPA', if_true: files('vhost-vdpa.c'))
 virtio_ss.add(when: 'CONFIG_VIRTIO_BALLOON', if_true: 
files('virtio-balloon.c'))
-- 
2.27.0

[RFC 05/10] vhost: Add vhost_dev_from_virtio

[Eugenio Pérez]

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/vhost.h |  1 +
 hw/virtio/vhost.c | 17 +
 2 files changed, 18 insertions(+)

diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h
index 4a8bc75415..fca076e3f0 100644
--- a/include/hw/virtio/vhost.h
+++ b/include/hw/virtio/vhost.h
@@ -123,6 +123,7 @@ uint64_t vhost_get_features(struct vhost_dev *hdev, const 
int *feature_bits,
 void vhost_ack_features(struct vhost_dev *hdev, const int *feature_bits,
 uint64_t features);
 bool vhost_has_free_slot(void);
+struct vhost_dev *vhost_dev_from_virtio(const VirtIODevice *vdev);
 
 int vhost_net_set_backend(struct vhost_dev *hdev,
   struct vhost_vring_file *file);
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 28c7d78172..8683d507f5 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -61,6 +61,23 @@ bool vhost_has_free_slot(void)
 return slots_limit > used_memslots;
 }
 
+/*
+ * Get the vhost device associated to a VirtIO device.
+ */
+struct vhost_dev *vhost_dev_from_virtio(const VirtIODevice *vdev)
+{
+struct vhost_dev *hdev;
+
+QLIST_FOREACH(hdev, _devices, entry) {
+if (hdev->vdev == vdev) {
+return hdev;
+}
+}
+
+assert(hdev);
+return NULL;
+}
+
 static void vhost_dev_sync_region(struct vhost_dev *dev,
   MemoryRegionSection *section,
   uint64_t mfirst, uint64_t mlast,
-- 
2.27.0

[RFC 02/10] virtio: Add set_vq_handler

[Eugenio Pérez]

So other subsystem can override vq handler and device can reset it.

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/virtio.h |  5 +
 hw/net/virtio-net.c| 26 ++
 2 files changed, 31 insertions(+)

diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index 9b5479e256..9988c6d5c9 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -149,6 +149,11 @@ struct VirtioDeviceClass {
 void (*guest_notifier_mask)(VirtIODevice *vdev, int n, bool mask);
 int (*start_ioeventfd)(VirtIODevice *vdev);
 void (*stop_ioeventfd)(VirtIODevice *vdev);
+/*
+ * Set handler for a vq. NULL handler for reset to default.
+ */
+bool (*set_vq_handler)(VirtIODevice *vdev, unsigned int n,
+   VirtIOHandleOutput handle_output);
 /* Saving and loading of a device; trying to deprecate save/load
  * use vmsd for new devices.
  */
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 5150f295e8..f7b2998fb1 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -2699,6 +2699,31 @@ static void virtio_net_set_multiqueue(VirtIONet *n, int 
multiqueue)
 virtio_net_set_queues(n);
 }
 
+static bool virtio_net_set_vq_handler(VirtIODevice *vdev, unsigned int i,
+  VirtIOHandleOutput handle_output)
+{
+const VirtIONet *n = VIRTIO_NET(vdev);
+const unsigned max_queues = n->multiqueue ? n->max_queues : 1;
+VirtQueue *vq;
+
+/* Reset control queue also not supported */
+assert(i < max_queues * 2);
+
+vq = virtio_get_queue(vdev, i);
+if (handle_output == NULL) {
+if (i % 2) {
+handle_output = virtio_net_handle_rx;
+} else {
+const VirtIONetQueue *q = >vqs[i / 2];
+handle_output = q->tx_timer ? virtio_net_handle_tx_timer
+: virtio_net_handle_tx_bh;
+}
+}
+
+virtqueue_set_handler(vq, handle_output);
+return true;
+}
+
 static int virtio_net_post_load_device(void *opaque, int version_id)
 {
 VirtIONet *n = opaque;
@@ -3519,6 +3544,7 @@ static void virtio_net_class_init(ObjectClass *klass, 
void *data)
 vdc->set_status = virtio_net_set_status;
 vdc->guest_notifier_mask = virtio_net_guest_notifier_mask;
 vdc->guest_notifier_pending = virtio_net_guest_notifier_pending;
+vdc->set_vq_handler = virtio_net_set_vq_handler;
 vdc->legacy_features |= (0x1 << VIRTIO_NET_F_GSO);
 vdc->post_load = virtio_net_post_load_virtio;
 vdc->vmsd = _virtio_net_device;
-- 
2.27.0

[RFC 03/10] virtio: Add virtio_queue_get_idx

[Eugenio Pérez]

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/virtio.h | 2 ++
 hw/virtio/virtio.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index 9988c6d5c9..9013c03424 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -399,6 +399,8 @@ static inline bool virtio_device_disabled(VirtIODevice 
*vdev)
 return unlikely(vdev->disabled || vdev->broken);
 }
 
+unsigned virtio_queue_get_idx(const VirtIODevice *vdev, const VirtQueue *vq);
+
 bool virtio_legacy_allowed(VirtIODevice *vdev);
 bool virtio_legacy_check_disabled(VirtIODevice *vdev);
 
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index ebb780fb42..3d14b0ef74 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -500,6 +500,11 @@ void virtio_queue_set_notification(VirtQueue *vq, int 
enable)
 }
 }
 
+unsigned virtio_queue_get_idx(const VirtIODevice *vdev, const VirtQueue *vq)
+{
+return vq - vdev->vq;
+}
+
 int virtio_queue_ready(VirtQueue *vq)
 {
 return vq->vring.avail != 0;
-- 
2.27.0

[RFC 00/10] vDPA shadow virtqueue - notifications forwarding

[Eugenio Pérez]

This series enable vhost (And vhost-vdpa) notifications forwarding for
software assisted live migration, implemented through a shadow
virtqueue.

Shadow virtqueue is a new method of tracking memory for migration:
Instead of relay on vDPA device's dirty logging capability, SW assisted
LM intercepts dataplane, forwarding the descriptors between VM and
device.

In this migration mode, qemu offers a new (shadow) vring to the device
to read and write into, and forwards descriptors between host vring
and qemu one. On used buffer relay, qemu will mark the dirty memory as
with plain virtio-net devices. This way, devices does not need to have
dirty page logging capability.

This RFC series just enables just the notifications forwarding part,
not buffer forwarding/tracking.

It is based on the ideas of DPDK SW assisted LM, in the series of
DPDK's https://patchwork.dpdk.org/cover/48370/ , but will use memory in
qemu Virtual Address Space for rings, instead of in guest's.

Main changes from previous RFC [1] are:
* Use QMP to enable. Can disable through QMP too.
* Do not use vhost_dev_{enable,disable}_notifiers, since they override
  the VM ioeventfd set, and could cause race conditions. Do never modify
  irqfd or ioeventfd used for the guest.

Comments are welcome.

Thanks!

[1] https://patchew.org/QEMU/20201120185105.279030-1-epere...@redhat.com/

Eugenio Pérez (10):
  virtio: Add virtqueue_set_handler
  virtio: Add set_vq_handler
  virtio: Add virtio_queue_get_idx
  virtio: Add virtio_queue_host_notifier_status
  vhost: Add vhost_dev_from_virtio
  vhost: Save masked_notifier state
  vhost: Add VhostShadowVirtqueue
  vhost: Add x-vhost-enable-shadow-vq qmp
  vhost: Route guest->host notification through shadow virtqueue
  vhost: Route host->guest notification through shadow virtqueue

 qapi/net.json  |  23 +++
 hw/virtio/vhost-shadow-virtqueue.h |  31 
 include/hw/virtio/vhost.h  |   6 +
 include/hw/virtio/virtio.h |  14 +-
 hw/net/virtio-net.c|  26 
 hw/virtio/vhost-shadow-virtqueue.c | 234 +
 hw/virtio/vhost.c  | 161 
 hw/virtio/virtio.c |  24 +++
 hw/virtio/meson.build  |   2 +-
 9 files changed, 517 insertions(+), 4 deletions(-)
 create mode 100644 hw/virtio/vhost-shadow-virtqueue.h
 create mode 100644 hw/virtio/vhost-shadow-virtqueue.c

-- 
2.27.0

[RFC 01/10] virtio: Add virtqueue_set_handler

[Eugenio Pérez]

This allows qemu to override vq handler.

Signed-off-by: Eugenio Pérez 
---
 include/hw/virtio/virtio.h |  6 +++---
 hw/virtio/virtio.c | 14 ++
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index b7ece7a6a8..9b5479e256 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -47,6 +47,8 @@ size_t virtio_feature_get_config_size(VirtIOFeature *features,
   uint64_t host_features);
 
 typedef struct VirtQueue VirtQueue;
+typedef void (*VirtIOHandleOutput)(VirtIODevice *, VirtQueue *);
+typedef bool (*VirtIOHandleAIOOutput)(VirtIODevice *, VirtQueue *);
 
 #define VIRTQUEUE_MAX_SIZE 1024
 
@@ -174,9 +176,6 @@ void virtio_error(VirtIODevice *vdev, const char *fmt, ...) 
GCC_FMT_ATTR(2, 3);
 /* Set the child bus name. */
 void virtio_device_set_child_bus_name(VirtIODevice *vdev, char *bus_name);
 
-typedef void (*VirtIOHandleOutput)(VirtIODevice *, VirtQueue *);
-typedef bool (*VirtIOHandleAIOOutput)(VirtIODevice *, VirtQueue *);
-
 VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size,
 VirtIOHandleOutput handle_output);
 
@@ -184,6 +183,7 @@ void virtio_del_queue(VirtIODevice *vdev, int n);
 
 void virtio_delete_queue(VirtQueue *vq);
 
+void virtqueue_set_handler(VirtQueue *vq, VirtIOHandleOutput handler);
 void virtqueue_push(VirtQueue *vq, const VirtQueueElement *elem,
 unsigned int len);
 void virtqueue_flush(VirtQueue *vq, unsigned int count);
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index b308026596..ebb780fb42 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1796,6 +1796,20 @@ unsigned int virtqueue_drop_all(VirtQueue *vq)
 }
 }
 
+/*
+ * virtqueue_set_handler:
+ * @vq The #VirtQueue
+ * @handler The handler to call on vq event
+ * Replaces vq handler.
+ *
+ * Note: It takes no protection, so make sure no other calls to the handler
+ * are happening.
+ */
+void virtqueue_set_handler(VirtQueue *vq, VirtIOHandleOutput handler)
+{
+vq->handle_output = handler;
+}
+
 /* Reading and writing a structure directly to QEMUFile is *awful*, but
  * it is what QEMU has always done by mistake.  We can change it sooner
  * or later by bumping the version number of the affected vm states.
-- 
2.27.0

Re: [PATCH v3] tcg: Fix execution on Apple Silicon

[Roman Bolshakov]

On Fri, Jan 29, 2021 at 10:18:58AM -1000, Richard Henderson wrote:
> On 1/21/21 8:34 AM, Richard Henderson wrote:
> > On 1/12/21 5:28 PM, Roman Bolshakov wrote:
> >> @@ -1083,6 +1083,12 @@ static bool alloc_code_gen_buffer_anon(size_t size, 
> >> int prot,
> >>  {
> >>  void *buf;
> >>  
> >> +#if defined(MAC_OS_VERSION_11_0) && \
> >> +MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
> >> +if (__builtin_available(macOS 11.0, *)) {
> >> +flags |= MAP_JIT;
> >> +}
> >> +#endif
> > 
> > This hunk should be in alloc_code_gen_buffer, where we do the other flags
> > manipulation.
> > 
> > I'll drop this hunk and apply the rest, which is exclusively related to
> > toggling the jit bit.
> 
> Ping on this?
> 
Hi Richard,

> I would imagine that the patch would look something like
> 
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -1296,6 +1296,11 @@ static bool alloc_code_gen_buffer
>  #ifdef CONFIG_TCG_INTERPRETER
>  /* The tcg interpreter does not need execute permission. */
>  prot = PROT_READ | PROT_WRITE;
> +#elif defined(MAC_OS_VERSION_11_0) && \
> +MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
> +if (__builtin_available(macOS 11.0, *)) {
> +flags |= MAP_JIT;
> +}
>  #elif defined(CONFIG_DARWIN)
>  /* Applicable to both iOS and macOS (Apple Silicon). */
>  if (!splitwx) {
> 
> But I don't know how CONFIG_DARWIN, iOS, and MAC_OS_VERSION interact, and I'm
> not able to even compile-test the patch.
> Certainly the final comment there looks suspicious, given the preceding MAC_OS
> stanza...
> 

I thought you already added MAP_JIT in 6f70ddee19e. It's getting enabled
on my M1 laptop. Was it intended or not?

/* Applicable to both iOS and macOS (Apple Silicon). */
if (!splitwx) {
flags |= MAP_JIT;
}

TCG from master branch of QEMU works fine on M1. I'm not sure why do we
need to duplicate it.

Thanks,
Roman

Re: [PATCH v3 00/24] tcg: backend constraints cleanup

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20210129201028.787853-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210129201028.787853-1-richard.hender...@linaro.org
Subject: [PATCH v3 00/24] tcg: backend constraints cleanup

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag] 
patchew/20210129201028.787853-1-richard.hender...@linaro.org -> 
patchew/20210129201028.787853-1-richard.hender...@linaro.org
Auto packing the repository for optimum performance. You may also
run "git gc" manually. See "git help gc" for more information.
Switched to a new branch 'test'
99968b1 tcg: Remove TCG_TARGET_CON_SET_H
f4db259 tcg/tci: Split out constraint sets to tcg-target-con-set.h
0f05bc5 tcg/sparc: Split out constraint sets to tcg-target-con-set.h
6877c98 tcg/s390: Split out constraint sets to tcg-target-con-set.h
2e37d8d tcg/riscv: Split out constraint sets to tcg-target-con-set.h
c6ec388 tcg/ppc: Split out constraint sets to tcg-target-con-set.h
9785a4f tcg/mips: Split out constraint sets to tcg-target-con-set.h
c347e78 tcg/arm: Split out constraint sets to tcg-target-con-set.h
b868c9a tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
a792388 tcg/i386: Split out constraint sets to tcg-target-con-set.h
96c2084 tcg: Remove TCG_TARGET_CON_STR_H
5197aa7 tcg/sparc: Split out target constraints to tcg-target-con-str.h
dee58ce tcg/s390: Split out target constraints to tcg-target-con-str.h
8bdfd7d tcg/riscv: Split out target constraints to tcg-target-con-str.h
5574bf9 tcg/mips: Split out target constraints to tcg-target-con-str.h
ef40966 tcg/tci: Split out target constraints to tcg-target-con-str.h
109e507 tcg/ppc: Split out target constraints to tcg-target-con-str.h
fd98327 tcg/aarch64: Split out target constraints to tcg-target-con-str.h
fd76598 tcg/arm: Split out target constraints to tcg-target-con-str.h
d8bdc37 tcg/i386: Split out target constraints to tcg-target-con-str.h
d1febe5 tcg/i386: Tidy register constraint definitions
8768867 tcg/i386: Move constraint type check to tcg_target_const_match
6d85b0e tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
c1a401c tcg/tci: Drop L and S constraints

=== OUTPUT BEGIN ===
1/24 Checking commit c1a401cedd92 (tcg/tci: Drop L and S constraints)
2/24 Checking commit 6d85b0e6c1ae (tcg/tci: Remove TCG_TARGET_HAS_* ifdefs)
3/24 Checking commit 8768867ab61f (tcg/i386: Move constraint type check to 
tcg_target_const_match)
4/24 Checking commit d1febe5a517c (tcg/i386: Tidy register constraint 
definitions)
5/24 Checking commit d8bdc376cf31 (tcg/i386: Split out target constraints to 
tcg-target-con-str.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#22: 
new file mode 100644

ERROR: Macros with multiple statements should be enclosed in a do - while loop
#191: FILE: tcg/tcg.c:2471:
+#define CONST(CASE, MASK) \
+case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;

ERROR: trailing statements should be on next line
#192: FILE: tcg/tcg.c:2472:
+case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;

ERROR: Macros with multiple statements should be enclosed in a do - while loop
#193: FILE: tcg/tcg.c:2473:
+#define REGS(CASE, MASK) \
+case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;

ERROR: trailing statements should be on next line
#194: FILE: tcg/tcg.c:2474:
+case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;

total: 4 errors, 1 warnings, 175 lines checked

Patch 5/24 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

6/24 Checking commit fd76598d1908 (tcg/arm: Split out target constraints to 
tcg-target-con-str.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17: 
new file mode 100644

total: 0 errors, 1 warnings, 111 lines checked

Patch 6/24 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/24 Checking commit fd98327bcedb (tcg/aarch64: Split out target constraints to 
tcg-target-con-str.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17: 
new file mode 100644

total: 0 errors, 1 warnings, 89 lines checked

Patch 7/24 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/24 Checking commit 109e5079eec2 (tcg/ppc: Split out target constraints to 
tcg-target-con-str.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17: 
new file mode 100644

[PATCH v3 24/24] tcg: Remove TCG_TARGET_CON_SET_H

[Richard Henderson]

All backends have now been converted to tcg-target-con-set.h,
so we can remove the fallback code.

Reviewed-by: Peter Maydell 
Reviewed-by: Alistair Francis 
Signed-off-by: Richard Henderson 
---
 tcg/aarch64/tcg-target.h |  1 -
 tcg/arm/tcg-target.h |  1 -
 tcg/i386/tcg-target.h|  1 -
 tcg/mips/tcg-target.h|  1 -
 tcg/ppc/tcg-target.h |  1 -
 tcg/riscv/tcg-target.h   |  1 -
 tcg/s390/tcg-target.h|  1 -
 tcg/sparc/tcg-target.h   |  1 -
 tcg/tci/tcg-target.h |  2 --
 tcg/tcg.c| 12 
 10 files changed, 22 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 200e9b5e0e..5ec30dba25 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -155,6 +155,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 4d201b1216..8d1fee6327 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -142,6 +142,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 48a6f2a336..b693d3692d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e520a9d6e3..c2c32fb38f 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,6 +207,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 551f8d0fc9..d1339afc66 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index a998b951e4..727c8df418 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -171,6 +171,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 7aafd25a46..641464eea4 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,6 +159,5 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f50e8d50ee..f66f5d07dc 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -168,6 +168,5 @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 1efd8c4fb0..bb784e018e 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -207,6 +207,4 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 /* no need to flush icache explicitly */
 }
 
-#define TCG_TARGET_CON_SET_H
-
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index df9f32763e..63a12b197b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -69,9 +69,6 @@
 /* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
 static void tcg_target_init(TCGContext *s);
-#ifndef TCG_TARGET_CON_SET_H
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
-#endif
 static void tcg_target_qemu_prologue(TCGContext *s);
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 intptr_t value, intptr_t addend);
@@ -349,7 +346,6 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
 s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
 }
 
-#ifdef TCG_TARGET_CON_SET_H
 #define C_PFX1(P, A)P##A
 #define C_PFX2(P, A, B) P##A##_##B
 #define C_PFX3(P, A, B, C)  P##A##_##B##_##C
@@ -453,8 +449,6 @@ static const TCGTargetOpDef constraint_sets[] = {
 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, 
I4)
 

[PATCH v3 21/24] tcg/s390: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target-con-set.h |  29 
 tcg/s390/tcg-target.h |   1 +
 tcg/s390/tcg-target.c.inc | 121 ++
 3 files changed, 81 insertions(+), 70 deletions(-)
 create mode 100644 tcg/s390/tcg-target-con-set.h

diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h
new file mode 100644
index 00..31985e4903
--- /dev/null
+++ b/tcg/s390/tcg-target-con-set.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 641464eea4..7aafd25a46 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 3fec7fec5f..b67470137c 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
 }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
-static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
-static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
-static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
-static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
-static const TCGTargetOpDef a2_r
-= { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
-static const TCGTargetOpDef a2_ri
-= { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
-static const TCGTargetOpDef a2_rA
-= { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8u_i64:
@@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_ld32u_i64:
 case INDEX_op_ld32s_i64:
 case INDEX_op_ld_i64:
+return C_O1_I1(r, r);
+
 case INDEX_op_st8_i32:
 case INDEX_op_st8_i64:
 case INDEX_op_st16_i32:
@@ -2315,11 +2301,22 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_st_i32:
 case INDEX_op_st32_i64:
 case INDEX_op_st_i64:
-return _r;
+return C_O0_I2(r, r);
 
 case INDEX_op_add_i32:
 case INDEX_op_add_i64:
-return _r_ri;
+case INDEX_op_shl_i64:
+case INDEX_op_shr_i64:
+case INDEX_op_sar_i64:
+case INDEX_op_rotl_i32:
+case INDEX_op_rotl_i64:
+case INDEX_op_rotr_i32:
+case INDEX_op_rotr_i64:
+case INDEX_op_clz_i64:
+case INDEX_op_setcond_i32:
+case INDEX_op_setcond_i64:
+return C_O1_I2(r, r, ri);
+
 case INDEX_op_sub_i32:
 case INDEX_op_sub_i64:
 case INDEX_op_and_i32:
@@ -2328,35 +2325,33 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_or_i64:
 case INDEX_op_xor_i32:
 case INDEX_op_xor_i64:
-return (s390_facilities & FACILITY_DISTINCT_OPS ? _r_ri : _0_ri);
+return (s390_facilities & FACILITY_DISTINCT_OPS
+? C_O1_I2(r, r, ri)
+: C_O1_I2(r, 0, ri));
 
 case INDEX_op_mul_i32:
 /* If we have the general-instruction-extensions, then we have
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit.  */
-return (s390_facilities & FACILITY_GEN_INST_EXT ? _0_ri : _0_rI);
+return (s390_facilities & FACILITY_GEN_INST_EXT
+? C_O1_I2(r, 0, ri)
+: C_O1_I2(r, 0, rI));
+
 case 

Re: [PATCH v3] tcg: Fix execution on Apple Silicon

[Richard Henderson]

On 1/21/21 8:34 AM, Richard Henderson wrote:
> On 1/12/21 5:28 PM, Roman Bolshakov wrote:
>> @@ -1083,6 +1083,12 @@ static bool alloc_code_gen_buffer_anon(size_t size, 
>> int prot,
>>  {
>>  void *buf;
>>  
>> +#if defined(MAC_OS_VERSION_11_0) && \
>> +MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
>> +if (__builtin_available(macOS 11.0, *)) {
>> +flags |= MAP_JIT;
>> +}
>> +#endif
> 
> This hunk should be in alloc_code_gen_buffer, where we do the other flags
> manipulation.
> 
> I'll drop this hunk and apply the rest, which is exclusively related to
> toggling the jit bit.

Ping on this?

I would imagine that the patch would look something like

--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1296,6 +1296,11 @@ static bool alloc_code_gen_buffer
 #ifdef CONFIG_TCG_INTERPRETER
 /* The tcg interpreter does not need execute permission. */
 prot = PROT_READ | PROT_WRITE;
+#elif defined(MAC_OS_VERSION_11_0) && \
+MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_VERSION_11_0
+if (__builtin_available(macOS 11.0, *)) {
+flags |= MAP_JIT;
+}
 #elif defined(CONFIG_DARWIN)
 /* Applicable to both iOS and macOS (Apple Silicon). */
 if (!splitwx) {

But I don't know how CONFIG_DARWIN, iOS, and MAC_OS_VERSION interact, and I'm
not able to even compile-test the patch.
Certainly the final comment there looks suspicious, given the preceding MAC_OS
stanza...


r~

[PATCH v3 17/24] tcg/arm: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/arm/tcg-target-con-set.h | 35 ++
 tcg/arm/tcg-target.h |  1 +
 tcg/arm/tcg-target.c.inc | 94 
 3 files changed, 68 insertions(+), 62 deletions(-)
 create mode 100644 tcg/arm/tcg-target-con-set.h

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
new file mode 100644
index 00..ab63e089c2
--- /dev/null
+++ b/tcg/arm/tcg-target-con-set.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Arm target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, rIN)
+C_O0_I2(s, s)
+C_O0_I3(s, s, s)
+C_O0_I4(r, r, rI, rI)
+C_O0_I4(s, s, s, s)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, l, l)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rIN)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, r, r, rI, rI)
+C_O1_I4(r, r, rIN, rIK, 0)
+C_O2_I1(r, r, l)
+C_O2_I2(r, r, l, l)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, rIN, rIK)
+C_O2_I4(r, r, rI, rI, rIN, rIK)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 8d1fee6327..4d201b1216 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index bbd41d2491..8457108a87 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2036,57 +2036,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
 }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
-static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
-static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
-static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
-static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
-static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-static const TCGTargetOpDef r_r_rIN
-= { .args_ct_str = { "r", "r", "rIN" } };
-static const TCGTargetOpDef r_r_rIK
-= { .args_ct_str = { "r", "r", "rIK" } };
-static const TCGTargetOpDef r_r_r_r
-= { .args_ct_str = { "r", "r", "r", "r" } };
-static const TCGTargetOpDef r_r_l_l
-= { .args_ct_str = { "r", "r", "l", "l" } };
-static const TCGTargetOpDef s_s_s_s
-= { .args_ct_str = { "s", "s", "s", "s" } };
-static const TCGTargetOpDef br
-= { .args_ct_str = { "r", "rIN" } };
-static const TCGTargetOpDef ext2
-= { .args_ct_str = { "r", "rZ", "rZ" } };
-static const TCGTargetOpDef dep
-= { .args_ct_str = { "r", "0", "rZ" } };
-static const TCGTargetOpDef movc
-= { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
-static const TCGTargetOpDef add2
-= { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
-static const TCGTargetOpDef sub2
-= { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
-static const TCGTargetOpDef br2
-= { .args_ct_str = { "r", "r", "rI", "rI" } };
-static const TCGTargetOpDef setc2
-= { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
 case INDEX_op_ld16u_i32:
 case INDEX_op_ld16s_i32:
 case INDEX_op_ld_i32:
-case INDEX_op_st8_i32:
-case INDEX_op_st16_i32:
-case INDEX_op_st_i32:
 case INDEX_op_neg_i32:
 case INDEX_op_not_i32:
 case INDEX_op_bswap16_i32:
@@ -2096,62 +2056,72 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_ext16u_i32:
 case INDEX_op_extract_i32:
 case INDEX_op_sextract_i32:
-return _r;
+return C_O1_I1(r, r);
+
+case INDEX_op_st8_i32:
+case INDEX_op_st16_i32:
+case INDEX_op_st_i32:
+return C_O0_I2(r, r);
 
 case INDEX_op_add_i32:
 case INDEX_op_sub_i32:
 case INDEX_op_setcond_i32:
-return _r_rIN;
+return C_O1_I2(r, r, 

Re: [PATCH v2 2/2] pci: add romsize property

[Paolo Bonzini]

On 29/01/21 21:06, BALATON Zoltan wrote:
The empty property value configures the device not to have a ROM file 
at all. The commit message says that ROM files (if they exist) cannot 
be empty, corresponding to this code in pci_add_option_rom:


   } else if (size == 0) {
   error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
   g_free(path);
   return;
   }


OK, then it was just not clear to me that the commit message talks about 
the romfile itself and not the property.


By the way, does it make sense to compare uint32_t value to -1 and could 
that provoke some compiler/sanitiser warnings? Is it better to have a 
signed type or use UINT32_MAX or simlar instead?


There is probably some warning for it but I think not even -Wextra 
enables it by default.


Paolo

[PATCH v3 16/24] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/aarch64/tcg-target-con-set.h | 36 +
 tcg/aarch64/tcg-target.h |  1 +
 tcg/aarch64/tcg-target.c.inc | 86 +++-
 3 files changed, 65 insertions(+), 58 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-set.h

diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h
new file mode 100644
index 00..d6c6866878
--- /dev/null
+++ b/tcg/aarch64/tcg-target-con-set.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Define AArch64 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(lZ, l)
+C_O0_I2(r, rA)
+C_O0_I2(rZ, r)
+C_O0_I2(w, r)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, w)
+C_O1_I1(w, wr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rA)
+C_O1_I2(r, r, rAL)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rL)
+C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
+C_O1_I2(w, w, w)
+C_O1_I2(w, w, wN)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
+C_O1_I4(r, r, rA, rZ, rZ)
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 5ec30dba25..200e9b5e0e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 42037c98fa..3c1ee39fd4 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2547,42 +2547,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, 
unsigned vece,
 va_end(va);
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
-static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
-static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
-static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
-static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
-static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
-static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
-static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
-static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
-static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
-static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
-static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
-static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
-static const TCGTargetOpDef r_r_rAL
-= { .args_ct_str = { "r", "r", "rAL" } };
-static const TCGTargetOpDef dep
-= { .args_ct_str = { "r", "0", "rZ" } };
-static const TCGTargetOpDef ext2
-= { .args_ct_str = { "r", "rZ", "rZ" } };
-static const TCGTargetOpDef movc
-= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
-static const TCGTargetOpDef add2
-= { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
-static const TCGTargetOpDef w_w_w_w
-= { .args_ct_str = { "w", "w", "w", "w" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
@@ -2621,7 +2590,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_extract_i64:
 case INDEX_op_sextract_i32:
 case INDEX_op_sextract_i64:
-return _r;
+return C_O1_I1(r, r);
 
 case INDEX_op_st8_i32:
 case INDEX_op_st16_i32:
@@ -2630,7 +2599,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_st16_i64:
 case INDEX_op_st32_i64:
 case INDEX_op_st_i64:
-return _r;
+return C_O0_I2(rZ, r);
 
 case INDEX_op_add_i32:
 case INDEX_op_add_i64:
@@ -2638,7 +2607,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_sub_i64:
 case 

[PATCH v3 19/24] tcg/ppc: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/ppc/tcg-target-con-set.h |  42 +++
 tcg/ppc/tcg-target.h |   1 +
 tcg/ppc/tcg-target.c.inc | 136 +++
 3 files changed, 99 insertions(+), 80 deletions(-)
 create mode 100644 tcg/ppc/tcg-target-con-set.h

diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
new file mode 100644
index 00..a1a345883d
--- /dev/null
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define PowerPC target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(S, S)
+C_O0_I2(v, r)
+C_O0_I3(S, S, S)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(S, S, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I1(v, r)
+C_O1_I1(v, v)
+C_O1_I1(v, vr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, rI, ri)
+C_O1_I2(r, rI, rT)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rT)
+C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rZW)
+C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
+C_O1_I4(r, r, ri, rZ, rZ)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(L, L, L)
+C_O2_I2(L, L, L, L)
+C_O2_I4(r, r, rI, rZM, r, r)
+C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index d1339afc66..551f8d0fc9 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index e5aa8d2d10..4377d15d62 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3456,62 +3456,17 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, 
unsigned vece,
 va_end(va);
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
-static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
-static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
-static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
-static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
-static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
-static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
-static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
-static const TCGTargetOpDef r_rI_ri
-= { .args_ct_str = { "r", "rI", "ri" } };
-static const TCGTargetOpDef r_rI_rT
-= { .args_ct_str = { "r", "rI", "rT" } };
-static const TCGTargetOpDef r_r_rZW
-= { .args_ct_str = { "r", "r", "rZW" } };
-static const TCGTargetOpDef L_L_L_L
-= { .args_ct_str = { "L", "L", "L", "L" } };
-static const TCGTargetOpDef S_S_S_S
-= { .args_ct_str = { "S", "S", "S", "S" } };
-static const TCGTargetOpDef movc
-= { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
-static const TCGTargetOpDef dep
-= { .args_ct_str = { "r", "0", "rZ" } };
-static const TCGTargetOpDef br2
-= { .args_ct_str = { "r", "r", "ri", "ri" } };
-static const TCGTargetOpDef setc2
-= { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
-static const TCGTargetOpDef add2
-= { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
-static const TCGTargetOpDef sub2
-= { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
-static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
-static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
-static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
-static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
-static const TCGTargetOpDef v_v_v_v
-= { .args_ct_str = { "v", "v", "v", "v" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
 case INDEX_op_ld16u_i32:
 case INDEX_op_ld16s_i32:
 case INDEX_op_ld_i32:
-case INDEX_op_st8_i32:
-case INDEX_op_st16_i32:
-case INDEX_op_st_i32:
  

[PATCH v3 23/24] tcg/tci: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

This requires finishing the conversion to tcg_target_op_def.

Signed-off-by: Richard Henderson 
---
 tcg/tci/tcg-target-con-set.h |  25 
 tcg/tci/tcg-target.h |   2 +
 tcg/tci/tcg-target.c.inc | 279 +--
 3 files changed, 161 insertions(+), 145 deletions(-)
 create mode 100644 tcg/tci/tcg-target-con-set.h

diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
new file mode 100644
index 00..38e82f7535
--- /dev/null
+++ b/tcg/tci/tcg-target-con-set.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * TCI target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I3(r, r, r)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(r, r, r, r)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, ri, ri)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, r)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index bb784e018e..1efd8c4fb0 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -207,4 +207,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 /* no need to flush icache explicitly */
 }
 
+#define TCG_TARGET_CON_SET_H
+
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 493bbf1e39..62bedaca28 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -37,154 +37,143 @@
 /* Bitfield n...m (in 32 bit value). */
 #define BITS(n, m) (((0xU << (31 - n)) >> (31 - n + m)) << m)
 
-/* Macros used in tcg_target_op_defs. */
-#define R   "r"
-#define RI  "ri"
-#if TCG_TARGET_REG_BITS == 32
-# define R64"r", "r"
-#else
-# define R64"r"
-#endif
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L  "r", "r"
-# define S  "r", "r"
-#else
-# define L  "r"
-# define S  "r"
-#endif
-
-/* TODO: documentation. */
-static const TCGTargetOpDef tcg_target_op_defs[] = {
-{ INDEX_op_exit_tb, { NULL } },
-{ INDEX_op_goto_tb, { NULL } },
-{ INDEX_op_br, { NULL } },
-
-{ INDEX_op_ld8u_i32, { R, R } },
-{ INDEX_op_ld8s_i32, { R, R } },
-{ INDEX_op_ld16u_i32, { R, R } },
-{ INDEX_op_ld16s_i32, { R, R } },
-{ INDEX_op_ld_i32, { R, R } },
-{ INDEX_op_st8_i32, { R, R } },
-{ INDEX_op_st16_i32, { R, R } },
-{ INDEX_op_st_i32, { R, R } },
-
-{ INDEX_op_add_i32, { R, RI, RI } },
-{ INDEX_op_sub_i32, { R, RI, RI } },
-{ INDEX_op_mul_i32, { R, RI, RI } },
-{ INDEX_op_div_i32, { R, R, R } },
-{ INDEX_op_divu_i32, { R, R, R } },
-{ INDEX_op_rem_i32, { R, R, R } },
-{ INDEX_op_remu_i32, { R, R, R } },
-/* TODO: Does R, RI, RI result in faster code than R, R, RI?
-   If both operands are constants, we can optimize. */
-{ INDEX_op_and_i32, { R, RI, RI } },
-{ INDEX_op_andc_i32, { R, RI, RI } },
-{ INDEX_op_eqv_i32, { R, RI, RI } },
-{ INDEX_op_nand_i32, { R, RI, RI } },
-{ INDEX_op_nor_i32, { R, RI, RI } },
-{ INDEX_op_or_i32, { R, RI, RI } },
-{ INDEX_op_orc_i32, { R, RI, RI } },
-{ INDEX_op_xor_i32, { R, RI, RI } },
-{ INDEX_op_shl_i32, { R, RI, RI } },
-{ INDEX_op_shr_i32, { R, RI, RI } },
-{ INDEX_op_sar_i32, { R, RI, RI } },
-{ INDEX_op_rotl_i32, { R, RI, RI } },
-{ INDEX_op_rotr_i32, { R, RI, RI } },
-{ INDEX_op_deposit_i32, { R, "0", R } },
-
-{ INDEX_op_brcond_i32, { R, RI } },
-
-{ INDEX_op_setcond_i32, { R, R, RI } },
-{ INDEX_op_setcond_i64, { R, R, RI } },
-
-/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
-{ INDEX_op_add2_i32, { R, R, R, R, R, R } },
-{ INDEX_op_sub2_i32, { R, R, R, R, R, R } },
-{ INDEX_op_brcond2_i32, { R, R, RI, RI } },
-{ INDEX_op_mulu2_i32, { R, R, R, R } },
-{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-
-{ INDEX_op_not_i32, { R, R } },
-{ INDEX_op_neg_i32, { R, R } },
-
-{ INDEX_op_ld8u_i64, { R, R } },
-{ INDEX_op_ld8s_i64, { R, R } },
-{ INDEX_op_ld16u_i64, { R, R } },
-{ INDEX_op_ld16s_i64, { R, R } },
-{ INDEX_op_ld32u_i64, { R, R } },
-{ INDEX_op_ld32s_i64, { R, R } },
-{ INDEX_op_ld_i64, { R, R } },
-
-{ INDEX_op_st8_i64, { R, R } },
-{ INDEX_op_st16_i64, { R, R } },
-{ INDEX_op_st32_i64, { R, R } },
-{ INDEX_op_st_i64, { R, R } },
-
-{ INDEX_op_add_i64, { R, RI, RI } },
-{ INDEX_op_sub_i64, { R, RI, RI } },
-{ INDEX_op_mul_i64, { R, RI, RI } },
-{ INDEX_op_div_i64, { R, R, R } },
-{ INDEX_op_divu_i64, { R, R, R } },
-{ INDEX_op_rem_i64, { R, R, R } },
-{ INDEX_op_remu_i64, { R, R, R } },
-{ INDEX_op_and_i64, { R, RI, RI } },
-{ INDEX_op_andc_i64, { R, RI, RI } },
-{ INDEX_op_eqv_i64, { 

[PATCH v3 14/24] tcg: Remove TCG_TARGET_CON_STR_H

[Richard Henderson]

All backends have now been converted to tcg-target-con-str.h,
so we can remove the fallback code.

Reviewed-by: Peter Maydell 
Reviewed-by: Alistair Francis 
Signed-off-by: Richard Henderson 
---
 tcg/aarch64/tcg-target.h |  1 -
 tcg/arm/tcg-target.h |  1 -
 tcg/i386/tcg-target.h|  1 -
 tcg/mips/tcg-target.h|  1 -
 tcg/ppc/tcg-target.h |  1 -
 tcg/riscv/tcg-target.h   |  1 -
 tcg/s390/tcg-target.h|  1 -
 tcg/sparc/tcg-target.h   |  1 -
 tcg/tci/tcg-target.h |  2 --
 tcg/tcg.c| 16 
 10 files changed, 26 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 4fc20b58ec..5ec30dba25 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -155,6 +155,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 16336cd545..8d1fee6327 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -142,6 +142,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 77693e13ea..b693d3692d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index d850200855..c2c32fb38f 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,6 +207,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 40ed4b82dd..d1339afc66 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index daf3ef7b5c..727c8df418 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -171,6 +171,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index c43d6aba84..641464eea4 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,6 +159,5 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 5185b00524..f66f5d07dc 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -168,6 +168,5 @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index ab832aecc3..bb784e018e 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -207,6 +207,4 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 /* no need to flush icache explicitly */
 }
 
-#define TCG_TARGET_CON_STR_H
-
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8cfa28ed84..39bcdff8dc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -103,10 +103,6 @@ static void tcg_register_jit_int(const void *buf, size_t 
size,
 __attribute__((unused));
 
 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
-#ifndef TCG_TARGET_CON_STR_H
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type);
-#endif
 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2);
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -2464,7 +2460,6 @@ static void process_op_defs(TCGContext *s)
 ct_str++;
 break;
 
-#ifdef TCG_TARGET_CON_STR_H
 /* Include all of the target-specific constraints. */
 
 #undef CONST
@@ -2480,17 +2475,6 @@ static void process_op_defs(TCGContext *s)
 default:
 /* Typo in TCGTargetOpDef constraint. */
   

[PATCH v3 18/24] tcg/mips: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/mips/tcg-target-con-set.h | 36 +
 tcg/mips/tcg-target.h |  1 +
 tcg/mips/tcg-target.c.inc | 96 +++
 3 files changed, 66 insertions(+), 67 deletions(-)
 create mode 100644 tcg/mips/tcg-target-con-set.h

diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
new file mode 100644
index 00..fe3e868a2f
--- /dev/null
+++ b/tcg/mips/tcg-target-con-set.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I2(SZ, S)
+C_O0_I3(SZ, S, S)
+C_O0_I3(SZ, SZ, S)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O0_I4(SZ, SZ, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rJ)
+C_O1_I2(r, r, rWZ)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, 0)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, rZ, rZ, rN, rN)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..e520a9d6e3 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 432d38a010..ab55f3109b 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2112,52 +2112,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
 }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
-static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
-static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
-static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
-static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
-static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
-static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
-static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
-static const TCGTargetOpDef SZ_SZ_S
-= { .args_ct_str = { "SZ", "SZ", "S" } };
-static const TCGTargetOpDef SZ_SZ_S_S
-= { .args_ct_str = { "SZ", "SZ", "S", "S" } };
-static const TCGTargetOpDef r_rZ_rN
-= { .args_ct_str = { "r", "rZ", "rN" } };
-static const TCGTargetOpDef r_rZ_rZ
-= { .args_ct_str = { "r", "rZ", "rZ" } };
-static const TCGTargetOpDef r_r_rIK
-= { .args_ct_str = { "r", "r", "rIK" } };
-static const TCGTargetOpDef r_r_rWZ
-= { .args_ct_str = { "r", "r", "rWZ" } };
-static const TCGTargetOpDef r_r_r_r
-= { .args_ct_str = { "r", "r", "r", "r" } };
-static const TCGTargetOpDef r_r_L_L
-= { .args_ct_str = { "r", "r", "L", "L" } };
-static const TCGTargetOpDef dep
-= { .args_ct_str = { "r", "0", "rZ" } };
-static const TCGTargetOpDef movc
-= { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
-static const TCGTargetOpDef movc_r6
-= { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-static const TCGTargetOpDef add2
-= { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
-static const TCGTargetOpDef br2
-= { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
-static const TCGTargetOpDef setc2
-= { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
@@ -2190,7 +2149,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_extrl_i64_i32:
 case INDEX_op_extrh_i64_i32:
 case INDEX_op_extract_i64:
-return _r;
+return C_O1_I1(r, r);
 
 case INDEX_op_st8_i32:
 case INDEX_op_st16_i32:
@@ -2199,14 +2158,14 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_st16_i64:
 case INDEX_op_st32_i64:
 case INDEX_op_st_i64:
-   

[PATCH v3 22/24] tcg/sparc: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/sparc/tcg-target-con-set.h | 32 +++
 tcg/sparc/tcg-target.h |  1 +
 tcg/sparc/tcg-target.c.inc | 75 +++---
 3 files changed, 56 insertions(+), 52 deletions(-)
 create mode 100644 tcg/sparc/tcg-target-con-set.h

diff --git a/tcg/sparc/tcg-target-con-set.h b/tcg/sparc/tcg-target-con-set.h
new file mode 100644
index 00..3b751dc3fb
--- /dev/null
+++ b/tcg/sparc/tcg-target-con-set.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Sparc target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(RZ, r)
+C_O0_I2(rZ, rJ)
+C_O0_I2(RZ, RJ)
+C_O0_I2(sZ, A)
+C_O0_I2(SZ, A)
+C_O1_I1(r, A)
+C_O1_I1(R, A)
+C_O1_I1(r, r)
+C_O1_I1(r, R)
+C_O1_I1(R, r)
+C_O1_I1(R, R)
+C_O1_I2(R, R, R)
+C_O1_I2(r, rZ, rJ)
+C_O1_I2(R, RZ, RJ)
+C_O1_I4(r, rZ, rJ, rI, 0)
+C_O1_I4(R, RZ, RJ, RI, 0)
+C_O2_I2(r, r, rZ, rJ)
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f66f5d07dc..f50e8d50ee 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -168,5 +168,6 @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index e291eb0b95..3d50f985c6 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -1573,40 +1573,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
-static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
-static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
-static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
-static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
-static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
-static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
-static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
-static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
-static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
-static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
-static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
-static const TCGTargetOpDef r_rZ_rJ
-= { .args_ct_str = { "r", "rZ", "rJ" } };
-static const TCGTargetOpDef R_RZ_RJ
-= { .args_ct_str = { "R", "RZ", "RJ" } };
-static const TCGTargetOpDef r_r_rZ_rJ
-= { .args_ct_str = { "r", "r", "rZ", "rJ" } };
-static const TCGTargetOpDef movc_32
-= { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
-static const TCGTargetOpDef movc_64
-= { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
-static const TCGTargetOpDef add2_32
-= { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
-static const TCGTargetOpDef add2_64
-= { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
@@ -1615,12 +1586,12 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_ld_i32:
 case INDEX_op_neg_i32:
 case INDEX_op_not_i32:
-return _r;
+return C_O1_I1(r, r);
 
 case INDEX_op_st8_i32:
 case INDEX_op_st16_i32:
 case INDEX_op_st_i32:
-return _r;
+return C_O0_I2(rZ, r);
 
 case INDEX_op_add_i32:
 case INDEX_op_mul_i32:
@@ -1636,18 +1607,18 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_shr_i32:
 case INDEX_op_sar_i32:
 case INDEX_op_setcond_i32:
-return _rZ_rJ;
+return C_O1_I2(r, rZ, rJ);
 
 case INDEX_op_brcond_i32:
-return _rJ;
+return C_O0_I2(rZ, rJ);
 case INDEX_op_movcond_i32:
-return _32;
+return C_O1_I4(r, rZ, rJ, rI, 0);
 case INDEX_op_add2_i32:
 case INDEX_op_sub2_i32:
-return _32;
+return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
 case INDEX_op_mulu2_i32:
 case INDEX_op_muls2_i32:
-return _r_rZ_rJ;
+return C_O2_I2(r, r, rZ, rJ);
 

[PATCH v3 13/24] tcg/sparc: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 tcg/sparc/tcg-target-con-str.h | 23 ++
 tcg/sparc/tcg-target.h |  5 +--
 tcg/sparc/tcg-target.c.inc | 81 +-
 3 files changed, 55 insertions(+), 54 deletions(-)
 create mode 100644 tcg/sparc/tcg-target-con-str.h

diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h
new file mode 100644
index 00..fdb25d9313
--- /dev/null
+++ b/tcg/sparc/tcg-target-con-str.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Sparc target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('R', ALL_GENERAL_REGS64)
+REGS('s', ALL_QLDST_REGS)
+REGS('S', ALL_QLDST_REGS64)
+REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S11)
+CONST('J', TCG_CT_CONST_S13)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 95ab9af955..5185b00524 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -66,10 +66,6 @@ typedef enum {
 TCG_REG_I7,
 } TCGReg;
 
-#define TCG_CT_CONST_S11  0x100
-#define TCG_CT_CONST_S13  0x200
-#define TCG_CT_CONST_ZERO 0x400
-
 /* used for function call generation */
 #define TCG_REG_CALL_STACK TCG_REG_O6
 
@@ -172,5 +168,6 @@ extern bool use_vis3_instructions;
 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 28b5b6559a..e291eb0b95 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -67,18 +67,38 @@ static const char * const 
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 # define SPARC64 0
 #endif
 
-/* Note that sparcv8plus can only hold 64 bit quantities in %g and %o
-   registers.  These are saved manually by the kernel in full 64-bit
-   slots.  The %i and %l registers are saved by the register window
-   mechanism, which only allocates space for 32 bits.  Given that this
-   window spill/fill can happen on any signal, we must consider the
-   high bits of the %i and %l registers garbage at all times.  */
-#if SPARC64
-# define ALL_64  0xu
+#define TCG_CT_CONST_S11  0x100
+#define TCG_CT_CONST_S13  0x200
+#define TCG_CT_CONST_ZERO 0x400
+
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
 #else
-# define ALL_64  0xu
+#define SOFTMMU_RESERVE_REGS 0
 #endif
 
+/*
+ * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
+ * registers.  These are saved manually by the kernel in full 64-bit
+ * slots.  The %i and %l registers are saved by the register window
+ * mechanism, which only allocates space for 32 bits.  Given that this
+ * window spill/fill can happen on any signal, we must consider the
+ * high bits of the %i and %l registers garbage at all times.
+ */
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
+#if SPARC64
+# define ALL_GENERAL_REGS64  ALL_GENERAL_REGS
+#else
+# define ALL_GENERAL_REGS64  MAKE_64BIT_MASK(0, 16)
+#endif
+#define ALL_QLDST_REGS   (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+#define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
+
 /* Define some temporary registers.  T2 is used for constant generation.  */
 #define TCG_REG_T1  TCG_REG_G1
 #define TCG_REG_T2  TCG_REG_O7
@@ -320,45 +340,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 return true;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'r':
-ct->regs = 0x;
-break;
-case 'R':
-ct->regs = ALL_64;
-break;
-case 'A': /* qemu_ld/st address constraint */
-ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0x;
-reserve_helpers:
-tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
-tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
-break;
-case 's': /* qemu_st data 32-bit constraint */
-ct->regs = 0x;
-goto reserve_helpers;
-case 'S': /* qemu_st data 64-bit constraint */
-ct->regs = ALL_64;
-goto reserve_helpers;
-case 'I':
-ct->ct |= TCG_CT_CONST_S11;
-break;
-case 'J':
-ct->ct |= TCG_CT_CONST_S13;
-break;
-case 'Z':
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}

[PATCH v3 10/24] tcg/mips: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Richard Henderson 
---
 tcg/mips/tcg-target-con-str.h | 24 +++
 tcg/mips/tcg-target.h |  1 +
 tcg/mips/tcg-target.c.inc | 77 ++-
 3 files changed, 46 insertions(+), 56 deletions(-)
 create mode 100644 tcg/mips/tcg-target-con-str.h

diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
new file mode 100644
index 00..e4b2965c72
--- /dev/null
+++ b/tcg/mips/tcg-target-con-str.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_U16)
+CONST('J', TCG_CT_CONST_S16)
+CONST('K', TCG_CT_CONST_P2M1)
+CONST('N', TCG_CT_CONST_N16)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..d850200855 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #ifdef CONFIG_SOFTMMU
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 7293169ab2..432d38a010 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -171,67 +171,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_N16  0x1000   /* "Negatable" 16-bit: -32767 - 32767 */
 #define TCG_CT_CONST_WSZ  0x2000   /* word size */
 
+#define ALL_GENERAL_REGS  0xu
+#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+(NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
+#define ALL_QSTORE_REGS \
+(NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS   \
+   ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3)  \
+   : (1 << TCG_REG_A1)))
+#else
+#define ALL_QLOAD_REGS   NOA0_REGS
+#define ALL_QSTORE_REGS  NOA0_REGS
+#endif
+
+
 static inline bool is_p2m1(tcg_target_long val)
 {
 return val && ((val + 1) & val) == 0;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch(*ct_str++) {
-case 'r':
-ct->regs = 0x;
-break;
-case 'L': /* qemu_ld input arg constraint */
-ct->regs = 0x;
-tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-}
-#endif
-break;
-case 'S': /* qemu_st constraint */
-ct->regs = 0x;
-tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
-if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
-tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
-} else {
-tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
-}
-#endif
-break;
-case 'I':
-ct->ct |= TCG_CT_CONST_U16;
-break;
-case 'J':
-ct->ct |= TCG_CT_CONST_S16;
-break;
-case 'K':
-ct->ct |= TCG_CT_CONST_P2M1;
-break;
-case 'N':
-ct->ct |= TCG_CT_CONST_N16;
-break;
-case 'W':
-ct->ct |= TCG_CT_CONST_WSZ;
-break;
-case 'Z':
-/* We are cheating a bit here, using the fact that the register
-   ZERO is also the register number 0. Hence there is no need
-   to check for const_args in each instruction. */
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
  const TCGArgConstraint *arg_ct)
@@ -1697,6 +1657,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode 
opc,
 TCGArg a0, a1, a2;
 int c2;
 
+/*
+ * Note that many operands use the constraint set "rZ".
+ * We make use of the fact that 0 is the ZERO register,
+ * and hence such cases need not check for const_args.
+ */
 a0 = args[0];
 a1 = args[1];
 a2 = args[2];
-- 
2.25.1

[PATCH v3 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/i386/tcg-target-con-set.h |  55 ++
 tcg/i386/tcg-target.h |   1 +
 tcg/tcg.c | 119 +
 tcg/i386/tcg-target.c.inc | 194 --
 4 files changed, 242 insertions(+), 127 deletions(-)
 create mode 100644 tcg/i386/tcg-target-con-set.h

diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
new file mode 100644
index 00..78774d1005
--- /dev/null
+++ b/tcg/i386/tcg-target-con-set.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define i386 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ *
+ * C_N1_Im(...) defines a constraint set with 1 output and  inputs,
+ * except that the output must use a new register.
+ */
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(qi, r)
+C_O0_I2(re, r)
+C_O0_I2(ri, r)
+C_O0_I2(r, re)
+C_O0_I2(s, L)
+C_O0_I2(x, r)
+C_O0_I3(L, L, L)
+C_O0_I3(s, L, L)
+C_O0_I4(L, L, L, L)
+C_O0_I4(r, r, ri, ri)
+C_O1_I1(r, 0)
+C_O1_I1(r, L)
+C_O1_I1(r, q)
+C_O1_I1(r, r)
+C_O1_I1(x, r)
+C_O1_I1(x, x)
+C_O1_I2(Q, 0, Q)
+C_O1_I2(q, r, re)
+C_O1_I2(r, 0, ci)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, 0, re)
+C_O1_I2(r, 0, reZ)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, re)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(x, x, x)
+C_N1_I2(r, r, r)
+C_N1_I2(r, r, rW)
+C_O1_I3(x, x, x, x)
+C_O1_I4(r, r, re, r, 0)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(r, r, L)
+C_O2_I2(a, d, a, r)
+C_O2_I2(r, r, L, L)
+C_O2_I3(a, d, 0, 1, r)
+C_O2_I4(r, r, 0, 1, re, re)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b693d3692d..48a6f2a336 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 39bcdff8dc..df9f32763e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -69,7 +69,9 @@
 /* Forward declarations for functions declared in tcg-target.c.inc and
used here. */
 static void tcg_target_init(TCGContext *s);
+#ifndef TCG_TARGET_CON_SET_H
 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
+#endif
 static void tcg_target_qemu_prologue(TCGContext *s);
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 intptr_t value, intptr_t addend);
@@ -347,6 +349,112 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
 s->tb_jmp_reset_offset[which] = tcg_current_code_size(s);
 }
 
+#ifdef TCG_TARGET_CON_SET_H
+#define C_PFX1(P, A)P##A
+#define C_PFX2(P, A, B) P##A##_##B
+#define C_PFX3(P, A, B, C)  P##A##_##B##_##C
+#define C_PFX4(P, A, B, C, D)   P##A##_##B##_##C##_##D
+#define C_PFX5(P, A, B, C, D, E)P##A##_##B##_##C##_##D##_##E
+#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
+
+/* Define an enumeration for the various combinations. */
+
+#define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1),
+#define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2),
+#define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3),
+#define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4),
+
+#define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1),
+#define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2),
+#define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3),
+#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
+
+#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
+
+#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
+#define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2),
+#define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3),
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, 
I4),
+
+typedef enum {
+#include "tcg-target-con-set.h"
+} TCGConstraintSetIndex;
+
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+/* Put all of the constraint sets into an array, indexed by the enum. */
+
+#define C_O0_I1(I1) { .args_ct_str = { #I1 } },
+#define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } },
+#define C_O0_I3(I1, I2, I3) 

[PATCH v3 11/24] tcg/riscv: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Signed-off-by: Richard Henderson 
---
 tcg/riscv/tcg-target-con-str.h | 21 ++
 tcg/riscv/tcg-target.h |  1 +
 tcg/riscv/tcg-target.c.inc | 52 +-
 3 files changed, 35 insertions(+), 39 deletions(-)
 create mode 100644 tcg/riscv/tcg-target-con-str.h

diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
new file mode 100644
index 00..8d8afaee53
--- /dev/null
+++ b/tcg/riscv/tcg-target-con-str.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define RISC-V target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S12)
+CONST('N', TCG_CT_CONST_N12)
+CONST('M', TCG_CT_CONST_M12)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 727c8df418..daf3ef7b5c 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 71c0badc02..20d5b5ef01 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -122,6 +122,19 @@ static const int tcg_target_call_oarg_regs[] = {
 #define TCG_CT_CONST_N12   0x400
 #define TCG_CT_CONST_M12   0x800
 
+#define ALL_GENERAL_REGS  MAKE_64BIT_MASK(0, 32)
+/*
+ * For softmmu, we need to avoid conflicts with the first 5
+ * argument registers to call the helper.  Some of these are
+ * also used for the tlb lookup.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
+#else
+#define SOFTMMU_RESERVE_REGS  0
+#endif
+
+
 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 {
 if (TCG_TARGET_REG_BITS == 32) {
@@ -131,45 +144,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, 
int pos, int len)
 }
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'r':
-ct->regs = 0x;
-break;
-case 'L':
-/* qemu_ld/qemu_st constraint */
-ct->regs = 0x;
-/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
-#if defined(CONFIG_SOFTMMU)
-tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
-tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
-tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
-tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
-tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
-#endif
-break;
-case 'I':
-ct->ct |= TCG_CT_CONST_S12;
-break;
-case 'N':
-ct->ct |= TCG_CT_CONST_N12;
-break;
-case 'M':
-ct->ct |= TCG_CT_CONST_M12;
-break;
-case 'Z':
-/* we can use a zero immediate as a zero register argument. */
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
   const TCGArgConstraint *arg_ct)
-- 
2.25.1

[PATCH v3 08/24] tcg/ppc: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/ppc/tcg-target-con-str.h | 30 +++
 tcg/ppc/tcg-target.h |  1 +
 tcg/ppc/tcg-target.c.inc | 73 
 3 files changed, 46 insertions(+), 58 deletions(-)
 create mode 100644 tcg/ppc/tcg-target-con-str.h

diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
new file mode 100644
index 00..298ca20d5b
--- /dev/null
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define PowerPC target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('v', ALL_VECTOR_REGS)
+REGS('A', 1u << TCG_REG_R3)
+REGS('B', 1u << TCG_REG_R4)
+REGS('C', 1u << TCG_REG_R5)
+REGS('D', 1u << TCG_REG_R6)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_U16)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('T', TCG_CT_CONST_S32)
+CONST('U', TCG_CT_CONST_U32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index d1339afc66..40ed4b82dd 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index cf64892295..e5aa8d2d10 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -62,6 +62,21 @@
 #define TCG_CT_CONST_MONE 0x2000
 #define TCG_CT_CONST_WSZ  0x4000
 
+#define ALL_GENERAL_REGS  0xu
+#define ALL_VECTOR_REGS   0xull
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+(ALL_GENERAL_REGS & \
+ ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5)))
+#define ALL_QSTORE_REGS \
+(ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \
+  (1 << TCG_REG_R5) | (1 << TCG_REG_R6)))
+#else
+#define ALL_QLOAD_REGS  (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3))
+#define ALL_QSTORE_REGS ALL_QLOAD_REGS
+#endif
+
 TCGPowerISA have_isa;
 static bool have_isel;
 bool have_altivec;
@@ -222,64 +237,6 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const 
tcg_insn_unit *target)
 return false;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'A': case 'B': case 'C': case 'D':
-tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
-break;
-case 'r':
-ct->regs = 0x;
-break;
-case 'v':
-ct->regs = 0xull;
-break;
-case 'L':   /* qemu_ld constraint */
-ct->regs = 0x;
-tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
-tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
-#endif
-break;
-case 'S':   /* qemu_st constraint */
-ct->regs = 0x;
-tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#ifdef CONFIG_SOFTMMU
-tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
-#endif
-break;
-case 'I':
-ct->ct |= TCG_CT_CONST_S16;
-break;
-case 'J':
-ct->ct |= TCG_CT_CONST_U16;
-break;
-case 'M':
-ct->ct |= TCG_CT_CONST_MONE;
-break;
-case 'T':
-ct->ct |= TCG_CT_CONST_S32;
-break;
-case 'U':
-ct->ct |= TCG_CT_CONST_U32;
-break;
-case 'W':
-ct->ct |= TCG_CT_CONST_WSZ;
-break;
-case 'Z':
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
   const TCGArgConstraint *arg_ct)
-- 
2.25.1

[PATCH v3 20/24] tcg/riscv: Split out constraint sets to tcg-target-con-set.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Reviewed-by: Alistair Francis 
Signed-off-by: Richard Henderson 
---
 tcg/riscv/tcg-target-con-set.h | 30 
 tcg/riscv/tcg-target.h |  1 +
 tcg/riscv/tcg-target.c.inc | 83 ++
 3 files changed, 54 insertions(+), 60 deletions(-)
 create mode 100644 tcg/riscv/tcg-target-con-set.h

diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
new file mode 100644
index 00..cf0ac4d751
--- /dev/null
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define RISC-V target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with  outputs and  inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(LZ, L)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I3(LZ, L, L)
+C_O0_I3(LZ, LZ, L)
+C_O0_I4(LZ, LZ, L, L)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I4(r, r, rZ, rZ, rM, rM)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 727c8df418..a998b951e4 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CON_SET_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 20d5b5ef01..e700c52067 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1543,50 +1543,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 }
 }
 
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 {
-static const TCGTargetOpDef r
-= { .args_ct_str = { "r" } };
-static const TCGTargetOpDef r_r
-= { .args_ct_str = { "r", "r" } };
-static const TCGTargetOpDef rZ_r
-= { .args_ct_str = { "rZ", "r" } };
-static const TCGTargetOpDef rZ_rZ
-= { .args_ct_str = { "rZ", "rZ" } };
-static const TCGTargetOpDef rZ_rZ_rZ_rZ
-= { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
-static const TCGTargetOpDef r_r_ri
-= { .args_ct_str = { "r", "r", "ri" } };
-static const TCGTargetOpDef r_r_rI
-= { .args_ct_str = { "r", "r", "rI" } };
-static const TCGTargetOpDef r_rZ_rN
-= { .args_ct_str = { "r", "rZ", "rN" } };
-static const TCGTargetOpDef r_rZ_rZ
-= { .args_ct_str = { "r", "rZ", "rZ" } };
-static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
-= { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-static const TCGTargetOpDef r_L
-= { .args_ct_str = { "r", "L" } };
-static const TCGTargetOpDef r_r_L
-= { .args_ct_str = { "r", "r", "L" } };
-static const TCGTargetOpDef r_L_L
-= { .args_ct_str = { "r", "L", "L" } };
-static const TCGTargetOpDef r_r_L_L
-= { .args_ct_str = { "r", "r", "L", "L" } };
-static const TCGTargetOpDef LZ_L
-= { .args_ct_str = { "LZ", "L" } };
-static const TCGTargetOpDef LZ_L_L
-= { .args_ct_str = { "LZ", "L", "L" } };
-static const TCGTargetOpDef LZ_LZ_L
-= { .args_ct_str = { "LZ", "LZ", "L" } };
-static const TCGTargetOpDef LZ_LZ_L_L
-= { .args_ct_str = { "LZ", "LZ", "L", "L" } };
-static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
-= { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
 switch (op) {
 case INDEX_op_goto_ptr:
-return 
+return C_O0_I1(r);
 
 case INDEX_op_ld8u_i32:
 case INDEX_op_ld8s_i32:
@@ -1618,7 +1579,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_extrl_i64_i32:
 case INDEX_op_extrh_i64_i32:
 case INDEX_op_ext_i32_i64:
-return _r;
+return C_O1_I1(r, r);
 
 case INDEX_op_st8_i32:
 case INDEX_op_st16_i32:
@@ -1627,7 +1588,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case INDEX_op_st16_i64:
 case INDEX_op_st32_i64:
 case INDEX_op_st_i64:
-return _r;
+return C_O0_I2(rZ, r);
 
 case INDEX_op_add_i32:
 case INDEX_op_and_i32:
@@ -1637,11 +1598,11 @@ static const TCGTargetOpDef 
*tcg_target_op_def(TCGOpcode op)
 case INDEX_op_and_i64:
 case INDEX_op_or_i64:
 case INDEX_op_xor_i64:
-return _r_rI;
+return C_O1_I2(r, r, rI);
 
 case INDEX_op_sub_i32:
 case INDEX_op_sub_i64:
-return _rZ_rN;
+return C_O1_I2(r, rZ, rN);
 
 case INDEX_op_mul_i32:
 case INDEX_op_mulsh_i32:
@@ -1659,7 +1620,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 case 

[PATCH v3 09/24] tcg/tci: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Richard Henderson 
---
 tcg/tci/tcg-target-con-str.h | 11 +++
 tcg/tci/tcg-target.h |  2 ++
 tcg/tci/tcg-target.c.inc | 14 --
 3 files changed, 13 insertions(+), 14 deletions(-)
 create mode 100644 tcg/tci/tcg-target-con-str.h

diff --git a/tcg/tci/tcg-target-con-str.h b/tcg/tci/tcg-target-con-str.h
new file mode 100644
index 00..87c0f19e9c
--- /dev/null
+++ b/tcg/tci/tcg-target-con-str.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define TCI target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index bb784e018e..ab832aecc3 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -207,4 +207,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 /* no need to flush icache explicitly */
 }
 
+#define TCG_TARGET_CON_STR_H
+
 #endif /* TCG_TARGET_H */
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index b62e14d5ce..493bbf1e39 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -302,20 +302,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 return true;
 }
 
-/* Parse target specific constraints. */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'r':
-ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
-
 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 /* Show current bytecode. Used by tcg interpreter. */
 void tci_disas(uint8_t opc)
-- 
2.25.1

[PATCH v3 12/24] tcg/s390: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/s390/tcg-target-con-str.h | 28 ++
 tcg/s390/tcg-target.h |  1 +
 tcg/s390/tcg-target.c.inc | 53 +--
 3 files changed, 42 insertions(+), 40 deletions(-)
 create mode 100644 tcg/s390/tcg-target-con-str.h

diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h
new file mode 100644
index 00..892d8f8c06
--- /dev/null
+++ b/tcg/s390/tcg-target-con-str.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+/*
+ * A (single) even/odd pair for division.
+ * TODO: Add something to the register allocator to allow
+ * this kind of regno+1 pairing to be done more generally.
+ */
+REGS('a', 1u << TCG_REG_R2)
+REGS('b', 1u << TCG_REG_R3)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_S33)
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_S32)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 641464eea4..c43d6aba84 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 8517e55232..3fec7fec5f 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -42,6 +42,19 @@
 #define TCG_CT_CONST_S33   0x400
 #define TCG_CT_CONST_ZERO  0x800
 
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
+#else
+#define SOFTMMU_RESERVE_REGS 0
+#endif
+
+
 /* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0.  */
 #define TCG_REG_NONE0
@@ -403,46 +416,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 return false;
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'r':  /* all registers */
-ct->regs = 0x;
-break;
-case 'L':  /* qemu_ld/st constraint */
-ct->regs = 0x;
-tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-break;
-case 'a':  /* force R2 for division */
-ct->regs = 0;
-tcg_regset_set_reg(ct->regs, TCG_REG_R2);
-break;
-case 'b':  /* force R3 for division */
-ct->regs = 0;
-tcg_regset_set_reg(ct->regs, TCG_REG_R3);
-break;
-case 'A':
-ct->ct |= TCG_CT_CONST_S33;
-break;
-case 'I':
-ct->ct |= TCG_CT_CONST_S16;
-break;
-case 'J':
-ct->ct |= TCG_CT_CONST_S32;
-break;
-case 'Z':
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
-
 /* Test if a constant matches the constraint. */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
   const TCGArgConstraint *arg_ct)
-- 
2.25.1

[PATCH v3 07/24] tcg/aarch64: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/aarch64/tcg-target-con-str.h | 24 +++
 tcg/aarch64/tcg-target.h |  1 +
 tcg/aarch64/tcg-target.c.inc | 51 +---
 3 files changed, 33 insertions(+), 43 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-str.h

diff --git a/tcg/aarch64/tcg-target-con-str.h b/tcg/aarch64/tcg-target-con-str.h
new file mode 100644
index 00..00adb64594
--- /dev/null
+++ b/tcg/aarch64/tcg-target-con-str.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Define AArch64 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLDST_REGS)
+REGS('w', ALL_VECTOR_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_AIMM)
+CONST('L', TCG_CT_CONST_LIMM)
+CONST('M', TCG_CT_CONST_MONE)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('N', TCG_CT_CONST_ANDI)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 5ec30dba25..4fc20b58ec 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 23954ec7cf..42037c98fa 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -126,51 +126,16 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_ORRI 0x1000
 #define TCG_CT_CONST_ANDI 0x2000
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'r': /* general registers */
-ct->regs |= 0xu;
-break;
-case 'w': /* advsimd registers */
-ct->regs |= 0xull;
-break;
-case 'l': /* qemu_ld / qemu_st address, data_reg */
-ct->regs = 0xu;
+#define ALL_GENERAL_REGS  0xu
+#define ALL_VECTOR_REGS   0xull
+
 #ifdef CONFIG_SOFTMMU
-/* x0 and x1 will be overwritten when reading the tlb entry,
-   and x2, and x3 for helper args, better to avoid using them. */
-tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
-tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
-tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
+#define ALL_QLDST_REGS \
+(ALL_GENERAL_REGS & ~((1 << TCG_REG_X0) | (1 << TCG_REG_X1) | \
+  (1 << TCG_REG_X2) | (1 << TCG_REG_X3)))
+#else
+#define ALL_QLDST_REGS   ALL_GENERAL_REGS
 #endif
-break;
-case 'A': /* Valid for arithmetic immediate (positive or negative).  */
-ct->ct |= TCG_CT_CONST_AIMM;
-break;
-case 'L': /* Valid for logical immediate.  */
-ct->ct |= TCG_CT_CONST_LIMM;
-break;
-case 'M': /* minus one */
-ct->ct |= TCG_CT_CONST_MONE;
-break;
-case 'O': /* vector orr/bic immediate */
-ct->ct |= TCG_CT_CONST_ORRI;
-break;
-case 'N': /* vector orr/bic immediate, inverted */
-ct->ct |= TCG_CT_CONST_ANDI;
-break;
-case 'Z': /* zero */
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
-default:
-return NULL;
-}
-return ct_str;
-}
 
 /* Match a constant valid for addition (12-bit, optionally shifted).  */
 static inline bool is_aimm(uint64_t val)
-- 
2.25.1

[PATCH v3 06/24] tcg/arm: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/arm/tcg-target-con-str.h | 22 +++
 tcg/arm/tcg-target.h |  1 +
 tcg/arm/tcg-target.c.inc | 74 +---
 3 files changed, 41 insertions(+), 56 deletions(-)
 create mode 100644 tcg/arm/tcg-target-con-str.h

diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
new file mode 100644
index 00..a0ab7747db
--- /dev/null
+++ b/tcg/arm/tcg-target-con-str.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define Arm target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('l', ALL_QLOAD_REGS)
+REGS('s', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_ARM)
+CONST('K', TCG_CT_CONST_INV)
+CONST('N', TCG_CT_CONST_NEG)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 8d1fee6327..16336cd545 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, 
uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c2b26b3c45..bbd41d2491 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -237,65 +237,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_NEG  0x400
 #define TCG_CT_CONST_ZERO 0x800
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-   const char *ct_str, TCGType type)
-{
-switch (*ct_str++) {
-case 'I':
-ct->ct |= TCG_CT_CONST_ARM;
-break;
-case 'K':
-ct->ct |= TCG_CT_CONST_INV;
-break;
-case 'N': /* The gcc constraint letter is L, already used here.  */
-ct->ct |= TCG_CT_CONST_NEG;
-break;
-case 'Z':
-ct->ct |= TCG_CT_CONST_ZERO;
-break;
+#define ALL_GENERAL_REGS  0xu
 
-case 'r':
-ct->regs = 0x;
-break;
-
-/* qemu_ld address */
-case 'l':
-ct->regs = 0x;
+/*
+ * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
+ * and r0-r1 doing the byte swapping, so don't use these.
+ * r3 is removed for softmmu to avoid clashes with helper arguments.
+ */
 #ifdef CONFIG_SOFTMMU
-/* r0-r2,lr will be overwritten when reading the tlb entry,
-   so don't use these. */
-tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
+#define ALL_QLOAD_REGS \
+(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+  (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
+  (1 << TCG_REG_R14)))
+#define ALL_QSTORE_REGS \
+(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
+  (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \
+  ((TARGET_LONG_BITS == 64) << TCG_REG_R3)))
+#else
+#define ALL_QLOAD_REGS   ALL_GENERAL_REGS
+#define ALL_QSTORE_REGS \
+(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1)))
 #endif
-break;
-
-/* qemu_st address & data */
-case 's':
-ct->regs = 0x;
-/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
-   and r0-r1 doing the byte swapping, so don't use these. */
-tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
-#if defined(CONFIG_SOFTMMU)
-/* Avoid clashes with registers being used for helper args */
-tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-#if TARGET_LONG_BITS == 64
-/* Avoid clashes with registers being used for helper args */
-tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-#endif
-tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
-#endif
-break;
-
-default:
-return NULL;
-}
-return ct_str;
-}
 
 static inline uint32_t rotl(uint32_t val, int n)
 {
-- 
2.25.1

[PATCH v3 01/24] tcg/tci: Drop L and S constraints

[Richard Henderson]

These are identical to the 'r' constraint.

Reviewed-by: Peter Maydell 
Signed-off-by: Richard Henderson 
---
 tcg/tci/tcg-target.c.inc | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 15981265db..9c45f5f88f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -46,11 +46,11 @@
 # define R64"r"
 #endif
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L  "L", "L"
-# define S  "S", "S"
+# define L  "r", "r"
+# define S  "r", "r"
 #else
-# define L  "L"
-# define S  "S"
+# define L  "r"
+# define S  "r"
 #endif
 
 /* TODO: documentation. */
@@ -390,8 +390,6 @@ static const char *target_parse_constraint(TCGArgConstraint 
*ct,
 {
 switch (*ct_str++) {
 case 'r':
-case 'L':   /* qemu_ld constraint */
-case 'S':   /* qemu_st constraint */
 ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
 break;
 default:
-- 
2.25.1

[PATCH v3 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h

[Richard Henderson]

This eliminates the target-specific function target_parse_constraint
and folds it into the single caller, process_op_defs.  Since this is
done directly into the switch statement, duplicates are compilation
errors rather than silently ignored at runtime.

Signed-off-by: Richard Henderson 
---
 tcg/i386/tcg-target-con-str.h | 33 +
 tcg/i386/tcg-target.h |  1 +
 tcg/tcg.c | 33 ++---
 tcg/i386/tcg-target.c.inc | 69 ---
 4 files changed, 62 insertions(+), 74 deletions(-)
 create mode 100644 tcg/i386/tcg-target-con-str.h

diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
new file mode 100644
index 00..24e6bcb80d
--- /dev/null
+++ b/tcg/i386/tcg-target-con-str.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define i386 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ *
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('a', 1u << TCG_REG_EAX)
+REGS('b', 1u << TCG_REG_EBX)
+REGS('c', 1u << TCG_REG_ECX)
+REGS('d', 1u << TCG_REG_EDX)
+REGS('S', 1u << TCG_REG_ESI)
+REGS('D', 1u << TCG_REG_EDI)
+
+REGS('r', ALL_GENERAL_REGS)
+REGS('x', ALL_VECTOR_REGS)
+REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
+REGS('Q', ALL_BYTEH_REGS) /* regs with a second byte (e.g. %ah) */
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)/* qemu_st8_i32 data */
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('e', TCG_CT_CONST_S32)
+CONST('I', TCG_CT_CONST_I32)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_U32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b693d3692d..77693e13ea 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t 
tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9e1b0d73c7..8cfa28ed84 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -103,8 +103,10 @@ static void tcg_register_jit_int(const void *buf, size_t 
size,
 __attribute__((unused));
 
 /* Forward declarations for functions declared and used in tcg-target.c.inc. */
+#ifndef TCG_TARGET_CON_STR_H
 static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type);
+#endif
 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2);
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -2415,7 +2417,6 @@ static void process_op_defs(TCGContext *s)
 for (op = 0; op < NB_OPS; op++) {
 TCGOpDef *def = _op_defs[op];
 const TCGTargetOpDef *tdefs;
-TCGType type;
 int i, nb_args;
 
 if (def->flags & TCG_OPF_NOT_PRESENT) {
@@ -2431,7 +2432,6 @@ static void process_op_defs(TCGContext *s)
 /* Missing TCGTargetOpDef entry. */
 tcg_debug_assert(tdefs != NULL);
 
-type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
 for (i = 0; i < nb_args; i++) {
 const char *ct_str = tdefs->args_ct_str[i];
 /* Incomplete TCGTargetOpDef entry. */
@@ -2463,11 +2463,34 @@ static void process_op_defs(TCGContext *s)
 def->args_ct[i].ct |= TCG_CT_CONST;
 ct_str++;
 break;
+
+#ifdef TCG_TARGET_CON_STR_H
+/* Include all of the target-specific constraints. */
+
+#undef CONST
+#define CONST(CASE, MASK) \
+case CASE: def->args_ct[i].ct |= MASK; ct_str++; break;
+#define REGS(CASE, MASK) \
+case CASE: def->args_ct[i].regs |= MASK; ct_str++; break;
+
+#include "tcg-target-con-str.h"
+
+#undef REGS
+#undef CONST
 default:
-ct_str = target_parse_constraint(>args_ct[i],
- ct_str, type);
 /* Typo in TCGTargetOpDef constraint. */
-tcg_debug_assert(ct_str != NULL);
+g_assert_not_reached();
+#else
+default:
+{
+TCGType type = (def->flags & TCG_OPF_64BIT
+? TCG_TYPE_I64 : TCG_TYPE_I32);
+ct_str = target_parse_constraint(>args_ct[i],
+ ct_str, type);
+/* Typo in TCGTargetOpDef constraint. */
+tcg_debug_assert(ct_str != NULL);
+}
+#endif
 }
 }
 }
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 

[PATCH v3 04/24] tcg/i386: Tidy register constraint definitions

[Richard Henderson]

Create symbolic constants for all low-byte-addressable
and second-byte-addressable registers.  Create a symbol
for the registers that need reserving for softmmu.

There is no functional change for 's', as this letter is
only used for i386.  The BYTEL name is correct for the
action we wish from the constraint.

Signed-off-by: Richard Henderson 
---
 tcg/i386/tcg-target.c.inc | 40 +++
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 540debdf34..4feb7e2aa1 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -132,6 +132,22 @@ static const int tcg_target_call_oarg_regs[] = {
 # define TCG_REG_L1 TCG_REG_EDX
 #endif
 
+#define ALL_BYTEH_REGS 0x000fu
+#if TCG_TARGET_REG_BITS == 64
+# define ALL_GENERAL_REGS  0xu
+# define ALL_VECTOR_REGS   0xu
+# define ALL_BYTEL_REGSALL_GENERAL_REGS
+#else
+# define ALL_GENERAL_REGS  0x00ffu
+# define ALL_VECTOR_REGS   0x00ffu
+# define ALL_BYTEL_REGSALL_BYTEH_REGS
+#endif
+#ifdef CONFIG_SOFTMMU
+# define SOFTMMU_RESERVE_REGS  ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
+#else
+# define SOFTMMU_RESERVE_REGS  0
+#endif
+
 /* The host compiler should supply  to enable runtime features
detection, as we're not going to go so far as our own inline assembly.
If not available, default values will be assumed.  */
@@ -193,14 +209,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 return true;
 }
 
-#if TCG_TARGET_REG_BITS == 64
-#define ALL_GENERAL_REGS   0xu
-#define ALL_VECTOR_REGS0xu
-#else
-#define ALL_GENERAL_REGS   0x00ffu
-#define ALL_VECTOR_REGS0x00ffu
-#endif
-
 /* parse target specific constraints */
 static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
@@ -226,11 +234,11 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 break;
 case 'q':
 /* A register that can be used as a byte operand.  */
-ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xf;
+ct->regs |= ALL_BYTEL_REGS;
 break;
 case 'Q':
 /* A register with an addressable second byte (e.g. %ah).  */
-ct->regs = 0xf;
+ct->regs |= ALL_BYTEH_REGS;
 break;
 case 'r':
 /* A general register.  */
@@ -247,19 +255,11 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 
 case 'L':
 /* qemu_ld/st data+address constraint */
-ct->regs = TCG_TARGET_REG_BITS == 64 ? 0x : 0xff;
-#ifdef CONFIG_SOFTMMU
-tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
-#endif
+ct->regs |= ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS;
 break;
 case 's':
 /* qemu_st8_i32 data constraint */
-ct->regs = 0xf;
-#ifdef CONFIG_SOFTMMU
-tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
-tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
-#endif
+ct->regs |= ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS;
 break;
 
 case 'e':
-- 
2.25.1

[PATCH v3 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs

[Richard Henderson]

The opcodes always exist, regardless of whether or not they
are enabled.  Remove the unnecessary ifdefs.

Signed-off-by: Richard Henderson 
---
 tcg/tci/tcg-target.c.inc | 82 
 1 file changed, 82 deletions(-)

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9c45f5f88f..b62e14d5ce 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -71,70 +71,42 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
 { INDEX_op_add_i32, { R, RI, RI } },
 { INDEX_op_sub_i32, { R, RI, RI } },
 { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
 { INDEX_op_div_i32, { R, R, R } },
 { INDEX_op_divu_i32, { R, R, R } },
 { INDEX_op_rem_i32, { R, R, R } },
 { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
-{ INDEX_op_div2_i32, { R, R, "0", "1", R } },
-{ INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
 /* TODO: Does R, RI, RI result in faster code than R, R, RI?
If both operands are constants, we can optimize. */
 { INDEX_op_and_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i32
 { INDEX_op_andc_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i32
 { INDEX_op_eqv_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i32
 { INDEX_op_nand_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i32
 { INDEX_op_nor_i32, { R, RI, RI } },
-#endif
 { INDEX_op_or_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i32
 { INDEX_op_orc_i32, { R, RI, RI } },
-#endif
 { INDEX_op_xor_i32, { R, RI, RI } },
 { INDEX_op_shl_i32, { R, RI, RI } },
 { INDEX_op_shr_i32, { R, RI, RI } },
 { INDEX_op_sar_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i32
 { INDEX_op_rotl_i32, { R, RI, RI } },
 { INDEX_op_rotr_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i32
 { INDEX_op_deposit_i32, { R, "0", R } },
-#endif
 
 { INDEX_op_brcond_i32, { R, RI } },
 
 { INDEX_op_setcond_i32, { R, R, RI } },
-#if TCG_TARGET_REG_BITS == 64
 { INDEX_op_setcond_i64, { R, R, RI } },
-#endif /* TCG_TARGET_REG_BITS == 64 */
 
-#if TCG_TARGET_REG_BITS == 32
 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 { INDEX_op_mulu2_i32, { R, R, R, R } },
 { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-#endif
 
-#if TCG_TARGET_HAS_not_i32
 { INDEX_op_not_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i32
 { INDEX_op_neg_i32, { R, R } },
-#endif
 
-#if TCG_TARGET_REG_BITS == 64
 { INDEX_op_ld8u_i64, { R, R } },
 { INDEX_op_ld8s_i64, { R, R } },
 { INDEX_op_ld16u_i64, { R, R } },
@@ -151,81 +123,39 @@ static const TCGTargetOpDef tcg_target_op_defs[] = {
 { INDEX_op_add_i64, { R, RI, RI } },
 { INDEX_op_sub_i64, { R, RI, RI } },
 { INDEX_op_mul_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i64
 { INDEX_op_div_i64, { R, R, R } },
 { INDEX_op_divu_i64, { R, R, R } },
 { INDEX_op_rem_i64, { R, R, R } },
 { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
-{ INDEX_op_div2_i64, { R, R, "0", "1", R } },
-{ INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif
 { INDEX_op_and_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i64
 { INDEX_op_andc_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i64
 { INDEX_op_eqv_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i64
 { INDEX_op_nand_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i64
 { INDEX_op_nor_i64, { R, RI, RI } },
-#endif
 { INDEX_op_or_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i64
 { INDEX_op_orc_i64, { R, RI, RI } },
-#endif
 { INDEX_op_xor_i64, { R, RI, RI } },
 { INDEX_op_shl_i64, { R, RI, RI } },
 { INDEX_op_shr_i64, { R, RI, RI } },
 { INDEX_op_sar_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i64
 { INDEX_op_rotl_i64, { R, RI, RI } },
 { INDEX_op_rotr_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i64
 { INDEX_op_deposit_i64, { R, "0", R } },
-#endif
 { INDEX_op_brcond_i64, { R, RI } },
 
-#if TCG_TARGET_HAS_ext8s_i64
 { INDEX_op_ext8s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
 { INDEX_op_ext16s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32s_i64
 { INDEX_op_ext32s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i64
 { INDEX_op_ext8u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
 { INDEX_op_ext16u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32u_i64
 { INDEX_op_ext32u_i64, { R, R } },
-#endif
 { INDEX_op_ext_i32_i64, { R, R } },
 { INDEX_op_extu_i32_i64, { R, R } },
-#if TCG_TARGET_HAS_bswap16_i64
 { INDEX_op_bswap16_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
 { INDEX_op_bswap32_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap64_i64
 { INDEX_op_bswap64_i64, { R, R } },

[PATCH v3 03/24] tcg/i386: Move constraint type check to tcg_target_const_match

[Richard Henderson]

Rather than check the type when filling in the constraint,
check it when matching the constant.  This removes the only
use of the type argument to target_parse_constraint.

Signed-off-by: Richard Henderson 
---
 tcg/i386/tcg-target.c.inc | 28 +---
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 050f3cb0b1..540debdf34 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -263,13 +263,13 @@ static const char 
*target_parse_constraint(TCGArgConstraint *ct,
 break;
 
 case 'e':
-ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_S32);
+ct->ct |= TCG_CT_CONST_S32;
 break;
 case 'Z':
-ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_U32);
+ct->ct |= TCG_CT_CONST_U32;
 break;
 case 'I':
-ct->ct |= (type == TCG_TYPE_I32 ? TCG_CT_CONST : TCG_CT_CONST_I32);
+ct->ct |= TCG_CT_CONST_I32;
 break;
 
 default:
@@ -286,14 +286,20 @@ static inline int tcg_target_const_match(tcg_target_long 
val, TCGType type,
 if (ct & TCG_CT_CONST) {
 return 1;
 }
-if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
-return 1;
-}
-if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
-return 1;
-}
-if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
-return 1;
+if (type == TCG_TYPE_I32) {
+if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
+return 1;
+}
+} else {
+if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+return 1;
+}
+if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+return 1;
+}
+if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
+return 1;
+}
 }
 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
 return 1;
-- 
2.25.1

[PATCH v3 00/24] tcg: backend constraints cleanup

[Richard Henderson]

This pulls out constraints to a couple of headers, which
reduces the boilerplate just a little.

I have a longer term goal, which this aids, in which I
move some of the startup-time debug-only validation into
build/compile-time validation.  But not yet.

Changes for v3:
  * Split out tci ifdef removal.
  * Regularize ALL_GENERAL_REGS, SOFTMMU_RESERVE_REGS
across the backends.
  * Do not lose sparc 'A' constraint (oops).
  * Fix i386 andc constraint set.

Changes for v2:
  * Rename "conset" -> "con-str" and "constr" -> "con-str" (pmm).
  * Fix a bunch of comment spelling mistakes.
  * Add some macro usage comments.

Patches lacking review:
  02-tcg-tci-Remove-TCG_TARGET_HAS_-ifdefs.patch
  03-tcg-i386-Move-constraint-type-check-to-tcg_target.patch
  04-tcg-i386-Tidy-register-constraint-definitions.patch
  05-tcg-i386-Split-out-target-constraints-to-tcg-targ.patch
  11-tcg-riscv-Split-out-target-constraints-to-tcg-tar.patch
  13-tcg-sparc-Split-out-target-constraints-to-tcg-tar.patch
  23-tcg-tci-Split-out-constraint-sets-to-tcg-target-c.patch


r~


Richard Henderson (24):
  tcg/tci: Drop L and S constraints
  tcg/tci: Remove TCG_TARGET_HAS_* ifdefs
  tcg/i386: Move constraint type check to tcg_target_const_match
  tcg/i386: Tidy register constraint definitions
  tcg/i386: Split out target constraints to tcg-target-con-str.h
  tcg/arm: Split out target constraints to tcg-target-con-str.h
  tcg/aarch64: Split out target constraints to tcg-target-con-str.h
  tcg/ppc: Split out target constraints to tcg-target-con-str.h
  tcg/tci: Split out target constraints to tcg-target-con-str.h
  tcg/mips: Split out target constraints to tcg-target-con-str.h
  tcg/riscv: Split out target constraints to tcg-target-con-str.h
  tcg/s390: Split out target constraints to tcg-target-con-str.h
  tcg/sparc: Split out target constraints to tcg-target-con-str.h
  tcg: Remove TCG_TARGET_CON_STR_H
  tcg/i386: Split out constraint sets to tcg-target-con-set.h
  tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
  tcg/arm: Split out constraint sets to tcg-target-con-set.h
  tcg/mips: Split out constraint sets to tcg-target-con-set.h
  tcg/ppc: Split out constraint sets to tcg-target-con-set.h
  tcg/riscv: Split out constraint sets to tcg-target-con-set.h
  tcg/s390: Split out constraint sets to tcg-target-con-set.h
  tcg/sparc: Split out constraint sets to tcg-target-con-set.h
  tcg/tci: Split out constraint sets to tcg-target-con-set.h
  tcg: Remove TCG_TARGET_CON_SET_H

 tcg/aarch64/tcg-target-con-set.h |  36 
 tcg/aarch64/tcg-target-con-str.h |  24 +++
 tcg/arm/tcg-target-con-set.h |  35 +++
 tcg/arm/tcg-target-con-str.h |  22 ++
 tcg/i386/tcg-target-con-set.h|  55 +
 tcg/i386/tcg-target-con-str.h|  33 +++
 tcg/mips/tcg-target-con-set.h|  36 
 tcg/mips/tcg-target-con-str.h|  24 +++
 tcg/ppc/tcg-target-con-set.h |  42 
 tcg/ppc/tcg-target-con-str.h |  30 +++
 tcg/riscv/tcg-target-con-set.h   |  30 +++
 tcg/riscv/tcg-target-con-str.h   |  21 ++
 tcg/s390/tcg-target-con-set.h|  29 +++
 tcg/s390/tcg-target-con-str.h|  28 +++
 tcg/sparc/tcg-target-con-set.h   |  32 +++
 tcg/sparc/tcg-target-con-str.h   |  23 ++
 tcg/sparc/tcg-target.h   |   4 -
 tcg/tci/tcg-target-con-set.h |  25 +++
 tcg/tci/tcg-target-con-str.h |  11 +
 tcg/tcg.c| 136 +++-
 tcg/aarch64/tcg-target.c.inc | 137 
 tcg/arm/tcg-target.c.inc | 168 +--
 tcg/i386/tcg-target.c.inc| 317 +--
 tcg/mips/tcg-target.c.inc| 173 +--
 tcg/ppc/tcg-target.c.inc | 209 ++
 tcg/riscv/tcg-target.c.inc   | 135 
 tcg/s390/tcg-target.c.inc| 174 ++-
 tcg/sparc/tcg-target.c.inc   | 156 +-
 tcg/tci/tcg-target.c.inc | 359 +++
 29 files changed, 1244 insertions(+), 1260 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target-con-set.h
 create mode 100644 tcg/aarch64/tcg-target-con-str.h
 create mode 100644 tcg/arm/tcg-target-con-set.h
 create mode 100644 tcg/arm/tcg-target-con-str.h
 create mode 100644 tcg/i386/tcg-target-con-set.h
 create mode 100644 tcg/i386/tcg-target-con-str.h
 create mode 100644 tcg/mips/tcg-target-con-set.h
 create mode 100644 tcg/mips/tcg-target-con-str.h
 create mode 100644 tcg/ppc/tcg-target-con-set.h
 create mode 100644 tcg/ppc/tcg-target-con-str.h
 create mode 100644 tcg/riscv/tcg-target-con-set.h
 create mode 100644 tcg/riscv/tcg-target-con-str.h
 create mode 100644 tcg/s390/tcg-target-con-set.h
 create mode 100644 tcg/s390/tcg-target-con-str.h
 create mode 100644 tcg/sparc/tcg-target-con-set.h
 create mode 100644 tcg/sparc/tcg-target-con-str.h
 create mode 100644 tcg/tci/tcg-target-con-set.h
 create mode 100644 tcg/tci/tcg-target-con-str.h

-- 
2.25.1

Re: [PATCH v2 2/2] pci: add romsize property

[BALATON Zoltan]

On Fri, 29 Jan 2021, Paolo Bonzini wrote:

On 29/01/21 20:51, BALATON Zoltan wrote:
otherwise the BIOS emulator in the guest firmware crashes and this works so 
I think romfile can be empty and it's a useful feature to have in this case 
for example. I don't know if this patch changes anything about that but the 
commit message saying that romfile cannot be empty may be wrong.


The empty property value configures the device not to have a ROM file at all. 
The commit message says that ROM files (if they exist) cannot be empty, 
corresponding to this code in pci_add_option_rom:


   } else if (size == 0) {
   error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
   g_free(path);
   return;
   }


OK, then it was just not clear to me that the commit message talks about 
the romfile itself and not the property.


By the way, does it make sense to compare uint32_t value to -1 and could 
that provoke some compiler/sanitiser warnings? Is it better to have a 
signed type or use UINT32_MAX or simlar instead?


Regards,
BALATON Zoltan

Re: [RFC PATCH 3/4] hw/xen/Kconfig: Introduce XEN_PV config

[Paolo Bonzini]

On 29/01/21 20:44, Philippe Mathieu-Daudé wrote:

xenpv machine requires USB, IDE_PIIX and PCI:

   /usr/bin/ld:
   libcommon.fa.p/hw_xen_xen-legacy-backend.c.o: in function 
`xen_be_register_common':
   hw/xen/xen-legacy-backend.c:757: undefined reference to `xen_usb_ops'
   libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`unplug_disks':
   hw/i386/xen/xen_platform.c:153: undefined reference to 
`pci_piix3_xen_ide_unplug'
   libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`pci_unplug_nics':
   hw/i386/xen/xen_platform.c:137: undefined reference to `pci_for_each_device'
   libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`xen_platform_realize':
   hw/i386/xen/xen_platform.c:483: undefined reference to `pci_register_bar'

Signed-off-by: Philippe Mathieu-Daudé 
---
  hw/Kconfig | 1 +
  hw/xen/Kconfig | 6 ++
  2 files changed, 7 insertions(+)
  create mode 100644 hw/xen/Kconfig

diff --git a/hw/Kconfig b/hw/Kconfig
index 5ad3c6b5a4b..f2a95591d94 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -39,6 +39,7 @@ source usb/Kconfig
  source virtio/Kconfig
  source vfio/Kconfig
  source watchdog/Kconfig
+source xen/Kconfig
  
  # arch Kconfig

  source arm/Kconfig
diff --git a/hw/xen/Kconfig b/hw/xen/Kconfig
new file mode 100644
index 000..15944144a17
--- /dev/null
+++ b/hw/xen/Kconfig
@@ -0,0 +1,6 @@
+config XEN_PV
+bool
+depends on XEN
+select PCI
+select USB
+select IDE_PIIX



Since you're hacking around you can also "select ISA_BUS" here, but the 
right solution would be to have a "config XEN_FV" and leave 
hw/i386/xen/xen_platform.c out of XEN_PV.


Paolo

Re: [RFC PATCH 2/4] hw/ide/Kconfig: IDE_PIIX requires IDE_ISA

[Paolo Bonzini]

On 29/01/21 20:44, Philippe Mathieu-Daudé wrote:

hw/ide/piix.c has a strong dependency on hw/isa/isa-bus.c:

   /usr/bin/ld: libcommon.fa.p/hw_ide_piix.c.o: in function 
`pci_piix_init_ports':
   /usr/bin/ld: hw/ide/piix.c:141: undefined reference to `isa_get_irq'

Signed-off-by: Philippe Mathieu-Daudé 
---
  hw/ide/Kconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig
index 41cdd9cbe03..0f5d316558b 100644
--- a/hw/ide/Kconfig
+++ b/hw/ide/Kconfig
@@ -17,6 +17,7 @@ config IDE_ISA
  
  config IDE_PIIX

  bool
+select IDE_ISA
  select IDE_PCI
  select IDE_QDEV
  



This is also incorrect, it should be "depends on ISA_BUS".

Paolo

Re: [RFC PATCH 1/4] hw/ide/Kconfig: IDE_ISA requires ISA_BUS

[Paolo Bonzini]

On 29/01/21 20:44, Philippe Mathieu-Daudé wrote:

hw/ide/ioport.c has a strong dependency on hw/isa/isa-bus.c:

   /usr/bin/ld: libcommon.fa.p/hw_ide_ioport.c.o: in function `ide_init_ioport':
   /usr/bin/ld: hw/ide/ioport.c:61: undefined reference to 
`isa_register_portio_list'

Signed-off-by: Philippe Mathieu-Daudé 
---
  hw/ide/Kconfig | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig
index 5d9106b1ac2..41cdd9cbe03 100644
--- a/hw/ide/Kconfig
+++ b/hw/ide/Kconfig
@@ -12,7 +12,7 @@ config IDE_PCI
  
  config IDE_ISA

  bool
-depends on ISA_BUS
+select ISA_BUS
  select IDE_QDEV
  
  config IDE_PIIX


This is incorrect.  Buses are "depended on", not selected, and this is 
documented in docs/devel/kconfig.rst.


Paolo

Re: [PATCH v2 2/2] pci: add romsize property

[Paolo Bonzini]

On 29/01/21 20:51, BALATON Zoltan wrote:
otherwise the BIOS emulator in the guest firmware crashes and this works 
so I think romfile can be empty and it's a useful feature to have in 
this case for example. I don't know if this patch changes anything about 
that but the commit message saying that romfile cannot be empty may be 
wrong.


The empty property value configures the device not to have a ROM file at 
all.  The commit message says that ROM files (if they exist) cannot be 
empty, corresponding to this code in pci_add_option_rom:


} else if (size == 0) {
error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
g_free(path);
return;
}

Paolo

[PATCH] chardev/char-io: Fix polling by not removing polls when buffers are full

[Iris Johnson]

Currently, the chardev backend code will prepare for IO polling to occur
by potentially adding or removing a watch of the backing channel for the
chardev. The chardev poll is added if the fd_can_read() function reports
more than 0 byte of buffer space, if a poll handler is already setup and
the bufer is now empty, the poll handler is removed.

This causes a bug where the device buffer becomes ready, but the poll is
blocking on a sleep (potentially forever), because the buffer is small
and fills up immediately, while the backend channel has more data. This
leads to a stall condition or potentially a deadlock in the guest.

The guest is looping, waiting for data to be reported as ready to read,
the host sees that the buffer is ready for reading and adds the poll,
the poll returns since data is available and data is made available to
the guest. Before the guest code is able to retrieve the data and clear
the full buffer, the poll code runs again, sees that the buffer is now
full, and removes the poll. At this point only a timeout from another
polled source, or another source having it's poll complete will result
in the loop running again to see that the buffer is now ready and to
add the poll again.

We solve this issue by removing the logic that removes the poll, keeping
the existing logic to only create the poll once there's space for the
first read.

Buglink: https://bugs.launchpad.net/qemu/+bug/1913341
Signed-off-by: Iris Johnson 
---
 chardev/char-io.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/chardev/char-io.c b/chardev/char-io.c
index 8ced184160..fa9e222f78 100644
--- a/chardev/char-io.c
+++ b/chardev/char-io.c
@@ -50,16 +50,14 @@ static gboolean io_watch_poll_prepare(GSource *source,
 return FALSE;
 }
 
-if (now_active) {
+if (now_active && !was_active) {
 iwp->src = qio_channel_create_watch(
 iwp->ioc, G_IO_IN | G_IO_ERR | G_IO_HUP | G_IO_NVAL);
 g_source_set_callback(iwp->src, iwp->fd_read, iwp->opaque, NULL);
 g_source_add_child_source(source, iwp->src);
 g_source_unref(iwp->src);
-} else {
-g_source_remove_child_source(source, iwp->src);
-iwp->src = NULL;
 }
+
 return FALSE;
 }
 
-- 
2.25.1

Re: [PULL 00/36] Misc patches (buildsys, i386, fuzzing) for 2021-01-29

[Paolo Bonzini]

On 29/01/21 20:49, Peter Maydell wrote:

On Fri, 29 Jan 2021 at 11:33, Paolo Bonzini  wrote:


The following changes since commit 0bcd12fb1513bad44f05f2d3a8eef2a99b3077b6:

   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
(2021-01-28 12:30:30 +)

are available in the Git repository at:

   https://gitlab.com/bonzini/qemu.git tags/for-upstream

for you to fetch changes up to 6c52f4644c9c8a18b8495e169e539632a897f135:

   accel/kvm/kvm-all: Fix wrong return code handling in dirty log code 
(2021-01-29 10:38:38 +0100)




Fails to build, OSX:

../../subprojects/libslirp/src/slirp.c:131:17: error: unused variable
'old_stat' [-Werror,-Wunused-variable]
 struct stat old_stat;
 ^
../../subprojects/libslirp/src/slirp.c:143:10: error: unused variable
'buff' [-Werror,-Wunused-variable]
 char buff[512];
  ^


Hmm this is the same slirp failure that in theory should have been fixed 
by Marc-André.  I'll check again on Monday.


Paolo

Re: [PATCH v2 2/2] pci: add romsize property

[BALATON Zoltan]

On Fri, 29 Jan 2021, Paolo Bonzini wrote:

This property can be useful for distros to set up known-good ROM sizes for
migration purposes.  The VM will fail to start if the ROM is too large,
and migration compatibility will not be broken if the ROM is too small.

Note that even though romsize is a uint32_t, it has to be between 1
(because empty ROM files are not accepted, and romsize must be greater
than the file) and 2^31 (because values above are not powers of two and
are rejected).


I've found I have to use this command to disable vgabios-ati.bin:

qemu-system-ppc -M sam460ex -device ati-vga,romfile=""

otherwise the BIOS emulator in the guest firmware crashes and this works 
so I think romfile can be empty and it's a useful feature to have in this 
case for example. I don't know if this patch changes anything about that 
but the commit message saying that romfile cannot be empty may be wrong.


Regards,
BALATON Zoltan


Reviewed-by: Dr. David Alan Gilbert 
Reviewed-by: Peter Xu 
Signed-off-by: Paolo Bonzini 
---
hw/pci/pci.c | 19 +--
hw/xen/xen_pt_load_rom.c | 14 --
include/hw/pci/pci.h |  1 +
3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bbce10050b..5b3fe3c294 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -68,6 +68,7 @@ static void pcibus_reset(BusState *qbus);
static Property pci_props[] = {
DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
+DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1),
DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
@@ -2107,6 +2108,11 @@ static void pci_qdev_realize(DeviceState *qdev, Error 
**errp)
bool is_default_rom;
uint16_t class_id;

+if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) {
+error_setg(errp, "ROM size %d is not a power of two", 
pci_dev->romsize);
+return;
+}
+
/* initialize cap_present for pci_is_express() and pci_config_size(),
 * Note that hybrid PCIs are not set automatically and need to manage
 * QEMU_PCI_CAP_EXPRESS manually */
@@ -2372,7 +2378,16 @@ static void pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom,
g_free(path);
return;
}
-size = pow2ceil(size);
+if (pdev->romsize != -1) {
+if (size > pdev->romsize) {
+error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM size 
%u",
+   pdev->romfile, (uint32_t)size, pdev->romsize);
+g_free(path);
+return;
+}
+} else {
+pdev->romsize = pow2ceil(size);
+}

vmsd = qdev_get_vmsd(DEVICE(pdev));

@@ -2382,7 +2397,7 @@ static void pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom,
snprintf(name, sizeof(name), "%s.rom", 
object_get_typename(OBJECT(pdev)));
}
pdev->has_rom = true;
-memory_region_init_rom(>rom, OBJECT(pdev), name, size, _fatal);
+memory_region_init_rom(>rom, OBJECT(pdev), name, pdev->romsize, 
_fatal);
ptr = memory_region_get_ram_ptr(>rom);
if (load_image_size(path, ptr, size) < 0) {
error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
diff --git a/hw/xen/xen_pt_load_rom.c b/hw/xen/xen_pt_load_rom.c
index a50a80837e..153812f8cd 100644
--- a/hw/xen/xen_pt_load_rom.c
+++ b/hw/xen/xen_pt_load_rom.c
@@ -53,10 +53,20 @@ void *pci_assign_dev_load_option_rom(PCIDevice *dev,
}
fseek(fp, 0, SEEK_SET);

+if (dev->romsize != -1) {
+if (st.st_size > dev->romsize) {
+error_report("ROM BAR \"%s\" (%ld bytes) is too large for ROM size 
%d",
+ rom_file, (long) st.st_size, dev->romsize);
+goto close_rom;
+}
+} else {
+dev->romsize = st.st_size;
+}
+
snprintf(name, sizeof(name), "%s.rom", object_get_typename(owner));
-memory_region_init_ram(>rom, owner, name, st.st_size, _abort);
+memory_region_init_ram(>rom, owner, name, dev->romsize, _abort);
ptr = memory_region_get_ram_ptr(>rom);
-memset(ptr, 0xff, st.st_size);
+memset(ptr, 0xff, dev->romsize);

if (!fread(ptr, 1, st.st_size, fp)) {
error_report("pci-assign: Cannot read from host %s", rom_file);
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 259f9c992d..b028245b62 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -343,6 +343,7 @@ struct PCIDevice {

/* Location of option rom */
char *romfile;
+uint32_t romsize;
bool has_rom;
MemoryRegion rom;
uint32_t rom_bar;

Re: [PULL 00/36] Misc patches (buildsys, i386, fuzzing) for 2021-01-29

[Peter Maydell]

On Fri, 29 Jan 2021 at 11:33, Paolo Bonzini  wrote:
>
> The following changes since commit 0bcd12fb1513bad44f05f2d3a8eef2a99b3077b6:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
> (2021-01-28 12:30:30 +)
>
> are available in the Git repository at:
>
>   https://gitlab.com/bonzini/qemu.git tags/for-upstream
>
> for you to fetch changes up to 6c52f4644c9c8a18b8495e169e539632a897f135:
>
>   accel/kvm/kvm-all: Fix wrong return code handling in dirty log code 
> (2021-01-29 10:38:38 +0100)
>
> 

Fails to build, OSX:

../../subprojects/libslirp/src/slirp.c:131:17: error: unused variable
'old_stat' [-Werror,-Wunused-variable]
struct stat old_stat;
^
../../subprojects/libslirp/src/slirp.c:143:10: error: unused variable
'buff' [-Werror,-Wunused-variable]
char buff[512];
 ^

thanks
-- PMM

[RFC PATCH 4/4] hw/xen: Have the xenpv machine select 9pfs

[Philippe Mathieu-Daudé]

9pfs is not an accelerator feature but a machine one.

Signed-off-by: Philippe Mathieu-Daudé 
---
 accel/Kconfig  | 1 -
 hw/xen/Kconfig | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/Kconfig b/accel/Kconfig
index 461104c7715..b9e9a2d35b0 100644
--- a/accel/Kconfig
+++ b/accel/Kconfig
@@ -15,4 +15,3 @@ config KVM
 
 config XEN
 bool
-select FSDEV_9P if VIRTFS
diff --git a/hw/xen/Kconfig b/hw/xen/Kconfig
index 15944144a17..14009cd6a05 100644
--- a/hw/xen/Kconfig
+++ b/hw/xen/Kconfig
@@ -4,3 +4,4 @@ config XEN_PV
 select PCI
 select USB
 select IDE_PIIX
+select FSDEV_9P if VIRTFS
-- 
2.26.2

[RFC PATCH 3/4] hw/xen/Kconfig: Introduce XEN_PV config

[Philippe Mathieu-Daudé]

xenpv machine requires USB, IDE_PIIX and PCI:

  /usr/bin/ld:
  libcommon.fa.p/hw_xen_xen-legacy-backend.c.o: in function 
`xen_be_register_common':
  hw/xen/xen-legacy-backend.c:757: undefined reference to `xen_usb_ops'
  libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`unplug_disks':
  hw/i386/xen/xen_platform.c:153: undefined reference to 
`pci_piix3_xen_ide_unplug'
  libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`pci_unplug_nics':
  hw/i386/xen/xen_platform.c:137: undefined reference to `pci_for_each_device'
  libqemu-i386-softmmu.fa.p/hw_i386_xen_xen_platform.c.o: in function 
`xen_platform_realize':
  hw/i386/xen/xen_platform.c:483: undefined reference to `pci_register_bar'

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/Kconfig | 1 +
 hw/xen/Kconfig | 6 ++
 2 files changed, 7 insertions(+)
 create mode 100644 hw/xen/Kconfig

diff --git a/hw/Kconfig b/hw/Kconfig
index 5ad3c6b5a4b..f2a95591d94 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -39,6 +39,7 @@ source usb/Kconfig
 source virtio/Kconfig
 source vfio/Kconfig
 source watchdog/Kconfig
+source xen/Kconfig
 
 # arch Kconfig
 source arm/Kconfig
diff --git a/hw/xen/Kconfig b/hw/xen/Kconfig
new file mode 100644
index 000..15944144a17
--- /dev/null
+++ b/hw/xen/Kconfig
@@ -0,0 +1,6 @@
+config XEN_PV
+bool
+depends on XEN
+select PCI
+select USB
+select IDE_PIIX
-- 
2.26.2

[RFC PATCH 2/4] hw/ide/Kconfig: IDE_PIIX requires IDE_ISA

[Philippe Mathieu-Daudé]

hw/ide/piix.c has a strong dependency on hw/isa/isa-bus.c:

  /usr/bin/ld: libcommon.fa.p/hw_ide_piix.c.o: in function 
`pci_piix_init_ports':
  /usr/bin/ld: hw/ide/piix.c:141: undefined reference to `isa_get_irq'

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/ide/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig
index 41cdd9cbe03..0f5d316558b 100644
--- a/hw/ide/Kconfig
+++ b/hw/ide/Kconfig
@@ -17,6 +17,7 @@ config IDE_ISA
 
 config IDE_PIIX
 bool
+select IDE_ISA
 select IDE_PCI
 select IDE_QDEV
 
-- 
2.26.2

[RFC PATCH 1/4] hw/ide/Kconfig: IDE_ISA requires ISA_BUS

[Philippe Mathieu-Daudé]

hw/ide/ioport.c has a strong dependency on hw/isa/isa-bus.c:

  /usr/bin/ld: libcommon.fa.p/hw_ide_ioport.c.o: in function `ide_init_ioport':
  /usr/bin/ld: hw/ide/ioport.c:61: undefined reference to 
`isa_register_portio_list'

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/ide/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig
index 5d9106b1ac2..41cdd9cbe03 100644
--- a/hw/ide/Kconfig
+++ b/hw/ide/Kconfig
@@ -12,7 +12,7 @@ config IDE_PCI
 
 config IDE_ISA
 bool
-depends on ISA_BUS
+select ISA_BUS
 select IDE_QDEV
 
 config IDE_PIIX
-- 
2.26.2

[RFC PATCH 0/4] hw/xen: Fixes to only build the XEN_PV machine

[Philippe Mathieu-Daudé]

Hi Alex,

These are the Xen patches I'm carrying to build the xenpv
machine alone. I haven't tried to build the xenfv one.

Tagged as RFC because this was part of a draft, so must be
think better, but I don't have much time to finish it.
Anyhow quick review appreciated.

Missing (out of scope of this draft):
Possibility to build another config than the default-configs/
ones.

Regards,

Phil.

Philippe Mathieu-Daudé (4):
  hw/ide/Kconfig: IDE_ISA requires ISA_BUS
  hw/ide/Kconfig: IDE_PIIX requires IDE_ISA
  hw/xen/Kconfig: Introduce XEN_PV config
  hw/xen: Have the xenpv machine select 9pfs

 accel/Kconfig  | 1 -
 hw/Kconfig | 1 +
 hw/ide/Kconfig | 3 ++-
 hw/xen/Kconfig | 7 +++
 4 files changed, 10 insertions(+), 2 deletions(-)
 create mode 100644 hw/xen/Kconfig

-- 
2.26.2

Re: [PULL v2 00/46] target-arm queue

[Peter Maydell]

On Fri, 29 Jan 2021 at 16:08, Peter Maydell  wrote:
>
> v2 update: fix memory leaks in pvpanic-pci test case spotted by
> oss-fuzz gitlab CI run.
>
> -- PMM
>
> The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' 
> into staging (2021-01-28 22:43:18 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210129-1
>
> for you to fetch changes up to 14711b6f54708b9583796db02b12ee7bd0331502:
>
>   hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 
> 15:54:44 +)
>
> 
> target-arm queue:
>  * Implement ID_PFR2
>  * Conditionalize DBGDIDR
>  * rename xlnx-zcu102.canbusN properties
>  * provide powerdown/reset mechanism for secure firmware on 'virt' board
>  * hw/misc: Fix arith overflow in NPCM7XX PWM module
>  * target/arm: Replace magic value by MMU_DATA_LOAD definition
>  * configure: fix preadv errors on Catalina macOS with new XCode
>  * Various configure and other cleanups in preparation for iOS support
>  * hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
>  * Implement pvpanic-pci device
>  * Convert the CMSDK timer devices to the Clock framework
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM

Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass

[Eduardo Habkost]

On Fri, Jan 29, 2021 at 09:19:00AM -1000, Richard Henderson wrote:
> On 1/28/21 11:00 PM, Claudio Fontana wrote:
> > Do you think I should redo the series anyway? I would have started this way
> > in the first place, but I tried not to redo Eduardo's work.
> I think that would be a good idea, yes.

Maybe just removing the #ifdefs from patch 01 (which were not
present in the patch I wrote) could be a way to avoid redoing the
whole series.

-- 
Eduardo

[PATCH v2 1/2] pci: reject too large ROMs

[Paolo Bonzini]

get_image_size() returns an int64_t, which pci_add_option_rom() assigns
to an "int" without any range checking.  A 32-bit BAR could be up to
2 GiB in size, so reject anything above it.  In order to accomodate
a rounded-up size of 2 GiB, change pci_patch_ids's size argument
to unsigned.

Signed-off-by: Paolo Bonzini 
---
 hw/pci/pci.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index a6b0c5602e..bbce10050b 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -25,6 +25,7 @@
 #include "qemu/osdep.h"
 #include "qemu-common.h"
 #include "qemu/datadir.h"
+#include "qemu/units.h"
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bridge.h"
@@ -2258,7 +2258,7 @@ static uint8_t pci_find_capability_at_offset(PCIDevice 
*pdev, uint8_t offset)
 
 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
This is needed for an option rom which is used for more than one device. */
-static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
+static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size)
 {
 uint16_t vendor_id;
 uint16_t device_id;
@@ -2316,7 +2316,7 @@ static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, 
int size)
 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
Error **errp)
 {
-int size;
+int64_t size;
 char *path;
 void *ptr;
 char name[32];
@@ -2366,6 +2366,11 @@ static void pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom,
 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
 g_free(path);
 return;
+} else if (size > 2 * GiB) {
+error_setg(errp, "romfile \"%s\" too large (size cannot exceed 2 GiB)",
+   pdev->romfile);
+g_free(path);
+return;
 }
 size = pow2ceil(size);
 
-- 
2.29.2

[PATCH v2 2/2] pci: add romsize property

[Paolo Bonzini]

This property can be useful for distros to set up known-good ROM sizes for
migration purposes.  The VM will fail to start if the ROM is too large,
and migration compatibility will not be broken if the ROM is too small.

Note that even though romsize is a uint32_t, it has to be between 1
(because empty ROM files are not accepted, and romsize must be greater
than the file) and 2^31 (because values above are not powers of two and
are rejected).

Reviewed-by: Dr. David Alan Gilbert 
Reviewed-by: Peter Xu 
Signed-off-by: Paolo Bonzini 
---
 hw/pci/pci.c | 19 +--
 hw/xen/xen_pt_load_rom.c | 14 --
 include/hw/pci/pci.h |  1 +
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index bbce10050b..5b3fe3c294 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -68,6 +68,7 @@ static void pcibus_reset(BusState *qbus);
 static Property pci_props[] = {
 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
+DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, -1),
 DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
@@ -2107,6 +2108,11 @@ static void pci_qdev_realize(DeviceState *qdev, Error 
**errp)
 bool is_default_rom;
 uint16_t class_id;
 
+if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) {
+error_setg(errp, "ROM size %d is not a power of two", 
pci_dev->romsize);
+return;
+}
+
 /* initialize cap_present for pci_is_express() and pci_config_size(),
  * Note that hybrid PCIs are not set automatically and need to manage
  * QEMU_PCI_CAP_EXPRESS manually */
@@ -2372,7 +2378,16 @@ static void pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom,
 g_free(path);
 return;
 }
-size = pow2ceil(size);
+if (pdev->romsize != -1) {
+if (size > pdev->romsize) {
+error_setg(errp, "romfile \"%s\" (%u bytes) is too large for ROM 
size %u",
+   pdev->romfile, (uint32_t)size, pdev->romsize);
+g_free(path);
+return;
+}
+} else {
+pdev->romsize = pow2ceil(size);
+}
 
 vmsd = qdev_get_vmsd(DEVICE(pdev));
 
@@ -2382,7 +2397,7 @@ static void pci_add_option_rom(PCIDevice *pdev, bool 
is_default_rom,
 snprintf(name, sizeof(name), "%s.rom", 
object_get_typename(OBJECT(pdev)));
 }
 pdev->has_rom = true;
-memory_region_init_rom(>rom, OBJECT(pdev), name, size, _fatal);
+memory_region_init_rom(>rom, OBJECT(pdev), name, pdev->romsize, 
_fatal);
 ptr = memory_region_get_ram_ptr(>rom);
 if (load_image_size(path, ptr, size) < 0) {
 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile);
diff --git a/hw/xen/xen_pt_load_rom.c b/hw/xen/xen_pt_load_rom.c
index a50a80837e..153812f8cd 100644
--- a/hw/xen/xen_pt_load_rom.c
+++ b/hw/xen/xen_pt_load_rom.c
@@ -53,10 +53,20 @@ void *pci_assign_dev_load_option_rom(PCIDevice *dev,
 }
 fseek(fp, 0, SEEK_SET);
 
+if (dev->romsize != -1) {
+if (st.st_size > dev->romsize) {
+error_report("ROM BAR \"%s\" (%ld bytes) is too large for ROM size 
%d",
+ rom_file, (long) st.st_size, dev->romsize);
+goto close_rom;
+}
+} else {
+dev->romsize = st.st_size;
+}
+
 snprintf(name, sizeof(name), "%s.rom", object_get_typename(owner));
-memory_region_init_ram(>rom, owner, name, st.st_size, _abort);
+memory_region_init_ram(>rom, owner, name, dev->romsize, _abort);
 ptr = memory_region_get_ram_ptr(>rom);
-memset(ptr, 0xff, st.st_size);
+memset(ptr, 0xff, dev->romsize);
 
 if (!fread(ptr, 1, st.st_size, fp)) {
 error_report("pci-assign: Cannot read from host %s", rom_file);
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 259f9c992d..b028245b62 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -343,6 +343,7 @@ struct PCIDevice {
 
 /* Location of option rom */
 char *romfile;
+uint32_t romsize;
 bool has_rom;
 MemoryRegion rom;
 uint32_t rom_bar;
-- 
2.29.2

[PATCH v2 0/2] pci: add romsize property

[Paolo Bonzini]

This property can be useful for distros to set up known-good ROM sizes for
migration purposes.  The VM will fail to start if the ROM is too large,
and migration compatibility will not be broken if the ROM is too small.

The main difference from v1 is the first patch, which fixes overflow
issues in nearby code.  The second patch is the same as v1 except for
replacing %d->%u in the error message.

Paolo

Paolo Bonzini (2):
  pci: reject too large ROMs
  pci: add romsize property

 hw/pci/pci.c | 28 
 hw/xen/xen_pt_load_rom.c | 14 --
 include/hw/pci/pci.h |  1 +
 3 files changed, 37 insertions(+), 6 deletions(-)

-- 
2.29.2

Re: [PATCH] tests/acceptance: Re-enable the microblaze test

[Wainer dos Santos Moschetta]

Hi Thomas,

On 1/29/21 2:40 AM, Thomas Huth wrote:

On 28/01/2021 20.34, Wainer dos Santos Moschetta wrote:

Hi,

On 1/28/21 12:28 PM, Thomas Huth wrote:
The microblaze kernel sometimes gets stuck during boot (ca. 1 out of 
200

times), so we disabled the corresponding acceptance tests some months
ago. However, it's likely better to check that the kernel is still
starting than to not testing it at all anymore. Move the test to
a separate file, enable it again and check for an earlier console
message that should always appear.

Signed-off-by: Thomas Huth 
---
  MAINTAINERS    |  1 +
  tests/acceptance/boot_linux_console.py |  9 ---
  tests/acceptance/machine_microblaze.py | 35 
++

  3 files changed, 36 insertions(+), 9 deletions(-)
  create mode 100644 tests/acceptance/machine_microblaze.py

diff --git a/MAINTAINERS b/MAINTAINERS
index 34359a99b8..157ad4f7ef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1112,6 +1112,7 @@ M: Edgar E. Iglesias 
  S: Maintained
  F: hw/microblaze/petalogix_s3adsp1800_mmu.c
  F: include/hw/char/xilinx_uartlite.h
+F: tests/acceptance/machine_microblaze.py
  petalogix_ml605
  M: Edgar E. Iglesias 
diff --git a/tests/acceptance/boot_linux_console.py 
b/tests/acceptance/boot_linux_console.py

index fb41bb7144..969fbf3952 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -1047,15 +1047,6 @@ class BootLinuxConsole(LinuxKernelTest):
  tar_hash = 'ac688fd00561a2b6ce1359f9ff6aa2b98c9a570c'
  self.do_test_advcal_2018('07', tar_hash, 'sanity-clause.elf')
-    @skip("Test currently broken") # Console stuck as of 5.2-rc1
-    def test_microblaze_s3adsp1800(self):
-    """
-    :avocado: tags=arch:microblaze
-    :avocado: tags=machine:petalogix-s3adsp1800
-    """
-    tar_hash = '08bf3e3bfb6b6c7ce1e54ab65d54e189f2caf13f'
-    self.do_test_advcal_2018('17', tar_hash, 'ballerina.bin')
-
  def test_or1k_sim(self):
  """
  :avocado: tags=arch:or1k
diff --git a/tests/acceptance/machine_microblaze.py 
b/tests/acceptance/machine_microblaze.py

new file mode 100644
index 00..7f6d18495d
--- /dev/null
+++ b/tests/acceptance/machine_microblaze.py
@@ -0,0 +1,35 @@
+# Functional test that boots a microblaze Linux kernel and checks 
the console

+#
+# Copyright (c) 2018, 2021 Red Hat, Inc.
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import Test
+from avocado_qemu import wait_for_console_pattern
+from avocado.utils import archive
+
+class MicroblazeMachine(Test):
+
+    timeout = 90
+
+    def test_microblaze_s3adsp1800(self):
+    """
+    :avocado: tags=arch:microblaze
+    :avocado: tags=machine:petalogix-s3adsp1800
+    """
+
+    tar_url = ('https://www.qemu-advent-calendar.org'
+   '/2018/download/day17.tar.xz')
+    tar_hash = '08bf3e3bfb6b6c7ce1e54ab65d54e189f2caf13f'
+    file_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
+    archive.extract(file_path, self.workdir)
+    self.vm.set_console()
+    self.vm.add_args('-kernel', self.workdir + 
'/day17/ballerina.bin')

+    self.vm.launch()
+    wait_for_console_pattern(self, 'This architecture does not 
have '

+   'kernel memory protection')
+    # Note:
+    # The kernel sometimes gets stuck after the "This 
architecture ..."
+    # message, that's why we don't test for a later string 
here. This

+    # needs some investigation by a microblaze wizard one day...



The change looks good to me.

Also I appreciate the note you left on code. In addition I suggest to 
put some tag to indicate it needs some investigation or that it is 
flaky (although that's not the case anymore), because it will ease 
the discovery and filtering of "problematic" tests. What do you think?


Sounds reasonable, but I'm not aware of any such tags in the 
"acceptance" code yet... what exactly do you have in mind?


First, I don't want to hold this patch any longer. So:

Reviewed-by: Wainer dos Santos Moschetta 

Then back to the tags discussion...

I agree with Philippe when he says [1] that Avocado tags might be 
underused. But unlike his idea (see [1], which I think is very good btw) 
here I mentioned the use of tags to solve a different problem: ease the 
search for tests that need maintenance.


The test in this patch, for example, could be tagged "needReview" 
(sorry, there must exist a better tag name). If it was failing 
intermittently (and we hope your changes prevent that) then we could 
have it tagged "flaky". Disabled tests get marked as "disabled", and so 
on. Thus, one can use the `avocado list -t needReview` command to get 
the list of tests.


I will come up with a RFC series so we may continue this conversation on 
concrete examples. Sounds good to you?

Re: [PATCH v14 15/22] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass

[Richard Henderson]

On 1/28/21 11:00 PM, Claudio Fontana wrote:
> Do you think I should redo the series anyway? I would have started this way
> in the first place, but I tried not to redo Eduardo's work.
I think that would be a good idea, yes.


r~

Re: [PATCH v4 09/12] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M

[Philippe Mathieu-Daudé]

On 10/3/20 11:48 AM, Richard Henderson wrote:
> On 9/29/20 5:43 PM, Philippe Mathieu-Daudé wrote:
>> +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: 
>> files('m_helper-stub.c'))
>> +
>>  arm_ss.add(zlib)
>>  
>>  arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c'))
>> +arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
> 
> I'm a bit surprised about adding the file twice.
> Since ARM_V7M depends on TCG, isn't the second line redundant?

This does:

if TCG
if CONFIG_ARM_V7M
files('m_helper.c')
else #!V7M
files('m_helper-stub.c'))
endif
else #!TCG
files('m_helper-stub.c'))
endif

So:

if !TCG or !V7M
files('m_helper-stub.c'))
else
files('m_helper.c')
endif

There might be a better way to express that in Meson...
I only understood how to do AND with arrays, but not OR.

Paolo/Marc-André, is it possible?

Thanks,

Phil.

Re: [PULL 17/21] hw/adc: Add an ADC module for NPCM7XX

[Philippe Mathieu-Daudé]

On 1/29/21 6:15 PM, wuhaotsh--- via wrote:
> On Fri, Jan 29, 2021 at 6:41 AM Philippe Mathieu-Daudé  > wrote:
> 
> Hi Hao Wu,
> 
> On 1/12/21 5:57 PM, Peter Maydell wrote:
> > From: Hao Wu mailto:wuhao...@google.com>>
> >
> > The ADC is part of NPCM7XX Module. Its behavior is controled by the
> > ADC_CON register. It converts one of the eight analog inputs into a
> > digital input and stores it in the ADC_DATA register when enabled.
> >
> > Users can alter input value by using qom-set QMP command.
> >
> > Reviewed-by: Havard Skinnemoen  >
> > Reviewed-by: Tyrone Ting  >
> > Signed-off-by: Hao Wu  >
> > Message-id: 20210108190945.949196-4-wuhao...@google.com
> 
> > [PMM: Added missing hw/adc/trace.h file]
> > Reviewed-by: Peter Maydell  >
> > Signed-off-by: Peter Maydell  >
> > ---
> >  docs/system/arm/nuvoton.rst    |   2 +-
> >  meson.build                    |   1 +
> >  hw/adc/trace.h                 |   1 +
> >  include/hw/adc/npcm7xx_adc.h   |  69 ++
> >  include/hw/arm/npcm7xx.h       |   2 +
> >  hw/adc/npcm7xx_adc.c           | 301 ++
> >  hw/arm/npcm7xx.c               |  24 ++-
> >  tests/qtest/npcm7xx_adc-test.c | 377
> +
> >  hw/adc/meson.build             |   1 +
> >  hw/adc/trace-events            |   5 +
> >  tests/qtest/meson.build        |   3 +-
> >  11 files changed, 783 insertions(+), 3 deletions(-)
> >  create mode 100644 hw/adc/trace.h
> >  create mode 100644 include/hw/adc/npcm7xx_adc.h
> >  create mode 100644 hw/adc/npcm7xx_adc.c
> >  create mode 100644 tests/qtest/npcm7xx_adc-test.c
> >  create mode 100644 hw/adc/trace-events
> ...

> > +
> > +REG32(NPCM7XX_ADC_CON, 0x0)
> > +REG32(NPCM7XX_ADC_DATA, 0x4)
> > +
> > +/* Register field definitions. */
> > +#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
> > +#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
> > +#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
> > +#define NPCM7XX_ADC_CON_INT     BIT(18)
> > +#define NPCM7XX_ADC_CON_EN      BIT(17)
> > +#define NPCM7XX_ADC_CON_RST     BIT(16)
> > +#define NPCM7XX_ADC_CON_CONV    BIT(14)
> > +#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
> > +
> > +#define NPCM7XX_ADC_MAX_RESULT      1023
> > +#define NPCM7XX_ADC_DEFAULT_IREF    200
> > +#define NPCM7XX_ADC_CONV_CYCLES     20
> > +#define NPCM7XX_ADC_RESET_CYCLES    10
> > +#define NPCM7XX_ADC_R0_INPUT        50
> > +#define NPCM7XX_ADC_R1_INPUT        150
> > +
> > +static void npcm7xx_adc_reset(NPCM7xxADCState *s)
> > +{
> > +    timer_del(>conv_timer);
> > +    s->con = 0x000c0001;
> 
> This initialize CON to:
> 
> NPCM7XX_ADC_CON_REFSEL | NPCM7XX_ADC_CON_INT | BIT(0)
> 
> What is bit 0?
> 
> This reset value is from h/w spec. The bit is reserved and not used
> currently.

OK thanks. Since the datasheet is not public, better document
the reserved/unused bits to avoid further questioning later ;)

Thanks,

Phil.

[PATCH] docs/system: document an example booting the versatilepb machine

[Alex Bennée]

There is a bit more out there including Aurelien's excellent write up
and older Debian images here:

  https://www.aurel32.net/info/debian_arm_qemu.php
  https://people.debian.org/~aurel32/qemu/armel/

However the web is transitory and git is forever so lets add something
to the fine manual.

Cc: Anders Roxell 
Cc: Aurelien Jarno 
Signed-off-by: Alex Bennée 
---
 docs/system/arm/versatile.rst | 32 
 1 file changed, 32 insertions(+)

diff --git a/docs/system/arm/versatile.rst b/docs/system/arm/versatile.rst
index 51221c30a4..d16f20ccae 100644
--- a/docs/system/arm/versatile.rst
+++ b/docs/system/arm/versatile.rst
@@ -27,3 +27,35 @@ The Arm Versatile baseboard is emulated with the following 
devices:
devices.
 
 -  PL181 MultiMedia Card Interface with SD card.
+
+Booting a Linux kernel
+--
+
+Building a current Linux kernel with ``versatile_defconfig`` should be
+enough to get something running.
+
+.. code-block:: bash
+
+  $ export ARCH=arm
+  $ export CROSS_COMPILE=arm-linux-gnueabihf-
+  $ make versatile_defconfig
+  $ make
+
+You may want to enable some additional modules if you want to boot
+something from the SCSI interface::
+
+  CONFIG_PCI=y
+  CONFIG_PCI_VERSATILE=y
+  CONFIG_SCSI=y
+  CONFIG_SCSI_SYM53C8XX_2=y
+
+You can then boot with a command line like:
+
+.. code-block:: bash
+
+  $ qemu-system-arm -machine type=versatilepb \
+  -serial mon:stdio \
+  -drive if=scsi,driver=file,filename=debian-buster-armel-rootfs.ext4 \
+  -kernel zImage \
+  -dtb versatile-pb.dtb  \
+  -append "console=ttyAMA0 ro root=/dev/sda"
-- 
2.20.1

Re: [PATCH] iotests/testrunner: fix recognition of python tests

[John Snow]

On 1/29/21 4:06 AM, Vladimir Sementsov-Ogievskiy wrote:

We should drop final '\n' before comparing with python3 shebang.

Fixes: d74c754c924ca34e90b7c96ce2f5609d82c0e628
Signed-off-by: Vladimir Sementsov-Ogievskiy 


Reviewed-by: John Snow 


---
  tests/qemu-iotests/testrunner.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/qemu-iotests/testrunner.py b/tests/qemu-iotests/testrunner.py
index a581be6a29..24b3fba115 100644
--- a/tests/qemu-iotests/testrunner.py
+++ b/tests/qemu-iotests/testrunner.py
@@ -248,7 +248,7 @@ class TestRunner(ContextManager['TestRunner']):
  
  with f_test.open(encoding="utf-8") as f:

  try:
-if f.readline() == '#!/usr/bin/env python3':
+if f.readline().rstrip() == '#!/usr/bin/env python3':
  args.insert(0, self.env.python)
  except UnicodeDecodeError:  # binary test? for future.
  pass

Re: [PATCH] iotests/297: pylint: ignore too many statements

[John Snow]

On 1/29/21 4:50 AM, Kevin Wolf wrote:

Am 28.01.2021 um 21:08 hat Vladimir Sementsov-Ogievskiy geschrieben:

28.01.2021 23:04, Vladimir Sementsov-Ogievskiy wrote:

Ignore two complains, which now lead to 297 failure on testenv.py and
testrunner.py.

Fixes: 2e5a2f57db481f18fcf70be2a36b1417370b8476
Fixes: d74c754c924ca34e90b7c96ce2f5609d82c0e628
Signed-off-by: Vladimir Sementsov-Ogievskiy 
---


Forget to note:

I don't add exclusions to pylintrc intentionally, as I think these
warnings are reasonable, and it's good that vim ALE show them.. Still,
adding them to pylintrc works too if you prefer.


I would have disabled the warning completely because I don't think
length in lines is a good measure for code quality. But if we think that
these warnings are in fact reasonable, then we should fix them and not
just disable them partially.

It's the same reason why we have -Werror enabled. If you leave warnings
around without any intention to fix them, the useful warnings will drown
in the masses of intentionally ignored ones.

Kevin



It's at least a sniff test. There are extremely valid reasons for many 
of the "warnings" to be suppressed, but usually you should have to 
consciously justify it, I think.


Vladimir put the suppression in pylintrc under the "Temporary" section 
for v2, which I think is appropriate, so I gave it my R-B.


--js

Re: [PATCH v2] iotests/297: pylint: ignore too many statements

[John Snow]

On 1/29/21 11:13 AM, Vladimir Sementsov-Ogievskiy wrote:

Ignore two complains, which now lead to 297 failure on testenv.py and
testrunner.py.

Fixes: 2e5a2f57db481f18fcf70be2a36b1417370b8476
Fixes: d74c754c924ca34e90b7c96ce2f5609d82c0e628


^ Thanks for this


Signed-off-by: Vladimir Sementsov-Ogievskiy 


Reviewed-by: John Snow 


---
  tests/qemu-iotests/pylintrc | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/tests/qemu-iotests/pylintrc b/tests/qemu-iotests/pylintrc
index cd3702e23c..7a6c0a9474 100644
--- a/tests/qemu-iotests/pylintrc
+++ b/tests/qemu-iotests/pylintrc
@@ -21,6 +21,8 @@ disable=invalid-name,
  unsubscriptable-object,
  # These are temporary, and should be removed:
  missing-docstring,
+too-many-return-statements,
+too-many-statements
  
  [FORMAT]