[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

[frank . chang]

From: Frank Chang 

In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang 
---
 fpu/softfloat-specialize.c.inc | 17 +
 1 file changed, 17 insertions(+)

diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index c2f87addb25..9c37265e20b 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -624,6 +624,23 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass 
b_cls, FloatClass c_cls,
 } else {
 return 1;
 }
+#elif defined(TARGET_RISCV)
+/*
+ * For RISC-V, InvalidOp is set when multiplicands are Inf and zero
+ * and returns default NaN.
+ */
+if (infzero) {
+float_raise(float_flag_invalid, status);
+return 3;
+}
+
+if (is_nan(a_cls)) {
+return 0;
+} else if (is_nan(b_cls)) {
+return 1;
+} else {
+return 2;
+}
 #elif defined(TARGET_XTENSA)
 /*
  * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
-- 
2.17.1

Re: [RFC PATCH 14/15] gitlab-ci: Allow forks to use different set of jobs

[Thomas Huth]

On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:

Forks run the same jobs than mainstream, which might be overkill.
Allow them to easily rebase their custom set, while keeping using
the mainstream templates, and ability to pick specific jobs from
the mainstream set.

To switch to your set, simply add your .gitlab-ci.yml as
.gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml (where CI_PROJECT_NAMESPACE
is your gitlab 'namespace', usually username). This file will be
used instead of the default mainstream set.

Signed-off-by: Philippe Mathieu-Daudé 
---
  .gitlab-ci.yml | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 718c8e004be..35fd35075db 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -9,7 +9,12 @@ generate-config:
  paths:
- generated-config.yml
script:
-- cp .gitlab-ci.d/qemu-project.yml generated-config.yml
+- if test -e .gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml ;
+  then
+cp .gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml generated-config.yml ;
+  else
+cp .gitlab-ci.d/qemu-project.yml generated-config.yml ;
+  fi


I think you could merge this with the previous patch, since the previous 
patch is not very useful on its own.


Anyway, I like the idea, that could be useful for downstream, indeed!

 Thomas

Re: [PATCH 1/2] spapr.c: do not use MachineClass::max_cpus to limit CPUs

[David Gibson]

On Thu, Apr 08, 2021 at 05:40:48PM -0300, Daniel Henrique Barboza wrote:
> Up to this patch, 'max_cpus' value is hardcoded to 1024 (commit
> 6244bb7e5811). In theory this patch would simply bump it to 2048, since
> it's the default NR_CPUS kernel setting for ppc64 servers nowadays, but
> the whole mechanic of MachineClass:max_cpus is flawed for the pSeries
> machine. The two supported accelerators, KVM and TCG, can live without
> it.
> 
> TCG guests don't have a theoretical limit. The user must be free to
> emulate as many CPUs as the hardware is capable of. And even if there
> were a limit, max_cpus is not the proper way to report it since it's a
> common value checked by SMP code in machine_smp_parse() for KVM as well.
> 
> For KVM guests, the proper way to limit KVM CPUs is by host
> configuration via NR_CPUS, not a QEMU hardcoded value. There is no
> technical reason for a pSeries QEMU guest to forcefully stay below
> NR_CPUS.
> 
> This hardcoded value also disregard hosts that might have a lower
> NR_CPUS limit, say 512. In this case, machine.c:machine_smp_parse() will
> allow a 1024 value to pass, but then kvm_init() will complain about it
> because it will exceed NR_CPUS:
> 
> Number of SMP cpus requested (1024) exceeds the maximum cpus supported
> by KVM (512)
> 
> A better 'max_cpus' value would consider host settings, but
> MachineClass::max_cpus is defined well before machine_init() and
> kvm_init(). We can't check for KVM limits because it's too soon, so we
> end up making a guess.

Well.. it's not so much that we're guessing KVM limits.  I think
max_cpus in the generic code is more about hard CPU limits which are
part of the machine architecture itself.  You're right that that
doesn't really make sense for the paravirtual PAPR machine though.

> This patch makes MachineClass:max_cpus settings innocuous by setting it
> to INT32_MAX. machine.c:machine_smp_parse() will not fail the
> verification based on max_cpus, letting kvm_init() do the checking with
> actual host settings. And TCG guests get to do whatever the hardware is
> capable of emulating.
> 
> Signed-off-by: Daniel Henrique Barboza 

Applied to ppc-for-6.1.

> ---
>  hw/ppc/spapr.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 73a06df3b1..d6a67da21f 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -4482,7 +4482,16 @@ static void spapr_machine_class_init(ObjectClass *oc, 
> void *data)
>  mc->init = spapr_machine_init;
>  mc->reset = spapr_machine_reset;
>  mc->block_default_type = IF_SCSI;
> -mc->max_cpus = 1024;
> +
> +/*
> + * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values
> + * should be limited by the host capability instead of hardcoded.
> + * max_cpus for KVM guests will be checked in kvm_init(), and TCG
> + * guests are welcome to have as many CPUs as the host are capable
> + * of emulate.
> + */
> +mc->max_cpus = INT32_MAX;
> +
>  mc->no_parallel = 1;
>  mc->default_boot_order = "";
>  mc->default_ram_size = 512 * MiB;

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH 2/2] spapr.h: increase FDT_MAX_SIZE

[David Gibson]

On Thu, Apr 08, 2021 at 05:40:49PM -0300, Daniel Henrique Barboza wrote:
> Certain SMP topologies stress, e.g. 1 thread/core, 2048 cores and
> 1 socket, stress the current maximum size of the pSeries FDT:
> 
> Calling ibm,client-architecture-support...qemu-system-ppc64: error
> creating device tree: (fdt_setprop(fdt, offset,
> "ibm,processor-segment-sizes", segs, sizeof(segs))): FDT_ERR_NOSPACE
> 
> 2048 is the default NR_CPUS value for the pSeries kernel. It's expected
> that users will want QEMU to be able to handle this kind of
> configuration.
> 
> Bumping FDT_MAX_SIZE to 2MB is enough for these setups to be created.
> 
> Signed-off-by: Daniel Henrique Barboza 

Applied to ppc-for-6.1, thanks.

> ---
>  include/hw/ppc/spapr.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index bf7cab7a2c..3deb382678 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -95,7 +95,7 @@ typedef enum {
>  #define SPAPR_CAP_FIXED_CCD 0x03
>  #define SPAPR_CAP_FIXED_NA  0x10 /* Lets leave a bit of a gap... 
> */
>  
> -#define FDT_MAX_SIZE0x10
> +#define FDT_MAX_SIZE0x20
>  
>  /*
>   * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH 11/15] gitlab-ci: Extract core container jobs to container-core.yml

[Thomas Huth]

On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:

It is not possible to use the previously extracted templates
without this set of core containers. Extract them into a new
file (container-core.yml) to be able to build them without
having to build all the other containers by default.

Signed-off-by: Philippe Mathieu-Daudé 
---
  .gitlab-ci.d/container-core.yml | 17 +
  .gitlab-ci.d/containers.yml | 16 +---
  2 files changed, 18 insertions(+), 15 deletions(-)
  create mode 100644 .gitlab-ci.d/container-core.yml


Reviewed-by: Thomas Huth 

Re: [PATCH 10/15] gitlab-ci: Extract all default build/test jobs to buildtest.yml

[Thomas Huth]

On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:

Extract the build/test jobs run by default on the mainstream
CI into a new file (buildtest.yml) and their templates into
(buildtest-template.yml), to be able to reuse the templates
without having to run all these mainstream jobs by default.

Signed-off-by: Philippe Mathieu-Daudé 
---
  .gitlab-ci.d/buildtest-template.yml |  80 +++
  .gitlab-ci.d/buildtest.yml  | 744 +
  .gitlab-ci.yml  | 824 +---
  3 files changed, 825 insertions(+), 823 deletions(-)
  create mode 100644 .gitlab-ci.d/buildtest-template.yml
  create mode 100644 .gitlab-ci.d/buildtest.yml


I like the idea, the main .gitlab-ci.yml was way to crowded already anyway.

Not sure if "buildtest.yml" is such a good name (since it's not only about 
building, but also about testing), but I fail to come up with a better 
suggestion...


Just a suggestion for discussion, not sure whether it's such a good idea 
yet: Maybe we could split it up even further into "system.yml" (with the 
various jobs that only test the "softmmu" binaries), "user.yml" (with the 
--disable-system jobs) and "misc.yml" (with mixed jobs) ?



diff --git a/.gitlab-ci.d/buildtest-template.yml 
b/.gitlab-ci.d/buildtest-template.yml
new file mode 100644
index 000..b24a153d904
--- /dev/null
+++ b/.gitlab-ci.d/buildtest-template.yml
@@ -0,0 +1,80 @@
+.native_build_job_template:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  before_script:
+- JOBS=$(expr $(nproc) + 1)
+  script:
+- mkdir build
+- cd build
+- if test -n "$TARGETS";
+  then
+../configure --enable-werror --disable-docs $CONFIGURE_ARGS 
--target-list="$TARGETS" ;
+  else
+../configure --enable-werror --disable-docs $CONFIGURE_ARGS ;
+  fi || { cat config.log meson-logs/meson-log.txt && exit 1; }
+- if test -n "$LD_JOBS";
+  then
+meson configure . -Dbackend_max_links="$LD_JOBS" ;
+  fi || exit 1;
+- make -j"$JOBS"
+- if test -n "$MAKE_CHECK_ARGS";
+  then
+make -j"$JOBS" $MAKE_CHECK_ARGS ;
+  fi
+
+.native_test_job_template:
+  stage: test
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  script:
+- scripts/git-submodule.sh update
+$(sed -n '/GIT_SUBMODULES=/ s/.*=// p' build/config-host.mak)
+- cd build
+- find . -type f -exec touch {} +
+# Avoid recompiling by hiding ninja with NINJA=":"
+- make NINJA=":" $MAKE_CHECK_ARGS
+
+.integration_test_job_template:
+  cache:
+key: "${CI_JOB_NAME}-cache"
+paths:
+  - ${CI_PROJECT_DIR}/avocado-cache
+policy: pull-push
+  artifacts:
+name: "$CI_JOB_NAME-$CI_COMMIT_REF_SLUG"
+when: always
+expire_in: 2 days
+paths:
+  - build/tests/results/latest/results.xml
+  - build/tests/results/latest/test-results
+reports:
+  junit: build/tests/results/latest/results.xml
+  before_script:
+- mkdir -p ~/.config/avocado
+- echo "[datadir.paths]" > ~/.config/avocado/avocado.conf
+- echo "cache_dirs = ['${CI_PROJECT_DIR}/avocado-cache']"
+   >> ~/.config/avocado/avocado.conf
+- echo -e '[job.output.testlogs]\nstatuses = ["FAIL", "INTERRUPT"]'
+   >> ~/.config/avocado/avocado.conf
+- if [ -d ${CI_PROJECT_DIR}/avocado-cache ]; then
+du -chs ${CI_PROJECT_DIR}/avocado-cache ;
+  fi
+- export AVOCADO_ALLOW_UNTRUSTED_CODE=1
+  after_script:
+- cd build
+- du -chs ${CI_PROJECT_DIR}/avocado-cache
+
+build-system-alpine:
+  extends: .native_build_job_template
+  needs:
+- job: amd64-alpine-container
+  variables:
+IMAGE: alpine
+TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
+  moxie-softmmu microblazeel-softmmu mips64el-softmmu
+MAKE_CHECK_ARGS: check-build
+CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
+  artifacts:
+expire_in: 2 days
+paths:
+  - .git-submodule-status
+  - build


build-system-alpine should certainly not go into the template file, but into 
the file below instead.



diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
new file mode 100644
index 000..c24553eab05
--- /dev/null
+++ b/.gitlab-ci.d/buildtest.yml
@@ -0,0 +1,744 @@

[...]

+check-patch:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-patch.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000
+  allow_failure: true
+
+check-dco:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-dco.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000


These two should not be here anymore since they 

Re: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

[David Gibson]

On Tue, Apr 13, 2021 at 05:43:02PM +, Bruno Piazera Larsen wrote:
> > I'm actually not sure if we'll want translate_init.c for !tcg builds.
> > It's *primarily* for TCG, but we still need at least some of the cpu
> > state structure for KVM, and some of that is initialized in
> > translate_init.
> >
> > I think it will probably make more sense to leave it in for a first
> > cut.  Later refinement might end up removing it.
> >
> > The whole #include translate_init.c.inc thing might make for some
> > awkward fiddling in this, of course.
> 
> I just checked, there is going to be some shuffling of functions
> around, as there are some static variables defined on translate.c,
> and used in translate_init.c.inc, some functions needed for KVM
> on translate.c and some TCG only functions in the
> translate_init.c.inc.
> 
> The trivial path is to:
> * rename translate_init.c.inc to cpu_init.c (since it has to do with
> initial definitions for CPUs, and it's not related to translating
> anymore);
> * move gen_write_xer and gen_read_xer into cpu_init.c, as they're
> used for some sprs, and whatever needs to be moved with it

Hmm.. that doesn't seem right.  gen_*() functions are explicitly for
generating code, so it really seems like they belong in the
translation file.

> * move is_indirect_opcode and ind_table to translate.c, since they
> are used to translate ppc instructions, and the things defined for
> these functions
> * Figure out what needs to be added to the includes for both
> files to compile
> * move opcodes and invalid_handler into cpu_init.c, because they
> are only used by stuff in this file.
> 
> I'm just not sure about this last point. The stuff that use opcodes
> create the callback tables for TCG, AFAICT. The better plan would
> be to move all of that to tanslate.c, but might be a lot.
> 
> Can I follow the trivial plan for the first cut and leave a TODO in
> the code for a better solution in the future? Or is there a nuance
> about one of those functions that I have not understood?
> 
> 
> Bruno Piazera Larsen
> 
> Instituto de Pesquisas 
> ELDORADO
> 
> Departamento Computação Embarcada
> 
> Analista de Software Trainee
> 
> Aviso Legal - Disclaimer
> 
> 
> De: David Gibson
> Enviadas: Terça-feira, 13 de Abril de 2021 03:40
> Para: Bruno Piazera Larsen
> Cc: Fabiano Rosas; Thomas Huth; qemu-devel@nongnu.org; Luis Fernando Fujita 
> Pires; Andre Fernando da Silva; Lucas Mateus Martins Araujo e Castro; 
> Fernando Eckhardt Valle; qemu-...@nongnu.org; lagar...@br.ibm.com; Matheus 
> Kowalczuk Ferst
> Assunto: Re: [PATCH 1/4] target/ppc: Code motion required to build disabling 
> tcg
> 
> On Mon, Apr 12, 2021 at 12:05:31PM +, Bruno Piazera Larsen wrote:
> > > A general advice for this whole series is: make sure you add in some
> > > words explaining why you decided to make a particular change. It will be
> > > much easier to review if we know what were the logical steps leading to
> > > the change.
> >
> > Fair point, I should've thought about that.
> >
> > > > This commit does the necessary code motion from translate_init.c.inc
> > >
> > > For instance, I don't immediately see why these changes are necessary. I
> > > see that translate_init.c.inc already has some `#ifdef CONFIG_TCG`, so
> > > why do we need to move a bunch of code into cpu.c instead of just adding
> > > more code under ifdef CONFIG_TCG? (I'm not saying it's wrong, just trying 
> > > to
> > > understand the reasoning).
> >
> > There are 3 main reasons for this decision. The first is kind of silly, but 
> > when I read translate.c my mind jumped to translating machine code to TCG, 
> > and the amount of TCGv variables at the start reinforced this notion.
> > The second was that both s390x and i386 removed it (translate.c) from 
> > compilation, so I had no good reason to doubt it.
> > The last (and arguably most important) is that translate.c is many 
> > thousands of lines long (translate_init.c.inc alone was almost 11k). The 
> > whole point of disabling TCG is to speed up compilation and reduce the 
> > final file size, so I think it makes sense to remove that big file.
> > And the final nail in the coffin is that at no point did it cross my mind 
> > to keep the init part of translation, but remove the rest
> >
> > Also, I'm not a fan of big ifdefs, because it's kinda hard to follow them 
> > when viewing 

Re: [PATCH 3/4] target/ppc: Add stubs for tcg functions, so it builds

[David Gibson]

On Fri, Apr 09, 2021 at 12:19:15PM -0300, Bruno Larsen (billionai) wrote:
> This file basically adds all stubs required to build the project
> with disable-tcg. most of these are not going to remain stubs by the
> end, but this part is where it got complicated, and I wanted to get
> an RFC ASAP. Most of these have to do with mmu emulation, so they'll
> probably be replaced by a KVM implementation in the final product,
> but I'm not sure which ones have to be replace, which can remain
> stubs, and which should not be called at all. Input in general is
> very much welcome.
> 
> Signed-off-by: Bruno Larsen (billionai) 
> ---
>  target/ppc/tcg-stub.c | 139 ++
>  1 file changed, 139 insertions(+)
>  create mode 100644 target/ppc/tcg-stub.c
> 
> diff --git a/target/ppc/tcg-stub.c b/target/ppc/tcg-stub.c
> new file mode 100644
> index 00..5dc8cf8911
> --- /dev/null
> +++ b/target/ppc/tcg-stub.c
> @@ -0,0 +1,139 @@
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "mmu-hash64.h"
> +
> +/* STUFF FOR FIRST LINKER ERROR */
> +/* This stuff happens in target/ppc files */
> +
> +#if !defined(CONFIG_USER_ONLY)
> +
> +void ppc_store_sdr1(CPUPPCState *env, target_ulong value) {

In general stubbing ppc_store_*() functions doesn't look seem like a
good idea.  At the very least the KVM code will need to update the
register in env so that it gets synced with KVM later.  I think you're
going to be better off moving those ppc_store_*() functions used from
KVM code into somewhere common, then #ifdefing to remove any TCG
specific operations from them (or else providing KVM stubs for the TCG
things they call).

> +/* stub to make things compile */
> +return;
> +}
> +
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value) {
> +/* stub to make things compile */
> +return;
> +}
> +
> +#endif /* !defined(CONFIG_USER_ONLY) */
> +void ppc_store_msr(CPUPPCState *env, target_ulong value) {
> +/* stub to make things compile */
> +return;
> +}
> +
> +void dump_mmu(CPUPPCState *env){
> +/* stub to make things compile */
> +return;
> +}
> +
> +void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) {
> +/* stub to make things compile */
> +return;
> +}
> +
> +void ppc_cpu_do_interrupt(CPUState *cpu) {
> +/* stub to make things compile */
> +return;
> +}
> +
> +/* STUFF FOR SECOND LINKER ERROR*/
> +/* these errors happen mostly in hw/ppc */
> +
> +#ifdef TARGET_PPC64
> +int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
> +  target_ulong esid, target_ulong vsid) {
> +/* rquired by kvm.c and machine.c */
> +return 0;
> +}
> +
> +void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
> + bool (*cb)(void *, uint32_t, uint32_t),
> + void *opaque) {
> +/* required by spapr_caps.c */
> +return; 
> +}
> +
> +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) {
> +/* required by spapr_* */
> +return;
> +}
> +
> +const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
> + hwaddr ptex, int n) {
> +/* used by spapr_hcall a bunch */
> +return NULL;
> +}
> +
> +void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
> +hwaddr ptex, int n) {
> +/* used a bunch by spapr_hcall */
> +return; 
> +}
> +
> +void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> +   target_ulong pte_index,
> +   target_ulong pte0, target_ulong pte1){
> +return; 
> +}
> +
> +unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> +  uint64_t pte0, uint64_t pte1) {
> +return 0;
> +}
> +#endif
> +
> +void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) {
> +/* required by spapr_events spapr_mce_dispatch_elog */
> +return;
> +}
> +#ifndef CONFIG_USER_ONLY
> +void ppc_cpu_do_system_reset(CPUState *cs){
> +/* required by pnv and spapr */
> +return;
> +}
> +#endif
> +
> +bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
> +   ppc_v3_pate_t *entry);
> +
> +bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
> +   ppc_v3_pate_t *entry) {
> +/* used by spapr_hcall: ppc_hash64_hpt_mask */
> +return true;
> +}
> +
> +/* THIRD BATCH OF ERRORS, AFTER MOVING STUFF FROM TRANSLATE TO CPU.C */
> +
> +/* they are all coming from cpu.c, probably */
> +
> +void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) {
> +return;
> +}
> +
> +void init_ppc_proc(PowerPCCPU *cpu) {
> +return;
> +}
> +
> +void destroy_ppc_opcodes(PowerPCCPU *cpu) {
> +return;
> +}
> +
> +void ppc_tlb_invalidate_all(CPUPPCState *env) {
> +return;
> +}
> +
> +void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags) {
> +return;
> +}
> +
> +void ppc_cpu_dump_statistics(CPUState 

Re: [PATCH 1/4] target/ppc: Code motion required to build disabling tcg

[David Gibson]

On Tue, Apr 13, 2021 at 06:38:57PM -0300, Fabiano Rosas wrote:
> Bruno Piazera Larsen  writes:
> 
> >> I'm actually not sure if we'll want translate_init.c for !tcg builds.
> >> It's *primarily* for TCG, but we still need at least some of the cpu
> >> state structure for KVM, and some of that is initialized in
> >> translate_init.
> >>
> >> I think it will probably make more sense to leave it in for a first
> >> cut.  Later refinement might end up removing it.
> >>
> >> The whole #include translate_init.c.inc thing might make for some
> >> awkward fiddling in this, of course.
> >
> > I just checked, there is going to be some shuffling of functions
> > around, as there are some static variables defined on translate.c,
> > and used in translate_init.c.inc, some functions needed for KVM
> > on translate.c and some TCG only functions in the
> > translate_init.c.inc.
> >
> > The trivial path is to:
> > * rename translate_init.c.inc to cpu_init.c (since it has to do with
> > initial definitions for CPUs, and it's not related to translating
> > anymore);
> 
> Below I'm assuming we have one place for TCG stuff and other for KVM
> stuff, whatever this particular discussion ends up producing.
> 
> > * move gen_write_xer and gen_read_xer into cpu_init.c, as they're
> > used for some sprs, and whatever needs to be moved with it
> 
> I'd leave them where they are currently. Instead what I think we should
> do is to find a way to not need the uea/oea/hea|read/write callbacks
> with KVM.
> 
> Maybe extract a function from _spr_register that sets what is common for
> both tcg and kvm (num, name, initial_value, AFAICT). Then alter the
> gen_spr* functions to first create all registers and then call both
> configs to supplement:
> 
> //tcg.c
> static void tcg_gen_spr_generic(CPUPPCState *env)
> {
> // these only set the callbacks
> spr_register(env, SPR_FOO,
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_foo, _write_foo);
> spr_register(env, SPR_BAR,
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_bar, _write_bar);
> }
> 
> //kvm.c
> static void kvm_gen_spr_generic(CPUPPCState *env)
> {
> // these only set one_reg_id
> spr_register_kvm(env, SPR_FOO, KVM_REG_PPC_FOO);
> spr_register_kvm(env, SPR_BAR, KVM_REG_PPC_BAR);
> }

I really dislike the idea above - it'd be way too easy for KVM and TCG
to get out of sync.  Instead make spr_register() itself a macro if
necessary, so it just ignores the access functions in the !TCG case.

> //common.c
> static void gen_spr_generic(CPUPPCState *env)
> {
> // these only set name, num, initial value
> spr_register(env, SPR_FOO, "FOO", 0xf00);
> spr_register(env, SPR_BAR, "BAR", 0xb4d);
> ...
> 
> // have these stubbed if not chosen via config
> tcg_gen_spr_generic(env);
> kvm_gen_spr_generic(env);
> }
> 
> init_ppc_proc()
> {
> ...
> gen_spr_generic(env);
> ...
> }
> 
> Can anyone see a better way? That would be much easier if we could
> afford to say that TCG and KVM are mutually exclusive for a given build,
> but I don't think they are.
> 
> > * move is_indirect_opcode and ind_table to translate.c, since they
> > are used to translate ppc instructions, and the things defined for
> > these functions
> 
> Makes sense. This and the other part below about callback tables would
> be mostly about moving code so it's a candidate for coming soon.
> 
> > * Figure out what needs to be added to the includes for both
> > files to compile
> > * move opcodes and invalid_handler into cpu_init.c, because they
> > are only used by stuff in this file.
> >
> > I'm just not sure about this last point. The stuff that use opcodes
> > create the callback tables for TCG, AFAICT. The better plan would
> > be to move all of that to tanslate.c, but might be a lot.
> 
> translate.c seems like a better place indeed.
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH 08/15] gitlab-ci: Extract DCO/style check jobs to checks.yml

[Thomas Huth]

On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:

Extract the DCO / checkpatch jobs to a new file (checks.yml)
to be able to run them without having to run all the jobs
included in the default .gitlab-ci.yml, which are mainly useful
for mainstream CI.

Signed-off-by: Philippe Mathieu-Daudé 
---
  .gitlab-ci.d/checks.yml | 24 
  .gitlab-ci.yml  |  1 +
  2 files changed, 25 insertions(+)
  create mode 100644 .gitlab-ci.d/checks.yml

diff --git a/.gitlab-ci.d/checks.yml b/.gitlab-ci.d/checks.yml
new file mode 100644
index 000..f695627b7cd
--- /dev/null
+++ b/.gitlab-ci.d/checks.yml
@@ -0,0 +1,24 @@
+check-patch:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-patch.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000
+  allow_failure: true
+
+check-dco:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-dco.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index bf4862a78de..ba35b3917e7 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -12,6 +12,7 @@ include:
- local: '/.gitlab-ci.d/opensbi.yml'
- local: '/.gitlab-ci.d/containers.yml'
- local: '/.gitlab-ci.d/crossbuilds.yml'
+  - local: '/.gitlab-ci.d/checks.yml'
  
  .native_build_job_template:

stage: build



You added the new file, but it looks like you did not remove the jobs from 
the main .gitlab-ci.yml file ? ... that looks like a mistake?


Also, "checks.yml" sounds a little bit too generic. Maybe rather name it 
"style-check.yml" or something similar?


 Thomas

Re: [PATCH 05/15] gitlab-ci: Rename acceptance_test_job -> integration_test_job

[Thomas Huth]

On 19/04/2021 01.34, Philippe Mathieu-Daudé wrote:

From: Philippe Mathieu-Daudé 

The acceptance tests aren't accepting anything,
rename them as integration tests.

Reviewed-by: Wainer dos Santos Moschetta 
Reviewed-by: Willian Rampazzo 
Signed-off-by: Philippe Mathieu-Daudé 
---
  .gitlab-ci.yml | 20 ++--
  1 file changed, 10 insertions(+), 10 deletions(-)


Acked-by: Thomas Huth 

FWIW, I'm in favour of renaming the tests/acceptance directory to 
tests/integration , too.

Re: target/ppc: sPAPR invalid function calls when compiling without TCG

[David Gibson]

On Wed, Apr 14, 2021 at 06:28:26PM +, Lucas Mateus Martins Araujo e Castro 
wrote:
> Hi, I have been working on billionai's patch to enable the --disable-tcg 
> option on PowerPC and one of the problems is that 5 files in hw/ppc use 
> functions implemented in mmu-hash64.c which is not compiled with 
> --disable-tcg, I'd like to know how to correct the spapr function call, 
> should I
> 
>   *   change the calls to generic functions that should call the correct 
> function based on if kvm is being used or not,
>   *   should I just implement said functions independently of mmu-hash64.c 
> and always call them,
>   *   should I just implement said functions independently of mmu-hash64.c 
> and only call it with --disable-tcg option turned on,
>   *   find a way to not have said calls when compiling without TCG as they're 
> not necessary,
>   *   just create a stub
> 
> Here's when each function is called by each .c:
> spapr.c:
> function do_lpcr_sync call ppc_store_lpcr

I think ppc_store_lpcr() needs to be moved so that it's compiled with
KVM as well, but #ifdef out the hreg_compute_hflags() line in that case.

> 
> spapr_hcall.c:
> function h_enter call ppc_hash64_hpte_page_shift_noslb, 
> ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
> function remove_hpte call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes 
> and ppc_hash64_tlb_flush_hpte
> function h_protect call ppc_hash64_map_hptes, ppc_hash64_unmap_hptes and 
> ppc_hash64_tlb_flush_hpte
> function h_read call ppc_hash64_map_hptes and ppc_hash64_unmap_hptes
> function rehash_hpte call ppc_hash64_hpte_page_shift_noslb
> function rehash_hpt call ppc_hash64_map_hptes and ppc_hash64_unmap_hptes

h_enter, remove_hpte, h_protect, h_read and rehash_hpte should never
be called for a KVM guest (KVM will intercept the relevant hcalls
before they reach qemu).  I think it would make sense to split of a
TCG only portion of spapr_hcall.c into a new file.  You'll then
probably need !TCG stubs for those hypercalls, which should trip a
fatal error (if KVM hasn't handled the calls, there's nothing we can
do that will salvage the situation).

> spapr_rtas.c:
> function rtas_start_cpu call ppc_store_lpcr
> function rtas_stop_self call ppc_store_lpcr

As above.

> spapr_spapr_cpu_core.c
> function spapr_reset_vcpu call ppc_store_lpcr
> function spapr_cpu_set_entry_state call ppc_store_lpcr

As above.

> spapr_caps.c:
> function cap_large_decr_cpu_apply call ppc_store_lpcr

As above.

> function cap_hpt_maxpagesize_cpu_apply call ppc_hash64_filter_pagesizes

Ok, you definitely need the filter_pagesizes logic, even with KVM, so
that will also have to be moved out of the TCG only file.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH] block/file-posix: Fix problem with fallocate(PUNCH_HOLE) on GPFS

[Thomas Huth]

On 16/04/2021 22.34, Nir Soffer wrote:

On Fri, Apr 16, 2021 at 8:23 AM Thomas Huth  wrote:


A customer reported that running

  qemu-img convert -t none -O qcow2 -f qcow2 input.qcow2 output.qcow2

fails for them with the following error message when the images are
stored on a GPFS file system:

  qemu-img: error while writing sector 0: Invalid argument

After analyzing the strace output, it seems like the problem is in
handle_aiocb_write_zeroes(): The call to fallocate(FALLOC_FL_PUNCH_HOLE)
returns EINVAL, which can apparently happen if the file system has
a different idea of the granularity of the operation. It's arguably
a bug in GPFS, since the PUNCH_HOLE mode should not result in EINVAL
according to the man-page of fallocate(), but the file system is out
there in production and so we have to deal with it. In commit 294682cc3a
("block: workaround for unaligned byte range in fallocate()") we also
already applied the a work-around for the same problem to the earlier
fallocate(FALLOC_FL_ZERO_RANGE) call, so do it now similar with the
PUNCH_HOLE call.

Signed-off-by: Thomas Huth 
---
  block/file-posix.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/block/file-posix.c b/block/file-posix.c
index 20e14f8e96..7a40428d52 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1675,6 +1675,13 @@ static int handle_aiocb_write_zeroes(void *opaque)
  }
  s->has_fallocate = false;
  } else if (ret != -ENOTSUP) {
+if (ret == -EINVAL) {
+/*
+ * File systems like GPFS do not like unaligned byte ranges,
+ * treat it like unsupported (so caller falls back to pwrite)
+ */
+return -ENOTSUP;


This skips the next fallback, using plain fallocate(0) if we write
after the end of the file. Is this intended?

We can treat the buggy EINVAL return value as "filesystem is buggy,
let's not try other options", or "let's try the next option". Since falling
back to actually writing zeroes is so much slower, I think it is better to
try the next option.


I just did the same work-around as in commit 294682cc3a7 ... so if we agree 
to try the other options, too, we should change that spot, too...


However, what is not clear to me, how would you handle s->has_write_zeroes 
and s->has_discard in such a case? Set them to "false"? ... but it could 
still work for some blocks with different alignment ... but if we keep them 
set to "true", the code tries again and again to call these ioctls, maybe 
wasting other precious cycles for this?


Maybe we should do a different approach instead: In case we hit a EINVAL 
here, print an error a la:


 error_report_once("You are running on a buggy file system, please complain 
to the file system vendor");


and return -ENOTSUP ... then it's hopefully clear to the users why they are 
getting a bad performance, and that they should complain to the file system 
vendor instead to get their problem fixed.



This issue affects also libnbd (nbdcopy file backend).

Do we have a bug for GFS?


The GPFS-related bug is:
https://bugzilla.redhat.com/show_bug.cgi?id=1944861

 Thomas

Re: [PATCH v5 3/3] ppc: Enable 2nd DAWR support on p10

[David Gibson]

On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2nd DAWR or not. If it's supported, allow
> user to set the pa-feature bit in guest DT using cap-dawr1 machine
> capability. Though, watchpoint on powerpc TCG guest is not supported
> and thus 2nd DAWR is not enabled for TCG mode.
> 
> Signed-off-by: Ravi Bangoria 
> Reviewed-by: Greg Kurz 

So, I'm actually not sure if using an spapr capability is what we want
to do here.  The problem is that presumably the idea is to at some
point make the DAWR1 capability default to on (on POWER10, at least).
But at that point you'll no longer to be able to start TCG guests
without explicitly disabling it.  That's technically correct, since we
don't implement DAWR1 in TCG, but then we also don't implement DAWR0
and we let that slide... which I think is probably going to cause less
irritation on balance.

I'm wondering if we're actually just better off setting the pa feature
just based on the guest CPU model.  TCG will be broken if you try to
use it, but then, it already is.  AFAIK there's no inherent reason we
couldn't implement DAWR support in TCG, it's just never been worth the
trouble.

> ---
>  hw/ppc/spapr.c  |  7 ++-
>  hw/ppc/spapr_caps.c | 32 
>  include/hw/ppc/spapr.h  |  6 +-
>  target/ppc/cpu.h|  2 ++
>  target/ppc/kvm.c| 12 
>  target/ppc/kvm_ppc.h| 12 
>  target/ppc/translate_init.c.inc | 15 +++
>  7 files changed, 84 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 73a06df3b1..6317fad973 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -238,7 +238,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
>  0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
>  /* 54: DecFP, 56: DecI, 58: SHA */
>  0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> -/* 60: NM atomic, 62: RNG */
> +/* 60: NM atomic, 62: RNG, 64: DAWR1 (ISA 3.1) */
>  0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
>  };
>  uint8_t *pa_features = NULL;
> @@ -279,6 +279,9 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
>   * in pa-features. So hide it from them. */
>  pa_features[40 + 2] &= ~0x80; /* Radix MMU */
>  }
> +if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) {
> +pa_features[66] |= 0x80;
> +}
>  
>  _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, 
> pa_size)));
>  }
> @@ -2003,6 +2006,7 @@ static const VMStateDescription vmstate_spapr = {
>  _spapr_cap_ccf_assist,
>  _spapr_cap_fwnmi,
>  _spapr_fwnmi,
> +_spapr_cap_dawr1,
>  NULL
>  }
>  };
> @@ -4542,6 +4546,7 @@ static void spapr_machine_class_init(ObjectClass *oc, 
> void *data)
>  smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
>  smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
>  smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
> +smc->default_caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF;
>  spapr_caps_add_properties(smc);
>  smc->irq = _irq_dual;
>  smc->dr_phb_enabled = true;
> diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
> index 9ea7ddd1e9..98a6b15f29 100644
> --- a/hw/ppc/spapr_caps.c
> +++ b/hw/ppc/spapr_caps.c
> @@ -523,6 +523,28 @@ static void cap_fwnmi_apply(SpaprMachineState *spapr, 
> uint8_t val,
>  }
>  }
>  
> +static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
> +   Error **errp)
> +{
> +ERRP_GUARD();
> +if (!val) {
> +return; /* Disable by default */
> +}
> +
> +if (tcg_enabled()) {
> +error_setg(errp, "DAWR1 not supported in TCG.");
> +error_append_hint(errp, "Try appending -machine cap-dawr1=off\n");
> +} else if (kvm_enabled()) {
> +if (!kvmppc_has_cap_dawr1()) {
> +error_setg(errp, "DAWR1 not supported by KVM.");
> +error_append_hint(errp, "Try appending -machine 
> cap-dawr1=off\n");
> +} else if (kvmppc_set_cap_dawr1(val) < 0) {
> +error_setg(errp, "Error enabling cap-dawr1 with KVM.");
> +error_append_hint(errp, "Try appending -machine 
> cap-dawr1=off\n");
> +}
> +}
> +}
> +
>  SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
>  [SPAPR_CAP_HTM] = {
>  .name = "htm",
> @@ -631,6 +653,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
>  .type = "bool",
>  .apply = cap_fwnmi_apply,
>  },
> +[SPAPR_CAP_DAWR1] = {
> +.name = "dawr1",
> +.description = "Allow 2nd Data Address Watchpoint 

Re: [PATCH v5 2/3] ppc: Rename current DAWR macros and variables

[David Gibson]

On Mon, Apr 12, 2021 at 05:14:32PM +0530, Ravi Bangoria wrote:
> Power10 is introducing second DAWR. Use real register names (with
> suffix 0) from ISA for current macros and variables used by Qemu.
> 
> One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
> uapi header and thus not changed in kernel as well as Qemu.
> 
> Signed-off-by: Ravi Bangoria 
> Reviewed-by: Greg Kurz 
> Reviewed-by: David Gibson 

This stands independently of the other patches, so I've applied it to 
ppc-for-6.1.

> ---
>  include/hw/ppc/spapr.h  | 2 +-
>  target/ppc/cpu.h| 4 ++--
>  target/ppc/translate_init.c.inc | 4 ++--
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index bf7cab7a2c..5f90bb26d5 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -363,7 +363,7 @@ struct SpaprMachineState {
>  
>  /* Values for 2nd argument to H_SET_MODE */
>  #define H_SET_MODE_RESOURCE_SET_CIABR   1
> -#define H_SET_MODE_RESOURCE_SET_DAWR2
> +#define H_SET_MODE_RESOURCE_SET_DAWR0   2
>  #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
>  #define H_SET_MODE_RESOURCE_LE  4
>  
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index e73416da68..cd02d65303 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1459,10 +1459,10 @@ typedef PowerPCCPU ArchCPU;
>  #define SPR_MPC_BAR   (0x09F)
>  #define SPR_PSPB  (0x09F)
>  #define SPR_DPDES (0x0B0)
> -#define SPR_DAWR  (0x0B4)
> +#define SPR_DAWR0 (0x0B4)
>  #define SPR_RPR   (0x0BA)
>  #define SPR_CIABR (0x0BB)
> -#define SPR_DAWRX (0x0BC)
> +#define SPR_DAWRX0(0x0BC)
>  #define SPR_HFSCR (0x0BE)
>  #define SPR_VRSAVE(0x100)
>  #define SPR_USPRG0(0x100)
> diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
> index c03a7c4f52..879e6df217 100644
> --- a/target/ppc/translate_init.c.inc
> +++ b/target/ppc/translate_init.c.inc
> @@ -7748,12 +7748,12 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
>  
>  static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>  {
> -spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
> +spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
>  SPR_NOACCESS, SPR_NOACCESS,
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_generic, _write_generic,
>  KVM_REG_PPC_DAWR, 0x);
> -spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
> +spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
>  SPR_NOACCESS, SPR_NOACCESS,
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_generic, _write_generic,

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [RFC-PATCH] ppc/spapr: Add support for H_SCM_PERFORMANCE_STATS hcall

[David Gibson]

On Thu, Apr 15, 2021 at 01:23:43PM +0530, Vaibhav Jain wrote:
> Add support for H_SCM_PERFORMANCE_STATS described at [1] for
> spapr nvdimms. This enables guest to fetch performance stats[2] like
> expected life of an nvdimm ('MemLife ') etc and display them to the
> user. Linux kernel support for fetching these performance stats and
> exposing them to the user-space was done via [3].
> 
> The hcall semantics mandate that each nvdimm performance stats is
> uniquely identied by a 8-byte ascii string (e.g 'MemLife ') and its
> value be a 8-byte integer. These performance-stats are exchanged with
> the guest in via a guest allocated buffer called
> 'requestAndResultBuffer' or rr-buffer for short. This buffer contains
> a header descibed by 'struct papr_scm_perf_stats' followed by an array
> of performance-stats described by 'struct papr_scm_perf_stat'. The
> hypervisor is expected to validate the rr-buffer header and then based
> on the request copy the needed performance-stats to the array of
> 'struct papr_scm_perf_stat' following the header.
> 
> The patch proposes a new function h_scm_performance_stats() that
> services the H_SCM_PERFORMANCE_STATS hcall. After verifying the
> validity of the rr-buffer header via scm_perf_check_rr_buffer() it
> proceeds to fill the rr-buffer with requested performance-stats. The
> value of individual stats is retrived from individual accessor
> function for the stat which are indexed in the array
> 'nvdimm_perf_stats'.
> 
> References:
> [1] "Hypercall Op-codes (hcalls)"
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/powerpc/papr_hcalls.rst#n269
> [2] Sysfs attribute documentation for papr_scm
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-bus-papr-pmem#n36
> [3] "powerpc/papr_scm: Fetch nvdimm performance stats from PHYP"
> https://lore.kernel.org/r/20200731064153.182203-2-vaib...@linux.ibm.com
> 
> Signed-off-by: Vaibhav Jain 
> ---
>  hw/ppc/spapr_nvdimm.c  | 243 +
>  include/hw/ppc/spapr.h |  19 +++-
>  2 files changed, 261 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
> index 252204e25f..4830eae4a4 100644
> --- a/hw/ppc/spapr_nvdimm.c
> +++ b/hw/ppc/spapr_nvdimm.c
> @@ -35,6 +35,11 @@
>  /* SCM device is unable to persist memory contents */
>  #define PAPR_PMEM_UNARMED PPC_BIT(0)
>  
> +/* Maximum output buffer size needed to return all nvdimm_perf_stats */
> +#define SCM_STATS_MAX_OUTPUT_BUFFER  (sizeof(struct papr_scm_perf_stats) + \
> +  sizeof(struct papr_scm_perf_stat) * \
> +  ARRAY_SIZE(nvdimm_perf_stats))
> +
>  bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
> uint64_t size, Error **errp)
>  {
> @@ -502,6 +507,243 @@ static target_ulong h_scm_health(PowerPCCPU *cpu, 
> SpaprMachineState *spapr,
>  return H_SUCCESS;
>  }
>  
> +static int perf_stat_noop(SpaprDrc *drc, uint8_t unused[8], uint64_t *val)
> +{
> +*val = 0;
> +return H_SUCCESS;
> +}
> +
> +static int perf_stat_memlife(SpaprDrc *drc, uint8_t unused[8], uint64_t *val)
> +{
> +/* Assume full life available of an NVDIMM right now */
> +*val = 100;

AFAICT the reporting mechanism makes basically all the stats
optional.  Doesn't it make more sense to omit stats, rather than use
dummy values in this case?  Or is this just an example for the RFC?

> +return H_SUCCESS;
> +}
> +
> +/*
> + * Holds all supported performance stats accessors. Each 
> performance-statistic
> + * is uniquely identified by a 8-byte ascii string for example: 'MemLife '
> + * which indicate in percentage how much usage life of an nvdimm is 
> remaining.
> + * 'NoopStat' which is primarily used to test support for retriving 
> performance
> + * stats and also to replace unknown stats present in the rr-buffer.
> + *
> + */
> +static const struct {
> +char stat_id[8];
> +int  (*stat_getval)(SpaprDrc *drc, uint8_t id[8],  uint64_t *val);
> +} nvdimm_perf_stats[] = {
> +{ "NoopStat", perf_stat_noop},
> +{ "MemLife ", perf_stat_memlife},
> +};
> +
> +/*
> + * Given a nvdimm drc and stat-name return its value. In case given stat-name
> + * isnt supported then return H_PARTIAL.
> + */
> +static int nvdimm_stat_getval(SpaprDrc *drc, uint8_t id[8], uint64_t *val)
> +{
> +int index;
> +
> +/* Lookup the stats-id in the nvdimm_perf_stats table */
> +for (index = 0; index < ARRAY_SIZE(nvdimm_perf_stats); ++index) {
> +

No blank line here.

> +if (memcmp(nvdimm_perf_stats[index].stat_id, [0], 8) == 0 &&
> +nvdimm_perf_stats[index].stat_getval) {

I don't see any reason you'd want an entry in the table with a NULL
function, so I don't think you need both tests.

> +

No blank line here either.

> +return nvdimm_perf_stats[index].stat_getval(drc, id, 

[Bug 1816189] Re: Unable to create or revert snapshots

[Launchpad Bug Tracker]

[Expired for QEMU because there has been no activity for 60 days.]

** Changed in: qemu
   Status: Incomplete => Expired

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Title:
  Unable to create or revert snapshots

Status in QEMU:
  Expired

Bug description:
  With an update to Qemu (3.1.x) I am unable to revert snapshots using
  virt-manager or virsh. Virtual Machines existing before the update
  seem to function properly. It is only after creating a new machine
  that snapshots are misbehaving. I tested spinning up vms of
  tumbleweed, leap15, and ubuntu 18.04. Each of them had the following
  issues:

  - With the machine running, live reversions act like they apply, but no 
changes are actually made.
  - With the machine paused, reversion also does not apply.
  - With the machine turned off, reversion is not possible. Virsh is unable to 
find the snapshot, and virt-manager errors out with:

  Error running snapshot 'FreshInstall': internal error: qemu
  unexpectedly closed the monitor: 2019-01-15T19:19:46.020247Z qemu-
  system-x86_64: Device 'drive-virtio-disk0' does not have the requested
  snapshot 'FreshInstall'

  Traceback (most recent call last):
File "/usr/share/virt-manager/virtManager/asyncjob.py", line 75, in 
cb_wrapper
  callback(asyncjob, *args, **kwargs)
File "/usr/share/virt-manager/virtManager/asyncjob.py", line 111, in tmpcb
  callback(*args, **kwargs)
File "/usr/share/virt-manager/virtManager/libvirtobject.py", line 66, in 
newfn
  ret = fn(self, *args, **kwargs)
File "/usr/share/virt-manager/virtManager/domain.py", line 1105, in 
revert_to_snapshot
  self._backend.revertToSnapshot(snap.get_backend())
File "/usr/lib64/python3.6/site-packages/libvirt.py", line 2024, in 
revertToSnapshot
  if ret == -1: raise libvirtError ('virDomainRevertToSnapshot() failed', 
dom=self)

  libvirt.libvirtError: internal error: qemu unexpectedly closed the
  monitor: 2019-01-15T19:19:46.020247Z qemu-system-x86_64: Device
  'drive-virtio-disk0' does not have the requested snapshot
  'FreshInstall'

  After doing some digging, the error occurs because of the following commit:
  d98f26073bebddcd3da0ba1b86c3a34e840c0fb8

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[Bug 1815263] Re: hvf accelerator crashes on quest boot

[Launchpad Bug Tracker]

[Expired for QEMU because there has been no activity for 60 days.]

** Changed in: qemu
   Status: Incomplete => Expired

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Title:
  hvf accelerator crashes on quest boot

Status in QEMU:
  Expired

Bug description:
  Host OS: macOS High Sierra (10.13.6)
  MacBook Pro (Retina, Mid 2015)
  Processor: 2.8GHz Intel Core i7
  Guest OS: OpenBSD 6.4 install media (install64.iso)
  Qemu 3.1.0 release, built with:
  ./configure --prefix=/usr/local/Cellar/qemu/3.1.0_1 --cc=clang
--host-cc=clang
--disable-bsd-user
--disable-guest-agent
--enable-curses
--enable-libssh2
--enable-vde
--extra-cflags=-DNCURSES_WIDECHAR=1
--enable-cocoa
--disable-sdl
--disable-gtk
--enable-hvf
--target-list=x86_64-softmmu
--enable-debug

  I invoke qemu like this:
  Last command had exit code: 0 at 22:58
  nwallace@nwallace-ltm3:~
  $ sudo qemu-system-x86_64 -M accel=hvf -boot d -cdrom 
~/Downloads/install64.iso
  Password:
  qemu-system-x86_64: warning: host doesn't support requested feature: 
CPUID.8001H:ECX.svm [bit 2]
  bad size

  Abort trap: 6
  Last command had exit code: 134 at 22:58
  nwallace@nwallace-ltm3:~
  $

  I ran qemu in lldb to get a stack trace and I get:
  Last command had exit code: 0 at 22:54
  nwallace@nwallace-ltm3:~/Downloads
  $ sudo lldb -- qemu-system-x86_64 -M accel=hvf -boot d -cdrom 
/Users/nwallace/Downloads/install64.iso
  Password:
  (lldb) target create "qemu-system-x86_64"
  Current executable set to 'qemu-system-x86_64' (x86_64).
  (lldb) settings set -- target.run-args  "-M" "accel=hvf" "-boot" "d" "-cdrom" 
"/Users/nwallace/Downloads/install64.i
  so"
  (lldb) run
  Process 96474 launched: '/usr/local/bin/qemu-system-x86_64' (x86_64)
  Process 96474 stopped
  * thread #1, queue = 'com.apple.main-thread', stop reason = signal SIGUSR2
  frame #0: 0x7fff5ef0c00a libsystem_kernel.dylib`__sigsuspend + 10
  libsystem_kernel.dylib`__sigsuspend:
  ->  0x7fff5ef0c00a <+10>: jae0x7fff5ef0c014; <+20>
  0x7fff5ef0c00c <+12>: movq   %rax, %rdi
  0x7fff5ef0c00f <+15>: jmp0x7fff5ef02b0e; cerror
  0x7fff5ef0c014 <+20>: retq
  Target 0: (qemu-system-x86_64) stopped.
  (lldb) process handle SIGUSR1 -n true -p true -s false
  NAME PASS   STOP   NOTIFY
  ===  =  =  ==
  SIGUSR1  true   false  true
  (lldb) process handle SIGUSR2 -n true -p true -s false
  NAME PASS   STOP   NOTIFY
  ===  =  =  ==
  SIGUSR2  true   false  true
  (lldb) c
  Process 96474 resuming
  qemu-system-x86_64: warning: host doesn't support requested feature: 
CPUID.8001H:ECX.svm [bit 2]
  Process 96474 stopped and restarted: thread 9 received signal: SIGUSR2
  
  Process 96474 stopped and restarted: thread 9 received signal: SIGUSR2
  bad size

  Process 96474 stopped
  * thread #9, stop reason = signal SIGABRT
  frame #0: 0x7fff5ef0bb66 libsystem_kernel.dylib`__pthread_kill + 10
  libsystem_kernel.dylib`__pthread_kill:
  ->  0x7fff5ef0bb66 <+10>: jae0x7fff5ef0bb70; <+20>
  0x7fff5ef0bb68 <+12>: movq   %rax, %rdi
  0x7fff5ef0bb6b <+15>: jmp0x7fff5ef02ae9; cerror_nocancel
  0x7fff5ef0bb70 <+20>: retq
  Target 0: (qemu-system-x86_64) stopped.
  (lldb) bt
  * thread #9, stop reason = signal SIGABRT
* frame #0: 0x7fff5ef0bb66 libsystem_kernel.dylib`__pthread_kill + 10
  frame #1: 0x7fff5f0d6080 libsystem_pthread.dylib`pthread_kill + 333
  frame #2: 0x7fff5ee671ae libsystem_c.dylib`abort + 127
  frame #3: 0x00010016b6ec qemu-system-x86_64`exec_cmps_single + 400
  frame #4: 0x00010016ada4 qemu-system-x86_64`exec_cmps + 65
  frame #5: 0x000100169aaa qemu-system-x86_64`exec_instruction + 48
  frame #6: 0x000100164eb2 qemu-system-x86_64`hvf_vcpu_exec + 2658
  frame #7: 0x00010005bed6 qemu-system-x86_64`qemu_hvf_cpu_thread_fn + 
200
  frame #8: 0x0001003ee531 qemu-system-x86_64`qemu_thread_start + 107
  frame #9: 0x7fff5f0d3661 libsystem_pthread.dylib`_pthread_body + 340
  frame #10: 0x7fff5f0d350d libsystem_pthread.dylib`_pthread_start + 377
  frame #11: 0x7fff5f0d2bf9 libsystem_pthread.dylib`thread_start + 13
  (lldb) quit
  Quitting LLDB will kill one or more processes. Do you really want to proceed: 
[Y/n] Y
  Last command had exit code: 0 at 23:01
  nwallace@nwallace-ltm3:~/Downloads
  $

  
  I'm happy to work with someone more knowledgeable to reproduce this issue and 
provide debugging assistance as I'm able.

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[Bug 1815445] Re: change and eject commands are not working on an overlay

[Launchpad Bug Tracker]

[Expired for QEMU because there has been no activity for 60 days.]

** Changed in: qemu
   Status: Incomplete => Expired

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Title:
  change and eject commands are not working on an overlay

Status in QEMU:
  Expired

Bug description:
  From qemu monitor, 'change' and 'eject' commands are not working on a CD 
overlay.
  'info block' returns:
cd0-overlay0: /home/guillaume/test/cd0-overlay0 (qcow2)
  Attached to:  cd0-device
  Removable device: not locked, tray closed
  Cache mode:   writeback, ignore flushes
  Backing file: /home/guillaume/test.iso (chain depth: 1)

  But 'eject cd0-overlay0' returns:
Device 'cd0-overlay0' not found
  I also tried 'cd0-device' and 'cd0'.

  Same problem with 'change' command.

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Re: [PATCH 1/1] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()

[David Gibson]

On Fri, Apr 16, 2021 at 06:09:41PM -0300, Daniel Henrique Barboza wrote:
> The Linux kernel will call set-indicator to move a DRC to 'unisolate' in
> the case a device removal fails. Setting a DRC that is already

Only issue I have with this patch is that this isn't quite accurate
yet.  Can you reword this to include some of the rationale from the
cover letters about how a previous no-op is a safe choice to allow
guest->hv error signalling and that we expect the Linux kernel to use
it at some point.

> unisolated or configured to 'unisolate' is a no-op for the current
> hypervisors that supports pSeries guests, namely QEMU and phyp, and is
> being used to signal hotunplug errors if the hypervisor has the code for
> it.
> 
> This patch changes drc_unisolate_logical() to implement in the pSeries
> machine. For CPUs it's a simple matter of setting drc->unplug_requested
> to 'false', while for LMBs the process is similar to the rollback that
> is done in rtas_ibm_configure_connector(). Although at this moment the
> Linux kernel is only reporting CPU removal errors, let's get the code
> ready to handle LMBs as well.
> 
> Signed-off-by: Daniel Henrique Barboza 

Otherwise,

Reviewed-by: David Gibson 

> ---
>  hw/ppc/spapr_drc.c | 23 +++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
> index 9e16505fa1..6918e0c9d1 100644
> --- a/hw/ppc/spapr_drc.c
> +++ b/hw/ppc/spapr_drc.c
> @@ -151,9 +151,32 @@ static uint32_t drc_isolate_logical(SpaprDrc *drc)
>  
>  static uint32_t drc_unisolate_logical(SpaprDrc *drc)
>  {
> +SpaprMachineState *spapr = NULL;
> +
>  switch (drc->state) {
>  case SPAPR_DRC_STATE_LOGICAL_UNISOLATE:
>  case SPAPR_DRC_STATE_LOGICAL_CONFIGURED:
> +/*
> + * Unisolating a logical DRC that was marked for unplug
> + * means that the kernel is refusing the removal.
> + */
> +if (drc->unplug_requested && drc->dev) {
> +if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB) {
> +spapr = SPAPR_MACHINE(qdev_get_machine());
> +
> +spapr_memory_unplug_rollback(spapr, drc->dev);
> +}
> +
> +drc->unplug_requested = false;
> +error_report("Device hotunplug rejected by the guest "
> + "for device %s", drc->dev->id);
> +
> +/*
> + * TODO: send a QAPI DEVICE_UNPLUG_ERROR event when
> + * it is implemented.
> + */
> +}
> +
>  return RTAS_OUT_SUCCESS; /* Nothing to do */
>  case SPAPR_DRC_STATE_LOGICAL_AVAILABLE:
>  break; /* see below */

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [RFC PATCH v2 1/6] device_tree: Add qemu_fdt_add_path

[David Gibson]

On Sat, Apr 17, 2021 at 10:36:20AM +0800, wangyanan (Y) wrote:
> Hi David,
> 
> On 2021/4/16 12:52, David Gibson wrote:
> > On Tue, Apr 13, 2021 at 04:07:40PM +0800, Yanan Wang wrote:
> > > From: Andrew Jones 
> > > 
> > > qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
> > > it also adds any missing subnodes in the path. We also tweak
> > > an error message of qemu_fdt_add_subnode().
> > > 
> > > We'll make use of this new function in a coming patch.
> > > 
> > > Signed-off-by: Andrew Jones 
> > > Signed-off-by: Yanan Wang 
> > > ---
> > >   include/sysemu/device_tree.h |  1 +
> > >   softmmu/device_tree.c| 45 ++--
> > >   2 files changed, 44 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h
> > > index 8a2fe55622..ef060a9759 100644
> > > --- a/include/sysemu/device_tree.h
> > > +++ b/include/sysemu/device_tree.h
> > > @@ -121,6 +121,7 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const char 
> > > *path);
> > >   uint32_t qemu_fdt_alloc_phandle(void *fdt);
> > >   int qemu_fdt_nop_node(void *fdt, const char *node_path);
> > >   int qemu_fdt_add_subnode(void *fdt, const char *name);
> > > +int qemu_fdt_add_path(void *fdt, const char *path);
> > >   #define qemu_fdt_setprop_cells(fdt, node_path, property, ...)   
> > >   \
> > >   do {
> > >   \
> > > diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c
> > > index 2691c58cf6..8592c7aa1b 100644
> > > --- a/softmmu/device_tree.c
> > > +++ b/softmmu/device_tree.c
> > > @@ -541,8 +541,8 @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
> > >   retval = fdt_add_subnode(fdt, parent, basename);
> > >   if (retval < 0) {
> > > -error_report("FDT: Failed to create subnode %s: %s", name,
> > > - fdt_strerror(retval));
> > > +error_report("%s: Failed to create subnode %s: %s",
> > > + __func__, name, fdt_strerror(retval));
> > >   exit(1);
> > >   }
> > > @@ -550,6 +550,47 @@ int qemu_fdt_add_subnode(void *fdt, const char *name)
> > >   return retval;
> > >   }
> > > +/*
> > > + * Like qemu_fdt_add_subnode(), but will add all missing
> > > + * subnodes in the path.
> > > + */
> > > +int qemu_fdt_add_path(void *fdt, const char *path)
> > > +{
> > > +char *dupname, *basename, *p;
> > > +int parent, retval = -1;
> > > +
> > > +if (path[0] != '/') {
> > > +return retval;
> > > +}
> > > +
> > > +parent = fdt_path_offset(fdt, "/");
> > Getting the offset for "/" is never needed - it's always 0.
> Thanks, will fix it.
> > > +p = dupname = g_strdup(path);
> > You shouldn't need the strdup(), see below.
> > 
> > > +
> > > +while (p) {
> > > +*p = '/';
> > > +basename = p + 1;
> > > +p = strchr(p + 1, '/');
> > > +if (p) {
> > > +*p = '\0';
> > > +}
> > > +retval = fdt_path_offset(fdt, dupname);
> > The fdt_path_offset_namelen() function exists *exactly* so that you
> > can look up partial parths without having to mangle your input
> > string.  Just set the namelen right, and it will ignore anything to
> > the right of that.
> Function fdt_path_offset_namelen() seems more reasonable.
> 
> After we call qemu_fdt_add_path() to add "/cpus/cpu-map/socket0/core0"
> successfully,
> if we want to add another path like "/cpus/cpu-map/socket0/core1" we will
> get the error
> -FDT_ERR_NOTFOUND for each partial path. But actually
> "/cpus/cpu-map/socket0"
> already exists, so by using fdt_path_offset_namelen() with right namelen we
> can avoid
> the error retval for this part.

I don't quite follow what you're saying here.  AFAICT your logic was
correct - it just involved a lot of mangling the given path (adding
and removing \0s) which becomes unnecessary with
fdt_path_offset_namelen().

> > > +if (retval < 0 && retval != -FDT_ERR_NOTFOUND) {
> > > +error_report("%s: Invalid path %s: %s",
> > > + __func__, path, fdt_strerror(retval));
> > If you're getting an error other than FDT_ERR_NOTFOUND here, chances
> > are it's not an invalid path, but a corrupted fdt blob or something
> > else.
> 
> Right, there can be variable reasons for the fail in addition to the invalid
> path.
> 
> > > +exit(1);
> > > +} else if (retval == -FDT_ERR_NOTFOUND) {
> > > +retval = fdt_add_subnode(fdt, parent, basename);
> > > +if (retval < 0) {
> > > +break;
> > > +}
> I found another question here. If path "/cpus/cpu-map/socket0/core0" has
> already
> been added, when we want to add another path "/cpus/cpu-map/socket0/core1"
> and go here with retval = fdt_add_subnode(fdt, parent, "cpus"), then retval
> will
> be -FDT_ERR_EXISTS, but we can't just break the loop in this case.
> 
> Am I right of the explanation 

Re: [RFC PATCH 0/3] tests/tcg/ppc64le: paddi tests

[David Gibson]

On Fri, Apr 16, 2021 at 11:13:48AM -0300, Matheus K. Ferst wrote:
> On 16/04/2021 00:52, David Gibson wrote:
> > On Thu, Apr 15, 2021 at 06:41:35PM -0300, matheus.fe...@eldorado.org.br 
> > wrote:
> > > From: Matheus Ferst 
> > > 
> > > Based-on: <20210413211129.457272-1-luis.pi...@eldorado.org.br>
> > 
> > First things first: it's unclear to me if this is testing stuff that's
> > already merged, or it's speculative tests for the in-progress prefixed
> > instruction stuff.  i.e. If these tests are applied right now, will
> > they pass?
> 
> GCC-10 images can be used to test already merged Power10 instructions, such
> as brh/brw/brd, but I haven't writen tests for them (yet?). Both tests are
> targeting paddi, whose implementation is in-progress, so applying them now
> will fail. Maybe I should split the series? Patch 1 for now, and Patch 2 and
> 3 when paddi are merged?

That sounds reasonable, as long as patch 1 does *something* visible
now (e.g. running existing tests with the new compiler).

> 
> > > This series adds gcc-10 based images to enable the build of tests with 
> > > Power10
> > > instructions. Then two tests for paddi are added:
> > > - The first one checks a weird behavior observed on POWER10 Functional 
> > > Simulator
> > >1.1.0, where the 34-bit immediate is treated as a 32-bits one;
> > > - The second one exercises the R=1 path of paddi, where CIA is used 
> > > instead of RA.
> > >The test is failing with the current implementation because we use 
> > > cpu_nip,
> > >which is not updated all the time. Luis already has the fix, it should 
> > > be
> > >applied on the next version of his patch series.
> > > 
> > > The main reason to submit this patch as an RFC first is the docker part. 
> > > I would
> > > lie if I tell you that I understand half of what is going on there.
> > >   - 'make docker-test-tcg' fails, but apparently on unrelated things;
> > >   - 'make docker-run-test-tcg@debian-ppc64el-cross' passes, but it looks
> > > like the test is skipped?
> > >   - 'make check-tcg' runs the test and passes (with the fix in place for 
> > > the
> > > second).
> > 
> > What sort of host was that on?  Unfortunately 'make check-tcg' has
> > been broken on a POWER host for some time, and I've never had time to
> > look into it.
> > 
> 
> I'm testing on amd64, but I can also try on ppc64le.
> 
> > > 
> > > Finally, get_maintainer.pl found no maintainers for
> > > tests/tcg/ppc64{,le}/Makefile.target. Would it be Mr. Gibson?
> > 
> > Uh... sorta?  I also don't know much about what's going on here, but
> > I'm probably maintainer by default.
> > 
> 
> So, should I update MAINTAINERS in this series?
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH v2 06/11] hw/pci-host/raven: Assert PCI I/O AddressSpace is based at 0x80000000

[David Gibson]

On Sat, Apr 17, 2021 at 12:30:23PM +0200, Philippe Mathieu-Daudé wrote:
> Commit 1ae1dc5ba24 ("raven: Set a correct PCI I/O memory region")
> abused an AddressSpace API weakness which allows set non-zero base
> address to AddressSpace root region. We will fix that in the next
> commit. First add an assertion to ensure no regression is introduced.
> As raven_io_address() is called by both MemoryRegionOps handlers, it
> is a good place for such assert call.
> 
> Signed-off-by: Philippe Mathieu-Daudé 

Acked-by: David Gibson 

> ---
>  hw/pci-host/raven.c | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
> index 730f31a8931..36652122424 100644
> --- a/hw/pci-host/raven.c
> +++ b/hw/pci-host/raven.c
> @@ -141,6 +141,17 @@ static const MemoryRegionOps raven_intack_ops = {
>  static inline hwaddr raven_io_address(PREPPCIState *s,
>hwaddr addr)
>  {
> +/*
> + * We shouldn't access AddressSpace internals. However this assert
> + * is temporarily introduced to prove a subtle inconsistency from
> + * commit 1ae1dc5ba24 ("raven: Set a correct PCI I/O memory region"):
> + * AddressSpace root region must be zero-based, but the Raven use is not.
> + *
> + * Assert the root region is based on physical address 0x8000
> + * until the issue is fixed.
> + */
> +assert(s->pci_io_as.root->addr == PCI_IO_BASE_ADDR);
> +
>  if (s->contiguous_map == 0) {
>  /* 64 KB contiguous space for IOs */
>  addr &= 0x;

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH v2 05/11] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition

[David Gibson]

On Sat, Apr 17, 2021 at 12:30:22PM +0200, Philippe Mathieu-Daudé wrote:
> Rather than using the magic 0x8000 number for the PCI I/O BAR
> physical address on the main system bus, use a definition.
> 
> Signed-off-by: Philippe Mathieu-Daudé 

Acked-by: David Gibson 

> ---
>  hw/pci-host/raven.c | 11 +++
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
> index 0a9162fba97..730f31a8931 100644
> --- a/hw/pci-host/raven.c
> +++ b/hw/pci-host/raven.c
> @@ -82,6 +82,8 @@ struct PRePPCIState {
>  
>  #define BIOS_SIZE (1 * MiB)
>  
> +#define PCI_IO_BASE_ADDR0x8000  /* Physical address on main bus */
> +
>  static inline uint32_t raven_pci_io_config(hwaddr addr)
>  {
>  int i;
> @@ -159,7 +161,7 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr,
>  uint8_t buf[4];
>  
>  addr = raven_io_address(s, addr);
> -address_space_read(>pci_io_as, addr + 0x8000,
> +address_space_read(>pci_io_as, addr + PCI_IO_BASE_ADDR,
> MEMTXATTRS_UNSPECIFIED, buf, size);
>  
>  if (size == 1) {
> @@ -191,7 +193,7 @@ static void raven_io_write(void *opaque, hwaddr addr,
>  g_assert_not_reached();
>  }
>  
> -address_space_write(>pci_io_as, addr + 0x8000,
> +address_space_write(>pci_io_as, addr + PCI_IO_BASE_ADDR,
>  MEMTXATTRS_UNSPECIFIED, buf, size);
>  }
>  
> @@ -294,8 +296,9 @@ static void raven_pcihost_initfn(Object *obj)
>  address_space_init(>pci_io_as, >pci_io, "raven-io");
>  
>  /* CPU address space */
> -memory_region_add_subregion(address_space_mem, 0x8000, >pci_io);
> -memory_region_add_subregion_overlap(address_space_mem, 0x8000,
> +memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
> +>pci_io);
> +memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
>  >pci_io_non_contiguous, 1);
>  memory_region_add_subregion(address_space_mem, 0xc000, 
> >pci_memory);
>  pci_root_bus_new_inplace(>pci_bus, sizeof(s->pci_bus), DEVICE(obj), 
> NULL,

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH v2 04/11] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

[David Gibson]

On Sat, Apr 17, 2021 at 12:30:21PM +0200, Philippe Mathieu-Daudé wrote:
> The ASIC PCI bridge chipset from Motorola is named 'Raven'.
> This chipset is used in the PowerPC Reference Platform (PReP),
> but not restricted to it. Rename it accordingly.
> 
> Signed-off-by: Philippe Mathieu-Daudé 

Acked-by: David Gibson 

> ---
>  hw/pci-host/{prep.c => raven.c} | 0
>  MAINTAINERS | 2 +-
>  hw/pci-host/Kconfig | 2 +-
>  hw/pci-host/meson.build | 2 +-
>  hw/ppc/Kconfig  | 2 +-
>  5 files changed, 4 insertions(+), 4 deletions(-)
>  rename hw/pci-host/{prep.c => raven.c} (100%)
> 
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/raven.c
> similarity index 100%
> rename from hw/pci-host/prep.c
> rename to hw/pci-host/raven.c
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 36055f14c59..0e8f9cbc2ab 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1302,7 +1302,7 @@ S: Maintained
>  F: hw/ppc/prep.c
>  F: hw/ppc/prep_systemio.c
>  F: hw/ppc/rs6000_mc.c
> -F: hw/pci-host/prep.[hc]
> +F: hw/pci-host/raven.c
>  F: hw/isa/i82378.c
>  F: hw/isa/pc87312.c
>  F: hw/dma/i82374.c
> diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
> index 2ccc96f02ce..593d90e5588 100644
> --- a/hw/pci-host/Kconfig
> +++ b/hw/pci-host/Kconfig
> @@ -6,7 +6,7 @@ config XEN_IGD_PASSTHROUGH
>  default y
>  depends on XEN && PCI_I440FX
>  
> -config PREP_PCI
> +config RAVEN_PCI
>  bool
>  select PCI
>  select OR_IRQ
> diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
> index 87a896973e7..2460f365471 100644
> --- a/hw/pci-host/meson.build
> +++ b/hw/pci-host/meson.build
> @@ -13,7 +13,7 @@
>  pci_ss.add(when: 'CONFIG_SH_PCI', if_true: files('sh_pci.c'))
>  
>  # PPC devices
> -pci_ss.add(when: 'CONFIG_PREP_PCI', if_true: files('prep.c'))
> +pci_ss.add(when: 'CONFIG_RAVEN_PCI', if_true: files('raven.c'))
>  pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
>  # NewWorld PowerMac
>  pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index d11dc30509d..ebbe95eb90f 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -73,7 +73,7 @@ config PREP
>  imply PCI_DEVICES
>  imply TEST_DEVICES
>  select CS4231A
> -select PREP_PCI
> +select RAVEN_PCI
>  select I82378
>  select LSI_SCSI_PCI
>  select M48T59

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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[RFC PATCH 13/15] gitlab-ci: Switch to dynamically generated pipelines

[Philippe Mathieu-Daudé]

Switch to the dynamically generated pipeline scheme described in:
https://docs.gitlab.com/ee/ci/parent_child_pipelines.html#dynamic-child-pipelines

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 533a7e61339..718c8e004be 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,2 +1,21 @@
-include:
-  - local: '/.gitlab-ci.d/qemu-project.yml'
+# Dynamic child pipelines
+# 
https://docs.gitlab.com/ee/ci/parent_child_pipelines.html#dynamic-child-pipelines
+
+generate-config:
+  stage: build
+  variables:
+GIT_SUBMODULE_STRATEGY: none
+  artifacts:
+paths:
+  - generated-config.yml
+  script:
+- cp .gitlab-ci.d/qemu-project.yml generated-config.yml
+
+generate-pipeline:
+  stage: test
+  variables:
+GIT_SUBMODULE_STRATEGY: none
+  trigger:
+include:
+  - artifact: generated-config.yml
+job: generate-config
-- 
2.26.3

[PATCH 12/15] gitlab-ci: Move current job set to qemu-project.yml

[Philippe Mathieu-Daudé]

To allow forks to easily decide which jobs they want to run,
but without disrupting the current default, move the current
set of jobs to a new file corresponding to the jobs run by
the mainstream project CI:
https://gitlab.com/qemu-project/qemu/-/pipelines

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/qemu-project.yml | 8 
 .gitlab-ci.yml| 8 +---
 2 files changed, 9 insertions(+), 7 deletions(-)
 create mode 100644 .gitlab-ci.d/qemu-project.yml

diff --git a/.gitlab-ci.d/qemu-project.yml b/.gitlab-ci.d/qemu-project.yml
new file mode 100644
index 000..8f13a584a29
--- /dev/null
+++ b/.gitlab-ci.d/qemu-project.yml
@@ -0,0 +1,8 @@
+include:
+  - local: '/.gitlab-ci.d/stages.yml'
+  - local: '/.gitlab-ci.d/edk2.yml'
+  - local: '/.gitlab-ci.d/opensbi.yml'
+  - local: '/.gitlab-ci.d/containers.yml'
+  - local: '/.gitlab-ci.d/crossbuilds.yml'
+  - local: '/.gitlab-ci.d/buildtest.yml'
+  - local: '/.gitlab-ci.d/checks.yml'
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8f13a584a29..533a7e61339 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,8 +1,2 @@
 include:
-  - local: '/.gitlab-ci.d/stages.yml'
-  - local: '/.gitlab-ci.d/edk2.yml'
-  - local: '/.gitlab-ci.d/opensbi.yml'
-  - local: '/.gitlab-ci.d/containers.yml'
-  - local: '/.gitlab-ci.d/crossbuilds.yml'
-  - local: '/.gitlab-ci.d/buildtest.yml'
-  - local: '/.gitlab-ci.d/checks.yml'
+  - local: '/.gitlab-ci.d/qemu-project.yml'
-- 
2.26.3

[RFC PATCH 14/15] gitlab-ci: Allow forks to use different set of jobs

[Philippe Mathieu-Daudé]

Forks run the same jobs than mainstream, which might be overkill.
Allow them to easily rebase their custom set, while keeping using
the mainstream templates, and ability to pick specific jobs from
the mainstream set.

To switch to your set, simply add your .gitlab-ci.yml as
.gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml (where CI_PROJECT_NAMESPACE
is your gitlab 'namespace', usually username). This file will be
used instead of the default mainstream set.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 718c8e004be..35fd35075db 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -9,7 +9,12 @@ generate-config:
 paths:
   - generated-config.yml
   script:
-- cp .gitlab-ci.d/qemu-project.yml generated-config.yml
+- if test -e .gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml ;
+  then
+cp .gitlab-ci.d/${CI_PROJECT_NAMESPACE}.yml generated-config.yml ;
+  else
+cp .gitlab-ci.d/qemu-project.yml generated-config.yml ;
+  fi
 
 generate-pipeline:
   stage: test
-- 
2.26.3

[PATCH 07/15] gitlab-ci: Extract crossbuild job templates to crossbuild-template.yml

[Philippe Mathieu-Daudé]

Extract the crossbuild job templates to a new file
(crossbuild-template.yml) to be able to reuse them
without having to run all the jobs included, which
are mainly useful for mainstream CI.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/crossbuild-template.yml | 41 ++
 .gitlab-ci.d/crossbuilds.yml | 43 ++--
 2 files changed, 43 insertions(+), 41 deletions(-)
 create mode 100644 .gitlab-ci.d/crossbuild-template.yml

diff --git a/.gitlab-ci.d/crossbuild-template.yml 
b/.gitlab-ci.d/crossbuild-template.yml
new file mode 100644
index 000..bc790a43486
--- /dev/null
+++ b/.gitlab-ci.d/crossbuild-template.yml
@@ -0,0 +1,41 @@
+.cross_system_build_job:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  timeout: 80m
+  script:
+- mkdir build
+- cd build
+- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
+  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
+--disable-user --target-list-exclude="arm-softmmu cris-softmmu
+  i386-softmmu microblaze-softmmu mips-softmmu mipsel-softmmu
+  mips64-softmmu ppc-softmmu sh4-softmmu xtensa-softmmu"
+- make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
+
+# Job to cross-build specific accelerators.
+#
+# Set the $ACCEL variable to select the specific accelerator (default to
+# KVM), and set extra options (such disabling other accelerators) via the
+# $ACCEL_CONFIGURE_OPTS variable.
+.cross_accel_build_job:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  timeout: 30m
+  script:
+- mkdir build
+- cd build
+- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
+  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
+--disable-tools --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS
+- make -j$(expr $(nproc) + 1) all check-build
+
+.cross_user_build_job:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  script:
+- mkdir build
+- cd build
+- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
+  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
+--disable-system
+- make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 2d95784ed51..7a0d2069c14 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -1,44 +1,5 @@
-.cross_system_build_job:
-  stage: build
-  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
-  timeout: 80m
-  script:
-- mkdir build
-- cd build
-- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
-  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
---disable-user --target-list-exclude="arm-softmmu cris-softmmu
-  i386-softmmu microblaze-softmmu mips-softmmu mipsel-softmmu
-  mips64-softmmu ppc-softmmu sh4-softmmu xtensa-softmmu"
-- make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
-
-# Job to cross-build specific accelerators.
-#
-# Set the $ACCEL variable to select the specific accelerator (default to
-# KVM), and set extra options (such disabling other accelerators) via the
-# $ACCEL_CONFIGURE_OPTS variable.
-.cross_accel_build_job:
-  stage: build
-  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
-  timeout: 30m
-  script:
-- mkdir build
-- cd build
-- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
-  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
---disable-tools --enable-${ACCEL:-kvm} $ACCEL_CONFIGURE_OPTS
-- make -j$(expr $(nproc) + 1) all check-build
-
-.cross_user_build_job:
-  stage: build
-  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
-  script:
-- mkdir build
-- cd build
-- PKG_CONFIG_PATH=$PKG_CONFIG_PATH
-  ../configure --enable-werror --disable-docs $QEMU_CONFIGURE_OPTS
---disable-system
-- make -j$(expr $(nproc) + 1) all check-build $MAKE_CHECK_ARGS
+include:
+  - local: '/.gitlab-ci.d/crossbuild-template.yml'
 
 cross-armel-system:
   extends: .cross_system_build_job
-- 
2.26.3

[NOTFORMERGE PATCH 15/15] gitlab-ci: Use my own set of jobs for CI pipeline

[Philippe Mathieu-Daudé]

This is an example to use a different set of jobs than the
mainstream one (currently 116 jobs).

Here I only select 2 jobs:
- cross-s390x-kvm-only
- build-libvhost-user

Including their dependencies, I have to run 8 jobs.

Result (build time 15 minutes and 25 seconds):
  https://gitlab.com/philmd/qemu/-/pipelines/284362446

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/philmd.yml | 33 +
 1 file changed, 33 insertions(+)
 create mode 100644 .gitlab-ci.d/philmd.yml

diff --git a/.gitlab-ci.d/philmd.yml b/.gitlab-ci.d/philmd.yml
new file mode 100644
index 000..402228e6ed1
--- /dev/null
+++ b/.gitlab-ci.d/philmd.yml
@@ -0,0 +1,33 @@
+include:
+  - local: '/.gitlab-ci.d/stages.yml'
+  - local: '/.gitlab-ci.d/container-core.yml'
+  - local: '/.gitlab-ci.d/crossbuild-template.yml'
+  - local: '/.gitlab-ci.d/checks.yml'
+
+build-libvhost-user:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/fedora:latest
+  needs:
+job: amd64-fedora-container
+  before_script:
+- dnf install -y meson ninja-build
+  script:
+- mkdir subprojects/libvhost-user/build
+- cd subprojects/libvhost-user/build
+- meson
+- ninja
+
+s390x-debian-cross-container:
+  extends: .container_job_template
+  stage: containers-layer2
+  needs: ['amd64-debian10-container']
+  variables:
+NAME: debian-s390x-cross
+
+cross-s390x-kvm-only:
+  extends: .cross_accel_build_job
+  needs:
+job: s390x-debian-cross-container
+  variables:
+IMAGE: debian-s390x-cross
+ACCEL_CONFIGURE_OPTS: --disable-tcg
-- 
2.26.3

[PATCH 08/15] gitlab-ci: Extract DCO/style check jobs to checks.yml

[Philippe Mathieu-Daudé]

Extract the DCO / checkpatch jobs to a new file (checks.yml)
to be able to run them without having to run all the jobs
included in the default .gitlab-ci.yml, which are mainly useful
for mainstream CI.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/checks.yml | 24 
 .gitlab-ci.yml  |  1 +
 2 files changed, 25 insertions(+)
 create mode 100644 .gitlab-ci.d/checks.yml

diff --git a/.gitlab-ci.d/checks.yml b/.gitlab-ci.d/checks.yml
new file mode 100644
index 000..f695627b7cd
--- /dev/null
+++ b/.gitlab-ci.d/checks.yml
@@ -0,0 +1,24 @@
+check-patch:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-patch.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000
+  allow_failure: true
+
+check-dco:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
+  needs:
+job: amd64-centos8-container
+  script: .gitlab-ci.d/check-dco.py
+  except:
+variables:
+  - $CI_PROJECT_NAMESPACE == 'qemu-project' && $CI_COMMIT_BRANCH == 
'master'
+  variables:
+GIT_DEPTH: 1000
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index bf4862a78de..ba35b3917e7 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -12,6 +12,7 @@ include:
   - local: '/.gitlab-ci.d/opensbi.yml'
   - local: '/.gitlab-ci.d/containers.yml'
   - local: '/.gitlab-ci.d/crossbuilds.yml'
+  - local: '/.gitlab-ci.d/checks.yml'
 
 .native_build_job_template:
   stage: build
-- 
2.26.3

[PATCH 10/15] gitlab-ci: Extract all default build/test jobs to buildtest.yml

[Philippe Mathieu-Daudé]

Extract the build/test jobs run by default on the mainstream
CI into a new file (buildtest.yml) and their templates into
(buildtest-template.yml), to be able to reuse the templates
without having to run all these mainstream jobs by default.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/buildtest-template.yml |  80 +++
 .gitlab-ci.d/buildtest.yml  | 744 +
 .gitlab-ci.yml  | 824 +---
 3 files changed, 825 insertions(+), 823 deletions(-)
 create mode 100644 .gitlab-ci.d/buildtest-template.yml
 create mode 100644 .gitlab-ci.d/buildtest.yml

diff --git a/.gitlab-ci.d/buildtest-template.yml 
b/.gitlab-ci.d/buildtest-template.yml
new file mode 100644
index 000..b24a153d904
--- /dev/null
+++ b/.gitlab-ci.d/buildtest-template.yml
@@ -0,0 +1,80 @@
+.native_build_job_template:
+  stage: build
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  before_script:
+- JOBS=$(expr $(nproc) + 1)
+  script:
+- mkdir build
+- cd build
+- if test -n "$TARGETS";
+  then
+../configure --enable-werror --disable-docs $CONFIGURE_ARGS 
--target-list="$TARGETS" ;
+  else
+../configure --enable-werror --disable-docs $CONFIGURE_ARGS ;
+  fi || { cat config.log meson-logs/meson-log.txt && exit 1; }
+- if test -n "$LD_JOBS";
+  then
+meson configure . -Dbackend_max_links="$LD_JOBS" ;
+  fi || exit 1;
+- make -j"$JOBS"
+- if test -n "$MAKE_CHECK_ARGS";
+  then
+make -j"$JOBS" $MAKE_CHECK_ARGS ;
+  fi
+
+.native_test_job_template:
+  stage: test
+  image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
+  script:
+- scripts/git-submodule.sh update
+$(sed -n '/GIT_SUBMODULES=/ s/.*=// p' build/config-host.mak)
+- cd build
+- find . -type f -exec touch {} +
+# Avoid recompiling by hiding ninja with NINJA=":"
+- make NINJA=":" $MAKE_CHECK_ARGS
+
+.integration_test_job_template:
+  cache:
+key: "${CI_JOB_NAME}-cache"
+paths:
+  - ${CI_PROJECT_DIR}/avocado-cache
+policy: pull-push
+  artifacts:
+name: "$CI_JOB_NAME-$CI_COMMIT_REF_SLUG"
+when: always
+expire_in: 2 days
+paths:
+  - build/tests/results/latest/results.xml
+  - build/tests/results/latest/test-results
+reports:
+  junit: build/tests/results/latest/results.xml
+  before_script:
+- mkdir -p ~/.config/avocado
+- echo "[datadir.paths]" > ~/.config/avocado/avocado.conf
+- echo "cache_dirs = ['${CI_PROJECT_DIR}/avocado-cache']"
+   >> ~/.config/avocado/avocado.conf
+- echo -e '[job.output.testlogs]\nstatuses = ["FAIL", "INTERRUPT"]'
+   >> ~/.config/avocado/avocado.conf
+- if [ -d ${CI_PROJECT_DIR}/avocado-cache ]; then
+du -chs ${CI_PROJECT_DIR}/avocado-cache ;
+  fi
+- export AVOCADO_ALLOW_UNTRUSTED_CODE=1
+  after_script:
+- cd build
+- du -chs ${CI_PROJECT_DIR}/avocado-cache
+
+build-system-alpine:
+  extends: .native_build_job_template
+  needs:
+- job: amd64-alpine-container
+  variables:
+IMAGE: alpine
+TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
+  moxie-softmmu microblazeel-softmmu mips64el-softmmu
+MAKE_CHECK_ARGS: check-build
+CONFIGURE_ARGS: --enable-docs --enable-trace-backends=log,simple,syslog
+  artifacts:
+expire_in: 2 days
+paths:
+  - .git-submodule-status
+  - build
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
new file mode 100644
index 000..c24553eab05
--- /dev/null
+++ b/.gitlab-ci.d/buildtest.yml
@@ -0,0 +1,744 @@
+include:
+  - local: '/.gitlab-ci.d/buildtest-template.yml'
+
+check-system-alpine:
+  extends: .native_test_job_template
+  needs:
+- job: build-system-alpine
+  artifacts: true
+  variables:
+IMAGE: alpine
+MAKE_CHECK_ARGS: check
+
+acceptance-system-alpine:
+  extends: .native_test_job_template
+  needs:
+- job: build-system-alpine
+  artifacts: true
+  variables:
+IMAGE: alpine
+MAKE_CHECK_ARGS: check-acceptance
+  extends: .integration_test_job_template
+
+build-system-ubuntu:
+  extends: .native_build_job_template
+  needs:
+job: amd64-ubuntu2004-container
+  variables:
+IMAGE: ubuntu2004
+CONFIGURE_ARGS: --enable-docs --enable-fdt=system --enable-slirp=system
+TARGETS: aarch64-softmmu alpha-softmmu cris-softmmu hppa-softmmu
+  moxie-softmmu microblazeel-softmmu mips64el-softmmu
+MAKE_CHECK_ARGS: check-build
+  artifacts:
+expire_in: 2 days
+paths:
+  - build
+
+check-system-ubuntu:
+  extends: .native_test_job_template
+  needs:
+- job: build-system-ubuntu
+  artifacts: true
+  variables:
+IMAGE: ubuntu2004
+MAKE_CHECK_ARGS: check
+
+acceptance-system-ubuntu:
+  extends: .native_test_job_template
+  needs:
+- job: build-system-ubuntu
+  artifacts: true
+  variables:
+IMAGE: ubuntu2004
+MAKE_CHECK_ARGS: check-acceptance
+  extends: 

[PATCH 06/15] gitlab-ci: Extract container job template to container-template.yml

[Philippe Mathieu-Daudé]

Extract the container job template to a new file
(container-template.yml) to be able to reuse it
without having to run all the jobs included, which
are mainly useful for mainstream CI.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/container-template.yml | 22 ++
 .gitlab-ci.d/containers.yml | 24 ++--
 2 files changed, 24 insertions(+), 22 deletions(-)
 create mode 100644 .gitlab-ci.d/container-template.yml

diff --git a/.gitlab-ci.d/container-template.yml 
b/.gitlab-ci.d/container-template.yml
new file mode 100644
index 000..9e3f3ae3c26
--- /dev/null
+++ b/.gitlab-ci.d/container-template.yml
@@ -0,0 +1,22 @@
+.container_job_template:
+  image: docker:stable
+  stage: containers
+  services:
+- docker:dind
+  before_script:
+- export TAG="$CI_REGISTRY_IMAGE/qemu/$NAME:latest"
+- export COMMON_TAG="$CI_REGISTRY/qemu-project/qemu/$NAME:latest"
+- apk add python3
+- docker info
+- docker login $CI_REGISTRY -u "$CI_REGISTRY_USER" -p 
"$CI_REGISTRY_PASSWORD"
+  script:
+- echo "TAG:$TAG"
+- echo "COMMON_TAG:$COMMON_TAG"
+- docker pull "$TAG" || docker pull "$COMMON_TAG" || true
+- ./tests/docker/docker.py --engine docker build
+  -t "qemu/$NAME" -f "tests/docker/dockerfiles/$NAME.docker"
+  -r $CI_REGISTRY_IMAGE
+- docker tag "qemu/$NAME" "$TAG"
+- docker push "$TAG"
+  after_script:
+- docker logout
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 4ef76d1f54d..0bf4899df10 100644
--- a/.gitlab-ci.d/containers.yml
+++ b/.gitlab-ci.d/containers.yml
@@ -1,25 +1,5 @@
-.container_job_template:
-  image: docker:stable
-  stage: containers
-  services:
-- docker:dind
-  before_script:
-- export TAG="$CI_REGISTRY_IMAGE/qemu/$NAME:latest"
-- export COMMON_TAG="$CI_REGISTRY/qemu-project/qemu/$NAME:latest"
-- apk add python3
-- docker info
-- docker login $CI_REGISTRY -u "$CI_REGISTRY_USER" -p 
"$CI_REGISTRY_PASSWORD"
-  script:
-- echo "TAG:$TAG"
-- echo "COMMON_TAG:$COMMON_TAG"
-- docker pull "$TAG" || docker pull "$COMMON_TAG" || true
-- ./tests/docker/docker.py --engine docker build
-  -t "qemu/$NAME" -f "tests/docker/dockerfiles/$NAME.docker"
-  -r $CI_REGISTRY_IMAGE
-- docker tag "qemu/$NAME" "$TAG"
-- docker push "$TAG"
-  after_script:
-- docker logout
+include:
+  - local: '/.gitlab-ci.d/container-template.yml'
 
 amd64-alpine-container:
   extends: .container_job_template
-- 
2.26.3

[PATCH 11/15] gitlab-ci: Extract core container jobs to container-core.yml

[Philippe Mathieu-Daudé]

It is not possible to use the previously extracted templates
without this set of core containers. Extract them into a new
file (container-core.yml) to be able to build them without
having to build all the other containers by default.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/container-core.yml | 17 +
 .gitlab-ci.d/containers.yml | 16 +---
 2 files changed, 18 insertions(+), 15 deletions(-)
 create mode 100644 .gitlab-ci.d/container-core.yml

diff --git a/.gitlab-ci.d/container-core.yml b/.gitlab-ci.d/container-core.yml
new file mode 100644
index 000..e8dd1f476a2
--- /dev/null
+++ b/.gitlab-ci.d/container-core.yml
@@ -0,0 +1,17 @@
+include:
+  - local: '/.gitlab-ci.d/container-template.yml'
+
+amd64-centos8-container:
+  extends: .container_job_template
+  variables:
+NAME: centos8
+
+amd64-fedora-container:
+  extends: .container_job_template
+  variables:
+NAME: fedora
+
+amd64-debian10-container:
+  extends: .container_job_template
+  variables:
+NAME: debian10
diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 0bf4899df10..c371f8587e1 100644
--- a/.gitlab-ci.d/containers.yml
+++ b/.gitlab-ci.d/containers.yml
@@ -1,5 +1,6 @@
 include:
   - local: '/.gitlab-ci.d/container-template.yml'
+  - local: '/.gitlab-ci.d/container-core.yml'
 
 amd64-alpine-container:
   extends: .container_job_template
@@ -11,16 +12,6 @@ amd64-centos7-container:
   variables:
 NAME: centos7
 
-amd64-centos8-container:
-  extends: .container_job_template
-  variables:
-NAME: centos8
-
-amd64-debian10-container:
-  extends: .container_job_template
-  variables:
-NAME: debian10
-
 amd64-debian11-container:
   extends: .container_job_template
   variables:
@@ -190,11 +181,6 @@ cris-fedora-cross-container:
   variables:
 NAME: fedora-cris-cross
 
-amd64-fedora-container:
-  extends: .container_job_template
-  variables:
-NAME: fedora
-
 i386-fedora-cross-container:
   extends: .container_job_template
   variables:
-- 
2.26.3

[PATCH 05/15] gitlab-ci: Rename acceptance_test_job -> integration_test_job

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

The acceptance tests aren't accepting anything,
rename them as integration tests.

Reviewed-by: Wainer dos Santos Moschetta 
Reviewed-by: Willian Rampazzo 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 07e5e737685..bf4862a78de 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -48,7 +48,7 @@ include:
 # Avoid recompiling by hiding ninja with NINJA=":"
 - make NINJA=":" $MAKE_CHECK_ARGS
 
-.acceptance_test_job_template:
+.integration_test_job_template:
   cache:
 key: "${CI_JOB_NAME}-cache"
 paths:
@@ -111,7 +111,7 @@ acceptance-system-alpine:
   variables:
 IMAGE: alpine
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-system-ubuntu:
   extends: .native_build_job_template
@@ -145,7 +145,7 @@ acceptance-system-ubuntu:
   variables:
 IMAGE: ubuntu2004
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-system-debian:
   extends: .native_build_job_template
@@ -179,7 +179,7 @@ acceptance-system-debian:
   variables:
 IMAGE: debian-amd64
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-system-fedora:
   extends: .native_build_job_template
@@ -214,7 +214,7 @@ acceptance-system-fedora:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-system-centos:
   extends: .native_build_job_template
@@ -249,7 +249,7 @@ acceptance-system-centos:
   variables:
 IMAGE: centos8
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-system-opensuse:
   extends: .native_build_job_template
@@ -282,7 +282,7 @@ acceptance-system-opensuse:
   variables:
 IMAGE: opensuse-leap
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 
 build-disabled:
@@ -525,7 +525,7 @@ acceptance-cfi-aarch64:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-cfi-ppc64-s390x:
   extends: .native_build_job_template
@@ -562,7 +562,7 @@ acceptance-cfi-ppc64-s390x:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 build-cfi-x86_64:
   extends: .native_build_job_template
@@ -599,7 +599,7 @@ acceptance-cfi-x86_64:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  extends: .acceptance_test_job_template
+  extends: .integration_test_job_template
 
 tsan-build:
   extends: .native_build_job_template
-- 
2.26.3

[PATCH 04/15] gitlab-ci: Replace YAML anchors by extends (acceptance_test_job)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends

Reviewed-by: Wainer dos Santos Moschetta 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 11bda3abf33..07e5e737685 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -48,7 +48,7 @@ include:
 # Avoid recompiling by hiding ninja with NINJA=":"
 - make NINJA=":" $MAKE_CHECK_ARGS
 
-.acceptance_template: _definition
+.acceptance_test_job_template:
   cache:
 key: "${CI_JOB_NAME}-cache"
 paths:
@@ -111,7 +111,7 @@ acceptance-system-alpine:
   variables:
 IMAGE: alpine
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-system-ubuntu:
   extends: .native_build_job_template
@@ -145,7 +145,7 @@ acceptance-system-ubuntu:
   variables:
 IMAGE: ubuntu2004
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-system-debian:
   extends: .native_build_job_template
@@ -179,7 +179,7 @@ acceptance-system-debian:
   variables:
 IMAGE: debian-amd64
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-system-fedora:
   extends: .native_build_job_template
@@ -214,7 +214,7 @@ acceptance-system-fedora:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-system-centos:
   extends: .native_build_job_template
@@ -249,7 +249,7 @@ acceptance-system-centos:
   variables:
 IMAGE: centos8
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-system-opensuse:
   extends: .native_build_job_template
@@ -282,7 +282,7 @@ acceptance-system-opensuse:
   variables:
 IMAGE: opensuse-leap
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 
 build-disabled:
@@ -525,7 +525,7 @@ acceptance-cfi-aarch64:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-cfi-ppc64-s390x:
   extends: .native_build_job_template
@@ -562,7 +562,7 @@ acceptance-cfi-ppc64-s390x:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 build-cfi-x86_64:
   extends: .native_build_job_template
@@ -599,7 +599,7 @@ acceptance-cfi-x86_64:
   variables:
 IMAGE: fedora
 MAKE_CHECK_ARGS: check-acceptance
-  <<: *acceptance_definition
+  extends: .acceptance_test_job_template
 
 tsan-build:
   extends: .native_build_job_template
-- 
2.26.3

[PATCH 02/15] gitlab-ci: Replace YAML anchors by extends (native_build_job)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends

Reviewed-by: Wainer dos Santos Moschetta 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 64 +-
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 52d65d6c04f..98d73429405 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -13,7 +13,7 @@ include:
   - local: '/.gitlab-ci.d/containers.yml'
   - local: '/.gitlab-ci.d/crossbuilds.yml'
 
-.native_build_job_template: _build_job_definition
+.native_build_job_template:
   stage: build
   image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
   before_script:
@@ -79,7 +79,7 @@ include:
 - du -chs ${CI_PROJECT_DIR}/avocado-cache
 
 build-system-alpine:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 - job: amd64-alpine-container
   variables:
@@ -114,7 +114,7 @@ acceptance-system-alpine:
   <<: *acceptance_definition
 
 build-system-ubuntu:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-ubuntu2004-container
   variables:
@@ -148,7 +148,7 @@ acceptance-system-ubuntu:
   <<: *acceptance_definition
 
 build-system-debian:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-container
   variables:
@@ -182,7 +182,7 @@ acceptance-system-debian:
   <<: *acceptance_definition
 
 build-system-fedora:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-fedora-container
   variables:
@@ -217,7 +217,7 @@ acceptance-system-fedora:
   <<: *acceptance_definition
 
 build-system-centos:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-centos8-container
   variables:
@@ -252,7 +252,7 @@ acceptance-system-centos:
   <<: *acceptance_definition
 
 build-system-opensuse:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-opensuse-leap-container
   variables:
@@ -286,7 +286,7 @@ acceptance-system-opensuse:
 
 
 build-disabled:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-fedora-container
   variables:
@@ -373,7 +373,7 @@ build-disabled:
 # Also use a different coroutine implementation (which is only really of
 # interest to KVM users, i.e. with TCG disabled)
 build-tcg-disabled:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-centos8-container
   variables:
@@ -396,7 +396,7 @@ build-tcg-disabled:
 260 261 262 263 264 270 272 273 277 279
 
 build-user:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -405,7 +405,7 @@ build-user:
 MAKE_CHECK_ARGS: check-tcg
 
 build-user-static:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -415,7 +415,7 @@ build-user-static:
 
 # Only build the softmmu targets we have check-tcg tests for
 build-some-softmmu:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -428,7 +428,7 @@ build-some-softmmu:
 # we skip sparc64-linux-user until it has been fixed somewhat
 # we skip cris-linux-user as it doesn't use the common run loop
 build-user-plugins:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -438,7 +438,7 @@ build-user-plugins:
   timeout: 1h 30m
 
 build-user-centos7:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-centos7-container
   variables:
@@ -447,7 +447,7 @@ build-user-centos7:
 MAKE_CHECK_ARGS: check-tcg
 
 build-some-softmmu-plugins:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -457,7 +457,7 @@ build-some-softmmu-plugins:
 MAKE_CHECK_ARGS: check-tcg
 
 clang-system:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-fedora-container
   variables:
@@ -469,7 +469,7 @@ clang-system:
 MAKE_CHECK_ARGS: check-qtest check-tcg
 
 clang-user:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
 job: amd64-debian-user-cross-container
   variables:
@@ -491,7 +491,7 @@ clang-user:
 # Split in three sets of build/check/acceptance to limit the execution time of 
each
 # job
 build-cfi-aarch64:
-  <<: *native_build_job_definition
+  extends: .native_build_job_template
   needs:
   - job: amd64-fedora-container
   variables:
@@ 

[PATCH 09/15] gitlab-ci: Extract build stages to stages.yml

[Philippe Mathieu-Daudé]

Extract the build stages used by our job templates to a new file
(stages.yml) to be able to include it with the other templates,
without having to run all the jobs included in the default
.gitlab-ci.yml, which are mainly useful for mainstream CI.

Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/stages.yml |  8 
 .gitlab-ci.yml  | 10 +-
 2 files changed, 9 insertions(+), 9 deletions(-)
 create mode 100644 .gitlab-ci.d/stages.yml

diff --git a/.gitlab-ci.d/stages.yml b/.gitlab-ci.d/stages.yml
new file mode 100644
index 000..f50826018df
--- /dev/null
+++ b/.gitlab-ci.d/stages.yml
@@ -0,0 +1,8 @@
+# Currently we have two build stages after our containers are built:
+#  - build (for traditional build and test or first stage build)
+#  - test (for test stages, using build artefacts from a build stage)
+stages:
+  - containers
+  - containers-layer2
+  - build
+  - test
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ba35b3917e7..c367d42977c 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,13 +1,5 @@
-# Currently we have two build stages after our containers are built:
-#  - build (for traditional build and test or first stage build)
-#  - test (for test stages, using build artefacts from a build stage)
-stages:
-  - containers
-  - containers-layer2
-  - build
-  - test
-
 include:
+  - local: '/.gitlab-ci.d/stages.yml'
   - local: '/.gitlab-ci.d/edk2.yml'
   - local: '/.gitlab-ci.d/opensbi.yml'
   - local: '/.gitlab-ci.d/containers.yml'
-- 
2.26.3

[PATCH 03/15] gitlab-ci: Replace YAML anchors by extends (native_test_job)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends

Reviewed-by: Wainer dos Santos Moschetta 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.yml | 40 
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 98d73429405..11bda3abf33 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -37,7 +37,7 @@ include:
 make -j"$JOBS" $MAKE_CHECK_ARGS ;
   fi
 
-.native_test_job_template: _test_job_definition
+.native_test_job_template:
   stage: test
   image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
   script:
@@ -95,7 +95,7 @@ build-system-alpine:
   - build
 
 check-system-alpine:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-alpine
   artifacts: true
@@ -104,7 +104,7 @@ check-system-alpine:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-alpine:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-alpine
   artifacts: true
@@ -129,7 +129,7 @@ build-system-ubuntu:
   - build
 
 check-system-ubuntu:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-ubuntu
   artifacts: true
@@ -138,7 +138,7 @@ check-system-ubuntu:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-ubuntu:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-ubuntu
   artifacts: true
@@ -163,7 +163,7 @@ build-system-debian:
   - build
 
 check-system-debian:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-debian
   artifacts: true
@@ -172,7 +172,7 @@ check-system-debian:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-debian:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-debian
   artifacts: true
@@ -198,7 +198,7 @@ build-system-fedora:
   - build
 
 check-system-fedora:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-fedora
   artifacts: true
@@ -207,7 +207,7 @@ check-system-fedora:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-fedora:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-fedora
   artifacts: true
@@ -233,7 +233,7 @@ build-system-centos:
   - build
 
 check-system-centos:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-centos
   artifacts: true
@@ -242,7 +242,7 @@ check-system-centos:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-centos:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-centos
   artifacts: true
@@ -266,7 +266,7 @@ build-system-opensuse:
   - build
 
 check-system-opensuse:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-opensuse
   artifacts: true
@@ -275,7 +275,7 @@ check-system-opensuse:
 MAKE_CHECK_ARGS: check
 
 acceptance-system-opensuse:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-system-opensuse
   artifacts: true
@@ -509,7 +509,7 @@ build-cfi-aarch64:
   - build
 
 check-cfi-aarch64:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-aarch64
   artifacts: true
@@ -518,7 +518,7 @@ check-cfi-aarch64:
 MAKE_CHECK_ARGS: check
 
 acceptance-cfi-aarch64:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-aarch64
   artifacts: true
@@ -546,7 +546,7 @@ build-cfi-ppc64-s390x:
   - build
 
 check-cfi-ppc64-s390x:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-ppc64-s390x
   artifacts: true
@@ -555,7 +555,7 @@ check-cfi-ppc64-s390x:
 MAKE_CHECK_ARGS: check
 
 acceptance-cfi-ppc64-s390x:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-ppc64-s390x
   artifacts: true
@@ -583,7 +583,7 @@ build-cfi-x86_64:
   - build
 
 check-cfi-x86_64:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-x86_64
   artifacts: true
@@ -592,7 +592,7 @@ check-cfi-x86_64:
 MAKE_CHECK_ARGS: check
 
 acceptance-cfi-x86_64:
-  <<: *native_test_job_definition
+  extends: .native_test_job_template
   needs:
 - job: build-cfi-x86_64
   artifacts: true
@@ -630,7 +630,7 @@ build-deprecated:
 # We split the check-tcg step as test failures are expected but we still
 # want to catch the build breaking.
 check-deprecated:
-  <<: 

[PATCH 01/15] gitlab-ci: Replace YAML anchors by extends (container_job)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

'extends' is an alternative to using YAML anchors
and is a little more flexible and readable. See:
https://docs.gitlab.com/ee/ci/yaml/#extends

Reviewed-by: Wainer dos Santos Moschetta 
Reviewed-by: Thomas Huth 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/containers.yml | 76 ++---
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 33e4046e233..4ef76d1f54d 100644
--- a/.gitlab-ci.d/containers.yml
+++ b/.gitlab-ci.d/containers.yml
@@ -1,4 +1,4 @@
-.container_job_template: _job_definition
+.container_job_template:
   image: docker:stable
   stage: containers
   services:
@@ -22,230 +22,230 @@
 - docker logout
 
 amd64-alpine-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   variables:
 NAME: alpine
 
 amd64-centos7-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   variables:
 NAME: centos7
 
 amd64-centos8-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   variables:
 NAME: centos8
 
 amd64-debian10-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   variables:
 NAME: debian10
 
 amd64-debian11-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   variables:
 NAME: debian11
 
 alpha-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-alpha-cross
 
 amd64-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-amd64-cross
 
 amd64-debian-user-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-all-test-cross
 
 amd64-debian-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-amd64
 
 arm64-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-arm64-cross
 
 arm64-test-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian11-container']
   variables:
 NAME: debian-arm64-test-cross
 
 armel-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-armel-cross
 
 armhf-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-armhf-cross
 
 hppa-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-hppa-cross
 
 m68k-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-m68k-cross
 
 mips64-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-mips64-cross
 
 mips64el-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-mips64el-cross
 
 mips-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-mips-cross
 
 mipsel-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-mipsel-cross
 
 powerpc-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-powerpc-cross
 
 ppc64-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: ['amd64-debian10-container']
   variables:
 NAME: debian-ppc64-cross
 
 ppc64el-debian-cross-container:
-  <<: *container_job_definition
+  extends: .container_job_template
   stage: containers-layer2
   needs: 

[RFC PATCH 00/15] gitlab-ci: Allow forks to use different pipelines than mainstream

[Philippe Mathieu-Daudé]

TL;DR: Patch 13 is an experiment to dynamically generate pipelines.

Hi,

This series is an intent to allow git forks to use different set
of jobs than the ones used by the mainstream repository.

Currently, a fork gets the mainstream CI pipeline YAML configuration
and runs its set of jobs by default. Mainstream tests many cases
which might not be always useful to forks. Beside, one mainstream
pipeline might be a waste of ressources when forks provide their
own runners to their gitlab namespace, or use private instances.

This is not a new / unique problem to our community, and Gitlab
already figured it out. They describe this case as Upstream (our
project mainline) / Downstream (a fork).

The pipeline is divided in 2 steps. First the "upstream" part, which
does some evaluation, and depending on the result, triggers the
"downstream" part. The "upstream" is committed into mainline, and
dynamically generate the "downstream" pipeline. This allows forks
to easily rebase with mainstream, avoiding merge conflicts.

This might not be adapted to the QEMU use case, but I wanted to give
it a try.

Gitlab recommends to use job templates. To be able to re-use /
include templates, they can not use YAML anchors. All current jobs
has first to be converted to use the 'extends' keyworkd.
This is done by patches 1-5 (already reviewed).

Patches 6-12 extract various generic jobs (which can be reused by
forks) as template.

Patches 13-14 follow Gitlab guideline to generate dynamic pipelines

Patch 15 is an example of how a fork could use mainstream templates
to maintain his own set of jobs.

The PRO is forks can contribute to templates.

Regards,

Phil.

Philippe Mathieu-Daudé (15):
  gitlab-ci: Replace YAML anchors by extends (container_job)
  gitlab-ci: Replace YAML anchors by extends (native_build_job)
  gitlab-ci: Replace YAML anchors by extends (native_test_job)
  gitlab-ci: Replace YAML anchors by extends (acceptance_test_job)
  gitlab-ci: Rename acceptance_test_job -> integration_test_job
  gitlab-ci: Extract container job template to container-template.yml
  gitlab-ci: Extract crossbuild job templates to crossbuild-template.yml
  gitlab-ci: Extract DCO/style check jobs to checks.yml
  gitlab-ci: Extract build stages to stages.yml
  gitlab-ci: Extract all default build/test jobs to buildtest.yml
  gitlab-ci: Extract core container jobs to container-core.yml
  gitlab-ci: Move current job set to qemu-project.yml
  gitlab-ci: Switch to dynamically generated pipelines
  gitlab-ci: Allow forks to use different set of jobs
  gitlab-ci: Use my own set of jobs for CI pipeline

 .gitlab-ci.d/buildtest-template.yml  |  80 +++
 .gitlab-ci.d/buildtest.yml   | 744 +++
 .gitlab-ci.d/checks.yml  |  24 +
 .gitlab-ci.d/container-core.yml  |  17 +
 .gitlab-ci.d/container-template.yml  |  22 +
 .gitlab-ci.d/containers.yml  | 108 ++--
 .gitlab-ci.d/crossbuild-template.yml |  41 ++
 .gitlab-ci.d/crossbuilds.yml |  43 +-
 .gitlab-ci.d/philmd.yml  |  33 ++
 .gitlab-ci.d/qemu-project.yml|   8 +
 .gitlab-ci.d/stages.yml  |   8 +
 .gitlab-ci.yml   | 845 +--
 12 files changed, 1033 insertions(+), 940 deletions(-)
 create mode 100644 .gitlab-ci.d/buildtest-template.yml
 create mode 100644 .gitlab-ci.d/buildtest.yml
 create mode 100644 .gitlab-ci.d/checks.yml
 create mode 100644 .gitlab-ci.d/container-core.yml
 create mode 100644 .gitlab-ci.d/container-template.yml
 create mode 100644 .gitlab-ci.d/crossbuild-template.yml
 create mode 100644 .gitlab-ci.d/philmd.yml
 create mode 100644 .gitlab-ci.d/qemu-project.yml
 create mode 100644 .gitlab-ci.d/stages.yml

-- 
2.26.3

Re: [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds

[no-reply]

Patchew URL: https://patchew.org/QEMU/20210418225058.1257014-1-f4...@amsat.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210418225058.1257014-1-f4...@amsat.org
Subject: [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  patchew/20210418163134.1133100-1-f4...@amsat.org -> 
patchew/20210418163134.1133100-1-f4...@amsat.org
 * [new tag] patchew/20210418225058.1257014-1-f4...@amsat.org -> 
patchew/20210418225058.1257014-1-f4...@amsat.org
Switched to a new branch 'test'
686d87a gitlab-ci: Add KVM mips64el cross-build jobs
6892737 hw/mips: Restrict non-virtualized machines to TCG
d55d3a0 target/mips: Move TCG source files under tcg/ sub directory
b158932 target/mips: Move CP0 helpers to sysemu/cp0.c
36ed45f target/mips: Move exception management code to exception.c
8086a23 target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
411fe68 target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
3b48e47 target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
6b27ac4 target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
0ba1d79 target/mips: Move tlb_helper.c to tcg/sysemu/
c13ccc6 target/mips: Restrict mmu_init() to TCG
1f23674 target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
e99f746 target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
d738b53 target/mips: Move physical addressing code to sysemu/physaddr.c
53c0561 target/mips: Move sysemu specific files under sysemu/ subfolder
2db9661 target/mips: Move cpu_signal_handler definition around
922e532 target/mips: Add simple user-mode mips_cpu_tlb_fill()
b490e0c target/mips: Add simple user-mode mips_cpu_do_interrupt()
e50303f target/mips: Introduce tcg-internal.h for TCG specific declarations
3a5a7e4 meson: Introduce meson_user_arch source set for arch-specific user-mode
f7abf7e6 target/mips: Extract load/store helpers to ldst_helper.c
d32351e target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"
ed5faec target/mips: Turn printfpr() macro into a proper function
3dd608f target/mips: Restrict mips_cpu_dump_state() to cpu.c
4f5c9f4 target/mips: Optimize CPU/FPU regnames[] arrays
9bb0ffe target/mips: Make CPU/FPU regnames[] arrays global
d7b68ee target/mips: Move msa_reset() to new source file
c058012 target/mips: Move IEEE rounding mode array to new source file
f7acb82 target/mips: Simplify meson TCG rules

=== OUTPUT BEGIN ===
1/29 Checking commit f7acb82c17d8 (target/mips: Simplify meson TCG rules)
2/29 Checking commit c05801205ab1 (target/mips: Move IEEE rounding mode array 
to new source file)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 39 lines checked

Patch 2/29 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/29 Checking commit d7b68ee9d4f7 (target/mips: Move msa_reset() to new source 
file)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#37: 
new file mode 100644

total: 0 errors, 1 warnings, 70 lines checked

Patch 3/29 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/29 Checking commit 9bb0ffec8d1f (target/mips: Make CPU/FPU regnames[] arrays 
global)
5/29 Checking commit 4f5c9f47b7c1 (target/mips: Optimize CPU/FPU regnames[] 
arrays)
6/29 Checking commit 3dd608f1c8eb (target/mips: Restrict mips_cpu_dump_state() 
to cpu.c)
7/29 Checking commit ed5faec21b4c (target/mips: Turn printfpr() macro into a 
proper function)
8/29 Checking commit d32351edac7d (target/mips: Declare mips_cpu_set_error_pc() 
inlined in "internal.h")
9/29 Checking commit f7abf7e60011 (target/mips: Extract load/store helpers to 
ldst_helper.c)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
new file mode 100644

total: 0 errors, 1 warnings, 591 lines checked

Patch 9/29 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/29 Checking commit 3a5a7e410ac4 (meson: Introduce meson_user_arch source set 
for arch-specific 

[PATCH v2 29/29] gitlab-ci: Add KVM mips64el cross-build jobs

[Philippe Mathieu-Daudé]

Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).

Only build the mips64el target which is known to work
and has users.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 .gitlab-ci.d/crossbuilds.yml | 8 
 1 file changed, 8 insertions(+)

diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 2d95784ed51..e44e4b49a25 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -176,6 +176,14 @@ cross-s390x-kvm-only:
 IMAGE: debian-s390x-cross
 ACCEL_CONFIGURE_OPTS: --disable-tcg
 
+cross-mips64el-kvm-only:
+  extends: .cross_accel_build_job
+  needs:
+job: mips64el-debian-cross-container
+  variables:
+IMAGE: debian-mips64el-cross
+ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=mips64el-softmmu
+
 cross-win32-system:
   extends: .cross_system_build_job
   needs:
-- 
2.26.3

[PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory

[Philippe Mathieu-Daudé]

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h |  2 +-
 target/mips/internal.h   | 11 ---
 target/mips/tcg/tcg-internal.h   | 11 +++
 target/mips/{ => tcg}/msa_helper.h.inc   |  0
 target/mips/{ => tcg}/mips32r6.decode|  0
 target/mips/{ => tcg}/mips64r6.decode|  0
 target/mips/{ => tcg}/msa32.decode   |  0
 target/mips/{ => tcg}/msa64.decode   |  0
 target/mips/{ => tcg}/tx79.decode|  0
 target/mips/{ => tcg}/dsp_helper.c   |  0
 target/mips/{ => tcg}/exception.c|  0
 target/mips/{ => tcg}/fpu_helper.c   |  0
 target/mips/{ => tcg}/ldst_helper.c  |  0
 target/mips/{ => tcg}/lmmi_helper.c  |  0
 target/mips/{ => tcg}/msa_helper.c   |  0
 target/mips/{ => tcg}/msa_translate.c|  0
 target/mips/{ => tcg}/mxu_translate.c|  0
 target/mips/{ => tcg}/op_helper.c|  0
 target/mips/{ => tcg}/rel6_translate.c   |  0
 target/mips/{ => tcg}/translate.c|  0
 target/mips/{ => tcg}/translate_addr_const.c |  0
 target/mips/{ => tcg}/tx79_translate.c   |  0
 target/mips/{ => tcg}/txx9_translate.c   |  0
 target/mips/meson.build  | 31 
 target/mips/tcg/meson.build  | 29 ++
 25 files changed, 41 insertions(+), 43 deletions(-)
 rename target/mips/{ => tcg}/msa_helper.h.inc (100%)
 rename target/mips/{ => tcg}/mips32r6.decode (100%)
 rename target/mips/{ => tcg}/mips64r6.decode (100%)
 rename target/mips/{ => tcg}/msa32.decode (100%)
 rename target/mips/{ => tcg}/msa64.decode (100%)
 rename target/mips/{ => tcg}/tx79.decode (100%)
 rename target/mips/{ => tcg}/dsp_helper.c (100%)
 rename target/mips/{ => tcg}/exception.c (100%)
 rename target/mips/{ => tcg}/fpu_helper.c (100%)
 rename target/mips/{ => tcg}/ldst_helper.c (100%)
 rename target/mips/{ => tcg}/lmmi_helper.c (100%)
 rename target/mips/{ => tcg}/msa_helper.c (100%)
 rename target/mips/{ => tcg}/msa_translate.c (100%)
 rename target/mips/{ => tcg}/mxu_translate.c (100%)
 rename target/mips/{ => tcg}/op_helper.c (100%)
 rename target/mips/{ => tcg}/rel6_translate.c (100%)
 rename target/mips/{ => tcg}/translate.c (100%)
 rename target/mips/{ => tcg}/translate_addr_const.c (100%)
 rename target/mips/{ => tcg}/tx79_translate.c (100%)
 rename target/mips/{ => tcg}/txx9_translate.c (100%)

diff --git a/target/mips/helper.h b/target/mips/helper.h
index ba301ae160d..a9c6c7d1a31 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -608,4 +608,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
 #include "tcg/sysemu_helper.h.inc"
 #endif /* !CONFIG_USER_ONLY */
 
-#include "msa_helper.h.inc"
+#include "tcg/msa_helper.h.inc"
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 588e89cfcda..c3c8eb0a177 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -82,9 +82,6 @@ extern const int mips_defs_number;
 
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
-  MMUAccessType access_type,
-  int mmu_idx, uintptr_t retaddr);
 
 #define USEG_LIMIT  ((target_ulong)(int32_t)0x7FFFUL)
 #define KSEG0_BASE  ((target_ulong)(int32_t)0x8000UL)
@@ -151,12 +148,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
-vaddr addr, unsigned size,
-MMUAccessType access_type,
-int mmu_idx, MemTxAttrs attrs,
-MemTxResult response, uintptr_t retaddr);
-
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
@@ -209,8 +200,6 @@ static inline bool 
cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 return r;
 }
 
-void mips_tcg_init(void);
-
 void msa_reset(CPUMIPSState *env);
 
 /* cp0_timer.c */
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 70f0d5da436..ae9b35ff706 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -11,15 +11,21 @@
 #define MIPS_TCG_INTERNAL_H
 
 #include "tcg/tcg.h"
+#include "exec/memattrs.h"
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
+void mips_tcg_init(void);
+
 void 

[PATCH v2 26/29] target/mips: Move CP0 helpers to sysemu/cp0.c

[Philippe Mathieu-Daudé]

Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |   9 +--
 target/mips/cpu.c  | 103 ---
 target/mips/sysemu/cp0.c   | 123 +
 target/mips/sysemu/meson.build |   1 +
 4 files changed, 129 insertions(+), 107 deletions(-)
 create mode 100644 target/mips/sysemu/cp0.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8158078b08b..588e89cfcda 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -156,6 +156,11 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 MMUAccessType access_type,
 int mmu_idx, MemTxAttrs attrs,
 MemTxResult response, uintptr_t retaddr);
+
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
+
 extern const VMStateDescription vmstate_mips_cpu;
 
 #endif /* !CONFIG_USER_ONLY */
@@ -406,8 +411,4 @@ static inline void compute_hflags(CPUMIPSState *env)
 }
 }
 
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
-
 #endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 61d0dd69751..9dec912af98 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -42,109 +42,6 @@ const char regnames[32][4] = {
 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
 };
 
-#if !defined(CONFIG_USER_ONLY)
-
-/* Called for updates to CP0_Status.  */
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
-{
-int32_t tcstatus, *tcst;
-uint32_t v = cpu->CP0_Status;
-uint32_t cu, mx, asid, ksu;
-uint32_t mask = ((1 << CP0TCSt_TCU3)
-   | (1 << CP0TCSt_TCU2)
-   | (1 << CP0TCSt_TCU1)
-   | (1 << CP0TCSt_TCU0)
-   | (1 << CP0TCSt_TMX)
-   | (3 << CP0TCSt_TKSU)
-   | (0xff << CP0TCSt_TASID));
-
-cu = (v >> CP0St_CU0) & 0xf;
-mx = (v >> CP0St_MX) & 0x1;
-ksu = (v >> CP0St_KSU) & 0x3;
-asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-
-tcstatus = cu << CP0TCSt_TCU0;
-tcstatus |= mx << CP0TCSt_TMX;
-tcstatus |= ksu << CP0TCSt_TKSU;
-tcstatus |= asid;
-
-if (tc == cpu->current_tc) {
-tcst = >active_tc.CP0_TCStatus;
-} else {
-tcst = >tcs[tc].CP0_TCStatus;
-}
-
-*tcst &= ~mask;
-*tcst |= tcstatus;
-compute_hflags(cpu);
-}
-
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
-{
-uint32_t mask = env->CP0_Status_rw_bitmask;
-target_ulong old = env->CP0_Status;
-
-if (env->insn_flags & ISA_MIPS_R6) {
-bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-#if defined(TARGET_MIPS64)
-uint32_t ksux = (1 << CP0St_KX) & val;
-ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
-ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
-val = (val & ~(7 << CP0St_UX)) | ksux;
-#endif
-if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
-mask &= ~(3 << CP0St_KSU);
-}
-mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
-}
-
-env->CP0_Status = (old & ~mask) | (val & mask);
-#if defined(TARGET_MIPS64)
-if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
-/* Access to at least one of the 64-bit segments has been disabled */
-tlb_flush(env_cpu(env));
-}
-#endif
-if (ase_mt_available(env)) {
-sync_c0_status(env, env, env->current_tc);
-} else {
-compute_hflags(env);
-}
-}
-
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
-{
-uint32_t mask = 0x00C00300;
-uint32_t old = env->CP0_Cause;
-int i;
-
-if (env->insn_flags & ISA_MIPS_R2) {
-mask |= 1 << CP0Ca_DC;
-}
-if (env->insn_flags & ISA_MIPS_R6) {
-mask &= ~((1 << CP0Ca_WP) & val);
-}
-
-env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
-
-if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
-if (env->CP0_Cause & (1 << CP0Ca_DC)) {
-cpu_mips_stop_count(env);
-} else {
-cpu_mips_start_count(env);
-}
-}
-
-/* Set/reset software interrupts */
-for (i = 0 ; i < 2 ; i++) {
-if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
-cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
-}
-}
-}
-
-#endif /* !CONFIG_USER_ONLY */
-
 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
 {
 if (is_fpu64) {
diff --git 

[PATCH v2 28/29] hw/mips: Restrict non-virtualized machines to TCG

[Philippe Mathieu-Daudé]

Only the malta and loongson3-virt machines support KVM.

Restrict the other machines to TCG:

 - mipssim
 - magnum
 - pica61
 - fuloong2e
 - boston

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/mips/meson.build | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index 1195716dc73..dd0101ad4d8 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,12 +1,15 @@
 mips_ss = ss.source_set()
 mips_ss.add(files('bootloader.c', 'mips_int.c'))
 mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
-mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
 mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 
'loongson3_virt.c'))
-mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
 mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c'))
-mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
-mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
 mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'))
 
+if 'CONFIG_TCG' in config_all
+mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c'))
+mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c'))
+mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c'))
+mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt])
+endif
+
 hw_arch += {'mips': mips_ss}
-- 
2.26.3

[PATCH v2 25/29] target/mips: Move exception management code to exception.c

[Philippe Mathieu-Daudé]

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  13 ---
 target/mips/tcg/tcg-internal.h |  14 +++
 target/mips/cpu.c  | 113 --
 target/mips/exception.c| 169 +
 target/mips/op_helper.c|  37 
 target/mips/meson.build|   1 +
 6 files changed, 184 insertions(+), 163 deletions(-)
 create mode 100644 target/mips/exception.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 88020e22365..8158078b08b 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -80,7 +80,6 @@ extern const char fregnames[32][4];
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
@@ -411,16 +410,4 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, 
int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 
-const char *mips_exception_name(int32_t exception);
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t 
exception,
-  int error_code, uintptr_t pc);
-
-static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
-uint32_t exception,
-uintptr_t pc)
-{
-do_raise_exception_err(env, exception, 0, pc);
-}
-
 #endif
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index e507dd1630f..70f0d5da436 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -14,11 +14,25 @@
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
+void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
 
+const char *mips_exception_name(int32_t exception);
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t 
exception,
+  int error_code, uintptr_t pc);
+
+static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
+uint32_t exception,
+uintptr_t pc)
+{
+do_raise_exception_err(env, exception, 0, pc);
+}
+
 #if !defined(CONFIG_USER_ONLY)
 
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 949b8ef94ea..61d0dd69751 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -218,112 +218,12 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, 
int flags)
 }
 }
 
-static const char * const excp_names[EXCP_LAST + 1] = {
-[EXCP_RESET] = "reset",
-[EXCP_SRESET] = "soft reset",
-[EXCP_DSS] = "debug single step",
-[EXCP_DINT] = "debug interrupt",
-[EXCP_NMI] = "non-maskable interrupt",
-[EXCP_MCHECK] = "machine check",
-[EXCP_EXT_INTERRUPT] = "interrupt",
-[EXCP_DFWATCH] = "deferred watchpoint",
-[EXCP_DIB] = "debug instruction breakpoint",
-[EXCP_IWATCH] = "instruction fetch watchpoint",
-[EXCP_AdEL] = "address error load",
-[EXCP_AdES] = "address error store",
-[EXCP_TLBF] = "TLB refill",
-[EXCP_IBE] = "instruction bus error",
-[EXCP_DBp] = "debug breakpoint",
-[EXCP_SYSCALL] = "syscall",
-[EXCP_BREAK] = "break",
-[EXCP_CpU] = "coprocessor unusable",
-[EXCP_RI] = "reserved instruction",
-[EXCP_OVERFLOW] = "arithmetic overflow",
-[EXCP_TRAP] = "trap",
-[EXCP_FPE] = "floating point",
-[EXCP_DDBS] = "debug data break store",
-[EXCP_DWATCH] = "data watchpoint",
-[EXCP_LTLBL] = "TLB modify",
-[EXCP_TLBL] = "TLB load",
-[EXCP_TLBS] = "TLB store",
-[EXCP_DBE] = "data bus error",
-[EXCP_DDBL] = "debug data break load",
-[EXCP_THREAD] = "thread",
-[EXCP_MDMX] = "MDMX",
-[EXCP_C2E] = "precise coprocessor 2",
-[EXCP_CACHE] = "cache error",
-[EXCP_TLBXI] = "TLB execute-inhibit",
-[EXCP_TLBRI] = "TLB read-inhibit",
-[EXCP_MSADIS] = "MSA disabled",
-[EXCP_MSAFPE] = "MSA floating point",
-};
-
-const char *mips_exception_name(int32_t exception)
-{
-if (exception < 0 || exception > EXCP_LAST) {
-return "unknown";
-}
-return excp_names[exception];
-}
-
 void cpu_set_exception_base(int vp_index, target_ulong address)
 {
 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 

[PATCH v2 24/29] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c

[Philippe Mathieu-Daudé]

Move TLB management helpers to tcg/sysemu/tlb_helper.c.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h|  10 -
 target/mips/internal.h  |   7 -
 target/mips/tcg/sysemu_helper.h.inc |   9 +
 target/mips/op_helper.c | 333 
 target/mips/tcg/sysemu/tlb_helper.c | 331 +++
 5 files changed, 340 insertions(+), 350 deletions(-)

diff --git a/target/mips/helper.h b/target/mips/helper.h
index d49620f9282..ba301ae160d 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -202,16 +202,6 @@ FOP_PROTO(sune)
 FOP_PROTO(sne)
 #undef FOP_PROTO
 
-/* Special functions */
-#ifndef CONFIG_USER_ONLY
-DEF_HELPER_1(tlbwi, void, env)
-DEF_HELPER_1(tlbwr, void, env)
-DEF_HELPER_1(tlbp, void, env)
-DEF_HELPER_1(tlbr, void, env)
-DEF_HELPER_1(tlbinv, void, env)
-DEF_HELPER_1(tlbinvf, void, env)
-DEF_HELPER_3(ginvt, void, env, tl, i32)
-#endif /* !CONFIG_USER_ONLY */
 DEF_HELPER_1(rdhwr_cpunum, tl, env)
 DEF_HELPER_1(rdhwr_synci_step, tl, env)
 DEF_HELPER_1(rdhwr_cc, tl, env)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index a59e2f9007d..88020e22365 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -152,13 +152,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-void r4k_helper_tlbwi(CPUMIPSState *env);
-void r4k_helper_tlbwr(CPUMIPSState *env);
-void r4k_helper_tlbp(CPUMIPSState *env);
-void r4k_helper_tlbr(CPUMIPSState *env);
-void r4k_helper_tlbinv(CPUMIPSState *env);
-void r4k_helper_tlbinvf(CPUMIPSState *env);
-
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
 MMUAccessType access_type,
diff --git a/target/mips/tcg/sysemu_helper.h.inc 
b/target/mips/tcg/sysemu_helper.h.inc
index 1ccbf687237..4353a966f97 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -167,6 +167,15 @@ DEF_HELPER_1(evpe, tl, env)
 DEF_HELPER_1(dvp, tl, env)
 DEF_HELPER_1(evp, tl, env)
 
+/* TLB */
+DEF_HELPER_1(tlbwi, void, env)
+DEF_HELPER_1(tlbwr, void, env)
+DEF_HELPER_1(tlbp, void, env)
+DEF_HELPER_1(tlbr, void, env)
+DEF_HELPER_1(tlbinv, void, env)
+DEF_HELPER_1(tlbinvf, void, env)
+DEF_HELPER_3(ginvt, void, env, tl, i32)
+
 /* Special */
 DEF_HELPER_1(di, tl, env)
 DEF_HELPER_1(ei, tl, env)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 659c4d15668..c6373d1de3f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -325,339 +325,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong 
arg)
 return env->CP0_YQMask;
 }
 
-#ifndef CONFIG_USER_ONLY
-/* TLB management */
-static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
-{
-/* Discard entries from env->tlb[first] onwards.  */
-while (env->tlb->tlb_in_use > first) {
-r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
-}
-}
-
-static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
-{
-#if defined(TARGET_MIPS64)
-return extract64(entrylo, 6, 54);
-#else
-return extract64(entrylo, 6, 24) | /* PFN */
-   (extract64(entrylo, 32, 32) << 24); /* PFNX */
-#endif
-}
-
-static void r4k_fill_tlb(CPUMIPSState *env, int idx)
-{
-r4k_tlb_t *tlb;
-uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
-
-/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
-tlb = >tlb->mmu.r4k.tlb[idx];
-if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
-tlb->EHINV = 1;
-return;
-}
-tlb->EHINV = 0;
-tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
-#if defined(TARGET_MIPS64)
-tlb->VPN &= env->SEGMask;
-#endif
-tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-tlb->MMID = env->CP0_MemoryMapID;
-tlb->PageMask = env->CP0_PageMask;
-tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
-tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
-tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
-tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
-tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
-tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
-tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
-tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
-tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
-tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
-tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
-tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
-tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
-}
-
-void r4k_helper_tlbinv(CPUMIPSState *env)
-{
-bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
-uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
-uint32_t MMID = env->CP0_MemoryMapID;
-uint32_t tlb_mmid;
-r4k_tlb_t *tlb;
-int idx;
-
-MMID = mi ? MMID : (uint32_t) ASID;
-for (idx = 0; idx < env->tlb->nb_tlb; 

[PATCH v2 23/29] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

Move helper_cache() to tcg/sysemu/special_helper.c.

The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.

Signed-off-by: Philippe Mathieu-Daudé 
---
v2: Use STUB_HELPER() :) (rth)
---
 target/mips/helper.h|  2 --
 target/mips/tcg/sysemu_helper.h.inc |  1 +
 target/mips/op_helper.c | 35 -
 target/mips/tcg/sysemu/special_helper.c | 33 +++
 target/mips/translate.c | 13 +
 5 files changed, 47 insertions(+), 37 deletions(-)

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 4ee7916d8b2..d49620f9282 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -614,8 +614,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
 DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
 DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
 
-DEF_HELPER_3(cache, void, env, tl, i32)
-
 #ifndef CONFIG_USER_ONLY
 #include "tcg/sysemu_helper.h.inc"
 #endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/tcg/sysemu_helper.h.inc 
b/target/mips/tcg/sysemu_helper.h.inc
index 38e55cbf118..1ccbf687237 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -173,3 +173,4 @@ DEF_HELPER_1(ei, tl, env)
 DEF_HELPER_1(eret, void, env)
 DEF_HELPER_1(eretnc, void, env)
 DEF_HELPER_1(deret, void, env)
+DEF_HELPER_3(cache, void, env, tl, i32)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 3903545831f..659c4d15668 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -789,38 +789,3 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 }
 }
 #endif /* !CONFIG_USER_ONLY */
-
-void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
-{
-#ifndef CONFIG_USER_ONLY
-static const char *const type_name[] = {
-"Primary Instruction",
-"Primary Data or Unified Primary",
-"Tertiary",
-"Secondary"
-};
-uint32_t cache_type = extract32(op, 0, 2);
-uint32_t cache_operation = extract32(op, 2, 3);
-target_ulong index = addr & 0x1fff;
-
-switch (cache_operation) {
-case 0b010: /* Index Store Tag */
-memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
- MO_64, MEMTXATTRS_UNSPECIFIED);
-break;
-case 0b001: /* Index Load Tag */
-memory_region_dispatch_read(env->itc_tag, index, >CP0_TagLo,
-MO_64, MEMTXATTRS_UNSPECIFIED);
-break;
-case 0b000: /* Index Invalidate */
-case 0b100: /* Hit Invalidate */
-case 0b110: /* Hit Writeback */
-/* no-op */
-break;
-default:
-qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
-  cache_operation, type_name[cache_type]);
-break;
-}
-#endif
-}
diff --git a/target/mips/tcg/sysemu/special_helper.c 
b/target/mips/tcg/sysemu/special_helper.c
index 927a640d076..ffd5d0086b6 100644
--- a/target/mips/tcg/sysemu/special_helper.c
+++ b/target/mips/tcg/sysemu/special_helper.c
@@ -138,3 +138,36 @@ void helper_deret(CPUMIPSState *env)
 
 debug_post_eret(env);
 }
+
+void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
+{
+static const char *const type_name[] = {
+"Primary Instruction",
+"Primary Data or Unified Primary",
+"Tertiary",
+"Secondary"
+};
+uint32_t cache_type = extract32(op, 0, 2);
+uint32_t cache_operation = extract32(op, 2, 3);
+target_ulong index = addr & 0x1fff;
+
+switch (cache_operation) {
+case 0b010: /* Index Store Tag */
+memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
+ MO_64, MEMTXATTRS_UNSPECIFIED);
+break;
+case 0b001: /* Index Load Tag */
+memory_region_dispatch_read(env->itc_tag, index, >CP0_TagLo,
+MO_64, MEMTXATTRS_UNSPECIFIED);
+break;
+case 0b000: /* Index Invalidate */
+case 0b100: /* Hit Invalidate */
+case 0b110: /* Hit Writeback */
+/* no-op */
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n",
+  cache_operation, type_name[cache_type]);
+break;
+}
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8702f9220be..c2e60178d05 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -39,6 +39,19 @@
 #include "fpu_helper.h"
 #include "translate.h"
 
+/*
+ * Many sysemu-only helpers are not reachable for user-only.
+ * Define stub generators here, so that we need not either sprinkle
+ * ifdefs through the translator, nor provide the helper function.
+ */
+#define STUB_HELPER(NAME, ...) \
+static inline void 

[PATCH v2 18/29] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

[Philippe Mathieu-Daudé]

Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.

Move the opcode definitions to tcg/sysemu_helper.h.inc.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h  | 166 +
 target/mips/tcg/sysemu_helper.h.inc   | 168 ++
 target/mips/{ => tcg/sysemu}/cp0_helper.c |   0
 target/mips/{ => tcg/sysemu}/mips-semi.c  |   0
 target/mips/meson.build   |   5 -
 target/mips/tcg/meson.build   |   3 +
 target/mips/tcg/sysemu/meson.build|   4 +
 7 files changed, 179 insertions(+), 167 deletions(-)
 create mode 100644 target/mips/tcg/sysemu_helper.h.inc
 rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)
 rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)
 create mode 100644 target/mips/tcg/sysemu/meson.build

diff --git a/target/mips/helper.h b/target/mips/helper.h
index 709494445dd..bc308e5db13 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
 DEF_HELPER_2(raise_exception, noreturn, env, i32)
 DEF_HELPER_1(raise_exception_debug, noreturn, env)
 
-#ifndef CONFIG_USER_ONLY
-DEF_HELPER_1(do_semihosting, void, env)
-#endif
-
 #ifdef TARGET_MIPS64
 DEF_HELPER_4(sdl, void, env, tl, tl, int)
 DEF_HELPER_4(sdr, void, env, tl, tl, int)
@@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
 
 DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
 
-#ifndef CONFIG_USER_ONLY
-/* CP0 helpers */
-DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
-DEF_HELPER_1(mfc0_mvpconf0, tl, env)
-DEF_HELPER_1(mfc0_mvpconf1, tl, env)
-DEF_HELPER_1(mftc0_vpecontrol, tl, env)
-DEF_HELPER_1(mftc0_vpeconf0, tl, env)
-DEF_HELPER_1(mfc0_random, tl, env)
-DEF_HELPER_1(mfc0_tcstatus, tl, env)
-DEF_HELPER_1(mftc0_tcstatus, tl, env)
-DEF_HELPER_1(mfc0_tcbind, tl, env)
-DEF_HELPER_1(mftc0_tcbind, tl, env)
-DEF_HELPER_1(mfc0_tcrestart, tl, env)
-DEF_HELPER_1(mftc0_tcrestart, tl, env)
-DEF_HELPER_1(mfc0_tchalt, tl, env)
-DEF_HELPER_1(mftc0_tchalt, tl, env)
-DEF_HELPER_1(mfc0_tccontext, tl, env)
-DEF_HELPER_1(mftc0_tccontext, tl, env)
-DEF_HELPER_1(mfc0_tcschedule, tl, env)
-DEF_HELPER_1(mftc0_tcschedule, tl, env)
-DEF_HELPER_1(mfc0_tcschefback, tl, env)
-DEF_HELPER_1(mftc0_tcschefback, tl, env)
-DEF_HELPER_1(mfc0_count, tl, env)
-DEF_HELPER_1(mfc0_saar, tl, env)
-DEF_HELPER_1(mfhc0_saar, tl, env)
-DEF_HELPER_1(mftc0_entryhi, tl, env)
-DEF_HELPER_1(mftc0_status, tl, env)
-DEF_HELPER_1(mftc0_cause, tl, env)
-DEF_HELPER_1(mftc0_epc, tl, env)
-DEF_HELPER_1(mftc0_ebase, tl, env)
-DEF_HELPER_2(mftc0_configx, tl, env, tl)
-DEF_HELPER_1(mfc0_lladdr, tl, env)
-DEF_HELPER_1(mfc0_maar, tl, env)
-DEF_HELPER_1(mfhc0_maar, tl, env)
-DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
-DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
-DEF_HELPER_1(mfc0_debug, tl, env)
-DEF_HELPER_1(mftc0_debug, tl, env)
-#ifdef TARGET_MIPS64
-DEF_HELPER_1(dmfc0_tcrestart, tl, env)
-DEF_HELPER_1(dmfc0_tchalt, tl, env)
-DEF_HELPER_1(dmfc0_tccontext, tl, env)
-DEF_HELPER_1(dmfc0_tcschedule, tl, env)
-DEF_HELPER_1(dmfc0_tcschefback, tl, env)
-DEF_HELPER_1(dmfc0_lladdr, tl, env)
-DEF_HELPER_1(dmfc0_maar, tl, env)
-DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
-DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
-DEF_HELPER_1(dmfc0_saar, tl, env)
-#endif /* TARGET_MIPS64 */
-
-DEF_HELPER_2(mtc0_index, void, env, tl)
-DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mttc0_vpecontrol, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mttc0_vpeconf0, void, env, tl)
-DEF_HELPER_2(mtc0_vpeconf1, void, env, tl)
-DEF_HELPER_2(mtc0_yqmask, void, env, tl)
-DEF_HELPER_2(mtc0_vpeopt, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo0, void, env, tl)
-DEF_HELPER_2(mtc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mttc0_tcstatus, void, env, tl)
-DEF_HELPER_2(mtc0_tcbind, void, env, tl)
-DEF_HELPER_2(mttc0_tcbind, void, env, tl)
-DEF_HELPER_2(mtc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mttc0_tcrestart, void, env, tl)
-DEF_HELPER_2(mtc0_tchalt, void, env, tl)
-DEF_HELPER_2(mttc0_tchalt, void, env, tl)
-DEF_HELPER_2(mtc0_tccontext, void, env, tl)
-DEF_HELPER_2(mttc0_tccontext, void, env, tl)
-DEF_HELPER_2(mtc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mttc0_tcschedule, void, env, tl)
-DEF_HELPER_2(mtc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mttc0_tcschefback, void, env, tl)
-DEF_HELPER_2(mtc0_entrylo1, void, env, tl)
-DEF_HELPER_2(mtc0_context, void, env, tl)
-DEF_HELPER_2(mtc0_memorymapid, void, env, tl)
-DEF_HELPER_2(mtc0_pagemask, void, env, tl)
-DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
-DEF_HELPER_2(mtc0_segctl0, void, env, tl)
-DEF_HELPER_2(mtc0_segctl1, void, env, tl)
-DEF_HELPER_2(mtc0_segctl2, void, env, tl)
-DEF_HELPER_2(mtc0_pwfield, void, env, tl)
-DEF_HELPER_2(mtc0_pwsize, void, env, tl)
-DEF_HELPER_2(mtc0_wired, void, env, tl)

[PATCH v2 22/29] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/helper.h|   5 -
 target/mips/tcg/tcg-internal.h  |   3 +
 target/mips/tcg/sysemu_helper.h.inc |   7 ++
 target/mips/cpu.c   |  17 ---
 target/mips/op_helper.c | 100 -
 target/mips/tcg/sysemu/special_helper.c | 140 
 target/mips/tcg/sysemu/meson.build  |   1 +
 7 files changed, 151 insertions(+), 122 deletions(-)
 create mode 100644 target/mips/tcg/sysemu/special_helper.c

diff --git a/target/mips/helper.h b/target/mips/helper.h
index bc308e5db13..4ee7916d8b2 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -210,11 +210,6 @@ DEF_HELPER_1(tlbp, void, env)
 DEF_HELPER_1(tlbr, void, env)
 DEF_HELPER_1(tlbinv, void, env)
 DEF_HELPER_1(tlbinvf, void, env)
-DEF_HELPER_1(di, tl, env)
-DEF_HELPER_1(ei, tl, env)
-DEF_HELPER_1(eret, void, env)
-DEF_HELPER_1(eretnc, void, env)
-DEF_HELPER_1(deret, void, env)
 DEF_HELPER_3(ginvt, void, env, tl, i32)
 #endif /* !CONFIG_USER_ONLY */
 DEF_HELPER_1(rdhwr_cpunum, tl, env)
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 6615151cba2..e507dd1630f 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -10,6 +10,7 @@
 #ifndef MIPS_TCG_INTERNAL_H
 #define MIPS_TCG_INTERNAL_H
 
+#include "tcg/tcg.h"
 #include "hw/core/cpu.h"
 #include "cpu.h"
 
@@ -27,6 +28,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, 
int32_t *pagemask);
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
+bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
+
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type);
 void cpu_mips_tlb_flush(CPUMIPSState *env);
diff --git a/target/mips/tcg/sysemu_helper.h.inc 
b/target/mips/tcg/sysemu_helper.h.inc
index d136c4160a7..38e55cbf118 100644
--- a/target/mips/tcg/sysemu_helper.h.inc
+++ b/target/mips/tcg/sysemu_helper.h.inc
@@ -166,3 +166,10 @@ DEF_HELPER_1(evpe, tl, env)
 /* R6 Multi-threading */
 DEF_HELPER_1(dvp, tl, env)
 DEF_HELPER_1(evp, tl, env)
+
+/* Special */
+DEF_HELPER_1(di, tl, env)
+DEF_HELPER_1(ei, tl, env)
+DEF_HELPER_1(eret, void, env)
+DEF_HELPER_1(eretnc, void, env)
+DEF_HELPER_1(deret, void, env)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index acc149aa573..949b8ef94ea 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -342,23 +342,6 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
 env->hflags &= ~MIPS_HFLAG_BMASK;
 env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 }
-
-# ifndef CONFIG_USER_ONLY
-static bool mips_io_recompile_replay_branch(CPUState *cs,
-const TranslationBlock *tb)
-{
-MIPSCPU *cpu = MIPS_CPU(cs);
-CPUMIPSState *env = >env;
-
-if ((env->hflags & MIPS_HFLAG_BMASK) != 0
-&& env->active_tc.PC != tb->pc) {
-env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
-env->hflags &= ~MIPS_HFLAG_BMASK;
-return true;
-}
-return false;
-}
-# endif /* !CONFIG_USER_ONLY */
 #endif /* CONFIG_TCG */
 
 static bool mips_cpu_has_work(CPUState *cs)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 9b6f570c897..3903545831f 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -656,106 +656,6 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, 
uint32_t type)
 }
 }
 
-/* Specials */
-target_ulong helper_di(CPUMIPSState *env)
-{
-target_ulong t0 = env->CP0_Status;
-
-env->CP0_Status = t0 & ~(1 << CP0St_IE);
-return t0;
-}
-
-target_ulong helper_ei(CPUMIPSState *env)
-{
-target_ulong t0 = env->CP0_Status;
-
-env->CP0_Status = t0 | (1 << CP0St_IE);
-return t0;
-}
-
-static void debug_pre_eret(CPUMIPSState *env)
-{
-if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
-qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-env->active_tc.PC, env->CP0_EPC);
-if (env->CP0_Status & (1 << CP0St_ERL)) {
-qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
-}
-if (env->hflags & MIPS_HFLAG_DM) {
-qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
-}
-qemu_log("\n");
-}
-}
-
-static void debug_post_eret(CPUMIPSState *env)
-{
-if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
-qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
-env->active_tc.PC, env->CP0_EPC);
-if (env->CP0_Status & (1 << CP0St_ERL)) {
-qemu_log(" ErrorEPC " TARGET_FMT_lx, 

[PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder

[Philippe Mathieu-Daudé]

Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.
Update the KVM MIPS entry in MAINTAINERS.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: Update MAINTAINERS
---
 target/mips/{ => sysemu}/addr.c  |  0
 target/mips/{ => sysemu}/cp0_timer.c |  0
 target/mips/{ => sysemu}/machine.c   |  0
 MAINTAINERS  |  3 ++-
 target/mips/meson.build  | 12 ++--
 target/mips/sysemu/meson.build   |  5 +
 6 files changed, 13 insertions(+), 7 deletions(-)
 rename target/mips/{ => sysemu}/addr.c (100%)
 rename target/mips/{ => sysemu}/cp0_timer.c (100%)
 rename target/mips/{ => sysemu}/machine.c (100%)
 create mode 100644 target/mips/sysemu/meson.build

diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c
similarity index 100%
rename from target/mips/addr.c
rename to target/mips/sysemu/addr.c
diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c
similarity index 100%
rename from target/mips/cp0_timer.c
rename to target/mips/sysemu/cp0_timer.c
diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c
similarity index 100%
rename from target/mips/machine.c
rename to target/mips/sysemu/machine.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 36055f14c59..0620326544e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -404,7 +404,8 @@ F: target/arm/kvm.c
 MIPS KVM CPUs
 M: Huacai Chen 
 S: Odd Fixes
-F: target/mips/kvm.c
+F: target/mips/kvm*
+F: target/mips/sysemu/
 
 PPC KVM CPUs
 M: David Gibson 
diff --git a/target/mips/meson.build b/target/mips/meson.build
index ca3cc62cf7a..9a507937ece 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -7,6 +7,7 @@
 ]
 
 mips_user_ss = ss.source_set()
+mips_softmmu_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -14,6 +15,11 @@
   'gdbstub.c',
   'msa.c',
 ))
+
+if have_system
+  subdir('sysemu')
+endif
+
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
 mips_tcg_ss.add(files(
@@ -41,12 +47,6 @@
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
-mips_softmmu_ss = ss.source_set()
-mips_softmmu_ss.add(files(
-  'addr.c',
-  'cp0_timer.c',
-  'machine.c',
-))
 mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
   'cp0_helper.c',
   'mips-semi.c',
diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build
new file mode 100644
index 000..f2a1ff46081
--- /dev/null
+++ b/target/mips/sysemu/meson.build
@@ -0,0 +1,5 @@
+mips_softmmu_ss.add(files(
+  'addr.c',
+  'cp0_timer.c',
+  'machine.c',
+))
-- 
2.26.3

[PATCH v2 20/29] target/mips: Move tlb_helper.c to tcg/sysemu/

[Philippe Mathieu-Daudé]

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()

Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h| 5 -
 target/mips/tcg/tcg-internal.h| 5 +
 target/mips/{ => tcg/sysemu}/tlb_helper.c | 3 ---
 target/mips/meson.build   | 1 -
 target/mips/tcg/sysemu/meson.build| 1 +
 5 files changed, 6 insertions(+), 9 deletions(-)
 rename target/mips/{ => tcg/sysemu}/tlb_helper.c (99%)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 548fd73c7cc..df419760df0 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -164,16 +164,12 @@ void r4k_helper_tlbp(CPUMIPSState *env);
 void r4k_helper_tlbr(CPUMIPSState *env);
 void r4k_helper_tlbinv(CPUMIPSState *env);
 void r4k_helper_tlbinvf(CPUMIPSState *env);
-void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
 MMUAccessType access_type,
 int mmu_idx, MemTxAttrs attrs,
 MemTxResult response, uintptr_t retaddr);
-hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
-  MMUAccessType access_type);
-
 extern const VMStateDescription vmstate_mips_cpu;
 
 #endif /* !CONFIG_USER_ONLY */
@@ -424,7 +420,6 @@ static inline void compute_hflags(CPUMIPSState *env)
 }
 }
 
-void cpu_mips_tlb_flush(CPUMIPSState *env);
 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 70655bab45c..6615151cba2 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -24,8 +24,13 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
+  MMUAccessType access_type);
+void cpu_mips_tlb_flush(CPUMIPSState *env);
+
 #endif /* !CONFIG_USER_ONLY */
 
 #endif
diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
similarity index 99%
rename from target/mips/tlb_helper.c
rename to target/mips/tcg/sysemu/tlb_helper.c
index 2304fff4c42..82cfb0a9135 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -25,8 +25,6 @@
 #include "exec/log.h"
 #include "hw/mips/cpudevs.h"
 
-#if !defined(CONFIG_USER_ONLY)
-
 /* no MMU emulation */
 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, MMUAccessType access_type)
@@ -1071,4 +1069,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int 
use_extra)
 }
 }
 }
-#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/meson.build b/target/mips/meson.build
index a55af1cd6cf..ff5eb210dfd 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -31,7 +31,6 @@
   'msa_translate.c',
   'op_helper.c',
   'rel6_translate.c',
-  'tlb_helper.c',
   'translate.c',
   'translate_addr_const.c',
   'txx9_translate.c',
diff --git a/target/mips/tcg/sysemu/meson.build 
b/target/mips/tcg/sysemu/meson.build
index 5c3024e7760..73ab9571ba6 100644
--- a/target/mips/tcg/sysemu/meson.build
+++ b/target/mips/tcg/sysemu/meson.build
@@ -1,4 +1,5 @@
 mips_softmmu_ss.add(files(
   'cp0_helper.c',
   'mips-semi.c',
+  'tlb_helper.c',
 ))
-- 
2.26.3

[PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope

[Philippe Mathieu-Daudé]

The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  6 --
 target/mips/tcg/sysemu/tlb_helper.c | 13 +++--
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index df419760df0..a59e2f9007d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -152,12 +152,6 @@ struct CPUMIPSTLBContext {
 } mmu;
 };
 
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type);
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type);
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type);
 void r4k_helper_tlbwi(CPUMIPSState *env);
 void r4k_helper_tlbwr(CPUMIPSState *env);
 void r4k_helper_tlbp(CPUMIPSState *env);
diff --git a/target/mips/tcg/sysemu/tlb_helper.c 
b/target/mips/tcg/sysemu/tlb_helper.c
index 82cfb0a9135..cbb4ccf0dac 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -26,8 +26,8 @@
 #include "hw/mips/cpudevs.h"
 
 /* no MMU emulation */
-int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-   target_ulong address, MMUAccessType access_type)
+static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+  target_ulong address, MMUAccessType access_type)
 {
 *physical = address;
 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -35,8 +35,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, 
int *prot,
 }
 
 /* fixed mapping MMU emulation */
-int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-  target_ulong address, MMUAccessType access_type)
+static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type)
 {
 if (address <= (int32_t)0x7FFFUL) {
 if (!(env->CP0_Status & (1 << CP0St_ERL))) {
@@ -55,8 +56,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr 
*physical, int *prot,
 }
 
 /* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
-target_ulong address, MMUAccessType access_type)
+static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+   target_ulong address, MMUAccessType access_type)
 {
 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 uint32_t MMID = env->CP0_MemoryMapID;
-- 
2.26.3

[PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode

[Philippe Mathieu-Daudé]

Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'target_user_arch' set for user emulation.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: meson_user_arch -> target_user_arch in description (rth)

Cc: Paolo Bonzini 
---
 meson.build | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/meson.build b/meson.build
index d8bb1ec5aa9..1ffdc9e6c4e 100644
--- a/meson.build
+++ b/meson.build
@@ -1751,6 +1751,7 @@
 hw_arch = {}
 target_arch = {}
 target_softmmu_arch = {}
+target_user_arch = {}
 
 ###
 # Trace files #
@@ -2168,6 +2169,11 @@
 abi = config_target['TARGET_ABI_DIR']
 target_type='user'
 qemu_target_name = 'qemu-' + target_name
+if arch in target_user_arch
+  t = target_user_arch[arch].apply(config_target, strict: false)
+  arch_srcs += t.sources()
+  arch_deps += t.dependencies()
+endif
 if 'CONFIG_LINUX_USER' in config_target
   base_dir = 'linux-user'
   target_inc += include_directories('linux-user/host/' / 
config_host['ARCH'])
-- 
2.26.3

[PATCH v2 17/29] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 4 
 target/mips/tcg/tcg-internal.h | 9 +
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8789ffb319f..d7980ba9a94 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env);
 void r4k_helper_tlbinv(CPUMIPSState *env);
 void r4k_helper_tlbinvf(CPUMIPSState *env);
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
-uint32_t cpu_mips_get_random(CPUMIPSState *env);
 
 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 vaddr addr, unsigned size,
@@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
 /* helper.c */
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
 
-/* op_helper.c */
-void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
-
 static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
  target_ulong error_pc)
 {
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 24438667f47..b65580af211 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -11,10 +11,19 @@
 #define MIPS_TCG_INTERNAL_H
 
 #include "hw/core/cpu.h"
+#include "cpu.h"
 
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
 
+#if !defined(CONFIG_USER_ONLY)
+
+void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
+
+uint32_t cpu_mips_get_random(CPUMIPSState *env);
+
+#endif /* !CONFIG_USER_ONLY */
+
 #endif
-- 
2.26.3

[PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG

[Philippe Mathieu-Daudé]

mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 3 ---
 target/mips/tcg/tcg-internal.h | 2 ++
 target/mips/cpu.c  | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index d7980ba9a94..548fd73c7cc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t 
value);
 void cpu_mips_start_count(CPUMIPSState *env);
 void cpu_mips_stop_count(CPUMIPSState *env);
 
-/* helper.c */
-void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-
 static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
  target_ulong error_pc)
 {
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index b65580af211..70655bab45c 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
 #if !defined(CONFIG_USER_ONLY)
 
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
+
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index fcbf95c85b9..acc149aa573 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error 
**errp)
 
 env->exception_base = (int32_t)0xBFC0;
 
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 mmu_init(env, env->cpu_model);
 #endif
 fpu_init(env, env->cpu_model);
-- 
2.26.3

[PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c

[Philippe Mathieu-Daudé]

As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  1 -
 target/mips/cpu.c   | 77 +
 target/mips/translate.c | 77 -
 3 files changed, 77 insertions(+), 78 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 37f54a8b3fc..57072a941e7 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -79,7 +79,6 @@ extern const int mips_defs_number;
 
 void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ed9552ebeb7..232f701b836 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
+{
+int i;
+int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
+
+#define printfpr(fp)\
+do {\
+if (is_fpu64)   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu: %13g\n",\
+ (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
+ (double)(fp)->fd,  \
+ (double)(fp)->fs[FP_ENDIAN_IDX],   \
+ (double)(fp)->fs[!FP_ENDIAN_IDX]); \
+else {  \
+fpr_t tmp;  \
+tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
+tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
+qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
+ " fd:%13g fs:%13g psu:%13g\n", \
+ tmp.w[FP_ENDIAN_IDX], tmp.d,   \
+ (double)tmp.fd,\
+ (double)tmp.fs[FP_ENDIAN_IDX], \
+ (double)tmp.fs[!FP_ENDIAN_IDX]);   \
+}   \
+} while (0)
+
+
+qemu_fprintf(f,
+ "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
+ get_float_exception_flags(>active_fpu.fp_status));
+for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
+qemu_fprintf(f, "%3s: ", fregnames[i]);
+printfpr(>active_fpu.fpr[i]);
+}
+
+#undef printfpr
+}
+
+static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = >env;
+int i;
+
+qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
+ " LO=0x" TARGET_FMT_lx " ds %04x "
+ TARGET_FMT_lx " " TARGET_FMT_ld "\n",
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
+for (i = 0; i < 32; i++) {
+if ((i & 3) == 0) {
+qemu_fprintf(f, "GPR%02d:", i);
+}
+qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ regnames[i], env->active_tc.gpr[i]);
+if ((i & 3) == 3) {
+qemu_fprintf(f, "\n");
+}
+}
+
+qemu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC0x"
+ TARGET_FMT_lx "\n",
+ env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+qemu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
+ PRIx64 "\n",
+ env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
+qemu_fprintf(f, "Config2 0x%08x Config3 0x%08x\n",
+ env->CP0_Config2, env->CP0_Config3);
+qemu_fprintf(f, "Config4 0x%08x Config5 0x%08x\n",
+ env->CP0_Config4, env->CP0_Config5);
+if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
+fpu_dump_state(env, f, flags);
+}
+}
+
 static const char * const excp_names[EXCP_LAST + 1] = {
 

[PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c

[Philippe Mathieu-Daudé]

Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: phys.c -> physaddr.c in description (rth)
---
 target/mips/internal.h |  25 +++-
 target/mips/sysemu/physaddr.c  | 257 +
 target/mips/tlb_helper.c   | 254 
 target/mips/sysemu/meson.build |   1 +
 4 files changed, 282 insertions(+), 255 deletions(-)
 create mode 100644 target/mips/sysemu/physaddr.c

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 8deb0703a34..8789ffb319f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -81,15 +81,38 @@ extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
   MMUAccessType access_type,
   int mmu_idx, uintptr_t retaddr);
 
+#define USEG_LIMIT  ((target_ulong)(int32_t)0x7FFFUL)
+#define KSEG0_BASE  ((target_ulong)(int32_t)0x8000UL)
+#define KSEG1_BASE  ((target_ulong)(int32_t)0xA000UL)
+#define KSEG2_BASE  ((target_ulong)(int32_t)0xC000UL)
+#define KSEG3_BASE  ((target_ulong)(int32_t)0xE000UL)
+
+#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x4000UL)
+#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x6000UL)
+
 #if !defined(CONFIG_USER_ONLY)
 
+enum {
+TLBRET_XI = -6,
+TLBRET_RI = -5,
+TLBRET_DIRTY = -4,
+TLBRET_INVALID = -3,
+TLBRET_NOMATCH = -2,
+TLBRET_BADADDR = -1,
+TLBRET_MATCH = 0
+};
+
+int get_physical_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong real_address,
+ MMUAccessType access_type, int mmu_idx);
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
 typedef struct r4k_tlb_t r4k_tlb_t;
 struct r4k_tlb_t {
 target_ulong VPN;
diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c
new file mode 100644
index 000..1918633aa1c
--- /dev/null
+++ b/target/mips/sysemu/physaddr.c
@@ -0,0 +1,257 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "../internal.h"
+
+static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
+{
+/*
+ * Interpret access control mode and mmu_idx.
+ *   AdE? TLB?
+ *  AM  K S U E  K S U E
+ * UK0  0 1 1 0  0 - - 0
+ * MK1  0 1 1 0  1 - - !eu
+ * MSK   2  0 0 1 0  1 1 - !eu
+ * MUSK  3  0 0 0 0  1 1 1 !eu
+ * MUSUK 4  0 0 0 0  0 1 1 0
+ * USK   5  0 0 1 0  0 0 - 0
+ * - 6  - - - -  - - - -
+ * UUSK  7  0 0 0 0  0 0 0 0
+ */
+int32_t adetlb_mask;
+
+switch (mmu_idx) {
+case 3: /* ERL */
+/* If EU is set, always unmapped */
+if (eu) {
+return 0;
+}
+/* fall through */
+case MIPS_HFLAG_KM:
+/* Never AdE, TLB mapped if AM={1,2,3} */
+adetlb_mask = 0x7000;
+goto check_tlb;
+
+case MIPS_HFLAG_SM:
+/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
+adetlb_mask = 0xc038;
+goto check_ade;
+
+case MIPS_HFLAG_UM:
+/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
+adetlb_mask = 0xe418;
+/* fall through */
+check_ade:
+/* does this AM cause AdE in current execution mode */
+if ((adetlb_mask << am) < 0) {
+return TLBRET_BADADDR;
+}
+adetlb_mask <<= 8;
+/* fall through */
+check_tlb:
+/* is this AM mapped in current execution mode */
+return ((adetlb_mask << am) < 0);
+default:
+assert(0);
+return TLBRET_BADADDR;
+};
+}
+
+static int get_seg_physical_address(CPUMIPSState *env, hwaddr 

[PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around

[Philippe Mathieu-Daudé]

We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.

To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 284ef8d1e1a..8deb0703a34 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -151,14 +151,13 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr 
physaddr,
 MemTxResult response, uintptr_t retaddr);
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type);
-#endif
+
+extern const VMStateDescription vmstate_mips_cpu;
+
+#endif /* !CONFIG_USER_ONLY */
 
 #define cpu_signal_handler cpu_mips_signal_handler
 
-#ifndef CONFIG_USER_ONLY
-extern const VMStateDescription vmstate_mips_cpu;
-#endif
-
 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 {
 return (env->CP0_Status & (1 << CP0St_IE)) &&
-- 
2.26.3

[PATCH v2 03/29] target/mips: Move msa_reset() to new source file

[Philippe Mathieu-Daudé]

mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.

Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/msa.c| 60 
 target/mips/msa_helper.c | 36 
 target/mips/meson.build  |  1 +
 3 files changed, 61 insertions(+), 36 deletions(-)
 create mode 100644 target/mips/msa.c

diff --git a/target/mips/msa.c b/target/mips/msa.c
new file mode 100644
index 000..61f1a9a5936
--- /dev/null
+++ b/target/mips/msa.c
@@ -0,0 +1,60 @@
+/*
+ * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "internal.h"
+#include "fpu/softfloat.h"
+#include "fpu_helper.h"
+
+void msa_reset(CPUMIPSState *env)
+{
+if (!ase_msa_available(env)) {
+return;
+}
+
+#ifdef CONFIG_USER_ONLY
+/* MSA access enabled */
+env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+/*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+env->active_tc.msacsr = 0;
+
+restore_msa_fp_status(env);
+
+/* tininess detected after rounding.*/
+set_float_detect_tininess(float_tininess_after_rounding,
+  >active_tc.msa_fp_status);
+
+/* clear float_status exception flags */
+set_float_exception_flags(0, >active_tc.msa_fp_status);
+
+/* clear float_status nan mode */
+set_default_nan_mode(0, >active_tc.msa_fp_status);
+
+/* set proper signanling bit meaning ("1" means "quiet") */
+set_snan_bit_is_one(0, >active_tc.msa_fp_status);
+}
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 4caefe29ad7..04af54f66d1 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
 #endif
 }
-
-void msa_reset(CPUMIPSState *env)
-{
-if (!ase_msa_available(env)) {
-return;
-}
-
-#ifdef CONFIG_USER_ONLY
-/* MSA access enabled */
-env->CP0_Config5 |= 1 << CP0C5_MSAEn;
-env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
-/*
- * MSA CSR:
- * - non-signaling floating point exception mode off (NX bit is 0)
- * - Cause, Enables, and Flags are all 0
- * - round to nearest / ties to even (RM bits are 0)
- */
-env->active_tc.msacsr = 0;
-
-restore_msa_fp_status(env);
-
-/* tininess detected after rounding.*/
-set_float_detect_tininess(float_tininess_after_rounding,
-  >active_tc.msa_fp_status);
-
-/* clear float_status exception flags */
-set_float_exception_flags(0, >active_tc.msa_fp_status);
-
-/* clear float_status nan mode */
-set_default_nan_mode(0, >active_tc.msa_fp_status);
-
-/* set proper signanling bit meaning ("1" means "quiet") */
-set_snan_bit_is_one(0, >active_tc.msa_fp_status);
-}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 5fcb211ca9a..daf5f1d55bc 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -11,6 +11,7 @@
   'cpu.c',
   'fpu.c',
   'gdbstub.c',
+  'msa.c',
 ))
 mips_tcg_ss = ss.source_set()
 mips_tcg_ss.add(gen)
-- 
2.26.3

[PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill()

[Philippe Mathieu-Daudé]

tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().

Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.

This will allow us to restrict tlb_helper.c to sysemu.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/user/tlb_helper.c | 36 +++
 target/mips/tlb_helper.c  | 10 -
 2 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/target/mips/tcg/user/tlb_helper.c 
b/target/mips/tcg/user/tlb_helper.c
index 453b9e9b930..b835144b820 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -22,6 +22,42 @@
 #include "exec/exec-all.h"
 #include "internal.h"
 
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
+MMUAccessType access_type)
+{
+CPUState *cs = env_cpu(env);
+
+env->error_code = 0;
+if (access_type == MMU_INST_FETCH) {
+env->error_code |= EXCP_INST_NOTAVAIL;
+}
+
+/* Reference to kernel address from user mode or supervisor mode */
+/* Reference to supervisor address from user mode */
+if (access_type == MMU_DATA_STORE) {
+cs->exception_index = EXCP_AdES;
+} else {
+cs->exception_index = EXCP_AdEL;
+}
+
+/* Raise exception */
+if (!(env->hflags & MIPS_HFLAG_DM)) {
+env->CP0_BadVAddr = address;
+}
+}
+
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr)
+{
+MIPSCPU *cpu = MIPS_CPU(cs);
+CPUMIPSState *env = >env;
+
+/* data access */
+raise_mmu_exception(env, address, access_type);
+do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
+}
+
 void mips_cpu_do_interrupt(CPUState *cs)
 {
 cs->exception_index = EXCP_NONE;
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 46e9555c9ab..bb4b503ff72 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
 env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 MMUAccessType access_type, int tlb_error)
 {
@@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, 
target_ulong address,
 env->error_code = error_code;
 }
 
-#if !defined(CONFIG_USER_ONLY)
-
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
@@ -833,7 +829,6 @@ refill:
 return true;
 }
 #endif
-#endif /* !CONFIG_USER_ONLY */
 
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = >env;
-#if !defined(CONFIG_USER_ONLY)
 hwaddr physical;
 int prot;
-#endif
 int ret = TLBRET_BADADDR;
 
 /* data access */
-#if !defined(CONFIG_USER_ONLY)
 /* XXX: put correct access by using cpu_restore_state() correctly */
 ret = get_physical_address(env, , , address,
access_type, mmu_idx);
@@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 if (probe) {
 return false;
 }
-#endif
 
 raise_mmu_exception(env, address, access_type, ret);
 do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
 }
 
-#ifndef CONFIG_USER_ONLY
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
   MMUAccessType access_type)
 {
-- 
2.26.3

[PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c

[Philippe Mathieu-Daudé]

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/ldst_helper.c | 304 ++
 target/mips/op_helper.c   | 274 --
 target/mips/meson.build   |   1 +
 3 files changed, 305 insertions(+), 274 deletions(-)
 create mode 100644 target/mips/ldst_helper.c

diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c
new file mode 100644
index 000..3fbcc3509ab
--- /dev/null
+++ b/target/mips/ldst_helper.c
@@ -0,0 +1,304 @@
+/*
+ *  MIPS emulation load/store helpers for QEMU.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/memop.h"
+#include "internal.h"
+
+#ifndef CONFIG_USER_ONLY
+
+static inline hwaddr do_translate_address(CPUMIPSState *env,
+  target_ulong address,
+  MMUAccessType access_type,
+  uintptr_t retaddr)
+{
+hwaddr paddr;
+CPUState *cs = env_cpu(env);
+
+paddr = cpu_mips_translate_address(env, address, access_type);
+
+if (paddr == -1LL) {
+cpu_loop_exit_restore(cs, retaddr);
+} else {
+return paddr;
+}
+}
+
+#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
+{ \
+if (arg & almask) {   \
+if (!(env->hflags & MIPS_HFLAG_DM)) { \
+env->CP0_BadVAddr = arg;  \
+} \
+do_raise_exception(env, EXCP_AdEL, GETPC());  \
+} \
+env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
+env->lladdr = arg;\
+env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());  \
+return env->llval;\
+}
+HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
+#ifdef TARGET_MIPS64
+HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
+#endif
+#undef HELPER_LD_ATOMIC
+
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#define GET_LMASK(v) ((v) & 3)
+#define GET_OFFSET(addr, offset) (addr + (offset))
+#else
+#define GET_LMASK(v) (((v) & 3) ^ 3)
+#define GET_OFFSET(addr, offset) (addr - (offset))
+#endif
+
+void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
+
+if (GET_LMASK(arg2) <= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) <= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 0) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
+  mem_idx, GETPC());
+}
+}
+
+void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+int mem_idx)
+{
+cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+
+if (GET_LMASK(arg2) >= 1) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) >= 2) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+  mem_idx, GETPC());
+}
+
+if (GET_LMASK(arg2) == 3) {
+cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+  mem_idx, GETPC());
+}
+}
+
+#if defined(TARGET_MIPS64)
+/*
+ * "half" load and stores.  We must do the memory access inline,
+ * or fault 

[PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations

[Philippe Mathieu-Daudé]

We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h |  7 +++
 target/mips/tcg/tcg-internal.h | 20 
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 target/mips/tcg/tcg-internal.h

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 81671d567d0..284ef8d1e1a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -9,6 +9,9 @@
 #define MIPS_INTERNAL_H
 
 #include "exec/memattrs.h"
+#ifdef CONFIG_TCG
+#include "tcg/tcg-internal.h"
+#endif
 
 /*
  * MMU types, the first four entries have the same layout as the
@@ -77,7 +80,6 @@ extern const char fregnames[32][4];
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
-void mips_cpu_do_interrupt(CPUState *cpu);
 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -212,9 +214,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
 
 /* helper.c */
 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-   MMUAccessType access_type, int mmu_idx,
-   bool probe, uintptr_t retaddr);
 
 /* op_helper.c */
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
new file mode 100644
index 000..24438667f47
--- /dev/null
+++ b/target/mips/tcg/tcg-internal.h
@@ -0,0 +1,20 @@
+/*
+ * MIPS internal definitions and helpers (TCG accelerator)
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef MIPS_TCG_INTERNAL_H
+#define MIPS_TCG_INTERNAL_H
+
+#include "hw/core/cpu.h"
+
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+   MMUAccessType access_type, int mmu_idx,
+   bool probe, uintptr_t retaddr);
+
+#endif
-- 
2.26.3

[PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file

[Philippe Mathieu-Daudé]

restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.

kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.

Except this tiny array, the rest of fpu_helper.c is only useful
for the TCG accelerator.

To be able to restrict fpu_helper.c to TCG, we need to move the
ieee_rm[] array to a new source file.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/fpu.c| 18 ++
 target/mips/fpu_helper.c |  8 
 target/mips/meson.build  |  1 +
 3 files changed, 19 insertions(+), 8 deletions(-)
 create mode 100644 target/mips/fpu.c

diff --git a/target/mips/fpu.c b/target/mips/fpu.c
new file mode 100644
index 000..39a2f7fd22e
--- /dev/null
+++ b/target/mips/fpu.c
@@ -0,0 +1,18 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ *  Copyright (C) 2004-2005  Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "fpu/softfloat-helpers.h"
+#include "fpu_helper.h"
+
+/* convert MIPS rounding mode in FCR31 to IEEE library */
+const FloatRoundMode ieee_rm[4] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down
+};
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 6dd853259e2..8ce56ed7c81 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -38,14 +38,6 @@
 #define FP_TO_INT32_OVERFLOW 0x7fff
 #define FP_TO_INT64_OVERFLOW 0x7fffULL
 
-/* convert MIPS rounding mode in FCR31 to IEEE library */
-const FloatRoundMode ieee_rm[4] = {
-float_round_nearest_even,
-float_round_to_zero,
-float_round_up,
-float_round_down
-};
-
 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
 {
 target_ulong arg1 = 0;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3733d1200f7..5fcb211ca9a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -9,6 +9,7 @@
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
+  'fpu.c',
   'gdbstub.c',
 ))
 mips_tcg_ss = ss.source_set()
-- 
2.26.3

[PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt()

[Philippe Mathieu-Daudé]

The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.

Add this simple implementation to tcg/user/tlb_helper.c, and
the corresponding Meson machinery to build this file when user
emulation is configured.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
v2: Renamed helper.c -> tlb_helper.c (rth)
---
 target/mips/tcg/user/tlb_helper.c | 28 
 target/mips/tlb_helper.c  |  5 -
 target/mips/meson.build   |  5 +
 target/mips/tcg/meson.build   |  3 +++
 target/mips/tcg/user/meson.build  |  3 +++
 5 files changed, 39 insertions(+), 5 deletions(-)
 create mode 100644 target/mips/tcg/user/tlb_helper.c
 create mode 100644 target/mips/tcg/meson.build
 create mode 100644 target/mips/tcg/user/meson.build

diff --git a/target/mips/tcg/user/tlb_helper.c 
b/target/mips/tcg/user/tlb_helper.c
new file mode 100644
index 000..453b9e9b930
--- /dev/null
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -0,0 +1,28 @@
+/*
+ * MIPS TLB (Translation lookaside buffer) helpers.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "internal.h"
+
+void mips_cpu_do_interrupt(CPUState *cs)
+{
+cs->exception_index = EXCP_NONE;
+}
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 8d3ea497803..46e9555c9ab 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -964,11 +964,8 @@ static inline void set_badinstr_registers(CPUMIPSState 
*env)
 }
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 void mips_cpu_do_interrupt(CPUState *cs)
 {
-#if !defined(CONFIG_USER_ONLY)
 MIPSCPU *cpu = MIPS_CPU(cs);
 CPUMIPSState *env = >env;
 bool update_badinstr = 0;
@@ -1271,11 +1268,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
  env->CP0_DEPC);
 }
-#endif
 cs->exception_index = EXCP_NONE;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
 {
 CPUState *cs = env_cpu(env);
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 15c2f835c68..ca3cc62cf7a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -6,6 +6,7 @@
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
 ]
 
+mips_user_ss = ss.source_set()
 mips_ss = ss.source_set()
 mips_ss.add(files(
   'cpu.c',
@@ -34,6 +35,9 @@
 ), if_false: files(
   'mxu_translate.c',
 ))
+if 'CONFIG_TCG' in config_all
+  subdir('tcg')
+endif
 
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
@@ -52,3 +56,4 @@
 
 target_arch += {'mips': mips_ss}
 target_softmmu_arch += {'mips': mips_softmmu_ss}
+target_user_arch += {'mips': mips_user_ss}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
new file mode 100644
index 000..b74fa04303e
--- /dev/null
+++ b/target/mips/tcg/meson.build
@@ -0,0 +1,3 @@
+if have_user
+  subdir('user')
+endif
diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build
new file mode 100644
index 000..79badcd3217
--- /dev/null
+++ b/target/mips/tcg/user/meson.build
@@ -0,0 +1,3 @@
+mips_user_ss.add(files(
+  'tlb_helper.c',
+))
-- 
2.26.3

[PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"

[Philippe Mathieu-Daudé]

Rename set_pc() as mips_cpu_set_error_pc(), declare it inlined
and use it in cpu.c and op_helper.c.

Reported-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  | 11 +++
 target/mips/cpu.c   |  8 +---
 target/mips/op_helper.c | 16 +++-
 3 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 57072a941e7..81671d567d0 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -219,6 +219,17 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 /* op_helper.c */
 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 
+static inline void mips_cpu_set_error_pc(CPUMIPSState *env,
+ target_ulong error_pc)
+{
+env->active_tc.PC = error_pc & ~(target_ulong)1;
+if (error_pc & 1) {
+env->hflags |= MIPS_HFLAG_M16;
+} else {
+env->hflags &= ~(MIPS_HFLAG_M16);
+}
+}
+
 static inline void restore_pamask(CPUMIPSState *env)
 {
 if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 90ae232c8b8..fcbf95c85b9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -327,14 +327,8 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState 
*env,
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
 MIPSCPU *cpu = MIPS_CPU(cs);
-CPUMIPSState *env = >env;
 
-env->active_tc.PC = value & ~(target_ulong)1;
-if (value & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
+mips_cpu_set_error_pc(>env, value);
 }
 
 #ifdef CONFIG_TCG
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index b80e8f75401..f7da8c83aee 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -993,24 +993,14 @@ static void debug_post_eret(CPUMIPSState *env)
 }
 }
 
-static void set_pc(CPUMIPSState *env, target_ulong error_pc)
-{
-env->active_tc.PC = error_pc & ~(target_ulong)1;
-if (error_pc & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
-}
-
 static inline void exception_return(CPUMIPSState *env)
 {
 debug_pre_eret(env);
 if (env->CP0_Status & (1 << CP0St_ERL)) {
-set_pc(env, env->CP0_ErrorEPC);
+mips_cpu_set_error_pc(env, env->CP0_ErrorEPC);
 env->CP0_Status &= ~(1 << CP0St_ERL);
 } else {
-set_pc(env, env->CP0_EPC);
+mips_cpu_set_error_pc(env, env->CP0_EPC);
 env->CP0_Status &= ~(1 << CP0St_EXL);
 }
 compute_hflags(env);
@@ -1036,7 +1026,7 @@ void helper_deret(CPUMIPSState *env)
 env->hflags &= ~MIPS_HFLAG_DM;
 compute_hflags(env);
 
-set_pc(env, env->CP0_DEPC);
+mips_cpu_set_error_pc(env, env->CP0_DEPC);
 
 debug_post_eret(env);
 }
-- 
2.26.3

[PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global

[Philippe Mathieu-Daudé]

The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.

To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by declaring them in "internal.h".

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h  |  3 +++
 target/mips/cpu.c   |  7 +++
 target/mips/fpu.c   |  7 +++
 target/mips/translate.c | 14 --
 4 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 99264b8bf6a..a8644f754a6 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -71,6 +71,9 @@ struct mips_def_t {
 int32_t SAARP;
 };
 
+extern const char * const regnames[32];
+extern const char * const fregnames[32];
+
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index dce1e166bde..f354d18aec4 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,6 +35,13 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
+const char * const regnames[32] = {
+"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+};
+
 #if !defined(CONFIG_USER_ONLY)
 
 /* Called for updates to CP0_Status.  */
diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 39a2f7fd22e..1447dba3fa3 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -16,3 +16,10 @@ const FloatRoundMode ieee_rm[4] = {
 float_round_up,
 float_round_down
 };
+
+const char * const fregnames[32] = {
+"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71fa5ec1973..f99d4d4016d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1267,13 +1267,6 @@ TCGv_i64 fpu_f64[32];
 #define DISAS_STOP   DISAS_TARGET_0
 #define DISAS_EXIT   DISAS_TARGET_1
 
-static const char * const regnames[] = {
-"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
-"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
-"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
-};
-
 static const char * const regnames_HI[] = {
 "HI0", "HI1", "HI2", "HI3",
 };
@@ -1282,13 +1275,6 @@ static const char * const regnames_LO[] = {
 "LO0", "LO1", "LO2", "LO3",
 };
 
-static const char * const fregnames[] = {
-"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
-"f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
-"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
-};
-
 /* General purpose registers moves. */
 void gen_load_gpr(TCGv t, int reg)
 {
-- 
2.26.3

[PATCH v2 01/29] target/mips: Simplify meson TCG rules

[Philippe Mathieu-Daudé]

We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.

Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/meson.build | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3b131c4a7f6..3733d1200f7 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -26,10 +26,9 @@
   'translate_addr_const.c',
   'txx9_translate.c',
 ))
-mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
+mips_tcg_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
-))
-mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
+), if_false: files(
   'mxu_translate.c',
 ))
 
-- 
2.26.3

[PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function

[Philippe Mathieu-Daudé]

Turn printfpr() macro into a proper function: fpu_dump_fpr().

Suggested-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/cpu.c | 48 ++-
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 232f701b836..90ae232c8b8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -145,44 +145,40 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong 
val)
 
 #endif /* !CONFIG_USER_ONLY */
 
+static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64)
+{
+if (is_fpu64) {
+qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n",
+ fpr->w[FP_ENDIAN_IDX], fpr->d,
+ (double)fpr->fd,
+ (double)fpr->fs[FP_ENDIAN_IDX],
+ (double)fpr->fs[!FP_ENDIAN_IDX]);
+} else {
+fpr_t tmp;
+
+tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX];
+tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX];
+qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n",
+ tmp.w[FP_ENDIAN_IDX], tmp.d,
+ (double)tmp.fd,
+ (double)tmp.fs[FP_ENDIAN_IDX],
+ (double)tmp.fs[!FP_ENDIAN_IDX]);
+}
+}
+
 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
 {
 int i;
 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
 
-#define printfpr(fp)\
-do {\
-if (is_fpu64)   \
-qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
- " fd:%13g fs:%13g psu: %13g\n",\
- (fp)->w[FP_ENDIAN_IDX], (fp)->d,   \
- (double)(fp)->fd,  \
- (double)(fp)->fs[FP_ENDIAN_IDX],   \
- (double)(fp)->fs[!FP_ENDIAN_IDX]); \
-else {  \
-fpr_t tmp;  \
-tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX];  \
-tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX];   \
-qemu_fprintf(f, "w:%08x d:%016" PRIx64  \
- " fd:%13g fs:%13g psu:%13g\n", \
- tmp.w[FP_ENDIAN_IDX], tmp.d,   \
- (double)tmp.fd,\
- (double)tmp.fs[FP_ENDIAN_IDX], \
- (double)tmp.fs[!FP_ENDIAN_IDX]);   \
-}   \
-} while (0)
-
-
 qemu_fprintf(f,
  "CP1 FCR0 0x%08x  FCR31 0x%08x  SR.FR %d  fp_status 0x%02x\n",
  env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
  get_float_exception_flags(>active_fpu.fp_status));
 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
 qemu_fprintf(f, "%3s: ", fregnames[i]);
-printfpr(>active_fpu.fpr[i]);
+fpu_dump_fpr(>active_fpu.fpr[i], f, is_fpu64);
 }
-
-#undef printfpr
 }
 
 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-- 
2.26.3

[PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays

[Philippe Mathieu-Daudé]

Since all entries are no more than 4 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 4 const char.

Suggested-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/internal.h | 4 ++--
 target/mips/cpu.c  | 2 +-
 target/mips/fpu.c  | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index a8644f754a6..37f54a8b3fc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -71,8 +71,8 @@ struct mips_def_t {
 int32_t SAARP;
 };
 
-extern const char * const regnames[32];
-extern const char * const fregnames[32];
+extern const char regnames[32][4];
+extern const char fregnames[32][4];
 
 extern const struct mips_def_t mips_defs[];
 extern const int mips_defs_number;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f354d18aec4..ed9552ebeb7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,7 +35,7 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
-const char * const regnames[32] = {
+const char regnames[32][4] = {
 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
diff --git a/target/mips/fpu.c b/target/mips/fpu.c
index 1447dba3fa3..c7c487c1f9f 100644
--- a/target/mips/fpu.c
+++ b/target/mips/fpu.c
@@ -17,7 +17,7 @@ const FloatRoundMode ieee_rm[4] = {
 float_round_down
 };
 
-const char * const fregnames[32] = {
+const char fregnames[32][4] = {
 "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
 "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-- 
2.26.3

[PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds

[Philippe Mathieu-Daudé]

TL;DR:

This series restrict TCG-specific objects by moving them to
the tcg/ subdir. Code is moved around to satisfy 3 cases:
{ generic sysemu / tcg sysemu / tcg user}.

Since v1:
- Addressed Richard review comments
- Added Richard R-b tag

Missing review: 5, 7, 8, 17, 18, 23

Hi,

This series move the MIPS TCG files under target/mips/tcg/.
tcg/ is split into {sysemu and user}, and code common to
both user/sysemu is left under tcg/ root.

Non-user code is moved to sysemu/ (common to TCG and KVM).

- Patches 1 & 10 are Meson generic
- Patches 2 to 9 move generic symbols around to satisfly KVM linking
- Patch 11 introduces tcg-internal.h where we'll move TCG specific
  prototypes from the current big internal.h
- Patches 12-27 move code by topic (first user, then sysemu, then tcg)
- Patch 28 restrict TCG specific machines to TCG (to actually
  only build malta/loongson3-virt machines when restricted to KVM)
- Patch 29 finally add a CI job with "KVM-only" config:
  https://gitlab.com/philmd/qemu/-/jobs/1189874868 (12min 5sec)

Diffstat is not that bad, and many #ifdef'ry removed.

Please review,

Phil.

Based-on: <20210413081008.3409459-1-f4...@amsat.org>
  "exec: Remove accel/tcg/ from include paths"

Philippe Mathieu-Daudé (29):
  target/mips: Simplify meson TCG rules
  target/mips: Move IEEE rounding mode array to new source file
  target/mips: Move msa_reset() to new source file
  target/mips: Make CPU/FPU regnames[] arrays global
  target/mips: Optimize CPU/FPU regnames[] arrays
  target/mips: Restrict mips_cpu_dump_state() to cpu.c
  target/mips: Turn printfpr() macro into a proper function
  target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"
  target/mips: Extract load/store helpers to ldst_helper.c
  meson: Introduce meson_user_arch source set for arch-specific
user-mode
  target/mips: Introduce tcg-internal.h for TCG specific declarations
  target/mips: Add simple user-mode mips_cpu_do_interrupt()
  target/mips: Add simple user-mode mips_cpu_tlb_fill()
  target/mips: Move cpu_signal_handler definition around
  target/mips: Move sysemu specific files under sysemu/ subfolder
  target/mips: Move physical addressing code to sysemu/physaddr.c
  target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
  target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
  target/mips: Restrict mmu_init() to TCG
  target/mips: Move tlb_helper.c to tcg/sysemu/
  target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
  target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
  target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
  target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
  target/mips: Move exception management code to exception.c
  target/mips: Move CP0 helpers to sysemu/cp0.c
  target/mips: Move TCG source files under tcg/ sub directory
  hw/mips: Restrict non-virtualized machines to TCG
  gitlab-ci: Add KVM mips64el cross-build jobs

 meson.build  |6 +
 target/mips/helper.h |  183 +--
 target/mips/internal.h   |  106 +-
 target/mips/tcg/tcg-internal.h   |   64 +
 target/mips/{ => tcg}/msa_helper.h.inc   |0
 target/mips/tcg/sysemu_helper.h.inc  |  185 +++
 target/mips/{ => tcg}/mips32r6.decode|0
 target/mips/{ => tcg}/mips64r6.decode|0
 target/mips/{ => tcg}/msa32.decode   |0
 target/mips/{ => tcg}/msa64.decode   |0
 target/mips/{ => tcg}/tx79.decode|0
 target/mips/cpu.c|  311 ++---
 target/mips/fpu.c|   25 +
 target/mips/msa.c|   60 +
 target/mips/op_helper.c  | 1210 --
 target/mips/{ => sysemu}/addr.c  |0
 target/mips/sysemu/cp0.c |  123 ++
 target/mips/{ => sysemu}/cp0_timer.c |0
 target/mips/{ => sysemu}/machine.c   |0
 target/mips/sysemu/physaddr.c|  257 
 target/mips/{ => tcg}/dsp_helper.c   |0
 target/mips/tcg/exception.c  |  169 +++
 target/mips/{ => tcg}/fpu_helper.c   |8 -
 target/mips/tcg/ldst_helper.c|  304 +
 target/mips/{ => tcg}/lmmi_helper.c  |0
 target/mips/{ => tcg}/msa_helper.c   |   36 -
 target/mips/{ => tcg}/msa_translate.c|0
 target/mips/{ => tcg}/mxu_translate.c|0
 target/mips/tcg/op_helper.c  |  421 ++
 target/mips/{ => tcg}/rel6_translate.c   |0
 target/mips/{ => tcg/sysemu}/cp0_helper.c|0
 target/mips/{ => tcg/sysemu}/mips-semi.c |0
 target/mips/tcg/sysemu/special_helper.c  |  173 +++
 target/mips/{ => tcg/sysemu}/tlb_helper.c|  612 +
 target/mips/{ => tcg}/translate.c|  104 +-
 target/mips/{ => tcg}/translate_addr_const.c |0
 

Re: [PATCH 06/26] target/mips: Extract load/store helpers to ldst_helper.c

[Philippe Mathieu-Daudé]

On 4/18/21 9:08 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> +static inline hwaddr do_translate_address(CPUMIPSState *env,
>> +  target_ulong address,
>> +  MMUAccessType access_type,
>> +  uintptr_t retaddr)
>> +{
>> +    hwaddr paddr;
>> +    CPUState *cs = env_cpu(env);
>> +
>> +    paddr = cpu_mips_translate_address(env, address, access_type);
>> +
>> +    if (paddr == -1LL) {
>> +    cpu_loop_exit_restore(cs, retaddr);
>> +    } else {
>> +    return paddr;
>> +    }
>> +}
> 
> Code motion, so,
> Reviewed-by: Richard Henderson 
> 
> but I think that it's a mistake for cpu_mips_translate_address to split
> the raise_mmu_exception from the cpu_loop_exit_restore.  If you make the
> changes to env to indicate the exception, you *must* then go back to the
> main loop.
> 
> There seems to be exactly one caller, this one, so it should be trivial
> to change, which the lets do_translate_address vanish entirely.

I'm taking note of this comment and will try to address it later.

Re: [PATCH 14/26] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

[Philippe Mathieu-Daudé]

On 4/18/21 9:35 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> Declare cpu_mips_get_random() and update_pagemask() on local scope,
> 
> What is "local scope"?  Anyway, I don't see what this has to do with the
> rest of the code movement.

I guess I meant 'TCG'. I'll split.

[Bug 1921061] Re: Corsair iCUE Install Fails, qemu VM Reboots

[Russell Morris]

Hi,

Slight update - as I decided to passthru my NIC as well => driver
install there also causes a VM (Windows 10) reboot. Seems all driver
installs fail?

Running on the latest master, QEMU emulator version 5.2.93 (v6.0.0-rc3).

Thanks!

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921061

Title:
  Corsair iCUE Install Fails, qemu VM Reboots

Status in QEMU:
  New

Bug description:
  Hi,

  I had this working before, but in the latest version of QEMU (built
  from master), when I try to install Corsair iCUE, and it gets to the
  driver install point => my Windows 10 VM just reboots! I would be
  happy to capture logs, but ... what logs exist for an uncontrolled
  reboot? Thinking they are lost in the reboot :-(.

  Thanks!

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1921061/+subscriptions

Re: [PATCH v4 08/12] target/hexagon: prepare input for the idef-parser

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

+++ b/target/hexagon/idef-parser/prepare
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+#
+# Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved.
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see .
+#
+
+set -e
+set -o pipefail
+
+# Run the preprocessor and drop comments
+cpp "$@" | grep -v '^#'


Any reason not to handle '#' lines in the parser?


r~

Re: [PATCH v4 07/12] target/hexagon: expose next PC in DisasContext

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/translate.c | 3 ++-
  target/hexagon/translate.h | 1 +
  2 files changed, 3 insertions(+), 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 06/12] target/hexagon: introduce new helper functions

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

+void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot)
+{
+tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
+tcg_gen_movi_tl(hex_store_width[slot], width);
+tcg_gen_mov_tl(hex_store_val32[slot], src);
+}
+
+void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
+unsigned slot)
+{
+gen_store32(vaddr, src, 1, slot);
+ctx->store_width[slot] = 1;
+}


Why is store_width here and not in gen_store32?
Do you really need so many helpers here, as opposed to making use of MemOp?


+void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+gen_sat_i32(dest, source, width);
+TCGv zero = tcg_const_i32(0);
+TCGv one = tcg_const_i32(1);
+tcg_gen_movcond_i32(TCG_COND_NE, ovfl, source, dest, one, zero);


(source != dest ? 1 : 0) -> (source != dest).

Therefore, tcg_gen_setcond_i32.

Or did you intend

ovfl = (source != dest ? 1 : ovfl)?

which is probably still better as

  tcg_gen_setcond_tl(TCG_COND_NE, tmp, source,dest);
  tcg_gen_or_tl(ovfl, ovfl, tmp);


+void gen_fbrev(TCGv result, TCGv src)
+{
+TCGv lo = tcg_temp_new();
+TCGv tmp1 = tcg_temp_new();
+TCGv tmp2 = tcg_temp_new();
+
+/* Bit reversal of low 16 bits */
+tcg_gen_extract_tl(lo, src, 0, 16);
+tcg_gen_andi_tl(tmp1, lo, 0x);
+tcg_gen_shri_tl(tmp1, tmp1, 1);
+tcg_gen_andi_tl(tmp2, lo, 0x);
+tcg_gen_shli_tl(tmp2, tmp2, 1);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_andi_tl(tmp1, lo, 0x);
+tcg_gen_shri_tl(tmp1, tmp1, 2);
+tcg_gen_andi_tl(tmp2, lo, 0x);
+tcg_gen_shli_tl(tmp2, tmp2, 2);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_andi_tl(tmp1, lo, 0xf0f0);
+tcg_gen_shri_tl(tmp1, tmp1, 4);
+tcg_gen_andi_tl(tmp2, lo, 0x0f0f);
+tcg_gen_shli_tl(tmp2, tmp2, 4);
+tcg_gen_or_tl(lo, tmp1, tmp2);
+tcg_gen_bswap16_tl(lo, lo);
+
+/* Final tweaks */
+tcg_gen_deposit_tl(result, src, lo, 0, 16);
+tcg_gen_or_tl(result, result, lo);
+
+tcg_temp_free(lo);
+tcg_temp_free(tmp1);
+tcg_temp_free(tmp2);
+}


Coordinate with Taylor.
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg10007.html


r~

Re: [PATCH 23/26] target/mips: Move helper.h -> tcg/helper.h.inc

[Philippe Mathieu-Daudé]

On 4/18/21 10:34 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> TCG frontend "exec/helper-head.h" expects each target to declare
>> its helpers in 'target/$TARGET/helper.h'. To ease maintenance we
>> rather to have all TCG specific files under our tcg/ sub directory.
>>
>> Move the current 'helper.h' there, and add a one-line 'helper.h'
>> which re-include it.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>>   target/mips/helper.h | 614 +--
>>   target/mips/tcg/helper.h.inc | 613 ++
>>   2 files changed, 614 insertions(+), 613 deletions(-)
>>   create mode 100644 target/mips/tcg/helper.h.inc
> 
> Eh.  Ok, I guess.
> 
> If we renamed the file tcg-helper.h{,.inc?} globally, would you still
> want it moved into your tcg/ subdirectory?

Not really... I wanted to have anything TCG related under tcg/,
but I can't find any good reason for it (I was thinking about
finer MAINTAINERS granularity, but this doesn't bring much).

I'll drop this patch, no need to change the other targets.

Thanks for the reviews!

Phil.

Re: [PATCH v4 05/12] target/hexagon: make helper functions non-static

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Make certain helper functions non-static, making them available outside
genptr.c. These functions are required by code generated by the
idef-parser.

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/genptr.c | 7 ---
  target/hexagon/genptr.h | 6 ++
  2 files changed, 10 insertions(+), 3 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 04/12] target/hexagon: make slot number an unsigned

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Paolo Montesel

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  target/hexagon/genptr.c | 6 --
  target/hexagon/macros.h | 2 +-
  2 files changed, 5 insertions(+), 3 deletions(-)


Acked-by: Richard Henderson 

r~

Re: [PATCH v4 02/12] target/hexagon: update MAINTAINERS for idef-parser

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Alessandro Di Federico

Signed-off-by: Alessandro Di Federico
---
  MAINTAINERS | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v4 01/12] tcg: expose TCGCond manipulation routines

[Richard Henderson]

On 4/15/21 9:34 AM, Alessandro Di Federico wrote:

From: Alessandro Di Federico

This commit moves into a separate file routines used to manipulate
TCGCond. These will be employed by the idef-parser.

Signed-off-by: Alessandro Di Federico
Signed-off-by: Paolo Montesel
---
  include/tcg/tcg-cond.h | 101 +
  include/tcg/tcg.h  |  70 +---
  2 files changed, 102 insertions(+), 69 deletions(-)
  create mode 100644 include/tcg/tcg-cond.h


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 10/26] target/mips: Add simple user-mode mips_cpu_tlb_fill()

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().

Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.

This will allow us to restrict tlb_helper.c to sysemu.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/tcg/user/helper.c | 36 +++
  target/mips/tlb_helper.c  | 10 --
  2 files changed, 36 insertions(+), 10 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 09/26] target/mips: Add simple user-mode mips_cpu_do_interrupt()

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

  target/mips/tcg/user/helper.c| 28 


Since only this and the next helper go in here, perhaps continue to call it 
tlb_helper.c?  Otherwise,


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 25/26] hw/mips: Restrict non-virtualized machines to TCG

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Only the malta and loongson3-virt machines support KVM.

Restrict the other machines to TCG:

  - mipssim
  - magnum
  - pica61
  - fuloong2e
  - boston

Signed-off-by: Philippe Mathieu-Daudé
---
  hw/mips/meson.build | 11 +++
  1 file changed, 7 insertions(+), 4 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 26/26] gitlab-ci: Add KVM mips64el cross-build jobs

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).

Only build the mips64el target which is known to work
and has users.

Signed-off-by: Philippe Mathieu-Daudé
---
  .gitlab-ci.d/crossbuilds.yml | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 24/26] target/mips: Move TCG source files under tcg/ sub directory

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.

Signed-off-by: Philippe Mathieu-Daudé
---


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 23/26] target/mips: Move helper.h -> tcg/helper.h.inc

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

TCG frontend "exec/helper-head.h" expects each target to declare
its helpers in 'target/$TARGET/helper.h'. To ease maintenance we
rather to have all TCG specific files under our tcg/ sub directory.

Move the current 'helper.h' there, and add a one-line 'helper.h'
which re-include it.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/helper.h | 614 +--
  target/mips/tcg/helper.h.inc | 613 ++
  2 files changed, 614 insertions(+), 613 deletions(-)
  create mode 100644 target/mips/tcg/helper.h.inc


Eh.  Ok, I guess.

If we renamed the file tcg-helper.h{,.inc?} globally, would you still want it 
moved into your tcg/ subdirectory?



r~

Re: [PATCH 22/26] target/mips: Move CP0 helpers to sysemu/cp0.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |   9 +--
  target/mips/cpu.c  | 103 ---
  target/mips/sysemu/cp0.c   | 123 +
  target/mips/sysemu/meson.build |   1 +
  4 files changed, 129 insertions(+), 107 deletions(-)
  create mode 100644 target/mips/sysemu/cp0.c


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 21/26] target/mips: Move exception management code to exception.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h |  13 ---
  target/mips/tcg/tcg-internal.h |  14 +++
  target/mips/cpu.c  | 113 --
  target/mips/exception.c| 169 +
  target/mips/op_helper.c|  37 
  target/mips/meson.build|   1 +
  6 files changed, 184 insertions(+), 163 deletions(-)
  create mode 100644 target/mips/exception.c


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 19/26] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Philippe Mathieu-Daudé]

On 4/18/21 9:52 PM, Richard Henderson wrote:
> On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:
>> Move helper_cache() to tcg/sysemu/special_helper.c.
>>
>> The CACHE opcode is privileged and is not accessible in user
>> emulation. However we get a link failure when restricting the
>> symbol to sysemu. For now, add a stub to satisfy linking, which
>> abort if ever called.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>>   target/mips/op_helper.c | 35 -
>>   target/mips/tcg/sysemu/special_helper.c | 33 +++
>>   target/mips/tcg/user/stubs.c    | 29 
>>   target/mips/tcg/user/meson.build    |  1 +
>>   4 files changed, 63 insertions(+), 35 deletions(-)
>>   create mode 100644 target/mips/tcg/user/stubs.c
> 
> You could add a different stub to translate.c instead.  See
> 
> https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08595.html

Great!

I think STUB_HELPER() belong to include/exec/helper-*.h.

Thanks,

Phil.

Re: Resetting non-qdev children in a 3-phase reset device

[Philippe Mathieu-Daudé]

+Markus

On 4/9/21 8:13 PM, Peter Maydell wrote:
> I wanted to convert the hw/misc/mps2-scc.c device from old-style
> to 3-phase reset as a prerequisite for another change to the device,
> but I ran into a problem because currently it has some TYPE_DEVICE
> QOM child objects, the LEDs. Because TYPE_DEVICE don't live in the
> qbus hierarchy, the device resets them manually in its DeviceClass::reset
> method:
> 
> for (i = 0; i < ARRAY_SIZE(s->led); i++) {
> device_cold_reset(DEVICE(s->led[i]));
> }
> 
> This makes converting to 3-phase reset awkward. The obvious "natural"
> approach would be to say "in this device's phase X, invoke phase X
> for these objects", but we have no API for that. (The functions which
> would do it, resettable_phase_enter() etc, are static inside resettable.c.)
> 
> Ignoring the phasing and trying to just call device_cold_reset() in
> the 'enter' phase results in an assertion failure, because we trip
> the assert(!enter_phase_in_progress) in resettable_assert_reset(),
> which doesn't expect us to be triggering a reset inside a reset.
> 
> Ideally one would want to be able to add the LEDs to the list of
> things which are children of this object for purposes of reset
> (so they are iterated as part of the resettable_child_foreach()
> logic and their phases are automatically invoked at the right point).
> But for a subclass of DeviceState that's device_reset_child_foreach()
> and it only iterates any qbus children of this device.
> 
> Any clever ideas?

Not very clever... We could kludge it by calling device_legacy_reset()
instead of device_cold_reset() in mps2_fpgaio_reset()... But that
mean we are going backward with the API.


OK, back to read your previous explanations... and the threads around.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg723312.html
https://www.mail-archive.com/qemu-devel@nongnu.org/msg738242.html

"Note that [qdev/qbus hierarchy] is an entirely separate thing
from the QOM hierarchy of parent-and-child object relationships."

Hmm OK. I guess I'm confused seeing parts are overlapping when they
aren't. So setting the QOM parent relationship helps in having a
correct QOM path and the object is displayed nicely in the qom-tree,
but doesn't bring anything on the qdev side.

So back to qdev.

- TYPE_DEVICE (aka 'qdev') is abstract.
  It inherits TYPE_OBJECT.
  It can provide a bus (aka qbus) to plug things.
  It implements TYPE_RESETTABLE_INTERFACE.

- TYPE_SYS_BUS_DEVICE is also abstract.
  It inherits from TYPE_DEVICE, setting qbus=TYPE_SYSTEM_BUS

(
To confuse more, there is some undocumented API called
'device_listener' in qdev which instead uses sysbus:
void device_listener_register(DeviceListener *listener);
void device_listener_unregister(DeviceListener *listener);
)

Making MachineState inherit TYPE_DEVICE and re-implement the
TYPE_RESETTABLE_INTERFACE doesn't seem going in the right
direction...
If TYPE_MACHINE were qdev, its qbus could be a ResetBus. Again
it feels wrong (over engineering).

> Maybe some mechanism for marking "these things which are my
> QOM children I want to be reset when I am reset (so make them> reset children 
> of me and don't reset them as part of the
> qbus-tree-walking)" would be useful. I do think that in a
> lot of cases we want to be doing something closer to "reset
> along the QOM tree".

Eh here you mention QOM again... Shouldn't it be qdev?

I know the LED is just an example of a broader problem.
I indeed took care to add the QOM parent relation:

(qemu) info qom-tree
/machine (mps2-an385-machine)
  /fpgaio (mps2-fpgaio)
/mps2-fpgaio[0] (memory-region)
/userled0 (led)
  /unnamed-gpio-in[0] (irq)
/userled1 (led)
  /unnamed-gpio-in[0] (irq)
  /scc (mps2-scc)
/mps2-scc[0] (memory-region)
/scc-led0 (led)
  /unnamed-gpio-in[0] (irq)
/scc-led1 (led)
  /unnamed-gpio-in[0] (irq)
...

So looking at this qom-tree, the reset tree seems to me
more natural than the sysbus one, but IIRC not many models
set this QOM relationship.
QOM objects aren't enforced to have a relation with a parent,
as opposed as recent changes from Markus to always have a qdev
on a qbus). But even without parent they end in the /unattached
container below /machine, so if the reset were there, the
machine could still iterate over the /unattached children.

> I really do need to spend some time working
> out what the right thing with reset is and how we might get
> from where we are now to there...

Well, finally this QOM-tree reset is appealing.

Sorry if I haven't been very helpful :S Still processing the
problem in background...

Regards,

Phil.

Re: [PATCH 20/26] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move TLB management helpers to tcg/sysemu/tlb_helper.c.

Signed-off-by: Philippe Mathieu-Daudé
---
4 checkpatch errors:

   ERROR: space prohibited after that '&' (ctx:WxW)
   #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
   +tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
   +tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
   +tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
 ^

   ERROR: space prohibited after that '&' (ctx:WxW)
   #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
   +tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
 ^


Wow, that's amazingly bogus.  I'm amazed that no one has re-written checkpatch 
in e.g. sparse...


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 19/26] target/mips: Move helper_cache() to tcg/sysemu/special_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move helper_cache() to tcg/sysemu/special_helper.c.

The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub to satisfy linking, which
abort if ever called.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/op_helper.c | 35 -
  target/mips/tcg/sysemu/special_helper.c | 33 +++
  target/mips/tcg/user/stubs.c| 29 
  target/mips/tcg/user/meson.build|  1 +
  4 files changed, 63 insertions(+), 35 deletions(-)
  create mode 100644 target/mips/tcg/user/stubs.c


You could add a different stub to translate.c instead.  See

https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg08595.html


r~

Re: [PATCH v2] hw/mips/jazz: Remove confusing ifdef'ry

[Philippe Mathieu-Daudé]

On 4/18/21 8:48 PM, Richard Henderson wrote:
> On 4/18/21 9:51 AM, Philippe Mathieu-Daudé wrote:
>> The jazz machine is not used under user emulation and
>> does not support KVM. Simplify the ifdef'ry.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> Reviewed-by: Richard Henderson
>> Reviewed-by: Claudio Fontana
>> Message-Id:<20210226132723.3969650-3-f4...@amsat.org>
>> ---
>> v2: Rebased.
>>
>> Based-on:<20210418163134.1133100-1-f4...@amsat.org>
>> ---
>>   hw/mips/jazz.c | 4 
>>   1 file changed, 4 deletions(-)
> 
> Were you going to apply this one before my cleanup to completely remove
> this hook manipulation?
> 
> https://patchew.org/QEMU/20210227232519.222663-1-richard.hender...@linaro.org/20210227232519.222663-2-richard.hender...@linaro.org/

Doh I completely forgot your patch =)

Let's forget about mine then!

Regards,

Phil.

Re: [PATCH 18/26] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".

Signed-off-by: Philippe Mathieu-Daudé 


Reviewed-by: Richard Henderson 


-static void set_pc(CPUMIPSState *env, target_ulong error_pc)
-{
-env->active_tc.PC = error_pc & ~(target_ulong)1;
-if (error_pc & 1) {
-env->hflags |= MIPS_HFLAG_M16;
-} else {
-env->hflags &= ~(MIPS_HFLAG_M16);
-}
-}


I'll note that this is identical to mips_cpu_set_pc, bar CPUState vs 
CPUMIPSState.


r~

Re: [PATCH 17/26] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h  |  6 --
  target/mips/tcg/sysemu/tlb_helper.c | 13 +++--
  2 files changed, 7 insertions(+), 12 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 16/26] target/mips: Move tlb_helper.c to tcg/sysemu/

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()

Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h| 5 -
  target/mips/tcg/tcg-internal.h| 5 +
  target/mips/{ => tcg/sysemu}/tlb_helper.c | 3 ---
  target/mips/meson.build   | 1 -
  target/mips/tcg/sysemu/meson.build| 1 +
  5 files changed, 6 insertions(+), 9 deletions(-)
  rename target/mips/{ => tcg/sysemu}/tlb_helper.c (99%)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 15/26] target/mips: Restrict mmu_init() to TCG

[Richard Henderson]

On 4/18/21 9:31 AM, Philippe Mathieu-Daudé wrote:

mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/internal.h | 3 ---
  target/mips/tcg/tcg-internal.h | 2 ++
  target/mips/cpu.c  | 2 +-
  3 files changed, 3 insertions(+), 4 deletions(-)


Reviewed-by: Richard Henderson 

r~