Re: [PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Edgar E. Iglesias]

On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé 
> 
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
> 
> Convert the generic reset to a enter/exit resettable ones, and
> remove the qemu_register_reset() call.

Same comment here regarding reset_exit -> reset_hold.

Cheers,
Edgar


> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/timer/etraxfs_timer.c | 14 +++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
> index 5379006086f..7dd3daf6771 100644
> --- a/hw/timer/etraxfs_timer.c
> +++ b/hw/timer/etraxfs_timer.c
> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>  }
>  };
>  
> -static void etraxfs_timer_reset(void *opaque)
> +static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
>  {
> -ETRAXTimerState *t = opaque;
> +ETRAXTimerState *t = ETRAX_TIMER(obj);
>  
>  ptimer_transaction_begin(t->ptimer_t0);
>  ptimer_stop(t->ptimer_t0);
> @@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
>  t->rw_wd_ctrl = 0;
>  t->r_intr = 0;
>  t->rw_intr_mask = 0;
> +}
> +
> +static void etraxfs_timer_reset_exit(Object *obj)
> +{
> +ETRAXTimerState *t = ETRAX_TIMER(obj);
> +
>  qemu_irq_lower(t->irq);
>  }
>  
> @@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, 
> Error **errp)
>  memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>"etraxfs-timer", 0x5c);
>  sysbus_init_mmio(sbd, &t->mmio);
> -qemu_register_reset(etraxfs_timer_reset, t);
>  }
>  
>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
>  {
>  DeviceClass *dc = DEVICE_CLASS(klass);
> +ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>  dc->realize = etraxfs_timer_realize;
> +rc->phases.enter = etraxfs_timer_reset_enter;
> +rc->phases.exit = etraxfs_timer_reset_exit;
>  }
>  
>  static const TypeInfo etraxfs_timer_info = {
> -- 
> 2.26.3
> 

Re: [PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Edgar E. Iglesias]

On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé 
> 
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
> 
> Convert the generic reset to a enter/exit resettable ones, and
> remove the qemu_register_reset() call.

Hi Philippe,

The interrupt should be updated in the reset_hold phase, otherwise
interrupts stay asserted while the device is in reset.

Otherwise this looks good to me.

Cheers,
Edgar


> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/timer/etraxfs_timer.c | 14 +++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
> index 5379006086f..7dd3daf6771 100644
> --- a/hw/timer/etraxfs_timer.c
> +++ b/hw/timer/etraxfs_timer.c
> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>  }
>  };
>  
> -static void etraxfs_timer_reset(void *opaque)
> +static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
>  {
> -ETRAXTimerState *t = opaque;
> +ETRAXTimerState *t = ETRAX_TIMER(obj);
>  
>  ptimer_transaction_begin(t->ptimer_t0);
>  ptimer_stop(t->ptimer_t0);
> @@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
>  t->rw_wd_ctrl = 0;
>  t->r_intr = 0;
>  t->rw_intr_mask = 0;
> +}
> +
> +static void etraxfs_timer_reset_exit(Object *obj)
> +{
> +ETRAXTimerState *t = ETRAX_TIMER(obj);
> +
>  qemu_irq_lower(t->irq);
>  }
>  
> @@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, 
> Error **errp)
>  memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>"etraxfs-timer", 0x5c);
>  sysbus_init_mmio(sbd, &t->mmio);
> -qemu_register_reset(etraxfs_timer_reset, t);
>  }
>  
>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
>  {
>  DeviceClass *dc = DEVICE_CLASS(klass);
> +ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>  dc->realize = etraxfs_timer_realize;
> +rc->phases.enter = etraxfs_timer_reset_enter;
> +rc->phases.exit = etraxfs_timer_reset_exit;
>  }
>  
>  static const TypeInfo etraxfs_timer_info = {
> -- 
> 2.26.3
> 

[Bug 1793904] Re: files are randomly overwritten by Zero Bytes

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


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Title:
  files are randomly overwritten by Zero Bytes

Status in QEMU:
  Incomplete

Bug description:
  Hello together,

  I am currently tracking down a "Hard to reproduce" bug on my systems
  that I first discovered during gitlab installation:

  
  Here is the Text from the Gitlab Bug 
https://gitlab.com/gitlab-org/gitlab-ce/issues/51023
  
--

  Steps to reproduce

  I still do not have all the steps together to reproduce, so far it is:
  apt install gitlab-ce and
  gitlab-rake backup:recovery
  Then it works for some time before it fails.

  What is the current bug behavior?

  I have a 12 hour old Installation of gitlab ce 11.2.3-ce.0 for debian
  stretch on a fresh debian stretch system together with our imported
  data. However it turns out that some gitlab related files contain Zero
  bytes instead of actual data.

  root@gitlab:~# xxd -l 16 /opt/gitlab/bin/gitlab-ctl
  :          

  This behaviour is somewhat strange because it was working for a few
  minutes/hours. I did write a shell script to find out which files are
  affected of this memory loss. It turns out that only files located
  under /opt/gitlab are affected, if I rule out files like
  /var/log/faillog and some postgresql table files.

  What I find even stranger is that it does not seem to affect
  Logfiles/databases/git_repositorys but application files, like .rb
  scripts. and not all of them. No non gitlab package is affected.

  What is the expected correct behavior?
  Binarys and .rb files should stay as they are.

  Possible fixes

  I am still investigating, I hope that it is not an infrastructure problem 
(libvirt/qemu/glusterfs) it can still be one but the point that files of 
/opt/gitlab are affected and not any logfile and that we to not have similar 
problems with any other system leads me to the application for now.
  If I would have used docker the same problem might have caused a reboot of 
the container.
  But for the Debian package it is a bit of work to recover. That is all a 
workaround, however.
  
-

  I do have found 2 more systems having the same problem with different
  software:

  root@erp:~# xxd -l 16 /usr/share/perl/5.26.2/constant.pm
  :          

  The Filesize itself is, compared with another machine 1660 Bytes
  for both the corrupted and the intact file. It looks to me from the
  outside that if some data in the qcow2 file is written too many bytes
  get written so it sometimes overwites data of existing files located
  right after the position in memory where the write goes to.

  I would like to rule out Linux+Ext4 filesystems because I find it
  highly unlikely that such an error keeps undiscovered in that part of
  the environment for long. I think the same might go for qemu.

  Which leaves qemu, gemu+gluster:// mount, qcow2 volumes, glusterfs,
  network. So I am now going to check if I can find any system which
  gets its volumes via fusermount instead of gluster:// path if the
  error is gone there. This may take a while.

  
  - some software versions---

  QEMU emulator version 2.12.0 (Debian 1:2.12+dfsg-3)
  Copyright (c) 2003-2017 Fabrice Bellard and the QEMU Project developers

  libvirt-daemon-driver-storage-gluster/testing,unstable,now 4.6.0-2
  amd64 [installed]

  ii  glusterfs-client   4.1.3-1amd64

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[Bug 1802465] Re: typing string via VNC is unreliable

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


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Title:
  typing string via VNC is unreliable

Status in QEMU:
  Incomplete

Bug description:
  QEMU version is 3.0.0

  # Description

  The problem is that, when typing string through VNC, it can be
  unreliable -- sometimes some key strokes get skipped, sometimes get
  swapped, sometimes get repeated.  There's no problem when typing
  through VNC on physical hardware.

  # Steps to reproduce

  1. Launch virtual machine by:

  qemu-kvm -display vnc=:1 -m 2048 opensuse-leap-15.qcow2

  2. Connect to VNC by:

  vncviewer -Shared :5901

  3. Simulate a series of key strokes by "vncdotool" [1]:

  vncdotool -s 127.0.0.1::5901 typefile strings_to_be_typed.txt

  4. Usually after a few hundred keys are typed, something goes wrong.

  I attached a screenshot that it mistypes " hello" to "h ello".

  [1] https://github.com/sibson/vncdotool

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[Bug 1802915] Re: GTK display refresh rate is throttled

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  GTK display refresh rate is throttled

Status in QEMU:
  Incomplete

Bug description:
  Guest OS running with GL enabled GTK display shows a reduced refresh
  rate, e.g. moving cursor around with iGVT-g DMA Buf.

  Apparently, a default refresh interval GUI_REFRESH_INTERVAL_DEFAULT
  (30ms) is defined in include/ui/console.h, throttling the display
  refresh rate at 33Hz.

  To correct this throttle issue, a shorter interval (16 or 17
  milliseconds) should be applied to display change listener or the
  default value should be modified.

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[Bug 1781281] Re: qemu-ppc64le uncaught target signal 4 (Illegal instruction)

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  qemu-ppc64le uncaught target signal 4 (Illegal instruction)

Status in QEMU:
  Incomplete

Bug description:
  qemu-ppc64le version 2.12.0
  host machine: x86_64 Arch Linux 

  I'm currently working on VSX support in libVPX, I'm using qemu to
  test, on line 723 of vpx_dsp/ppc/loopfilter_vsx.c, when I change the
  vec_sub to vec_subs I get:

  qemu: uncaught target signal 4 (Illegal instruction) - core dumped

  Thread 1 "qemu-ppc64le" received signal SIGILL, Illegal instruction.
  0x766d1bf6 in sigsuspend () from /usr/lib/libc.so.6
  (gdb) bt
  #0  0x766d1bf6 in sigsuspend () from /usr/lib/libc.so.6
  #1  0x5567ee68 in ?? ()
  #2  0x5567fd18 in ?? ()
  #3  0x556805ef in process_pending_signals ()
  #4  0x55661e69 in cpu_loop ()
  #5  0x5561fd72 in main ()

  This can be reproduced by downloading this patch (patchset 1):

  https://chromium-review.googlesource.com/c/webm/libvpx/+/1134034

  and running

  qemu-ppc64le -L /home/ltrudeau/x-tools/powerpc64le-unknown-linux-gnu
  /powerpc64le-unknown-linux-gnu/sysroot/  ./test_libvpx
  --gtest_also_run_disabled_tests "--gtest_filter=VSX/*Loop*/*"

  I don't observe any issues when running the code on a POWER9 machine.

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[Bug 1783437] Re: read-modify-write page faults error code has write bit unset

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  read-modify-write page faults error code has write bit unset

Status in QEMU:
  Incomplete

Bug description:
  Consider the attached C file, which does a read-modify-write of the
  form `add [mem], reg`, where `mem` points to a non-present page. In
  the resulting page fault, the W/R bit is not set, while real hardware
  does set this bit.

  % gcc -m32 qemu-bug1.c&& ./a.out && qemu-i386 ./a.out
  page fault: addr=0x7000 err=0x6
  page fault: addr=0x7000 err=0x4

  Tested on the qemu-3.0.0-rc1 release.

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[Bug 1785485] Re: Mouse moves erratically when using scroll wheel on Windows NT 4, Windows 95, and Windows 3.1 guests

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  Mouse moves erratically when using scroll wheel on Windows NT 4,
  Windows 95, and Windows 3.1 guests

Status in QEMU:
  Incomplete

Bug description:
  QEMU version: 3.0.0 RC3
  Guests: Windows NT 4.0, Windows 95, Windows 3.1

  Program: When the user uses the scroll wheel, the mouse's movement
  becomes erratic.

  This is noticed immediately when the scroll wheel is used. Sometimes
  the problem can be fixed by moving the scroll wheel some more.

  My theory is this problem is because of the lack of support for the
  Microsoft Intellimouse in these guest operating systems.

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[Bug 1790260] Re: binfmt support not working for x86 host and x86_64 guest

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  binfmt support not working for x86 host and x86_64 guest

Status in QEMU:
  Incomplete

Bug description:
  this is a problem in the qemu-binfmt-conf.sh script and maybe
  somewhere else. the version i checked is the current github mirror
  https://github.com/qemu/qemu/blob/master/scripts/qemu-binfmt-conf.sh

  i am running linux mint 19 32bit on a 32bit x86 cpu and i want to run
  some applications that are only available as x86_64 packages. i use
  multiarch and qemu and it works for simple applications like cacafire.
  however i want to run the application natively from the shell without
  having to use qemu-x86_64 . i also installed the binfmt-support
  package. when i run update-binfmts --display then an extry for x86_64
  is missing and transparent execution is not working.

  the problem seems to be in the qemu-binfmt-conf.sh script. it disables
  the creation of entries for cpus of the same family. this is not a
  problem if you are using a 64bit cpu because 32bit binaries run on it
  natively but it doesnt work in the opposite way. hacking line 310 from

   if [ "$host_family" != "$family" ] ; then

  to

   if [ "$cpu" = "x86_64" ] || [ "$host_family" != "$family" ] ;
  then

  and running it with the --systemd ALL parameter causes a x86_64 config
  file to be created. it still doesnt work but that might have different
  causes.

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[Bug 1793859] Re: GTK display and mouse input area scaling fails when using vfio-pci device

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  GTK display and mouse input area scaling fails when using vfio-pci
  device

Status in QEMU:
  Incomplete

Bug description:
  Version qemu 3.0.0-1 running on Arch. Found on Windows 8.1 and Windows
  10 VM's when using Intel gvt-g device.

  While in fullscreen the GTK display is scaled larger than the x11
  screen or virtual machine resolution. Without choosing zoom-to-fit
  portions of the VM display are not shown on x11 screen regardless of
  the VM resolution. When zoom-to-fit is done the mouse that's shown on
  screen and actual input are off sync. The mouse can wander off screen
  when going left and down.

  This message is shown when changing from gxl-vga to vfio-pci in view menu. 
  (qemu-system-x86_64:6472): Gtk-WARNING **: 09:50:06.663: drawing failure for 
widget 'GtkDrawingArea': NULL pointer
  (qemu-system-x86_64:6472): Gtk-WARNING **: 09:50:06.664: drawing failure for 
widget 'GtkNotebook': NULL pointer
  (qemu-system-x86_64:6472): Gtk-WARNING **: 09:50:06.664: drawing failure for 
widget 'GtkBox': NULL pointer
  (qemu-system-x86_64:6472): Gtk-WARNING **: 09:50:06.664: drawing failure for 
widget 'GtkWindow': NULL pointer

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[Bug 1785902] Re: local/9pfs: Too many levels of symbolic links

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
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Title:
  local/9pfs: Too many levels of symbolic links

Status in QEMU:
  Incomplete

Bug description:
  Version: 2.9.1

  The primary symptom is resolving symlink fails w/ error "too many
  levels of symbolic links".

  My analysis showed that local_readlink() uses local_open_nofollow() to
  open the file and then tries to read it. local_open_nofollow() then
  tries to open the file w/ O_NOFOLLOW, which obviously fails if the
  requested file is a symlink.

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[Bug 1701798] Re: dynamically linked binaries crash for big-endian targets

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
   Status: New => Incomplete

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Title:
  dynamically linked binaries crash for big-endian targets

Status in QEMU:
  Incomplete

Bug description:
  On the targets
hppa
m68k
mips
mips64
powerpc
powerpc64
s390x
sparc64
  dynamically linked binaries crash, but statically linked binaries work.
  On the targets
aarch64
alpha
armhf
powerpc64le
sh4
  both dynamically linked and statically linked binaries work.

  How to reproduce:

  1) On Ubuntu 16.04, install the packages
  g++-5-aarch64-linux-gnu
  g++-5-alpha-linux-gnu
  g++-5-arm-linux-gnueabihf
  g++-5-hppa-linux-gnu
  g++-5-m68k-linux-gnu
  g++-5-mips-linux-gnu
  g++-5-mips64-linux-gnuabi64
  g++-5-powerpc-linux-gnu
  g++-5-powerpc64-linux-gnu
  g++-5-powerpc64le-linux-gnu
  g++-5-s390x-linux-gnu
  g++-5-sh4-linux-gnu
  g++-5-sparc64-linux-gnu

  2) Install qemu 2.9.0 from source (for m68k, use the 2.7.0-m68k
  code from https://github.com/vivier/qemu-m68k.git):
  $ ../configure --prefix=/home/bruno/inst-qemu/2.9.0 
--target-list=aarch64-softmmu,alpha-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mipsel-softmmu,mips64-softmmu,mips64el-softmmu,ppc-softmmu,ppc64-softmmu,s390x-softmmu,sh4-softmmu,sparc-softmmu,sparc64-softmmu,x86_64-softmmu,aarch64-linux-user,alpha-linux-user,arm-linux-user,hppa-linux-user,m68k-linux-user,mips-linux-user,mipsel-linux-user,mips64-linux-user,mips64el-linux-user,ppc-linux-user,ppc64-linux-user,ppc64le-linux-user,s390x-linux-user,sh4-linux-user,sparc-linux-user,sparc64-linux-user
 --disable-strip --disable-werror --enable-gtk --enable-vnc
  $ make
  $ make install

  3) Cross-compile the programs:

  $ aarch64-linux-gnu-gcc-5 -O hello.c -o hello.aarch64
  $ alpha-linux-gnu-gcc-5 -O hello.c -o hello.alpha
  $ arm-linux-gnueabihf-gcc-5 -O hello.c -o hello.armhf
  $ hppa-linux-gnu-gcc-5 -O hello.c -o hello.hppa
  $ m68k-linux-gnu-gcc-5 -O hello.c -o hello.m68k
  $ mips-linux-gnu-gcc-5 -O hello.c -o hello.mips
  $ mips64-linux-gnuabi64-gcc-5 -O hello.c -o hello.mips64
  $ powerpc-linux-gnu-gcc-5 -O hello.c -o hello.powerpc
  $ powerpc64-linux-gnu-gcc-5 -O hello.c -o hello.powerpc64
  $ powerpc64le-linux-gnu-gcc-5 -O hello.c -o hello.powerpc64le
  $ s390x-linux-gnu-gcc-5 -O hello.c -o hello.s390x
  $ sh4-linux-gnu-gcc-5 -O hello.c -o hello.sh4
  $ sparc64-linux-gnu-gcc-5 -O hello.c -o hello.sparc64

  4) Run the programs:

  * aarch64 works:
  $ QEMU_LD_PREFIX=/usr/aarch64-linux-gnu ~/inst-qemu/2.9.0/bin/qemu-aarch64 
hello.aarch64
  Hello world

  * alpha works:
  $ QEMU_LD_PREFIX=/usr/alpha-linux-gnu ~/inst-qemu/2.9.0/bin/qemu-alpha 
hello.alpha 
  Hello world

  * armhf works:
  $ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf ~/inst-qemu/2.9.0/bin/qemu-arm 
hello.armhf
  Hello world

  * powerpc64le works:
  $ QEMU_LD_PREFIX=/usr/powerpc64le-linux-gnu 
~/inst-qemu/2.9.0/bin/qemu-ppc64le hello.powerpc64le
  Hello world

  * sh4 works:
  $ QEMU_LD_PREFIX=/usr/sh4-linux-gnu ~/inst-qemu/2.9.0/bin/qemu-sh4 hello.sh4
  Hello world

  * = sparc64 does not work:
  $ QEMU_LD_PREFIX=/usr/sparc64-linux-gnu ~/inst-qemu/2.9.0/bin/qemu-sparc64 
hello.sparc64
  Segmentation fault (core dumped)

  When I copy the file to a machine with `uname -srm` = "Linux 4.5.0-2-sparc64 
sparc64",
  it works:
  $ ./hello.sparc64
  Hello world

  When I copy the file and its execution environment /usr/sparc64-linux-gnu to 
the
  same machine and run the binary in a chroot environment:
  # /bin/hello.sparc64 
  Hello world

  * = mips does not work:
  $ QEMU_LD_PREFIX=/usr/mips-linux-gnu ~/inst-qemu/2.9.0/bin/qemu-mips 
hello.mips
  qemu: uncaught target signal 11 (Segmentation fault) - core dumped

  When I copy the file to a machine with `uname -srm` = "Linux 
3.16.0-4-4kc-malta mips",
  it works:
  $ ./hello.mips
  Hello world

  When I copy the file and its execution environment /usr/mips-linux-gnu to the
  same machine and run the binary in a chroot environment:
  # /bin/hello.mips 
  Hello world

  * = mips64 does not work:
  $ QEMU_LD_PREFIX=/usr/mips64-linux-gnuabi64 ~/inst-qemu/2.9.0/bin/qemu-mips64 
hello.mips64
  qemu: uncaught target signal 11 (Segmentation fault) - core dumped

  When I copy the file to a machine with `uname -srm` = "Linux 
3.16.0-4-5kc-malta mips64",
  it 

[Bug 1703147] Re: Xfer:features:read truncating xml sent to gdb frontends

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
   Status: New => Incomplete

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Title:
  Xfer:features:read truncating xml sent to gdb frontends

Status in QEMU:
  Incomplete

Bug description:
  Around line 1326 in gdbstub.c:

  if (len > (MAX_PACKET_LENGTH - 5) / 2)
  len = (MAX_PACKET_LENGTH - 5) / 2;

  is truncating processor reg description xml files longer than 2045
  bytes.  Deleting these lines works for my immediate need, but they
  seem to be trying to fix some buffer overrun condition so I won't
  offer a patch until we understand their purpose.

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[Bug 1762558] Re: Many crashes with "memslot_get_virt: slot_id 170 too big"-type errors in 2.12.0 rc2

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
   Status: New => Incomplete

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Title:
  Many crashes with "memslot_get_virt: slot_id 170 too big"-type errors
  in 2.12.0 rc2

Status in QEMU:
  Incomplete

Bug description:
  Since qemu 2.12.0 rc2 - qemu-2.12.0-0.6.rc2.fc29 - landed in Fedora
  Rawhide, just about all of our openQA-automated tests of Rawhide
  guests which run with qxl / SPICE graphics in the guest have died
  partway in, always shortly after the test switches from the installer
  (an X environment) to a console on a tty. qemu is, I think, hanging.
  There are always some errors like this right around the time of the
  hang:

  [2018-04-09T20:13:42.0736 UTC] [debug] QEMU: id 0, group 0, virt start 0, 
virt end , generation 0, delta 0
  [2018-04-09T20:13:42.0736 UTC] [debug] QEMU: id 1, group 1, virt start 
7f42dbc0, virt end 7f42dfbfe000, generation 0, delta 7f42dbc0
  [2018-04-09T20:13:42.0736 UTC] [debug] QEMU: id 2, group 1, virt start 
7f42d7a0, virt end 7f42dba0, generation 0, delta 7f42d7a0
  [2018-04-09T20:13:42.0736 UTC] [debug] QEMU: 
  [2018-04-09T20:13:42.0736 UTC] [debug] QEMU: (process:45812): Spice-CRITICAL 
**: memslot.c:111:memslot_get_virt: slot_id 218 too big, addr=da8e21fbda8e21fb

  or occasionally like this:

  [2018-04-09T20:13:58.0717 UTC] [debug] QEMU: id 0, group 0, virt start 0, 
virt end , generation 0, delta 0
  [2018-04-09T20:13:58.0720 UTC] [debug] QEMU: id 1, group 1, virt start 
7ff093c0, virt end 7ff097bfe000, generation 0, delta 7ff093c0
  [2018-04-09T20:13:58.0720 UTC] [debug] QEMU: id 2, group 1, virt start 
7ff08fa0, virt end 7ff093a0, generation 0, delta 7ff08fa0
  [2018-04-09T20:13:58.0720 UTC] [debug] QEMU: 
  [2018-04-09T20:13:58.0720 UTC] [debug] QEMU: (process:25622): Spice-WARNING 
**: memslot.c:68:memslot_validate_virt: virtual address out of range
  [2018-04-09T20:13:58.0720 UTC] [debug] QEMU: virt=0x0+0x18 slot_id=0 
group_id=1
  [2018-04-09T20:13:58.0721 UTC] [debug] QEMU: slot=0x0-0x0 delta=0x0
  [2018-04-09T20:13:58.0721 UTC] [debug] QEMU: 
  [2018-04-09T20:13:58.0721 UTC] [debug] QEMU: (process:25622): Spice-WARNING 
**: display-channel.c:2426:display_channel_validate_surface: invalid surface_id 
1048576
  [2018-04-09T20:14:14.0728 UTC] [debug] QEMU: id 0, group 0, virt start 0, 
virt end , generation 0, delta 0
  [2018-04-09T20:14:14.0728 UTC] [debug] QEMU: id 1, group 1, virt start 
7ff093c0, virt end 7ff097bfe000, generation 0, delta 7ff093c0
  [2018-04-09T20:14:14.0728 UTC] [debug] QEMU: id 2, group 1, virt start 
7ff08fa0, virt end 7ff093a0, generation 0, delta 7ff08fa0
  [2018-04-09T20:14:14.0728 UTC] [debug] QEMU: 
  [2018-04-09T20:14:14.0728 UTC] [debug] QEMU: (process:25622): Spice-CRITICAL 
**: memslot.c:122:memslot_get_virt: address generation is not valid, group_id 
1, slot_id 0, gen 110, slot_gen 0

  The same tests running on Fedora 28 guests on the same hosts are not
  hanging, and the same tests were not hanging right before the qemu
  package got updated, so this seems very strongly tied to the new qemu.

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[Bug 1776478] Re: Getting qemu: uncaught target signal 6 when running lv2 plugin cross-compilation

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
   Status: New => Incomplete

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Title:
  Getting qemu: uncaught target signal 6 when running  lv2 plugin cross-
  compilation

Status in QEMU:
  Incomplete

Bug description:
  Hey,
  I am part of the Zynthian team and we use qemu-arm-static to cross compile 
lv2 audio plugins.

  When running a compilation of DISTRHO-Ports we get:

  lv2_ttl_generator: pthread_mutex_lock.c:81: __pthread_mutex_lock: Assertion 
`mutex->__data.__owner == 0' failed.
  qemu: uncaught target signal 6 (Aborted) - core dumped
  ./scripts/generate-ttl.sh: line 27: 16524 Aborted $GEN ./$FILE
  Makefile:62: recipe for target 'gen_lv2' failed
  make[1]: *** [gen_lv2] Error 134
  make[1]: Leaving directory '/home/pi/zynthian-sw/plugins/DISTRHO-Ports'
  Makefile:104: recipe for target 'lv2' failed
  make: *** [lv2] Error 2

  
  lv2_ttl_generator source is here:
  https://github.com/DISTRHO/DISTRHO-Ports/tree/master/libs/lv2-ttl-generator

  The command that is ruining is
  lv2_ttl_generator ./TAL-Filter-2.so 

  And ./TAL-Filter-2.so source is here:
  https://github.com/DISTRHO/DISTRHO-Ports/tree/master/ports/tal-filter-2/source


  Is there a way to debug what is going on?
  This runs fine on a Raspberrypi which is armv7

  A workaround would also help.

  
  Bug in Zynthian:
  https://github.com/zynthian/zynthian-sys/issues/59
  Bug in DISTRHO-Ports:
  https://github.com/DISTRHO/DISTRHO-Ports/issues/29

  Using qemu-arm-static version from master from two days ago:
  qemu-arm version 2.12.50 (v2.12.0-1182-ga7a7309ca5-dirty), commit: 
a7a7309ca52c327c6603d60db90ae4feeae719f7

  Also saw this in qemu-arm version 2.12.0 (Debian 1:2.12+dfsg-3)

  Thanks,
  Guy

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[Bug 1770417] Re: Qemu can not parse long fqdns during drive-mirror

[Thomas Huth]

The QEMU project is currently considering to move its bug tracking to
another system. For this we need to know which bugs are still valid
and which could be closed already. Thus we are setting older bugs to
"Incomplete" now.

If you still think this bug report here is valid, then please switch
the state back to "New" within the next 60 days, otherwise this report
will be marked as "Expired". Or please mark it as "Fix Released" if
the problem has been solved with a newer version of QEMU already.

Thank you and sorry for the inconvenience.


** Changed in: qemu
   Status: New => Incomplete

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Title:
  Qemu can not parse long fqdns during drive-mirror

Status in QEMU:
  Incomplete
Status in qemu package in Ubuntu:
  Confirmed

Bug description:
  During migration of an openstack booted instance, I got the following
  error:

  Apr 12 10:55:22 cmp1 libvirtd[4133]: 2018-04-12 10:55:22.133+:
  4139: error : qemuMonitorJSONCheckError:392 : internal error: unable
  to execute QEMU command 'drive-mirror': error parsing address 'cmp0
  .sandriichenko-deploy-heat-virtual-mcp-pike-ovs-76.bud-mk.local:49153'

  A bit more info in libvirt bug
  https://bugzilla.redhat.com/show_bug.cgi?id=1568939

  To reproduce it with qemu only, I followed the guide at
  https://github.com/qemu/qemu/blob/master/docs/interop/live-block-
  operations.rst#id21. On dest and source compute nodes, I launched an
  instance:

  qemu-system-x86_64 -display none -nodefconfig -M q35 -nodefaults -m
  512 -blockdev node-name=node-
  TargetDisk,driver=qcow2,file.driver=file,file.node-
  name=file,file.filename=./test-instance-mirror.qcow2 -device virtio-
  blk,drive=node-TargetDisk,id=virtio0 -S -monitor stdio -qmp unix
  :./qmp-sock,server,nowait -incoming tcp:localhost:

  Then on dest node I launched nbd server:

  (qemu) nbd_server_start cmp0:49153
  (qemu) nbd_server_add -w node-TargetDisk

  On the source node:

  (qemu) drive_mirror -n  node-TargetDisk 
nbd:cmp0.vdrok-deploy-heat-virtual-mcp-pike-ovs-foobarbuzz.bud-mk.local:49153:exportname=node-TargetDisk
  error parsing address 
'cmp0.vdrok-deploy-heat-virtual-mcp-pike-ovs-foobarbuzz.bud-mk.local:49153'

  When using short host name instead of FQDN address seems to be parsed
  fine:

  (qemu) drive_mirror -n  node-TargetDisk 
nbd:cmp0:49153:exportname=node-TargetDisk qcow2
  Image is not in qcow2 format

  (not sure why it is not a qcow2 format, as I have qcow2 image with raw
  backing file, but this is unrelated)

  QEMU version is 2.11.1 from bionic

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[Bug 1874674] Re: [Feature request] acceptance test class to run user-mode binaries

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/82


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #82
   https://gitlab.com/qemu-project/qemu/-/issues/82

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Title:
  [Feature request] acceptance test class to run user-mode binaries

Status in QEMU:
  Expired

Bug description:
  Currently the acceptance test framework only target system-mode emulation.
  It would be useful to test user-mode too.

  Ref: https://www.mail-archive.com/qemu-devel@nongnu.org/msg626610.html

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[Bug 584155] Re: support horisontal mouse wheel

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/79


** Changed in: qemu
   Status: Confirmed => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #79
   https://gitlab.com/qemu-project/qemu/-/issues/79

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Title:
  support horisontal mouse wheel

Status in QEMU:
  Expired
Status in qemu-kvm package in Debian:
  Confirmed

Bug description:
  Brad Jorsch provided a series of patches to support horisontal mouse 
scrolling in qemu-emulated mouse.
  See Debian bug#579968 -- 
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=579968 and submission to 
qemu-devel list at 
http://www.mail-archive.com/qemu-devel@nongnu.org/msg30991.html .

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[Bug 603878] Re: [Feature request] qemu-img option about recompressing

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/81


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #81
   https://gitlab.com/qemu-project/qemu/-/issues/81

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Title:
  [Feature request] qemu-img option about recompressing

Status in QEMU:
  Expired

Bug description:
  Suppose I have a fresh compressed qcow2 image. After some time the
  data were recorded without compression. I decide to make "QEMU-IMG
  convert" for that image to reduce its size.

  I want a new option, which selects between the two algorithms overdriven 
images:
  1. extract all / compress again when converting images (in the current 
implementation)
  2. compress only uncompressed blocks and just copy the compressed blocks 
without re-compression.

  This option is only needed when converting compressed image to
  compressed and the compression algorithm is the same.

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[Bug 601946] Re: [Feature request] qemu-img multi-threaded compressed image conversion

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/80


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #80
   https://gitlab.com/qemu-project/qemu/-/issues/80

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Title:
  [Feature request] qemu-img multi-threaded compressed image conversion

Status in QEMU:
  Expired

Bug description:
  Feature request:
  qemu-img multi-threaded compressed image conversion

  Suppose I want to convert raw image to compressed qcow2. Multi-
  threaded conversion will be much faster, because bottleneck is
  compressing data.

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Re: [PATCH] tap-bsd: Remove special casing for older OpenBSD releases

[Brad Smith]

On 4/1/2021 3:24 AM, Jason Wang wrote:


在 2021/3/30 上午4:38, Brad Smith 写道:

On 3/28/2021 11:58 PM, Jason Wang wrote:



在 2021/3/29 上午11:03, Brad Smith 写道:

It very much is correct. We don't care about such releases anymore.



So is there a doc/wiki to say Qemu doesn't support those OpenBSD 
release?


The (OpenBSD itself and QEMU) project only makes a concerted effort 
to support
two previous releases. I can't remember where in the QEMU Wiki it is 
mentioned.


Just looking at the Meson requirement alone limits us to the previous 
two releases
never mind older. Even if that wasn't a consideration there would be 
issues with
a few other dependencies like Gtk before going back this far to 
support such old

OpenBSD releases.




Ok. So I've applied this patch.

Thanks



I do not see where.

Re: [PATCH] oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure

[Brad Smith]

ping.

On 4/1/2021 1:34 PM, Brad Smith wrote:

OpenBSD prior to 6.3 required a workaround to utilize fcntl(F_SETFL) on memory
devices.

Since modern verions of OpenBSD that are only officialy supported and buildable
on do not have this issue I am garbage collecting this workaround.


Signed-off-by: Brad Smith 

diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index 36820fec16..7b4bec1402 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -273,17 +273,6 @@ int qemu_try_set_nonblock(int fd)
  return -errno;
  }
  if (fcntl(fd, F_SETFL, f | O_NONBLOCK) == -1) {
-#ifdef __OpenBSD__
-/*
- * Previous to OpenBSD 6.3, fcntl(F_SETFL) is not permitted on
- * memory devices and sets errno to ENODEV.
- * It's OK if we fail to set O_NONBLOCK on devices like /dev/null,
- * because they will never block anyway.
- */
-if (errno == ENODEV) {
-return 0;
-}
-#endif
  return -errno;
  }
  return 0;

Re: [PATCH] tcg/ppc: Fix building with Clang

[Brad Smith]

On 4/22/2021 11:39 AM, Richard Henderson wrote:

On 4/22/21 2:20 AM, Peter Maydell wrote:

On Thu, 22 Apr 2021 at 06:18, Richard Henderson

I'm thinking something like

#if !defined(_CALL_SYSV) && \
  !defined(_CALL_DARWIN) && \
  !defined(_CALL_AIX) && \
  !defined(_CALL_ELF)
# if defined(__APPLE__)
#  define _CALL_DARWIN
# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
#  define _CALL_SYSV
# else
#  error "Unknown ABI"
# endif
#endif


Doesn't this also need some case that handles "64bit ppc clang which 
doesn't

define _CALL_anything" ?


Clang does define _CALL_ELF for ppc64:

 // ABI options.
 if (ABI == "elfv1")
   Builder.defineMacro("_CALL_ELF", "1");
 if (ABI == "elfv2")
   Builder.defineMacro("_CALL_ELF", "2");



Able to spin up a patch that you think is appropriate?

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Guenter Roeck]

On 5/1/21 5:24 PM, Bin Meng wrote:
> On Sun, May 2, 2021 at 7:21 AM Guenter Roeck  wrote:
>>
>> On 5/1/21 2:40 PM, Philippe Mathieu-Daudé wrote:
>>> On 5/1/21 10:12 PM, Guenter Roeck wrote:
 On 4/30/21 9:28 PM, Bin Meng wrote:
> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
>>
>> Hi,
>>
>> On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
>>> From: Bin Meng 
>>>
>>> At present, when booting U-Boot on QEMU sabrelite, we see:
>>>
>>>   Net:   Board Net Initialization Failed
>>>   No ethernet found.
>>>
>>> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
>>> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
>>> board, the Ethernet PHY is at address 6. Adjust this by updating the
>>> "fec-phy-num" property of the fsl_imx6 SoC object.
>>>
>>> With this change, U-Boot sees the PHY but complains MAC address:
>>>
>>>   Net:   using phy at 6
>>>   FEC [PRIME]
>>>   Error: FEC address not set.
>>>
>>> This is due to U-Boot tries to read the MAC address from the fuse,
>>> which QEMU does not have any valid content filled in. However this
>>> does not prevent the Ethernet from working in QEMU. We just need to
>>> set up the MAC address later in the U-Boot command shell, by:
>>>
>>>   => setenv ethaddr 00:11:22:33:44:55
>>>
>>
>> With this patch in place, the standard Ethernet interface no longer 
>> works when
>> booting sabrelite Linux images directly (without u-boot) using the 
>> following
>> qemu command.
>> qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
>> ...
>>
>> The Ethernet interface still instantiates, but packet transfer to the 
>> host
>> no longer works. Reverting this patch fixes the problem for me.
>>
>> Is there a qemu command line parameter that is now necessary to 
>> instantiate
>> the Ethernet interface when booting Linux ?
>
> Enabling "guest_errors" shows that Linux kernel fec driver is trying
> to read PHY at address 0, which is not what we want.
>
> [imx.fec.phy]imx_phy_read: Bad phy num 0
>
> The device tree blob of the sabrelite does not contain a node for the
> ethernet phy specifying phy address, so I suspect Linux kernel driver
> is using default phy address 0 instead.
>
> Could you please test on a real hardware to see what happens?
>

 The problem is that qemu returns 0 when the OS tries to read from a
 non-existing PHY. Linux expects it to return 0x, and believes that
 a PHY is there if 0 is returned.
>>>
>>> Correct.
>>>
>>
>> I'll send a patch. Next question is why the Ethernet interfaces on 
>> mcimx6ul-evk
>> and mcimx7d-sabre don't work. I either get no connectivity at all (similar to
>> the above) or something like
>>
>> fec 2188000.ethernet eth1: Unable to connect to phy
>> ifconfig: SIOCSIFFLAGS: No such device
>>
>> Any idea ?
> 
> I don't see these 2 are supported targets of QEMU:
> https://wiki.qemu.org/Documentation/Platforms/ARM
> 

Reality says otherwise.

$ qemu-system-arm --version
QEMU emulator version 6.0.0 (v6.0.0-25-geac5bb0cc1-dirty)
Copyright (c) 2003-2021 Fabrice Bellard and the QEMU Project developers
$ qemu-system-arm -M ? | grep mcim
mcimx6ul-evk Freescale i.MX6UL Evaluation Kit (Cortex A7)
mcimx7d-sabreFreescale i.MX7 DUAL SABRE (Cortex A7)

Guenter

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Bin Meng]

On Sun, May 2, 2021 at 7:21 AM Guenter Roeck  wrote:
>
> On 5/1/21 2:40 PM, Philippe Mathieu-Daudé wrote:
> > On 5/1/21 10:12 PM, Guenter Roeck wrote:
> >> On 4/30/21 9:28 PM, Bin Meng wrote:
> >>> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
> 
>  Hi,
> 
>  On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
> > From: Bin Meng 
> >
> > At present, when booting U-Boot on QEMU sabrelite, we see:
> >
> >   Net:   Board Net Initialization Failed
> >   No ethernet found.
> >
> > U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
> > U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
> > board, the Ethernet PHY is at address 6. Adjust this by updating the
> > "fec-phy-num" property of the fsl_imx6 SoC object.
> >
> > With this change, U-Boot sees the PHY but complains MAC address:
> >
> >   Net:   using phy at 6
> >   FEC [PRIME]
> >   Error: FEC address not set.
> >
> > This is due to U-Boot tries to read the MAC address from the fuse,
> > which QEMU does not have any valid content filled in. However this
> > does not prevent the Ethernet from working in QEMU. We just need to
> > set up the MAC address later in the U-Boot command shell, by:
> >
> >   => setenv ethaddr 00:11:22:33:44:55
> >
> 
>  With this patch in place, the standard Ethernet interface no longer 
>  works when
>  booting sabrelite Linux images directly (without u-boot) using the 
>  following
>  qemu command.
>  qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
>  ...
> 
>  The Ethernet interface still instantiates, but packet transfer to the 
>  host
>  no longer works. Reverting this patch fixes the problem for me.
> 
>  Is there a qemu command line parameter that is now necessary to 
>  instantiate
>  the Ethernet interface when booting Linux ?
> >>>
> >>> Enabling "guest_errors" shows that Linux kernel fec driver is trying
> >>> to read PHY at address 0, which is not what we want.
> >>>
> >>> [imx.fec.phy]imx_phy_read: Bad phy num 0
> >>>
> >>> The device tree blob of the sabrelite does not contain a node for the
> >>> ethernet phy specifying phy address, so I suspect Linux kernel driver
> >>> is using default phy address 0 instead.
> >>>
> >>> Could you please test on a real hardware to see what happens?
> >>>
> >>
> >> The problem is that qemu returns 0 when the OS tries to read from a
> >> non-existing PHY. Linux expects it to return 0x, and believes that
> >> a PHY is there if 0 is returned.
> >
> > Correct.
> >
>
> I'll send a patch. Next question is why the Ethernet interfaces on 
> mcimx6ul-evk
> and mcimx7d-sabre don't work. I either get no connectivity at all (similar to
> the above) or something like
>
> fec 2188000.ethernet eth1: Unable to connect to phy
> ifconfig: SIOCSIFFLAGS: No such device
>
> Any idea ?

I don't see these 2 are supported targets of QEMU:
https://wiki.qemu.org/Documentation/Platforms/ARM

Regards,
Bin

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Guenter Roeck]

On 5/1/21 2:40 PM, Philippe Mathieu-Daudé wrote:
> On 5/1/21 10:12 PM, Guenter Roeck wrote:
>> On 4/30/21 9:28 PM, Bin Meng wrote:
>>> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:

 Hi,

 On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
> From: Bin Meng 
>
> At present, when booting U-Boot on QEMU sabrelite, we see:
>
>   Net:   Board Net Initialization Failed
>   No ethernet found.
>
> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
> board, the Ethernet PHY is at address 6. Adjust this by updating the
> "fec-phy-num" property of the fsl_imx6 SoC object.
>
> With this change, U-Boot sees the PHY but complains MAC address:
>
>   Net:   using phy at 6
>   FEC [PRIME]
>   Error: FEC address not set.
>
> This is due to U-Boot tries to read the MAC address from the fuse,
> which QEMU does not have any valid content filled in. However this
> does not prevent the Ethernet from working in QEMU. We just need to
> set up the MAC address later in the U-Boot command shell, by:
>
>   => setenv ethaddr 00:11:22:33:44:55
>

 With this patch in place, the standard Ethernet interface no longer works 
 when
 booting sabrelite Linux images directly (without u-boot) using the 
 following
 qemu command.
 qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
 ...

 The Ethernet interface still instantiates, but packet transfer to the host
 no longer works. Reverting this patch fixes the problem for me.

 Is there a qemu command line parameter that is now necessary to instantiate
 the Ethernet interface when booting Linux ?
>>>
>>> Enabling "guest_errors" shows that Linux kernel fec driver is trying
>>> to read PHY at address 0, which is not what we want.
>>>
>>> [imx.fec.phy]imx_phy_read: Bad phy num 0
>>>
>>> The device tree blob of the sabrelite does not contain a node for the
>>> ethernet phy specifying phy address, so I suspect Linux kernel driver
>>> is using default phy address 0 instead.
>>>
>>> Could you please test on a real hardware to see what happens?
>>>
>>
>> The problem is that qemu returns 0 when the OS tries to read from a
>> non-existing PHY. Linux expects it to return 0x, and believes that
>> a PHY is there if 0 is returned.
> 
> Correct.
> 

I'll send a patch. Next question is why the Ethernet interfaces on mcimx6ul-evk
and mcimx7d-sabre don't work. I either get no connectivity at all (similar to
the above) or something like

fec 2188000.ethernet eth1: Unable to connect to phy
ifconfig: SIOCSIFFLAGS: No such device

Any idea ?

Thanks,
Guenter

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Bin Meng]

On Sun, May 2, 2021 at 4:12 AM Guenter Roeck  wrote:
>
> On 4/30/21 9:28 PM, Bin Meng wrote:
> > On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
> >>
> >> Hi,
> >>
> >> On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
> >>> From: Bin Meng 
> >>>
> >>> At present, when booting U-Boot on QEMU sabrelite, we see:
> >>>
> >>>   Net:   Board Net Initialization Failed
> >>>   No ethernet found.
> >>>
> >>> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
> >>> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
> >>> board, the Ethernet PHY is at address 6. Adjust this by updating the
> >>> "fec-phy-num" property of the fsl_imx6 SoC object.
> >>>
> >>> With this change, U-Boot sees the PHY but complains MAC address:
> >>>
> >>>   Net:   using phy at 6
> >>>   FEC [PRIME]
> >>>   Error: FEC address not set.
> >>>
> >>> This is due to U-Boot tries to read the MAC address from the fuse,
> >>> which QEMU does not have any valid content filled in. However this
> >>> does not prevent the Ethernet from working in QEMU. We just need to
> >>> set up the MAC address later in the U-Boot command shell, by:
> >>>
> >>>   => setenv ethaddr 00:11:22:33:44:55
> >>>
> >>
> >> With this patch in place, the standard Ethernet interface no longer works 
> >> when
> >> booting sabrelite Linux images directly (without u-boot) using the 
> >> following
> >> qemu command.
> >> qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
> >> ...
> >>
> >> The Ethernet interface still instantiates, but packet transfer to the host
> >> no longer works. Reverting this patch fixes the problem for me.
> >>
> >> Is there a qemu command line parameter that is now necessary to instantiate
> >> the Ethernet interface when booting Linux ?
> >
> > Enabling "guest_errors" shows that Linux kernel fec driver is trying
> > to read PHY at address 0, which is not what we want.
> >
> > [imx.fec.phy]imx_phy_read: Bad phy num 0
> >
> > The device tree blob of the sabrelite does not contain a node for the
> > ethernet phy specifying phy address, so I suspect Linux kernel driver
> > is using default phy address 0 instead.
> >
> > Could you please test on a real hardware to see what happens?
> >
>
> The problem is that qemu returns 0 when the OS tries to read from a
> non-existing PHY. Linux expects it to return 0x, and believes that
> a PHY is there if 0 is returned. This helps:

Good catch! Please send a patch for this.

>
> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
> index f03450c028..3c90c38e26 100644
> --- a/hw/net/imx_fec.c
> +++ b/hw/net/imx_fec.c
> @@ -285,7 +285,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
>  if (phy != s->phy_num) {
>  qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
>TYPE_IMX_FEC, __func__, phy);
> -return 0;
> +return 0x;
>  }
>
> Note that this is not really a guest error; any OS can and likely
> will scan the MII bus for connected phy chips.

Agree.

Regards,
Bin

[PATCH v5 10/10] qtest: Do not restrict bios-tables-test to Aarch64 hosts anymore

[Philippe Mathieu-Daudé]

Since commit 82bf7ae84ce ("target/arm: Remove KVM support for
32-bit Arm hosts") we can remove the comment / check added in
commit ab6b6a4 and directly run the bios-tables-test.

Reviewed-by: Eric Blake 
Reviewed-by: Alex Bennée 
Tested-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/meson.build | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 0c767389217..46de073d155 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -175,14 +175,13 @@
'boot-serial-test',
'hexloader-test']
 
-# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test 
unconditional
 qtests_aarch64 = \
-  (cpu != 'arm' ? ['bios-tables-test'] : []) + 
 \
   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? 
['tpm-tis-device-test'] : []) +\
   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? 
['tpm-tis-device-swtpm-test'] : []) +  \
   ['arm-cpu-features',
'numa-test',
'boot-serial-test',
+   'bios-tables-test',
'xlnx-can-test',
'migration-test']
 
-- 
2.26.3

[PATCH v5 09/10] qtest/migration-test: Skip tests if KVM not builtin on s390x/ppc64

[Philippe Mathieu-Daudé]

We might have a s390x/ppc64 QEMU binary built without the KVM
accelerator (configured with --disable-kvm).
Checking for /dev/kvm accessibility isn't enough, also check for the
accelerator in the binary.

Reviewed-by: David Gibson 
Reviewed-by: Greg Kurz 
Reviewed-by: Cornelia Huck 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/migration-test.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 3a711bb4929..c32a2aa30a2 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -1408,7 +1408,7 @@ int main(int argc, char **argv)
  */
 if (g_str_equal(qtest_get_arch(), "ppc64") &&
 (access("/sys/module/kvm_hv", F_OK) ||
- access("/dev/kvm", R_OK | W_OK))) {
+ access("/dev/kvm", R_OK | W_OK) || !qtest_has_accel("kvm"))) {
 g_test_message("Skipping test: kvm_hv not available");
 return g_test_run();
 }
@@ -1419,7 +1419,7 @@ int main(int argc, char **argv)
  */
 if (g_str_equal(qtest_get_arch(), "s390x")) {
 #if defined(HOST_S390X)
-if (access("/dev/kvm", R_OK | W_OK)) {
+if (access("/dev/kvm", R_OK | W_OK) || !qtest_has_accel("kvm")) {
 g_test_message("Skipping test: kvm not available");
 return g_test_run();
 }
-- 
2.26.3

[PATCH v5 07/10] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for TCG

[Philippe Mathieu-Daudé]

Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, only run these tests if TCG
is built into the QEMU binary.

Suggested-by: Andrew Jones 
Reviewed-by: Andrew Jones 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/arm-cpu-features.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index b1d406542f7..0d9145dd168 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -20,7 +20,7 @@
  */
 #define SVE_MAX_VQ 16
 
-#define MACHINE "-machine virt,gic-version=max -accel tcg "
+#define MACHINE_TCG "-machine virt,gic-version=max -accel tcg "
 #define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
 "  'arguments': { 'type': 'full', "
@@ -337,7 +337,7 @@ static void sve_tests_sve_max_vq_8(const void *data)
 {
 QTestState *qts;
 
-qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
+qts = qtest_init(MACHINE_TCG "-cpu max,sve-max-vq=8");
 
 assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
 
@@ -372,7 +372,7 @@ static void sve_tests_sve_off(const void *data)
 {
 QTestState *qts;
 
-qts = qtest_init(MACHINE "-cpu max,sve=off");
+qts = qtest_init(MACHINE_TCG "-cpu max,sve=off");
 
 /* SVE is off, so the map should be empty. */
 assert_sve_vls(qts, "max", 0, NULL);
@@ -428,7 +428,7 @@ static void test_query_cpu_model_expansion(const void *data)
 {
 QTestState *qts;
 
-qts = qtest_init(MACHINE "-cpu max");
+qts = qtest_init(MACHINE_TCG "-cpu max");
 
 /* Test common query-cpu-model-expansion input validation */
 assert_type_full(qts);
@@ -593,8 +593,10 @@ int main(int argc, char **argv)
 {
 g_test_init(&argc, &argv, NULL);
 
-qtest_add_data_func("/arm/query-cpu-model-expansion",
-NULL, test_query_cpu_model_expansion);
+if (qtest_has_accel("tcg")) {
+qtest_add_data_func("/arm/query-cpu-model-expansion",
+NULL, test_query_cpu_model_expansion);
+}
 
 /*
  * For now we only run KVM specific tests with AArch64 QEMU in
@@ -608,7 +610,7 @@ int main(int argc, char **argv)
 NULL, sve_tests_sve_off_kvm);
 }
 
-if (g_str_equal(qtest_get_arch(), "aarch64")) {
+if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("tcg")) {
 qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
 NULL, sve_tests_sve_max_vq_8);
 qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
-- 
2.26.3

[PATCH v5 08/10] qtest/bios-tables-test: Make test build-independent from accelerator

[Philippe Mathieu-Daudé]

Now than we can probe if the TCG accelerator is available
at runtime with a QMP command, do it once at the beginning
and only register the tests we can run.
We can then replace the #ifdef'ry by an assertion.

Reviewed-by: Eric Blake 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/bios-tables-test.c | 99 ++
 1 file changed, 52 insertions(+), 47 deletions(-)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 156d4174aa3..a4c7bddf6f3 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -97,6 +97,7 @@ typedef struct {
 QTestState *qts;
 } test_data;
 
+static bool tcg_accel_available;
 static char disk[] = "tests/acpi-test-disk-XX";
 static const char *data_dir = "tests/data/acpi";
 #ifdef CONFIG_IASL
@@ -718,15 +719,11 @@ static void test_acpi_one(const char *params, test_data 
*data)
 char *args;
 bool use_uefi = data->uefi_fl1 && data->uefi_fl2;
 
-#ifndef CONFIG_TCG
-if (data->tcg_only) {
-g_test_skip("TCG disabled, skipping ACPI tcg_only test");
-return;
-}
-#endif /* CONFIG_TCG */
+assert(!data->tcg_only || tcg_accel_available);
 
 args = test_acpi_create_args(data, params, use_uefi);
 data->qts = qtest_init(args);
+
 test_acpi_load_tables(data, use_uefi);
 
 if (getenv(ACPI_REBUILD_EXPECTED_AML)) {
@@ -1504,6 +1501,8 @@ int main(int argc, char *argv[])
 const char *arch = qtest_get_arch();
 int ret;
 
+tcg_accel_available = qtest_has_accel("tcg");
+
 g_test_init(&argc, &argv, NULL);
 
 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
@@ -1512,56 +1511,62 @@ int main(int argc, char *argv[])
 return ret;
 }
 qtest_add_func("acpi/q35/oem-fields", test_acpi_oem_fields_q35);
-qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis);
-qtest_add_func("acpi/piix4", test_acpi_piix4_tcg);
 qtest_add_func("acpi/oem-fields", test_acpi_oem_fields_pc);
-qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge);
+qtest_add_func("acpi/microvm/oem-fields", 
test_acpi_oem_fields_microvm);
 qtest_add_func("acpi/piix4/pci-hotplug/no_root_hotplug",
test_acpi_piix4_no_root_hotplug);
 qtest_add_func("acpi/piix4/pci-hotplug/no_bridge_hotplug",
test_acpi_piix4_no_bridge_hotplug);
 qtest_add_func("acpi/piix4/pci-hotplug/off",
test_acpi_piix4_no_acpi_pci_hotplug);
-qtest_add_func("acpi/q35", test_acpi_q35_tcg);
-qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
-qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
-qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi);
-qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi);
-qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);
-qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp);
-qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp);
-qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp);
-qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem);
-qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem);
-qtest_add_func("acpi/piix4/nosmm", test_acpi_piix4_tcg_nosmm);
-qtest_add_func("acpi/piix4/smm-compat",
-   test_acpi_piix4_tcg_smm_compat);
-qtest_add_func("acpi/piix4/smm-compat-nosmm",
-   test_acpi_piix4_tcg_smm_compat_nosmm);
-qtest_add_func("acpi/piix4/nohpet", test_acpi_piix4_tcg_nohpet);
-qtest_add_func("acpi/q35/nosmm", test_acpi_q35_tcg_nosmm);
-qtest_add_func("acpi/q35/smm-compat",
-   test_acpi_q35_tcg_smm_compat);
-qtest_add_func("acpi/q35/smm-compat-nosmm",
-   test_acpi_q35_tcg_smm_compat_nosmm);
-qtest_add_func("acpi/q35/nohpet", test_acpi_q35_tcg_nohpet);
-qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm);
-qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
-qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
-qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
-qtest_add_func("acpi/microvm", test_acpi_microvm_tcg);
-qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg);
-qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg);
-qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2_tcg);
-qtest_add_func("acpi/microvm/oem-fields", 
test_acpi_oem_fields_microvm);
-if (strcmp(arch, "x86_64") == 0) {
-qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg);
+if (tcg_accel_available) {
+qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis);
+qtest_add_func(

[PATCH v5 03/10] tests/qtest: Add qtest_has_accel() method

[Philippe Mathieu-Daudé]

Introduce the qtest_has_accel() method which allows a runtime
query on whether a QEMU instance has an accelerator built-in.

Reviewed-by: Eric Blake 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/libqos/libqtest.h |  8 
 tests/qtest/libqtest.c| 29 +
 2 files changed, 37 insertions(+)

diff --git a/tests/qtest/libqos/libqtest.h b/tests/qtest/libqos/libqtest.h
index a68dcd79d44..d80c618c18d 100644
--- a/tests/qtest/libqos/libqtest.h
+++ b/tests/qtest/libqos/libqtest.h
@@ -763,6 +763,14 @@ void qmp_expect_error_and_unref(QDict *rsp, const char 
*class);
  */
 bool qtest_probe_child(QTestState *s);
 
+/**
+ * qtest_has_accel:
+ * @accel_name: Accelerator name to check for.
+ *
+ * Returns: true if the accelerator is built in.
+ */
+bool qtest_has_accel(const char *accel_name);
+
 /**
  * qtest_set_expected_status:
  * @s: QTestState instance to operate on.
diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
index 71e359efcd3..2156b7e3972 100644
--- a/tests/qtest/libqtest.c
+++ b/tests/qtest/libqtest.c
@@ -393,6 +393,35 @@ QTestState *qtest_init_with_serial(const char *extra_args, 
int *sock_fd)
 return qts;
 }
 
+bool qtest_has_accel(const char *accel_name)
+{
+bool has_accel = false;
+QDict *response;
+QList *accels;
+QListEntry *accel;
+QTestState *qts;
+
+qts = qtest_initf("-accel qtest -machine none");
+response = qtest_qmp(qts, "{'execute': 'query-accels'}");
+accels = qdict_get_qlist(response, "return");
+
+QLIST_FOREACH_ENTRY(accels, accel) {
+QDict *accel_dict = qobject_to(QDict, qlist_entry_obj(accel));
+const char *name = qdict_get_str(accel_dict, "name");
+
+if (g_str_equal(name, accel_name)) {
+has_accel = true;
+break;
+}
+}
+qobject_unref(response);
+
+qtest_quit(qts);
+
+return has_accel;
+}
+
+
 void qtest_quit(QTestState *s)
 {
 qtest_remove_abrt_handler(s);
-- 
2.26.3

[PATCH v5 05/10] qtest/arm-cpu-features: Restrict sve_tests_sve_off_kvm test to KVM

[Philippe Mathieu-Daudé]

The sve_tests_sve_off_kvm() test is KVM specific.
Only run it if KVM is available.

Suggested-by: Andrew Jones 
Reviewed-by: Andrew Jones 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/arm-cpu-features.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 7f4b2521277..66300c3bc20 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -604,6 +604,8 @@ int main(int argc, char **argv)
 if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
 qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
 NULL, test_query_cpu_model_expansion_kvm);
+qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+NULL, sve_tests_sve_off_kvm);
 }
 
 if (g_str_equal(qtest_get_arch(), "aarch64")) {
@@ -611,8 +613,6 @@ int main(int argc, char **argv)
 NULL, sve_tests_sve_max_vq_8);
 qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
 NULL, sve_tests_sve_off);
-qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
-NULL, sve_tests_sve_off_kvm);
 }
 
 return g_test_run();
-- 
2.26.3

[PATCH v5 06/10] qtest/arm-cpu-features: Remove TCG fallback to KVM specific tests

[Philippe Mathieu-Daudé]

sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm()
tests are now only being run if KVM is available. Drop the TCG
fallback.

Suggested-by: Andrew Jones 
Reviewed-by: Andrew Jones 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/arm-cpu-features.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 66300c3bc20..b1d406542f7 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -21,7 +21,7 @@
 #define SVE_MAX_VQ 16
 
 #define MACHINE "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
 "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
-- 
2.26.3

[PATCH v5 02/10] accel: Introduce 'query-accels' QMP command

[Philippe Mathieu-Daudé]

Introduce the 'query-accels' QMP command which returns a list
of built-in accelerator names.

- Accelerator is a QAPI enum of all existing accelerators,

- AcceleratorInfo is a QAPI structure providing accelerator
  specific information. Currently the common structure base
  provides the name of the accelerator, while the specific
  part is empty, but each accelerator can expand it.

- 'query-accels' QMP command returns a list of @AcceleratorInfo

For example on a KVM-only build we get:

{ "execute": "query-accels" }
{
"return": [
{
"name": "qtest"
},
{
"name": "kvm"
}
]
}

Note that we can't make the enum values or union branches conditional
because of target-specific poisoning of accelerator definitions.

Reviewed-by: Eric Blake 
Reviewed-by: Alex Bennée 
Tested-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 qapi/machine.json | 47 +
 accel/accel-qmp.c | 49 +++
 accel/meson.build |  2 +-
 3 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 accel/accel-qmp.c

diff --git a/qapi/machine.json b/qapi/machine.json
index 6e90d463fc9..6dd3b765248 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1274,3 +1274,50 @@
 ##
 { 'event': 'MEM_UNPLUG_ERROR',
   'data': { 'device': 'str', 'msg': 'str' } }
+
+##
+# @Accelerator:
+#
+# An enumeration of accelerator names.
+#
+# Since: 6.1
+##
+{ 'enum': 'Accelerator',
+  'data': [ 'hax', 'hvf', 'kvm', 'qtest', 'tcg', 'whpx', 'xen' ] }
+
+##
+# @AcceleratorInfo:
+#
+# Accelerator information.
+#
+# @name: The accelerator name.
+#
+# Since: 6.1
+##
+{ 'struct': 'AcceleratorInfo',
+  'data': { 'name': 'Accelerator' } }
+
+##
+# @query-accels:
+#
+# Get a list of AcceleratorInfo for all built-in accelerators.
+#
+# Returns: a list of @AcceleratorInfo describing each accelerator.
+#
+# Since: 6.1
+#
+# Example:
+#
+# -> { "execute": "query-accels" }
+# <- { "return": [
+#{
+#"name": "qtest"
+#},
+#{
+#"name": "kvm"
+#}
+#] }
+#
+##
+{ 'command': 'query-accels',
+  'returns': ['AcceleratorInfo'] }
diff --git a/accel/accel-qmp.c b/accel/accel-qmp.c
new file mode 100644
index 000..426737b3f9a
--- /dev/null
+++ b/accel/accel-qmp.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU accelerators, QMP commands
+ *
+ * Copyright (c) 2021 Red Hat Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/qapi-commands-machine.h"
+
+static const bool accel_builtin_list[ACCELERATOR__MAX] = {
+[ACCELERATOR_QTEST] = true,
+#ifdef CONFIG_TCG
+[ACCELERATOR_TCG] = true,
+#endif
+#ifdef CONFIG_KVM
+[ACCELERATOR_KVM] = true,
+#endif
+#ifdef CONFIG_HAX
+[ACCELERATOR_HAX] = true,
+#endif
+#ifdef CONFIG_HVF
+[ACCELERATOR_HVF] = true,
+#endif
+#ifdef CONFIG_WHPX
+[ACCELERATOR_WHPX] = true,
+#endif
+#ifdef CONFIG_XEN_BACKEND
+[ACCELERATOR_XEN] = true,
+#endif
+};
+
+AcceleratorInfoList *qmp_query_accels(Error **errp)
+{
+AcceleratorInfoList *list = NULL, **tail = &list;
+
+for (Accelerator accel = 0; accel < ACCELERATOR__MAX; accel++) {
+if (accel_builtin_list[accel]) {
+AcceleratorInfo *info = g_new0(AcceleratorInfo, 1);
+
+info->name = accel;
+
+QAPI_LIST_APPEND(tail, info);
+}
+}
+
+return list;
+}
diff --git a/accel/meson.build b/accel/meson.build
index b44ba30c864..7a48f6d568d 100644
--- a/accel/meson.build
+++ b/accel/meson.build
@@ -1,4 +1,4 @@
-specific_ss.add(files('accel-common.c'))
+specific_ss.add(files('accel-common.c', 'accel-qmp.c'))
 softmmu_ss.add(files('accel-softmmu.c'))
 user_ss.add(files('accel-user.c'))
 
-- 
2.26.3

[PATCH v5 04/10] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for KVM

[Philippe Mathieu-Daudé]

Use the recently added generic qtest_has_accel() method to
check if KVM is available.

Suggested-by: Claudio Fontana 
Reviewed-by: Andrew Jones 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/qtest/arm-cpu-features.c | 25 +
 1 file changed, 1 insertion(+), 24 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 8252b85bb85..7f4b2521277 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -26,21 +26,6 @@
 "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
 
-static bool kvm_enabled(QTestState *qts)
-{
-QDict *resp, *qdict;
-bool enabled;
-
-resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
-g_assert(qdict_haskey(resp, "return"));
-qdict = qdict_get_qdict(resp, "return");
-g_assert(qdict_haskey(qdict, "enabled"));
-enabled = qdict_get_bool(qdict, "enabled");
-qobject_unref(resp);
-
-return enabled;
-}
-
 static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
 {
 return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
@@ -493,14 +478,6 @@ static void test_query_cpu_model_expansion_kvm(const void 
*data)
 
 qts = qtest_init(MACHINE_KVM "-cpu max");
 
-/*
- * These tests target the 'host' CPU type, so KVM must be enabled.
- */
-if (!kvm_enabled(qts)) {
-qtest_quit(qts);
-return;
-}
-
 /* Enabling and disabling kvm-no-adjvtime should always work. */
 assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime");
 assert_set_feature(qts, "host", "kvm-no-adjvtime", true);
@@ -624,7 +601,7 @@ int main(int argc, char **argv)
  * order avoid attempting to run an AArch32 QEMU with KVM on
  * AArch64 hosts. That won't work and isn't easy to detect.
  */
-if (g_str_equal(qtest_get_arch(), "aarch64")) {
+if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
 qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
 NULL, test_query_cpu_model_expansion_kvm);
 }
-- 
2.26.3

[PATCH v5 01/10] MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section

[Philippe Mathieu-Daudé]

We want the ARM maintainers and the qemu-arm@ list to be
notified when this file is modified. Add an entry to the
'ARM TCG CPUs' section in the MAINTAINERS file.

Acked-by: Andrew Jones 
Reviewed-by: Thomas Huth 
Reviewed-by: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4c05ff8bbab..5f1f59f9b3c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -156,6 +156,7 @@ S: Maintained
 F: target/arm/
 F: tests/tcg/arm/
 F: tests/tcg/aarch64/
+F: tests/qtest/arm-cpu-features.c
 F: hw/arm/
 F: hw/cpu/a*mpcore.c
 F: include/hw/cpu/a*mpcore.h
-- 
2.26.3

[PATCH v5 00/10] qtests: Check accelerator available at runtime via QMP 'query-accels'

[Philippe Mathieu-Daudé]

Series fully reviewed.

Hi,

This series aims at having accelerator-independent qtests
by querying a QEMU instance at runtime to check the list
of built-in accelerators.

First we add the 'query-accels' QMP command,
then we add the qtest_has_accel() method to libqtest,
finally we use this new method to allow running
bios-tables-test on KVM-only builds.

Since v5:
- Removed patch 10 (Markus, patch justification not clear)
  'qtest/qmp-cmd-test: Make test build-independent from accelerator'
- Removed patch 12 (Alex, icount / record/replay issue)
  'tests/meson: Only build softfloat objects if TCG is selected (again)'
- Sorted @Accelerator QAPI enum (Eric)
- Added R-b/T-b

Since v4:
- Added Markus review comments
- Added R-b/A-b tags

Since v3:
- Addressed Markus & Drew review comments
- Added qtest/migration-test patch

Since v2:
- Addressed Eric & Paolo review comments

Since v1:
- kept over-engineered union (I don't how to do simple enum)
- dropped arm-cpu-features patches for now
- fixed typos (Eric)
- rename qtest_has_accel (Thomas)
- probe accel with machine none previous qtest (Paolo)
- iterate over QAPI enum (Markus)

Eric's suggestion of conditional QAPI didn't worked out,
as accelerator definitions are poisoned.

Phil.

Philippe Mathieu-Daudé (10):
  MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section
  accel: Introduce 'query-accels' QMP command
  tests/qtest: Add qtest_has_accel() method
  qtest/arm-cpu-features: Use generic qtest_has_accel() to check for KVM
  qtest/arm-cpu-features: Restrict sve_tests_sve_off_kvm test to KVM
  qtest/arm-cpu-features: Remove TCG fallback to KVM specific tests
  qtest/arm-cpu-features: Use generic qtest_has_accel() to check for TCG
  qtest/bios-tables-test: Make test build-independent from accelerator
  qtest/migration-test: Skip tests if KVM not builtin on s390x/ppc64
  qtest: Do not restrict bios-tables-test to Aarch64 hosts anymore

 qapi/machine.json  | 47 
 tests/qtest/libqos/libqtest.h  |  8 +++
 accel/accel-qmp.c  | 49 +
 tests/qtest/arm-cpu-features.c | 55 ++-
 tests/qtest/bios-tables-test.c | 99 ++
 tests/qtest/libqtest.c | 29 ++
 tests/qtest/migration-test.c   |  4 +-
 MAINTAINERS|  1 +
 accel/meson.build  |  2 +-
 tests/qtest/meson.build|  3 +-
 10 files changed, 207 insertions(+), 90 deletions(-)
 create mode 100644 accel/accel-qmp.c

-- 
2.26.3

Re: [PULL 00/31] target/hexagon patch queue

[Richard Henderson]

On 5/1/21 1:40 PM, Peter Maydell wrote:

Build failure on the gitlab CI "clang-user" job:
https://gitlab.com/qemu-project/qemu/-/jobs/1229108656

../target/hexagon/genptr.c:31:20: error: unused function
'gen_read_reg' [-Werror,-Wunused-function]
static inline TCGv gen_read_reg(TCGv result, int num)
^
../target/hexagon/genptr.c:322:20: error: unused function
'gen_set_byte' [-Werror,-Wunused-function]
static inline void gen_set_byte(int N, TCGv result, TCGv src)
^

(this is clang being stricter than gcc about unused static
inline functions again.)


Dangit, I merged Taylor's patch to fix this Friday and then tagged from the 
wrong machine today.



r~

Re: [PATCH v4 02/12] accel: Introduce 'query-accels' QMP command

[Philippe Mathieu-Daudé]

On 4/30/21 9:03 PM, Eric Blake wrote:
> On 4/15/21 11:32 AM, Philippe Mathieu-Daudé wrote:
>> Introduce the 'query-accels' QMP command which returns a list
>> of built-in accelerator names.
>>
>> - Accelerator is a QAPI enum of all existing accelerators,
>>
>> - AcceleratorInfo is a QAPI structure providing accelerator
>>   specific information. Currently the common structure base
>>   provides the name of the accelerator, while the specific
>>   part is empty, but each accelerator can expand it.
>>
>> - 'query-accels' QMP command returns a list of @AcceleratorInfo
>>
>> For example on a KVM-only build we get:
>>
>> { "execute": "query-accels" }
>> {
>> "return": [
>> {
>> "name": "qtest"
>> },
>> {
>> "name": "kvm"
>> }
>> ]
>> }
>>
>> Note that we can't make the enum values or union branches conditional
>> because of target-specific poisoning of accelerator definitions.
>>
>> Reviewed-by: Eric Blake 
>> Signed-off-by: Philippe Mathieu-Daudé 
>> ---
>> Since v3: Simplify over-engineered AcceleratorInfo (Markus, kept Eric R-b)
>> Since v2: @since 6.0 -> 6.1, added note (Eric)
>> Since v1: 'type' -> 'name' in comments
> 
>> +++ b/qapi/machine.json
>> @@ -1274,3 +1274,50 @@
>>  ##
>>  { 'event': 'MEM_UNPLUG_ERROR',
>>'data': { 'device': 'str', 'msg': 'str' } }
>> +
>> +##
>> +# @Accelerator:
>> +#
>> +# An enumeration of accelerator names.
>> +#
>> +# Since: 6.1
>> +##
>> +{ 'enum': 'Accelerator',
>> +  'data': [ 'qtest', 'tcg', 'kvm', 'hax', 'hvf', 'whpx', 'xen' ] }
> 
> There's no requirement for enums to be in any order, although if the
> list is likely to get larger over time, lexicographic order makes it
> easier to know where to insert new entries.  Up to you whether it is
> worth sorting, and your decision does not invalidate my R-b.

OK will do, thanks!

[PATCH v2 2/2] hw/rtc/mc146818rtc: Convert to 3-phase reset (Resettable interface)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

TYPE_MC146818_RTC is an ISA device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).

We have 2 reset() methods: a generic one and the qdev one.
Merge them into a reset_enter handler (keeping the IRQ lowering
to a reset_exit one), and remove the qemu_register_reset() call.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/rtc/mc146818rtc.c | 42 ++
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index 5d0fcacd0c0..6bf075ba8ce 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -872,22 +872,6 @@ static void rtc_notify_suspend(Notifier *notifier, void 
*data)
 rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 }
 
-static void rtc_reset(void *opaque)
-{
-RTCState *s = opaque;
-
-s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
-s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
-check_update_timer(s);
-
-qemu_irq_lower(s->irq);
-
-if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
-s->irq_coalesced = 0;
-s->irq_reinject_on_ack_count = 0;
-}
-}
-
 static const MemoryRegionOps cmos_ops = {
 .read = cmos_ioport_read,
 .write = cmos_ioport_write,
@@ -962,7 +946,6 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
 memory_region_add_coalescing(&s->coalesced_io, 0, 1);
 
 qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3);
-qemu_register_reset(rtc_reset, s);
 
 object_property_add_tm(OBJECT(s), "date", rtc_get_date);
 
@@ -998,15 +981,32 @@ static Property mc146818rtc_properties[] = {
 DEFINE_PROP_END_OF_LIST(),
 };
 
-static void rtc_resetdev(DeviceState *d)
+static void rtc_reset_enter(Object *obj, ResetType type)
 {
-RTCState *s = MC146818_RTC(d);
+RTCState *s = MC146818_RTC(obj);
 
 /* Reason: VM do suspend self will set 0xfe
  * Reset any values other than 0xfe(Guest suspend case) */
 if (s->cmos_data[0x0f] != 0xfe) {
 s->cmos_data[0x0f] = 0x00;
 }
+
+s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
+s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
+check_update_timer(s);
+
+
+if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
+s->irq_coalesced = 0;
+s->irq_reinject_on_ack_count = 0;
+}
+}
+
+static void rtc_reset_exit(Object *obj)
+{
+RTCState *s = MC146818_RTC(obj);
+
+qemu_irq_lower(s->irq);
 }
 
 static void rtc_build_aml(ISADevice *isadev, Aml *scope)
@@ -1033,11 +1033,13 @@ static void rtc_build_aml(ISADevice *isadev, Aml *scope)
 static void rtc_class_initfn(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
 
 dc->realize = rtc_realizefn;
-dc->reset = rtc_resetdev;
 dc->vmsd = &vmstate_rtc;
+rc->phases.enter = rtc_reset_enter;
+rc->phases.exit = rtc_reset_exit;
 isa->build_aml = rtc_build_aml;
 device_class_set_props(dc, mc146818rtc_properties);
 }
-- 
2.26.3

[PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé 

TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).

Convert the generic reset to a enter/exit resettable ones, and
remove the qemu_register_reset() call.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/timer/etraxfs_timer.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
index 5379006086f..7dd3daf6771 100644
--- a/hw/timer/etraxfs_timer.c
+++ b/hw/timer/etraxfs_timer.c
@@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
 }
 };
 
-static void etraxfs_timer_reset(void *opaque)
+static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
 {
-ETRAXTimerState *t = opaque;
+ETRAXTimerState *t = ETRAX_TIMER(obj);
 
 ptimer_transaction_begin(t->ptimer_t0);
 ptimer_stop(t->ptimer_t0);
@@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
 t->rw_wd_ctrl = 0;
 t->r_intr = 0;
 t->rw_intr_mask = 0;
+}
+
+static void etraxfs_timer_reset_exit(Object *obj)
+{
+ETRAXTimerState *t = ETRAX_TIMER(obj);
+
 qemu_irq_lower(t->irq);
 }
 
@@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, Error 
**errp)
 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
   "etraxfs-timer", 0x5c);
 sysbus_init_mmio(sbd, &t->mmio);
-qemu_register_reset(etraxfs_timer_reset, t);
 }
 
 static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+ResettableClass *rc = RESETTABLE_CLASS(klass);
 
 dc->realize = etraxfs_timer_realize;
+rc->phases.enter = etraxfs_timer_reset_enter;
+rc->phases.exit = etraxfs_timer_reset_exit;
 }
 
 static const TypeInfo etraxfs_timer_info = {
-- 
2.26.3

[PATCH v2 0/2] hw: Convert mc146818rtc & etraxfs_timer to 3-phase reset interface

[Philippe Mathieu-Daudé]

Remove qemu_register_reset() when a qdev type has a qbus parent,
implementing the 3-phase Resettable interface.

Since v1:
- Use 3-phase reset interface instead of qdev one (Laurent)

Supersedes: <20210423233652.3042941-1-f4...@amsat.org>

Philippe Mathieu-Daudé (2):
  hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable
interface)
  hw/rtc/mc146818rtc: Convert to 3-phase reset (Resettable interface)

 hw/rtc/mc146818rtc.c | 42 +---
 hw/timer/etraxfs_timer.c | 14 +++---
 2 files changed, 33 insertions(+), 23 deletions(-)

-- 
2.26.3

Re: [PATCH 1/2] hw/timer/etraxfs_timer: Qdev'ify reset()

[Philippe Mathieu-Daudé]

On 5/1/21 6:46 PM, Laurent Vivier wrote:
> Le 24/04/2021 à 01:36, Philippe Mathieu-Daudé a écrit :
>> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
>> handler is called automatically when its qbus parent is reset.
>> Convert the generic reset to a qdev one, and remove the
>> qemu_register_reset() call.
>>
>> Signed-off-by: Philippe Mathieu-Daudé 
>> ---
>>  hw/timer/etraxfs_timer.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
>> index 5379006086f..3cfab3e3284 100644
>> --- a/hw/timer/etraxfs_timer.c
>> +++ b/hw/timer/etraxfs_timer.c
>> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>>  }
>>  };
>>  
>> -static void etraxfs_timer_reset(void *opaque)
>> +static void etraxfs_timer_reset(DeviceState *dev)
>>  {
>> -ETRAXTimerState *t = opaque;
>> +ETRAXTimerState *t = ETRAX_TIMER(dev);
>>  
>>  ptimer_transaction_begin(t->ptimer_t0);
>>  ptimer_stop(t->ptimer_t0);
>> @@ -343,7 +343,6 @@ static void etraxfs_timer_realize(DeviceState *dev, 
>> Error **errp)
>>  memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>>"etraxfs-timer", 0x5c);
>>  sysbus_init_mmio(sbd, &t->mmio);
>> -qemu_register_reset(etraxfs_timer_reset, t);
>>  }
>>  
>>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
>> @@ -351,6 +350,7 @@ static void etraxfs_timer_class_init(ObjectClass *klass, 
>> void *data)
>>  DeviceClass *dc = DEVICE_CLASS(klass);
>>  
>>  dc->realize = etraxfs_timer_realize;
>> +dc->reset = etraxfs_timer_reset;
>>  }
>>  
>>  static const TypeInfo etraxfs_timer_info = {
>>
> 
> Reviewed-by: Laurent Vivier 
> 
> But according to the comment in DeviceClass, we should use the resettable 
> interface now:
> 
> docs/devel/reset.rst

Eh... As a first step, I think we gain in removing the
qemu_register_reset() call.

It seems overkill to use the 3-state reset interface,
but if it is deprecated, then OK.

Thanks for reviewing,

Phil.

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Philippe Mathieu-Daudé]

On 5/1/21 10:12 PM, Guenter Roeck wrote:
> On 4/30/21 9:28 PM, Bin Meng wrote:
>> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
>>>
>>> Hi,
>>>
>>> On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
 From: Bin Meng 

 At present, when booting U-Boot on QEMU sabrelite, we see:

   Net:   Board Net Initialization Failed
   No ethernet found.

 U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
 U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
 board, the Ethernet PHY is at address 6. Adjust this by updating the
 "fec-phy-num" property of the fsl_imx6 SoC object.

 With this change, U-Boot sees the PHY but complains MAC address:

   Net:   using phy at 6
   FEC [PRIME]
   Error: FEC address not set.

 This is due to U-Boot tries to read the MAC address from the fuse,
 which QEMU does not have any valid content filled in. However this
 does not prevent the Ethernet from working in QEMU. We just need to
 set up the MAC address later in the U-Boot command shell, by:

   => setenv ethaddr 00:11:22:33:44:55

>>>
>>> With this patch in place, the standard Ethernet interface no longer works 
>>> when
>>> booting sabrelite Linux images directly (without u-boot) using the following
>>> qemu command.
>>> qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
>>> ...
>>>
>>> The Ethernet interface still instantiates, but packet transfer to the host
>>> no longer works. Reverting this patch fixes the problem for me.
>>>
>>> Is there a qemu command line parameter that is now necessary to instantiate
>>> the Ethernet interface when booting Linux ?
>>
>> Enabling "guest_errors" shows that Linux kernel fec driver is trying
>> to read PHY at address 0, which is not what we want.
>>
>> [imx.fec.phy]imx_phy_read: Bad phy num 0
>>
>> The device tree blob of the sabrelite does not contain a node for the
>> ethernet phy specifying phy address, so I suspect Linux kernel driver
>> is using default phy address 0 instead.
>>
>> Could you please test on a real hardware to see what happens?
>>
> 
> The problem is that qemu returns 0 when the OS tries to read from a
> non-existing PHY. Linux expects it to return 0x, and believes that
> a PHY is there if 0 is returned.

Correct.

> This helps:
> 
> diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
> index f03450c028..3c90c38e26 100644
> --- a/hw/net/imx_fec.c
> +++ b/hw/net/imx_fec.c
> @@ -285,7 +285,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
>  if (phy != s->phy_num) {
>  qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
>TYPE_IMX_FEC, __func__, phy);
> -return 0;
> +return 0x;
>  }
> 
> Note that this is not really a guest error; any OS can and likely
> will scan the MII bus for connected phy chips.

Correct. This should be a trace event instead.

Re: [PULL 00/31] target/hexagon patch queue

[Peter Maydell]

On Sat, 1 May 2021 at 19:43, Richard Henderson
 wrote:
>
> The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' 
> into staging (2021-04-30 16:02:00 +0100)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-hex-20210501
>
> for you to fetch changes up to 26f7c044ad234c3dfa7ca2ddf047a71d815e66dc:
>
>   Hexagon (target/hexagon) CABAC decode bin (2021-05-01 08:31:43 -0700)
>
> 
> Minor cleanups.
> Finish the rest of the hexagon integer instructions.
>
> 

Build failure on the gitlab CI "clang-user" job:
https://gitlab.com/qemu-project/qemu/-/jobs/1229108656

../target/hexagon/genptr.c:31:20: error: unused function
'gen_read_reg' [-Werror,-Wunused-function]
static inline TCGv gen_read_reg(TCGv result, int num)
^
../target/hexagon/genptr.c:322:20: error: unused function
'gen_set_byte' [-Werror,-Wunused-function]
static inline void gen_set_byte(int N, TCGv result, TCGv src)
^

(this is clang being stricter than gcc about unused static
inline functions again.)

thanks
-- PMM

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Guenter Roeck]

On 4/30/21 9:28 PM, Bin Meng wrote:
> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
>>
>> Hi,
>>
>> On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
>>> From: Bin Meng 
>>>
>>> At present, when booting U-Boot on QEMU sabrelite, we see:
>>>
>>>   Net:   Board Net Initialization Failed
>>>   No ethernet found.
>>>
>>> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
>>> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
>>> board, the Ethernet PHY is at address 6. Adjust this by updating the
>>> "fec-phy-num" property of the fsl_imx6 SoC object.
>>>
>>> With this change, U-Boot sees the PHY but complains MAC address:
>>>
>>>   Net:   using phy at 6
>>>   FEC [PRIME]
>>>   Error: FEC address not set.
>>>
>>> This is due to U-Boot tries to read the MAC address from the fuse,
>>> which QEMU does not have any valid content filled in. However this
>>> does not prevent the Ethernet from working in QEMU. We just need to
>>> set up the MAC address later in the U-Boot command shell, by:
>>>
>>>   => setenv ethaddr 00:11:22:33:44:55
>>>
>>
>> With this patch in place, the standard Ethernet interface no longer works 
>> when
>> booting sabrelite Linux images directly (without u-boot) using the following
>> qemu command.
>> qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
>> ...
>>
>> The Ethernet interface still instantiates, but packet transfer to the host
>> no longer works. Reverting this patch fixes the problem for me.
>>
>> Is there a qemu command line parameter that is now necessary to instantiate
>> the Ethernet interface when booting Linux ?
> 
> Enabling "guest_errors" shows that Linux kernel fec driver is trying
> to read PHY at address 0, which is not what we want.
> 
> [imx.fec.phy]imx_phy_read: Bad phy num 0
> 
> The device tree blob of the sabrelite does not contain a node for the
> ethernet phy specifying phy address, so I suspect Linux kernel driver
> is using default phy address 0 instead.
> 
> Could you please test on a real hardware to see what happens?
> 

The problem is that qemu returns 0 when the OS tries to read from a
non-existing PHY. Linux expects it to return 0x, and believes that
a PHY is there if 0 is returned. This helps:

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index f03450c028..3c90c38e26 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -285,7 +285,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
 if (phy != s->phy_num) {
 qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
   TYPE_IMX_FEC, __func__, phy);
-return 0;
+return 0x;
 }

Note that this is not really a guest error; any OS can and likely
will scan the MII bus for connected phy chips.

Guenter

Re: [PULL 0/5] tcg patch queue

[no-reply]

Patchew URL: 
https://patchew.org/QEMU/20210501185116.1338875-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210501185116.1338875-1-richard.hender...@linaro.org
Subject: [PULL 0/5] tcg patch queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag] 
patchew/20210501185116.1338875-1-richard.hender...@linaro.org -> 
patchew/20210501185116.1338875-1-richard.hender...@linaro.org
Switched to a new branch 'test'
3f52d0d decodetree: Extend argument set syntax to allow types
2f170a4 decodetree: Add support for 64-bit instructions
6567eed decodetree: More use of f-strings
95caca8 decodetree: Introduce whex and whexC helpers
b9a64b1 exec: Remove accel/tcg/ from include paths

=== OUTPUT BEGIN ===
1/5 Checking commit b9a64b13ad89 (exec: Remove accel/tcg/ from include paths)
2/5 Checking commit 95caca818e08 (decodetree: Introduce whex and whexC helpers)
ERROR: line over 90 characters
#52: FILE: scripts/decodetree.py:495:
+output(ind, f'if ((insn & {whexC(innermask)}) == 
{whexC(innerbits)}) {{\n')

WARNING: line over 80 characters
#53: FILE: scripts/decodetree.py:496:
+output(ind, f'/* {str_match_bits(p.fixedbits, 
p.fixedmask)} */\n')

total: 1 errors, 1 warnings, 136 lines checked

Patch 2/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/5 Checking commit 6567eed04461 (decodetree: More use of f-strings)
4/5 Checking commit 2f170a408195 (decodetree: Add support for 64-bit 
instructions)
WARNING: line over 80 characters
#75: FILE: scripts/decodetree.py:236:
+ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - 
pos}, {ext})'

total: 0 errors, 1 warnings, 63 lines checked

Patch 4/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/5 Checking commit 3f52d0d96c42 (decodetree: Extend argument set syntax to 
allow types)
Use of uninitialized value $acpi_testexpected in string eq at 
./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#156: 
new file mode 100644

total: 0 errors, 1 warnings, 121 lines checked

Patch 5/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210501185116.1338875-1-richard.hender...@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[PATCH 0/2] input-linux: Allow to toggle grab from QMP

[Rainer Müller]

This adds an grab-active bool option to input-linux objects to control
the grab state of evdev devices from QMP. The first patch fixes
a problem with multiple keyboards that was previously unlikely, as the
user will only use one device at a time. It could be merged
independently, but I am submitting them together as this becomes more
relevant when grab state can be controlled from QMP.

Rainer Müller (2):
  input-linux: Delay grab toggle if keys are pressed
  input-linux: Allow to toggle grab from QMP

 qapi/qom.json|  3 +++
 ui/input-linux.c | 46 +-
 2 files changed, 44 insertions(+), 5 deletions(-)

-- 
2.25.1

[PULL 4/5] decodetree: Add support for 64-bit instructions

[Richard Henderson]

From: Luis Fernando Fujita Pires 

Allow '64' to be specified for the instruction width command line params
and use the appropriate extract and deposit functions in that case.

This will be used to implement the new 64-bit Power ISA 3.1 instructions.

Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Luis Pires 
Message-Id: 

[rth: Drop the change to the field type; use bitop_width instead of separate
variables for extract/deposit; use "ull" for 64-bit constants.]
Reviewed-by: Luis Pires 
Signed-off-by: Richard Henderson 
---
 scripts/decodetree.py | 21 ++---
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index d5da101167..f85da45ee3 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -27,6 +27,7 @@
 import getopt
 
 insnwidth = 32
+bitop_width = 32
 insnmask = 0x
 variablewidth = False
 fields = {}
@@ -112,7 +113,9 @@ def whexC(val):
 """Return a hex string for val padded for insnwidth,
and with the proper suffix for a C constant."""
 suffix = ''
-if val >= 0x8000:
+if val >= 0x1:
+suffix = 'ull'
+elif val >= 0x8000:
 suffix = 'u'
 return whex(val) + suffix
 
@@ -199,11 +202,9 @@ def __str__(self):
 return str(self.pos) + ':' + s + str(self.len)
 
 def str_extract(self):
-if self.sign:
-extr = 'sextract32'
-else:
-extr = 'extract32'
-return f'{extr}(insn, {self.pos}, {self.len})'
+global bitop_width
+s = 's' if self.sign else ''
+return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
 
 def __eq__(self, other):
 return self.sign == other.sign and self.mask == other.mask
@@ -224,6 +225,7 @@ def __str__(self):
 return str(self.subs)
 
 def str_extract(self):
+global bitop_width
 ret = '0'
 pos = 0
 for f in reversed(self.subs):
@@ -231,7 +233,7 @@ def str_extract(self):
 if pos == 0:
 ret = ext
 else:
-ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
+ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - 
pos}, {ext})'
 pos += f.len
 return ret
 
@@ -1270,6 +1272,7 @@ def main():
 global insntype
 global insnmask
 global decode_function
+global bitop_width
 global variablewidth
 global anyextern
 
@@ -1299,6 +1302,10 @@ def main():
 if insnwidth == 16:
 insntype = 'uint16_t'
 insnmask = 0x
+elif insnwidth == 64:
+insntype = 'uint64_t'
+insnmask = 0x
+bitop_width = 64
 elif insnwidth != 32:
 error(0, 'cannot handle insns of width', insnwidth)
 else:
-- 
2.25.1

[PATCH 2/2] input-linux: Allow to toggle grab from QMP

[Rainer Müller]

This patch allows to boot a guest without the input-linux device being
grabbed immediately from the host. This is useful when the guest is
automatically started, but is supposed to stay in the background until
the user actively switches to it with a key combination.

In this usage example the host continues to own the keyboard until the
user explicitly toggles the grab state with both control keys:
  -object input-linux,id=kbd1,evdev=/dev/input/eventX,grab-active=off

When grab-active is not given, input-linux will behave as before and
devices are being grabbed immediately on initialization.

Note that even if grab_all=on is set, other devices will initially be
grabbed according to their own grab-active option. The first toggle
operation on a grab_all=on device will sync state to the other devices.

Furthermore, this new option allows to toggle the grab state from QMP
with the qom-set command. By setting grab-active at runtime, the device
will be grabbed or released as indicated by the passed value.

  $ ./scripts/qmp-shell /tmp/qmp.sock
  (QEMU) qom-set path=/objects/kbd1 property=grab-active value=true
  {"return": {}}
  (QEMU) qom-get path=/objects/kbd1 property=grab-active
  {"return": true}

For devices with grab_all=on, the action will propagate to other devices
as if the grab toggle hotkey was used.

Signed-off-by: Rainer Müller 
---
 qapi/qom.json|  3 +++
 ui/input-linux.c | 39 +++
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/qapi/qom.json b/qapi/qom.json
index cd0e76d564..51704465ec 100644
--- a/qapi/qom.json
+++ b/qapi/qom.json
@@ -488,6 +488,8 @@
 #
 # @repeat: enables auto-repeat events (default: false)
 #
+# @grab-active: if true, device is grabbed (default: true)
+#
 # @grab-toggle: the key or key combination that toggles device grab
 #   (default: ctrl-ctrl)
 #
@@ -497,6 +499,7 @@
   'data': { 'evdev': 'str',
 '*grab_all': 'bool',
 '*repeat': 'bool',
+'*grab-active': 'bool',
 '*grab-toggle': 'GrabToggleKeys' } }
 
 ##
diff --git a/ui/input-linux.c b/ui/input-linux.c
index 47d489d738..64efb83e21 100644
--- a/ui/input-linux.c
+++ b/ui/input-linux.c
@@ -399,10 +399,9 @@ static void input_linux_complete(UserCreatable *uc, Error 
**errp)
 }
 
 qemu_set_fd_handler(il->fd, input_linux_event, NULL, il);
-if (il->keycount) {
-/* delay grab until all keys are released */
-il->grab_request = true;
-} else {
+/* delay grab until all keys are released */
+if (il->grab_request && !il->keycount) {
+il->grab_request = false;
 input_linux_toggle_grab(il);
 }
 QTAILQ_INSERT_TAIL(&inputs, il, next);
@@ -493,8 +492,37 @@ static void input_linux_set_grab_toggle(Object *obj, int 
value,
 il->grab_toggle = value;
 }
 
+static bool input_linux_get_grab_active(Object *obj, Error **errp)
+{
+InputLinux *il = INPUT_LINUX(obj);
+
+return il->grab_active;
+}
+
+static void input_linux_set_grab_active(Object *obj, bool value,
+Error **errp)
+{
+InputLinux *il = INPUT_LINUX(obj);
+
+if (!il->initialized) {
+il->grab_request = value;
+return;
+}
+
+if (il->grab_active != value) {
+if (il->keycount) {
+il->grab_request = true;
+} else {
+input_linux_toggle_grab(il);
+}
+}
+}
+
 static void input_linux_instance_init(Object *obj)
 {
+InputLinux *il = INPUT_LINUX(obj);
+
+il->grab_request = true;
 }
 
 static void input_linux_class_init(ObjectClass *oc, void *data)
@@ -512,6 +540,9 @@ static void input_linux_class_init(ObjectClass *oc, void 
*data)
 object_class_property_add_bool(oc, "repeat",
input_linux_get_repeat,
input_linux_set_repeat);
+object_class_property_add_bool(oc, "grab-active",
+   input_linux_get_grab_active,
+   input_linux_set_grab_active);
 object_class_property_add_enum(oc, "grab-toggle", "GrabToggleKeys",
&GrabToggleKeys_lookup,
input_linux_get_grab_toggle,
-- 
2.25.1

[PULL 3/5] decodetree: More use of f-strings

[Richard Henderson]

Reviewed-by: Luis Pires 
Signed-off-by: Richard Henderson 
---
 scripts/decodetree.py | 50 ---
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 0861e5d503..d5da101167 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -59,9 +59,9 @@ def error_with_file(file, lineno, *args):
 
 prefix = ''
 if file:
-prefix += '{0}:'.format(file)
+prefix += f'{file}:'
 if lineno:
-prefix += '{0}:'.format(lineno)
+prefix += f'{lineno}:'
 if prefix:
 prefix += ' '
 print(prefix, end='error: ', file=sys.stderr)
@@ -203,7 +203,7 @@ def str_extract(self):
 extr = 'sextract32'
 else:
 extr = 'extract32'
-return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
+return f'{extr}(insn, {self.pos}, {self.len})'
 
 def __eq__(self, other):
 return self.sign == other.sign and self.mask == other.mask
@@ -227,11 +227,11 @@ def str_extract(self):
 ret = '0'
 pos = 0
 for f in reversed(self.subs):
+ext = f.str_extract()
 if pos == 0:
-ret = f.str_extract()
+ret = ext
 else:
-ret = 'deposit32({0}, {1}, {2}, {3})' \
-  .format(ret, pos, 32 - pos, f.str_extract())
+ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
 pos += f.len
 return ret
 
@@ -675,11 +675,11 @@ def parse_field(lineno, name, toks):
 subtoks = t.split(':')
 sign = False
 else:
-error(lineno, 'invalid field token "{0}"'.format(t))
+error(lineno, f'invalid field token "{t}"')
 po = int(subtoks[0])
 le = int(subtoks[1])
 if po + le > insnwidth:
-error(lineno, 'field {0} too large'.format(t))
+error(lineno, f'field {t} too large')
 f = Field(sign, po, le)
 subs.append(f)
 width += le
@@ -724,9 +724,9 @@ def parse_arguments(lineno, name, toks):
 anyextern = True
 continue
 if not re.fullmatch(re_C_ident, t):
-error(lineno, 'invalid argument set token "{0}"'.format(t))
+error(lineno, f'invalid argument set token "{t}"')
 if t in flds:
-error(lineno, 'duplicate argument "{0}"'.format(t))
+error(lineno, f'duplicate argument "{t}"')
 flds.append(t)
 
 if name in arguments:
@@ -895,14 +895,14 @@ def parse_generic(lineno, parent_pat, name, toks):
 flen = flen[1:]
 shift = int(flen, 10)
 if shift + width > insnwidth:
-error(lineno, 'field {0} exceeds insnwidth'.format(fname))
+error(lineno, f'field {fname} exceeds insnwidth')
 f = Field(sign, insnwidth - width - shift, shift)
 flds = add_field(lineno, flds, fname, f)
 fixedbits <<= shift
 fixedmask <<= shift
 undefmask <<= shift
 else:
-error(lineno, 'invalid token "{0}"'.format(t))
+error(lineno, f'invalid token "{t}"')
 width += shift
 
 if variablewidth and width < insnwidth and width % 8 == 0:
@@ -914,7 +914,7 @@ def parse_generic(lineno, parent_pat, name, toks):
 
 # We should have filled in all of the bits of the instruction.
 elif not (is_format and width == 0) and width != insnwidth:
-error(lineno, 'definition has {0} bits'.format(width))
+error(lineno, f'definition has {width} bits')
 
 # Do not check for fields overlapping fields; one valid usage
 # is to be able to duplicate fields via import.
@@ -932,8 +932,7 @@ def parse_generic(lineno, parent_pat, name, toks):
 if arg:
 for f in flds.keys():
 if f not in arg.fields:
-error(lineno, 'field {0} not in argument set {1}'
-  .format(f, arg.name))
+error(lineno, f'field {f} not in argument set {arg.name}')
 else:
 arg = infer_argument_set(flds)
 if name in formats:
@@ -960,13 +959,12 @@ def parse_generic(lineno, parent_pat, name, toks):
 arg = fmt.base
 for f in flds.keys():
 if f not in arg.fields:
-error(lineno, 'field {0} not in argument set {1}'
-  .format(f, arg.name))
+error(lineno, f'field {f} not in argument set {arg.name}')
 if f in fmt.fields.keys():
-error(lineno, 'field {0} set by format and pattern'.format(f))
+error(lineno, f'field {f} set by format and pattern')
 for f in arg.fields:
 if f not in flds.keys() and f not in fmt.fields.keys():
-error(lineno, 'field {0} not initialized'.format(f))
+error(lineno, f'field {f}

[PULL 27/31] Hexagon (target/hexagon) circular addressing

[Richard Henderson]

From: Taylor Simpson 

The following instructions are added
L2_loadrub_pci  Rd32 = memub(Rx32++#s4:0:circ(Mu2))
L2_loadrb_pci   Rd32 = memb(Rx32++#s4:0:circ(Mu2))
L2_loadruh_pci  Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
L2_loadrh_pci   Rd32 = memh(Rx32++#s4:1:circ(Mu2))
L2_loadri_pci   Rd32 = memw(Rx32++#s4:2:circ(Mu2))
L2_loadrd_pci   Rdd32 = memd(Rx32++#s4:3:circ(Mu2))
S2_storerb_pci  memb(Rx32++#s4:0:circ(Mu2)) = Rt32
S2_storerh_pci  memh(Rx32++#s4:1:circ(Mu2)) = Rt32
S2_storerf_pci  memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32
S2_storeri_pci  memw(Rx32++#s4:2:circ(Mu2)) = Rt32
S2_storerd_pci  memd(Rx32++#s4:3:circ(Mu2)) = Rtt32
S2_storerbnew_pci   memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new
S2_storerhnew_pci   memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new
S2_storerinew_pci   memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new
L2_loadrub_pcr  Rd32 = memub(Rx32++I:circ(Mu2))
L2_loadrb_pcr   Rd32 = memb(Rx32++I:circ(Mu2))
L2_loadruh_pcr  Rd32 = memuh(Rx32++I:circ(Mu2))
L2_loadrh_pcr   Rd32 = memh(Rx32++I:circ(Mu2))
L2_loadri_pcr   Rd32 = memw(Rx32++I:circ(Mu2))
L2_loadrd_pcr   Rdd32 = memd(Rx32++I:circ(Mu2))
S2_storerb_pcr  memb(Rx32++I:circ(Mu2)) = Rt32
S2_storerh_pcr  memh(Rx32++I:circ(Mu2)) = Rt32
S2_storerf_pcr  memh(Rx32++I:circ(Mu2)) = Rt32.H32
S2_storeri_pcr  memw(Rx32++I:circ(Mu2)) = Rt32
S2_storerd_pcr  memd(Rx32++I:circ(Mu2)) = Rtt32
S2_storerbnew_pcr   memb(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerhnew_pcr   memh(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerinew_pcr   memw(Rx32++I:circ(Mu2)) = Nt8.new

Test cases in tests/tcg/hexagon/circ.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-23-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  | 112 +-
 target/hexagon/macros.h   |  92 +
 target/hexagon/genptr.c   | 100 ++
 target/hexagon/op_helper.c|  36 +-
 tests/tcg/hexagon/circ.c  | 486 ++
 target/hexagon/imported/encode_pp.def |  10 +
 target/hexagon/imported/ldst.idef |   4 +
 target/hexagon/imported/macros.def|  26 ++
 tests/tcg/hexagon/Makefile.target |   2 +
 9 files changed, 845 insertions(+), 23 deletions(-)
 create mode 100644 tests/tcg/hexagon/circ.c

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 6bc578dfda..25c228c112 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -38,6 +38,8 @@
  * _ap   absolute set  r0 = memw(r1=##variable)
  * _pr   post increment register   r0 = memw(r1++m1)
  * _pi   post increment immediate  r0 = memb(r1++#1)
+ * _pci  post increment circular immediate r0 = memw(r1++#4:circ(m0))
+ * _pcr  post increment circular register  r0 = memw(r1++I:circ(m0))
  */
 
 /* Macros for complex addressing modes */
@@ -56,7 +58,22 @@
 fEA_REG(RxV); \
 fPM_I(RxV, siV); \
 } while (0)
-
+#define GET_EA_pci \
+do { \
+TCGv tcgv_siV = tcg_const_tl(siV); \
+tcg_gen_mov_tl(EA, RxV); \
+gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
+hex_gpr[HEX_REG_CS0 + MuN]); \
+tcg_temp_free(tcgv_siV); \
+} while (0)
+#define GET_EA_pcr(SHIFT) \
+do { \
+TCGv ireg = tcg_temp_new(); \
+tcg_gen_mov_tl(EA, RxV); \
+gen_read_ireg(ireg, MuV, (SHIFT)); \
+gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
+tcg_temp_free(ireg); \
+} while (0)
 
 /* Instructions with multiple definitions */
 #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \
@@ -80,6 +97,36 @@
 #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \
 fGEN_TCG_LOAD_AP(RddV, 8, u)
 
+#define fGEN_TCG_L2_loadrub_pci(SHORTCODE)SHORTCODE
+#define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadruh_pci(SHORTCODE)SHORTCODE
+#define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE
+
+#define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \
+do { \
+TCGv ireg = tcg_temp_new(); \
+tcg_gen_mov_tl(EA, RxV); \
+gen_read_ireg(ireg, MuV, SHIFT); \
+gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
+LOAD; \
+tcg_temp_free(ireg); \
+} while (0)
+
+#define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \
+  fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV))
+#define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \
+  fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV))
+#define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \
+  fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV

[PATCH 1/2] input-linux: Delay grab toggle if keys are pressed

[Rainer Müller]

When multiple keyboards are passed to the guest with input-linux, there
could still be keys pressed on the other keyboard when toggling grab.
Delay toggling grab on the other keyboard until all keys are released,
otherwise keys could be stuck on host without a key up event.

Signed-off-by: Rainer Müller 
---
 ui/input-linux.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/ui/input-linux.c b/ui/input-linux.c
index 05c0c98819..47d489d738 100644
--- a/ui/input-linux.c
+++ b/ui/input-linux.c
@@ -89,7 +89,12 @@ static void input_linux_toggle_grab(InputLinux *il)
 continue;
 }
 if (item->grab_active != il->grab_active) {
-input_linux_toggle_grab(item);
+if (item->keycount) {
+/* delay grab until all keys are released */
+item->grab_request = true;
+} else {
+input_linux_toggle_grab(item);
+}
 }
 }
 }
-- 
2.25.1

[PULL 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing

[Richard Henderson]

From: Taylor Simpson 

The following instructions are added
L2_loadrub_pbr  Rd32 = memub(Rx32++Mu2:brev)
L2_loadrb_pbr   Rd32 = memb(Rx32++Mu2:brev)
L2_loadruh_pbr  Rd32 = memuh(Rx32++Mu2:brev)
L2_loadrh_pbr   Rd32 = memh(Rx32++Mu2:brev)
L2_loadri_pbr   Rd32 = memw(Rx32++Mu2:brev)
L2_loadrd_pbr   Rdd32 = memd(Rx32++Mu2:brev)
S2_storerb_pbr  memb(Rx32++Mu2:brev).=.Rt32
S2_storerh_pbr  memh(Rx32++Mu2:brev).=.Rt32
S2_storerf_pbr  memh(Rx32++Mu2:brev).=.Rt.H32
S2_storeri_pbr  memw(Rx32++Mu2:brev).=.Rt32
S2_storerd_pbr  memd(Rx32++Mu2:brev).=.Rt32
S2_storerinew_pbr   memw(Rx32++Mu2:brev).=.Nt8.new
S2_storerbnew_pbr   memw(Rx32++Mu2:brev).=.Nt8.new
S2_storerhnew_pbr   memw(Rx32++Mu2:brev).=.Nt8.new

Test cases in tests/tcg/hexagon/brev.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-24-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  |  28 
 target/hexagon/helper.h   |   1 +
 target/hexagon/macros.h   |   1 +
 target/hexagon/op_helper.c|   8 ++
 tests/tcg/hexagon/brev.c  | 190 ++
 target/hexagon/imported/encode_pp.def |   4 +
 target/hexagon/imported/ldst.idef |   2 +
 target/hexagon/imported/macros.def|   6 +
 tests/tcg/hexagon/Makefile.target |   1 +
 9 files changed, 241 insertions(+)
 create mode 100644 tests/tcg/hexagon/brev.c

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 25c228c112..8f0ec01f0a 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -37,6 +37,7 @@
  * _sp   stack pointer relativer0 = memw(r29+#12)
  * _ap   absolute set  r0 = memw(r1=##variable)
  * _pr   post increment register   r0 = memw(r1++m1)
+ * _pbr  post increment bit reverser0 = memw(r1++m1:brev)
  * _pi   post increment immediate  r0 = memb(r1++#1)
  * _pci  post increment circular immediate r0 = memw(r1++#4:circ(m0))
  * _pcr  post increment circular register  r0 = memw(r1++I:circ(m0))
@@ -53,6 +54,11 @@
 fEA_REG(RxV); \
 fPM_M(RxV, MuV); \
 } while (0)
+#define GET_EA_pbr \
+do { \
+gen_helper_fbrev(EA, RxV); \
+tcg_gen_add_tl(RxV, RxV, MuV); \
+} while (0)
 #define GET_EA_pi \
 do { \
 fEA_REG(RxV); \
@@ -128,16 +134,22 @@
   fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV))
 
 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE)  SHORTCODE
+#define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE
 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE)   SHORTCODE
+#define fGEN_TCG_L2_loadrb_pbr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrb_pi(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE)  SHORTCODE
+#define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE
 #define fGEN_TCG_L2_loadruh_pi(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE)   SHORTCODE
+#define fGEN_TCG_L2_loadrh_pbr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadri_pr(SHORTCODE)   SHORTCODE
+#define fGEN_TCG_L2_loadri_pbr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadri_pi(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadrd_pr(SHORTCODE)   SHORTCODE
+#define fGEN_TCG_L2_loadrd_pbr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE)   SHORTCODE
 
 /*
@@ -265,41 +277,57 @@
 tcg_temp_free(BYTE); \
 } while (0)
 
+#define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \
+fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \
 fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \
 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV)))
 
+#define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \
+fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \
 fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \
 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV)))
 
+#define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \
+fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \
 fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \
 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV)))
 
+#define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \
+fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \
 fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \
 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV))
 
+#define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \
+fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \
 fGEN_TCG_STORE(SHORTCODE)
 #define fGEN_

[PULL 2/5] decodetree: Introduce whex and whexC helpers

[Richard Henderson]

Form a hex constant of the appropriate insnwidth.
Begin using f-strings on changed lines.

Reviewed-by: Luis Pires 
Signed-off-by: Richard Henderson 
---
 scripts/decodetree.py | 66 +--
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 4637b633e7..0861e5d503 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -102,6 +102,21 @@ def str_fields(fields):
 return r[1:]
 
 
+def whex(val):
+"""Return a hex string for val padded for insnwidth"""
+global insnwidth
+return f'0x{val:0{insnwidth // 4}x}'
+
+
+def whexC(val):
+"""Return a hex string for val padded for insnwidth,
+   and with the proper suffix for a C constant."""
+suffix = ''
+if val >= 0x8000:
+suffix = 'u'
+return whex(val) + suffix
+
+
 def str_match_bits(bits, mask):
 """Return a string pretty-printing BITS/MASK"""
 global insnwidth
@@ -477,11 +492,8 @@ def output_code(self, i, extracted, outerbits, outermask):
 if outermask != p.fixedmask:
 innermask = p.fixedmask & ~outermask
 innerbits = p.fixedbits & ~outermask
-output(ind, 'if ((insn & ',
-   '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits),
-   ') {\n')
-output(ind, '/* ',
-   str_match_bits(p.fixedbits, p.fixedmask), ' */\n')
+output(ind, f'if ((insn & {whexC(innermask)}) == 
{whexC(innerbits)}) {{\n')
+output(ind, f'/* {str_match_bits(p.fixedbits, 
p.fixedmask)} */\n')
 p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
 output(ind, '}\n')
 else:
@@ -500,12 +512,12 @@ def __init__(self, fm, tm):
 
 def str1(self, i):
 ind = str_indent(i)
-r = '{0}{1:08x}'.format(ind, self.fixedmask)
+r = ind + whex(self.fixedmask)
 if self.format:
 r += ' ' + self.format.name
 r += ' [\n'
 for (b, s) in self.subs:
-r += '{0}  {1:08x}:\n'.format(ind, b)
+r += ind + f'  {whex(b)}:\n'
 r += s.str1(i + 4) + '\n'
 r += ind + ']'
 return r
@@ -529,16 +541,16 @@ def output_code(self, i, extracted, outerbits, outermask):
 if sh > 0:
 # Propagate SH down into the local functions.
 def str_switch(b, sh=sh):
-return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
+return f'(insn >> {sh}) & {b >> sh:#x}'
 
 def str_case(b, sh=sh):
-return '0x{0:x}'.format(b >> sh)
+return hex(b >> sh)
 else:
 def str_switch(b):
-return 'insn & 0x{0:08x}'.format(b)
+return f'insn & {whexC(b)}'
 
 def str_case(b):
-return '0x{0:08x}'.format(b)
+return whexC(b)
 
 output(ind, 'switch (', str_switch(self.thismask), ') {\n')
 for b, s in sorted(self.subs):
@@ -962,19 +974,19 @@ def parse_generic(lineno, parent_pat, name, toks):
 
 # Validate the masks that we have assembled.
 if fieldmask & fixedmask:
-error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})'
-  .format(fieldmask, fixedmask))
+error(lineno, 'fieldmask overlaps fixedmask ',
+  f'({whex(fieldmask)} & {whex(fixedmask)})')
 if fieldmask & undefmask:
-error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
-  .format(fieldmask, undefmask))
+error(lineno, 'fieldmask overlaps undefmask ',
+  f'({whex(fieldmask)} & {whex(undefmask)})')
 if fixedmask & undefmask:
-error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
-  .format(fixedmask, undefmask))
+error(lineno, 'fixedmask overlaps undefmask ',
+  f'({whex(fixedmask)} & {whex(undefmask)})')
 if not is_format:
 allbits = fieldmask | fixedmask | undefmask
 if allbits != insnmask:
-error(lineno, 'bits left unspecified (0x{0:08x})'
-  .format(allbits ^ insnmask))
+error(lineno, 'bits left unspecified ',
+  f'({whex(allbits ^ insnmask)})')
 # end parse_general
 
 
@@ -1104,10 +1116,9 @@ def __init__(self, m, w):
 
 def str1(self, i):
 ind = str_indent(i)
-r = '{0}{1:08x}'.format(ind, self.mask)
-r += ' [\n'
+r = ind + whex(self.mask) + ' [\n'
 for (b, s) in self.subs:
-r += '{0}  {1:08x}:\n'.format(ind, b)
+r += ind + f'  {whex(b)}:\n'
 r += s.str1(i + 4) + '\n'
 r += ind + ']'
 return r
@@ -1131,16 +1142,16 @@ def output_code(self, i, extracted, outerbits, 
outermask):
 if sh > 0:
 # Propagate SH down into the l

[PULL 31/31] Hexagon (target/hexagon) CABAC decode bin

[Richard Henderson]

From: Taylor Simpson 

The following instruction is added
S2_cabacdecbinRdd32=decbin(Rss32,Rtt32)

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-27-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.h |  4 ++
 target/hexagon/macros.h   |  7 +++
 target/hexagon/arch.c | 91 +++
 tests/tcg/hexagon/misc.c  | 28 +
 target/hexagon/imported/encode_pp.def |  1 +
 target/hexagon/imported/macros.def| 15 +
 target/hexagon/imported/shift.idef| 47 ++
 7 files changed, 193 insertions(+)

diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h
index 3e0c334209..70918065d3 100644
--- a/target/hexagon/arch.h
+++ b/target/hexagon/arch.h
@@ -20,6 +20,10 @@
 
 #include "qemu/int128.h"
 
+extern const uint8_t rLPS_table_64x4[64][4];
+extern const uint8_t AC_next_state_MPS_64[64];
+extern const uint8_t AC_next_state_LPS_64[64];
+
 uint64_t interleave(uint32_t odd, uint32_t even);
 uint64_t deinterleave(uint64_t src);
 int32_t conv_round(int32_t a, int n);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index ec5bf60f5e..b726c3b791 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -222,6 +222,13 @@ static inline void gen_pred_cancel(TCGv pred, int slot_num)
 (((HIBIT) - (LOWBIT) + 1) ? \
 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 0LL)
+#define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
+do { \
+int width = ((HIBIT) - (LOWBIT) + 1); \
+INREG = (width >= 0 ? \
+deposit64((INREG), (LOWBIT), width, (INVAL)) : \
+INREG); \
+} while (0)
 
 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index dee852e106..68a55b3bd4 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -27,6 +27,97 @@
 #define SF_MANTBITS23
 #define float32_nanmake_float32(0x)
 
+/*
+ * These three tables are used by the cabacdecbin instruction
+ */
+const uint8_t rLPS_table_64x4[64][4] = {
+{128, 176, 208, 240},
+{128, 167, 197, 227},
+{128, 158, 187, 216},
+{123, 150, 178, 205},
+{116, 142, 169, 195},
+{111, 135, 160, 185},
+{105, 128, 152, 175},
+{100, 122, 144, 166},
+{95, 116, 137, 158},
+{90, 110, 130, 150},
+{85, 104, 123, 142},
+{81, 99, 117, 135},
+{77, 94, 111, 128},
+{73, 89, 105, 122},
+{69, 85, 100, 116},
+{66, 80, 95, 110},
+{62, 76, 90, 104},
+{59, 72, 86, 99},
+{56, 69, 81, 94},
+{53, 65, 77, 89},
+{51, 62, 73, 85},
+{48, 59, 69, 80},
+{46, 56, 66, 76},
+{43, 53, 63, 72},
+{41, 50, 59, 69},
+{39, 48, 56, 65},
+{37, 45, 54, 62},
+{35, 43, 51, 59},
+{33, 41, 48, 56},
+{32, 39, 46, 53},
+{30, 37, 43, 50},
+{29, 35, 41, 48},
+{27, 33, 39, 45},
+{26, 31, 37, 43},
+{24, 30, 35, 41},
+{23, 28, 33, 39},
+{22, 27, 32, 37},
+{21, 26, 30, 35},
+{20, 24, 29, 33},
+{19, 23, 27, 31},
+{18, 22, 26, 30},
+{17, 21, 25, 28},
+{16, 20, 23, 27},
+{15, 19, 22, 25},
+{14, 18, 21, 24},
+{14, 17, 20, 23},
+{13, 16, 19, 22},
+{12, 15, 18, 21},
+{12, 14, 17, 20},
+{11, 14, 16, 19},
+{11, 13, 15, 18},
+{10, 12, 15, 17},
+{10, 12, 14, 16},
+{9, 11, 13, 15},
+{9, 11, 12, 14},
+{8, 10, 12, 14},
+{8, 9, 11, 13},
+{7, 9, 11, 12},
+{7, 9, 10, 12},
+{7, 8, 10, 11},
+{6, 8, 9, 11},
+{6, 7, 9, 10},
+{6, 7, 8, 9},
+{2, 2, 2, 2}
+};
+
+const uint8_t AC_next_state_MPS_64[64] = {
+1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+31, 32, 33, 34, 35, 36, 37, 38, 39, 40,
+41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
+51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+61, 62, 62, 63
+};
+
+
+const uint8_t AC_next_state_LPS_64[64] = {
+0, 0, 1, 2, 2, 4, 4, 5, 6, 7,
+8, 9, 9, 11, 11, 12, 13, 13, 15, 15,
+16, 16, 18, 18, 19, 19, 21, 21, 22, 22,
+23, 24, 24, 25, 26, 26, 27, 27, 28, 29,
+29, 30, 30, 30, 31, 32, 32, 33, 33, 33,
+34, 34, 35, 35, 35, 36, 36, 36, 37, 37,
+37, 38, 38, 63
+};
+
 #define BITS_MASK_8 0xULL
 #define PAIR_MASK_8 0xULL
 #define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index e5d78b471f..17c39198fc 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -231,6 +231,14 @@ static void check(int val, int expect)
 }
 }
 
+static void check64(long long val, long long expect)
+{
+if (val != expect) {
+printf("ERROR: 0x%016llx != 0x%016llx\n", val, expect);
+err++;
+}
+}
+
 uint32_t init[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
 uint3

[PULL 0/5] tcg patch queue

[Richard Henderson]

The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into 
staging (2021-04-30 16:02:00 +0100)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501

for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:

  decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 
-0700)


Include cleanups.
Decodetree enhancements for power10.


Luis Fernando Fujita Pires (1):
  decodetree: Add support for 64-bit instructions

Philippe Mathieu-Daudé (1):
  exec: Remove accel/tcg/ from include paths

Richard Henderson (3):
  decodetree: Introduce whex and whexC helpers
  decodetree: More use of f-strings
  decodetree: Extend argument set syntax to allow types

 docs/devel/decodetree.rst |  11 ++-
 meson.build   |   1 -
 include/exec/helper-gen.h |   4 +-
 include/exec/helper-proto.h   |   4 +-
 include/exec/helper-tcg.h |   4 +-
 tests/decode/succ_argset_type1.decode |   1 +
 scripts/decodetree.py | 172 +++---
 7 files changed, 112 insertions(+), 85 deletions(-)
 create mode 100644 tests/decode/succ_argset_type1.decode

[PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c

[Richard Henderson]

From: Taylor Simpson 

Rdd32 = add(Rss32, Rtt32, Px4):carry
Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
Sub with carry

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-22-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  | 37 
 target/hexagon/genptr.c   | 11 
 tests/tcg/hexagon/multi_result.c  | 82 +++
 target/hexagon/imported/alu.idef  | 15 +
 target/hexagon/imported/encode_pp.def |  2 +
 5 files changed, 147 insertions(+)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index aea0c55564..6bc578dfda 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -237,6 +237,43 @@
 tcg_temp_free_i64(tmp); \
 } while (0)
 
+/*
+ * Add or subtract with carry.
+ * Predicate register is used as an extra input and output.
+ * r5:4 = add(r1:0, r3:2, p1):carry
+ */
+#define fGEN_TCG_A4_addp_c(SHORTCODE) \
+do { \
+TCGv_i64 carry = tcg_temp_new_i64(); \
+TCGv_i64 zero = tcg_const_i64(0); \
+tcg_gen_extu_i32_i64(carry, PxV); \
+tcg_gen_andi_i64(carry, carry, 1); \
+tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
+tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
+tcg_gen_extrl_i64_i32(PxV, carry); \
+gen_8bitsof(PxV, PxV); \
+tcg_temp_free_i64(carry); \
+tcg_temp_free_i64(zero); \
+} while (0)
+
+/* r5:4 = sub(r1:0, r3:2, p1):carry */
+#define fGEN_TCG_A4_subp_c(SHORTCODE) \
+do { \
+TCGv_i64 carry = tcg_temp_new_i64(); \
+TCGv_i64 zero = tcg_const_i64(0); \
+TCGv_i64 not_RttV = tcg_temp_new_i64(); \
+tcg_gen_extu_i32_i64(carry, PxV); \
+tcg_gen_andi_i64(carry, carry, 1); \
+tcg_gen_not_i64(not_RttV, RttV); \
+tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
+tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
+tcg_gen_extrl_i64_i32(PxV, carry); \
+gen_8bitsof(PxV, PxV); \
+tcg_temp_free_i64(carry); \
+tcg_temp_free_i64(zero); \
+tcg_temp_free_i64(not_RttV); \
+} while (0)
+
 /*
  * Compare each of the 8 unsigned bytes
  * The minimum is placed in each byte of the destination.
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 9dbebc64b5..333f7d74bf 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -361,5 +361,16 @@ static inline void gen_store_conditional8(CPUHexagonState 
*env,
 tcg_gen_movi_tl(hex_llsc_addr, ~0);
 }
 
+static TCGv gen_8bitsof(TCGv result, TCGv value)
+{
+TCGv zero = tcg_const_tl(0);
+TCGv ones = tcg_const_tl(0xff);
+tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
+tcg_temp_free(zero);
+tcg_temp_free(ones);
+
+return result;
+}
+
 #include "tcg_funcs_generated.c.inc"
 #include "tcg_func_table_generated.c.inc"
diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_result.c
index 95d99a0c90..52997b3128 100644
--- a/tests/tcg/hexagon/multi_result.c
+++ b/tests/tcg/hexagon/multi_result.c
@@ -85,6 +85,38 @@ static long long vminub(long long Rtt, long long Rss,
   return result;
 }
 
+static long long add_carry(long long Rss, long long Rtt,
+   int pred_in, int *pred_result)
+{
+  long long result;
+  int predval = pred_in;
+
+  asm volatile("p0 = %1\n\t"
+   "%0 = add(%2, %3, p0):carry\n\t"
+   "%1 = p0\n\t"
+   : "=r"(result), "+r"(predval)
+   : "r"(Rss), "r"(Rtt)
+   : "p0");
+  *pred_result = predval;
+  return result;
+}
+
+static long long sub_carry(long long Rss, long long Rtt,
+   int pred_in, int *pred_result)
+{
+  long long result;
+  int predval = pred_in;
+
+  asm volatile("p0 = !cmp.eq(%1, #0)\n\t"
+   "%0 = sub(%2, %3, p0):carry\n\t"
+   "%1 = p0\n\t"
+   : "=r"(result), "+r"(predval)
+   : "r"(Rss), "r"(Rtt)
+   : "p0");
+  *pred_result = predval;
+  return result;
+}
+
 int err;
 
 static void check_ll(long long val, long long expect)
@@ -188,12 +220,62 @@ static void test_vminub()
 check_p(pred_result, 0xaa);
 }
 
+static void test_add_carry()
+{
+long long res64;
+int pred_result;
+
+res64 = add_carry(0xLL,
+  0xLL,
+  1, &pred_result);
+check_ll(res64, 0xLL);
+check_p(pred_result, 0xff);
+
+res64 = add_carry(0x0001LL,
+  0xLL,
+  0, &pred_result);
+check_ll(res64, 0xLL);
+check_p(pred_result, 0xff);
+
+res64 = add_carry(0x0001LL,
+  0xLL,
+  

[PULL 21/31] Hexagon (target/hexagon) compile all debug code

[Richard Henderson]

From: Taylor Simpson 

Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot

Suggested-by: Philippe Mathieu-Daudé 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-17-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/helper.h|  2 --
 target/hexagon/internal.h  | 11 +++---
 target/hexagon/translate.h |  2 --
 target/hexagon/genptr.c| 72 ++---
 target/hexagon/op_helper.c | 14 +++-
 target/hexagon/translate.c | 74 ++
 6 files changed, 81 insertions(+), 94 deletions(-)

diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 715c24662f..efe6069118 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -19,11 +19,9 @@
 #include "helper_protos_generated.h.inc"
 
 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
-#if HEX_DEBUG
 DEF_HELPER_1(debug_start_packet, void, env)
 DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, 
int)
 DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int)
-#endif
 DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
 
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 2da85c8606..6b20affdfa 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -22,11 +22,12 @@
  * Change HEX_DEBUG to 1 to turn on debugging output
  */
 #define HEX_DEBUG 0
-#if HEX_DEBUG
-#define HEX_DEBUG_LOG(...) qemu_log(__VA_ARGS__)
-#else
-#define HEX_DEBUG_LOG(...) do { } while (0)
-#endif
+#define HEX_DEBUG_LOG(...) \
+do { \
+if (HEX_DEBUG) { \
+qemu_log(__VA_ARGS__); \
+} \
+} while (0)
 
 int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 97b12a7d18..703fd1345f 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -41,11 +41,9 @@ typedef struct DisasContext {
 
 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
 {
-#if HEX_DEBUG
 if (test_bit(rnum, ctx->regs_written)) {
 HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
 }
-#endif
 ctx->reg_log[ctx->reg_log_idx] = rnum;
 ctx->reg_log_idx++;
 set_bit(rnum, ctx->regs_written);
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index b87e264ccf..24d575853c 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -42,17 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum, 
TCGv val, int slot)
 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
val, hex_new_value[rnum]);
-#if HEX_DEBUG
-/*
- * Do this so HELPER(debug_commit_end) will know
- *
- * Note that slot_mask indicates the value is not written
- * (i.e., slot was cancelled), so we create a true/false value before
- * or'ing with hex_reg_written[rnum].
- */
-tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
-tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
-#endif
+if (HEX_DEBUG) {
+/*
+ * Do this so HELPER(debug_commit_end) will know
+ *
+ * Note that slot_mask indicates the value is not written
+ * (i.e., slot was cancelled), so we create a true/false value before
+ * or'ing with hex_reg_written[rnum].
+ */
+tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
+}
 
 tcg_temp_free(zero);
 tcg_temp_free(slot_mask);
@@ -61,10 +61,10 @@ static inline void gen_log_predicated_reg_write(int rnum, 
TCGv val, int slot)
 static inline void gen_log_reg_write(int rnum, TCGv val)
 {
 tcg_gen_mov_tl(hex_new_value[rnum], val);
-#if HEX_DEBUG
-/* Do this so HELPER(debug_commit_end) will know */
-tcg_gen_movi_tl(hex_reg_written[rnum], 1);
-#endif
+if (HEX_DEBUG) {
+/* Do this so HELPER(debug_commit_end) will know */
+tcg_gen_movi_tl(hex_reg_written[rnum], 1);
+}
 }
 
 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
@@ -84,19 +84,19 @@ static void gen_log_predicated_reg_write_pair(int rnum, 
TCGv_i64 val, int slot)
 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
slot_mask, zero,
val32, hex_new_value[rnum + 1]);
-#if HEX_DEBUG
-/*
- * Do this so HELPER(debug_commit_end) will know
- *
- * Note that slot_mask indicates the value is not written
- * (i.e., slot was cancelled), so we create a true/false value before
- * or'ing with hex_re

[PULL 25/31] Hexagon (target/hexagon) add A6_vminub_RdP

[Richard Henderson]

From: Taylor Simpson 

Rdd32,Pe4 = vminub(Rtt32, Rss32)
Vector min of bytes

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-21-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  | 27 +
 target/hexagon/genptr.c   | 22 +
 tests/tcg/hexagon/multi_result.c  | 34 +++
 target/hexagon/imported/alu.idef  | 10 
 target/hexagon/imported/encode_pp.def |  1 +
 5 files changed, 94 insertions(+)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 93310c5edc..aea0c55564 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -237,6 +237,33 @@
 tcg_temp_free_i64(tmp); \
 } while (0)
 
+/*
+ * Compare each of the 8 unsigned bytes
+ * The minimum is placed in each byte of the destination.
+ * Each bit of the predicate is set true if the bit from the first operand
+ * is greater than the bit from the second operand.
+ * r5:4,p1 = vminub(r1:0, r3:2)
+ */
+#define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \
+do { \
+TCGv left = tcg_temp_new(); \
+TCGv right = tcg_temp_new(); \
+TCGv tmp = tcg_temp_new(); \
+tcg_gen_movi_tl(PeV, 0); \
+tcg_gen_movi_i64(RddV, 0); \
+for (int i = 0; i < 8; i++) { \
+gen_get_byte_i64(left, i, RttV, false); \
+gen_get_byte_i64(right, i, RssV, false); \
+tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
+tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \
+tcg_gen_umin_tl(tmp, left, right); \
+gen_set_byte_i64(i, RddV, tmp); \
+} \
+tcg_temp_free(left); \
+tcg_temp_free(right); \
+tcg_temp_free(tmp); \
+} while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
 gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 24d575853c..9dbebc64b5 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -266,6 +266,28 @@ static inline void gen_write_ctrl_reg_pair(DisasContext 
*ctx, int reg_num,
 }
 }
 
+static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
+{
+TCGv_i64 res64 = tcg_temp_new_i64();
+if (sign) {
+tcg_gen_sextract_i64(res64, src, N * 8, 8);
+} else {
+tcg_gen_extract_i64(res64, src, N * 8, 8);
+}
+tcg_gen_extrl_i64_i32(result, res64);
+tcg_temp_free_i64(res64);
+
+return result;
+}
+
+static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
+{
+TCGv_i64 src64 = tcg_temp_new_i64();
+tcg_gen_extu_i32_i64(src64, src);
+tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
+tcg_temp_free_i64(src64);
+}
+
 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
 {
 tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_result.c
index c21148fc20..95d99a0c90 100644
--- a/tests/tcg/hexagon/multi_result.c
+++ b/tests/tcg/hexagon/multi_result.c
@@ -70,6 +70,21 @@ static long long vacsh(long long Rxx, long long Rss, long 
long Rtt,
   return result;
 }
 
+static long long vminub(long long Rtt, long long Rss,
+int *pred_result)
+{
+  long long result;
+  int predval;
+
+  asm volatile("%0,p0 = vminub(%2, %3)\n\t"
+   "%1 = p0\n\t"
+   : "=r"(result), "=r"(predval)
+   : "r"(Rtt), "r"(Rss)
+   : "p0");
+  *pred_result = predval;
+  return result;
+}
+
 int err;
 
 static void check_ll(long long val, long long expect)
@@ -155,11 +170,30 @@ static void test_vacsh()
 check(ovf_result, 0);
 }
 
+static void test_vminub()
+{
+long long res64;
+int pred_result;
+
+res64 = vminub(0x0807060504030201LL,
+   0x0102030405060708LL,
+   &pred_result);
+check_ll(res64, 0x0102030404030201LL);
+check_p(pred_result, 0xf0);
+
+res64 = vminub(0x0802060405030701LL,
+   0x0107030504060208LL,
+   &pred_result);
+check_ll(res64, 0x0102030404030201LL);
+check_p(pred_result, 0xaa);
+}
+
 int main()
 {
 test_sfrecipa();
 test_sfinvsqrta();
 test_vacsh();
+test_vminub();
 
 puts(err ? "FAIL" : "PASS");
 return err;
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index e8cc52c290..f0c9bb47ec 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1259,6 +1259,16 @@ Q6INSN(A5_ACS,"Rxx32,Pe4=vacsh(Rss32,Rtt32)",ATTRIBS(),
 }
 })
 
+Q6INSN(A6_vminub_RdP,"Rdd32,Pe4=vminub(Rtt32,Rss32)",ATTRIBS(),
+"Vector minimum of bytes, records minimum and decision vector",
+{
+fHIDE(int i;)
+for (i = 0; i < 8; i++) {
+fSETBIT(i, PeV, (fGETUBYTE(i,RttV) > fG

[PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh)

[Richard Henderson]

From: Taylor Simpson 

Rxx32,Pe4 = vacsh(Rss32, Rtt32)
Add compare and select elements of two vectors

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-20-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  |  5 ++
 target/hexagon/helper.h   |  2 +
 target/hexagon/op_helper.c| 33 +
 tests/tcg/hexagon/multi_result.c  | 69 +++
 target/hexagon/imported/alu.idef  | 19 
 target/hexagon/imported/encode_pp.def |  1 +
 6 files changed, 129 insertions(+)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index d78e7b8e5c..93310c5edc 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -199,6 +199,11 @@
  * Mathematical operations with more than one definition require
  * special handling
  */
+#define fGEN_TCG_A5_ACS(SHORTCODE) \
+do { \
+gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
+gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \
+} while (0)
 
 /*
  * Approximate reciprocal
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index cb7508f746..3824ae01ea 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -26,6 +26,8 @@ DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
 DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
 DEF_HELPER_2(sfinvsqrta, i64, env, f32)
+DEF_HELPER_4(vacsh_val, s64, env, s64, s64, s64)
+DEF_HELPER_FLAGS_4(vacsh_pred, TCG_CALL_NO_RWG_SE, s32, env, s64, s64, s64)
 
 /* Floating point */
 DEF_HELPER_2(conv_sf2df, f64, env, f32)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index a25fb98f24..f9fb6b 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -347,6 +347,39 @@ uint64_t HELPER(sfinvsqrta)(CPUHexagonState *env, float32 
RsV)
 return ((uint64_t)RdV << 32) | PeV;
 }
 
+int64_t HELPER(vacsh_val)(CPUHexagonState *env,
+   int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+for (int i = 0; i < 4; i++) {
+int xv = sextract64(RxxV, i * 16, 16);
+int sv = sextract64(RssV, i * 16, 16);
+int tv = sextract64(RttV, i * 16, 16);
+int max;
+xv = xv + tv;
+sv = sv - tv;
+max = xv > sv ? xv : sv;
+/* Note that fSATH can set the OVF bit in usr */
+RxxV = deposit64(RxxV, i * 16, 16, fSATH(max));
+}
+return RxxV;
+}
+
+int32_t HELPER(vacsh_pred)(CPUHexagonState *env,
+   int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+int32_t PeV = 0;
+for (int i = 0; i < 4; i++) {
+int xv = sextract64(RxxV, i * 16, 16);
+int sv = sextract64(RssV, i * 16, 16);
+int tv = sextract64(RttV, i * 16, 16);
+xv = xv + tv;
+sv = sv - tv;
+PeV = deposit32(PeV, i * 2, 1, (xv > sv));
+PeV = deposit32(PeV, i * 2 + 1, 1, (xv > sv));
+}
+return PeV;
+}
+
 /*
  * mem_noshuf
  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_result.c
index 67aa46249b..c21148fc20 100644
--- a/tests/tcg/hexagon/multi_result.c
+++ b/tests/tcg/hexagon/multi_result.c
@@ -45,8 +45,41 @@ static int sfinvsqrta(int Rs, int *pred_result)
   return result;
 }
 
+static long long vacsh(long long Rxx, long long Rss, long long Rtt,
+   int *pred_result, int *ovf_result)
+{
+  long long result = Rxx;
+  int predval;
+  int usr;
+
+  /*
+   * This instruction can set bit 0 (OVF/overflow) in usr
+   * Clear the bit first, then return that bit to the caller
+   */
+  asm volatile("r2 = usr\n\t"
+   "r2 = clrbit(r2, #0)\n\t"/* clear overflow bit */
+   "usr = r2\n\t"
+   "%0,p0 = vacsh(%3, %4)\n\t"
+   "%1 = p0\n\t"
+   "%2 = usr\n\t"
+   : "+r"(result), "=r"(predval), "=r"(usr)
+   : "r"(Rss), "r"(Rtt)
+   : "r2", "p0", "usr");
+  *pred_result = predval;
+  *ovf_result = (usr & 1);
+  return result;
+}
+
 int err;
 
+static void check_ll(long long val, long long expect)
+{
+if (val != expect) {
+printf("ERROR: 0x%016llx != 0x%016llx\n", val, expect);
+err++;
+}
+}
+
 static void check(int val, int expect)
 {
 if (val != expect) {
@@ -87,10 +120,46 @@ static void test_sfinvsqrta()
 check_p(pred_result, 0x0);
 }
 
+static void test_vacsh()
+{
+long long res64;
+int pred_result;
+int ovf_result;
+
+res64 = vacsh(0x0004000300020001LL,
+  0x0001000200030004LL,
+  0xLL, &pred_result, &ovf_result);
+check_ll(res64, 0x0004000300030004LL);
+check_p(pred_result, 0xf0);
+check(ovf_result, 0);
+
+res64 = vacsh(0x0004000300020001LL,

[PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta

[Richard Henderson]

From: Taylor Simpson 

Rd32,Pe4 = sfinvsqrta(Rs32)
Square root approx

The helper packs the 2 32-bit results into a 64-bit value,
and the fGEN_TCG override unpacks them into the proper results.

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-19-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.h |  2 ++
 target/hexagon/gen_tcg.h  | 16 +++
 target/hexagon/helper.h   |  1 +
 target/hexagon/arch.c | 21 ++-
 target/hexagon/op_helper.c| 21 +++
 tests/tcg/hexagon/fpstuff.c   | 15 ++
 tests/tcg/hexagon/multi_result.c  | 29 +++
 target/hexagon/imported/encode_pp.def |  1 +
 target/hexagon/imported/float.idef| 16 +++
 9 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h
index b6634e9615..3e0c334209 100644
--- a/target/hexagon/arch.h
+++ b/target/hexagon/arch.h
@@ -32,4 +32,6 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int 
*adjust,
 
 extern const uint8_t recip_lookup_table[128];
 
+extern const uint8_t invsqrt_lookup_table[128];
+
 #endif
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 428a670281..d78e7b8e5c 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -216,6 +216,22 @@
 tcg_temp_free_i64(tmp); \
 } while (0)
 
+/*
+ * Approximation of the reciprocal square root
+ * r1,p0 = sfinvsqrta(r0)
+ *
+ * The helper packs the 2 32-bit results into a 64-bit value,
+ * so unpack them into the proper results.
+ */
+#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
+do { \
+TCGv_i64 tmp = tcg_temp_new_i64(); \
+gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
+tcg_gen_extrh_i64_i32(RdV, tmp); \
+tcg_gen_extrl_i64_i32(PeV, tmp); \
+tcg_temp_free_i64(tmp); \
+} while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
 gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index b377293dd3..cb7508f746 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -25,6 +25,7 @@ DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, 
env, int, int)
 DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
 DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
+DEF_HELPER_2(sfinvsqrta, i64, env, f32)
 
 /* Floating point */
 DEF_HELPER_2(conv_sf2df, f64, env, f32)
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index 46edf45b13..dee852e106 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -247,7 +247,7 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int 
*adjust,
 int r_exp;
 int ret = 0;
 RsV = *Rs;
-if (float32_is_infinity(RsV)) {
+if (float32_is_any_nan(RsV)) {
 if (extract32(RsV, 22, 1) == 0) {
 float_raise(float_flag_invalid, fp_status);
 }
@@ -299,3 +299,22 @@ const uint8_t recip_lookup_table[128] = {
 0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00b, 0x00a, 0x009,
 0x008, 0x007, 0x006, 0x005, 0x004, 0x003, 0x002, 0x000,
 };
+
+const uint8_t invsqrt_lookup_table[128] = {
+0x069, 0x066, 0x063, 0x061, 0x05e, 0x05b, 0x059, 0x057,
+0x054, 0x052, 0x050, 0x04d, 0x04b, 0x049, 0x047, 0x045,
+0x043, 0x041, 0x03f, 0x03d, 0x03b, 0x039, 0x037, 0x036,
+0x034, 0x032, 0x030, 0x02f, 0x02d, 0x02c, 0x02a, 0x028,
+0x027, 0x025, 0x024, 0x022, 0x021, 0x01f, 0x01e, 0x01d,
+0x01b, 0x01a, 0x019, 0x017, 0x016, 0x015, 0x014, 0x012,
+0x011, 0x010, 0x00f, 0x00d, 0x00c, 0x00b, 0x00a, 0x009,
+0x008, 0x007, 0x006, 0x005, 0x004, 0x003, 0x002, 0x001,
+0x0fe, 0x0fa, 0x0f6, 0x0f3, 0x0ef, 0x0eb, 0x0e8, 0x0e4,
+0x0e1, 0x0de, 0x0db, 0x0d7, 0x0d4, 0x0d1, 0x0ce, 0x0cb,
+0x0c9, 0x0c6, 0x0c3, 0x0c0, 0x0be, 0x0bb, 0x0b8, 0x0b6,
+0x0b3, 0x0b1, 0x0af, 0x0ac, 0x0aa, 0x0a8, 0x0a5, 0x0a3,
+0x0a1, 0x09f, 0x09d, 0x09b, 0x099, 0x097, 0x095, 0x093,
+0x091, 0x08f, 0x08d, 0x08b, 0x089, 0x087, 0x086, 0x084,
+0x082, 0x080, 0x07f, 0x07d, 0x07b, 0x07a, 0x078, 0x077,
+0x075, 0x074, 0x072, 0x071, 0x06f, 0x06e, 0x06c, 0x06b,
+};
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 75861e26c4..a25fb98f24 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -326,6 +326,27 @@ uint64_t HELPER(sfrecipa)(CPUHexagonState *env, float32 
RsV, float32 RtV)
 return ((uint64_t)RdV << 32) | PeV;
 }
 
+uint64_t HELPER(sfinvsqrta)(CPUHexagonState *env, float32 RsV)
+{
+int PeV = 0;
+float32 RdV;
+int idx;
+int adjust;
+int mant;
+int exp;
+
+arch_fpop_start(env);
+if (arch_sf_invsqrt_common(&RsV, &RdV, &adjus

[PULL 29/31] Hexagon (target/hexagon) load and unpack bytes instructions

[Richard Henderson]

From: Taylor Simpson 

The following instructions are added
L2_loadbzw2_io  Rd32 = memubh(Rs32+#s11:1)
L2_loadbzw4_io  Rdd32 = memubh(Rs32+#s11:1)
L2_loadbsw2_io  Rd32 = membh(Rs32+#s11:1)
L2_loadbsw4_io  Rdd32 = membh(Rs32+#s11:1)

L4_loadbzw2_ur  Rd32 = memubh(Rt32<<#u2+#U6)
L4_loadbzw4_ur  Rdd32 = memubh(Rt32<<#u2+#U6)
L4_loadbsw2_ur  Rd32 = membh(Rt32<<#u2+#U6)
L4_loadbsw4_ur  Rdd32 = membh(Rt32<<#u2+#U6)

L4_loadbzw2_ap  Rd32 = memubh(Re32=#U6)
L4_loadbzw4_ap  Rdd32 = memubh(Re32=#U6)
L4_loadbsw2_ap  Rd32 = membh(Re32=#U6)
L4_loadbsw4_ap  Rdd32 = membh(Re32=#U6)

L2_loadbzw2_pr  Rd32 = memubh(Rx32++Mu2)
L2_loadbzw4_pr  Rdd32 = memubh(Rx32++Mu2)
L2_loadbsw2_pr  Rd32 = membh(Rx32++Mu2)
L2_loadbsw4_pr  Rdd32 = membh(Rx32++Mu2)

L2_loadbzw2_pbr Rd32 = memubh(Rx32++Mu2:brev)
L2_loadbzw4_pbr Rdd32 = memubh(Rx32++Mu2:brev)
L2_loadbsw2_pbr Rd32 = membh(Rx32++Mu2:brev)
L2_loadbsw4_pbr Rdd32 = membh(Rx32++Mu2:brev)

L2_loadbzw2_pi  Rd32 = memubh(Rx32++#s4:1)
L2_loadbzw4_pi  Rdd32 = memubh(Rx32++#s4:1)
L2_loadbsw2_pi  Rd32 = membh(Rx32++#s4:1)
L2_loadbsw4_pi  Rdd32 = membh(Rx32++#s4:1)

L2_loadbzw2_pci Rd32 = memubh(Rx32++#s4:1:circ(Mu2))
L2_loadbzw4_pci Rdd32 = memubh(Rx32++#s4:1:circ(Mu2))
L2_loadbsw2_pci Rd32 = membh(Rx32++#s4:1:circ(Mu2))
L2_loadbsw4_pci Rdd32 = membh(Rx32++#s4:1:circ(Mu2))

L2_loadbzw2_pcr Rd32 = memubh(Rx32++I:circ(Mu2))
L2_loadbzw4_pcr Rdd32 = memubh(Rx32++I:circ(Mu2))
L2_loadbsw2_pcr Rd32 = membh(Rx32++I:circ(Mu2))
L2_loadbsw4_pcr Rdd32 = membh(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_unpack.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-25-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  | 108 ++
 target/hexagon/macros.h   |  16 +
 target/hexagon/genptr.c   |  13 +
 tests/tcg/hexagon/load_unpack.c   | 474 ++
 target/hexagon/imported/encode_pp.def |   6 +
 target/hexagon/imported/ldst.idef |  43 +++
 tests/tcg/hexagon/Makefile.target |   1 +
 7 files changed, 661 insertions(+)
 create mode 100644 tests/tcg/hexagon/load_unpack.c

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 8f0ec01f0a..1120aaed4e 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -152,6 +152,114 @@
 #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE)   SHORTCODE
 
+/*
+ * These instructions load 2 bytes and places them in
+ * two halves of the destination register.
+ * The GET_EA macro determines the addressing mode.
+ * The SIGN argument determines whether to zero-extend or
+ * sign-extend.
+ */
+#define fGEN_TCG_loadbXw2(GET_EA, SIGN) \
+do { \
+TCGv tmp = tcg_temp_new(); \
+TCGv byte = tcg_temp_new(); \
+GET_EA; \
+fLOAD(1, 2, u, EA, tmp); \
+tcg_gen_movi_tl(RdV, 0); \
+for (int i = 0; i < 2; i++) { \
+gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \
+} \
+tcg_temp_free(tmp); \
+tcg_temp_free(byte); \
+} while (0)
+
+#define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \
+fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false)
+#define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \
+fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false)
+#define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \
+fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true)
+#define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \
+fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true)
+#define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_ap, false)
+#define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pr, false)
+#define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pbr, false)
+#define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pi, false)
+#define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_ap, true)
+#define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pr, true)
+#define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pbr, true)
+#define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pi, true)
+#define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pci, false)
+#define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pci, true)
+#define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pcr(1), false)
+#define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \
+fGEN_TCG_loadbXw2(GET_EA_pcr(1), true)
+
+/*
+ * These instructi

[PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction

[Richard Henderson]

From: Taylor Simpson 

Rd32,Pe4 = sfrecipa(Rs32, Rt32)
Recripocal approx

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-18-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.h |  2 +
 target/hexagon/gen_tcg.h  | 21 +++
 target/hexagon/helper.h   |  1 +
 target/hexagon/arch.c | 26 -
 target/hexagon/op_helper.c| 37 
 tests/tcg/hexagon/fpstuff.c   | 82 +++
 tests/tcg/hexagon/multi_result.c  | 68 ++
 target/hexagon/imported/encode_pp.def |  1 +
 target/hexagon/imported/float.idef| 16 ++
 tests/tcg/hexagon/Makefile.target |  1 +
 10 files changed, 252 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/hexagon/multi_result.c

diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h
index 6e0b0d9a24..b6634e9615 100644
--- a/target/hexagon/arch.h
+++ b/target/hexagon/arch.h
@@ -30,4 +30,6 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 
*Rd,
 int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
   float_status *fp_status);
 
+extern const uint8_t recip_lookup_table[128];
+
 #endif
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index a30048ee57..428a670281 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -195,6 +195,27 @@
 #define fGEN_TCG_S4_stored_locked(SHORTCODE) \
 do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
 
+/*
+ * Mathematical operations with more than one definition require
+ * special handling
+ */
+
+/*
+ * Approximate reciprocal
+ * r3,p1 = sfrecipa(r0, r1)
+ *
+ * The helper packs the 2 32-bit results into a 64-bit value,
+ * so unpack them into the proper results.
+ */
+#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
+do { \
+TCGv_i64 tmp = tcg_temp_new_i64(); \
+gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV);  \
+tcg_gen_extrh_i64_i32(RdV, tmp); \
+tcg_gen_extrl_i64_i32(PeV, tmp); \
+tcg_temp_free_i64(tmp); \
+} while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
 gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index efe6069118..b377293dd3 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -24,6 +24,7 @@ DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, 
void, env, int, int)
 DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int)
 DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
+DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
 
 /* Floating point */
 DEF_HELPER_2(conv_sf2df, f64, env, f32)
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index 40b6e3d0c0..46edf45b13 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -181,12 +181,13 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, 
float32 *Rd, int *adjust,
 /* or put Inf in num fixup? */
 uint8_t RsV_sign = float32_is_neg(RsV);
 uint8_t RtV_sign = float32_is_neg(RtV);
+/* Check that RsV is NOT infinite before we overwrite it */
+if (!float32_is_infinity(RsV)) {
+float_raise(float_flag_divbyzero, fp_status);
+}
 RsV = infinite_float32(RsV_sign ^ RtV_sign);
 RtV = float32_one;
 RdV = float32_one;
-if (float32_is_infinity(RsV)) {
-float_raise(float_flag_divbyzero, fp_status);
-}
 } else if (float32_is_infinity(RtV)) {
 RsV = make_float32(0x8000 & (RsV ^ RtV));
 RtV = float32_one;
@@ -279,3 +280,22 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int 
*adjust,
 *adjust = PeV;
 return ret;
 }
+
+const uint8_t recip_lookup_table[128] = {
+0x0fe, 0x0fa, 0x0f6, 0x0f2, 0x0ef, 0x0eb, 0x0e7, 0x0e4,
+0x0e0, 0x0dd, 0x0d9, 0x0d6, 0x0d2, 0x0cf, 0x0cc, 0x0c9,
+0x0c6, 0x0c2, 0x0bf, 0x0bc, 0x0b9, 0x0b6, 0x0b3, 0x0b1,
+0x0ae, 0x0ab, 0x0a8, 0x0a5, 0x0a3, 0x0a0, 0x09d, 0x09b,
+0x098, 0x096, 0x093, 0x091, 0x08e, 0x08c, 0x08a, 0x087,
+0x085, 0x083, 0x080, 0x07e, 0x07c, 0x07a, 0x078, 0x075,
+0x073, 0x071, 0x06f, 0x06d, 0x06b, 0x069, 0x067, 0x065,
+0x063, 0x061, 0x05f, 0x05e, 0x05c, 0x05a, 0x058, 0x056,
+0x054, 0x053, 0x051, 0x04f, 0x04e, 0x04c, 0x04a, 0x049,
+0x047, 0x045, 0x044, 0x042, 0x040, 0x03f, 0x03d, 0x03c,
+0x03a, 0x039, 0x037, 0x036, 0x034, 0x033, 0x032, 0x030,
+0x02f, 0x02d, 0x02c, 0x02b, 0x029, 0x028, 0x027, 0x025,
+0x024, 0x023, 0x021, 0x020, 0x01f, 0x01e, 0x01c, 0x01b,
+0x01a, 0x019, 0x017, 0x016, 0x015, 0x014, 0x013, 0x012,
+0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00b, 0x00a, 0x009,
+0x008, 0x007, 0x006, 0x005, 0x004, 0x003

[PULL 5/5] decodetree: Extend argument set syntax to allow types

[Richard Henderson]

Rather than force all structure members to be 'int',
allow the type of the member to be specified.

Reviewed-by: Luis Pires 
Signed-off-by: Richard Henderson 
---
 docs/devel/decodetree.rst | 11 ---
 tests/decode/succ_argset_type1.decode |  1 +
 scripts/decodetree.py | 45 +--
 3 files changed, 36 insertions(+), 21 deletions(-)
 create mode 100644 tests/decode/succ_argset_type1.decode

diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
index 74f66bf46e..49ea50c2a7 100644
--- a/docs/devel/decodetree.rst
+++ b/docs/devel/decodetree.rst
@@ -40,9 +40,6 @@ and returns an integral value extracted from there.
 
 A field with no ``unnamed_fields`` and no ``!function`` is in error.
 
-FIXME: the fields of the structure into which this result will be stored
-is restricted to ``int``.  Which means that we cannot expand 64-bit items.
-
 Field examples:
 
 +---+-+
@@ -66,9 +63,14 @@ Argument Sets
 Syntax::
 
   args_def:= '&' identifier ( args_elt )+ ( !extern )?
-  args_elt:= identifier
+  args_elt:= identifier (':' identifier)?
 
 Each *args_elt* defines an argument within the argument set.
+If the form of the *args_elt* contains a colon, the first
+identifier is the argument name and the second identifier is
+the argument type.  If the colon is missing, the argument
+type will be ``int``.
+
 Each argument set will be rendered as a C structure "arg_$name"
 with each of the fields being one of the member arguments.
 
@@ -86,6 +88,7 @@ Argument set examples::
 
   ®3   ra rb rc
   &loadstore  reg base offset
+  &longldst   reg base offset:int64_t
 
 
 Formats
diff --git a/tests/decode/succ_argset_type1.decode 
b/tests/decode/succ_argset_type1.decode
new file mode 100644
index 00..ed946b420d
--- /dev/null
+++ b/tests/decode/succ_argset_type1.decode
@@ -0,0 +1 @@
+&asdf b:bool c:uint64_t a
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index f85da45ee3..a03dc6b5e3 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -165,11 +165,15 @@ def is_contiguous(bits):
 return -1
 
 
-def eq_fields_for_args(flds_a, flds_b):
-if len(flds_a) != len(flds_b):
+def eq_fields_for_args(flds_a, arg):
+if len(flds_a) != len(arg.fields):
 return False
+# Only allow inference on default types
+for t in arg.types:
+if t != 'int':
+return False
 for k, a in flds_a.items():
-if k not in flds_b:
+if k not in arg.fields:
 return False
 return True
 
@@ -313,10 +317,11 @@ def __ne__(self, other):
 
 class Arguments:
 """Class representing the extracted fields of a format"""
-def __init__(self, nm, flds, extern):
+def __init__(self, nm, flds, types, extern):
 self.name = nm
 self.extern = extern
-self.fields = sorted(flds)
+self.fields = flds
+self.types = types
 
 def __str__(self):
 return self.name + ' ' + str(self.fields)
@@ -327,8 +332,8 @@ def struct_name(self):
 def output_def(self):
 if not self.extern:
 output('typedef struct {\n')
-for n in self.fields:
-output('int ', n, ';\n')
+for (n, t) in zip(self.fields, self.types):
+output(f'{t} {n};\n')
 output('} ', self.struct_name(), ';\n\n')
 # end Arguments
 
@@ -719,21 +724,27 @@ def parse_arguments(lineno, name, toks):
 global anyextern
 
 flds = []
+types = []
 extern = False
-for t in toks:
-if re.fullmatch('!extern', t):
+for n in toks:
+if re.fullmatch('!extern', n):
 extern = True
 anyextern = True
 continue
-if not re.fullmatch(re_C_ident, t):
-error(lineno, f'invalid argument set token "{t}"')
-if t in flds:
-error(lineno, f'duplicate argument "{t}"')
-flds.append(t)
+if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
+(n, t) = n.split(':')
+elif re.fullmatch(re_C_ident, n):
+t = 'int'
+else:
+error(lineno, f'invalid argument set token "{n}"')
+if n in flds:
+error(lineno, f'duplicate argument "{n}"')
+flds.append(n)
+types.append(t)
 
 if name in arguments:
 error(lineno, 'duplicate argument set', name)
-arguments[name] = Arguments(name, flds, extern)
+arguments[name] = Arguments(name, flds, types, extern)
 # end parse_arguments
 
 
@@ -760,11 +771,11 @@ def infer_argument_set(flds):
 global decode_function
 
 for arg in arguments.values():
-if eq_fields_for_args(flds, arg.fields):
+if eq_fields_for_args(flds, arg):
 return arg
 
 name = decode_function + str(len(arguments))
-arg = Arguments(name, flds.keys(), False)
+arg = Arguments(name, flds.keys(), ['int'] * len(f

[PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics

[Richard Henderson]

From: Taylor Simpson 

Change  (cond ? (res = x) : (res = y)) to res = (cond ? x : y)

This makes the semnatics easier to for idef-parser to deal with

The following instructions are impacted
C2_any8
C2_all8
C2_mux
C2_muxii
C2_muxir
C2_muxri

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-14-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/imported/compare.idef | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/hexagon/imported/compare.idef 
b/target/hexagon/imported/compare.idef
index 3551467854..abd016ffb5 100644
--- a/target/hexagon/imported/compare.idef
+++ b/target/hexagon/imported/compare.idef
@@ -198,11 +198,11 @@ 
Q6INSN(C4_or_orn,"Pd4=or(Ps4,or(Pt4,!Pu4))",ATTRIBS(A_CRSLOT23),
 
 Q6INSN(C2_any8,"Pd4=any8(Ps4)",ATTRIBS(A_CRSLOT23),
 "Logical ANY of low 8 predicate bits",
-{ PsV ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV ? 0xff : 0x00); })
 
 Q6INSN(C2_all8,"Pd4=all8(Ps4)",ATTRIBS(A_CRSLOT23),
 "Logical ALL of low 8 predicate bits",
-{ (PsV==0xff) ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV == 0xff ? 0xff : 0x00); })
 
 Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
 "Pack the odd and even bits of two predicate registers",
@@ -212,7 +212,7 @@ Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
 
 Q6INSN(C2_mux,"Rd32=mux(Pu4,Rs32,Rt32)",ATTRIBS(),
 "Scalar MUX",
-{ (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=RtV); })
+{ RdV = (fLSBOLD(PuV) ? RsV : RtV); })
 
 
 Q6INSN(C2_cmovenewit,"if (Pu4.new) Rd32=#s12",ATTRIBS(A_ARCHV2),
@@ -269,18 +269,18 @@ Q6INSN(C2_ccombinewf,"if (!Pu4) 
Rdd32=combine(Rs32,Rt32)",ATTRIBS(A_ARCHV2),
 
 Q6INSN(C2_muxii,"Rd32=mux(Pu4,#s8,#S8)",ATTRIBS(A_ARCHV2),
 "Scalar MUX immediates",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=SiV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : SiV); })
 
 
 
 Q6INSN(C2_muxir,"Rd32=mux(Pu4,Rs32,#s8)",ATTRIBS(A_ARCHV2),
 "Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=siV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? RsV : siV); })
 
 
 Q6INSN(C2_muxri,"Rd32=mux(Pu4,#s8,Rs32)",ATTRIBS(A_ARCHV2),
 "Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=RsV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : RsV); })
 
 
 
-- 
2.25.1

[PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Philippe Mathieu-Daudé 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-16-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/genptr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 6b74344795..b87e264ccf 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -15,7 +15,6 @@
  *  along with this program; if not, see .
  */
 
-#define QEMU_GENERATE
 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "cpu.h"
@@ -24,7 +23,9 @@
 #include "insn.h"
 #include "opcodes.h"
 #include "translate.h"
+#define QEMU_GENERATE   /* Used internally by macros.h */
 #include "macros.h"
+#undef QEMU_GENERATE
 #include "gen_tcg.h"
 
 static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
-- 
2.25.1

[PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions

[Richard Henderson]

From: Taylor Simpson 

Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-13-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/conv_emu.h   |  31 ---
 target/hexagon/helper.h |  16 ++--
 target/hexagon/conv_emu.c   | 177 
 target/hexagon/fma_emu.c|   1 -
 target/hexagon/op_helper.c  | 169 +-
 tests/tcg/hexagon/fpstuff.c | 145 +
 target/hexagon/meson.build  |   1 -
 7 files changed, 281 insertions(+), 259 deletions(-)
 delete mode 100644 target/hexagon/conv_emu.h
 delete mode 100644 target/hexagon/conv_emu.c

diff --git a/target/hexagon/conv_emu.h b/target/hexagon/conv_emu.h
deleted file mode 100644
index cade9de91f..00
--- a/target/hexagon/conv_emu.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, see .
- */
-
-#ifndef HEXAGON_CONV_EMU_H
-#define HEXAGON_CONV_EMU_H
-
-uint64_t conv_sf_to_8u(float32 in, float_status *fp_status);
-uint32_t conv_sf_to_4u(float32 in, float_status *fp_status);
-int64_t conv_sf_to_8s(float32 in, float_status *fp_status);
-int32_t conv_sf_to_4s(float32 in, float_status *fp_status);
-
-uint64_t conv_df_to_8u(float64 in, float_status *fp_status);
-uint32_t conv_df_to_4u(float64 in, float_status *fp_status);
-int64_t conv_df_to_8s(float64 in, float_status *fp_status);
-int32_t conv_df_to_4s(float64 in, float_status *fp_status);
-
-#endif
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index a5f340ce67..715c24662f 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -38,21 +38,21 @@ DEF_HELPER_2(conv_ud2sf, f32, env, s64)
 DEF_HELPER_2(conv_ud2df, f64, env, s64)
 DEF_HELPER_2(conv_d2sf, f32, env, s64)
 DEF_HELPER_2(conv_d2df, f64, env, s64)
-DEF_HELPER_2(conv_sf2uw, s32, env, f32)
+DEF_HELPER_2(conv_sf2uw, i32, env, f32)
 DEF_HELPER_2(conv_sf2w, s32, env, f32)
-DEF_HELPER_2(conv_sf2ud, s64, env, f32)
+DEF_HELPER_2(conv_sf2ud, i64, env, f32)
 DEF_HELPER_2(conv_sf2d, s64, env, f32)
-DEF_HELPER_2(conv_df2uw, s32, env, f64)
+DEF_HELPER_2(conv_df2uw, i32, env, f64)
 DEF_HELPER_2(conv_df2w, s32, env, f64)
-DEF_HELPER_2(conv_df2ud, s64, env, f64)
+DEF_HELPER_2(conv_df2ud, i64, env, f64)
 DEF_HELPER_2(conv_df2d, s64, env, f64)
-DEF_HELPER_2(conv_sf2uw_chop, s32, env, f32)
+DEF_HELPER_2(conv_sf2uw_chop, i32, env, f32)
 DEF_HELPER_2(conv_sf2w_chop, s32, env, f32)
-DEF_HELPER_2(conv_sf2ud_chop, s64, env, f32)
+DEF_HELPER_2(conv_sf2ud_chop, i64, env, f32)
 DEF_HELPER_2(conv_sf2d_chop, s64, env, f32)
-DEF_HELPER_2(conv_df2uw_chop, s32, env, f64)
+DEF_HELPER_2(conv_df2uw_chop, i32, env, f64)
 DEF_HELPER_2(conv_df2w_chop, s32, env, f64)
-DEF_HELPER_2(conv_df2ud_chop, s64, env, f64)
+DEF_HELPER_2(conv_df2ud_chop, i64, env, f64)
 DEF_HELPER_2(conv_df2d_chop, s64, env, f64)
 DEF_HELPER_3(sfadd, f32, env, f32, f32)
 DEF_HELPER_3(sfsub, f32, env, f32, f32)
diff --git a/target/hexagon/conv_emu.c b/target/hexagon/conv_emu.c
deleted file mode 100644
index 3985b1032a..00
--- a/target/hexagon/conv_emu.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, see .
- */
-
-#include "qemu/osdep.h"
-#include "qemu/host-utils.h"
-#include "fpu/softfloat.h"
-#include "macros.h"
-#include "conv_emu.h"
-
-#define LL_MAX_POS 0x7fffULL
-#define MAX_POS 0x7fffU
-
-static uint64_t conv_f64_to_8u_n(float64 in

[PULL 1/5] exec: Remove accel/tcg/ from include paths

[Richard Henderson]

From: Philippe Mathieu-Daudé 

When TCG is enabled, the accel/tcg/ include path is added to the
project global include search list. This accel/tcg/ directory
contains a header named "internal.h" which, while intented to
be internal to accel/tcg/, is accessible by all files compiled
when TCG is enabled. This might lead to problem with other
directories using the same "internal.h" header name:

  $ git ls-files | fgrep /internal.h
  accel/tcg/internal.h
  include/hw/ide/internal.h
  target/hexagon/internal.h
  target/mips/internal.h
  target/ppc/internal.h
  target/s390x/internal.h

As we don't need to expose accel/tcg/ internals to the rest of
the code base, simplify by removing it from the include search
list, and include the accel/tcg/ public headers relative to the
project root search path (which is already in the generic include
search path).

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Claudio Fontana 
Message-Id: <20210413081008.3409459-1-f4...@amsat.org>
Signed-off-by: Richard Henderson 
---
 meson.build | 1 -
 include/exec/helper-gen.h   | 4 ++--
 include/exec/helper-proto.h | 4 ++--
 include/exec/helper-tcg.h   | 4 ++--
 4 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/meson.build b/meson.build
index c6f4b0cf5e..d8bb1ec5aa 100644
--- a/meson.build
+++ b/meson.build
@@ -258,7 +258,6 @@ if not get_option('tcg').disabled()
 tcg_arch = 'riscv'
   endif
   add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / 
tcg_arch,
-'-iquote', meson.current_source_dir() / 'accel/tcg',
 language: ['c', 'cpp', 'objc'])
 
   accelerators += 'CONFIG_TCG'
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index 29c02f85dc..1c2e7a8ed3 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -81,8 +81,8 @@ static inline void glue(gen_helper_, 
name)(dh_retvar_decl(ret)  \
 #include "helper.h"
 #include "trace/generated-helpers.h"
 #include "trace/generated-helpers-wrappers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef DEF_HELPER_FLAGS_0
 #undef DEF_HELPER_FLAGS_1
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index 659f9298e8..ba100793a7 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -39,8 +39,8 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), 
dh_ctype(t3), \
 
 #include "helper.h"
 #include "trace/generated-helpers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef IN_HELPER_PROTO
 
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
index 27870509a2..6888514635 100644
--- a/include/exec/helper-tcg.h
+++ b/include/exec/helper-tcg.h
@@ -60,8 +60,8 @@
 
 #include "helper.h"
 #include "trace/generated-helpers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef str
 #undef DEF_HELPER_FLAGS_0
-- 
2.25.1

[PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-11-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/cpu.c   |  5 
 target/hexagon/op_helper.c | 47 --
 fpu/softfloat-specialize.c.inc |  3 +++
 3 files changed, 8 insertions(+), 47 deletions(-)

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index f044506d0f..ff44fd6637 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -23,6 +23,7 @@
 #include "exec/exec-all.h"
 #include "qapi/error.h"
 #include "hw/qdev-properties.h"
+#include "fpu/softfloat-helpers.h"
 
 static void hexagon_v67_cpu_init(Object *obj)
 {
@@ -205,8 +206,12 @@ static void hexagon_cpu_reset(DeviceState *dev)
 CPUState *cs = CPU(dev);
 HexagonCPU *cpu = HEXAGON_CPU(cs);
 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
+CPUHexagonState *env = &cpu->env;
 
 mcc->parent_reset(dev);
+
+set_default_nan_mode(1, &env->fp_status);
+set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
 }
 
 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 1d91fa2743..478421d147 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -296,26 +296,6 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, 
int32_t M, int32_t CS)
 return new_ptr;
 }
 
-/*
- * Hexagon FP operations return ~0 instead of NaN
- * The hex_check_sfnan/hex_check_dfnan functions perform this check
- */
-static float32 hex_check_sfnan(float32 x)
-{
-if (float32_is_any_nan(x)) {
-return make_float32(0xU);
-}
-return x;
-}
-
-static float64 hex_check_dfnan(float64 x)
-{
-if (float64_is_any_nan(x)) {
-return make_float64(0xULL);
-}
-return x;
-}
-
 /*
  * mem_noshuf
  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
@@ -373,7 +353,6 @@ float64 HELPER(conv_sf2df)(CPUHexagonState *env, float32 
RsV)
 float64 out_f64;
 arch_fpop_start(env);
 out_f64 = float32_to_float64(RsV, &env->fp_status);
-out_f64 = hex_check_dfnan(out_f64);
 arch_fpop_end(env);
 return out_f64;
 }
@@ -383,7 +362,6 @@ float32 HELPER(conv_df2sf)(CPUHexagonState *env, float64 
RssV)
 float32 out_f32;
 arch_fpop_start(env);
 out_f32 = float64_to_float32(RssV, &env->fp_status);
-out_f32 = hex_check_sfnan(out_f32);
 arch_fpop_end(env);
 return out_f32;
 }
@@ -393,7 +371,6 @@ float32 HELPER(conv_uw2sf)(CPUHexagonState *env, int32_t 
RsV)
 float32 RdV;
 arch_fpop_start(env);
 RdV = uint32_to_float32(RsV, &env->fp_status);
-RdV = hex_check_sfnan(RdV);
 arch_fpop_end(env);
 return RdV;
 }
@@ -403,7 +380,6 @@ float64 HELPER(conv_uw2df)(CPUHexagonState *env, int32_t 
RsV)
 float64 RddV;
 arch_fpop_start(env);
 RddV = uint32_to_float64(RsV, &env->fp_status);
-RddV = hex_check_dfnan(RddV);
 arch_fpop_end(env);
 return RddV;
 }
@@ -413,7 +389,6 @@ float32 HELPER(conv_w2sf)(CPUHexagonState *env, int32_t RsV)
 float32 RdV;
 arch_fpop_start(env);
 RdV = int32_to_float32(RsV, &env->fp_status);
-RdV = hex_check_sfnan(RdV);
 arch_fpop_end(env);
 return RdV;
 }
@@ -423,7 +398,6 @@ float64 HELPER(conv_w2df)(CPUHexagonState *env, int32_t RsV)
 float64 RddV;
 arch_fpop_start(env);
 RddV = int32_to_float64(RsV, &env->fp_status);
-RddV = hex_check_dfnan(RddV);
 arch_fpop_end(env);
 return RddV;
 }
@@ -433,7 +407,6 @@ float32 HELPER(conv_ud2sf)(CPUHexagonState *env, int64_t 
RssV)
 float32 RdV;
 arch_fpop_start(env);
 RdV = uint64_to_float32(RssV, &env->fp_status);
-RdV = hex_check_sfnan(RdV);
 arch_fpop_end(env);
 return RdV;
 }
@@ -443,7 +416,6 @@ float64 HELPER(conv_ud2df)(CPUHexagonState *env, int64_t 
RssV)
 float64 RddV;
 arch_fpop_start(env);
 RddV = uint64_to_float64(RssV, &env->fp_status);
-RddV = hex_check_dfnan(RddV);
 arch_fpop_end(env);
 return RddV;
 }
@@ -453,7 +425,6 @@ float32 HELPER(conv_d2sf)(CPUHexagonState *env, int64_t 
RssV)
 float32 RdV;
 arch_fpop_start(env);
 RdV = int64_to_float32(RssV, &env->fp_status);
-RdV = hex_check_sfnan(RdV);
 arch_fpop_end(env);
 return RdV;
 }
@@ -463,7 +434,6 @@ float64 HELPER(conv_d2df)(CPUHexagonState *env, int64_t 
RssV)
 float64 RddV;
 arch_fpop_start(env);
 RddV = int64_to_float64(RssV, &env->fp_status);
-RddV = hex_check_dfnan(RddV);
 arch_fpop_end(env);
 return RddV;
 }
@@ -625,7 +595,6 @@ float32 HELPER(sfadd)(CPUHexagonState *env, float32 RsV, 
float32 RtV)
 float32 RdV;
 arch_fpop_start(env);
 RdV = float32_add(RsV, RtV, &env->fp_status);
-RdV = hex_check_sfnan(RdV);
 arch_fpop_end(env);
 return RdV;
 }
@@ -635,7 +604,6 @@ flo

[PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-10-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index 699e2cfb8f..bb51f19a3d 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -95,7 +95,7 @@ int32_t conv_round(int32_t a, int n)
 
 /* Floating Point Stuff */
 
-static const int softfloat_roundingmodes[] = {
+static const FloatRoundMode softfloat_roundingmodes[] = {
 float_round_nearest_even,
 float_round_to_zero,
 float_round_down,
-- 
2.25.1

[PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-9-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.h   |  1 -
 target/hexagon/macros.h |  2 --
 target/hexagon/arch.c   | 13 -
 3 files changed, 16 deletions(-)

diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h
index 1f7f03693a..6e0b0d9a24 100644
--- a/target/hexagon/arch.h
+++ b/target/hexagon/arch.h
@@ -22,7 +22,6 @@
 
 uint64_t interleave(uint32_t odd, uint32_t even);
 uint64_t deinterleave(uint64_t src);
-uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c);
 int32_t conv_round(int32_t a, int n);
 void arch_fpop_start(CPUHexagonState *env);
 void arch_fpop_end(CPUHexagonState *env);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index cfcb8173ba..8cb211dfde 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -341,8 +341,6 @@ static inline void gen_logical_not(TCGv dest, TCGv src)
 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 
-#define fCARRY_FROM_ADD(A, B, C) carry_from_add64(A, B, C)
-
 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index 09de124818..699e2cfb8f 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -76,19 +76,6 @@ uint64_t deinterleave(uint64_t src)
 return myeven | (myodd << 32);
 }
 
-uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c)
-{
-uint64_t tmpa, tmpb, tmpc;
-tmpa = fGETUWORD(0, a);
-tmpb = fGETUWORD(0, b);
-tmpc = tmpa + tmpb + c;
-tmpa = fGETUWORD(1, a);
-tmpb = fGETUWORD(1, b);
-tmpc = tmpa + tmpb + fGETUWORD(1, tmpc);
-tmpc = fGETUWORD(1, tmpc);
-return tmpc;
-}
-
 int32_t conv_round(int32_t a, int n)
 {
 int64_t val;
-- 
2.25.1

[PULL 30/31] Hexagon (target/hexagon) load into shifted register instructions

[Richard Henderson]

From: Taylor Simpson 

The following instructions are added
L2_loadalignb_io  Ryy32 = memb_fifo(Rs32+#s11:1)
L2_loadalignh_io  Ryy32 = memh_fifo(Rs32+#s11:1)
L4_loadalignb_ur  Ryy32 = memb_fifo(Rt32<<#u2+#U6)
L4_loadalignh_ur  Ryy32 = memh_fifo(Rt32<<#u2+#U6)
L4_loadalignb_ap  Ryy32 = memb_fifo(Re32=#U6)
L4_loadalignh_ap  Ryy32 = memh_fifo(Re32=#U6)
L2_loadalignb_pr  Ryy32 = memb_fifo(Rx32++Mu2)
L2_loadalignh_pr  Ryy32 = memh_fifo(Rx32++Mu2)
L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev)
L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev)
L2_loadalignb_pi  Ryy32 = memb_fifo(Rx32++#s4:1)
L2_loadalignh_pi  Ryy32 = memh_fifo(Rx32++#s4:1)
L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2))
L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2))
L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2))
L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_align.c

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-26-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h  |  66 
 tests/tcg/hexagon/load_align.c| 415 ++
 target/hexagon/imported/encode_pp.def |   3 +
 target/hexagon/imported/ldst.idef |  19 ++
 tests/tcg/hexagon/Makefile.target |   1 +
 5 files changed, 504 insertions(+)
 create mode 100644 tests/tcg/hexagon/load_align.c

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 1120aaed4e..18fcdbc7e4 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -260,6 +260,72 @@
 #define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \
 fGEN_TCG_loadbXw4(GET_EA_pi, true)
 
+/*
+ * These instructions load a half word, shift the destination right by 16 bits
+ * and place the loaded value in the high half word of the destination pair.
+ * The GET_EA macro determines the addressing mode.
+ */
+#define fGEN_TCG_loadalignh(GET_EA) \
+do { \
+TCGv tmp = tcg_temp_new(); \
+TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
+GET_EA;  \
+fLOAD(1, 2, u, EA, tmp);  \
+tcg_gen_extu_i32_i64(tmp_i64, tmp); \
+tcg_gen_shri_i64(RyyV, RyyV, 16); \
+tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \
+tcg_temp_free(tmp); \
+tcg_temp_free_i64(tmp_i64); \
+} while (0)
+
+#define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \
+fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV))
+#define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \
+fGEN_TCG_loadalignh(fEA_RI(RsV, siV))
+#define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_pci)
+#define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_pcr(1))
+#define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_ap)
+#define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_pr)
+#define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_pbr)
+#define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \
+fGEN_TCG_loadalignh(GET_EA_pi)
+
+/* Same as above, but loads a byte instead of half word */
+#define fGEN_TCG_loadalignb(GET_EA) \
+do { \
+TCGv tmp = tcg_temp_new(); \
+TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
+GET_EA;  \
+fLOAD(1, 1, u, EA, tmp);  \
+tcg_gen_extu_i32_i64(tmp_i64, tmp); \
+tcg_gen_shri_i64(RyyV, RyyV, 8); \
+tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
+tcg_temp_free(tmp); \
+tcg_temp_free_i64(tmp_i64); \
+} while (0)
+
+#define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \
+fGEN_TCG_loadalignb(fEA_RI(RsV, siV))
+#define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \
+fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV))
+#define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_pci)
+#define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_pcr(0))
+#define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_ap)
+#define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_pr)
+#define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_pbr)
+#define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \
+fGEN_TCG_loadalignb(GET_EA_pi)
+
 /*
  * Predicated loads
  * Here is a primer to understand the tag names
diff --git a/tests/tcg/hexagon/load_align.c b/tests/tcg/hexagon/load_align.c
new file mode 100644
index 00..12fc9cbd8f
--- /dev/null
+++ b/tests/tcg/hexagon/load_align.c
@@ -0,0 +1,415 @@
+/*
+ *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights 
Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Softwa

[PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-12-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/arch.c | 28 +++-
 1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index bb51f19a3d..40b6e3d0c0 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -143,12 +143,6 @@ void arch_fpop_end(CPUHexagonState *env)
 }
 }
 
-static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_status)
-{
-float32 b = make_float32((SF_BIAS + p) << SF_MANTBITS);
-return float32_mul(a, b, fp_status);
-}
-
 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,
  float_status *fp_status)
 {
@@ -217,22 +211,22 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, 
float32 *Rd, int *adjust,
 if ((n_exp - d_exp + SF_BIAS) <= SF_MANTBITS) {
 /* Near quotient underflow / inexact Q */
 PeV = 0x80;
-RtV = float32_mul_pow2(RtV, -64, fp_status);
-RsV = float32_mul_pow2(RsV, 64, fp_status);
+RtV = float32_scalbn(RtV, -64, fp_status);
+RsV = float32_scalbn(RsV, 64, fp_status);
 } else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) {
 /* Near quotient overflow */
 PeV = 0x40;
-RtV = float32_mul_pow2(RtV, 32, fp_status);
-RsV = float32_mul_pow2(RsV, -32, fp_status);
+RtV = float32_scalbn(RtV, 32, fp_status);
+RsV = float32_scalbn(RsV, -32, fp_status);
 } else if (n_exp <= SF_MANTBITS + 2) {
-RtV = float32_mul_pow2(RtV, 64, fp_status);
-RsV = float32_mul_pow2(RsV, 64, fp_status);
+RtV = float32_scalbn(RtV, 64, fp_status);
+RsV = float32_scalbn(RsV, 64, fp_status);
 } else if (d_exp <= 1) {
-RtV = float32_mul_pow2(RtV, 32, fp_status);
-RsV = float32_mul_pow2(RsV, 32, fp_status);
+RtV = float32_scalbn(RtV, 32, fp_status);
+RsV = float32_scalbn(RsV, 32, fp_status);
 } else if (d_exp > 252) {
-RtV = float32_mul_pow2(RtV, -32, fp_status);
-RsV = float32_mul_pow2(RsV, -32, fp_status);
+RtV = float32_scalbn(RtV, -32, fp_status);
+RsV = float32_scalbn(RsV, -32, fp_status);
 }
 RdV = 0;
 ret = 1;
@@ -274,7 +268,7 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int 
*adjust,
 /* Basic checks passed */
 r_exp = float32_getexp(RsV);
 if (r_exp <= 24) {
-RsV = float32_mul_pow2(RsV, 64, fp_status);
+RsV = float32_scalbn(RsV, 64, fp_status);
 PeV = 0xe0;
 }
 RdV = 0;
-- 
2.25.1

[PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN

[Richard Henderson]

From: Taylor Simpson 

When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-6-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/translate.h |  3 --
 target/hexagon/translate.c | 62 --
 2 files changed, 33 insertions(+), 32 deletions(-)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 938f7fbb9f..12506c8caf 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -86,8 +86,5 @@ extern TCGv hex_llsc_addr;
 extern TCGv hex_llsc_val;
 extern TCGv_i64 hex_llsc_val_i64;
 
-void gen_exception(int excp);
-void gen_exception_debug(void);
-
 void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
 #endif
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index e235fdb315..9f2a531969 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -54,16 +54,40 @@ static const char * const hexagon_prednames[] = {
   "p0", "p1", "p2", "p3"
 };
 
-void gen_exception(int excp)
+static void gen_exception_raw(int excp)
 {
 TCGv_i32 helper_tmp = tcg_const_i32(excp);
 gen_helper_raise_exception(cpu_env, helper_tmp);
 tcg_temp_free_i32(helper_tmp);
 }
 
-void gen_exception_debug(void)
+static void gen_exec_counters(DisasContext *ctx)
 {
-gen_exception(EXCP_DEBUG);
+tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
+hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
+tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
+hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
+}
+
+static void gen_end_tb(DisasContext *ctx)
+{
+gen_exec_counters(ctx);
+tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
+if (ctx->base.singlestep_enabled) {
+gen_exception_raw(EXCP_DEBUG);
+} else {
+tcg_gen_exit_tb(NULL, 0);
+}
+ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static void gen_exception_end_tb(DisasContext *ctx, int excp)
+{
+gen_exec_counters(ctx);
+tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
+gen_exception_raw(excp);
+ctx->base.is_jmp = DISAS_NORETURN;
+
 }
 
 #if HEX_DEBUG
@@ -225,8 +249,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext 
*ctx,
 mark_implicit_writes(ctx, insn);
 insn->generate(env, ctx, insn, pkt);
 } else {
-gen_exception(HEX_EXCP_INVALID_OPCODE);
-ctx->base.is_jmp = DISAS_NORETURN;
+gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
 }
 }
 
@@ -447,14 +470,6 @@ static void update_exec_counters(DisasContext *ctx, Packet 
*pkt)
 ctx->num_insns += num_real_insns;
 }
 
-static void gen_exec_counters(DisasContext *ctx)
-{
-tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
-hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
-tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
-hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
-}
-
 static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
 {
 gen_reg_writes(ctx);
@@ -478,7 +493,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet 
*pkt)
 #endif
 
 if (pkt->pkt_has_cof) {
-ctx->base.is_jmp = DISAS_NORETURN;
+gen_end_tb(ctx);
 }
 }
 
@@ -491,8 +506,7 @@ static void decode_and_translate_packet(CPUHexagonState 
*env, DisasContext *ctx)
 
 nwords = read_packet_words(env, ctx, words);
 if (!nwords) {
-gen_exception(HEX_EXCP_INVALID_PACKET);
-ctx->base.is_jmp = DISAS_NORETURN;
+gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
 return;
 }
 
@@ -505,8 +519,7 @@ static void decode_and_translate_packet(CPUHexagonState 
*env, DisasContext *ctx)
 gen_commit_packet(ctx, &pkt);
 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
 } else {
-gen_exception(HEX_EXCP_INVALID_PACKET);
-ctx->base.is_jmp = DISAS_NORETURN;
+gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
 }
 }
 
@@ -536,9 +549,7 @@ static bool hexagon_tr_breakpoint_check(DisasContextBase 
*dcbase, CPUState *cpu,
 {
 DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
-ctx->base.is_jmp = DISAS_NORETURN;
-gen_exception_debug();
+gen_exception_end_tb(ctx, EXCP_DEBUG);
 /*
  * The address covered by the breakpoint must be included in
  * [tb->pc, tb->pc + tb->size) in order to for it to be
@@ -601,19 +612,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, 
CPUState *cpu)
 gen_exec_counters(ctx);
 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
 if (ctx->base.singlestep_enabled) {
-gen_exception_debug();
+gen_exception_raw(EXCP_DEBUG);
 } el

[PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu

[Richard Henderson]

From: Taylor Simpson 

Remove hexagon_env_get_cpu and replace with env_archcpu
Replace CPU(hexagon_env_get_cpu(env)) with env_cpu(env)

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-5-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/cpu.h  | 5 -
 linux-user/hexagon/cpu_loop.c | 2 +-
 target/hexagon/cpu.c  | 4 ++--
 target/hexagon/op_helper.c| 2 +-
 target/hexagon/translate.c| 2 +-
 5 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c..2855dd3881 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -127,11 +127,6 @@ typedef struct HexagonCPU {
 target_ulong lldb_stack_adjust;
 } HexagonCPU;
 
-static inline HexagonCPU *hexagon_env_get_cpu(CPUHexagonState *env)
-{
-return container_of(env, HexagonCPU, env);
-}
-
 #include "cpu_bits.h"
 
 #define cpu_signal_handler cpu_hexagon_signal_handler
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index 9a68ca05c3..bc34f5d7c3 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -25,7 +25,7 @@
 
 void cpu_loop(CPUHexagonState *env)
 {
-CPUState *cs = CPU(hexagon_env_get_cpu(env));
+CPUState *cs = env_cpu(env);
 int trapnr, signum, sigcode;
 target_ulong sigaddr;
 target_ulong syscallnum;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index c2fe357702..f044506d0f 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -71,7 +71,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
  */
 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
 {
-HexagonCPU *cpu = hexagon_env_get_cpu(env);
+HexagonCPU *cpu = env_archcpu(env);
 target_ulong stack_adjust = cpu->lldb_stack_adjust;
 target_ulong stack_start = env->stack_start;
 target_ulong stack_size = 0x1;
@@ -115,7 +115,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, int 
regnum)
 
 static void hexagon_dump(CPUHexagonState *env, FILE *f)
 {
-HexagonCPU *cpu = hexagon_env_get_cpu(env);
+HexagonCPU *cpu = env_archcpu(env);
 
 if (cpu->lldb_compat) {
 /*
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 5d35dfc8f3..7ac85549db 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -35,7 +35,7 @@ static void QEMU_NORETURN 
do_raise_exception_err(CPUHexagonState *env,
  uint32_t exception,
  uintptr_t pc)
 {
-CPUState *cs = CPU(hexagon_env_get_cpu(env));
+CPUState *cs = env_cpu(env);
 qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
 cs->exception_index = exception;
 cpu_loop_exit_restore(cs, pc);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index f975d7a5a1..e235fdb315 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -585,7 +585,7 @@ static void hexagon_tr_translate_packet(DisasContextBase 
*dcbase, CPUState *cpu)
  * The CPU log is used to compare against LLDB single stepping,
  * so end the TLB after every packet.
  */
-HexagonCPU *hex_cpu = hexagon_env_get_cpu(env);
+HexagonCPU *hex_cpu = env_archcpu(env);
 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 ctx->base.is_jmp = DISAS_TOO_MANY;
 }
-- 
2.25.1

[PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition

[Richard Henderson]

From: Taylor Simpson 

Include size in declaration
Remove {0, 0} entry

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-15-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/reg_fields.h | 4 ++--
 target/hexagon/reg_fields.c | 3 +--
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/hexagon/reg_fields.h b/target/hexagon/reg_fields.h
index d3c86c942f..9e2ad5d997 100644
--- a/target/hexagon/reg_fields.h
+++ b/target/hexagon/reg_fields.h
@@ -23,8 +23,6 @@ typedef struct {
 int width;
 } RegField;
 
-extern const RegField reg_field_info[];
-
 enum {
 #define DEF_REG_FIELD(TAG, START, WIDTH) \
 TAG,
@@ -33,4 +31,6 @@ enum {
 #undef DEF_REG_FIELD
 };
 
+extern const RegField reg_field_info[NUM_REG_FIELDS];
+
 #endif
diff --git a/target/hexagon/reg_fields.c b/target/hexagon/reg_fields.c
index bdcab79428..6713203725 100644
--- a/target/hexagon/reg_fields.c
+++ b/target/hexagon/reg_fields.c
@@ -18,10 +18,9 @@
 #include "qemu/osdep.h"
 #include "reg_fields.h"
 
-const RegField reg_field_info[] = {
+const RegField reg_field_info[NUM_REG_FIELDS] = {
 #define DEF_REG_FIELD(TAG, START, WIDTH)\
   { START, WIDTH },
 #include "reg_fields_def.h.inc"
-  { 0, 0 }
 #undef DEF_REG_FIELD
 };
-- 
2.25.1

[PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-8-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/cpu_bits.h  |  2 +-
 target/hexagon/insn.h  | 21 +-
 target/hexagon/translate.h |  2 +-
 target/hexagon/decode.c| 80 +++---
 target/hexagon/op_helper.c |  8 ++--
 target/hexagon/translate.c |  6 +--
 6 files changed, 60 insertions(+), 59 deletions(-)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 96af834d0e..96fef71729 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -47,7 +47,7 @@ static inline uint32_t iclass_bits(uint32_t encoding)
 return iclass;
 }
 
-static inline int is_packet_end(uint32_t endocing)
+static inline bool is_packet_end(uint32_t endocing)
 {
 uint32_t bits = parse_bits(endocing);
 return ((bits == 0x3) || (bits == 0x0));
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h
index 5756a1d0ca..2e345912a8 100644
--- a/target/hexagon/insn.h
+++ b/target/hexagon/insn.h
@@ -40,14 +40,15 @@ struct Instruction {
 
 uint32_t iclass:6;
 uint32_t slot:3;
-uint32_t part1:1;/*
+uint32_t which_extended:1;/* If has an extender, which immediate */
+uint32_t new_value_producer_slot:4;
+
+bool part1;  /*
   * cmp-jumps are split into two insns.
   * set for the compare and clear for the jump
   */
-uint32_t extension_valid:1;   /* Has a constant extender attached */
-uint32_t which_extended:1;/* If has an extender, which immediate */
-uint32_t is_endloop:1;   /* This is an end of loop */
-uint32_t new_value_producer_slot:4;
+bool extension_valid;   /* Has a constant extender attached */
+bool is_endloop;   /* This is an end of loop */
 int32_t immed[IMMEDS_MAX];/* immediate field */
 };
 
@@ -58,13 +59,13 @@ struct Packet {
 uint16_t encod_pkt_size_in_bytes;
 
 /* Pre-decodes about COF */
-uint32_t pkt_has_cof:1;  /* Has any change-of-flow */
-uint32_t pkt_has_endloop:1;
+bool pkt_has_cof;  /* Has any change-of-flow */
+bool pkt_has_endloop;
 
-uint32_t pkt_has_dczeroa:1;
+bool pkt_has_dczeroa;
 
-uint32_t pkt_has_store_s0:1;
-uint32_t pkt_has_store_s1:1;
+bool pkt_has_store_s0;
+bool pkt_has_store_s1;
 
 Insn insn[INSTRUCTIONS_MAX];
 };
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 0ecfbd7d52..97b12a7d18 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -36,7 +36,7 @@ typedef struct DisasContext {
 int preg_log_idx;
 DECLARE_BITMAP(pregs_written, NUM_PREGS);
 uint8_t store_width[STORES_MAX];
-uint8_t s1_store_processed;
+bool s1_store_processed;
 } DisasContext;
 
 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 65d97ce64b..dffe1d1972 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -340,8 +340,8 @@ static void decode_split_cmpjump(Packet *pkt)
 if (GET_ATTRIB(pkt->insn[i].opcode, A_NEWCMPJUMP)) {
 last = pkt->num_insns;
 pkt->insn[last] = pkt->insn[i];/* copy the instruction */
-pkt->insn[last].part1 = 1;/* last instruction does the CMP */
-pkt->insn[i].part1 = 0;/* existing instruction does the JUMP */
+pkt->insn[last].part1 = true;  /* last insn does the CMP */
+pkt->insn[i].part1 = false;/* existing insn does the JUMP 
*/
 pkt->num_insns++;
 }
 }
@@ -354,7 +354,7 @@ static void decode_split_cmpjump(Packet *pkt)
 }
 }
 
-static int decode_opcode_can_jump(int opcode)
+static bool decode_opcode_can_jump(int opcode)
 {
 if ((GET_ATTRIB(opcode, A_JUMP)) ||
 (GET_ATTRIB(opcode, A_CALL)) ||
@@ -362,15 +362,15 @@ static int decode_opcode_can_jump(int opcode)
 (opcode == J2_pause)) {
 /* Exception to A_JUMP attribute */
 if (opcode == J4_hintjumpr) {
-return 0;
+return false;
 }
-return 1;
+return true;
 }
 
-return 0;
+return false;
 }
 
-static int decode_opcode_ends_loop(int opcode)
+static bool decode_opcode_ends_loop(int opcode)
 {
 return GET_ATTRIB(opcode, A_HWLOOP0_END) ||
GET_ATTRIB(opcode, A_HWLOOP1_END);
@@ -383,9 +383,9 @@ static void decode_set_insn_attr_fields(Packet *pkt)
 int numinsns = pkt->num_insns;
 uint16_t opcode;
 
-pkt->pkt_has_cof = 0;
-pkt->pkt_has_endloop = 0;
-pkt->pkt_has_dczeroa = 0;
+pkt->pkt_has_cof = false;
+pkt->pkt_has_endloop = false;
+pkt->pkt_has_dczeroa = false;
 
 for (i = 0; i < numinsns; i++) 

[PULL 04/31] target/hexagon: fix typo in comment

[Richard Henderson]

From: Taylor Simpson 

Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Taylor Simpson 
Message-Id: <1615784115-26559-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 2c6d718579..d6b5c47500 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -298,7 +298,7 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, 
int32_t M, int32_t CS)
 }
 
 /*
- * Hexagon FP operations return ~0 insteat of NaN
+ * Hexagon FP operations return ~0 instead of NaN
  * The hex_check_sfnan/hex_check_dfnan functions perform this check
  */
 static float32 hex_check_sfnan(float32 x)
-- 
2.25.1

[PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup

[Richard Henderson]

From: Taylor Simpson 

Simplify TCG generation of hex_reg_written

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-2-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/genptr.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7481f4c1dd..87f5d92994 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
 
 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
 {
-TCGv one = tcg_const_tl(1);
 TCGv zero = tcg_const_tl(0);
 TCGv slot_mask = tcg_temp_new();
 
@@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum, 
TCGv val, int slot)
 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
val, hex_new_value[rnum]);
 #if HEX_DEBUG
-/* Do this so HELPER(debug_commit_end) will know */
-tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
-   one, hex_reg_written[rnum]);
+/*
+ * Do this so HELPER(debug_commit_end) will know
+ *
+ * Note that slot_mask indicates the value is not written
+ * (i.e., slot was cancelled), so we create a true/false value before
+ * or'ing with hex_reg_written[rnum].
+ */
+tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
 #endif
 
-tcg_temp_free(one);
 tcg_temp_free(zero);
 tcg_temp_free(slot_mask);
 }
-- 
2.25.1

[PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time

[Richard Henderson]

From: Taylor Simpson 

Multiple writes to the same preg are and'ed together.  Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.

Test added to tests/tcg/hexagon/misc.c

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-7-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/translate.h  |  2 ++
 target/hexagon/genptr.c | 22 +++---
 target/hexagon/translate.c  |  9 +++--
 tests/tcg/hexagon/misc.c| 19 +++
 target/hexagon/gen_tcg_funcs.py |  2 +-
 5 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 12506c8caf..0ecfbd7d52 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -34,6 +34,7 @@ typedef struct DisasContext {
 DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
 int preg_log[PRED_WRITES_MAX];
 int preg_log_idx;
+DECLARE_BITMAP(pregs_written, NUM_PREGS);
 uint8_t store_width[STORES_MAX];
 uint8_t s1_store_processed;
 } DisasContext;
@@ -60,6 +61,7 @@ static inline void ctx_log_pred_write(DisasContext *ctx, int 
pnum)
 {
 ctx->preg_log[ctx->preg_log_idx] = pnum;
 ctx->preg_log_idx++;
+set_bit(pnum, ctx->pregs_written);
 }
 
 static inline bool is_preloaded(DisasContext *ctx, int num)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 07d970fc6c..6b74344795 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -119,20 +119,28 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
 #endif
 }
 
-static inline void gen_log_pred_write(int pnum, TCGv val)
+static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
 {
 TCGv zero = tcg_const_tl(0);
 TCGv base_val = tcg_temp_new();
 TCGv and_val = tcg_temp_new();
 TCGv pred_written = tcg_temp_new();
 
-/* Multiple writes to the same preg are and'ed together */
 tcg_gen_andi_tl(base_val, val, 0xff);
-tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]);
-tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum);
-tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum],
-   pred_written, zero,
-   and_val, base_val);
+
+/*
+ * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
+ *
+ * Multiple writes to the same preg are and'ed together
+ * If this is the first predicate write in the packet, do a
+ * straight assignment.  Otherwise, do an and.
+ */
+if (!test_bit(pnum, ctx->pregs_written)) {
+tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val);
+} else {
+tcg_gen_and_tl(hex_new_pred_value[pnum],
+   hex_new_pred_value[pnum], base_val);
+}
 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
 
 tcg_temp_free(zero);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 9f2a531969..49ec8b76ed 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -172,6 +172,7 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
 ctx->reg_log_idx = 0;
 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
 ctx->preg_log_idx = 0;
+bitmap_zero(ctx->pregs_written, NUM_PREGS);
 for (i = 0; i < STORES_MAX; i++) {
 ctx->store_width[i] = 0;
 }
@@ -226,7 +227,7 @@ static void mark_implicit_pred_write(DisasContext *ctx, 
Insn *insn,
 }
 }
 
-static void mark_implicit_writes(DisasContext *ctx, Insn *insn)
+static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
 {
 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP,  HEX_REG_FP);
 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP,  HEX_REG_SP);
@@ -235,7 +236,10 @@ static void mark_implicit_writes(DisasContext *ctx, Insn 
*insn)
 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
+}
 
+static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
+{
 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
@@ -246,8 +250,9 @@ static void gen_insn(CPUHexagonState *env, DisasContext 
*ctx,
  Insn *insn, Packet *pkt)
 {
 if (insn->generate) {
-mark_implicit_writes(ctx, insn);
+mark_implicit_reg_writes(ctx, insn);
 insn->generate(env, ctx, insn, pkt);
+mark_implicit_pred_writes(ctx, insn);
 } else {
 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
 }
diff --git a/tests/tcg/hexagon/misc.c b/tests/

[PULL 05/31] target/hexagon: remove unnecessary semicolons

[Richard Henderson]

From: Taylor Simpson 

Reviewed-by: Philippe Mathieu-Daudé 
Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson 
Message-Id: <1615784100-26459-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/gen_tcg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index e044deaff2..a30048ee57 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -83,9 +83,9 @@
 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE)   SHORTCODE
-#define fGEN_TCG_L2_loadrb_pi(SHORTCODE)   SHORTCODE;
+#define fGEN_TCG_L2_loadrb_pi(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE)  SHORTCODE
-#define fGEN_TCG_L2_loadruh_pi(SHORTCODE)  SHORTCODE;
+#define fGEN_TCG_L2_loadruh_pi(SHORTCODE)  SHORTCODE
 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE)   SHORTCODE
 #define fGEN_TCG_L2_loadri_pr(SHORTCODE)   SHORTCODE
-- 
2.25.1

[PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots

[Richard Henderson]

From: Taylor Simpson 

Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson 
Message-Id: <1615784037-26129-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/iclass.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c
index 378d8a6a75..6091286993 100644
--- a/target/hexagon/iclass.c
+++ b/target/hexagon/iclass.c
@@ -53,10 +53,6 @@ SlotMask find_iclass_slots(Opcode opcode, int itype)
(opcode == Y2_isync) ||
(opcode == J2_pause) || (opcode == J4_hintjumpr)) {
 return SLOTS_2;
-} else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) {
-return SLOTS_01;
-} else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) {
-return SLOTS_01;
 } else if (GET_ATTRIB(opcode, A_CRSLOT23)) {
 return SLOTS_23;
 } else if (GET_ATTRIB(opcode, A_RESTRICT_PREFERSLOT0)) {
-- 
2.25.1

[PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM

[Richard Henderson]

From: Taylor Simpson 

Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson 
Message-Id: <1615784049-26215-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/decode.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index c9bacaa1ee..1c9c07412a 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -48,8 +48,8 @@ enum {
 DEF_REGMAP(R_16,  16, 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23)
 DEF_REGMAP(R__8,  8,  0, 2, 4, 6, 16, 18, 20, 22)
 
-#define DECODE_MAPPED_REG(REGNO, NAME) \
-insn->regno[REGNO] = DECODE_REGISTER_##NAME[insn->regno[REGNO]];
+#define DECODE_MAPPED_REG(OPNUM, NAME) \
+insn->regno[OPNUM] = DECODE_REGISTER_##NAME[insn->regno[OPNUM]];
 
 typedef struct {
 const struct DectreeTable *table_link;
-- 
2.25.1

[PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair

[Richard Henderson]

From: Taylor Simpson 

Similar to previous cleanup of gen_log_predicated_reg_write

Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-3-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/genptr.c | 27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 87f5d92994..07d970fc6c 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -69,36 +69,35 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
 {
 TCGv val32 = tcg_temp_new();
-TCGv one = tcg_const_tl(1);
 TCGv zero = tcg_const_tl(0);
 TCGv slot_mask = tcg_temp_new();
 
 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
 /* Low word */
 tcg_gen_extrl_i64_i32(val32, val);
-tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
-   val32, hex_new_value[rnum]);
-#if HEX_DEBUG
-/* Do this so HELPER(debug_commit_end) will know */
-tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum],
+tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
slot_mask, zero,
-   one, hex_reg_written[rnum]);
-#endif
-
+   val32, hex_new_value[rnum]);
 /* High word */
 tcg_gen_extrh_i64_i32(val32, val);
 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
slot_mask, zero,
val32, hex_new_value[rnum + 1]);
 #if HEX_DEBUG
-/* Do this so HELPER(debug_commit_end) will know */
-tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum + 1],
-   slot_mask, zero,
-   one, hex_reg_written[rnum + 1]);
+/*
+ * Do this so HELPER(debug_commit_end) will know
+ *
+ * Note that slot_mask indicates the value is not written
+ * (i.e., slot was cancelled), so we create a true/false value before
+ * or'ing with hex_reg_written[rnum].
+ */
+tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
+tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
+  slot_mask);
 #endif
 
 tcg_temp_free(val32);
-tcg_temp_free(one);
 tcg_temp_free(zero);
 tcg_temp_free(slot_mask);
 }
-- 
2.25.1

[PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives

[Richard Henderson]

From: Taylor Simpson 

Suggested-by: Richard Henderson 
Signed-off-by: Taylor Simpson 
Reviewed-by: Richard Henderson 
Message-Id: <1617930474-31979-4-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/cpu.c   |  9 -
 target/hexagon/decode.c|  6 +++---
 target/hexagon/fma_emu.c   | 39 +++---
 target/hexagon/op_helper.c | 37 ++--
 target/hexagon/translate.c |  2 +-
 5 files changed, 46 insertions(+), 47 deletions(-)

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index b0b3040dd1..c2fe357702 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -69,10 +69,9 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = 
{
  * stacks at different locations.  This is used to compensate so the diff is
  * cleaner.
  */
-static inline target_ulong adjust_stack_ptrs(CPUHexagonState *env,
- target_ulong addr)
+static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
 {
-HexagonCPU *cpu = container_of(env, HexagonCPU, env);
+HexagonCPU *cpu = hexagon_env_get_cpu(env);
 target_ulong stack_adjust = cpu->lldb_stack_adjust;
 target_ulong stack_start = env->stack_start;
 target_ulong stack_size = 0x1;
@@ -88,7 +87,7 @@ static inline target_ulong adjust_stack_ptrs(CPUHexagonState 
*env,
 }
 
 /* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */
-static inline target_ulong read_p3_0(CPUHexagonState *env)
+static target_ulong read_p3_0(CPUHexagonState *env)
 {
 int32_t control_reg = 0;
 int i;
@@ -116,7 +115,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, int 
regnum)
 
 static void hexagon_dump(CPUHexagonState *env, FILE *f)
 {
-HexagonCPU *cpu = container_of(env, HexagonCPU, env);
+HexagonCPU *cpu = hexagon_env_get_cpu(env);
 
 if (cpu->lldb_compat) {
 /*
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index 1c9c07412a..65d97ce64b 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -354,7 +354,7 @@ static void decode_split_cmpjump(Packet *pkt)
 }
 }
 
-static inline int decode_opcode_can_jump(int opcode)
+static int decode_opcode_can_jump(int opcode)
 {
 if ((GET_ATTRIB(opcode, A_JUMP)) ||
 (GET_ATTRIB(opcode, A_CALL)) ||
@@ -370,7 +370,7 @@ static inline int decode_opcode_can_jump(int opcode)
 return 0;
 }
 
-static inline int decode_opcode_ends_loop(int opcode)
+static int decode_opcode_ends_loop(int opcode)
 {
 return GET_ATTRIB(opcode, A_HWLOOP0_END) ||
GET_ATTRIB(opcode, A_HWLOOP1_END);
@@ -764,7 +764,7 @@ static void decode_add_endloop_insn(Insn *insn, int loopnum)
 }
 }
 
-static inline int decode_parsebits_is_loopend(uint32_t encoding32)
+static int decode_parsebits_is_loopend(uint32_t encoding32)
 {
 uint32_t bits = parse_bits(encoding32);
 return bits == 0x2;
diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c
index 842d903710..f324b83e3c 100644
--- a/target/hexagon/fma_emu.c
+++ b/target/hexagon/fma_emu.c
@@ -64,7 +64,7 @@ typedef union {
 };
 } Float;
 
-static inline uint64_t float64_getmant(float64 f64)
+static uint64_t float64_getmant(float64 f64)
 {
 Double a = { .i = f64 };
 if (float64_is_normal(f64)) {
@@ -91,7 +91,7 @@ int32_t float64_getexp(float64 f64)
 return -1;
 }
 
-static inline uint64_t float32_getmant(float32 f32)
+static uint64_t float32_getmant(float32 f32)
 {
 Float a = { .i = f32 };
 if (float32_is_normal(f32)) {
@@ -118,17 +118,17 @@ int32_t float32_getexp(float32 f32)
 return -1;
 }
 
-static inline uint32_t int128_getw0(Int128 x)
+static uint32_t int128_getw0(Int128 x)
 {
 return int128_getlo(x);
 }
 
-static inline uint32_t int128_getw1(Int128 x)
+static uint32_t int128_getw1(Int128 x)
 {
 return int128_getlo(x) >> 32;
 }
 
-static inline Int128 int128_mul_6464(uint64_t ai, uint64_t bi)
+static Int128 int128_mul_6464(uint64_t ai, uint64_t bi)
 {
 Int128 a, b;
 uint64_t pp0, pp1a, pp1b, pp1s, pp2;
@@ -152,7 +152,7 @@ static inline Int128 int128_mul_6464(uint64_t ai, uint64_t 
bi)
 return int128_make128(ret_low, pp2 + (pp1s >> 32));
 }
 
-static inline Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow)
+static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow)
 {
 Int128 ret = int128_sub(a, b);
 if (borrow != 0) {
@@ -170,7 +170,7 @@ typedef struct {
 uint8_t sticky;
 } Accum;
 
-static inline void accum_init(Accum *p)
+static void accum_init(Accum *p)
 {
 p->mant = int128_zero();
 p->exp = 0;
@@ -180,7 +180,7 @@ static inline void accum_init(Accum *p)
 p->sticky = 0;
 }
 
-static inline Accum accum_norm_left(Accum a)
+static Accum accum_norm_left(Accum a)
 {
 a.exp--;
 a.mant = int128_lshift(a.mant, 1);
@@ -190,6 +190,7 @@ static inline Accum accum_norm_left(Accum a)
 return a;
 }
 
+/* This function is marked inline fo

[PULL 01/31] target/hexagon: translation changes

[Richard Henderson]

From: Taylor Simpson 

Change cpu_ldl_code to translator_ldl.
Don't end the TB after every packet when HEX_DEBUG is on.
Make gen_check_store_width a simple call.

Reported-by: Richard Henderson <
Signed-off-by: Taylor Simpson 
Message-Id: <1615783984-25918-1-git-send-email-tsimp...@quicinc.com>
Signed-off-by: Richard Henderson 
---
 target/hexagon/translate.c | 26 +-
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index eeaad5f8ba..2317508fa5 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -88,8 +88,8 @@ static int read_packet_words(CPUHexagonState *env, 
DisasContext *ctx,
 
 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
-words[nwords] = cpu_ldl_code(env,
-ctx->base.pc_next + nwords * sizeof(uint32_t));
+words[nwords] =
+translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
 found_end = is_packet_end(words[nwords]);
 }
 if (!found_end) {
@@ -292,20 +292,16 @@ static void gen_pred_writes(DisasContext *ctx, Packet 
*pkt)
 tcg_temp_free(pval);
 }
 
-#if HEX_DEBUG
-static inline void gen_check_store_width(DisasContext *ctx, int slot_num)
+static void gen_check_store_width(DisasContext *ctx, int slot_num)
 {
+#if HEX_DEBUG
 TCGv slot = tcg_const_tl(slot_num);
 TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
 gen_helper_debug_check_store_width(cpu_env, slot, check);
 tcg_temp_free(slot);
 tcg_temp_free(check);
-}
-#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num) \
-gen_check_store_width(ctx, slot_num)
-#else
-#define HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num)  /* nothing */
 #endif
+}
 
 static bool slot_is_predicated(Packet *pkt, int slot_num)
 {
@@ -355,25 +351,25 @@ void process_store(DisasContext *ctx, Packet *pkt, int 
slot_num)
  */
 switch (ctx->store_width[slot_num]) {
 case 1:
-HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
+gen_check_store_width(ctx, slot_num);
 tcg_gen_qemu_st8(hex_store_val32[slot_num],
  hex_store_addr[slot_num],
  ctx->mem_idx);
 break;
 case 2:
-HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
+gen_check_store_width(ctx, slot_num);
 tcg_gen_qemu_st16(hex_store_val32[slot_num],
   hex_store_addr[slot_num],
   ctx->mem_idx);
 break;
 case 4:
-HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
+gen_check_store_width(ctx, slot_num);
 tcg_gen_qemu_st32(hex_store_val32[slot_num],
   hex_store_addr[slot_num],
   ctx->mem_idx);
 break;
 case 8:
-HEX_DEBUG_GEN_CHECK_STORE_WIDTH(ctx, slot_num);
+gen_check_store_width(ctx, slot_num);
 tcg_gen_qemu_st64(hex_store_val64[slot_num],
   hex_store_addr[slot_num],
   ctx->mem_idx);
@@ -593,10 +589,6 @@ static void hexagon_tr_translate_packet(DisasContextBase 
*dcbase, CPUState *cpu)
 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 ctx->base.is_jmp = DISAS_TOO_MANY;
 }
-#if HEX_DEBUG
-/* When debugging, only put one packet per TB */
-ctx->base.is_jmp = DISAS_TOO_MANY;
-#endif
 }
 }
 
-- 
2.25.1

[PULL 00/31] target/hexagon patch queue

[Richard Henderson]

The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into 
staging (2021-04-30 16:02:00 +0100)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-hex-20210501

for you to fetch changes up to 26f7c044ad234c3dfa7ca2ddf047a71d815e66dc:

  Hexagon (target/hexagon) CABAC decode bin (2021-05-01 08:31:43 -0700)


Minor cleanups.
Finish the rest of the hexagon integer instructions.


Taylor Simpson (31):
  target/hexagon: translation changes
  target/hexagon: remove unnecessary checks in find_iclass_slots
  target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM
  target/hexagon: fix typo in comment
  target/hexagon: remove unnecessary semicolons
  Hexagon (target/hexagon) TCG generation cleanup
  Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair
  Hexagon (target/hexagon) remove unnecessary inline directives
  Hexagon (target/hexagon) use env_archcpu and env_cpu
  Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN
  Hexagon (target/hexagon) decide if pred has been written at TCG gen time
  Hexagon (target/hexagon) change variables from int to bool when 
appropriate
  Hexagon (target/hexagon) remove unused carry_from_add64 function
  Hexagon (target/hexagon) change type of softfloat_roundingmodes
  Hexagon (target/hexagon) use softfloat default NaN and tininess
  Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
  Hexagon (target/hexagon) use softfloat for float-to-int conversions
  Hexagon (target/hexagon) cleanup ternary operators in semantics
  Hexagon (target/hexagon) cleanup reg_field_info definition
  Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h
  Hexagon (target/hexagon) compile all debug code
  Hexagon (target/hexagon) add F2_sfrecipa instruction
  Hexagon (target/hexagon) add F2_sfinvsqrta
  Hexagon (target/hexagon) add A5_ACS (vacsh)
  Hexagon (target/hexagon) add A6_vminub_RdP
  Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
  Hexagon (target/hexagon) circular addressing
  Hexagon (target/hexagon) bit reverse (brev) addressing
  Hexagon (target/hexagon) load and unpack bytes instructions
  Hexagon (target/hexagon) load into shifted register instructions
  Hexagon (target/hexagon) CABAC decode bin

 target/hexagon/arch.h |   9 +-
 target/hexagon/conv_emu.h |  31 ---
 target/hexagon/cpu.h  |   5 -
 target/hexagon/cpu_bits.h |   2 +-
 target/hexagon/gen_tcg.h  | 424 -
 target/hexagon/helper.h   |  23 +-
 target/hexagon/insn.h |  21 +-
 target/hexagon/internal.h |  11 +-
 target/hexagon/macros.h   | 118 -
 target/hexagon/reg_fields.h   |   4 +-
 target/hexagon/translate.h|   9 +-
 linux-user/hexagon/cpu_loop.c |   2 +-
 target/hexagon/arch.c | 181 ++---
 target/hexagon/conv_emu.c | 177 -
 target/hexagon/cpu.c  |  14 +-
 target/hexagon/decode.c   |  84 +++---
 target/hexagon/fma_emu.c  |  40 +--
 target/hexagon/genptr.c   | 244 ++---
 target/hexagon/iclass.c   |   4 -
 target/hexagon/op_helper.c| 398 ++--
 target/hexagon/reg_fields.c   |   3 +-
 target/hexagon/translate.c| 175 ++--
 tests/tcg/hexagon/brev.c  | 190 +
 tests/tcg/hexagon/circ.c  | 486 ++
 tests/tcg/hexagon/fpstuff.c   | 242 +
 tests/tcg/hexagon/load_align.c| 415 +
 tests/tcg/hexagon/load_unpack.c   | 474 +
 tests/tcg/hexagon/misc.c  |  47 
 tests/tcg/hexagon/multi_result.c  | 282 
 fpu/softfloat-specialize.c.inc|   3 +
 target/hexagon/gen_tcg_funcs.py   |   2 +-
 target/hexagon/imported/alu.idef  |  44 +++
 target/hexagon/imported/compare.idef  |  12 +-
 target/hexagon/imported/encode_pp.def |  30 +++
 target/hexagon/imported/float.idef|  32 +++
 target/hexagon/imported/ldst.idef |  68 +
 target/hexagon/imported/macros.def|  47 
 target/hexagon/imported/shift.idef|  47 
 target/hexagon/meson.build|   1 -
 tests/tcg/hexagon/Makefile.target |   6 +
 40 files changed, 3768 insertions(+), 639 deletions(-)
 delete mode 100644 target/hexagon/conv_emu.h
 delete mode 100644 target/hexagon/conv_emu.c
 create mode 100644 tests/tcg/hexagon/brev

[Bug 1750899] Re: Mouse cursor sometimes can't pass the invisible border on the right side of the screen

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/76


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #76
   https://gitlab.com/qemu-project/qemu/-/issues/76

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Title:
  Mouse cursor sometimes can't pass the invisible border on the right
  side of the screen

Status in QEMU:
  Expired

Bug description:
  I'm using qemu 2.11 on Gentoo Linux, with configured GPU passthrough (Radeon 
RX580) to the guest Windows 10.
  This configuration is alive for last 4 years, this time I changed a lot qemu, 
linux kernel and windows versions, changed GPU and always all was working as 
expected. I always used standard PS/2 mouse emulation and that was enough for 
me.

  Now, I bought two new monitors, instead of old one, and setup them as
  one logical monitor, using technology called Eyefinity - it's a part
  of standard Radeon software. Now Windows thinks, that I have one
  monitor with resolution 2160x1920 (I bought Dell monitors with a thin
  borders and use them in portrait mode).

  Windows uses it without any problems, but mouse become crazy - sometimes (~3 
times from each 5) I can't move cursor to the right border of the screen, it 
looks like the invisible vertical border. I spent really huge amount of time to 
understand, which component is the root of problem and found, that it's really 
a mouse. I tried all possible variants (standard, tablet, virtio-mouse-pci, 
virtio-tablet-pci), and found, that in both mouse variants bug is reproducing, 
and in both tablet variants - cursor stuck near all real borders and corners, 
so it's not a variant too.
  The only working variant becomes passing real USB port to my VM and insert 
second mouse to this port. So, now it's working, but I have two mice on my 
working place, which doesn't seems very useful.

  Here is my command line:

  QEMU_AUDIO_DRV=pa QEMU_PA_SAMPLES=4096 qemu-system-x86_64 -enable-kvm -M q35 
-m 12168 -cpu host,kvm=off -smp 4,sockets=1,cores=4 \
  -bios /usr/share/qemu/bios.bin -rtc base=localtime -vga none -device 
secondary-vga \
  -drive 
id=virtiocd,if=none,format=raw,file=/home/akushsky/virtio-win-0.1.141.iso \
  -device driver=ide-cd,bus=ide.1,drive=virtiocd \
  -device 
ioh3420,bus=pcie.0,addr=1c.0,multifunction=on,port=1,chassis=1,id=root.1 \
  -device 
vfio-pci,host=05:00.0,bus=root.1,addr=00.0,multifunction=on,romfile=/opt/kvm/images/Sapphire.RX580.8192.170320_1.bin,x-vga=on
 \
  -device virtio-scsi-pci,id=scsi \
  -drive 
file=/dev/sdb,id=disk,format=raw,if=none,discard=on,cache=none,aio=native,detect-zeroes=unmap
 -device scsi-hd,drive=disk,id=scsi0 \
  -device ich9-intel-hda,bus=pcie.0,addr=1b.0,id=sound0 -device 
hda-duplex,id=sound0-codec0,bus=sound0.0,cad=0 \
  -usb -usbdevice host:046d:c52b

  All in all, I checked on Windows 7 and Windows 10, and on qemu 2.10
  and 2.11 - bug is always reproducible.

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[Bug 1884302] Re: disable automatic mouse grabbing

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/75


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #75
   https://gitlab.com/qemu-project/qemu/-/issues/75

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Title:
  disable automatic mouse grabbing

Status in QEMU:
  Expired

Bug description:
  I'm using QEMU 5.0.0 on a Gentoo Linux host system. Guest is an Arch
  Linux system.

  I'd like to disable automatic mouse grabbing when the QEMU window is focused.
  I would prefer for QEMU to grab the mouse only after a click.

  I use the i3 window manager on my host system.
  Suppose I'm in workspace 1, while the QEMU window is in workspace 2.
  In order to switch to workspace 2, I need to press the "Win+2" key 
combination ("Win" is the Windows key).
  The problem is that the character "2" (from "Win+2") will get transferred to 
the guest system.
  For example, if I have a text editor opened under the guest system, the 
character "2" will be pasted inside the document I'm working on, which is 
pretty annoying.

  I would like instead to press the "Win+2" key combination and then
  explicitely click on the QEMU window with the mouse before grabbing
  it.

  Command line:

  qemu-system-x86_64 -drive
  
file=/home/fturco/qemu/arch.img,media=disk,index=0,if=virtio,format=raw,cache=none
  -cpu host -m 2G -k it -enable-kvm -net nic,model=virtio -net user -vga
  virtio -display sdl -usb -rtc base=utc -soundhw ac97 -monitor stdio
  -no-quit

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[Bug 1888663] Re: msmouse not recognized in guest

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/77


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #77
   https://gitlab.com/qemu-project/qemu/-/issues/77

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Title:
  msmouse not recognized in guest

Status in QEMU:
  Expired

Bug description:
  The msmouse option for emulating a serial mouse does not seem to work
  in a DOS guest.

  I'm on Windows 10 X64, I have tried launching qemu (commit 
d0cc248164961a7ba9d43806feffd76f9f6d7f41 but also way older) with:
  ./qemu-system-i386 -serial msmouse -fda mousetest.img
  ./qemu-system-i386 -chardev msmouse,id=msmouse -device 
isa-serial,chardev=msmouse -fda mousetest.img
  ./qemu-system-i386 -chardev msmouse,id=msmouse -device 
pci-serial,chardev=msmouse -chardev msmouse,id=msmouse -fda mousetest.img

  Then I boot FreeDOS (but regular DOS shows same behavior), start the 
CuteMouse driver and force the scan of a serial mouse with CTM /S.
  The mouse is never found. With other drivers (in the attachment), the mouse 
is probably not found but the driver is installed anyway, but it does not work 
(there's a MOUSETST in the same floppy; it works iwth CTM and PS/2 mouse 
emulation).

  Using a serial port sniffer inside the guest, it would seem that data
  is indeed transmitted. Setting a few printf in msmouse.c also confirms
  that the mouse gets initilized and starts transmitting data. However,
  it does not work...

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[Bug 1891830] Re: msmouse serial mouse emulation broken? No id byte sent on reset

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/78


** Changed in: qemu
   Status: New => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #78
   https://gitlab.com/qemu-project/qemu/-/issues/78

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Title:
  msmouse serial mouse emulation broken? No id byte sent on reset

Status in QEMU:
  Expired

Bug description:
  I took a shot at getting Windows 1.01 working.  It doesn't support a
  PS/2 mouse out-of-the-box but does support MS serial mice.  It doesn't
  seem to detect qemu's emulated msmouse.

  When I run this command:

  > qemu-system-i386 -nodefaults -hda my_windows1_hd.qcow2 -vga std
  -serial msmouse -trace enable='serial*'  -icount shift=10,align=on

  I get this output (edited):

  251908@1597626456.800452:serial_ioport_write write addr 0x04 val 0x01
  251908@1597626456.800460:serial_ioport_read read addr 0x00 val 0x00
  251908@1597626456.800462:serial_ioport_read read addr 0x00 val 0x00

  [snip]

  251908@1597626456.961641:serial_ioport_read read addr 0x00 val 0x00
  251908@1597626456.961642:serial_ioport_read read addr 0x00 val 0x00
  251908@1597626456.961644:serial_ioport_read read addr 0x00 val 0x00
  251908@1597626456.961647:serial_ioport_write write addr 0x04 val 0x0b
  251908@1597626456.961648:serial_ioport_read read addr 0x05 val 0x60
  251908@1597626456.961684:serial_ioport_read read addr 0x05 val 0x60
  251908@1597626456.961685:serial_ioport_read read addr 0x05 val 0x60

  [snip]

  251908@1597626457.045894:serial_ioport_read read addr 0x05 val 0x60
  251908@1597626457.045895:serial_ioport_read read addr 0x05 val 0x60
  251908@1597626457.045897:serial_ioport_read read addr 0x05 val 0x60
  251908@1597626457.045932:serial_ioport_read read addr 0x00 val 0x00

  The write of 0x01 and then 0x0b to reg 0x04 is the guest turning the
  RTS line off then on.  A real mouse will respond to this by sending
  0x4d, which is how the guest detects the mouse.

  Reproducible in current stable-4.2 and 5.0 (debian's build).  I am
  able to get the guest to use a real passed-through serial mouse (with
  a minor hack, separate bug filed for this)

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Re: [PATCH 1/2] hw/timer/etraxfs_timer: Qdev'ify reset()

[Laurent Vivier]

Le 24/04/2021 à 01:36, Philippe Mathieu-Daudé a écrit :
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset.
> Convert the generic reset to a qdev one, and remove the
> qemu_register_reset() call.
> 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  hw/timer/etraxfs_timer.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
> index 5379006086f..3cfab3e3284 100644
> --- a/hw/timer/etraxfs_timer.c
> +++ b/hw/timer/etraxfs_timer.c
> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>  }
>  };
>  
> -static void etraxfs_timer_reset(void *opaque)
> +static void etraxfs_timer_reset(DeviceState *dev)
>  {
> -ETRAXTimerState *t = opaque;
> +ETRAXTimerState *t = ETRAX_TIMER(dev);
>  
>  ptimer_transaction_begin(t->ptimer_t0);
>  ptimer_stop(t->ptimer_t0);
> @@ -343,7 +343,6 @@ static void etraxfs_timer_realize(DeviceState *dev, Error 
> **errp)
>  memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>"etraxfs-timer", 0x5c);
>  sysbus_init_mmio(sbd, &t->mmio);
> -qemu_register_reset(etraxfs_timer_reset, t);
>  }
>  
>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
> @@ -351,6 +350,7 @@ static void etraxfs_timer_class_init(ObjectClass *klass, 
> void *data)
>  DeviceClass *dc = DEVICE_CLASS(klass);
>  
>  dc->realize = etraxfs_timer_realize;
> +dc->reset = etraxfs_timer_reset;
>  }
>  
>  static const TypeInfo etraxfs_timer_info = {
> 

Reviewed-by: Laurent Vivier 

But according to the comment in DeviceClass, we should use the resettable 
interface now:

docs/devel/reset.rst

Thanks,
Laurent

Re: [PULL 00/10] Misc patches for 2021-04-30 (incl. NVMM accelerator)

[Peter Maydell]

On Sat, 1 May 2021 at 10:35, Paolo Bonzini  wrote:
>
> The following changes since commit b1cffefa1b163bce9aebc3416f562c1d3886eeaa:
>
>   Update version for v6.0.0-rc4 release (2021-04-20 16:30:01 +0100)
>
> are available in the Git repository at:
>
>   https://gitlab.com/bonzini/qemu.git tags/for-upstream
>
> for you to fetch changes up to 29740bdf1418c1193524356389cec825051c7a64:
>
>   gitlab-ci: use --meson=internal for CFI jobs (2021-04-30 21:39:59 +0200)
>
> 
> * NetBSD NVMM support
> * RateLimit mutex
> * Prepare for Meson 0.57 upgrade
>
> 

Fails to build on netbsd (on our usual tests/vm setup):

../src/target/i386/nvmm/nvmm-all.c: In function 'nvmm_vcpu_loop':
../src/target/i386/nvmm/nvmm-all.c:753:13: warning: implicit
declaration of function 'nvmm_vcpu_stop'; did you mean
'nvmm_vcpu_loop'? [-Wimplicit-function-declaration]
 nvmm_vcpu_stop(vcpu);
 ^~
 nvmm_vcpu_loop
../src/target/i386/nvmm/nvmm-all.c:753:13: warning: nested extern
declaration of 'nvmm_vcpu_stop' [-Wnested-externs]
../src/target/i386/nvmm/nvmm-all.c:770:14: error:
'NVMM_VCPU_EXIT_STOPPED' undeclared (first use in this function); did
you mean 'NVMM_VCPU_EXIT_CPUID'?
 case NVMM_VCPU_EXIT_STOPPED:
  ^~
  NVMM_VCPU_EXIT_CPUID
../src/target/i386/nvmm/nvmm-all.c:770:14: note: each undeclared
identifier is reported only once for each function it appears in

thanks
-- PMM

Re: [PATCH v4 0/3] nvdimm: Enable sync-dax property for nvdimm

[Aneesh Kumar K.V]

On 5/1/21 12:44 AM, Dan Williams wrote:

Some corrections to terminology confusion below...


...




file on the host in case of file backed v-nvdimms. This is addressed by
virtio-pmem in case of x86_64 by making explicit flushes translating to
fsync at qemu.


Note that virtio-pmem was a proposal for a specific optimization of
allowing guests to share page cache. The virtio-pmem approach is not
to be confused with actual persistent memory.



.



A new device property sync-dax is added to the nvdimm device. When the
sync-dax is 'writeback'(default for PPC), device property
"hcall-flush-required" is set, and the guest makes hcall H_SCM_FLUSH
requesting for an explicit flush.


I'm not sure "sync-dax" is a suitable name for the property of the
guest persistent memory. There is no requirement that the
memory-backend file for a guest be a dax-capable file. It's also
implementation specific what hypercall needs to be invoked for a given
occurrence of "sync-dax". What does that map to on non-PPC platforms
for example? It seems to me that an "nvdimm" device presents the
synchronous usage model and a whole other device type implements an
async-hypercall setup that the guest happens to service with its
nvdimm stack, but it's not an "nvdimm" anymore at that point.



What is attempted here is to use the same guest driver papr_scm.ko 
support the usecase of sharing page cache from the host instead of 
depending on a new guest driver virtio-pmem. This also try to correctly 
indicate to the guest that an usage like


-object memory-backend-file,id=memnvdimm1,mem-path=file_name
-device nvdimm,memdev=memnvdimm1

correctly indicate to the guest that we are indeed sharing page cache 
and not really emulating a persistent memory.


W.r.t non ppc platforms, it was discussed earlier and one of the 
suggestion there was to mark that as "unsafe".


Any suggestion for an alternate property name than "sync-dax"?


sync-dax is "unsafe" on all other platforms(x86, ARM) and old pseries machines
prior to 5.2 on PPC. sync-dax="writeback" on ARM and x86_64 is prevented
now as the flush semantics are unimplemented.


"sync-dax" has no meaning on its own, I think this needs an explicit
mechanism to convey both the "not-sync" property *and* the callback
method, it shouldn't be inferred by arch type.


Won't a non-sync property imply that guest needs to do a callback to 
ensure persistence? Hence they are related?



-aneesh

[Bug 1861677] Re: wavcapture crash with pulseaudio

[Philippe Mathieu-Daudé]

Fixed in v5.1.0, commit cbaf25d1f59 ("audio: fix wavcapture segfault").

** Changed in: qemu
   Status: New => Fix Released

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Title:
  wavcapture crash with pulseaudio

Status in QEMU:
  Fix Released

Bug description:
  As of commit 28db64fce55,
  using demo from QEMU advent calendar 2018 day 1:
  https://www.qemu-advent-calendar.org/2018/download/day01.tar.xz

  $ qemu-system-x86_64 -M pc \
-net none -soundhw pcspk \
-drive file=day01/fbird.img,format=raw,if=floppy \
-monitor stdio -S
  (qemu) info qtree 
  bus: main-system-bus
type System
dev: i440FX-pcihost, id ""
  bus: pci.0
dev: PIIX3, id ""
  bus: isa.0
dev: isa-pcspk, id ""
  audiodev = "pa"
  iobase = 97 (0x61)
  migrate = true
  (qemu) wavcapture out.wav pa
  (qemu) cont
  (qemu) # Press 'up' key in demo
  Segmentation fault (core dumped)

  (gdb) bt
  #0  0x555bfef0dc51 in audio_pcm_sw_write (sw=0x555c01333930, buf=0x0, 
size=14728) at audio/audio.c:725
  #1  0x555bfef10a49 in audio_capture_mix_and_clear (hw=0x555c012379b0, 
rpos=0, samples=3682) at audio/audio.c:1054
  #2  0x555bfef11059 in audio_run_out (s=0x555c01235550) at 
audio/audio.c:1186
  #3  0x555bfef11894 in audio_run (s=0x555c01235550, msg=0x555bff3e37e8 
"timer") at audio/audio.c:1355
  #4  0x555bfef10334 in audio_timer (opaque=0x555c01235550) at 
audio/audio.c:831
  #5  0x555bff33f041 in timerlist_run_timers (timer_list=0x555c00377b50) at 
util/qemu-timer.c:588
  #6  0x555bff33f0eb in qemu_clock_run_timers (type=QEMU_CLOCK_VIRTUAL) at 
util/qemu-timer.c:602
  #7  0x555bff33f3b6 in qemu_clock_run_all_timers () at 
util/qemu-timer.c:688
  #8  0x555bff33fb60 in main_loop_wait (nonblocking=0) at 
util/main-loop.c:525
  #9  0x555bfef0187c in main_loop () at vl.c:1683
  #10 0x555bfef090ab in main (argc=12, argv=0x7ffec49184c8, 
envp=0x7ffec4918530) at vl.c:4438
  (gdb) p *sw
  $1 = {card = 0x0, s = 0x0, info = {bits = 16, sign = 1, freq = 44100, 
nchannels = 2, bytes_per_frame = 4, bytes_per_second = 176400, swap_endianness 
= 0}, conv = 0x555bfef0ced1 , ratio = 4294967296, buf = 
0x555c0123f6f0, 
rate = 0x555c007c0ec0, total_hw_samples_mixed = 0, active = 1, empty = 1, 
hw = 0x555c014b12a0, name = 0x0, vol = {mute = 0, r = 4294967296, l = 
4294967296}, callback = {opaque = 0x0, fn = 0x0}, entries = {le_next = 0x0, 
  le_prev = 0x555c014b1310}}
  (gdb) p *sw->hw
  $2 = {s = 0x555c01235550, enabled = 1, poll_mode = 0, pending_disable = 0, 
info = {bits = 16, sign = 1, freq = 44100, nchannels = 2, bytes_per_frame = 4, 
bytes_per_second = 176400, swap_endianness = 0}, 
clip = 0x555bfef16376 , ts_helper = 0, 
mix_buf = 0x555c0059d680, buf_emul = 0x0, pos_emul = 0, pending_emul = 0, 
size_emul = 0, samples = 16384, sw_head = {lh_first = 0x555c01333930}, cap_head 
= {
  lh_first = 0x0}, pcm_ops = 0x0, entries = {le_next = 0x0, le_prev = 0x0}}

  sw->hw->pcm_ops is NULL.

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Re: [Bug 1861677] Re: wavcapture crash with pulseaudio

[Philippe Mathieu-Daudé]

On 5/1/21 3:01 PM, Volker Rümelin wrote:
>> You received this bug notification because you are a member of qemu-
>> devel-ml, which is subscribed to QEMU.
>>https://bugs.launchpad.net/bugs/1861677
>>
>> Title:
>>  wavcapture crash with pulseaudio
>>
>> Status in QEMU:
>>  New
> 
> Hi Philippe,
> 
> this bug was fixed with commit cbaf25d1f5 "audio: fix wavcapture segfault".

Indeed, thanks!

Phil.

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

[Guenter Roeck]

On 4/30/21 9:28 PM, Bin Meng wrote:
> On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck  wrote:
>>
>> Hi,
>>
>> On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote:
>>> From: Bin Meng 
>>>
>>> At present, when booting U-Boot on QEMU sabrelite, we see:
>>>
>>>   Net:   Board Net Initialization Failed
>>>   No ethernet found.
>>>
>>> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
>>> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
>>> board, the Ethernet PHY is at address 6. Adjust this by updating the
>>> "fec-phy-num" property of the fsl_imx6 SoC object.
>>>
>>> With this change, U-Boot sees the PHY but complains MAC address:
>>>
>>>   Net:   using phy at 6
>>>   FEC [PRIME]
>>>   Error: FEC address not set.
>>>
>>> This is due to U-Boot tries to read the MAC address from the fuse,
>>> which QEMU does not have any valid content filled in. However this
>>> does not prevent the Ethernet from working in QEMU. We just need to
>>> set up the MAC address later in the U-Boot command shell, by:
>>>
>>>   => setenv ethaddr 00:11:22:33:44:55
>>>
>>
>> With this patch in place, the standard Ethernet interface no longer works 
>> when
>> booting sabrelite Linux images directly (without u-boot) using the following
>> qemu command.
>> qemu-system-arm -M sabrelite -kernel arch/arm/boot/zImage
>> ...
>>
>> The Ethernet interface still instantiates, but packet transfer to the host
>> no longer works. Reverting this patch fixes the problem for me.
>>
>> Is there a qemu command line parameter that is now necessary to instantiate
>> the Ethernet interface when booting Linux ?
> 
> Enabling "guest_errors" shows that Linux kernel fec driver is trying
> to read PHY at address 0, which is not what we want.
> 
> [imx.fec.phy]imx_phy_read: Bad phy num 0
> 
> The device tree blob of the sabrelite does not contain a node for the
> ethernet phy specifying phy address, so I suspect Linux kernel driver
> is using default phy address 0 instead.
> 
> Could you please test on a real hardware to see what happens?
> 

I don't have access to real hardware, sorry.

Guenter

Re: [Bug 1861677] Re: wavcapture crash with pulseaudio

[Volker Rümelin]

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>https://bugs.launchpad.net/bugs/1861677


Title:
 wavcapture crash with pulseaudio

Status in QEMU:
 New


Hi Philippe,

this bug was fixed with commit cbaf25d1f5 "audio: fix wavcapture segfault".

With best regards,
Volker