Re: [PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);


tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
  {
-#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-(op & (0x7 << 18)))
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-uint8_t df = (ctx->opcode >> 16) & 0x3;
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv_i32 tws = tcg_const_i32(ws);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);


tcg_constant_i32.

Missing check_msa_access.


+switch (a->df) {
+case DF_BYTE:
+if (gen_msa_2r_b == NULL) {
+gen_reserved_instruction(ctx);
+} else {
+gen_msa_2r_b(cpu_env, twd, tws);


Why the null check?


r~

Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

Convert the FILL opcode (Vector Fill from GPR) to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/tcg/msa.decode  |  2 ++
  target/mips/tcg/msa_translate.c | 40 +++--
  2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 2997bfa24e3..e97490cf880 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
  @ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
  @bz_v   .. ... ..wt:5 sa:16 _bz df=3
  @bz .. ...  df:2 wt:5 sa:16 _bz
+@2r ..   df:2 ws:5 wd:5 ..  _r wt=0
  @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
  @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
  @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
@@ -76,6 +77,7 @@ BNZ 010001 111 .. . 
@bz
SRARI 00 010 ... . .  001010  @bit
SRLRI 00 011 ... . .  001010  @bit
  
+  FILL  00 1100 .. . .  00  @2r

FCLASS00 11001 . . .  00  @2rf
FTRUNC_S  00 110010001 . . .  00  @2rf
FTRUNC_U  00 110010010 . . .  00  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c6a77381c0e..fc0b80f83ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -53,7 +53,6 @@ enum {
  OPC_MSA_2R  = (0x18 << 21) | OPC_MSA_VEC,
  
  /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */

-OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
  OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
  OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
  OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
@@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx)
  TCGv_i32 tws = tcg_const_i32(ws);
  
  switch (MASK_MSA_2R(ctx->opcode)) {

-case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
-/* Double format valid only for MIPS64 */
-if (df == DF_DOUBLE) {
-gen_reserved_instruction(ctx);
-break;
-}
-#endif
-gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
-   twd, tws); /* trs */
-break;
  case OPC_NLOC_df:
  switch (df) {
  case DF_BYTE:
@@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx)
  tcg_temp_free_i32(tws);
  }
  
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)

+{
+TCGv_i32 twd;
+TCGv_i32 tws;
+TCGv_i32 tdf;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+/* Double format valid only for MIPS64 */
+gen_reserved_instruction(ctx);
+return true;
+}


I expect this reserved check should be above the MSA is disabled check, within 
check_msa_access.



+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);


tcg_constant_i32.

r~

Re: [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);


tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+#define TRANS_DF_E(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)


I think this would be better as a table.

#define TRANS_DF_E(NAME, trans_func, gen_func) \
static void (* const NAME##_tab[4])(TCGv_ptr, TCGv_i32, TCGV) = { \
gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)   \
};\
TRANS_MSA(trans_func, NAME##_tag[a->df])


r~

[Bug 1921664] Re: Coroutines are racy for risc64 emu on arm64 - crash on Assertion

[Launchpad Bug Tracker]

[Expired for QEMU because there has been no activity for 60 days.]

** Changed in: qemu
   Status: Incomplete => Expired

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921664

Title:
  Coroutines are racy for risc64 emu on arm64 - crash on Assertion

Status in QEMU:
  Expired
Status in qemu package in Ubuntu:
  Expired

Bug description:
  Note: this could as well be "riscv64 on arm64" for being slow@slow and affect
  other architectures as well.

  The following case triggers on a Raspberry Pi4 running with arm64 on
  Ubuntu 21.04 [1][2]. It might trigger on other environments as well,
  but that is what we have seen it so far.

 $ wget 
https://github.com/carlosedp/riscv-bringup/releases/download/v1.0/UbuntuFocal-riscv64-QemuVM.tar.gz
 $ tar xzf UbuntuFocal-riscv64-QemuVM.tar.gz
 $ ./run_riscvVM.sh
  (wait ~2 minutes)
 [ OK ] Reached target Local File Systems (Pre).
 [ OK ] Reached target Local File Systems.
  Starting udev Kernel Device Manager...
  qemu-system-riscv64: ../../util/qemu-coroutine-lock.c:57: 
qemu_co_queue_wait_impl: Assertion `qemu_in_coroutine()' failed.

  This is often, but not 100% reproducible and the cases differ slightly we
  see either of:
  - qemu-system-riscv64: ../../util/qemu-coroutine-lock.c:57: 
qemu_co_queue_wait_impl: Assertion `qemu_in_coroutine()' failed.
  - qemu-system-riscv64: ../../block/aio_task.c:64: aio_task_pool_wait_one: 
Assertion `qemu_coroutine_self() == pool->main_co' failed.

  Rebuilding working cases has shown to make them fail, as well as rebulding
  (or even reinstalling) bad cases has made them work. Also the same builds on
  different arm64 CPUs behave differently. TL;DR: The full list of conditions
  influencing good/bad case here are not yet known.

  [1]: 
https://ubuntu.com/tutorials/how-to-install-ubuntu-on-your-raspberry-pi#1-overview
  [2]: 
http://cdimage.ubuntu.com/daily-preinstalled/pending/hirsute-preinstalled-desktop-arm64+raspi.img.xz

  
  --- --- original report --- ---

  I regularly run a RISC-V (RV64GC) QEMU VM, but an update a few days
  ago broke it.  Now when I launch it, it hits an assertion:

  OpenSBI v0.6
     _  _
    / __ \  / |  _ \_   _|
   | |  | |_ __   ___ _ __ | (___ | |_) || |
   | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
   | |__| | |_) |  __/ | | |) | |_) || |_
    \/| .__/ \___|_| |_|_/|/_|
  | |
  |_|

  ...
  Found /boot/extlinux/extlinux.conf
  Retrieving file: /boot/extlinux/extlinux.conf
  618 bytes read in 2 ms (301.8 KiB/s)
  RISC-V Qemu Boot Options
  1:  Linux kernel-5.5.0-dirty
  2:  Linux kernel-5.5.0-dirty (recovery mode)
  Enter choice: 1:Linux kernel-5.5.0-dirty
  Retrieving file: /boot/initrd.img-5.5.0-dirty
  qemu-system-riscv64: ../../block/aio_task.c:64: aio_task_pool_wait_one: 
Assertion `qemu_coroutine_self() == pool->main_co' failed.
  ./run.sh: line 31:  1604 Aborted (core dumped) 
qemu-system-riscv64 -machine virt -nographic -smp 8 -m 8G -bios fw_payload.bin 
-device virtio-blk-devi
  ce,drive=hd0 -object rng-random,filename=/dev/urandom,id=rng0 -device 
virtio-rng-device,rng=rng0 -drive 
file=riscv64-UbuntuFocal-qemu.qcow2,format=qcow2,id=hd0 -devi
  ce virtio-net-device,netdev=usernet -netdev user,id=usernet,$ports

  Interestingly this doesn't happen on the AMD64 version of Ubuntu 21.04
  (fully updated).

  Think you have everything already, but just in case:

  $ lsb_release -rd
  Description:Ubuntu Hirsute Hippo (development branch)
  Release:21.04

  $ uname -a
  Linux minimacvm 5.11.0-11-generic #12-Ubuntu SMP Mon Mar 1 19:27:36 UTC 2021 
aarch64 aarch64 aarch64 GNU/Linux
  (note this is a VM running on macOS/M1)

  $ apt-cache policy qemu
  qemu:
    Installed: 1:5.2+dfsg-9ubuntu1
    Candidate: 1:5.2+dfsg-9ubuntu1
    Version table:
   *** 1:5.2+dfsg-9ubuntu1 500
  500 http://ports.ubuntu.com/ubuntu-ports hirsute/universe arm64 
Packages
  100 /var/lib/dpkg/status

  ProblemType: Bug
  DistroRelease: Ubuntu 21.04
  Package: qemu 1:5.2+dfsg-9ubuntu1
  ProcVersionSignature: Ubuntu 5.11.0-11.12-generic 5.11.0
  Uname: Linux 5.11.0-11-generic aarch64
  ApportVersion: 2.20.11-0ubuntu61
  Architecture: arm64
  CasperMD5CheckResult: unknown
  CurrentDmesg:
   Error: command ['pkexec', 'dmesg'] failed with exit code 127: 
polkit-agent-helper-1: error response to PolicyKit daemon: 
GDBus.Error:org.freedesktop.PolicyKit1.Error.Failed: No session for cookie
   Error executing command as another user: Not authorized

   This incident has been reported.
  Date: Mon Mar 29 02:33:25 2021
  Dependencies:

  KvmCmdLine: COMMAND STAT  EUID  RUID PIDPPID %CPU COMMAND
  Lspci-vt:
   -[:00]-+-00.0  Apple Inc. Device f020
  +-01.0  Red Hat, Inc. Virtio network device
  +-05.0  

[Bug 1921664] Re: Coroutines are racy for risc64 emu on arm64 - crash on Assertion

[Launchpad Bug Tracker]

[Expired for qemu (Ubuntu) because there has been no activity for 60
days.]

** Changed in: qemu (Ubuntu)
   Status: Incomplete => Expired

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1921664

Title:
  Coroutines are racy for risc64 emu on arm64 - crash on Assertion

Status in QEMU:
  Expired
Status in qemu package in Ubuntu:
  Expired

Bug description:
  Note: this could as well be "riscv64 on arm64" for being slow@slow and affect
  other architectures as well.

  The following case triggers on a Raspberry Pi4 running with arm64 on
  Ubuntu 21.04 [1][2]. It might trigger on other environments as well,
  but that is what we have seen it so far.

 $ wget 
https://github.com/carlosedp/riscv-bringup/releases/download/v1.0/UbuntuFocal-riscv64-QemuVM.tar.gz
 $ tar xzf UbuntuFocal-riscv64-QemuVM.tar.gz
 $ ./run_riscvVM.sh
  (wait ~2 minutes)
 [ OK ] Reached target Local File Systems (Pre).
 [ OK ] Reached target Local File Systems.
  Starting udev Kernel Device Manager...
  qemu-system-riscv64: ../../util/qemu-coroutine-lock.c:57: 
qemu_co_queue_wait_impl: Assertion `qemu_in_coroutine()' failed.

  This is often, but not 100% reproducible and the cases differ slightly we
  see either of:
  - qemu-system-riscv64: ../../util/qemu-coroutine-lock.c:57: 
qemu_co_queue_wait_impl: Assertion `qemu_in_coroutine()' failed.
  - qemu-system-riscv64: ../../block/aio_task.c:64: aio_task_pool_wait_one: 
Assertion `qemu_coroutine_self() == pool->main_co' failed.

  Rebuilding working cases has shown to make them fail, as well as rebulding
  (or even reinstalling) bad cases has made them work. Also the same builds on
  different arm64 CPUs behave differently. TL;DR: The full list of conditions
  influencing good/bad case here are not yet known.

  [1]: 
https://ubuntu.com/tutorials/how-to-install-ubuntu-on-your-raspberry-pi#1-overview
  [2]: 
http://cdimage.ubuntu.com/daily-preinstalled/pending/hirsute-preinstalled-desktop-arm64+raspi.img.xz

  
  --- --- original report --- ---

  I regularly run a RISC-V (RV64GC) QEMU VM, but an update a few days
  ago broke it.  Now when I launch it, it hits an assertion:

  OpenSBI v0.6
     _  _
    / __ \  / |  _ \_   _|
   | |  | |_ __   ___ _ __ | (___ | |_) || |
   | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
   | |__| | |_) |  __/ | | |) | |_) || |_
    \/| .__/ \___|_| |_|_/|/_|
  | |
  |_|

  ...
  Found /boot/extlinux/extlinux.conf
  Retrieving file: /boot/extlinux/extlinux.conf
  618 bytes read in 2 ms (301.8 KiB/s)
  RISC-V Qemu Boot Options
  1:  Linux kernel-5.5.0-dirty
  2:  Linux kernel-5.5.0-dirty (recovery mode)
  Enter choice: 1:Linux kernel-5.5.0-dirty
  Retrieving file: /boot/initrd.img-5.5.0-dirty
  qemu-system-riscv64: ../../block/aio_task.c:64: aio_task_pool_wait_one: 
Assertion `qemu_coroutine_self() == pool->main_co' failed.
  ./run.sh: line 31:  1604 Aborted (core dumped) 
qemu-system-riscv64 -machine virt -nographic -smp 8 -m 8G -bios fw_payload.bin 
-device virtio-blk-devi
  ce,drive=hd0 -object rng-random,filename=/dev/urandom,id=rng0 -device 
virtio-rng-device,rng=rng0 -drive 
file=riscv64-UbuntuFocal-qemu.qcow2,format=qcow2,id=hd0 -devi
  ce virtio-net-device,netdev=usernet -netdev user,id=usernet,$ports

  Interestingly this doesn't happen on the AMD64 version of Ubuntu 21.04
  (fully updated).

  Think you have everything already, but just in case:

  $ lsb_release -rd
  Description:Ubuntu Hirsute Hippo (development branch)
  Release:21.04

  $ uname -a
  Linux minimacvm 5.11.0-11-generic #12-Ubuntu SMP Mon Mar 1 19:27:36 UTC 2021 
aarch64 aarch64 aarch64 GNU/Linux
  (note this is a VM running on macOS/M1)

  $ apt-cache policy qemu
  qemu:
    Installed: 1:5.2+dfsg-9ubuntu1
    Candidate: 1:5.2+dfsg-9ubuntu1
    Version table:
   *** 1:5.2+dfsg-9ubuntu1 500
  500 http://ports.ubuntu.com/ubuntu-ports hirsute/universe arm64 
Packages
  100 /var/lib/dpkg/status

  ProblemType: Bug
  DistroRelease: Ubuntu 21.04
  Package: qemu 1:5.2+dfsg-9ubuntu1
  ProcVersionSignature: Ubuntu 5.11.0-11.12-generic 5.11.0
  Uname: Linux 5.11.0-11-generic aarch64
  ApportVersion: 2.20.11-0ubuntu61
  Architecture: arm64
  CasperMD5CheckResult: unknown
  CurrentDmesg:
   Error: command ['pkexec', 'dmesg'] failed with exit code 127: 
polkit-agent-helper-1: error response to PolicyKit daemon: 
GDBus.Error:org.freedesktop.PolicyKit1.Error.Failed: No session for cookie
   Error executing command as another user: Not authorized

   This incident has been reported.
  Date: Mon Mar 29 02:33:25 2021
  Dependencies:

  KvmCmdLine: COMMAND STAT  EUID  RUID PIDPPID %CPU COMMAND
  Lspci-vt:
   -[:00]-+-00.0  Apple Inc. Device f020
  +-01.0  Red Hat, Inc. Virtio network device
   

Re: [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 timm = tcg_const_i32(a->sa);


tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+timm = tcg_const_i32(a->sa);


tcg_constant_i32.  Otherwise,
Reviewed-by: Richard Henderson 

r~

Re: [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

  @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
  @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
  @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
+@bit.. ... df:7   ws:5 wd:5 ..  _ldst sa=0


Not sure why you seem over-keen to use _ldst, with fields that don't apply to these 
insns.  Drop that and you can more properly name the field dfm.



+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);


tcg_constant_i32.


r~

Re: [PATCH 10/33] target/mips: Extract df_extract() helper

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

Extract the common code which parses data formats to an helper.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/tcg/msa_translate.c | 68 +++--
  1 file changed, 39 insertions(+), 29 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3b0dfcca69d..7c1bbfaec61 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -272,6 +272,40 @@ static const char msaregnames[][6] = {
  "w30.d0", "w30.d1", "w31.d0", "w31.d1",
  };
  
+/* Encoding of Operation Field */

+static const struct dfe {
+enum CPUMIPSMSADataFormat df;
+int start;
+int length;
+uint32_t value;
+} df_elm[] = {
+/* Table 3.26 ELM Instruction Format */
+{DF_BYTE,   4, 2, 0b00},
+{DF_HALF,   3, 3, 0b100},
+{DF_WORD,   2, 4, 0b1100},
+{DF_DOUBLE, 1, 5, 0b11100}
+}, df_bit[] = {
+/* Table 3.28 BIT Instruction Format */
+{DF_BYTE,   3, 4, 0b1110},
+{DF_HALF,   4, 3, 0b110},
+{DF_WORD,   5, 2, 0b10},
+{DF_DOUBLE, 6, 1, 0b0}
+};


Possibly clearer as separate declarations instead of the comma.
The df field is redundant with the index.  At which point perhaps a

typedef const struct dfe dfe4[4];

might be helpful, both for the two declarations and...


+/* Extract Operation Field (used by ELM & BIT instructions) */
+static bool df_extract(const struct dfe *s, int value,
+   enum CPUMIPSMSADataFormat *df, uint32_t *x)


... the parameter.


+uint32_t df, m;

...

+if (!df_extract(df_bit, dfm, , )) {


How does the type of df not match the parameter?
Incomplete rebase?


r~

Re: [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
+TCGv_i32, TCGv_i32))
  {
+TCGv_i32 tdf = tcg_constant_i32(a->df);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 timm = tcg_const_i32(a->sa);


tcg_constant_i32.  Otherwise,

Reviewed-by: Richard Henderson 


r~

Re: [PATCH v2 1/2] vfio/pci: Fix vfio-pci sub-page MMIO BAR mmaping in live migration

[Kunkun Jiang]

Hi Eric,

On 2021/10/23 22:26, Eric Auger wrote:

Hi Kunkun,

On 10/22/21 12:01 PM, Kunkun Jiang wrote:

Hi Eric,

On 2021/10/22 0:15, Eric Auger wrote:

Hi Kunkun,

On 9/14/21 3:53 AM, Kunkun Jiang wrote:

We expand MemoryRegions of vfio-pci sub-page MMIO BARs to
vfio_pci_write_config to improve IO performance.

s/to vfio_pci_write_config/ in vfio_pci_write_config()

Thank you for your review. I will correct it in v3.

The MemoryRegions of destination VM will not be expanded
successful in live migration, because their addresses have

s/will not be expanded successful in live migration/are not expanded
anymore after live migration (?) Is that the correct symptom?

You are right. They are not expanded anymore after live migration,
not expanded unsuccessfully. I used the wrong words.

been updated in vmstate_load_state (vfio_pci_load_config).

So iterate BARs in vfio_pci_write_config and try to update
sub-page BARs.

Fixes: c5e2fb3ce4d (vfio: Add save and load functions for VFIO PCI
devices)

is it an actual fix or an optimization?

I recently realized that this is actually an optimization.

The VF driver in VM use the assembly language instructions,
which can operate two registers simultaneously, like stp, ldp.
These instructions would result in non-ISV data abort, which
cannot be handled well at the moment.

If the driver doesn't use such instructions,  not expanding
only affects performance.

I will add these to the commit message in the next version.

Reported-by: Nianyao Tang 
Reported-by: Qixin Gan 
Signed-off-by: Kunkun Jiang 
---
   hw/vfio/pci.c | 15 ++-
   1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index e1ea1d8a23..43c7e93153 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -2453,7 +2453,12 @@ static int vfio_pci_load_config(VFIODevice
*vbasedev, QEMUFile *f)
   {
   VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice,
vbasedev);
   PCIDevice *pdev = >pdev;
-    int ret;
+    pcibus_t old_addr[PCI_NUM_REGIONS - 1];
+    int bar, ret;
+
+    for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
+    old_addr[bar] = pdev->io_regions[bar].addr;
+    }

what are those values before the vmstate_load_state ie. can't you do the

Are you referring to pdev->io_regions[bar].addr ? All of the bars addr is
PCI_BAR_UNMAPPED (~(pcibus_t)0) before the vmstate_load_state.

OK that was my assumption. What I meant is in that case you always have

old_addr[bar] != pdev->io_regions[bar].addr, right? In the positive this check 
is not needed and you don't need old_addr at all.
In the original code this was needed since one wanted to call
vfio_sub_page_bar_update_mapping() only for the bar base address that were 
changed during the
vfio_pci_write_config.

As far as I know, there is at least one case. If the VF driver is not loaded
(insmod xxx.ko) in the VM, we will have old_addr[bar] == 
pdev->io_regions[bar].addr.
The vfio_sub_page_bar_update_mapping() will be called when 0 < bar size 
< host page size.
But vfio_sub_page_bar_update_mapping() will not change anything in this 
case.


Thanks,
Kunkun Jiang


Thanks

Eric


vfio_sub_page_bar_update_mapping() unconditionnaly on old_addr[bar] !=
pdev->io_regions[bar].addr

The size of Bar is a power of 2. The Bar, whose size is greater than host
page size, doesn't need to be expanded.

Can you explain more? May be I misunderstood you.

Thanks,
Kunkun Jiang

     ret = vmstate_load_state(f, _vfio_pci_config, vdev, 1);
   if (ret) {
@@ -2463,6 +2468,14 @@ static int vfio_pci_load_config(VFIODevice
*vbasedev, QEMUFile *f)
   vfio_pci_write_config(pdev, PCI_COMMAND,
     pci_get_word(pdev->config +
PCI_COMMAND), 2);
   +    for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
+    if (old_addr[bar] != pdev->io_regions[bar].addr &&
+    vdev->bars[bar].region.size > 0 &&
+    vdev->bars[bar].region.size < qemu_real_host_page_size) {
+    vfio_sub_page_bar_update_mapping(pdev, bar);
+    }
+    }
+
   if (msi_enabled(pdev)) {
   vfio_msi_enable(vdev);
   } else if (msix_enabled(pdev)) {

Thanks

Eric

.

.

Re: [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

Similar to the TRANS() macro introduced in commit fb3164e412d,
introduce TRANS_CHECK() which takes a boolean expression as
argument.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/tcg/translate.h | 9 +
  1 file changed, 9 insertions(+)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 6111493651f..3ef09cc50c9 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -224,6 +224,15 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
  static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  { return FUNC(ctx, a, __VA_ARGS__); }
  
+#define TRANS_CHECK(NAME, CHECK_EXPR, FUNC, ...) \

+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+if (!(CHECK_EXPR)) { \
+return false; \
+} \
+return FUNC(ctx, a, __VA_ARGS__); \
+}


So... if you're going to do this generically, you may want to adjust check_msa_access. 
OTOH, perhaps all you want is a more local TRANS_MSA, with the CHECK_EXPR built in.



r~

Re: [PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

+static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
+{
+TCGv_i32 tdf;
+TCGv_i32 twd;
+TCGv_i32 timm;
+
+if (!check_msa_access(ctx)) {
+return false;
+}


Return true.  I won't mention the return after check_msa_access again.


+twd = tcg_const_i32(a->wd);
+timm = tcg_const_i32(a->sa);


tcg_constant_i32.


r~

Re: [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

[Boris Ostrovsky]

On 10/23/21 4:14 PM, Michael S. Tsirkin wrote:

On Sat, Oct 23, 2021 at 07:52:21AM +0530, Ani Sinha wrote:


On Fri, 22 Oct 2021, Eric DeVolder wrote:


Ani, inline below.
eric

On 10/22/21 05:18, Ani Sinha wrote:


On Fri, 15 Oct 2021, Eric DeVolder wrote:



diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c

I do not think we need to include this for microvm machines. They are
supposed to have minimal ACPUI support. So lets not bloat it unless there
is a specific requirement to support ERST on microvms as well.

Would it be ok if I ifdef this on CONFIG_ERST also?

I think we should not touch microvm machine unless you can justify why you
need ERST support there.

OTOH why not? No idea... CC microvm maintainers and let them decide.



I would argue that ERST support for microvm is in fact more useful than for 
"regular" VMs: those VMs can use EFI storage for pstore while microvms won't 
have that option.


-boris

Re: [PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.

Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/tcg/msa.decode  | 15 +++
  target/mips/tcg/msa_translate.c | 20 ++--
  2 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 74d99f6862c..aa784cf12a9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,19 +13,18 @@
  
rs rt rd sa
  
-_bz df wt s16

+_bz df   wt sa


Tab or odd spacing?  Otherwise,

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.

Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/tcg/msa_translate.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 05/33] target/mips: Have check_msa_access() return a boolean

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled.

Signed-off-by: Philippe Mathieu-Daudé 
---
  target/mips/tcg/msa_translate.c | 20 +---
  1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..9e0a08fe335 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -293,19 +293,19 @@ void msa_translate_init(void)
  }
  }
  
-static inline int check_msa_access(DisasContext *ctx)

+static inline bool check_msa_access(DisasContext *ctx)
  {
  if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
   !(ctx->hflags & MIPS_HFLAG_F64))) {
  gen_reserved_instruction(ctx);
-return 0;
+return false;
  }
  
  if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {

  generate_exception_end(ctx, EXCP_MSADIS);
-return 0;
+return false;
  }


When we return false, we have raised an exception.


@@ -354,7 +354,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int 
s16, TCGCond cond)
  {
  TCGv_i64 t0;
  
-check_msa_access(ctx);

+if (!check_msa_access(ctx)) {
+return false;
+}


... which means that here we should return true, meaning that we have recognized the 
instruction and emitted some code for it.  In this case: we have recognized that the 
instruction is valid but not enabled.


Otherwise, we will return to decode_opc and (eventually) emit another 
gen_reserved_instruction.



r~

[PATCH 3/5] hw/sh4: Coding style: White space fixes

[BALATON Zoltan]

Signed-off-by: BALATON Zoltan 
---
 hw/char/sh_serial.c  | 23 ++-
 hw/intc/sh_intc.c| 25 -
 hw/pci-host/sh_pci.c | 10 --
 hw/sh4/r2d.c | 39 ---
 hw/sh4/sh7750.c  | 26 +-
 hw/sh4/sh7750_regnames.c |  5 +++--
 hw/sh4/sh7750_regs.h | 18 +-
 hw/sh4/shix.c|  2 +-
 hw/timer/sh_timer.c  | 22 --
 include/hw/sh4/sh.h  | 10 +-
 10 files changed, 97 insertions(+), 83 deletions(-)

diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c
index 05ae8e84ce..3fdb9f9a99 100644
--- a/hw/char/sh_serial.c
+++ b/hw/char/sh_serial.c
@@ -75,7 +75,7 @@ typedef struct {
 qemu_irq bri;
 } sh_serial_state;
 
-static void sh_serial_clear_fifo(sh_serial_state * s)
+static void sh_serial_clear_fifo(sh_serial_state *s)
 {
 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
 s->rx_cnt = 0;
@@ -93,7 +93,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 printf("sh_serial: write offs=0x%02x val=0x%02x\n",
offs, val);
 #endif
-switch(offs) {
+switch (offs) {
 case 0x00: /* SMR */
 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
 return;
@@ -131,7 +131,7 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 #endif
 }
 if (s->feat & SH_SERIAL_FEAT_SCIF) {
-switch(offs) {
+switch (offs) {
 case 0x10: /* FSR */
 if (!(val & (1 << 6)))
 s->flags &= ~SH_SERIAL_FLAG_TEND;
@@ -178,9 +178,8 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 case 0x24: /* LSR */
 return;
 }
-}
-else {
-switch(offs) {
+} else {
+switch (offs) {
 #if 0
 case 0x0c:
 ret = s->dr;
@@ -207,7 +206,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
 uint32_t ret = ~0;
 
 #if 0
-switch(offs) {
+switch (offs) {
 case 0x00:
 ret = s->smr;
 break;
@@ -223,7 +222,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
 }
 #endif
 if (s->feat & SH_SERIAL_FEAT_SCIF) {
-switch(offs) {
+switch (offs) {
 case 0x00: /* SMR */
 ret = s->smr;
 break;
@@ -270,9 +269,8 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
 ret = 0;
 break;
 }
-}
-else {
-switch(offs) {
+} else {
+switch (offs) {
 #if 0
 case 0x0c:
 ret = s->dr;
@@ -397,8 +395,7 @@ void sh_serial_init(MemoryRegion *sysmem,
 
 if (feat & SH_SERIAL_FEAT_SCIF) {
 s->fcr = 0;
-}
-else {
+} else {
 s->dr = 0xff;
 }
 
diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c
index 84eec7d4ba..783a05fa38 100644
--- a/hw/intc/sh_intc.c
+++ b/hw/intc/sh_intc.c
@@ -74,7 +74,7 @@ void sh_intc_toggle_source(struct intc_source *source,
   }
 }
 
-static void sh_intc_set_irq (void *opaque, int n, int level)
+static void sh_intc_set_irq(void *opaque, int n, int level)
 {
   struct intc_desc *desc = opaque;
   struct intc_source *source = &(desc->sources[n]);
@@ -236,7 +236,7 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset,
 printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
 #endif
 
-sh_intc_locate(desc, (unsigned long)offset, , 
+sh_intc_locate(desc, (unsigned long)offset, ,
_ids, , , );
 return *valuep;
 }
@@ -257,14 +257,20 @@ static void sh_intc_write(void *opaque, hwaddr offset,
 printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 #endif
 
-sh_intc_locate(desc, (unsigned long)offset, , 
+sh_intc_locate(desc, (unsigned long)offset, ,
_ids, , , );
 
 switch (mode) {
-case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
-case INTC_MODE_DUAL_SET: value |= *valuep; break;
-case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
-default: abort();
+case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
+break;
+case INTC_MODE_DUAL_SET:
+value |= *valuep;
+break;
+case INTC_MODE_DUAL_CLR:
+value = *valuep & ~value;
+break;
+default:
+abort();
 }
 
 for (k = 0; k <= first; k++) {
@@ -465,7 +471,7 @@ int sh_intc_init(MemoryRegion *sysmem,
 }
 
 desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
- 
+
 memory_region_init_io(>iomem, NULL, _intc_ops, desc,
   "interrupt-controller", 0x1ULL);
 
@@ -507,7 +513,8 @@ void sh_intc_set_irl(void *opaque, int n, int level)
 int i, irl = level ^ 15;
 for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
 if (i == irl)
-sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
+sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
+  

[PATCH 4/5] hw/sh4: Coding style: Add missing braces

[BALATON Zoltan]

Signed-off-by: BALATON Zoltan 
---
 hw/char/sh_serial.c  | 48 +++
 hw/intc/sh_intc.c| 83 ++--
 hw/sh4/r2d.c | 15 +---
 hw/sh4/sh7750.c  | 24 
 hw/sh4/sh7750_regnames.c |  3 +-
 hw/timer/sh_timer.c  | 22 ++-
 6 files changed, 116 insertions(+), 79 deletions(-)

diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c
index 3fdb9f9a99..1b1e6a6a04 100644
--- a/hw/char/sh_serial.c
+++ b/hw/char/sh_serial.c
@@ -103,8 +103,9 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 case 0x08: /* SCR */
 /* TODO : For SH7751, SCIF mask should be 0xfb. */
 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
-if (!(val & (1 << 5)))
+if (!(val & (1 << 5))) {
 s->flags |= SH_SERIAL_FLAG_TEND;
+}
 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
 qemu_set_irq(s->txi, val & (1 << 7));
 }
@@ -133,16 +134,21 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 if (s->feat & SH_SERIAL_FEAT_SCIF) {
 switch (offs) {
 case 0x10: /* FSR */
-if (!(val & (1 << 6)))
+if (!(val & (1 << 6))) {
 s->flags &= ~SH_SERIAL_FLAG_TEND;
-if (!(val & (1 << 5)))
+}
+if (!(val & (1 << 5))) {
 s->flags &= ~SH_SERIAL_FLAG_TDE;
-if (!(val & (1 << 4)))
+}
+if (!(val & (1 << 4))) {
 s->flags &= ~SH_SERIAL_FLAG_BRK;
-if (!(val & (1 << 1)))
+}
+if (!(val & (1 << 1))) {
 s->flags &= ~SH_SERIAL_FLAG_RDF;
-if (!(val & (1 << 0)))
+}
+if (!(val & (1 << 0))) {
 s->flags &= ~SH_SERIAL_FLAG_DR;
+}
 
 if (!(val & (1 << 1)) || !(val & (1 << 0))) {
 if (s->rxi) {
@@ -231,29 +237,37 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
 break;
 case 0x10: /* FSR */
 ret = 0;
-if (s->flags & SH_SERIAL_FLAG_TEND)
+if (s->flags & SH_SERIAL_FLAG_TEND) {
 ret |= (1 << 6);
-if (s->flags & SH_SERIAL_FLAG_TDE)
+}
+if (s->flags & SH_SERIAL_FLAG_TDE) {
 ret |= (1 << 5);
-if (s->flags & SH_SERIAL_FLAG_BRK)
+}
+if (s->flags & SH_SERIAL_FLAG_BRK) {
 ret |= (1 << 4);
-if (s->flags & SH_SERIAL_FLAG_RDF)
+}
+if (s->flags & SH_SERIAL_FLAG_RDF) {
 ret |= (1 << 1);
-if (s->flags & SH_SERIAL_FLAG_DR)
+}
+if (s->flags & SH_SERIAL_FLAG_DR) {
 ret |= (1 << 0);
+}
 
-if (s->scr & (1 << 5))
+if (s->scr & (1 << 5)) {
 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
+}
 
 break;
 case 0x14:
 if (s->rx_cnt > 0) {
 ret = s->rx_fifo[s->rx_tail++];
 s->rx_cnt--;
-if (s->rx_tail == SH_RX_FIFO_LENGTH)
+if (s->rx_tail == SH_RX_FIFO_LENGTH) {
 s->rx_tail = 0;
-if (s->rx_cnt < s->rtrg)
+}
+if (s->rx_cnt < s->rtrg) {
 s->flags &= ~SH_SERIAL_FLAG_RDF;
+}
 }
 break;
 case 0x18:
@@ -308,8 +322,9 @@ static int sh_serial_can_receive(sh_serial_state *s)
 
 static void sh_serial_receive_break(sh_serial_state *s)
 {
-if (s->feat & SH_SERIAL_FEAT_SCIF)
+if (s->feat & SH_SERIAL_FEAT_SCIF) {
 s->sr |= (1 << 4);
+}
 }
 
 static int sh_serial_can_receive1(void *opaque)
@@ -361,8 +376,9 @@ static void sh_serial_receive1(void *opaque, const uint8_t 
*buf, int size)
 static void sh_serial_event(void *opaque, QEMUChrEvent event)
 {
 sh_serial_state *s = opaque;
-if (event == CHR_EVENT_BREAK)
+if (event == CHR_EVENT_BREAK) {
 sh_serial_receive_break(s);
+}
 }
 
 static const MemoryRegionOps sh_serial_ops = {
diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c
index 783a05fa38..e7c9964dba 100644
--- a/hw/intc/sh_intc.c
+++ b/hw/intc/sh_intc.c
@@ -26,23 +26,23 @@ void sh_intc_toggle_source(struct intc_source *source,
 int pending_changed = 0;
 int old_pending;
 
-if ((source->enable_count == source->enable_max) && (enable_adj == -1))
+if ((source->enable_count == source->enable_max) && (enable_adj == -1)) {
 enable_changed = -1;
-
+}
 source->enable_count += enable_adj;
 
-if (source->enable_count == source->enable_max)
+if (source->enable_count == source->enable_max) {
 enable_changed = 1;
-
+}
 source->asserted += assert_adj;
 
 old_pending = source->pending;
 source->pending = source->asserted &&
   

[PATCH 5/5] hw/sh4: Coding style: Remove unnecessary casts

[BALATON Zoltan]

Signed-off-by: BALATON Zoltan 
---
 hw/timer/sh_timer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
index 68c109ecfd..02eb865908 100644
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@@ -233,7 +233,7 @@ static void *sh_timer_init(uint32_t freq, int feat, 
qemu_irq irq)
 {
 sh_timer_state *s;
 
-s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
+s = g_malloc0(sizeof(*s));
 s->freq = freq;
 s->feat = feat;
 s->tcor = 0x;
@@ -358,7 +358,7 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base,
 tmu012_state *s;
 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 
-s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
+s = g_malloc0(sizeof(*s));
 s->feat = feat;
 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
-- 
2.21.4

[PATCH 2/5] hw/sh4: Coding style: Fix multi-line comments

[BALATON Zoltan]

Signed-off-by: BALATON Zoltan 
---
 hw/char/sh_serial.c  |   6 +-
 hw/intc/sh_intc.c|   9 +-
 hw/sh4/r2d.c |   6 +-
 hw/sh4/sh7750.c  |  22 +-
 hw/sh4/sh7750_regs.h | 504 +--
 hw/sh4/shix.c|  10 +-
 hw/timer/sh_timer.c  |   7 +-
 7 files changed, 286 insertions(+), 278 deletions(-)

diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c
index 167f4d8cb9..05ae8e84ce 100644
--- a/hw/char/sh_serial.c
+++ b/hw/char/sh_serial.c
@@ -115,8 +115,10 @@ static void sh_serial_write(void *opaque, hwaddr offs,
 case 0x0c: /* FTDR / TDR */
 if (qemu_chr_fe_backend_connected(>chr)) {
 ch = val;
-/* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
+/*
+ * XXX this blocks entire thread. Rewrite to use
+ * qemu_chr_fe_write and background I/O callbacks
+ */
 qemu_chr_fe_write_all(>chr, , 1);
 }
 s->dr = val;
diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c
index a269b8fbd4..84eec7d4ba 100644
--- a/hw/intc/sh_intc.c
+++ b/hw/intc/sh_intc.c
@@ -450,8 +450,7 @@ int sh_intc_init(MemoryRegion *sysmem,
 desc->nr_mask_regs = nr_mask_regs;
 desc->prio_regs = prio_regs;
 desc->nr_prio_regs = nr_prio_regs;
-/* Allocate 4 MemoryRegions per register (2 actions * 2 aliases).
- **/
+/* Allocate 4 MemoryRegions per register (2 actions * 2 aliases) */
 desc->iomem_aliases = g_new0(MemoryRegion,
  (nr_mask_regs + nr_prio_regs) * 4);
 
@@ -498,8 +497,10 @@ int sh_intc_init(MemoryRegion *sysmem,
 return 0;
 }
 
-/* Assert level  IRL interrupt. 
-   0:deassert. 1:lowest priority,... 15:highest priority. */
+/*
+ * Assert level  IRL interrupt.
+ * 0:deassert. 1:lowest priority,... 15:highest priority
+ */
 void sh_intc_set_irl(void *opaque, int n, int level)
 {
 struct intc_source *s = opaque;
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 8f0d373b09..46f1fae48c 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -352,8 +352,10 @@ static void r2d_init(MachineState *machine)
 }
 
 if (kernel_cmdline) {
-/* I see no evidence that this .kernel_cmdline buffer requires
-   NUL-termination, so using strncpy should be ok. */
+/*
+ * I see no evidence that this .kernel_cmdline buffer requires
+ * NUL-termination, so using strncpy should be ok.
+ */
 strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 sizeof(boot_params.kernel_cmdline));
 }
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 2a175bfa74..2539924b00 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -82,9 +82,10 @@ static inline int has_bcr3_and_bcr4(SH7750State * s)
 {
 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
 }
-/**
- I/O ports
-**/
+
+/*
+ * I/O ports
+ */
 
 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
 {
@@ -194,9 +195,9 @@ static void portb_changed(SH7750State * s, uint16_t prev)
 gen_port_interrupts(s);
 }
 
-/**
- Memory
-**/
+/*
+ * Memory
+ */
 
 static void error_access(const char *kind, hwaddr addr)
 {
@@ -491,7 +492,8 @@ static const MemoryRegionOps sh7750_mem_ops = {
 .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-/* sh775x interrupt controller tables for sh_intc.c
+/*
+ * sh775x interrupt controller tables for sh_intc.c
  * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
  */
 
@@ -642,9 +644,9 @@ static struct intc_group groups_irl[] = {
 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
 };
 
-/**
- Memory mapped cache and TLB
-**/
+/*
+ * Memory mapped cache and TLB
+ */
 
 #define MM_REGION_MASK   0x0700
 #define MM_ICACHE_ADDR   (0)
diff --git a/hw/sh4/sh7750_regs.h b/hw/sh4/sh7750_regs.h
index fd1050646f..bd12b0532d 100644
--- a/hw/sh4/sh7750_regs.h
+++ b/hw/sh4/sh7750_regs.h
@@ -43,8 +43,7 @@
  * All register has 2 addresses: in 0xff00 - 0x (P4 address)  and
  * in 0x1f00 - 0x1fff (area 7 address)
  */
-#define SH7750_P4_BASE   0xff00 /* Accessible only in
-   privileged mode */
+#define SH7750_P4_BASE   0xff00 /* Accessible only in privileged mode 
*/
 #define SH7750_A7_BASE   0x1f00 /* Accessible only using TLB */
 
 #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
@@ -81,24 +80,24 @@
 #define SH7750_PTEL_PR_RWPO   0x0020 /*   read-write in priv mode */
 #define SH7750_PTEL_PR_ROPU   0x0040 /*   

[PATCH 0/5] hw/sh4: Codeing style fixes

[BALATON Zoltan]

This fixes coding style of files belonging to SH4 system emulation
which were not following current QEMU coding style requirements.

BALATON Zoltan (5):
  hw/sh4: Coding style: Remove tabs
  hw/sh4: Coding style: Fix multi-line comments
  hw/sh4: Coding style: White space fixes
  hw/sh4: Coding style: Add missing braces
  hw/sh4: Coding style: Remove unnecessary casts

 hw/char/sh_serial.c  |   77 +-
 hw/intc/sh_intc.c|  313 
 hw/pci-host/sh_pci.c |   10 +-
 hw/sh4/r2d.c |   68 +-
 hw/sh4/sh7750.c  |  571 +++---
 hw/sh4/sh7750_regnames.c |  148 ++--
 hw/sh4/sh7750_regs.h | 1600 +++---
 hw/sh4/shix.c|   12 +-
 hw/timer/sh_timer.c  |   55 +-
 include/hw/sh4/sh.h  |   20 +-
 10 files changed, 1466 insertions(+), 1408 deletions(-)

-- 
2.21.4

Re: [PATCH 01/33] tests/tcg: Fix some targets default cross compiler path

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:

We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.

Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by: Philippe Mathieu-Daudé
---
  tests/tcg/configure.sh | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PULL 00/11] Trivial branch for 6.2 patches

[Richard Henderson]

On 10/23/21 11:31 AM, Laurent Vivier wrote:

The following changes since commit 1dafe7656a9c2770065e91208edd4c073f5f98a9:

   Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' 
into staging (2021-10-22 07:47:13 -0700)

are available in the Git repository at:

   git://github.com/vivier/qemu.git tags/trivial-branch-for-6.2-pull-request

for you to fetch changes up to 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa:

   analyze-migration.py: fix extract contents ('-x') errors (2021-10-23 
20:28:56 +0200)


Trivial patches pull request 20211023



Greg Kurz (2):
   softmmu/physmem.c: Fix typo in comment
   README: Fix some documentation URLs

Laurent Vivier (2):
   analyze-migration.py: fix a long standing typo
   analyze-migration.py: fix extract contents ('-x') errors

Oğuz Ersen (1):
   po: update turkish translation

Philippe Mathieu-Daudé (3):
   disas/nios2: Fix style in print_insn_nios2()
   disas/nios2: Simplify endianess conversion
   MAINTAINERS: Add myself as reviewer of 'Machine core' API

Tong Ho (3):
   hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
   hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device
   hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device

  MAINTAINERS   |  1 +
  README.rst| 14 +++---
  disas/nios2.c | 73 ---
  hw/nvram/xlnx-efuse.c |  9 ++--
  hw/nvram/xlnx-versal-efuse-ctrl.c | 20 ++---
  hw/nvram/xlnx-zynqmp-efuse.c  | 18 +---
  include/disas/dis-asm.h   |  3 +-
  po/tr.po  | 25 +--
  scripts/analyze-migration.py  |  6 +--
  softmmu/physmem.c |  2 +-
  target/nios2/cpu.c|  6 +--
  11 files changed, 87 insertions(+), 90 deletions(-)


Applied, thanks.

r~

[PATCH 32/33] target/mips: Remove one MSA unnecessary decodetree overlap group

[Philippe Mathieu-Daudé]

Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.

Diff trivial to review using `git-diff --ignore-all-space`.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode | 398 ++---
 1 file changed, 198 insertions(+), 200 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 8189eae3499..9af995b71b6 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -44,205 +44,203 @@ BNZ_V   010001 0  .   
  @bz_v
 BZ  010001 110 .. . @bz
 BNZ 010001 111 .. . @bz
 
+ANDI00 00  . .  00  @i8
+ORI 00 01  . .  00  @i8
+NORI00 10  . .  00  @i8
+XORI00 11  . .  00  @i8
+BMNZI   00 00  . .  01  @i8
+BMZI00 01  . .  01  @i8
+BSELI   00 10  . .  01  @i8
+SHF 00 ..  . .  10  @i8_df
+
+ADDVI   00 000 .. . . . 000110  @u5
+SUBVI   00 001 .. . . . 000110  @u5
+MAXI_S  00 010 .. . . . 000110  @s5
+MAXI_U  00 011 .. . . . 000110  @u5
+MINI_S  00 100 .. . . . 000110  @s5
+MINI_U  00 101 .. . . . 000110  @u5
+
+CEQI00 000 .. . . . 000111  @s5
+CLTI_S  00 010 .. . . . 000111  @s5
+CLTI_U  00 011 .. . . . 000111  @u5
+CLEI_S  00 100 .. . . . 000111  @s5
+CLEI_U  00 101 .. . . . 000111  @u5
+
+LDI 00 110 .. ..  . 000111  @ldi
+
+SLLI00 000 ... . .  001001  @bit
+SRAI00 001 ... . .  001001  @bit
+SRLI00 010 ... . .  001001  @bit
+BCLRI   00 011 ... . .  001001  @bit
+BSETI   00 100 ... . .  001001  @bit
+BNEGI   00 101 ... . .  001001  @bit
+BINSLI  00 110 ... . .  001001  @bit
+BINSRI  00 111 ... . .  001001  @bit
+
+SAT_S   00 000 ... . .  001010  @bit
+SAT_U   00 001 ... . .  001010  @bit
+SRARI   00 010 ... . .  001010  @bit
+SRLRI   00 011 ... . .  001010  @bit
+
+SLL 00 000.. . . .  001101  @3r
+SRA 00 001.. . . .  001101  @3r
+SRL 00 010.. . . .  001101  @3r
+BCLR00 011.. . . .  001101  @3r
+BSET00 100.. . . .  001101  @3r
+BNEG00 101.. . . .  001101  @3r
+BINSL   00 110.. . . .  001101  @3r
+BINSR   00 111.. . . .  001101  @3r
+
+ADDV00 000.. . . .  001110  @3r
+SUBV00 001.. . . .  001110  @3r
+MAX_S   00 010.. . . .  001110  @3r
+MAX_U   00 011.. . . .  001110  @3r
+MIN_S   00 100.. . . .  001110  @3r
+MIN_U   00 101.. . . .  001110  @3r
+MAX_A   00 110.. . . .  001110  @3r
+MIN_A   00 111.. . . .  001110  @3r
+
+CEQ 00 000.. . . .  00  @3r
+CLT_S   00 010.. . . .  00  @3r
+CLT_U   00 011.. . . .  00  @3r
+CLE_S   00 100.. . . .  00  @3r
+CLE_U   00 101.. . . .  00  @3r
+
+ADD_A   00 000.. . . .  01  @3r
+ADDS_A  00 001.. . . .  01  @3r
+ADDS_S  00 010.. . . .  01  @3r
+ADDS_U  00 011.. . . .  01  @3r
+AVE_S   00 100.. . . .  01  @3r
+AVE_U   00 101.. . . .  01  @3r
+AVER_S  00 110.. . . .  01  @3r
+AVER_U  00 111.. . . .  01  @3r
+
+SUBS_S  00 000.. . . .  010001  @3r
+SUBS_U  00 001.. . . .  010001  @3r
+SUBSUS_U00 010.. 

[PATCH 25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)

[Philippe Mathieu-Daudé]

Convert 3-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  53 ++
 target/mips/tcg/msa_translate.c | 916 ++--
 2 files changed, 106 insertions(+), 863 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1d6fd86ef3d..3d0d9a52675 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,9 +80,54 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  SLL   00 000.. . . .  001101  @3r
+  SRA   00 001.. . . .  001101  @3r
+  SRL   00 010.. . . .  001101  @3r
+  BCLR  00 011.. . . .  001101  @3r
+  BSET  00 100.. . . .  001101  @3r
+  BNEG  00 101.. . . .  001101  @3r
   BINSL 00 110.. . . .  001101  @3r
   BINSR 00 111.. . . .  001101  @3r
 
+  ADDV  00 000.. . . .  001110  @3r
+  SUBV  00 001.. . . .  001110  @3r
+  MAX_S 00 010.. . . .  001110  @3r
+  MAX_U 00 011.. . . .  001110  @3r
+  MIN_S 00 100.. . . .  001110  @3r
+  MIN_U 00 101.. . . .  001110  @3r
+  MAX_A 00 110.. . . .  001110  @3r
+  MIN_A 00 111.. . . .  001110  @3r
+
+  CEQ   00 000.. . . .  00  @3r
+  CLT_S 00 010.. . . .  00  @3r
+  CLT_U 00 011.. . . .  00  @3r
+  CLE_S 00 100.. . . .  00  @3r
+  CLE_U 00 101.. . . .  00  @3r
+
+  ADD_A 00 000.. . . .  01  @3r
+  ADDS_A00 001.. . . .  01  @3r
+  ADDS_S00 010.. . . .  01  @3r
+  ADDS_U00 011.. . . .  01  @3r
+  AVE_S 00 100.. . . .  01  @3r
+  AVE_U 00 101.. . . .  01  @3r
+  AVER_S00 110.. . . .  01  @3r
+  AVER_U00 111.. . . .  01  @3r
+
+  SUBS_S00 000.. . . .  010001  @3r
+  SUBS_U00 001.. . . .  010001  @3r
+  SUBSUS_U  00 010.. . . .  010001  @3r
+  SUBSUU_S  00 011.. . . .  010001  @3r
+  ASUB_S00 100.. . . .  010001  @3r
+  ASUB_U00 101.. . . .  010001  @3r
+
+  MULV  00 000.. . . .  010010  @3r
+  MADDV 00 001.. . . .  010010  @3r
+  MSUBV 00 010.. . . .  010010  @3r
+  DIV_S 00 100.. . . .  010010  @3r
+  DIV_U 00 101.. . . .  010010  @3r
+  MOD_S 00 110.. . . .  010010  @3r
+  MOD_U 00 111.. . . .  010010  @3r
+
   DOTP_S00 000.. . . .  010011  @3r
   DOTP_U00 001.. . . .  010011  @3r
   DPADD_S   00 010.. . . .  010011  @3r
@@ -92,8 +137,16 @@ BNZ 010001 111 .. . 
@bz
 
   SLD   00 000 .. . . . 010100  @3r
   SPLAT 00 001 .. . . . 010100  @3r
+  PCKEV 00 010 .. . . . 010100  @3r
+  PCKOD 00 011 .. . . . 010100  @3r
+  ILVL  00 100 .. . . . 010100  @3r
+  ILVR  00 101 .. . . . 010100  @3r
+  ILVEV 00 110 .. . . . 010100  @3r
+  ILVOD 00 111 .. . . . 010100  @3r
 
   VSHF  00 000 .. . . . 010101  @3r
+  SRAR  00 001 .. . . . 010101  @3r
+  SRLR  00 010 .. . . . 010101  @3r
   HADD_S00 100.. . . .  010101  @3r
   HADD_U00 101.. . . .  010101  @3r
   HSUB_S00 110.. . . .  010101  @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1b69ec149a5..7813c126069 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,69 +24,10 @@
 
 #define MASK_MSA_MINOR(op)  (MASK_OP_MAJOR(op) | (op & 0x3F))
 enum {
-OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
-OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
-OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
-  

[PATCH 33/33] target/mips: Adjust style in msa_translate_init()

[Philippe Mathieu-Daudé]

While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5d8cad378e6..d196cad196b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -80,13 +80,15 @@ void msa_translate_init(void)
 int i;
 
 for (i = 0; i < 32; i++) {
-int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+int off;
 
 /*
  * The MSA vector registers are mapped on the
  * scalar floating-point unit (FPU) registers.
  */
+off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
 msa_wr_d[i * 2] = fpu_f64[i];
+
 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
 msa_wr_d[i * 2 + 1] =
 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
-- 
2.31.1

[PATCH 29/33] target/mips: Convert MSA MOVE.V opcode to decodetree

[Philippe Mathieu-Daudé]

Convert the MOVE.V opcode (Vector Move) to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  6 +-
 target/mips/tcg/msa_translate.c | 26 +-
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index dc5e561b9dc..1bde1983de3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
 @elm_df ..  df:6  ws:5 wd:5 ..  _elm
+@elm.. .. ws:5 wd:5 ..  _elm df=0
 @vec.. . wt:5 ws:5 wd:5 ..  _r df=0
 @2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
@@ -156,7 +157,10 @@ BNZ 010001 111 .. .    
 @bz
 
   SLDI  00  .. . .  011001  @elm_df
   SPLATI00 0001 .. . .  011001  @elm_df
-  COPY_S00 0010 .. . .  011001  @elm_df
+  {
+MOVE_V  00 001010  . .  011001  @elm
+COPY_S  00 0010 .. . .  011001  @elm_df
+  }
   COPY_U00 0011 .. . .  011001  @elm_df
   INSERT00 0100 .. . .  011001  @elm_df
   INSVE 00 0101 .. . .  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ff5dbd99f84..b03cde964e0 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,7 +31,6 @@ enum {
 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
 OPC_CTCMSA  = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 OPC_CFCMSA  = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_MOVE_V  = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -533,6 +532,26 @@ TRANS_DF_B(HADD_U,  trans_msa_3r,
gen_helper_msa_hadd_u);
 TRANS_DF_B(HSUB_S,  trans_msa_3r,gen_helper_msa_hsub_s);
 TRANS_DF_B(HSUB_U,  trans_msa_3r,gen_helper_msa_hsub_u);
 
+static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
+{
+TCGv_i32 tsr;
+TCGv_i32 tdt;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+tsr = tcg_const_i32(a->ws);
+tdt = tcg_const_i32(a->wd);
+
+gen_helper_msa_move_v(cpu_env, tdt, tsr);
+
+tcg_temp_free_i32(tdt);
+tcg_temp_free_i32(tsr);
+
+return true;
+}
+
 static void gen_msa_elm_3e(DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -551,9 +570,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
 gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
 gen_store_gpr(telm, dest);
 break;
-case OPC_MOVE_V:
-gen_helper_msa_move_v(cpu_env, tdt, tsr);
-break;
 default:
 MIPS_INVAL("MSA instruction");
 gen_reserved_instruction(ctx);
@@ -665,7 +681,7 @@ static void gen_msa_elm(DisasContext *ctx)
 uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
 
 if (dfn == 0x3E) {
-/* CTCMSA, CFCMSA, MOVE.V */
+/* CTCMSA, CFCMSA */
 gen_msa_elm_3e(ctx);
 return;
 }
-- 
2.31.1

[PATCH 21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)

[Philippe Mathieu-Daudé]

Convert 3-register floating-point or fixed-point operations
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  37 ++
 target/mips/tcg/msa_translate.c | 213 ++--
 2 files changed, 74 insertions(+), 176 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5c6a7415271..28b7a71d930 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -79,9 +79,46 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  FCAF  00  . . . . 011010  @3rf
+  FCUN  00 0001 . . . . 011010  @3rf
+  FCEQ  00 0010 . . . . 011010  @3rf
+  FCUEQ 00 0011 . . . . 011010  @3rf
+  FCLT  00 0100 . . . . 011010  @3rf
+  FCULT 00 0101 . . . . 011010  @3rf
+  FCLE  00 0110 . . . . 011010  @3rf
+  FCULE 00 0111 . . . . 011010  @3rf
+  FSAF  00 1000 . . . . 011010  @3rf
+  FSUN  00 1001 . . . . 011010  @3rf
+  FSEQ  00 1010 . . . . 011010  @3rf
+  FSUEQ 00 1011 . . . . 011010  @3rf
+  FSLT  00 1100 . . . . 011010  @3rf
+  FSULT 00 1101 . . . . 011010  @3rf
+  FSLE  00 1110 . . . . 011010  @3rf
+  FSULE 00  . . . . 011010  @3rf
+
+  FADD  00  . . . . 011011  @3rf
+  FSUB  00 0001 . . . . 011011  @3rf
+  FMUL  00 0010 . . . . 011011  @3rf
+  FDIV  00 0011 . . . . 011011  @3rf
+  FMADD 00 0100 . . . . 011011  @3rf
+  FMSUB 00 0101 . . . . 011011  @3rf
+  FEXP2 00 0111 . . . . 011011  @3rf
+  FEXDO 00 1000 . . . . 011011  @3rf
+  FTQ   00 1010 . . . . 011011  @3rf
+  FMIN  00 1100 . . . . 011011  @3rf
+  FMIN_A00 1101 . . . . 011011  @3rf
+  FMAX  00 1110 . . . . 011011  @3rf
+  FMAX_A00  . . . . 011011  @3rf
+
+  FCOR  00 0001 . . . . 011100  @3rf
+  FCUNE 00 0010 . . . . 011100  @3rf
+  FCNE  00 0011 . . . . 011100  @3rf
   MUL_Q 00 0100 . . . . 011100  @3rf
   MADD_Q00 0101 . . . . 011100  @3rf
   MSUB_Q00 0110 . . . . 011100  @3rf
+  FSOR  00 1001 . . . . 011100  @3rf
+  FSUNE 00 1010 . . . . 011100  @3rf
+  FSNE  00 1011 . . . . 011100  @3rf
   MULR_Q00 1100 . . . . 011100  @3rf
   MADDR_Q   00 1101 . . . . 011100  @3rf
   MSUBR_Q   00 1110 . . . . 011100  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 6e50bc9edf4..4543b7abdfb 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -34,9 +34,6 @@ enum {
 OPC_MSA_3R_14   = 0x14 | OPC_MSA,
 OPC_MSA_3R_15   = 0x15 | OPC_MSA,
 OPC_MSA_ELM = 0x19 | OPC_MSA,
-OPC_MSA_3RF_1A  = 0x1A | OPC_MSA,
-OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
-OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
 };
 
 enum {
@@ -115,43 +112,6 @@ enum {
 OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_INSVE_df= (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-
-/* 3RF instruction _df(bit 21) = _w, _d */
-OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
-OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
-OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
-OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
-OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
-OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
-OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
-OPC_FCUNE_df= (0x2 << 22) | OPC_MSA_3RF_1C,
-OPC_FCUEQ_df= (0x3 << 22) | OPC_MSA_3RF_1A,
-OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
-OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
-OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
-OPC_FMADD_df= (0x4 << 22) | OPC_MSA_3RF_1B,
-OPC_FCULT_df= (0x5 << 22) | OPC_MSA_3RF_1A,
-OPC_FMSUB_df= (0x5 << 22) | OPC_MSA_3RF_1B,
-OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
-OPC_FCULE_df   

[PATCH 30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree

[Philippe Mathieu-Daudé]

Convert the CFCMSA (Copy From Control MSA register) and
CTCMSA (Copy To Control MSA register) opcodes to decodetree.

Since they respectively overlap with the SLDI and SPLATI
opcodes, use decodetree overlap groups.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  | 10 +++-
 target/mips/tcg/msa_translate.c | 95 -
 2 files changed, 42 insertions(+), 63 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1bde1983de3..52dac0fde6d 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -155,8 +155,14 @@ BNZ 010001 111 .. .    
 @bz
   HSUB_S00 110.. . . .  010101  @3r
   HSUB_U00 111.. . . .  010101  @3r
 
-  SLDI  00  .. . .  011001  @elm_df
-  SPLATI00 0001 .. . .  011001  @elm_df
+  {
+CTCMSA  00 10  . .  011001  @elm
+SLDI00  .. . .  011001  @elm_df
+  }
+  {
+CFCMSA  00 000110  . .  011001  @elm
+SPLATI  00 0001 .. . .  011001  @elm_df
+  }
   {
 MOVE_V  00 001010  . .  011001  @elm
 COPY_S  00 0010 .. . .  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b03cde964e0..51af6f39cc4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -20,19 +20,6 @@
 /* Include the auto-generated decoder.  */
 #include "decode-msa.c.inc"
 
-#define OPC_MSA (0x1E << 26)
-
-#define MASK_MSA_MINOR(op)  (MASK_OP_MAJOR(op) | (op & 0x3F))
-enum {
-OPC_MSA_ELM = 0x19 | OPC_MSA,
-};
-
-enum {
-/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
-OPC_CTCMSA  = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_CFCMSA  = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-};
-
 static const char msaregnames[][6] = {
 "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
 "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
@@ -552,33 +539,46 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm 
*a)
 return true;
 }
 
-static void gen_msa_elm_3e(DisasContext *ctx)
+static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
 {
-#define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
-uint8_t source = (ctx->opcode >> 11) & 0x1f;
-uint8_t dest = (ctx->opcode >> 6) & 0x1f;
-TCGv telm = tcg_temp_new();
-TCGv_i32 tsr = tcg_const_i32(source);
-TCGv_i32 tdt = tcg_const_i32(dest);
+TCGv telm;
+TCGv_i32 tdt;
 
-switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
-case OPC_CTCMSA:
-gen_load_gpr(telm, source);
-gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
-break;
-case OPC_CFCMSA:
-gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
-gen_store_gpr(telm, dest);
-break;
-default:
-MIPS_INVAL("MSA instruction");
-gen_reserved_instruction(ctx);
-break;
+if (!check_msa_access(ctx)) {
+return false;
 }
 
+telm = tcg_temp_new();
+tdt = tcg_const_i32(a->wd);
+
+gen_load_gpr(telm, a->ws);
+gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
+
 tcg_temp_free(telm);
 tcg_temp_free_i32(tdt);
+
+return true;
+}
+
+static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
+{
+TCGv telm;
+TCGv_i32 tsr;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+telm = tcg_temp_new();
+tsr = tcg_const_i32(a->ws);
+
+gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
+gen_store_gpr(telm, a->wd);
+
+tcg_temp_free(telm);
 tcg_temp_free_i32(tsr);
+
+return true;
 }
 
 static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
@@ -676,19 +676,6 @@ TRANS_DF_D64(COPY_S,trans_msa_elm_d64, 
gen_helper_msa_copy_s);
 TRANS_DF_W64(COPY_U,trans_msa_elm_d64, gen_helper_msa_copy_u);
 TRANS_DF_D64(INSERT,trans_msa_elm_d64, gen_helper_msa_insert);
 
-static void gen_msa_elm(DisasContext *ctx)
-{
-uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-
-if (dfn == 0x3E) {
-/* CTCMSA, CFCMSA */
-gen_msa_elm_3e(ctx);
-return;
-}
-
-gen_reserved_instruction(ctx);
-}
-
 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
   enum CPUMIPSMSADataFormat df_base,
   void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
@@ -880,21 +867,7 @@ TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
 static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
-uint32_t opcode = ctx->opcode;
-
-if (!check_msa_access(ctx)) {
-return false;
-}
-
-switch (MASK_MSA_MINOR(opcode)) {
-case OPC_MSA_ELM:
-gen_msa_elm(ctx);
-break;
-default:
-MIPS_INVAL("MSA instruction");
-gen_reserved_instruction(ctx);
-

[PATCH 28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree

[Philippe Mathieu-Daudé]

Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  2 +
 target/mips/tcg/msa_translate.c | 92 -
 2 files changed, 12 insertions(+), 82 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 80a06d12746..dc5e561b9dc 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -156,7 +156,9 @@ BNZ 010001 111 .. . 
@bz
 
   SLDI  00  .. . .  011001  @elm_df
   SPLATI00 0001 .. . .  011001  @elm_df
+  COPY_S00 0010 .. . .  011001  @elm_df
   COPY_U00 0011 .. . .  011001  @elm_df
+  INSERT00 0100 .. . .  011001  @elm_df
   INSVE 00 0101 .. . .  011001  @elm_df
 
   FCAF  00  . . . . 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e033b365fdd..ff5dbd99f84 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,9 +31,7 @@ enum {
 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
 OPC_CTCMSA  = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 OPC_CFCMSA  = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_MOVE_V  = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -138,6 +136,11 @@ static inline bool check_msa_access(DisasContext *ctx)
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
 NULL, gen_func##_h, gen_func##_w, gen_func##_d)
 
+#define TRANS_DF_D64(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+DF_WORD, DF_DOUBLE, \
+gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
 #define TRANS_DF_W64(NAME, trans_func, gen_func) \
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
 DF_HALF, DF_WORD, \
@@ -642,7 +645,8 @@ static bool trans_msa_elm_d64(DisasContext *ctx, 
arg_msa_elm *a,
 gen_msa_elm_w(cpu_env, twd, tws, tn);
 break;
 case DF_DOUBLE:
-g_assert_not_reached();
+assert(gen_msa_elm_d != NULL);
+gen_msa_elm_d(cpu_env, twd, tws, tn);
 break;
 }
 
@@ -652,97 +656,21 @@ static bool trans_msa_elm_d64(DisasContext *ctx, 
arg_msa_elm *a,
 return true;
 }
 
+TRANS_DF_D64(COPY_S,trans_msa_elm_d64, gen_helper_msa_copy_s);
 TRANS_DF_W64(COPY_U,trans_msa_elm_d64, gen_helper_msa_copy_u);
-
-static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
-{
-#define MASK_MSA_ELM(op)(MASK_MSA_MINOR(op) | (op & (0xf << 22)))
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
-TCGv_i32 tws = tcg_const_i32(ws);
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv_i32 tn  = tcg_const_i32(n);
-
-switch (MASK_MSA_ELM(ctx->opcode)) {
-case OPC_COPY_S_df:
-case OPC_INSERT_df:
-#if !defined(TARGET_MIPS64)
-/* Double format valid only for MIPS64 */
-if (df == DF_DOUBLE) {
-gen_reserved_instruction(ctx);
-break;
-}
-#endif
-switch (MASK_MSA_ELM(ctx->opcode)) {
-case OPC_COPY_S_df:
-if (likely(wd != 0)) {
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
-break;
-case DF_HALF:
-gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
-break;
-case DF_WORD:
-gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
-break;
-#if defined(TARGET_MIPS64)
-case DF_DOUBLE:
-gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
-break;
-#endif
-default:
-assert(0);
-}
-}
-break;
-case OPC_INSERT_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
-break;
-case DF_HALF:
-gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
-break;
-case DF_WORD:
-gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
-break;
-#if defined(TARGET_MIPS64)
-case DF_DOUBLE:
-gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
-break;
-#endif
-default:
-assert(0);
-}
-break;
-}
-break;

[PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree

[Philippe Mathieu-Daudé]

Convert the FILL opcode (Vector Fill from GPR) to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  2 ++
 target/mips/tcg/msa_translate.c | 40 +++--
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 2997bfa24e3..e97490cf880 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
 @ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
@@ -76,6 +77,7 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  FILL  00 1100 .. . .  00  @2r
   FCLASS00 11001 . . .  00  @2rf
   FTRUNC_S  00 110010001 . . .  00  @2rf
   FTRUNC_U  00 110010010 . . .  00  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c6a77381c0e..fc0b80f83ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -53,7 +53,6 @@ enum {
 OPC_MSA_2R  = (0x18 << 21) | OPC_MSA_VEC,
 
 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
-OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
 OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
 OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
 OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
@@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx)
 TCGv_i32 tws = tcg_const_i32(ws);
 
 switch (MASK_MSA_2R(ctx->opcode)) {
-case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
-/* Double format valid only for MIPS64 */
-if (df == DF_DOUBLE) {
-gen_reserved_instruction(ctx);
-break;
-}
-#endif
-gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
-   twd, tws); /* trs */
-break;
 case OPC_NLOC_df:
 switch (df) {
 case DF_BYTE:
@@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx)
 tcg_temp_free_i32(tws);
 }
 
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
+{
+TCGv_i32 twd;
+TCGv_i32 tws;
+TCGv_i32 tdf;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+/* Double format valid only for MIPS64 */
+gen_reserved_instruction(ctx);
+return true;
+}
+
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+tdf = tcg_constant_i32(a->df);
+
+gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
+
+tcg_temp_free_i32(twd);
+tcg_temp_free_i32(tws);
+
+return true;
+}
+
 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
   void (*gen_msa_2rf)(TCGv_ptr, TCGv_i32,
   TCGv_i32, TCGv_i32))
-- 
2.31.1

[PATCH 24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)

[Philippe Mathieu-Daudé]

Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  3 +++
 target/mips/tcg/msa_translate.c | 37 +++--
 2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 4a9cf85fa7a..1d6fd86ef3d 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,6 +80,9 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  BINSL 00 110.. . . .  001101  @3r
+  BINSR 00 111.. . . .  001101  @3r
+
   DOTP_S00 000.. . . .  010011  @3r
   DOTP_U00 001.. . . .  010011  @3r
   DPADD_S   00 010.. . . .  010011  @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e1da532e5c9..1b69ec149a5 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -78,12 +78,10 @@ enum {
 OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
 OPC_DIV_U_df= (0x5 << 23) | OPC_MSA_3R_12,
 OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
-OPC_BINSL_df= (0x6 << 23) | OPC_MSA_3R_0D,
 OPC_MAX_A_df= (0x6 << 23) | OPC_MSA_3R_0E,
 OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
 OPC_MOD_S_df= (0x6 << 23) | OPC_MSA_3R_12,
 OPC_ILVEV_df= (0x6 << 23) | OPC_MSA_3R_14,
-OPC_BINSR_df= (0x7 << 23) | OPC_MSA_3R_0D,
 OPC_MIN_A_df= (0x7 << 23) | OPC_MSA_3R_0E,
 OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
 OPC_MOD_U_df= (0x7 << 23) | OPC_MSA_3R_12,
@@ -518,6 +516,9 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
 return true;
 }
 
+TRANS_DF_E(BINSL,   trans_msa_3r,gen_helper_msa_binsl);
+TRANS_DF_E(BINSR,   trans_msa_3r,gen_helper_msa_binsr);
+
 TRANS_DF_B(DOTP_S,  trans_msa_3r,gen_helper_msa_dotp_s);
 TRANS_DF_B(DOTP_U,  trans_msa_3r,gen_helper_msa_dotp_u);
 TRANS_DF_B(DPADD_S, trans_msa_3r,gen_helper_msa_dpadd_s);
@@ -548,38 +549,6 @@ static void gen_msa_3r(DisasContext *ctx)
 TCGv_i32 twt = tcg_const_i32(wt);
 
 switch (MASK_MSA_3R(ctx->opcode)) {
-case OPC_BINSL_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
-break;
-case DF_HALF:
-gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
-break;
-case DF_WORD:
-gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
-break;
-case DF_DOUBLE:
-gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
-break;
-}
-break;
-case OPC_BINSR_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
-break;
-case DF_HALF:
-gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
-break;
-case DF_WORD:
-gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
-break;
-case DF_DOUBLE:
-gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
-break;
-}
-break;
 case OPC_BCLR_df:
 switch (df) {
 case DF_BYTE:
-- 
2.31.1

[PATCH 27/33] target/mips: Convert MSA COPY_U opcode to decodetree

[Philippe Mathieu-Daudé]

Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.

Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  1 +
 target/mips/tcg/msa_translate.c | 90 +++--
 2 files changed, 65 insertions(+), 26 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 0f1674cd318..80a06d12746 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -156,6 +156,7 @@ BNZ 010001 111 .. . 
@bz
 
   SLDI  00  .. . .  011001  @elm_df
   SPLATI00 0001 .. . .  011001  @elm_df
+  COPY_U00 0011 .. . .  011001  @elm_df
   INSVE 00 0101 .. . .  011001  @elm_df
 
   FCAF  00  . . . . 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 95dcd4b5b06..e033b365fdd 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -33,7 +33,6 @@ enum {
 OPC_CFCMSA  = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_MOVE_V  = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
@@ -139,6 +138,11 @@ static inline bool check_msa_access(DisasContext *ctx)
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
 NULL, gen_func##_h, gen_func##_w, gen_func##_d)
 
+#define TRANS_DF_W64(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+DF_HALF, DF_WORD, \
+gen_func##_b, gen_func##_h, gen_func##_w, NULL)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
 {
@@ -591,6 +595,65 @@ TRANS_MSA(SLDI, trans_msa_elm_df, 
gen_helper_msa_sldi_df);
 TRANS_MSA(SPLATI,   trans_msa_elm_df, gen_helper_msa_splati_df);
 TRANS_MSA(INSVE,trans_msa_elm_df, gen_helper_msa_insve_df);
 
+static bool trans_msa_elm_d64(DisasContext *ctx, arg_msa_elm *a,
+  enum CPUMIPSMSADataFormat df_max32,
+  enum CPUMIPSMSADataFormat df_max64,
+  void (*gen_msa_elm_b)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32),
+  void (*gen_msa_elm_h)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32),
+  void (*gen_msa_elm_w)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32),
+  void (*gen_msa_elm_d)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32))
+{
+TCGv_i32 twd;
+TCGv_i32 tws;
+TCGv_i32 tn;
+uint32_t df, n;
+
+if (!df_extract(df_elm, a->df, , )) {
+gen_reserved_instruction(ctx);
+return true;
+}
+
+if (df > (TARGET_LONG_BITS == 64 ? df_max64 : df_max32)) {
+gen_reserved_instruction(ctx);
+return true;
+}
+
+if (a->wd == 0) {
+/* Treat as NOP. */
+return true;
+}
+
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+tn = tcg_constant_i32(n);
+
+switch (a->df) {
+case DF_BYTE:
+gen_msa_elm_b(cpu_env, twd, tws, tn);
+break;
+case DF_HALF:
+gen_msa_elm_h(cpu_env, twd, tws, tn);
+break;
+case DF_WORD:
+gen_msa_elm_w(cpu_env, twd, tws, tn);
+break;
+case DF_DOUBLE:
+g_assert_not_reached();
+break;
+}
+
+tcg_temp_free_i32(tws);
+tcg_temp_free_i32(twd);
+
+return true;
+}
+
+TRANS_DF_W64(COPY_U,trans_msa_elm_d64, gen_helper_msa_copy_u);
+
 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 {
 #define MASK_MSA_ELM(op)(MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -603,7 +666,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, 
uint32_t n)
 
 switch (MASK_MSA_ELM(ctx->opcode)) {
 case OPC_COPY_S_df:
-case OPC_COPY_U_df:
 case OPC_INSERT_df:
 #if !defined(TARGET_MIPS64)
 /* Double format valid only for MIPS64 */
@@ -611,11 +673,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, 
uint32_t n)
 gen_reserved_instruction(ctx);
 break;
 }
-if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
-  (df == DF_WORD)) {
-gen_reserved_instruction(ctx);
-break;
-}
 #endif
 switch (MASK_MSA_ELM(ctx->opcode)) {
 case OPC_COPY_S_df:
@@ -634,25 +691,6 @@ static 

[PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert load/store instructions to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  4 ++
 target/mips/tcg/msa_translate.c | 99 +
 2 files changed, 44 insertions(+), 59 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3dd07dced57..5fe6923ace5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -17,6 +17,7 @@
 _ldst   df wd wssa
 
 @lsa.. rs:5 rt:5 rd:5 ... sa:2 ..   
+@ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
@@ -73,5 +74,8 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  LD00 .. . .   1000 .. @ldst
+  ST00 .. . .   1001 .. @ldst
+
   MSA   00 --
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 2866687635d..52af99636a4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -38,16 +38,6 @@ enum {
 OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
 OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
 OPC_MSA_VEC = 0x1E | OPC_MSA,
-
-/* MI10 instruction */
-OPC_LD_B= (0x20) | OPC_MSA,
-OPC_LD_H= (0x21) | OPC_MSA,
-OPC_LD_W= (0x22) | OPC_MSA,
-OPC_LD_D= (0x23) | OPC_MSA,
-OPC_ST_B= (0x24) | OPC_MSA,
-OPC_ST_H= (0x25) | OPC_MSA,
-OPC_ST_W= (0x26) | OPC_MSA,
-OPC_ST_D= (0x27) | OPC_MSA,
 };
 
 enum {
@@ -298,6 +288,10 @@ static inline bool check_msa_access(DisasContext *ctx)
 #define TRANS_MSA(NAME, trans_func, gen_func) \
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
 
+#define TRANS_DF_E(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
 {
@@ -2104,55 +2098,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 case OPC_MSA_VEC:
 gen_msa_vec(ctx);
 break;
-case OPC_LD_B:
-case OPC_LD_H:
-case OPC_LD_W:
-case OPC_LD_D:
-case OPC_ST_B:
-case OPC_ST_H:
-case OPC_ST_W:
-case OPC_ST_D:
-{
-int32_t s10 = sextract32(ctx->opcode, 16, 10);
-uint8_t rs = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-uint8_t df = (ctx->opcode >> 0) & 0x3;
-
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv taddr = tcg_temp_new();
-gen_base_offset_addr(ctx, taddr, rs, s10 << df);
-
-switch (MASK_MSA_MINOR(opcode)) {
-case OPC_LD_B:
-gen_helper_msa_ld_b(cpu_env, twd, taddr);
-break;
-case OPC_LD_H:
-gen_helper_msa_ld_h(cpu_env, twd, taddr);
-break;
-case OPC_LD_W:
-gen_helper_msa_ld_w(cpu_env, twd, taddr);
-break;
-case OPC_LD_D:
-gen_helper_msa_ld_d(cpu_env, twd, taddr);
-break;
-case OPC_ST_B:
-gen_helper_msa_st_b(cpu_env, twd, taddr);
-break;
-case OPC_ST_H:
-gen_helper_msa_st_h(cpu_env, twd, taddr);
-break;
-case OPC_ST_W:
-gen_helper_msa_st_w(cpu_env, twd, taddr);
-break;
-case OPC_ST_D:
-gen_helper_msa_st_d(cpu_env, twd, taddr);
-break;
-}
-
-tcg_temp_free_i32(twd);
-tcg_temp_free(taddr);
-}
-break;
 default:
 MIPS_INVAL("MSA instruction");
 gen_reserved_instruction(ctx);
@@ -2162,6 +2107,42 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 return true;
 }
 
+static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
+   void (*gen_msa_b)(TCGv_ptr, TCGv_i32, TCGv),
+   void (*gen_msa_h)(TCGv_ptr, TCGv_i32, TCGv),
+   void (*gen_msa_w)(TCGv_ptr, TCGv_i32, TCGv),
+   void (*gen_msa_d)(TCGv_ptr, TCGv_i32, TCGv))
+{
+
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv taddr = tcg_temp_new();
+
+gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
+
+switch (a->df) {
+case DF_BYTE:
+gen_msa_b(cpu_env, twd, taddr);
+break;
+case 

[PATCH 26/33] target/mips: Convert MSA ELM instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert instructions with an immediate element index
and data format df/n to decodetree.

Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  6 +
 target/mips/tcg/msa_translate.c | 46 +++--
 2 files changed, 39 insertions(+), 13 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 3d0d9a52675..0f1674cd318 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -15,12 +15,14 @@
 
 _r  df wd ws wt
 _bz df   wt sa
+_elmdf wd ws
 _ldst   df wd wssa
 
 @lsa.. rs:5 rt:5 rd:5 ... sa:2 ..   
 @ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@elm_df ..  df:6  ws:5 wd:5 ..  _elm
 @vec.. . wt:5 ws:5 wd:5 ..  _r df=0
 @2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
@@ -152,6 +154,10 @@ BNZ 010001 111 .. .    
 @bz
   HSUB_S00 110.. . . .  010101  @3r
   HSUB_U00 111.. . . .  010101  @3r
 
+  SLDI  00  .. . .  011001  @elm_df
+  SPLATI00 0001 .. . .  011001  @elm_df
+  INSVE 00 0101 .. . .  011001  @elm_df
+
   FCAF  00  . . . . 011010  @3rf
   FCUN  00 0001 . . . . 011010  @3rf
   FCEQ  00 0010 . . . . 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7813c126069..95dcd4b5b06 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -29,15 +29,12 @@ enum {
 
 enum {
 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
-OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_CTCMSA  = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-OPC_SPLATI_df   = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_CFCMSA  = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 OPC_COPY_S_df   = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_MOVE_V  = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 OPC_COPY_U_df   = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 OPC_INSERT_df   = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
-OPC_INSVE_df= (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -561,6 +558,39 @@ static void gen_msa_elm_3e(DisasContext *ctx)
 tcg_temp_free_i32(tsr);
 }
 
+static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
+ void (*gen_msa_elm_df)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32,
+TCGv_i32))
+{
+TCGv_i32 twd;
+TCGv_i32 tws;
+TCGv_i32 tdf;
+TCGv_i32 tn;
+uint32_t df, n;
+
+if (!df_extract(df_elm, a->df, , )) {
+gen_reserved_instruction(ctx);
+return true;
+}
+
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+tdf = tcg_constant_i32(df);
+tn = tcg_constant_i32(n);
+
+gen_msa_elm_df(cpu_env, tdf, twd, tws, tn);
+
+tcg_temp_free_i32(tws);
+tcg_temp_free_i32(twd);
+
+return true;
+}
+
+TRANS_MSA(SLDI, trans_msa_elm_df, gen_helper_msa_sldi_df);
+TRANS_MSA(SPLATI,   trans_msa_elm_df, gen_helper_msa_splati_df);
+TRANS_MSA(INSVE,trans_msa_elm_df, gen_helper_msa_insve_df);
+
 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
 {
 #define MASK_MSA_ELM(op)(MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -570,18 +600,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, 
uint32_t n)
 TCGv_i32 tws = tcg_const_i32(ws);
 TCGv_i32 twd = tcg_const_i32(wd);
 TCGv_i32 tn  = tcg_const_i32(n);
-TCGv_i32 tdf = tcg_constant_i32(df);
 
 switch (MASK_MSA_ELM(ctx->opcode)) {
-case OPC_SLDI_df:
-gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
-break;
-case OPC_SPLATI_df:
-gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
-break;
-case OPC_INSVE_df:
-gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
-break;
 case OPC_COPY_S_df:
 case OPC_COPY_U_df:
 case OPC_INSERT_df:
-- 
2.31.1

[PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)

[Philippe Mathieu-Daudé]

Convert 3-register floating-point or fixed-point operations
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  8 
 target/mips/tcg/msa_translate.c | 70 +++--
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 72447041fef..5c6a7415271 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -24,6 +24,7 @@
 @vec.. . wt:5 ws:5 wd:5 ..  _r df=0
 @2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
+@3rf..  df:1 wt:5 ws:5 wd:5 ..  _r
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
@@ -78,6 +79,13 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  MUL_Q 00 0100 . . . . 011100  @3rf
+  MADD_Q00 0101 . . . . 011100  @3rf
+  MSUB_Q00 0110 . . . . 011100  @3rf
+  MULR_Q00 1100 . . . . 011100  @3rf
+  MADDR_Q   00 1101 . . . . 011100  @3rf
+  MSUBR_Q   00 1110 . . . . 011100  @3rf
+
   AND_V 00 0 . . .  00  @vec
   OR_V  00 1 . . .  00  @vec
   NOR_V 00 00010 . . .  00  @vec
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 461a427c9df..6e50bc9edf4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -130,12 +130,9 @@ enum {
 OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
 OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
 OPC_FMADD_df= (0x4 << 22) | OPC_MSA_3RF_1B,
-OPC_MUL_Q_df= (0x4 << 22) | OPC_MSA_3RF_1C,
 OPC_FCULT_df= (0x5 << 22) | OPC_MSA_3RF_1A,
 OPC_FMSUB_df= (0x5 << 22) | OPC_MSA_3RF_1B,
-OPC_MADD_Q_df   = (0x5 << 22) | OPC_MSA_3RF_1C,
 OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
-OPC_MSUB_Q_df   = (0x6 << 22) | OPC_MSA_3RF_1C,
 OPC_FCULE_df= (0x7 << 22) | OPC_MSA_3RF_1A,
 OPC_FEXP2_df= (0x7 << 22) | OPC_MSA_3RF_1B,
 OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
@@ -149,13 +146,10 @@ enum {
 OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
 OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
 OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
-OPC_MULR_Q_df   = (0xC << 22) | OPC_MSA_3RF_1C,
 OPC_FSULT_df= (0xD << 22) | OPC_MSA_3RF_1A,
 OPC_FMIN_A_df   = (0xD << 22) | OPC_MSA_3RF_1B,
-OPC_MADDR_Q_df  = (0xD << 22) | OPC_MSA_3RF_1C,
 OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
 OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
-OPC_MSUBR_Q_df  = (0xE << 22) | OPC_MSA_3RF_1C,
 OPC_FSULE_df= (0xF << 22) | OPC_MSA_3RF_1A,
 OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
 };
@@ -251,6 +245,9 @@ static inline bool check_msa_access(DisasContext *ctx)
 #define TRANS_MSA(NAME, trans_func, gen_func) \
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
 
+#define TRANS_DF(NAME, trans_func, df, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, df, gen_func)
+
 #define TRANS_DF_E(NAME, trans_func, gen_func) \
 TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
@@ -1652,6 +1649,33 @@ static void gen_msa_elm(DisasContext *ctx)
 gen_msa_elm_df(ctx, df, n);
 }
 
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+  enum CPUMIPSMSADataFormat df_base,
+  void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
+  TCGv_i32, TCGv_i32))
+{
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);
+/* adjust df value for floating-point instruction */
+TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
+
+gen_msa_3rf(cpu_env, tdf, twd, tws, twt);
+
+tcg_temp_free_i32(twt);
+tcg_temp_free_i32(tws);
+tcg_temp_free_i32(twd);
+
+return true;
+}
+
+TRANS_DF(MUL_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
+TRANS_DF(MADD_Q,trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
+TRANS_DF(MSUB_Q,trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS_DF(MULR_Q,trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
+TRANS_DF(MADDR_Q,   trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
+TRANS_DF(MSUBR_Q,   trans_msa_3rf, DF_HALF, 

[PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  8 
 target/mips/tcg/msa_translate.c | 72 +
 2 files changed, 26 insertions(+), 54 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 6347468a709..3dd07dced57 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
 @i8_df  .. df:2 sa:s8 ws:5 wd:5 ..  _ldst
+@i8 .. ..   sa:s8 ws:5 wd:5 ..  _ldst df=0
 @bit.. ... df:7   ws:5 wd:5 ..  _ldst sa=0
 
 LSA 00 . . . 000 .. 000101  @lsa
@@ -34,6 +35,13 @@ BZ  010001 110 .. . 
@bz
 BNZ 010001 111 .. . @bz
 
 {
+  ANDI  00 00  . .  00  @i8
+  ORI   00 01  . .  00  @i8
+  NORI  00 10  . .  00  @i8
+  XORI  00 11  . .  00  @i8
+  BMNZI 00 00  . .  01  @i8
+  BMZI  00 01  . .  01  @i8
+  BSELI 00 10  . .  01  @i8
   SHF   00 ..  . .  10  @i8_df
 
   ADDVI 00 000 .. . . . 000110  @u5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7cb078bfe92..2866687635d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,9 +24,6 @@
 
 #define MASK_MSA_MINOR(op)  (MASK_OP_MAJOR(op) | (op & 0x3F))
 enum {
-OPC_MSA_I8_00   = 0x00 | OPC_MSA,
-OPC_MSA_I8_01   = 0x01 | OPC_MSA,
-OPC_MSA_I8_02   = 0x02 | OPC_MSA,
 OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
 OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
 OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
@@ -54,15 +51,6 @@ enum {
 };
 
 enum {
-/* I8 instruction */
-OPC_ANDI_B  = (0x0 << 24) | OPC_MSA_I8_00,
-OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
-OPC_ORI_B   = (0x1 << 24) | OPC_MSA_I8_00,
-OPC_BMZI_B  = (0x1 << 24) | OPC_MSA_I8_01,
-OPC_NORI_B  = (0x2 << 24) | OPC_MSA_I8_00,
-OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
-OPC_XORI_B  = (0x3 << 24) | OPC_MSA_I8_00,
-
 /* VEC/2R/2RF instruction */
 OPC_AND_V   = (0x00 << 21) | OPC_MSA_VEC,
 OPC_OR_V= (0x01 << 21) | OPC_MSA_VEC,
@@ -418,50 +406,31 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
 }
 
-static void gen_msa_i8(DisasContext *ctx)
+static bool trans_msa_i8(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i8)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_I8(op)(MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
-uint8_t i8 = (ctx->opcode >> 16) & 0xff;
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 timm = tcg_const_i32(a->sa);
 
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv_i32 tws = tcg_const_i32(ws);
-TCGv_i32 ti8 = tcg_const_i32(i8);
-
-switch (MASK_MSA_I8(ctx->opcode)) {
-case OPC_ANDI_B:
-gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_ORI_B:
-gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_NORI_B:
-gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_XORI_B:
-gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_BMNZI_B:
-gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_BMZI_B:
-gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
-break;
-case OPC_BSELI_B:
-gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
-break;
-default:
-MIPS_INVAL("MSA instruction");
-gen_reserved_instruction(ctx);
-break;
-}
+gen_msa_i8(cpu_env, twd, tws, timm);
 
 tcg_temp_free_i32(twd);
 tcg_temp_free_i32(tws);
-tcg_temp_free_i32(ti8);
+tcg_temp_free_i32(timm);
+
+return true;
 }
 
+TRANS_MSA(ANDI, trans_msa_i8, gen_helper_msa_andi_b);
+TRANS_MSA(ORI,  trans_msa_i8, gen_helper_msa_ori_b);
+TRANS_MSA(NORI, trans_msa_i8, gen_helper_msa_nori_b);
+TRANS_MSA(XORI, trans_msa_i8, gen_helper_msa_xori_b);
+TRANS_MSA(BMNZI,trans_msa_i8, gen_helper_msa_bmnzi_b);
+TRANS_MSA(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b);
+TRANS_MSA(BSELI,

[PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert 2-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  3 ++
 target/mips/tcg/msa_translate.c | 91 +
 2 files changed, 28 insertions(+), 66 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index e97490cf880..88757f547eb 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -78,6 +78,9 @@ BNZ 010001 111 .. . 
@bz
   SRLRI 00 011 ... . .  001010  @bit
 
   FILL  00 1100 .. . .  00  @2r
+  PCNT  00 1101 .. . .  00  @2r
+  NLOC  00 1110 .. . .  00  @2r
+  NLZC  00 1111 .. . .  00  @2r
   FCLASS00 11001 . . .  00  @2rf
   FTRUNC_S  00 110010001 . . .  00  @2rf
   FTRUNC_U  00 110010010 . . .  00  @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fc0b80f83ac..f54e9d173ac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -50,13 +50,6 @@ enum {
 OPC_BMZ_V   = (0x05 << 21) | OPC_MSA_VEC,
 OPC_BSEL_V  = (0x06 << 21) | OPC_MSA_VEC,
 
-OPC_MSA_2R  = (0x18 << 21) | OPC_MSA_VEC,
-
-/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
-OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
-OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
-OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
-
 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
 OPC_SLL_df  = (0x0 << 23) | OPC_MSA_3R_0D,
 OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1832,75 +1825,44 @@ static void gen_msa_3rf(DisasContext *ctx)
 tcg_temp_free_i32(twt);
 }
 
-static void gen_msa_2r(DisasContext *ctx)
+static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
+ void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-(op & (0x7 << 18)))
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-uint8_t df = (ctx->opcode >> 16) & 0x3;
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv_i32 tws = tcg_const_i32(ws);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
 
-switch (MASK_MSA_2R(ctx->opcode)) {
-case OPC_NLOC_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_nloc_b(cpu_env, twd, tws);
-break;
-case DF_HALF:
-gen_helper_msa_nloc_h(cpu_env, twd, tws);
-break;
-case DF_WORD:
-gen_helper_msa_nloc_w(cpu_env, twd, tws);
-break;
-case DF_DOUBLE:
-gen_helper_msa_nloc_d(cpu_env, twd, tws);
-break;
+switch (a->df) {
+case DF_BYTE:
+if (gen_msa_2r_b == NULL) {
+gen_reserved_instruction(ctx);
+} else {
+gen_msa_2r_b(cpu_env, twd, tws);
 }
 break;
-case OPC_NLZC_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_nlzc_b(cpu_env, twd, tws);
-break;
-case DF_HALF:
-gen_helper_msa_nlzc_h(cpu_env, twd, tws);
-break;
-case DF_WORD:
-gen_helper_msa_nlzc_w(cpu_env, twd, tws);
-break;
-case DF_DOUBLE:
-gen_helper_msa_nlzc_d(cpu_env, twd, tws);
-break;
-}
+case DF_HALF:
+gen_msa_2r_h(cpu_env, twd, tws);
 break;
-case OPC_PCNT_df:
-switch (df) {
-case DF_BYTE:
-gen_helper_msa_pcnt_b(cpu_env, twd, tws);
-break;
-case DF_HALF:
-gen_helper_msa_pcnt_h(cpu_env, twd, tws);
-break;
-case DF_WORD:
-gen_helper_msa_pcnt_w(cpu_env, twd, tws);
-break;
-case DF_DOUBLE:
-gen_helper_msa_pcnt_d(cpu_env, twd, tws);
-break;
-}
+case DF_WORD:
+gen_msa_2r_w(cpu_env, twd, tws);
 break;
-default:
-MIPS_INVAL("MSA instruction");
-gen_reserved_instruction(ctx);
+case DF_DOUBLE:
+gen_msa_2r_d(cpu_env, twd, tws);
 break;
 }
 
 tcg_temp_free_i32(twd);
 tcg_temp_free_i32(tws);
+
+return true;
 }
 
+TRANS_DF_E(PCNT, trans_msa_2r, gen_helper_msa_pcnt);
+TRANS_DF_E(NLOC, trans_msa_2r, gen_helper_msa_nloc);
+TRANS_DF_E(NLZC, trans_msa_2r, gen_helper_msa_nlzc);
+
 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
 {
 TCGv_i32 twd;
@@ -2018,9 

[PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert 2-register floating-point operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  19 ++
 target/mips/tcg/msa_translate.c | 109 
 2 files changed, 46 insertions(+), 82 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5fe6923ace5..2997bfa24e3 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,6 +13,7 @@
 
   rs rt rd sa
 
+_r  df wd ws wt
 _bz df   wt sa
 _ldst   df wd wssa
 
@@ -20,6 +21,7 @@
 @ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
@@ -74,6 +76,23 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  FCLASS00 11001 . . .  00  @2rf
+  FTRUNC_S  00 110010001 . . .  00  @2rf
+  FTRUNC_U  00 110010010 . . .  00  @2rf
+  FSQRT 00 110010011 . . .  00  @2rf
+  FRSQRT00 110010100 . . .  00  @2rf
+  FRCP  00 110010101 . . .  00  @2rf
+  FRINT 00 110010110 . . .  00  @2rf
+  FLOG2 00 110010111 . . .  00  @2rf
+  FEXUPL00 110011000 . . .  00  @2rf
+  FEXUPR00 110011001 . . .  00  @2rf
+  FFQL  00 110011010 . . .  00  @2rf
+  FFQR  00 110011011 . . .  00  @2rf
+  FTINT_S   00 110011100 . . .  00  @2rf
+  FTINT_U   00 110011101 . . .  00  @2rf
+  FFINT_S   00 11000 . . .  00  @2rf
+  FFINT_U   00 11001 . . .  00  @2rf
+
   LD00 .. . .   1000 .. @ldst
   ST00 .. . .   1001 .. @ldst
 
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 52af99636a4..c6a77381c0e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -41,7 +41,7 @@ enum {
 };
 
 enum {
-/* VEC/2R/2RF instruction */
+/* VEC/2R instruction */
 OPC_AND_V   = (0x00 << 21) | OPC_MSA_VEC,
 OPC_OR_V= (0x01 << 21) | OPC_MSA_VEC,
 OPC_NOR_V   = (0x02 << 21) | OPC_MSA_VEC,
@@ -51,7 +51,6 @@ enum {
 OPC_BSEL_V  = (0x06 << 21) | OPC_MSA_VEC,
 
 OPC_MSA_2R  = (0x18 << 21) | OPC_MSA_VEC,
-OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
 
 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
 OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
@@ -59,24 +58,6 @@ enum {
 OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
 OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
 
-/* 2RF instruction df(bit 16) = _w, _d */
-OPC_FCLASS_df   = (0x00 << 17) | OPC_MSA_2RF,
-OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
-OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
-OPC_FSQRT_df= (0x03 << 17) | OPC_MSA_2RF,
-OPC_FRSQRT_df   = (0x04 << 17) | OPC_MSA_2RF,
-OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
-OPC_FRINT_df= (0x06 << 17) | OPC_MSA_2RF,
-OPC_FLOG2_df= (0x07 << 17) | OPC_MSA_2RF,
-OPC_FEXUPL_df   = (0x08 << 17) | OPC_MSA_2RF,
-OPC_FEXUPR_df   = (0x09 << 17) | OPC_MSA_2RF,
-OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
-OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
-OPC_FTINT_S_df  = (0x0C << 17) | OPC_MSA_2RF,
-OPC_FTINT_U_df  = (0x0D << 17) | OPC_MSA_2RF,
-OPC_FFINT_S_df  = (0x0E << 17) | OPC_MSA_2RF,
-OPC_FFINT_U_df  = (0x0F << 17) | OPC_MSA_2RF,
-
 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
 OPC_SLL_df  = (0x0 << 23) | OPC_MSA_3R_0D,
 OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1932,73 +1913,40 @@ static void gen_msa_2r(DisasContext *ctx)
 tcg_temp_free_i32(tws);
 }
 
-static void gen_msa_2rf(DisasContext *ctx)
+static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
+  void (*gen_msa_2rf)(TCGv_ptr, TCGv_i32,
+  TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_2RF(op)(MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
-(op & (0xf << 17)))
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-uint8_t df = (ctx->opcode >> 16) & 

[PATCH 31/33] target/mips: Remove generic MSA opcode

[Philippe Mathieu-Daudé]

All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  | 2 --
 target/mips/tcg/msa_translate.c | 7 ---
 2 files changed, 9 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 52dac0fde6d..8189eae3499 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -245,6 +245,4 @@ BNZ 010001 111 .. . 
@bz
 
   LD00 .. . .   1000 .. @ldst
   ST00 .. . .   1001 .. @ldst
-
-  MSA   00 --
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 51af6f39cc4..5d8cad378e6 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -865,13 +865,6 @@ TRANS_MSA(BMNZ_V,   trans_msa_vec, gen_helper_msa_bmnz_v);
 TRANS_MSA(BMZ_V,trans_msa_vec, gen_helper_msa_bmz_v);
 TRANS_MSA(BSEL_V,   trans_msa_vec, gen_helper_msa_bsel_v);
 
-static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
-{
-gen_reserved_instruction(ctx);
-
-return true;
-}
-
 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_ldst *a,
void (*gen_msa_b)(TCGv_ptr, TCGv_i32, TCGv),
void (*gen_msa_h)(TCGv_ptr, TCGv_i32, TCGv),
-- 
2.31.1

[PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert instructions with a 5-bit immediate value to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  | 15 +
 target/mips/tcg/msa_translate.c | 99 +
 2 files changed, 40 insertions(+), 74 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 86aa66f05b9..5aaa85456da 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -19,6 +19,8 @@
 @lsa.. rs:5 rt:5 rd:5 ... sa:2 ..   
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
+@s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
 
 LSA 00 . . . 000 .. 000101  @lsa
@@ -30,6 +32,19 @@ BZ  010001 110 .. . 
@bz
 BNZ 010001 111 .. . @bz
 
 {
+  ADDVI 00 000 .. . . . 000110  @u5
+  SUBVI 00 001 .. . . . 000110  @u5
+  MAXI_S00 010 .. . . . 000110  @s5
+  MAXI_U00 011 .. . . . 000110  @u5
+  MINI_S00 100 .. . . . 000110  @s5
+  MINI_U00 101 .. . . . 000110  @u5
+
+  CEQI  00 000 .. . . . 000111  @s5
+  CLTI_S00 010 .. . . . 000111  @s5
+  CLTI_U00 011 .. . . . 000111  @u5
+  CLEI_S00 100 .. . . . 000111  @s5
+  CLEI_U00 101 .. . . . 000111  @u5
+
   LDI   00 110 .. ..  . 000111  @ldi
 
   MSA   00 --
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7c1bbfaec61..962aef601cb 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
 OPC_MSA_I8_00   = 0x00 | OPC_MSA,
 OPC_MSA_I8_01   = 0x01 | OPC_MSA,
 OPC_MSA_I8_02   = 0x02 | OPC_MSA,
-OPC_MSA_I5_06   = 0x06 | OPC_MSA,
-OPC_MSA_I5_07   = 0x07 | OPC_MSA,
 OPC_MSA_BIT_09  = 0x09 | OPC_MSA,
 OPC_MSA_BIT_0A  = 0x0A | OPC_MSA,
 OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
@@ -58,19 +56,6 @@ enum {
 };
 
 enum {
-/* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
-OPC_ADDVI_df= (0x0 << 23) | OPC_MSA_I5_06,
-OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
-OPC_SUBVI_df= (0x1 << 23) | OPC_MSA_I5_06,
-OPC_MAXI_S_df   = (0x2 << 23) | OPC_MSA_I5_06,
-OPC_CLTI_S_df   = (0x2 << 23) | OPC_MSA_I5_07,
-OPC_MAXI_U_df   = (0x3 << 23) | OPC_MSA_I5_06,
-OPC_CLTI_U_df   = (0x3 << 23) | OPC_MSA_I5_07,
-OPC_MINI_S_df   = (0x4 << 23) | OPC_MSA_I5_06,
-OPC_CLEI_S_df   = (0x4 << 23) | OPC_MSA_I5_07,
-OPC_MINI_U_df   = (0x5 << 23) | OPC_MSA_I5_06,
-OPC_CLEI_U_df   = (0x5 << 23) | OPC_MSA_I5_07,
-
 /* I8 instruction */
 OPC_ANDI_B  = (0x0 << 24) | OPC_MSA_I8_00,
 OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
@@ -341,6 +326,9 @@ static inline bool check_msa_access(DisasContext *ctx)
 return true;
 }
 
+#define TRANS_MSA(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
 {
@@ -507,69 +495,36 @@ static void gen_msa_i8(DisasContext *ctx)
 tcg_temp_free_i32(ti8);
 }
 
-static void gen_msa_i5(DisasContext *ctx)
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
+TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_I5(op)(MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
-uint8_t u5 = extract32(ctx->opcode, 16, 5);
+TCGv_i32 tdf = tcg_constant_i32(a->df);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 timm = tcg_const_i32(a->sa);
 
-TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
-TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
-TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
-TCGv_i32 timm = tcg_temp_new_i32();
-tcg_gen_movi_i32(timm, u5);
+gen_msa_i5(cpu_env, tdf, twd, tws, timm);
 
-switch (MASK_MSA_I5(ctx->opcode)) {
-case OPC_ADDVI_df:
-gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
-break;
-case OPC_SUBVI_df:
-gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
-break;
-case 

[PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree

[Philippe Mathieu-Daudé]

Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  3 +++
 target/mips/tcg/msa_translate.c | 47 +
 2 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 91d71ff560c..6347468a709 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
+@i8_df  .. df:2 sa:s8 ws:5 wd:5 ..  _ldst
 @bit.. ... df:7   ws:5 wd:5 ..  _ldst sa=0
 
 LSA 00 . . . 000 .. 000101  @lsa
@@ -33,6 +34,8 @@ BZ  010001 110 .. . 
@bz
 BNZ 010001 111 .. . @bz
 
 {
+  SHF   00 ..  . .  10  @i8_df
+
   ADDVI 00 000 .. . . . 000110  @u5
   SUBVI 00 001 .. . . . 000110  @u5
   MAXI_S00 010 .. . . . 000110  @s5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 10bbe25172a..7cb078bfe92 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -57,13 +57,10 @@ enum {
 /* I8 instruction */
 OPC_ANDI_B  = (0x0 << 24) | OPC_MSA_I8_00,
 OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
-OPC_SHF_B   = (0x0 << 24) | OPC_MSA_I8_02,
 OPC_ORI_B   = (0x1 << 24) | OPC_MSA_I8_00,
 OPC_BMZI_B  = (0x1 << 24) | OPC_MSA_I8_01,
-OPC_SHF_H   = (0x1 << 24) | OPC_MSA_I8_02,
 OPC_NORI_B  = (0x2 << 24) | OPC_MSA_I8_00,
 OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
-OPC_SHF_W   = (0x2 << 24) | OPC_MSA_I8_02,
 OPC_XORI_B  = (0x3 << 24) | OPC_MSA_I8_00,
 
 /* VEC/2R/2RF instruction */
@@ -454,20 +451,6 @@ static void gen_msa_i8(DisasContext *ctx)
 case OPC_BSELI_B:
 gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
 break;
-case OPC_SHF_B:
-case OPC_SHF_H:
-case OPC_SHF_W:
-{
-uint8_t df = (ctx->opcode >> 24) & 0x3;
-if (df == DF_DOUBLE) {
-gen_reserved_instruction(ctx);
-} else {
-TCGv_i32 tdf = tcg_const_i32(df);
-gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
-tcg_temp_free_i32(tdf);
-}
-}
-break;
 default:
 MIPS_INVAL("MSA instruction");
 gen_reserved_instruction(ctx);
@@ -479,6 +462,36 @@ static void gen_msa_i8(DisasContext *ctx)
 tcg_temp_free_i32(ti8);
 }
 
+static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
+{
+TCGv_i32 tdf;
+TCGv_i32 twd;
+TCGv_i32 tws;
+TCGv_i32 timm;
+
+if (a->df == DF_DOUBLE) {
+gen_reserved_instruction(ctx);
+return true;
+}
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+tdf = tcg_constant_i32(a->df);
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
+timm = tcg_const_i32(a->sa);
+
+gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, timm);
+
+tcg_temp_free_i32(tws);
+tcg_temp_free_i32(twd);
+tcg_temp_free_i32(timm);
+
+return true;
+}
+
 static bool trans_msa_i5(DisasContext *ctx, arg_msa_ldst *a,
  void (*gen_msa_i5)(TCGv_ptr, TCGv_i32, TCGv_i32,
 TCGv_i32, TCGv_i32))
-- 
2.31.1

[PATCH 07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v

[Philippe Mathieu-Daudé]

This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.

Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  | 15 +++
 target/mips/tcg/msa_translate.c | 20 ++--
 2 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 74d99f6862c..aa784cf12a9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,19 +13,18 @@
 
   rs rt rd sa
 
-_bz df wt s16
+_bz df   wt sa
 
 @lsa.. rs:5 rt:5 rd:5 ... sa:2 ..   
-@bz .. ... ..   wt:5 s16:16 _bz df=3
-@bz_df  .. ... df:2 wt:5 s16:16 _bz
+@bz_v   .. ... ..wt:5 sa:16 _bz df=3
+@bz .. ...  df:2 wt:5 sa:16 _bz
 
 LSA 00 . . . 000 .. 000101  @lsa
 DLSA00 . . . 000 .. 010101  @lsa
 
-BZ_V010001 01011  . @bz
-BNZ_V   010001 0  . @bz
-
-BZ_x010001 110 .. . @bz_df
-BNZ_x   010001 111 .. . @bz_df
+BZ_V010001 01011  . @bz_v
+BNZ_V   010001 0  . @bz_v
+BZ  010001 110 .. . @bz
+BNZ 010001 111 .. . @bz
 
 MSA 00 --
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 1c4a802ff55..c2a48aecc46 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -350,7 +350,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t 
df, uint8_t wt,
 tcg_temp_free_i64(t1);
 }
 
-static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
 {
 TCGv_i64 t0;
 
@@ -368,7 +368,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int 
s16, TCGCond cond)
 tcg_gen_trunc_i64_tl(bcond, t0);
 tcg_temp_free_i64(t0);
 
-ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
 
 ctx->hflags |= MIPS_HFLAG_BC;
 ctx->hflags |= MIPS_HFLAG_BDS32;
@@ -378,15 +378,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int 
s16, TCGCond cond)
 
 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
 {
-return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
 }
 
 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
 {
-return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
 }
 
-static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool 
if_not)
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
 {
 if (!check_msa_access(ctx)) {
 return false;
@@ -399,21 +399,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int 
wt, int s16, bool if_not)
 
 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
 
-ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
 ctx->hflags |= MIPS_HFLAG_BC;
 ctx->hflags |= MIPS_HFLAG_BDS32;
 
 return true;
 }
 
-static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
 {
-return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
 }
 
-static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
 {
-return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
 }
 
 static void gen_msa_i8(DisasContext *ctx)
-- 
2.31.1

[PATCH 22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)

[Philippe Mathieu-Daudé]

Convert 3-register operations to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  6 ++
 target/mips/tcg/msa_translate.c | 35 ++---
 2 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 28b7a71d930..ca0fd568560 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -24,6 +24,7 @@
 @vec.. . wt:5 ws:5 wd:5 ..  _r df=0
 @2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
+@3r .. ...  df:2 wt:5 ws:5 wd:5 ..  _r
 @3rf..  df:1 wt:5 ws:5 wd:5 ..  _r
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
@@ -79,6 +80,11 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  SLD   00 000 .. . . . 010100  @3r
+  SPLAT 00 001 .. . . . 010100  @3r
+
+  VSHF  00 000 .. . . . 010101  @3r
+
   FCAF  00  . . . . 011010  @3rf
   FCUN  00 0001 . . . . 011010  @3rf
   FCEQ  00 0010 . . . . 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 4543b7abdfb..0c7055c68bd 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -45,15 +45,12 @@ enum {
 OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
 OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
 OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
-OPC_SLD_df  = (0x0 << 23) | OPC_MSA_3R_14,
-OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
 OPC_SRA_df  = (0x1 << 23) | OPC_MSA_3R_0D,
 OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
 OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
 OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
 OPC_MADDV_df= (0x1 << 23) | OPC_MSA_3R_12,
 OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
-OPC_SPLAT_df= (0x1 << 23) | OPC_MSA_3R_14,
 OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
 OPC_SRL_df  = (0x2 << 23) | OPC_MSA_3R_0D,
 OPC_MAX_S_df= (0x2 << 23) | OPC_MSA_3R_0E,
@@ -469,6 +466,29 @@ TRANS_MSA(SAT_U,trans_msa_bit, 
gen_helper_msa_sat_u_df);
 TRANS_MSA(SRARI,trans_msa_bit, gen_helper_msa_srari_df);
 TRANS_MSA(SRLRI,trans_msa_bit, gen_helper_msa_srlri_df);
 
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32, TCGv_i32,
+  TCGv_i32, TCGv_i32))
+{
+TCGv_i32 tdf = tcg_constant_i32(a->df);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);
+
+gen_msa_3r_df(cpu_env, tdf, twd, tws, twt);
+
+tcg_temp_free_i32(twd);
+tcg_temp_free_i32(tws);
+tcg_temp_free_i32(twt);
+
+return true;
+}
+
+TRANS_MSA(SLD,  trans_msa_3r_df, gen_helper_msa_sld_df);
+TRANS_MSA(SPLAT,trans_msa_3r_df, gen_helper_msa_splat_df);
+
+TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df);
+
 static void gen_msa_3r(DisasContext *ctx)
 {
 #define MASK_MSA_3R(op)(MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1219,12 +1239,6 @@ static void gen_msa_3r(DisasContext *ctx)
 break;
 }
 break;
-case OPC_SLD_df:
-gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
-break;
-case OPC_VSHF_df:
-gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
-break;
 case OPC_SUBV_df:
 switch (df) {
 case DF_BYTE:
@@ -1257,9 +1271,6 @@ static void gen_msa_3r(DisasContext *ctx)
 break;
 }
 break;
-case OPC_SPLAT_df:
-gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
-break;
 case OPC_SUBSUS_U_df:
 switch (df) {
 case DF_BYTE:
-- 
2.31.1

[PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers

[Philippe Mathieu-Daudé]

Similar to the TRANS() macro introduced in commit fb3164e412d,
introduce TRANS_CHECK() which takes a boolean expression as
argument.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/translate.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 6111493651f..3ef09cc50c9 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -224,6 +224,15 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
 { return FUNC(ctx, a, __VA_ARGS__); }
 
+#define TRANS_CHECK(NAME, CHECK_EXPR, FUNC, ...) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+if (!(CHECK_EXPR)) { \
+return false; \
+} \
+return FUNC(ctx, a, __VA_ARGS__); \
+}
+
 static inline bool cpu_is_bigendian(DisasContext *ctx)
 {
 return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
-- 
2.31.1

[PATCH 23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)

[Philippe Mathieu-Daudé]

Convert 3-register operations to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  11 ++
 target/mips/tcg/msa_translate.c | 213 +---
 2 files changed, 66 insertions(+), 158 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index ca0fd568560..4a9cf85fa7a 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -80,10 +80,21 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  DOTP_S00 000.. . . .  010011  @3r
+  DOTP_U00 001.. . . .  010011  @3r
+  DPADD_S   00 010.. . . .  010011  @3r
+  DPADD_U   00 011.. . . .  010011  @3r
+  DPSUB_S   00 100.. . . .  010011  @3r
+  DPSUB_U   00 101.. . . .  010011  @3r
+
   SLD   00 000 .. . . . 010100  @3r
   SPLAT 00 001 .. . . . 010100  @3r
 
   VSHF  00 000 .. . . . 010101  @3r
+  HADD_S00 100.. . . .  010101  @3r
+  HADD_U00 101.. . . .  010101  @3r
+  HSUB_S00 110.. . . .  010101  @3r
+  HSUB_U00 111.. . . .  010101  @3r
 
   FCAF  00  . . . . 011010  @3rf
   FCUN  00 0001 . . . . 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 0c7055c68bd..e1da532e5c9 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -44,13 +44,11 @@ enum {
 OPC_ADD_A_df= (0x0 << 23) | OPC_MSA_3R_10,
 OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
 OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
-OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
 OPC_SRA_df  = (0x1 << 23) | OPC_MSA_3R_0D,
 OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
 OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
 OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
 OPC_MADDV_df= (0x1 << 23) | OPC_MSA_3R_12,
-OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
 OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
 OPC_SRL_df  = (0x2 << 23) | OPC_MSA_3R_0D,
 OPC_MAX_S_df= (0x2 << 23) | OPC_MSA_3R_0E,
@@ -58,7 +56,6 @@ enum {
 OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
 OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
 OPC_MSUBV_df= (0x2 << 23) | OPC_MSA_3R_12,
-OPC_DPADD_S_df  = (0x2 << 23) | OPC_MSA_3R_13,
 OPC_PCKEV_df= (0x2 << 23) | OPC_MSA_3R_14,
 OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
 OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
@@ -66,7 +63,6 @@ enum {
 OPC_CLT_U_df= (0x3 << 23) | OPC_MSA_3R_0F,
 OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
 OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
-OPC_DPADD_U_df  = (0x3 << 23) | OPC_MSA_3R_13,
 OPC_PCKOD_df= (0x3 << 23) | OPC_MSA_3R_14,
 OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
 OPC_MIN_S_df= (0x4 << 23) | OPC_MSA_3R_0E,
@@ -74,30 +70,24 @@ enum {
 OPC_AVE_S_df= (0x4 << 23) | OPC_MSA_3R_10,
 OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
 OPC_DIV_S_df= (0x4 << 23) | OPC_MSA_3R_12,
-OPC_DPSUB_S_df  = (0x4 << 23) | OPC_MSA_3R_13,
 OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
-OPC_HADD_S_df   = (0x4 << 23) | OPC_MSA_3R_15,
 OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
 OPC_MIN_U_df= (0x5 << 23) | OPC_MSA_3R_0E,
 OPC_CLE_U_df= (0x5 << 23) | OPC_MSA_3R_0F,
 OPC_AVE_U_df= (0x5 << 23) | OPC_MSA_3R_10,
 OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
 OPC_DIV_U_df= (0x5 << 23) | OPC_MSA_3R_12,
-OPC_DPSUB_U_df  = (0x5 << 23) | OPC_MSA_3R_13,
 OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
-OPC_HADD_U_df   = (0x5 << 23) | OPC_MSA_3R_15,
 OPC_BINSL_df= (0x6 << 23) | OPC_MSA_3R_0D,
 OPC_MAX_A_df= (0x6 << 23) | OPC_MSA_3R_0E,
 OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
 OPC_MOD_S_df= (0x6 << 23) | OPC_MSA_3R_12,
 OPC_ILVEV_df= (0x6 << 23) | OPC_MSA_3R_14,
-OPC_HSUB_S_df   = (0x6 << 23) | OPC_MSA_3R_15,
 OPC_BINSR_df= (0x7 << 23) | OPC_MSA_3R_0D,
 OPC_MIN_A_df= (0x7 << 23) | OPC_MSA_3R_0E,
 OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
 OPC_MOD_U_df= (0x7 << 23) | OPC_MSA_3R_12,
 OPC_ILVOD_df= (0x7 << 23) | OPC_MSA_3R_14,
-OPC_HSUB_U_df   = (0x7 << 23) | OPC_MSA_3R_15,
 
 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
 OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
@@ -209,6 +199,10 @@ static inline bool check_msa_access(DisasContext *ctx)
 TRANS_CHECK(NAME, check_msa_access(ctx), 

[PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert instructions with an immediate bit index and
data format df/m to decodetree.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  | 15 +
 target/mips/tcg/msa_translate.c | 98 -
 2 files changed, 39 insertions(+), 74 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 5aaa85456da..91d71ff560c 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -22,6 +22,7 @@
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
 @s5 .. ... df:2 sa:s5 ws:5 wd:5 ..  _ldst
 @ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
+@bit.. ... df:7   ws:5 wd:5 ..  _ldst sa=0
 
 LSA 00 . . . 000 .. 000101  @lsa
 DLSA00 . . . 000 .. 010101  @lsa
@@ -47,5 +48,19 @@ BNZ 010001 111 .. . 
@bz
 
   LDI   00 110 .. ..  . 000111  @ldi
 
+  SLLI  00 000 ... . .  001001  @bit
+  SRAI  00 001 ... . .  001001  @bit
+  SRLI  00 010 ... . .  001001  @bit
+  BCLRI 00 011 ... . .  001001  @bit
+  BSETI 00 100 ... . .  001001  @bit
+  BNEGI 00 101 ... . .  001001  @bit
+  BINSLI00 110 ... . .  001001  @bit
+  BINSRI00 111 ... . .  001001  @bit
+
+  SAT_S 00 000 ... . .  001010  @bit
+  SAT_U 00 001 ... . .  001010  @bit
+  SRARI 00 010 ... . .  001010  @bit
+  SRLRI 00 011 ... . .  001010  @bit
+
   MSA   00 --
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 962aef601cb..10bbe25172a 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
 OPC_MSA_I8_00   = 0x00 | OPC_MSA,
 OPC_MSA_I8_01   = 0x01 | OPC_MSA,
 OPC_MSA_I8_02   = 0x02 | OPC_MSA,
-OPC_MSA_BIT_09  = 0x09 | OPC_MSA,
-OPC_MSA_BIT_0A  = 0x0A | OPC_MSA,
 OPC_MSA_3R_0D   = 0x0D | OPC_MSA,
 OPC_MSA_3R_0E   = 0x0E | OPC_MSA,
 OPC_MSA_3R_0F   = 0x0F | OPC_MSA,
@@ -222,20 +220,6 @@ enum {
 OPC_MSUBR_Q_df  = (0xE << 22) | OPC_MSA_3RF_1C,
 OPC_FSULE_df= (0xF << 22) | OPC_MSA_3RF_1A,
 OPC_FMAX_A_df   = (0xF << 22) | OPC_MSA_3RF_1B,
-
-/* BIT instruction df(bits 22..16) = _B _H _W _D */
-OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
-OPC_SAT_S_df= (0x0 << 23) | OPC_MSA_BIT_0A,
-OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
-OPC_SAT_U_df= (0x1 << 23) | OPC_MSA_BIT_0A,
-OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
-OPC_SRARI_df= (0x2 << 23) | OPC_MSA_BIT_0A,
-OPC_BCLRI_df= (0x3 << 23) | OPC_MSA_BIT_09,
-OPC_SRLRI_df= (0x3 << 23) | OPC_MSA_BIT_0A,
-OPC_BSETI_df= (0x4 << 23) | OPC_MSA_BIT_09,
-OPC_BNEGI_df= (0x5 << 23) | OPC_MSA_BIT_09,
-OPC_BINSLI_df   = (0x6 << 23) | OPC_MSA_BIT_09,
-OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
 };
 
 static const char msaregnames[][6] = {
@@ -547,78 +531,48 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
 return true;
 }
 
-static void gen_msa_bit(DisasContext *ctx)
+static bool trans_msa_bit(DisasContext *ctx, arg_msa_ldst *a,
+  void (*gen_msa_bit)(TCGv_ptr, TCGv_i32, TCGv_i32,
+  TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_BIT(op)(MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
 TCGv_i32 tdf;
 TCGv_i32 tm;
 TCGv_i32 twd;
 TCGv_i32 tws;
 uint32_t df, m;
 
-if (!df_extract(df_bit, dfm, , )) {
+if (!df_extract(df_bit, a->df, , )) {
 gen_reserved_instruction(ctx);
-return;
+return true;
 }
 
-tdf = tcg_const_i32(df);
+tdf = tcg_constant_i32(df);
 tm  = tcg_const_i32(m);
-twd = tcg_const_i32(wd);
-tws = tcg_const_i32(ws);
+twd = tcg_const_i32(a->wd);
+tws = tcg_const_i32(a->ws);
 
-switch (MASK_MSA_BIT(ctx->opcode)) {
-case OPC_SLLI_df:
-gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
-break;
-case OPC_SRAI_df:
-gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
-break;
-case OPC_SRLI_df:
-gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
-break;
-case OPC_BCLRI_df:
-gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
-break;
-case OPC_BSETI_df:
- 

[PATCH 06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum

[Philippe Mathieu-Daudé]

Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 9e0a08fe335..1c4a802ff55 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1801,10 +1801,10 @@ static void gen_msa_3rf(DisasContext *ctx)
 case OPC_MULR_Q_df:
 case OPC_MADDR_Q_df:
 case OPC_MSUBR_Q_df:
-tdf = tcg_constant_i32(df + 1);
+tdf = tcg_constant_i32(DF_HALF + df);
 break;
 default:
-tdf = tcg_constant_i32(df + 2);
+tdf = tcg_constant_i32(DF_WORD + df);
 break;
 }
 
@@ -2033,7 +2033,7 @@ static void gen_msa_2rf(DisasContext *ctx)
 TCGv_i32 twd = tcg_const_i32(wd);
 TCGv_i32 tws = tcg_const_i32(ws);
 /* adjust df value for floating-point instruction */
-TCGv_i32 tdf = tcg_constant_i32(df + 2);
+TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
 
 switch (MASK_MSA_2RF(ctx->opcode)) {
 case OPC_FCLASS_df:
-- 
2.31.1

[PATCH 05/33] target/mips: Have check_msa_access() return a boolean

[Philippe Mathieu-Daudé]

Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_translate.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..9e0a08fe335 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -293,19 +293,19 @@ void msa_translate_init(void)
 }
 }
 
-static inline int check_msa_access(DisasContext *ctx)
+static inline bool check_msa_access(DisasContext *ctx)
 {
 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
  !(ctx->hflags & MIPS_HFLAG_F64))) {
 gen_reserved_instruction(ctx);
-return 0;
+return false;
 }
 
 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
 generate_exception_end(ctx, EXCP_MSADIS);
-return 0;
+return false;
 }
-return 1;
+return true;
 }
 
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
@@ -354,7 +354,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int 
s16, TCGCond cond)
 {
 TCGv_i64 t0;
 
-check_msa_access(ctx);
+if (!check_msa_access(ctx)) {
+return false;
+}
 
 if (ctx->hflags & MIPS_HFLAG_BMASK) {
 gen_reserved_instruction(ctx);
@@ -386,7 +388,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
 
 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool 
if_not)
 {
-check_msa_access(ctx);
+if (!check_msa_access(ctx)) {
+return false;
+}
 
 if (ctx->hflags & MIPS_HFLAG_BMASK) {
 gen_reserved_instruction(ctx);
@@ -2158,7 +2162,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 {
 uint32_t opcode = ctx->opcode;
 
-check_msa_access(ctx);
+if (!check_msa_access(ctx)) {
+return false;
+}
 
 switch (MASK_MSA_MINOR(opcode)) {
 case OPC_MSA_I8_00:
-- 
2.31.1

[PATCH 10/33] target/mips: Extract df_extract() helper

[Philippe Mathieu-Daudé]

Extract the common code which parses data formats to an helper.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_translate.c | 68 +++--
 1 file changed, 39 insertions(+), 29 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3b0dfcca69d..7c1bbfaec61 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -272,6 +272,40 @@ static const char msaregnames[][6] = {
 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
 };
 
+/* Encoding of Operation Field */
+static const struct dfe {
+enum CPUMIPSMSADataFormat df;
+int start;
+int length;
+uint32_t value;
+} df_elm[] = {
+/* Table 3.26 ELM Instruction Format */
+{DF_BYTE,   4, 2, 0b00},
+{DF_HALF,   3, 3, 0b100},
+{DF_WORD,   2, 4, 0b1100},
+{DF_DOUBLE, 1, 5, 0b11100}
+}, df_bit[] = {
+/* Table 3.28 BIT Instruction Format */
+{DF_BYTE,   3, 4, 0b1110},
+{DF_HALF,   4, 3, 0b110},
+{DF_WORD,   5, 2, 0b10},
+{DF_DOUBLE, 6, 1, 0b0}
+};
+
+/* Extract Operation Field (used by ELM & BIT instructions) */
+static bool df_extract(const struct dfe *s, int value,
+   enum CPUMIPSMSADataFormat *df, uint32_t *x)
+{
+for (unsigned i = 0; i < 4; i++) {
+if (extract32(value, s->start, s->length) == s->value) {
+*x = extract32(value, 0, s->start);
+*df = s->df;
+return true;
+}
+}
+return false;
+}
+
 static TCGv_i64 msa_wr_d[64];
 
 void msa_translate_init(void)
@@ -562,7 +596,6 @@ static void gen_msa_bit(DisasContext *ctx)
 {
 #define MASK_MSA_BIT(op)(MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
 uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
-uint32_t df = 0, m = 0;
 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
 
@@ -570,20 +603,9 @@ static void gen_msa_bit(DisasContext *ctx)
 TCGv_i32 tm;
 TCGv_i32 twd;
 TCGv_i32 tws;
+uint32_t df, m;
 
-if ((dfm & 0x40) == 0x00) {
-m = dfm & 0x3f;
-df = DF_DOUBLE;
-} else if ((dfm & 0x60) == 0x40) {
-m = dfm & 0x1f;
-df = DF_WORD;
-} else if ((dfm & 0x70) == 0x60) {
-m = dfm & 0x0f;
-df = DF_HALF;
-} else if ((dfm & 0x78) == 0x70) {
-m = dfm & 0x7;
-df = DF_BYTE;
-} else {
+if (!df_extract(df_bit, dfm, , )) {
 gen_reserved_instruction(ctx);
 return;
 }
@@ -1768,25 +1790,13 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t 
df, uint32_t n)
 static void gen_msa_elm(DisasContext *ctx)
 {
 uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
-uint32_t df = 0, n = 0;
+uint32_t df, n;
 
-if ((dfn & 0x30) == 0x00) {
-n = dfn & 0x0f;
-df = DF_BYTE;
-} else if ((dfn & 0x38) == 0x20) {
-n = dfn & 0x07;
-df = DF_HALF;
-} else if ((dfn & 0x3c) == 0x30) {
-n = dfn & 0x03;
-df = DF_WORD;
-} else if ((dfn & 0x3e) == 0x38) {
-n = dfn & 0x01;
-df = DF_DOUBLE;
-} else if (dfn == 0x3E) {
+if (dfn == 0x3E) {
 /* CTCMSA, CFCMSA, MOVE.V */
 gen_msa_elm_3e(ctx);
 return;
-} else {
+} else if (!df_extract(df_elm, dfn, , )) {
 gen_reserved_instruction(ctx);
 return;
 }
-- 
2.31.1

[PATCH 02/33] target/mips: Fix MSA MADDV.B opcode

[Philippe Mathieu-Daudé]

The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo 
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.")
Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_helper.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index e40c1b70575..d978909527f 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
 
-pwd->b[0]  = msa_maddv_df(DF_BYTE, pwt->b[0],  pws->b[0],  pwt->b[0]);
-pwd->b[1]  = msa_maddv_df(DF_BYTE, pwt->b[1],  pws->b[1],  pwt->b[1]);
-pwd->b[2]  = msa_maddv_df(DF_BYTE, pwt->b[2],  pws->b[2],  pwt->b[2]);
-pwd->b[3]  = msa_maddv_df(DF_BYTE, pwt->b[3],  pws->b[3],  pwt->b[3]);
-pwd->b[4]  = msa_maddv_df(DF_BYTE, pwt->b[4],  pws->b[4],  pwt->b[4]);
-pwd->b[5]  = msa_maddv_df(DF_BYTE, pwt->b[5],  pws->b[5],  pwt->b[5]);
-pwd->b[6]  = msa_maddv_df(DF_BYTE, pwt->b[6],  pws->b[6],  pwt->b[6]);
-pwd->b[7]  = msa_maddv_df(DF_BYTE, pwt->b[7],  pws->b[7],  pwt->b[7]);
-pwd->b[8]  = msa_maddv_df(DF_BYTE, pwt->b[8],  pws->b[8],  pwt->b[8]);
-pwd->b[9]  = msa_maddv_df(DF_BYTE, pwt->b[9],  pws->b[9],  pwt->b[9]);
-pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
-pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
-pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
-pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
-pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
-pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+pwd->b[0]  = msa_maddv_df(DF_BYTE, pwd->b[0],  pws->b[0],  pwt->b[0]);
+pwd->b[1]  = msa_maddv_df(DF_BYTE, pwd->b[1],  pws->b[1],  pwt->b[1]);
+pwd->b[2]  = msa_maddv_df(DF_BYTE, pwd->b[2],  pws->b[2],  pwt->b[2]);
+pwd->b[3]  = msa_maddv_df(DF_BYTE, pwd->b[3],  pws->b[3],  pwt->b[3]);
+pwd->b[4]  = msa_maddv_df(DF_BYTE, pwd->b[4],  pws->b[4],  pwt->b[4]);
+pwd->b[5]  = msa_maddv_df(DF_BYTE, pwd->b[5],  pws->b[5],  pwt->b[5]);
+pwd->b[6]  = msa_maddv_df(DF_BYTE, pwd->b[6],  pws->b[6],  pwt->b[6]);
+pwd->b[7]  = msa_maddv_df(DF_BYTE, pwd->b[7],  pws->b[7],  pwt->b[7]);
+pwd->b[8]  = msa_maddv_df(DF_BYTE, pwd->b[8],  pws->b[8],  pwt->b[8]);
+pwd->b[9]  = msa_maddv_df(DF_BYTE, pwd->b[9],  pws->b[9],  pwt->b[9]);
+pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
 }
 
 void helper_msa_maddv_h(CPUMIPSState *env,
-- 
2.31.1

[PATCH 03/33] target/mips: Fix MSA MSUBV.B opcode

[Philippe Mathieu-Daudé]

The result of the 'Vector Multiply and Subtract' opcode is
incorrect with Byte vectors. Probably due to a copy/paste error,
commit 5f148a02327 mistakenly used the $wt (target register)
instead  of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo 
Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.")
Reviewed-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa_helper.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d978909527f..5667b1f0a15 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env,
 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
 
-pwd->b[0]  = msa_msubv_df(DF_BYTE, pwt->b[0],  pws->b[0],  pwt->b[0]);
-pwd->b[1]  = msa_msubv_df(DF_BYTE, pwt->b[1],  pws->b[1],  pwt->b[1]);
-pwd->b[2]  = msa_msubv_df(DF_BYTE, pwt->b[2],  pws->b[2],  pwt->b[2]);
-pwd->b[3]  = msa_msubv_df(DF_BYTE, pwt->b[3],  pws->b[3],  pwt->b[3]);
-pwd->b[4]  = msa_msubv_df(DF_BYTE, pwt->b[4],  pws->b[4],  pwt->b[4]);
-pwd->b[5]  = msa_msubv_df(DF_BYTE, pwt->b[5],  pws->b[5],  pwt->b[5]);
-pwd->b[6]  = msa_msubv_df(DF_BYTE, pwt->b[6],  pws->b[6],  pwt->b[6]);
-pwd->b[7]  = msa_msubv_df(DF_BYTE, pwt->b[7],  pws->b[7],  pwt->b[7]);
-pwd->b[8]  = msa_msubv_df(DF_BYTE, pwt->b[8],  pws->b[8],  pwt->b[8]);
-pwd->b[9]  = msa_msubv_df(DF_BYTE, pwt->b[9],  pws->b[9],  pwt->b[9]);
-pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
-pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
-pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
-pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
-pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
-pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+pwd->b[0]  = msa_msubv_df(DF_BYTE, pwd->b[0],  pws->b[0],  pwt->b[0]);
+pwd->b[1]  = msa_msubv_df(DF_BYTE, pwd->b[1],  pws->b[1],  pwt->b[1]);
+pwd->b[2]  = msa_msubv_df(DF_BYTE, pwd->b[2],  pws->b[2],  pwt->b[2]);
+pwd->b[3]  = msa_msubv_df(DF_BYTE, pwd->b[3],  pws->b[3],  pwt->b[3]);
+pwd->b[4]  = msa_msubv_df(DF_BYTE, pwd->b[4],  pws->b[4],  pwt->b[4]);
+pwd->b[5]  = msa_msubv_df(DF_BYTE, pwd->b[5],  pws->b[5],  pwt->b[5]);
+pwd->b[6]  = msa_msubv_df(DF_BYTE, pwd->b[6],  pws->b[6],  pwt->b[6]);
+pwd->b[7]  = msa_msubv_df(DF_BYTE, pwd->b[7],  pws->b[7],  pwt->b[7]);
+pwd->b[8]  = msa_msubv_df(DF_BYTE, pwd->b[8],  pws->b[8],  pwt->b[8]);
+pwd->b[9]  = msa_msubv_df(DF_BYTE, pwd->b[9],  pws->b[9],  pwt->b[9]);
+pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
 }
 
 void helper_msa_msubv_h(CPUMIPSState *env,
-- 
2.31.1

[PATCH 19/33] target/mips: Convert MSA VEC instruction format to decodetree

[Philippe Mathieu-Daudé]

Convert 3-register instructions with implicit data formats
to decodetree.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  8 
 target/mips/tcg/msa_translate.c | 82 +++--
 2 files changed, 24 insertions(+), 66 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 88757f547eb..72447041fef 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@
 @ldst   .. sa:s10 ws:5 wd:5  df:2   _ldst
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@vec.. . wt:5 ws:5 wd:5 ..  _r df=0
 @2r ..   df:2 ws:5 wd:5 ..  _r wt=0
 @2rf.. . df:1 ws:5 wd:5 ..  _r wt=0
 @u5 .. ... df:2 sa:5  ws:5 wd:5 ..  _ldst
@@ -77,6 +78,13 @@ BNZ 010001 111 .. . 
@bz
   SRARI 00 010 ... . .  001010  @bit
   SRLRI 00 011 ... . .  001010  @bit
 
+  AND_V 00 0 . . .  00  @vec
+  OR_V  00 1 . . .  00  @vec
+  NOR_V 00 00010 . . .  00  @vec
+  XOR_V 00 00011 . . .  00  @vec
+  BMNZ_V00 00100 . . .  00  @vec
+  BMZ_V 00 00101 . . .  00  @vec
+  BSEL_V00 00110 . . .  00  @vec
   FILL  00 1100 .. . .  00  @2r
   PCNT  00 1101 .. . .  00  @2r
   NLOC  00 1110 .. . .  00  @2r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index f54e9d173ac..461a427c9df 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -37,19 +37,9 @@ enum {
 OPC_MSA_3RF_1A  = 0x1A | OPC_MSA,
 OPC_MSA_3RF_1B  = 0x1B | OPC_MSA,
 OPC_MSA_3RF_1C  = 0x1C | OPC_MSA,
-OPC_MSA_VEC = 0x1E | OPC_MSA,
 };
 
 enum {
-/* VEC/2R instruction */
-OPC_AND_V   = (0x00 << 21) | OPC_MSA_VEC,
-OPC_OR_V= (0x01 << 21) | OPC_MSA_VEC,
-OPC_NOR_V   = (0x02 << 21) | OPC_MSA_VEC,
-OPC_XOR_V   = (0x03 << 21) | OPC_MSA_VEC,
-OPC_BMNZ_V  = (0x04 << 21) | OPC_MSA_VEC,
-OPC_BMZ_V   = (0x05 << 21) | OPC_MSA_VEC,
-OPC_BSEL_V  = (0x06 << 21) | OPC_MSA_VEC,
-
 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
 OPC_SLL_df  = (0x0 << 23) | OPC_MSA_3R_0D,
 OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1925,67 +1915,30 @@ TRANS_MSA(FTINT_U,  trans_msa_2rf, 
gen_helper_msa_ftint_u_df);
 TRANS_MSA(FFINT_S,  trans_msa_2rf, gen_helper_msa_ffint_s_df);
 TRANS_MSA(FFINT_U,  trans_msa_2rf, gen_helper_msa_ffint_u_df);
 
-static void gen_msa_vec_v(DisasContext *ctx)
+static bool trans_msa_vec(DisasContext *ctx, arg_msa_r *a,
+  void (*gen_msa_vec)(TCGv_ptr, TCGv_i32,
+  TCGv_i32, TCGv_i32))
 {
-#define MASK_MSA_VEC(op)(MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
-uint8_t wt = (ctx->opcode >> 16) & 0x1f;
-uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-TCGv_i32 twd = tcg_const_i32(wd);
-TCGv_i32 tws = tcg_const_i32(ws);
-TCGv_i32 twt = tcg_const_i32(wt);
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);
 
-switch (MASK_MSA_VEC(ctx->opcode)) {
-case OPC_AND_V:
-gen_helper_msa_and_v(cpu_env, twd, tws, twt);
-break;
-case OPC_OR_V:
-gen_helper_msa_or_v(cpu_env, twd, tws, twt);
-break;
-case OPC_NOR_V:
-gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
-break;
-case OPC_XOR_V:
-gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
-break;
-case OPC_BMNZ_V:
-gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
-break;
-case OPC_BMZ_V:
-gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
-break;
-case OPC_BSEL_V:
-gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
-break;
-default:
-MIPS_INVAL("MSA instruction");
-gen_reserved_instruction(ctx);
-break;
-}
+gen_msa_vec(cpu_env, twd, tws, twt);
 
 tcg_temp_free_i32(twd);
 tcg_temp_free_i32(tws);
 tcg_temp_free_i32(twt);
+
+return true;
 }
 
-static void gen_msa_vec(DisasContext *ctx)
-{
-switch (MASK_MSA_VEC(ctx->opcode)) {
-case OPC_AND_V:
-case OPC_OR_V:
-case OPC_NOR_V:
-case OPC_XOR_V:
-case OPC_BMNZ_V:
-case OPC_BMZ_V:
-case OPC_BSEL_V:
-gen_msa_vec_v(ctx);
-break;
-default:
-MIPS_INVAL("MSA instruction");
-

[PATCH 08/33] target/mips: Convert MSA LDI opcode to decodetree

[Philippe Mathieu-Daudé]

Convert the LDI opcode (Immediate Load) to decodetree. Since it
overlaps with the generic MSA handler, use a decodetree overlap
group.

Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/msa.decode  |  8 +++-
 target/mips/tcg/msa_translate.c | 30 ++
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index aa784cf12a9..86aa66f05b9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -14,10 +14,12 @@
   rs rt rd sa
 
 _bz df   wt sa
+_ldst   df wd wssa
 
 @lsa.. rs:5 rt:5 rd:5 ... sa:2 ..   
 @bz_v   .. ... ..wt:5 sa:16 _bz df=3
 @bz .. ...  df:2 wt:5 sa:16 _bz
+@ldi.. ... df:2 sa:s10 wd:5 ..  _ldst ws=0
 
 LSA 00 . . . 000 .. 000101  @lsa
 DLSA00 . . . 000 .. 010101  @lsa
@@ -27,4 +29,8 @@ BNZ_V   010001 0  . 
@bz_v
 BZ  010001 110 .. . @bz
 BNZ 010001 111 .. . @bz
 
-MSA 00 --
+{
+  LDI   00 110 .. ..  . 000111  @ldi
+
+  MSA   00 --
+}
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c2a48aecc46..3b0dfcca69d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -70,7 +70,6 @@ enum {
 OPC_CLEI_S_df   = (0x4 << 23) | OPC_MSA_I5_07,
 OPC_MINI_U_df   = (0x5 << 23) | OPC_MSA_I5_06,
 OPC_CLEI_U_df   = (0x5 << 23) | OPC_MSA_I5_07,
-OPC_LDI_df  = (0x6 << 23) | OPC_MSA_I5_07,
 
 /* I8 instruction */
 OPC_ANDI_B  = (0x0 << 24) | OPC_MSA_I8_00,
@@ -525,13 +524,6 @@ static void gen_msa_i5(DisasContext *ctx)
 case OPC_CLEI_U_df:
 gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
 break;
-case OPC_LDI_df:
-{
-int32_t s10 = sextract32(ctx->opcode, 11, 10);
-tcg_gen_movi_i32(timm, s10);
-gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
-}
-break;
 default:
 MIPS_INVAL("MSA instruction");
 gen_reserved_instruction(ctx);
@@ -544,6 +536,28 @@ static void gen_msa_i5(DisasContext *ctx)
 tcg_temp_free_i32(timm);
 }
 
+static bool trans_LDI(DisasContext *ctx, arg_msa_ldst *a)
+{
+TCGv_i32 tdf;
+TCGv_i32 twd;
+TCGv_i32 timm;
+
+if (!check_msa_access(ctx)) {
+return false;
+}
+
+tdf = tcg_constant_i32(a->df);
+twd = tcg_const_i32(a->wd);
+timm = tcg_const_i32(a->sa);
+
+gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
+
+tcg_temp_free_i32(twd);
+tcg_temp_free_i32(timm);
+
+return true;
+}
+
 static void gen_msa_bit(DisasContext *ctx)
 {
 #define MASK_MSA_BIT(op)(MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-- 
2.31.1

[PATCH 04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation

[Philippe Mathieu-Daudé]

The following commits added various user-mode tests
for various MSA instructions:

 - 0fdd986a6c8 ("Add tests for MSA integer add instructions")
 - 1be82d89011 ("Add tests for MSA integer average instructions")
 - 1d336c87a3c ("Add tests for MSA bit set instructions")
 - 1e6bea794c8 ("Add tests for MSA integer max/min instructions")
 - 2a367db039f ("Add tests for MSA pack instructions")
 - 3d9569b8550 ("Add tests for MSA move instructions")
 - 4b302ce90db ("Add tests for MSA integer multiply instructions")
 - 520e210c0aa ("Add tests for MSA integer compare instructions")
 - 53e116fed6d ("Add tests for MSA integer subtract instructions")
 - 666952ea7c1 ("Add tests for MSA bit move instructions")
 - 72f463bc080 ("Add tests for MSA integer divide instructions")
 - 8598f5fac1c ("Add tests for MSA FP max/min instructions")
 - 99d423e576a ("Add tests for MSA shift instructions")
 - a8f91dd9fd0 ("Add tests for MSA integer dot product instructions")
 - b62592ab655 ("Add tests for MSA bit counting instructions")
 - ba632924450 ("Add tests for MSA logic instructions")
 - fc76f486677 ("Add tests for MSA interleave instructions")

Cover them in the buildsys machinery so they are run automatically
when calling 'make check-tcg'.

Start running them on the mips64el target.

Cc: Alex Bennée 
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/tcg/mips/ase-msa.mak | 30 ++
 MAINTAINERS|  1 +
 tests/tcg/mips/Makefile.target |  5 +
 tests/tcg/mips64/Makefile.target   |  9 +
 tests/tcg/mips64el/Makefile.target | 12 
 tests/tcg/mipsel/Makefile.target   |  9 +
 6 files changed, 66 insertions(+)
 create mode 100644 tests/tcg/mips/ase-msa.mak
 create mode 100644 tests/tcg/mips64/Makefile.target
 create mode 100644 tests/tcg/mips64el/Makefile.target
 create mode 100644 tests/tcg/mipsel/Makefile.target

diff --git a/tests/tcg/mips/ase-msa.mak b/tests/tcg/mips/ase-msa.mak
new file mode 100644
index 000..be1ba967a5b
--- /dev/null
+++ b/tests/tcg/mips/ase-msa.mak
@@ -0,0 +1,30 @@
+# -*- Mode: makefile -*-
+#
+# MIPS MSA specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé 
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+MSA_DIR = $(SRC_PATH)/tests/tcg/mips/user/ase/msa
+
+MSA_TEST_CLASS = bit-count bit-move bit-set fixed-multiply \
+   float-max-min int-add int-average int-compare 
int-divide \
+   int-dot-product interleave int-max-min 
int-modulo \
+   int-multiply int-subtract logic move pack shift
+
+MSA_TEST_SRCS = $(foreach class,$(MSA_TEST_CLASS),$(wildcard 
$(MSA_DIR)/$(class)/*.c))
+
+MSA_TESTS = $(patsubst %.c,%,$(notdir $(MSA_TEST_SRCS)))
+
+$(MSA_TESTS): CFLAGS+=-mmsa $(MSA_CFLAGS)
+$(MSA_TESTS): %: $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard 
$(MSA_DIR)/$(CLASS)/%.c))
+   $(CC) -static $(CFLAGS) -o $@ \
+   $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard 
$(MSA_DIR)/$(CLASS)/$@.c))
+
+$(foreach test,$(MSA_TESTS),run-$(test)): QEMU_OPTS += -cpu $(MSA_CPU)
+
+# FIXME: These tests fail when using plugins
+ifneq ($(CONFIG_PLUGIN),y)
+TESTS += $(MSA_TESTS)
+endif
diff --git a/MAINTAINERS b/MAINTAINERS
index 4e77d03651b..53c6c549b80 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3111,6 +3111,7 @@ R: Jiaxun Yang 
 R: Aleksandar Rikalo 
 S: Odd Fixes
 F: tcg/mips/
+F: tests/tcg/mips*
 
 PPC TCG target
 M: Richard Henderson 
diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target
index 1a994d5525e..191fe179119 100644
--- a/tests/tcg/mips/Makefile.target
+++ b/tests/tcg/mips/Makefile.target
@@ -17,3 +17,8 @@ TESTS += $(MIPS_TESTS)
 hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -mabi=32
 hello-mips: LDFLAGS+=-nostdlib
 endif
+
+# FIXME enable MSA tests
+#MSA_CFLAGS=-march=mips64r5 -mnan=2008
+#MSA_CPU=P5600
+#include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target
new file mode 100644
index 000..d876b92f219
--- /dev/null
+++ b/tests/tcg/mips64/Makefile.target
@@ -0,0 +1,9 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé 
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# 64-bit MSA is tested on little-endian target
diff --git a/tests/tcg/mips64el/Makefile.target 
b/tests/tcg/mips64el/Makefile.target
new file mode 100644
index 000..87c0d6dce18
--- /dev/null
+++ b/tests/tcg/mips64el/Makefile.target
@@ -0,0 +1,12 @@
+# -*- Mode: makefile -*-
+#
+# mips64el specific TCG tests
+#
+# Copyright (c) 2021 Philippe Mathieu-Daudé 
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MSA
+MSA_CFLAGS=-march=mips64r5 -mnan=legacy
+MSA_CPU=Loongson-3A4000
+include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak
diff --git a/tests/tcg/mipsel/Makefile.target b/tests/tcg/mipsel/Makefile.target
new file mode 100644
index 000..c8acacb4497
--- /dev/null
+++ 

[PATCH 01/33] tests/tcg: Fix some targets default cross compiler path

[Philippe Mathieu-Daudé]

We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.

Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/tcg/configure.sh | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 1f985ccfc0c..b8574165fa6 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -46,7 +46,7 @@ fi
 : ${cross_cc_aarch64="aarch64-linux-gnu-gcc"}
 : ${cross_cc_aarch64_be="$cross_cc_aarch64"}
 : ${cross_cc_cflags_aarch64_be="-mbig-endian"}
-: $(cross_cc_alpha="alpha-linux-gnu-gcc")
+: ${cross_cc_alpha="alpha-linux-gnu-gcc"}
 : ${cross_cc_arm="arm-linux-gnueabihf-gcc"}
 : ${cross_cc_cflags_armeb="-mbig-endian"}
 : ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"}
@@ -55,17 +55,17 @@ fi
 : ${cross_cc_i386="i686-linux-gnu-gcc"}
 : ${cross_cc_cflags_i386="-m32"}
 : ${cross_cc_m68k="m68k-linux-gnu-gcc"}
-: $(cross_cc_mips64el="mips64el-linux-gnuabi64-gcc")
-: $(cross_cc_mips64="mips64-linux-gnuabi64-gcc")
-: $(cross_cc_mipsel="mipsel-linux-gnu-gcc")
-: $(cross_cc_mips="mips-linux-gnu-gcc")
+: ${cross_cc_mips64el="mips64el-linux-gnuabi64-gcc"}
+: ${cross_cc_mips64="mips64-linux-gnuabi64-gcc"}
+: ${cross_cc_mipsel="mipsel-linux-gnu-gcc"}
+: ${cross_cc_mips="mips-linux-gnu-gcc"}
 : ${cross_cc_ppc="powerpc-linux-gnu-gcc"}
 : ${cross_cc_cflags_ppc="-m32"}
 : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"}
 : ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"}
-: $(cross_cc_riscv64="riscv64-linux-gnu-gcc")
+: ${cross_cc_riscv64="riscv64-linux-gnu-gcc"}
 : ${cross_cc_s390x="s390x-linux-gnu-gcc"}
-: $(cross_cc_sh4="sh4-linux-gnu-gcc")
+: ${cross_cc_sh4="sh4-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultrasparc"}
 : ${cross_cc_sparc64="sparc64-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"}
-- 
2.31.1

[PATCH 00/33] target/mips: Fully convert MSA opcodes to decodetree

[Philippe Mathieu-Daudé]

Hi,

This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).

Massive convertions are - beside being often boring - bug-prone.
In this series we re-start running the MSA tests (the tests are
run automagically in the 'build-user-static' job on gitlab CI).

Although boring, the conversion is very clean, so I hope it will
be easy enough to review. The TRANS*() macros are heavily used.

When possible, constant fields are hold with tcg_constant().

Note, various opcodes can be optimized using TCG host vectors.
We won't address that in this series, as it makes the resulting
review harder. We will post that in a following series. Here we
simply dummy-convert.

The resulting msa.decode file is quite pleasant to look at, and
the diff-stat is encouraging: number of LoC halved.

Regards,

Phil.

git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
Based-on: <20211023164329.328137-1-f4...@amsat.org>

Philippe Mathieu-Daudé (33):
  tests/tcg: Fix some targets default cross compiler path
  target/mips: Fix MSA MADDV.B opcode
  target/mips: Fix MSA MSUBV.B opcode
  tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
  target/mips: Have check_msa_access() return a boolean
  target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
  target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
  target/mips: Convert MSA LDI opcode to decodetree
  target/mips: Introduce generic TRANS_CHECK() for decodetree helpers
  target/mips: Extract df_extract() helper
  target/mips: Convert MSA I5 instruction format to decodetree
  target/mips: Convert MSA BIT instruction format to decodetree
  target/mips: Convert MSA SHF opcode to decodetree
  target/mips: Convert MSA I8 instruction format to decodetree
  target/mips: Convert MSA load/store instruction format to decodetree
  target/mips: Convert MSA 2RF instruction format to decodetree
  target/mips: Convert MSA FILL opcode to decodetree
  target/mips: Convert MSA 2R instruction format to decodetree
  target/mips: Convert MSA VEC instruction format to decodetree
  target/mips: Convert MSA 3RF instruction format to decodetree
(DF_HALF)
  target/mips: Convert MSA 3RF instruction format to decodetree
(DF_WORD)
  target/mips: Convert MSA 3R instruction format to decodetree (part
1/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part
2/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part
3/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part
4/4)
  target/mips: Convert MSA ELM instruction format to decodetree
  target/mips: Convert MSA COPY_U opcode to decodetree
  target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
  target/mips: Convert MSA MOVE.V opcode to decodetree
  target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree
  target/mips: Remove generic MSA opcode
  target/mips: Remove one MSA unnecessary decodetree overlap group
  target/mips: Adjust style in msa_translate_init()

 tests/tcg/mips/ase-msa.mak |   30 +
 target/mips/tcg/translate.h|9 +
 target/mips/tcg/msa.decode |  231 ++-
 target/mips/tcg/msa_helper.c   |   64 +-
 target/mips/tcg/msa_translate.c| 2781 +++-
 MAINTAINERS|1 +
 tests/tcg/configure.sh |   14 +-
 tests/tcg/mips/Makefile.target |5 +
 tests/tcg/mips64/Makefile.target   |9 +
 tests/tcg/mips64el/Makefile.target |   12 +
 tests/tcg/mipsel/Makefile.target   |9 +
 11 files changed, 1052 insertions(+), 2113 deletions(-)
 create mode 100644 tests/tcg/mips/ase-msa.mak
 create mode 100644 tests/tcg/mips64/Makefile.target
 create mode 100644 tests/tcg/mips64el/Makefile.target
 create mode 100644 tests/tcg/mipsel/Makefile.target

-- 
2.31.1

Re: [PATCH 33/33] target/ppc: Implement lxvkq instruction

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

+static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
+{
+static const uint32_t valid_values = 0b00010010;


All of the specified values are non-zero, so this kinda duplicates the values table. 
Otherwise,


Reviewed-by: Richard Henderson 

r~



+static const uint64_t values[32] = {
+0, /* Unspecified */
+0x3FFFllu, /* QP +1.0 */
+0x4000llu, /* QP +2.0 */
+0x40008000llu, /* QP +3.0 */
+0x4001llu, /* QP +4.0 */
+0x40014000llu, /* QP +5.0 */
+0x40018000llu, /* QP +6.0 */
+0x4001C000llu, /* QP +7.0 */
+0x7FFFllu, /* QP +Inf */
+0x7FFF8000llu, /* QP dQNaN */
+0, /* Unspecified */
+0, /* Unspecified */
+0, /* Unspecified */
+0, /* Unspecified */
+0, /* Unspecified */
+0, /* Unspecified */
+0x8000llu, /* QP -0.0 */
+0xBFFFllu, /* QP -1.0 */
+0xC000llu, /* QP -2.0 */
+0xC0008000llu, /* QP -3.0 */
+0xC001llu, /* QP -4.0 */
+0xC0014000llu, /* QP -5.0 */
+0xC0018000llu, /* QP -6.0 */
+0xC001C000llu, /* QP -7.0 */
+0xllu, /* QP -Inf */
+};

Re: [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: Matheus Ferst

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
  target/ppc/helper.h |  4 +++
  target/ppc/insn64.decode| 19 ++
  target/ppc/int_helper.c | 15 
  target/ppc/translate/vsx-impl.c.inc | 55 +
  4 files changed, 93 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)"

Implemented the instruction XXSPLTIDP using decodetree.

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn64.decode|  2 ++
  target/ppc/translate/vsx-impl.c.inc | 10 ++
  2 files changed, 12 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)"

Implemented the XXSPLTIW instruction, using decodetree.

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn64.decode|  6 ++
  target/ppc/translate/vsx-impl.c.inc | 10 ++
  2 files changed, 16 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 29/33] target/ppc: implemented XXSPLTI32DX

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)" 

Implemented XXSPLTI32DX emulation using decodetree

Signed-off-by: Bruno Larsen (billionai) 
Signed-off-by: Matheus Ferst 
---
  target/ppc/insn64.decode| 11 
  target/ppc/translate/vsx-impl.c.inc | 41 +
  2 files changed, 52 insertions(+)

diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3edc7..8d8d5d5729 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@
  .. . ra:5    \
  _D si=%pls_si rt=%rt_tsxp
  
+# Format 8RR:D

+%8rr_si 32:s16 0:16
+%8rr_xt 16:1 21:5
+&8RR_D_IX   xt ix si:int32_t


What is it about this field that says signed, expecially?  It doesn't seem wrong, of 
course, but you are jumping through extra hoops here...



+get_cpu_vsrh(t0, a->xt);
+get_cpu_vsrl(t1, a->xt);
+
+tcg_gen_movi_i64(new_val, a->si);
+if (a->ix) {
+tcg_gen_movi_i64(mask, 0x);
+tcg_gen_shli_i64(new_val, new_val, 32);
+} else {
+tcg_gen_movi_i64(mask, 0x);
+}
+tcg_gen_and_i64(t0, t0, mask);
+tcg_gen_or_i64(t0, t0, new_val);
+tcg_gen_and_i64(t1, t1, mask);
+tcg_gen_or_i64(t1, t1, new_val);
+
+set_cpu_vsrh(a->xt, t0);
+set_cpu_vsrl(a->xt, t1);


You're working too hard here.  I think you should just store the two int32_t at the 
correct offsets.  And failing that, use tcg_gen_deposit_i64.



r~

Re: [PATCH 28/33] target/ppc: moved XXSPLTIB to using decodetree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)"

Changed the function that handles XXSPLTIB emulation to using
decodetree, but still use the same logic as before

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn32.decode|  5 +
  target/ppc/translate/vsx-impl.c.inc | 20 ++--
  target/ppc/translate/vsx-ops.c.inc  |  1 -
  3 files changed, 11 insertions(+), 15 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)"

Changed the function that handles XXSPLTW emulation to using decodetree,
but still using the same logic.

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn32.decode|  9 +
  target/ppc/translate/vsx-impl.c.inc | 17 ++---
  target/ppc/translate/vsx-ops.c.inc  |  1 -
  3 files changed, 15 insertions(+), 12 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Lucas Mateus Castro (alqotel)"

Implemented the instructions plxvp and pstxvp using decodetree

Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn64.decode| 9 +
  target/ppc/translate/vsx-impl.c.inc | 2 ++
  2 files changed, 11 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Lucas Mateus Castro (alqotel)"

Implemented the instructions plxv and pstxv using decodetree

Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn64.decode| 10 ++
  target/ppc/translate/vsx-impl.c.inc | 16 
  2 files changed, 26 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Lucas Mateus Castro (alqotel)"

Implemented the instructions lxvpx and stxvpx using decodetree

Signed-off-by: Lucas Mateus Castro (alqotel)
Signed-off-by: Matheus Ferst
---
  target/ppc/insn32.decode|  3 +++
  target/ppc/translate/vsx-impl.c.inc | 18 --
  2 files changed, 15 insertions(+), 6 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

  if (ctx->le_mode) {
-gen_addr_add(ctx, ea, ea, 8);
+gen_addr_add(ctx, ea, ea, paired ? 24 : 8);


Still questioning the address of the fault, but the rest of it looks ok.


r~

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

+if (ctx->le_mode) {
+gen_addr_add(ctx, ea, ea, 8);
+offset = -8;
+} else {
+offset = 8;
+}
+
+if (store) {
+get_cpu_vsrh(xt, rt);
+tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+gen_addr_add(ctx, ea, ea, offset);
+get_cpu_vsrl(xt, rt);
+tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+} else {
+tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+set_cpu_vsrh(rt, xt);
+gen_addr_add(ctx, ea, ea, offset);
+tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+set_cpu_vsrl(rt, xt);
+}


Actually, I'm going to reverse myself again.

This has a behaviour change: for LE, the first access is to EA+8 instead of EA.  Thus the 
SIGSEGV for a load from NULL will report address 8 not 0, which is probably not the 
correct result.



r~

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

[Richard Henderson]

On 10/23/21 1:34 PM, Richard Henderson wrote:

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+ int rt, bool store)


You need an int64_t displ before you add PLXV et al.  What happened to passing in arg_D as 
for the other integer instructions?



+    do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
+
+    if (ctx->le_mode) {
+    gen_addr_add(ctx, ea, ea, 8);
+    offset = -8;
+    } else {
+    offset = 8;
+    }


Adjust displ for le_mode, then you don't have to do the addition twice.


Nevermind, next patch fixes this one.
Fold the 3 lines back for a

Reviewed-by: Richard Henderson 

r~

Re: [PATCH 22/33] target/ppc: moved stxvx and lxvx from legacy to decodtree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

@@ -2075,7 +1969,7 @@ static void gen_xvxsigdp(DisasContext *ctx)
  tcg_temp_free_i64(xbl);
  }
  
-static bool do_lstxv(DisasContext *ctx, int ra, int displ,

+static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
   int rt, bool store)
  {
  TCGv ea;
@@ -2089,7 +1983,7 @@ static bool do_lstxv(DisasContext *ctx, int ra, int displ,
  mop = DEF_MEMOP(MO_Q);
  
  gen_set_access_type(ctx, ACCESS_INT);

-do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
+do_ea_calc(ctx, ra, displ, ea);
  
  if (ctx->le_mode) {

  gen_addr_add(ctx, ea, ea, 8);
@@ -2127,11 +2021,26 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, 
bool store)
  REQUIRE_VECTOR(ctx);
  }
  
-return do_lstxv(ctx, a->ra, a->si, a->rt, store);

+return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);


Ah, if these 3 lines had been in the previous patch, I wouldn't have been asking silly 
questions.  :-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+ int rt, bool store)


You need an int64_t displ before you add PLXV et al.  What happened to passing in arg_D as 
for the other integer instructions?



+do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
+
+if (ctx->le_mode) {
+gen_addr_add(ctx, ea, ea, 8);
+offset = -8;
+} else {
+offset = 8;
+}


Adjust displ for le_mode, then you don't have to do the addition twice.


r~

Re: [RESEND PATCH 2/2] hw/i386: Rename default_bus_bypass_iommu

[Michael S. Tsirkin]

On Fri, Oct 22, 2021 at 03:58:28PM +0100, Jean-Philippe Brucker wrote:
> On Fri, Oct 22, 2021 at 10:46:08AM -0400, Michael S. Tsirkin wrote:
> > On Wed, Oct 13, 2021 at 05:06:08PM +0100, Jean-Philippe Brucker wrote:
> > > Since commit d8fb7d0969d5 ("vl: switch -M parsing to keyval"), machine
> > > parameter definitions cannot use underscores, because keyval_dashify()
> > > transforms them to dashes and the parser doesn't find the parameter.
> > > 
> > > This affects option default_bus_bypass_iommu which was introduced in the
> > > same release:
> > > 
> > > $ qemu-system-x86_64 -M q35,default_bus_bypass_iommu=on
> > > qemu-system-x86_64: Property 
> > > 'pc-q35-6.1-machine.default-bus-bypass-iommu' not found
> > > 
> > > Rename the parameter to "default-bus-bypass-iommu". Passing
> > > "default_bus_bypass_iommu" is still valid since the underscore are
> > > transformed automatically.
> > > 
> > > Fixes: c9e96b04fc19 ("hw/i386: Add a default_bus_bypass_iommu pc machine 
> > > option")
> > > Reviewed-by: Eric Auger 
> > > Tested-by: Eric Auger 
> > > Signed-off-by: Jean-Philippe Brucker 
> > 
> > I can merge this one but I think it's independent of the
> > ARM patch, right? So just two independent patches.
> 
> Yes they are independent
> 
> Thanks,
> Jean

Ok just post them separately pls then.

> > 
> > > ---
> > >  hw/i386/pc.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > > index 86223acfd3..54e4c00dce 100644
> > > --- a/hw/i386/pc.c
> > > +++ b/hw/i386/pc.c
> > > @@ -1718,7 +1718,7 @@ static void pc_machine_class_init(ObjectClass *oc, 
> > > void *data)
> > >  object_class_property_add_bool(oc, "hpet",
> > >  pc_machine_get_hpet, pc_machine_set_hpet);
> > >  
> > > -object_class_property_add_bool(oc, "default_bus_bypass_iommu",
> > > +object_class_property_add_bool(oc, "default-bus-bypass-iommu",
> > >  pc_machine_get_default_bus_bypass_iommu,
> > >  pc_machine_set_default_bus_bypass_iommu);
> > >  
> > > -- 
> > > 2.33.0
> > 

Re: [PATCH v8 07/10] ACPI ERST: create ACPI ERST table for pc/x86 machines

[Michael S. Tsirkin]

On Sat, Oct 23, 2021 at 07:52:21AM +0530, Ani Sinha wrote:
> 
> 
> On Fri, 22 Oct 2021, Eric DeVolder wrote:
> 
> > Ani, inline below.
> > eric
> >
> > On 10/22/21 05:18, Ani Sinha wrote:
> > >
> > >
> > > On Fri, 15 Oct 2021, Eric DeVolder wrote:
> > >
> > > > This change exposes ACPI ERST support for x86 guests.
> > > >
> > > > Signed-off-by: Eric DeVolder 
> > > > ---
> > > >   hw/i386/acpi-build.c   | 9 +
> > > >   hw/i386/acpi-microvm.c | 9 +
> > > >   include/hw/acpi/erst.h | 5 +
> > > >   3 files changed, 23 insertions(+)
> > > >
> > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > index 81418b7..9c2f9d9 100644
> > > > --- a/hw/i386/acpi-build.c
> > > > +++ b/hw/i386/acpi-build.c
> > > > @@ -43,6 +43,7 @@
> > > >   #include "sysemu/tpm.h"
> > > >   #include "hw/acpi/tpm.h"
> > > >   #include "hw/acpi/vmgenid.h"
> > > > +#include "hw/acpi/erst.h"
> > > >   #include "sysemu/tpm_backend.h"
> > > >   #include "hw/rtc/mc146818rtc_regs.h"
> > > >   #include "migration/vmstate.h"
> > > > @@ -2499,6 +2500,7 @@ void acpi_build(AcpiBuildTables *tables,
> > > > MachineState *machine)
> > > >   GArray *tables_blob = tables->table_data;
> > > >   AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
> > > >   Object *vmgenid_dev;
> > > > +Object *erst_dev;
> > > >   char *oem_id;
> > > >   char *oem_table_id;
> > > >
> > > > @@ -2560,6 +2562,13 @@ void acpi_build(AcpiBuildTables *tables,
> > > > MachineState *machine)
> > > >   ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
> > > >   x86ms->oem_table_id);
> > > >
> > > > +erst_dev = find_erst_dev();
> > > > +if (erst_dev) {
> > > > +acpi_add_table(table_offsets, tables_blob);
> > > > +build_erst(tables_blob, tables->linker, erst_dev,
> > > > +   x86ms->oem_id, x86ms->oem_table_id);
> > > > +}
> > > > +
> > >
> > > This needs to be ifdef'd between CONFIG_ERST.
> > ok
> >
> > >
> > >
> > > >   vmgenid_dev = find_vmgenid_dev();
> > > >   if (vmgenid_dev) {
> > > >   acpi_add_table(table_offsets, tables_blob);
> > > > diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
> > >
> > > I do not think we need to include this for microvm machines. They are
> > > supposed to have minimal ACPUI support. So lets not bloat it unless there
> > > is a specific requirement to support ERST on microvms as well.
> > Would it be ok if I ifdef this on CONFIG_ERST also?
> 
> I think we should not touch microvm machine unless you can justify why you
> need ERST support there.

OTOH why not? No idea... CC microvm maintainers and let them decide.

> >
> > >
> > >
> > > > index 196d318..662c8ad 100644
> > > > --- a/hw/i386/acpi-microvm.c
> > > > +++ b/hw/i386/acpi-microvm.c
> > > > @@ -30,6 +30,7 @@
> > > >   #include "hw/acpi/bios-linker-loader.h"
> > > >   #include "hw/acpi/generic_event_device.h"
> > > >   #include "hw/acpi/utils.h"
> > > > +#include "hw/acpi/erst.h"
> > > >   #include "hw/i386/fw_cfg.h"
> > > >   #include "hw/i386/microvm.h"
> > > >   #include "hw/pci/pci.h"
> > > > @@ -158,6 +159,7 @@ static void acpi_build_microvm(AcpiBuildTables
> > > > *tables,
> > > >   X86MachineState *x86ms = X86_MACHINE(mms);
> > > >   GArray *table_offsets;
> > > >   GArray *tables_blob = tables->table_data;
> > > > +Object *erst_dev;
> > > >   unsigned dsdt, xsdt;
> > > >   AcpiFadtData pmfadt = {
> > > >   /* ACPI 5.0: 4.1 Hardware-Reduced ACPI */
> > > > @@ -207,6 +209,13 @@ static void acpi_build_microvm(AcpiBuildTables
> > > > *tables,
> > > >   ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
> > > >   x86ms->oem_table_id);
> > > >
> > > > +erst_dev = find_erst_dev();
> > > > +if (erst_dev) {
> > > > +acpi_add_table(table_offsets, tables_blob);
> > > > +build_erst(tables_blob, tables->linker, erst_dev,
> > > > +   x86ms->oem_id, x86ms->oem_table_id);
> > > > +}
> > > > +
> > >
> > >
> > >
> > > >   xsdt = tables_blob->len;
> > > >   build_xsdt(tables_blob, tables->linker, table_offsets,
> > > > x86ms->oem_id,
> > > >  x86ms->oem_table_id);
> > > > diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h
> > > > index 9d63717..b747fe7 100644
> > > > --- a/include/hw/acpi/erst.h
> > > > +++ b/include/hw/acpi/erst.h
> > > > @@ -16,4 +16,9 @@ void build_erst(GArray *table_data, BIOSLinker 
> > > > *linker,
> > > > Object *erst_dev,
> > > >
> > > >   #define TYPE_ACPI_ERST "acpi-erst"
> > > >
> > > > +/* returns NULL unless there is exactly one device */
> > > > +static inline Object *find_erst_dev(void)
> > > > +{
> > > > +return object_resolve_path_type("", TYPE_ACPI_ERST, NULL);
> > > > +}
> > > >   #endif
> > > > --
> > > > 1.8.3.1
> > > >
> > > >
> >

Re: [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: "Bruno Larsen (billionai)"

Introduce the macro to centralize checking if the VSX facility is
enabled and handle it correctly.

Signed-off-by: Bruno Larsen (billionai)
Signed-off-by: Luis Pires
Signed-off-by: Matheus Ferst
---
  target/ppc/translate.c | 8 
  1 file changed, 8 insertions(+)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

[Richard Henderson]

On 10/23/21 1:02 PM, BALATON Zoltan wrote:
So may question was not if it's possible but if having target_ulong different from what we 
had in qemu-system-ppc could cause any problems? I have no experience running 32-bit 
guests with qemu-system-ppc64 but previously when this came up one difference pointed out 
was that target_ulong would change if I remember the discussion correctly, but nobody now 
if that could be a problem.


It shouldn't be a problem.  We take care of NARROW_MODE, so that you can boot a ppc64 
guest kernel, and then run ppc32 user binaries under that.


If you do find a bug under those conditions, report it.

r~

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

[BALATON Zoltan]

On Sat, 23 Oct 2021, Richard Henderson wrote:

On 10/23/21 3:12 AM, BALATON Zoltan wrote:
You mentioning target_ulong reminded me a question I had. Currently we have 
qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines 
of the former too so you could run for example sam460ex with 
qemu-system-ppc64 (except mac99 which behaves differently based on which 
executable it's part of but you could use mac99 -cpu G4 with 
qemu-system-ppc64 as well). But isn't target_ulong different in these 
executables and could that cause a problem with this? I've always used 
qemu-system-ppc for 32 bit machines but we could have one just executable 
for all machines if there's no need for both.


Yes, we can, and probably should, have one executable for all PPC system 
emulation.  RISCV is actively working toward that, and I think it would be 
fairly easy for ARM and x86 to follow.


It's something relatively easy to do that reduces the size of the test 
matrix.


So may question was not if it's possible but if having target_ulong 
different from what we had in qemu-system-ppc could cause any problems? I 
have no experience running 32-bit guests with qemu-system-ppc64 but 
previously when this came up one difference pointed out was that 
target_ulong would change if I remember the discussion correctly, but 
nobody now if that could be a problem.


Regards,
BALATON Zoltan

Re: [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns

[Richard Henderson]

On 10/21/21 12:45 PM, matheus.fe...@eldorado.org.br wrote:

From: Matheus Ferst 

Implement the following PowerISA v3.1 instructions:
vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
 GPR-specified Left-Index
vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
 GPR-specified Left-Index
vextduwvlx: Vector Extract Double Unsigned Word to VSR using
 GPR-specified Left-Index
vextddvlx: Vector Extract Double Unsigned Doubleword to VSR using
GPR-specified Left-Index
vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
 GPR-specified Right-Index
vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
 GPR-specified Right-Index
vextduwvrx: Vector Extract Double Unsigned Word to VSR using
 GPR-specified Right-Index
vextddvrx: Vector Extract Double Unsigned Doubleword to VSR using
GPR-specified Right-Index

Signed-off-by: Luis Pires 
Signed-off-by: Matheus Ferst 
---
  target/ppc/helper.h |  4 +++
  target/ppc/insn32.decode| 12 +
  target/ppc/int_helper.c | 41 -
  target/ppc/translate/vmx-impl.c.inc | 37 ++
  4 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 53c65ca1c7..ac8ab7e436 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -336,6 +336,10 @@ DEF_HELPER_2(vextuwlx, tl, tl, avr)
  DEF_HELPER_2(vextubrx, tl, tl, avr)
  DEF_HELPER_2(vextuhrx, tl, tl, avr)
  DEF_HELPER_2(vextuwrx, tl, tl, avr)
+DEF_HELPER_5(VEXTDUBVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUHVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUWVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDDVLX, void, env, avr, avr, avr, tl)
  
  DEF_HELPER_2(vsbox, void, avr, avr)

  DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2eb7fb4e92..e438177b32 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
  %dx_d   6:s10 16:5 0:1
  @DX .. rt:5  . .. . .d=%dx_d
  
+ vrt vra vrb rc

+@VA .. vrt:5 vra:5 vrb:5 rc:5 ..
+
   vrt vra vrb sh
  @VN .. vrt:5 vra:5 vrb:5 .. sh:3 .. 
  
@@ -347,6 +350,15 @@ VPEXTD  000100 . . . 10110001101@VX
  
  ## Vector Permute and Formatting Instruction
  
+VEXTDUBVLX  000100 . . . . 011000   @VA

+VEXTDUBVRX  000100 . . . . 011001   @VA
+VEXTDUHVLX  000100 . . . . 011010   @VA
+VEXTDUHVRX  000100 . . . . 011011   @VA
+VEXTDUWVLX  000100 . . . . 011100   @VA
+VEXTDUWVRX  000100 . . . . 011101   @VA
+VEXTDDVLX   000100 . . . . 00   @VA
+VEXTDDVRX   000100 . . . . 01   @VA
+
  VINSERTB000100 . -  . 0111101   @VX_uim4
  VINSERTH000100 . -  . 01101001101   @VX_uim4
  VINSERTW000100 . -  . 01110001101   @VX_uim4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 5a925a564d..1577ea8788 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1673,8 +1673,47 @@ VINSX(B, uint8_t)
  VINSX(H, uint16_t)
  VINSX(W, uint32_t)
  VINSX(D, uint64_t)
-#undef ELEM_ADDR
  #undef VINSX
+#define VEXTDVLX(NAME, TYPE) \
+void glue(glue(helper_VEXTD, NAME), VLX)(CPUPPCState *env, ppc_avr_t *t,   
\
+ ppc_avr_t *a, ppc_avr_t *b,   
\
+ target_ulong index)   
\
+{  
\
+const int array_size = ARRAY_SIZE(t->u8), elem_size = sizeof(TYPE);
\
+const target_long idx = index; 
\
+   
\
+if (idx < 0) { 
\
+qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VEXTD" #NAME "VRX 
at"\
+" 0x" TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", env->nip,   
\
+32 - elem_size - idx, 32 - elem_size); 
\
+} else if (idx + elem_size <= array_size) {
\
+t->VsrD(0) = *(TYPE *)ELEM_ADDR(a, idx, elem_size);
\


You need an unaligned load here.


+t->VsrD(1) = 0;
\
+} else if (idx < array_size) { 
\
+ppc_avr_t tmp = { .u64 = { 0, 0 } };   
\
+const int len_a = array_size - idx, len_b = elem_size - len_a;   

[PATCH] linux-user/signal: Map exit signals in SIGCHLD siginfo_t

[Matthias Schiffer]

When converting a siginfo_t from waitid(), the interpretation of si_status
depends on the value of si_code: For CLD_EXITED, it is an exit code and
should be copied verbatim. For other codes, it is a signal number
(possibly with additional high bits from ptrace) that should be mapped.

This code was previously changed in commit 1c3dfb506ea3
("linux-user/signal: Decode waitid si_code"), but the fix was
incomplete.

Tested with the following test program:

#include 
#include 
#include 
#include 

int main() {
pid_t pid = fork();
if (pid == 0) {
exit(12);
} else {
siginfo_t siginfo = {};
waitid(P_PID, pid, , WEXITED);
printf("Code: %d, status: %d\n", (int)siginfo.si_code, 
(int)siginfo.si_status);
}

pid = fork();
if (pid == 0) {
raise(SIGUSR2);
} else {
siginfo_t siginfo = {};
waitid(P_PID, pid, , WEXITED);
printf("Code: %d, status: %d\n", (int)siginfo.si_code, 
(int)siginfo.si_status);
}
}

Output with an x86_64 host and mips64el target before 1c3dfb506ea3
(incorrect: exit code 12 is translated like a signal):

Code: 1, status: 17
Code: 2, status: 17

After 1c3dfb506ea3 (incorrect: signal number is not translated):

Code: 1, status: 12
Code: 2, status: 12

With this patch:

Code: 1, status: 12
Code: 2, status: 17

Signed-off-by: Matthias Schiffer 
---
 linux-user/signal.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index 14d8fdfde152..8e3af98ec0a7 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -403,7 +403,12 @@ static inline void 
host_to_target_siginfo_noswap(target_siginfo_t *tinfo,
 case TARGET_SIGCHLD:
 tinfo->_sifields._sigchld._pid = info->si_pid;
 tinfo->_sifields._sigchld._uid = info->si_uid;
-tinfo->_sifields._sigchld._status = info->si_status;
+if (si_code == CLD_EXITED)
+tinfo->_sifields._sigchld._status = info->si_status;
+else
+tinfo->_sifields._sigchld._status
+= host_to_target_signal(info->si_status & 0x7f)
+| (info->si_status & ~0x7f);
 tinfo->_sifields._sigchld._utime = info->si_utime;
 tinfo->_sifields._sigchld._stime = info->si_stime;
 si_type = QEMU_SI_CHLD;
-- 
2.33.1

[PULL 07/11] hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device

[Laurent Vivier]

From: Tong Ho 

Signed-off-by: Tong Ho 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Francisco Iglesias 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20211015203532.2463705-3-tong...@xilinx.com>
Signed-off-by: Laurent Vivier 
---
 hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c 
b/hw/nvram/xlnx-versal-efuse-ctrl.c
index d3623767032c..b35ba65ab57b 100644
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
@@ -439,9 +439,11 @@ static void efuse_pgm_addr_postw(RegisterInfo *reg, 
uint64_t val64)
  *   up to guest to do so (or by reset).
  */
 if (efuse_pgm_locked(s, bit)) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s: Denied setting of efuse<%u, %u, %u>\n",
-  object_get_canonical_path(OBJECT(s)),
+  path,
   FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
   FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
   FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
@@ -478,9 +480,11 @@ static void efuse_rd_addr_postw(RegisterInfo *reg, 
uint64_t val64)
 s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
   bit, );
 if (denied) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s: Denied reading of efuse<%u, %u>\n",
-  object_get_canonical_path(OBJECT(s)),
+  path,
   FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
   FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
 
@@ -625,9 +629,11 @@ static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
 s = XLNX_VERSAL_EFUSE_CTRL(dev);
 
 if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s[reg_0x%02lx]: Attempt to write locked register.\n",
-  object_get_canonical_path(OBJECT(s)), (long)addr);
+  path, (long)addr);
 } else {
 register_write_memory(opaque, addr, data, size);
 }
@@ -681,16 +687,20 @@ static void efuse_ctrl_realize(DeviceState *dev, Error 
**errp)
 const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2;
 
 if (!s->efuse) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
-   object_get_canonical_path(OBJECT(dev)));
+   path);
 return;
 }
 
 /* Sort property-defined pgm-locks for bsearch lookup */
 if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 error_setg(errp,
"%s.pg0-lock: array property item-count not multiple of %u",
-   object_get_canonical_path(OBJECT(dev)), lks_sz);
+   path, lks_sz);
 return;
 }
 
-- 
2.31.1

[PULL 08/11] hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device

[Laurent Vivier]

From: Tong Ho 

Signed-off-by: Tong Ho 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Francisco Iglesias 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20211015203532.2463705-4-tong...@xilinx.com>
Signed-off-by: Laurent Vivier 
---
 hw/nvram/xlnx-zynqmp-efuse.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
index 1f87dbf988d1..228ba0bbfaf1 100644
--- a/hw/nvram/xlnx-zynqmp-efuse.c
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
@@ -434,11 +434,12 @@ static void zynqmp_efuse_pgm_addr_postw(RegisterInfo 
*reg, uint64_t val64)
 if (!errmsg) {
 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
 } else {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s - eFuse write error: %s; addr=0x%x\n",
-  object_get_canonical_path(OBJECT(s)),
-  errmsg, (unsigned)val64);
+  path, errmsg, (unsigned)val64);
 }
 
 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
@@ -448,6 +449,7 @@ static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, 
uint64_t val64)
 static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
 {
 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
+g_autofree char *path = NULL;
 
 /*
  * Grant reads only to allowed bits; reference sources:
@@ -538,10 +540,10 @@ static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, 
uint64_t val64)
 return;
 
  denied:
+path = object_get_canonical_path(OBJECT(s));
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s: Denied efuse read from array %u, row %u\n",
-  object_get_canonical_path(OBJECT(s)),
-  efuse_ary, efuse_row);
+  path, efuse_ary, efuse_row);
 
 s->regs[R_EFUSE_RD_DATA] = 0;
 
@@ -731,9 +733,11 @@ static void zynqmp_efuse_reg_write(void *opaque, hwaddr 
addr,
 s = XLNX_ZYNQMP_EFUSE(dev);
 
 if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 qemu_log_mask(LOG_GUEST_ERROR,
   "%s[reg_0x%02lx]: Attempt to write locked register.\n",
-  object_get_canonical_path(OBJECT(s)), (long)addr);
+  path, (long)addr);
 } else {
 register_write_memory(opaque, addr, data, size);
 }
@@ -784,8 +788,10 @@ static void zynqmp_efuse_realize(DeviceState *dev, Error 
**errp)
 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
 
 if (!s->efuse) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
-   object_get_canonical_path(OBJECT(dev)));
+   path);
 return;
 }
 
-- 
2.31.1

Re: [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns

[Richard Henderson]

On 10/23/21 3:12 AM, BALATON Zoltan wrote:
You mentioning target_ulong reminded me a question I had. Currently we have 
qemu-system-ppc and qemu-system-ppc64 but the latter includes all machines of the former 
too so you could run for example sam460ex with qemu-system-ppc64 (except mac99 which 
behaves differently based on which executable it's part of but you could use mac99 -cpu G4 
with qemu-system-ppc64 as well). But isn't target_ulong different in these executables and 
could that cause a problem with this? I've always used qemu-system-ppc for 32 bit machines 
but we could have one just executable for all machines if there's no need for both.


Yes, we can, and probably should, have one executable for all PPC system emulation.  RISCV 
is actively working toward that, and I think it would be fairly easy for ARM and x86 to 
follow.


It's something relatively easy to do that reduces the size of the test matrix.


r~

[PULL 06/11] hw/nvram: Fix Memory Leak in Xilinx eFuse QOM

[Laurent Vivier]

From: Tong Ho 

Signed-off-by: Tong Ho 
Reviewed-by: Edgar E. Iglesias 
Reviewed-by: Francisco Iglesias 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20211015203532.2463705-2-tong...@xilinx.com>
Signed-off-by: Laurent Vivier 
---
 hw/nvram/xlnx-efuse.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index ee1caab54cba..a0fd77b586dc 100644
--- a/hw/nvram/xlnx-efuse.c
+++ b/hw/nvram/xlnx-efuse.c
@@ -144,10 +144,11 @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
 bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
 {
 if (efuse_ro_bits_find(s, bit)) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
   "Ignored setting of readonly efuse bit<%u,%u>!\n",
-  object_get_canonical_path(OBJECT(s)),
-  (bit / 32), (bit % 32));
+  path, (bit / 32), (bit % 32));
 return false;
 }
 
@@ -202,9 +203,11 @@ static void efuse_realize(DeviceState *dev, Error **errp)
 efuse_ro_bits_sort(s);
 
 if ((s->efuse_size % 32) != 0) {
+g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
 error_setg(errp,
"%s.efuse-size: %u: property value not multiple of 32.",
-   object_get_canonical_path(OBJECT(dev)), s->efuse_size);
+   path, s->efuse_size);
 return;
 }
 
-- 
2.31.1

[PULL 11/11] analyze-migration.py: fix extract contents ('-x') errors

[Laurent Vivier]

From: Laurent Vivier 

When we try to use 'analyze-migration.py -x' with python3,
we have the following errors:

  Traceback (most recent call last):
File "scripts/analyze-migration.py", line 593, in 
  f.write(jsonenc.encode(dump.vmsd_desc))
  TypeError: a bytes-like object is required, not 'str'

  Traceback (most recent call last):
File "scripts/analyze-migration.py", line 601, in 
  f.write(jsonenc.encode(dict))
  TypeError: a bytes-like object is required, not 'str'

This happens because the file 'f' is open in binary mode while
jsonenc.encode() returns a string.

The results are human-readable files, 'desc.json' and 'state.json',
so there is no reason to use the binary mode.

Signed-off-by: Laurent Vivier 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20211015131645.501281-3-lviv...@redhat.com>
Signed-off-by: Laurent Vivier 
---
 scripts/analyze-migration.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/scripts/analyze-migration.py b/scripts/analyze-migration.py
index 9d239d309f33..b82a1b0c58c4 100755
--- a/scripts/analyze-migration.py
+++ b/scripts/analyze-migration.py
@@ -588,7 +588,7 @@ def default(self, o):
 
 dump.read(desc_only = True)
 print("desc.json")
-f = open("desc.json", "wb")
+f = open("desc.json", "w")
 f.truncate()
 f.write(jsonenc.encode(dump.vmsd_desc))
 f.close()
@@ -596,7 +596,7 @@ def default(self, o):
 dump.read(write_memory = True)
 dict = dump.getDict()
 print("state.json")
-f = open("state.json", "wb")
+f = open("state.json", "w")
 f.truncate()
 f.write(jsonenc.encode(dict))
 f.close()
-- 
2.31.1

[PULL 10/11] analyze-migration.py: fix a long standing typo

[Laurent Vivier]

From: Laurent Vivier 

The parameters of '-d' can be either 'state' or 'desc', not 'dump'
as it is reported in the error message.

Fixes: b17425701d66 ("Add migration stream analyzation script")
Signed-off-by: Laurent Vivier 
Reviewed-by: Philippe Mathieu-Daudé 
Message-Id: <20211015131645.501281-2-lviv...@redhat.com>
Signed-off-by: Laurent Vivier 
---
 scripts/analyze-migration.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/analyze-migration.py b/scripts/analyze-migration.py
index d7177b212c86..9d239d309f33 100755
--- a/scripts/analyze-migration.py
+++ b/scripts/analyze-migration.py
@@ -610,4 +610,4 @@ def default(self, o):
 dump.read(desc_only = True)
 print(jsonenc.encode(dump.vmsd_desc))
 else:
-raise Exception("Please specify either -x, -d state or -d dump")
+raise Exception("Please specify either -x, -d state or -d desc")
-- 
2.31.1

[PULL 04/11] MAINTAINERS: Add myself as reviewer of 'Machine core' API

[Laurent Vivier]

From: Philippe Mathieu-Daudé 

In order to help Eduardo and Marcel with the machine
core API, add myself as reviewer. That will also help
me to learn more about this subsystem :)

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed by: Marcel Apfelbaum 
Message-Id: <20211007093108.323223-1-phi...@redhat.com>
Signed-off-by: Laurent Vivier 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4e77d03651bb..894dc4310526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1617,6 +1617,7 @@ F: pc-bios/bios-microvm.bin
 Machine core
 M: Eduardo Habkost 
 M: Marcel Apfelbaum 
+R: Philippe Mathieu-Daudé 
 S: Supported
 F: cpu.c
 F: hw/core/cpu.c
-- 
2.31.1

[PULL 02/11] disas/nios2: Fix style in print_insn_nios2()

[Laurent Vivier]

From: Philippe Mathieu-Daudé 

We are going to modify this function, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Laurent Vivier 
Reviewed-by: Thomas Huth 
Message-Id: <20210807110939.95853-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier 
---
 disas/nios2.c | 55 +--
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/disas/nios2.c b/disas/nios2.c
index c3e82140c798..d124902ae3e1 100644
--- a/disas/nios2.c
+++ b/disas/nios2.c
@@ -3482,38 +3482,37 @@ static int
 print_insn_nios2 (bfd_vma address, disassemble_info *info,
  enum bfd_endian endianness)
 {
-  bfd_byte buffer[INSNLEN];
-  int status;
-
-  status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
-  if (status == 0)
-{
-  unsigned long insn;
-  if (endianness == BFD_ENDIAN_BIG)
-   insn = (unsigned long) bfd_getb32 (buffer);
-  else
-   insn = (unsigned long) bfd_getl32 (buffer);
-  return nios2_disassemble (address, insn, info);
+bfd_byte buffer[INSNLEN];
+int status;
+
+status = (*info->read_memory_func)(address, buffer, INSNLEN, info);
+if (status == 0) {
+unsigned long insn;
+if (endianness == BFD_ENDIAN_BIG) {
+insn = (unsigned long) bfd_getb32(buffer);
+} else {
+insn = (unsigned long) bfd_getl32(buffer);
+}
+return nios2_disassemble(address, insn, info);
 }
 
-  /* We might have a 16-bit R2 instruction at the end of memory.  Try that.  */
-  if (info->mach == bfd_mach_nios2r2)
-{
-  status = (*info->read_memory_func) (address, buffer, 2, info);
-  if (status == 0)
-   {
- unsigned long insn;
- if (endianness == BFD_ENDIAN_BIG)
-   insn = (unsigned long) bfd_getb16 (buffer);
- else
-   insn = (unsigned long) bfd_getl16 (buffer);
- return nios2_disassemble (address, insn, info);
-   }
+/* We might have a 16-bit R2 instruction at the end of memory. Try that. */
+if (info->mach == bfd_mach_nios2r2) {
+status = (*info->read_memory_func)(address, buffer, 2, info);
+if (status == 0) {
+unsigned long insn;
+if (endianness == BFD_ENDIAN_BIG) {
+insn = (unsigned long) bfd_getb16(buffer);
+} else {
+insn = (unsigned long) bfd_getl16(buffer);
+}
+return nios2_disassemble(address, insn, info);
+}
 }
 
-  /* If we got here, we couldn't read anything.  */
-  (*info->memory_error_func) (status, address, info);
-  return -1;
+/* If we got here, we couldn't read anything.  */
+(*info->memory_error_func)(status, address, info);
+return -1;
 }
 
 /* These two functions are the main entry points, accessed from
-- 
2.31.1

[PULL 03/11] disas/nios2: Simplify endianess conversion

[Laurent Vivier]

From: Philippe Mathieu-Daudé 

Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization")
the disassemble_info->bfd_endian enum is set for all targets in
target_disas(). We can directly call print_insn_nios2() and simplify.

Signed-off-by: Philippe Mathieu-Daudé 
Reviewed-by: Laurent Vivier 
Reviewed-by: Thomas Huth 
Message-Id: <20210807110939.95853-3-f4...@amsat.org>
Signed-off-by: Laurent Vivier 
---
 disas/nios2.c   | 22 +++---
 include/disas/dis-asm.h |  3 +--
 target/nios2/cpu.c  |  6 +-
 3 files changed, 5 insertions(+), 26 deletions(-)

diff --git a/disas/nios2.c b/disas/nios2.c
index d124902ae3e1..98ac07d72e9d 100644
--- a/disas/nios2.c
+++ b/disas/nios2.c
@@ -3478,9 +3478,7 @@ nios2_disassemble (bfd_vma address, unsigned long opcode,
instruction word at the address given, and prints the disassembled
instruction on the stream info->stream using info->fprintf_func. */
 
-static int
-print_insn_nios2 (bfd_vma address, disassemble_info *info,
- enum bfd_endian endianness)
+int print_insn_nios2(bfd_vma address, disassemble_info *info)
 {
 bfd_byte buffer[INSNLEN];
 int status;
@@ -3488,7 +3486,7 @@ print_insn_nios2 (bfd_vma address, disassemble_info *info,
 status = (*info->read_memory_func)(address, buffer, INSNLEN, info);
 if (status == 0) {
 unsigned long insn;
-if (endianness == BFD_ENDIAN_BIG) {
+if (info->endian == BFD_ENDIAN_BIG) {
 insn = (unsigned long) bfd_getb32(buffer);
 } else {
 insn = (unsigned long) bfd_getl32(buffer);
@@ -3501,7 +3499,7 @@ print_insn_nios2 (bfd_vma address, disassemble_info *info,
 status = (*info->read_memory_func)(address, buffer, 2, info);
 if (status == 0) {
 unsigned long insn;
-if (endianness == BFD_ENDIAN_BIG) {
+if (info->endian == BFD_ENDIAN_BIG) {
 insn = (unsigned long) bfd_getb16(buffer);
 } else {
 insn = (unsigned long) bfd_getl16(buffer);
@@ -3514,17 +3512,3 @@ print_insn_nios2 (bfd_vma address, disassemble_info 
*info,
 (*info->memory_error_func)(status, address, info);
 return -1;
 }
-
-/* These two functions are the main entry points, accessed from
-   disassemble.c.  */
-int
-print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
-{
-  return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
-}
-
-int
-print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
-{
-  return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
-}
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 524f29196d9d..08e1beec854f 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -455,8 +455,7 @@ int print_insn_crisv32  (bfd_vma, 
disassemble_info*);
 int print_insn_crisv10  (bfd_vma, disassemble_info*);
 int print_insn_microblaze   (bfd_vma, disassemble_info*);
 int print_insn_ia64 (bfd_vma, disassemble_info*);
-int print_insn_big_nios2(bfd_vma, disassemble_info*);
-int print_insn_little_nios2 (bfd_vma, disassemble_info*);
+int print_insn_nios2(bfd_vma, disassemble_info*);
 int print_insn_xtensa   (bfd_vma, disassemble_info*);
 int print_insn_riscv32  (bfd_vma, disassemble_info*);
 int print_insn_riscv64  (bfd_vma, disassemble_info*);
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1ed..58ecd27d757e 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -147,11 +147,7 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, 
disassemble_info *info)
 {
 /* NOTE: NiosII R2 is not supported yet. */
 info->mach = bfd_arch_nios2;
-#ifdef TARGET_WORDS_BIGENDIAN
-info->print_insn = print_insn_big_nios2;
-#else
-info->print_insn = print_insn_little_nios2;
-#endif
+info->print_insn = print_insn_nios2;
 }
 
 static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int 
n)
-- 
2.31.1

[PULL 05/11] softmmu/physmem.c: Fix typo in comment

[Laurent Vivier]

From: Greg Kurz 

Fix the comment to match what the code is doing, as explained in
the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09
that introduced the change:

Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization
of vCPU and migration operations through calling run_on_cpu operation.
However, in replay mode this synchronization is unneeded, because
I/O and vCPU threads are already synchronized.
This patch disables such synchronization for record/replay mode.

Signed-off-by: Greg Kurz 
Reviewed-by: David Hildenbrand 
Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguette>
Signed-off-by: Laurent Vivier 
---
 softmmu/physmem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index f67ad2998121..555c907f6743 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -2633,7 +2633,7 @@ static void tcg_log_global_after_sync(MemoryListener 
*listener)
  * In record/replay mode this causes a deadlock, because
  * run_on_cpu waits for rr mutex. Therefore no races are possible
  * in this case and no need for making run_on_cpu when
- * record/replay is not enabled.
+ * record/replay is enabled.
  */
 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
-- 
2.31.1

[PULL 00/11] Trivial branch for 6.2 patches

[Laurent Vivier]

The following changes since commit 1dafe7656a9c2770065e91208edd4c073f5f98a9:

  Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' 
into staging (2021-10-22 07:47:13 -0700)

are available in the Git repository at:

  git://github.com/vivier/qemu.git tags/trivial-branch-for-6.2-pull-request

for you to fetch changes up to 2c92be50bcfa8b7529a39fc99078ef14dcfc71aa:

  analyze-migration.py: fix extract contents ('-x') errors (2021-10-23 20:28:56 
+0200)


Trivial patches pull request 20211023



Greg Kurz (2):
  softmmu/physmem.c: Fix typo in comment
  README: Fix some documentation URLs

Laurent Vivier (2):
  analyze-migration.py: fix a long standing typo
  analyze-migration.py: fix extract contents ('-x') errors

Oğuz Ersen (1):
  po: update turkish translation

Philippe Mathieu-Daudé (3):
  disas/nios2: Fix style in print_insn_nios2()
  disas/nios2: Simplify endianess conversion
  MAINTAINERS: Add myself as reviewer of 'Machine core' API

Tong Ho (3):
  hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
  hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device
  hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device

 MAINTAINERS   |  1 +
 README.rst| 14 +++---
 disas/nios2.c | 73 ---
 hw/nvram/xlnx-efuse.c |  9 ++--
 hw/nvram/xlnx-versal-efuse-ctrl.c | 20 ++---
 hw/nvram/xlnx-zynqmp-efuse.c  | 18 +---
 include/disas/dis-asm.h   |  3 +-
 po/tr.po  | 25 +--
 scripts/analyze-migration.py  |  6 +--
 softmmu/physmem.c |  2 +-
 target/nios2/cpu.c|  6 +--
 11 files changed, 87 insertions(+), 90 deletions(-)

-- 
2.31.1

[PULL 01/11] po: update turkish translation

[Laurent Vivier]

From: Oğuz Ersen 

Message-Id: 

Signed-off-by: Oğuz Ersen 
Reviewed-by: Laurent Vivier 
[lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/]
Signed-off-by: Laurent Vivier 
---
 po/tr.po | 25 -
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/po/tr.po b/po/tr.po
index 632c7f385132..f4f0425c4319 100644
--- a/po/tr.po
+++ b/po/tr.po
@@ -1,14 +1,15 @@
 # Turkish translation for QEMU.
 # This file is put in the public domain.
 # Ozan Çağlayan , 2013.
+# Oğuz Ersen , 2021.
 #
 msgid ""
 msgstr ""
 "Project-Id-Version: QEMU 1.4.50\n"
 "Report-Msgid-Bugs-To: qemu-devel@nongnu.org\n"
 "POT-Creation-Date: 2018-07-18 07:56+0200\n"
-"PO-Revision-Date: 2013-04-22 18:35+0300\n"
-"Last-Translator: Ozan Çağlayan \n"
+"PO-Revision-Date: 2021-08-15 22:17+0300\n"
+"Last-Translator: Oğuz Ersen \n"
 "Language-Team: Türkçe <>\n"
 "Language: tr\n"
 "MIME-Version: 1.0\n"
@@ -33,24 +34,22 @@ msgid "Power _Down"
 msgstr "_Kapat"
 
 msgid "_Quit"
-msgstr ""
+msgstr "_Çıkış"
 
 msgid "_Fullscreen"
-msgstr ""
+msgstr "_Tam Ekran"
 
 msgid "_Copy"
-msgstr ""
+msgstr "_Kopyala"
 
-#, fuzzy
 msgid "Zoom _In"
-msgstr "Yakınlaş ve Sığ_dır"
+msgstr "_Yakınlaş"
 
-#, fuzzy
 msgid "Zoom _Out"
-msgstr "Yakınlaş ve Sığ_dır"
+msgstr "_Uzaklaş"
 
 msgid "Best _Fit"
-msgstr ""
+msgstr "_En Uygun"
 
 msgid "Zoom To _Fit"
 msgstr "Yakınlaş ve Sığ_dır"
@@ -62,13 +61,13 @@ msgid "_Grab Input"
 msgstr "Girdiyi _Yakala"
 
 msgid "Show _Tabs"
-msgstr "Se_kmeleri Göster"
+msgstr "_Sekmeleri Göster"
 
 msgid "Detach Tab"
-msgstr ""
+msgstr "Sekmeyi Ayır"
 
 msgid "Show Menubar"
-msgstr ""
+msgstr "Menü Çubuğunu Göster"
 
 msgid "_Machine"
 msgstr "_Makine"
-- 
2.31.1

[PULL 09/11] README: Fix some documentation URLs

[Laurent Vivier]

From: Greg Kurz 

All of these pages live in the wiki, not in the main web site.

Signed-off-by: Greg Kurz 
Reviewed-by: Laurent Vivier 
Tested-by: Laurent Vivier 
Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguette>
Signed-off-by: Laurent Vivier 
---
 README.rst | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/README.rst b/README.rst
index 79b19f1481e1..23795b837740 100644
--- a/README.rst
+++ b/README.rst
@@ -59,9 +59,9 @@ of other UNIX targets. The simple steps to build QEMU are:
 
 Additional information can also be found online via the QEMU website:
 
-* ``_
-* ``_
-* ``_
+* ``_
+* ``_
+* ``_
 
 
 Submitting patches
@@ -84,8 +84,8 @@ the Developers Guide.
 Additional information on submitting patches can be found online via
 the QEMU website
 
-* ``_
-* ``_
+* ``_
+* ``_
 
 The QEMU website is also maintained under source control.
 
@@ -144,7 +144,7 @@ reported via GitLab.
 
 For additional information on bug reporting consult:
 
-* ``_
+* ``_
 
 
 ChangeLog
@@ -168,4 +168,4 @@ main methods being email and IRC
 Information on additional methods of contacting the community can be
 found online via the QEMU website:
 
-* ``_
+* ``_
-- 
2.31.1

Re: [PATCH v3 33/48] tcg/optimize: Add type to OptContext

[Richard Henderson]

On 10/22/21 3:11 PM, Luis Fernando Fujita Pires wrote:

From: Richard Henderson 


@@ -1392,18 +1408,18 @@ void tcg_optimize(TCGContext *s)
  /* Proceed with possible constant folding. */
  break;
  }
-if (opc == INDEX_op_sub_i32) {
+switch (ctx.type) {
+case TCG_TYPE_I32:
  neg_op = INDEX_op_neg_i32;
  have_neg = TCG_TARGET_HAS_neg_i32;
-} else if (opc == INDEX_op_sub_i64) {
+break;
+case TCG_TYPE_I64:
  neg_op = INDEX_op_neg_i64;
  have_neg = TCG_TARGET_HAS_neg_i64;
-} else if (TCG_TARGET_HAS_neg_vec) {
-TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
-unsigned vece = TCGOP_VECE(op);
+break;
+default:
  neg_op = INDEX_op_neg_vec;
-have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
-} else {
+have_neg = tcg_can_emit_vec_op(neg_op, ctx.type,
+ TCGOP_VECE(op)) > 0;


Should we replace the 'default' here with a case for TCG_TYPE_V{64,128,256} and 
add a new 'default' with g_assert_not_reached()?


Yes, that's probably a good idea.


r~

Re: [PATCH] tests/tcg: Fix some targets default cross compiler path

[Philippe Mathieu-Daudé]

On Sat, Oct 23, 2021 at 7:47 PM Alex Bennée  wrote:
> Philippe Mathieu-Daudé  writes:
>
> > We do not want a shell command substitution, but a parameter
> > substitution (with assignment). Replace $() -> ${}, otherwise
> > the expanded command return an empty string and the $cross_cc
> > variable is not set.
>
> Queued to testing/next, thanks.

Thanks. FYI now the build-user* jobs run more tests: before ~38min,
after ~41m30s. The difference is small and worth the coverage.

Re: [PATCH] tests/tcg: Fix some targets default cross compiler path

[Alex Bennée]

Philippe Mathieu-Daudé  writes:

> We do not want a shell command substitution, but a parameter
> substitution (with assignment). Replace $() -> ${}, otherwise
> the expanded command return an empty string and the $cross_cc
> variable is not set.

Queued to testing/next, thanks.

-- 
Alex Bennée

[PATCH] tests/tcg: Fix some targets default cross compiler path

[Philippe Mathieu-Daudé]

We do not want a shell command substitution, but a parameter
substitution (with assignment). Replace $() -> ${}, otherwise
the expanded command return an empty string and the $cross_cc
variable is not set.

Fixes: 634ef789f8e ("tests/tcg: add more default compilers to configure.sh")
Signed-off-by: Philippe Mathieu-Daudé 
---
 tests/tcg/configure.sh | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 1f985ccfc0c..b8574165fa6 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -46,7 +46,7 @@ fi
 : ${cross_cc_aarch64="aarch64-linux-gnu-gcc"}
 : ${cross_cc_aarch64_be="$cross_cc_aarch64"}
 : ${cross_cc_cflags_aarch64_be="-mbig-endian"}
-: $(cross_cc_alpha="alpha-linux-gnu-gcc")
+: ${cross_cc_alpha="alpha-linux-gnu-gcc"}
 : ${cross_cc_arm="arm-linux-gnueabihf-gcc"}
 : ${cross_cc_cflags_armeb="-mbig-endian"}
 : ${cross_cc_hexagon="hexagon-unknown-linux-musl-clang"}
@@ -55,17 +55,17 @@ fi
 : ${cross_cc_i386="i686-linux-gnu-gcc"}
 : ${cross_cc_cflags_i386="-m32"}
 : ${cross_cc_m68k="m68k-linux-gnu-gcc"}
-: $(cross_cc_mips64el="mips64el-linux-gnuabi64-gcc")
-: $(cross_cc_mips64="mips64-linux-gnuabi64-gcc")
-: $(cross_cc_mipsel="mipsel-linux-gnu-gcc")
-: $(cross_cc_mips="mips-linux-gnu-gcc")
+: ${cross_cc_mips64el="mips64el-linux-gnuabi64-gcc"}
+: ${cross_cc_mips64="mips64-linux-gnuabi64-gcc"}
+: ${cross_cc_mipsel="mipsel-linux-gnu-gcc"}
+: ${cross_cc_mips="mips-linux-gnu-gcc"}
 : ${cross_cc_ppc="powerpc-linux-gnu-gcc"}
 : ${cross_cc_cflags_ppc="-m32"}
 : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"}
 : ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"}
-: $(cross_cc_riscv64="riscv64-linux-gnu-gcc")
+: ${cross_cc_riscv64="riscv64-linux-gnu-gcc"}
 : ${cross_cc_s390x="s390x-linux-gnu-gcc"}
-: $(cross_cc_sh4="sh4-linux-gnu-gcc")
+: ${cross_cc_sh4="sh4-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultrasparc"}
 : ${cross_cc_sparc64="sparc64-linux-gnu-gcc"}
 : ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"}
-- 
2.31.1

Re: [PATCH 09/24] bsd-user/arm/target_arch_cpu.h: Implement system call dispatch

[Warner Losh]

On Sat, Oct 23, 2021 at 1:34 AM Kyle Evans  wrote:

> On Tue, Oct 19, 2021 at 11:45 AM Warner Losh  wrote:
> >
> > Implement the system call dispatch. This implements all three kinds of
> > system call: direct and the two indirect variants. It handles all the
> > special cases for thumb as well.
> >
> > Signed-off-by: Stacey Son 
> > Signed-off-by: Klye Evans 
> > Signed-off-by: Warner Losh 
>
> s/Klye/Kyle/
>

I'll fix the typo in the QEMU.SOB file I have... 

Thanks!


> > ---
> >  bsd-user/arm/target_arch_cpu.h | 95 ++
> >  1 file changed, 95 insertions(+)
> >
> > diff --git a/bsd-user/arm/target_arch_cpu.h
> b/bsd-user/arm/target_arch_cpu.h
> > index 62d6ee89b6..bc2eb05cfe 100644
> > --- a/bsd-user/arm/target_arch_cpu.h
> > +++ b/bsd-user/arm/target_arch_cpu.h
> > @@ -39,6 +39,7 @@ static inline void target_cpu_loop(CPUARMState *env)
> >  {
> >  int trapnr;
> >  target_siginfo_t info;
> > +unsigned int n;
> >  CPUState *cs = env_cpu(env);
> >
> >  for (;;) {
> > @@ -57,6 +58,100 @@ static inline void target_cpu_loop(CPUARMState *env)
> >  queue_signal(env, info.si_signo, );
> >  }
> >  break;
> > +case EXCP_SWI:
> > +case EXCP_BKPT:
> > +{
> > +env->eabi = 1; /* FreeBSD is eabi only now */
> > +/*
> > + * system call
> > + * See arm/arm/trap.c cpu_fetch_syscall_args()
> > + */
> > +if (trapnr == EXCP_BKPT) {
> > +if (env->thumb) {
> > +env->regs[15] += 2;
> > +} else {
> > +env->regs[15] += 4;
> > +}
> > +}
> > +n = env->regs[7];
> > +if (bsd_type == target_freebsd) {
> > +int ret;
> > +abi_ulong params = get_sp_from_cpustate(env);
> > +int32_t syscall_nr = n;
> > +int32_t arg1, arg2, arg3, arg4, arg5, arg6, arg7,
> arg8;
> > +
> > +/* See arm/arm/trap.c cpu_fetch_syscall_args() */
> > +if (syscall_nr == TARGET_FREEBSD_NR_syscall) {
> > +syscall_nr = env->regs[0];
> > +arg1 = env->regs[1];
> > +arg2 = env->regs[2];
> > +arg3 = env->regs[3];
> > +get_user_s32(arg4, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg5, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg6, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg7, params);
> > +arg8 = 0;
> > +} else if (syscall_nr ==
> TARGET_FREEBSD_NR___syscall) {
> > +syscall_nr = env->regs[0];
> > +arg1 = env->regs[2];
> > +arg2 = env->regs[3];
> > +get_user_s32(arg3, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg4, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg5, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg6, params);
> > +arg7 = 0;
> > +arg8 = 0;
> > +} else {
> > +arg1 = env->regs[0];
> > +arg2 = env->regs[1];
> > +arg3 = env->regs[2];
> > +arg4 = env->regs[3];
> > +get_user_s32(arg5, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg6, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg7, params);
> > +params += sizeof(int32_t);
> > +get_user_s32(arg8, params);
> > +}
> > +ret = do_freebsd_syscall(env, syscall_nr, arg1,
> arg2, arg3,
> > +arg4, arg5, arg6, arg7, arg8);
> > +/*
> > + * Compare to arm/arm/vm_machdep.c
> > + * cpu_set_syscall_retval()
> > + */
> > +if (-TARGET_EJUSTRETURN == ret) {
> > +/*
> > + * Returning from a successful sigreturn
> syscall.
> > + * Avoid clobbering register state.
> > + */
> > +break;
> > +}
> > +if (-TARGET_ERESTART == ret) {
> > +