Re: [PATCH v2] scripts/qapi: minor delinting
Queued, thanks!
Re: [PATCH v2] qapi/migration: Fix examples document wrong field name for arguments
Fabian Holler writes:
> The examples for the snapshot-* and calc-dirty-rate commands document
> that arguments for the commands are passed in a 'data' field.
> This is wrong, passing them in a "data" field results in
> the error:
> {"error": {"class": "GenericError", "desc": "QMP input member 'data'
> is unexpected"}}
> Arguments are expected to be passed in an field called "arguments".
>
> Replace "data" with "arguments" in the snapshot-* and calc-dirty-rate
> command examples.
>
> Signed-off-by: Fabian Holler
Reviewed-by: Markus Armbruster
Queued, thanks!
Re: [PATCH 20/20] tests: Add postcopy preempt test
On Tue, Feb 22, 2022 at 12:51:59PM +, Dr. David Alan Gilbert wrote: > * Peter Xu (pet...@redhat.com) wrote: > > Two tests are added: a normal postcopy preempt test, and a recovery test. > > Yes, this is difficult; without hugepages the tests are limited; did you > see if this test actually causes pages to go down the fast path? I didn't observe the test case explicitly, but I did observe in my own test that I ran that it goes with the fast path, or I can't get a huge speed up. Meanwhile my own test is only using 2M huge pages, and I can observe interruptions of huge page sendings frequently. But yeah let me try to capture something in this test too, at least to make sure the standalone socket is being used. Covering of huge pages might be doable but obviously requires host privileges, so I'll leave that for later. > > > > Reviewed-by: Dr. David Alan Gilbert Thanks, -- Peter Xu
Re: [PATCH 19/20] migration: Postcopy recover with preempt enabled
On Tue, Feb 22, 2022 at 11:32:10AM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU
> > thread
> > needs similar handling on fault tolerance. When ram_load_postcopy() fails,
> > instead of stopping the thread it halts with a semaphore, preparing to be
> > kicked again when recovery is detected.
> >
> > A mutex is introduced to make sure there's no concurrent operation upon the
> > socket. To make it simple, the fast ram load thread will take the mutex
> > during
> > its whole procedure, and only release it if it's paused. The fast-path
> > socket
> > will be properly released by the main loading thread safely when there's
> > network failures during postcopy with that mutex held.
>
> I *think* this is mostly OK; but I worry I don't understand all the
> cases; e.g.
> a) If the postcopy channel errors first
> b) If the main channel errors first
Ah right, I don't think I handled all the cases. Sorry.
We always check the main channel, but if the postcopy channel got faulted,
we may not fall into paused mode as expected.
I'll fix that up.
>
> Can you add some docs to walk through those and explain the locking ?
Sure.
The sem is mentioned in the last sentence of paragraph 1, where it's purely
used for a way to yield the fast ram load thread so that when something
wrong happens it can sleep on that semaphore. Then when we recover we'll
post to the semaphore to kick it up. We used it like that in many places,
e.g. postcopy_pause_sem_dst to yield the main load thread.
The 2nd paragraph above was for explaining why we need the mutex; it's
basically the same as rp_mutex protecting to_src_file, so that we won't
accidentally close() the qemufile during some other thread using it. So
the fast ram load thread needs to take that new mutex for mostly the whole
lifecycle of itself (because it's loading from that qemufile), meanwhile
only drop the mutex when it prepares to sleep. Then the main load thread
can recycle the postcopy channel using qemu_fclose() safely.
[...]
> > @@ -3466,6 +3468,17 @@ static MigThrError postcopy_pause(MigrationState *s)
> > qemu_file_shutdown(file);
> > qemu_fclose(file);
> >
> > +/*
> > + * Do the same to postcopy fast path socket too if there is. No
> > + * locking needed because no racer as long as we do this before
> > setting
> > + * status to paused.
> > + */
> > +if (s->postcopy_qemufile_src) {
> > +
> > migration_ioc_unregister_yank_from_file(s->postcopy_qemufile_src);
>
> Shouldn't this do a qemu_file_shutdown on here first?
Yes I probably should.
With all above, I plan to squash below changes into this patch:
---8<---
diff --git a/migration/migration.c b/migration/migration.c
index c68a281406..69778cab23 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -3475,6 +3475,7 @@ static MigThrError postcopy_pause(MigrationState *s)
*/
if (s->postcopy_qemufile_src) {
migration_ioc_unregister_yank_from_file(s->postcopy_qemufile_src);
+qemu_file_shutdown(s->postcopy_qemufile_src);
qemu_fclose(s->postcopy_qemufile_src);
s->postcopy_qemufile_src = NULL;
}
@@ -3534,8 +3535,13 @@ static MigThrError migration_detect_error(MigrationState
*s)
return MIG_THR_ERR_FATAL;
}
-/* Try to detect any file errors */
-ret = qemu_file_get_error_obj(s->to_dst_file, _error);
+/*
+ * Try to detect any file errors. Note that postcopy_qemufile_src will
+ * be NULL when postcopy preempt is not enabled.
+ */
+ret = qemu_file_get_error_obj_any(s->to_dst_file,
+ s->postcopy_qemufile_src,
+ _error);
if (!ret) {
/* Everything is fine */
assert(!local_error);
diff --git a/migration/qemu-file.c b/migration/qemu-file.c
index 1479cddad9..397652f0ba 100644
--- a/migration/qemu-file.c
+++ b/migration/qemu-file.c
@@ -139,6 +139,33 @@ int qemu_file_get_error_obj(QEMUFile *f, Error **errp)
return f->last_error;
}
+/*
+ * Get last error for either stream f1 or f2 with optional Error*.
+ * The error returned (non-zero) can be either from f1 or f2.
+ *
+ * If any of the qemufile* is NULL, then skip the check on that file.
+ *
+ * When there is no error on both qemufile, zero is returned.
+ */
+int qemu_file_get_error_obj_any(QEMUFile *f1, QEMUFile *f2, Error **errp)
+{
+int ret = 0;
+
+if (f1) {
+ret = qemu_file_get_error_obj(f1, errp);
+/* If there's already error detected, return */
+if (ret) {
+return ret;
+}
+}
+
+if (f2) {
+ret = qemu_file_get_error_obj(f2, errp);
+}
+
+return ret;
+}
+
/*
* Set the last error for stream f with optional Error*
*/
diff --git a/migration/qemu-file.h
Re: [PATCH v2 2/3] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall
Excerpts from David Gibson's message of February 17, 2022 10:17 am:
> On Wed, Feb 16, 2022 at 04:39:02PM +1000, Nicholas Piggin wrote:
>> The behaviour of the Address Translation Mode on Interrupt resource is
>> not consistently supported by all CPU versions or all KVM versions:
>> KVM-HV does not support mode 2, and does not support mode 3 on POWER7 or
>> early POWER9 processesors. KVM PR only supports mode 0. TCG supports all
>> modes (0, 2, 3). This leads to inconsistencies in guest behaviour and
>> could cause problems migrating guests.
>>
>> This was not noticable for Linux guests for a long time because the
>> kernel only uses modes 0 and 3, and it used to consider AIL-3 to be
>> advisory in that it would always keep the AIL-0 vectors around. Recent
>> Linux guests depend on the AIL mode working as specified in order to
>> support the SCV facility interrupt. If AIL-3 can not be provided, then
>> Linux must be given an error so it can disable the SCV facility, rather
>> than silently failing.
>>
>> Add the ail-mode-3 capability to specify that AIL-3 is supported. AIL-0
>> is implied as the baseline, and AIL-2 is no longer supported by spapr.
>> AIL-2 is not known to be used by any software, but support in TCG could
>> be restored with an ail-mode-2 capability quite easily if a regression
>> is reported.
>>
>> Modify the H_SET_MODE Address Translation Mode on Interrupt resource
>> handler to check capabilities and correctly return error if not
>> supported.
>>
>> A heuristic is added for KVM to determine AIL-3 support before the
>> introduction of a new KVM CAP, because blanket disabling AIL-3 has too
>> much performance cost.
>>
>> Signed-off-by: Nicholas Piggin
>
> Reviewed-by: David Gibson
>
> [snip]
>> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
>> index dc93b99189..1338c41f8f 100644
>> --- a/target/ppc/kvm.c
>> +++ b/target/ppc/kvm.c
>> @@ -2563,6 +2563,35 @@ int kvmppc_has_cap_rpt_invalidate(void)
>> return cap_rpt_invalidate;
>> }
>>
>> +bool kvmppc_supports_ail_3(void)
>> +{
>> +PowerPCCPUClass *pcc = kvm_ppc_get_host_cpu_class();
>> +
>> +/*
>> + * KVM PR only supports AIL-0
>> + */
>> +if (kvmppc_is_pr(kvm_state)) {
>> +return 0;
>> +}
>> +
>> +/*
>> + * KVM HV hosts support AIL-3 on POWER8 and above, except for radix
>> + * mode on some early POWER9s.
>> + */
>> +if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
>> +return 0;
>> +}
>> +
>> +/* These tests match the CPU_FTR_P9_RADIX_PREFETCH_BUG flag in Linux */
>> +if (((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD1) ||
>> +((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD20) ||
>> +((pcc->pvr & 0xff00) == CPU_POWERPC_POWER9_DD21)) {
>> +return 0;
>> +}
>
> Deducing what KVM supports rather than getting it to tell us
> explicitly with a cap is usually frowned upon. However, given the
> earlier discussion, I'm satisfied that this is the least bad available
> option, at least for now.
BTW this particular test doesn't work as I hoped because we only have
a power9 dd2.0 model.
Adding a 2.2 or 2.3 would be possible. Maybe overkill. I'll change
the test just to catch all POWER9 for now.
KVM cap has been allocated in the upstream kvm tree now though, so I'll
re-send soon.
Thanks,
Nick
Re: [PATCH 18/20] migration: Postcopy preemption enablement
On Tue, Feb 22, 2022 at 10:52:23AM +, Dr. David Alan Gilbert wrote: > This does get a bit complicated, which worries me a bit; the code here > is already quite complicated. Right, it's the way I chose in this patchset on solving this problem. Not sure whether there's any better and easier way. For example, we could have used a new thread to send requested pages, and synchronize it with the main thread. But that'll need other kind of complexity, and I can't quickly tell whether that'll be better. For this single patch, more than half of the complexity comes from the ability to interrupt sending one huge page half-way. It's a bit of a pity that, that part will be noop ultimately when with doublemap. However I kept those only because we don't know when doublemap will be ready, not to say, landing. Meanwhile we can't assume all kernels will have doublemap even in the future. > (If you repost, there are a few 'channel' variables that could probably > be 'unsigned' rather than int) That I can do for sure. > > Reviewed-by: Dr. David Alan Gilbert Thanks, -- Peter Xu
Re: [PATCH v3] target/riscv: Add isa extenstion strings to the device tree
On Wed, Feb 23, 2022 at 4:09 AM Atish Patra wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Suggested-by: Heiko Stubner
> Signed-off-by: Atish Patra
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> Changes from v2->v3:
> 1. Used g_strconcat to replace snprintf & a max isa string length as
> suggested by Anup.
> 2. I have not included the Tested-by Tag from Heiko because the
> implementation changed from v2 to v3.
>
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 29 +
> 1 file changed, 29 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b0a40b83e7a8..2c7ff6ef555a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,12 @@
>
> /* RISC-V CPU definitions */
>
> +/* This includes the null terminated character '\0' */
> +struct isa_ext_data {
> +const char *name;
> +bool enabled;
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -881,6 +887,28 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int
> max_str_len)
> +{
> +char *old = *isa_str;
> +char *new = *isa_str;
> +int i;
> +struct isa_ext_data isa_edata_arr[] = {
> +{ "svpbmt", cpu->cfg.ext_svpbmt },
> +{ "svinval", cpu->cfg.ext_svinval },
> +{ "svnapot", cpu->cfg.ext_svnapot },
> +};
> +
> +for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> +if (isa_edata_arr[i].enabled) {
> +new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> +g_free(old);
> +old = new;
> +}
> +}
> +
> +*isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -893,6 +921,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> +riscv_isa_string_ext(cpu, _str, maxlen);
> return isa_str;
> }
>
> --
> 2.30.2
>
>
Re: [PATCH 13/20] migration: Move channel setup out of postcopy_try_recover()
On Tue, Feb 22, 2022 at 10:57:34AM +, Dr. David Alan Gilbert wrote:
> * Peter Xu (pet...@redhat.com) wrote:
> > We used to use postcopy_try_recover() to replace migration_incoming_setup()
> > to
> > setup incoming channels. That's fine for the old world, but in the new
> > world
> > there can be more than one channels that need setup. Better move the
> > channel
> > setup out of it so that postcopy_try_recover() only handles the last phase
> > of
> > switching to the recovery phase.
> >
> > To do that in migration_fd_process_incoming(), move the
> > postcopy_try_recover()
> > call to be after migration_incoming_setup(), which will setup the channels.
> > While in migration_ioc_process_incoming(), postpone the recover() routine
> > right
> > before we'll jump into migration_incoming_process().
> >
> > A side benefit is we don't need to pass in QEMUFile* to
> > postcopy_try_recover()
> > anymore. Remove it.
> >
> > Signed-off-by: Peter Xu
>
> OK, but note one question below:
>
> Reviewed-by: Dr. David Alan Gilbert
Thanks.
>
> > ---
> > migration/migration.c | 23 +++
> > 1 file changed, 11 insertions(+), 12 deletions(-)
> >
> > diff --git a/migration/migration.c b/migration/migration.c
> > index 67520d3105..b2e6446457 100644
> > --- a/migration/migration.c
> > +++ b/migration/migration.c
> > @@ -665,19 +665,20 @@ void migration_incoming_process(void)
> > }
> >
> > /* Returns true if recovered from a paused migration, otherwise false */
> > -static bool postcopy_try_recover(QEMUFile *f)
> > +static bool postcopy_try_recover(void)
> > {
> > MigrationIncomingState *mis = migration_incoming_get_current();
> >
> > if (mis->state == MIGRATION_STATUS_POSTCOPY_PAUSED) {
> > /* Resumed from a paused postcopy migration */
> >
> > -mis->from_src_file = f;
> > +/* This should be set already in migration_incoming_setup() */
> > +assert(mis->from_src_file);
> > /* Postcopy has standalone thread to do vm load */
> > -qemu_file_set_blocking(f, true);
> > +qemu_file_set_blocking(mis->from_src_file, true);
>
> Does that set_blocking happen on the 2nd channel somewhere?
Nop. I think the rational is that by default all channels are blocking.
Then what happened is: migration code only sets the main channel to
non-blocking on incoming, that's in migration_incoming_setup(). Hence for
postcopy recovery we need to tweak it to blocking here.
The 2nd new channel is not operated by migration_incoming_setup(), but by
postcopy_preempt_new_channel(), so it keeps the original blocking state,
which should be blocking.
If we want to make that clear, we can proactively set non-blocking too in
postcopy_preempt_new_channel() on the 2nd channel. It's just that it
should be optional as long as blocking is the default for any new fd of a
socket.
Thanks,
--
Peter Xu
[PATCH 3/3] whpx: Added support for breakpoints and stepping
This adds support for breakpoints and stepping when debugging
WHPX-accelerated guests with gdb.
It enables reliable debugging of the Linux kernel in both single-CPU and SMP
modes.
Signed-off-by: Ivan Shcherbakov
---
gdbstub.c| 10 +
include/exec/gdbstub.h | 8 +
target/i386/whpx/whpx-all.c | 689 ++-
target/i386/whpx/whpx-internal.h | 29 ++
4 files changed, 721 insertions(+), 15 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 3c14c6a038..d30cbfa478 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -373,6 +373,12 @@ typedef struct GDBState {
} GDBState;
static GDBState gdbserver_state;
+static bool gdbserver_is_connected;
+
+bool gdb_is_connected(void)
+{
+return gdbserver_is_connected;
+}
static void init_gdbserver_state(void)
{
@@ -3410,6 +3416,10 @@ static void gdb_chr_event(void *opaque, QEMUChrEvent
event)
vm_stop(RUN_STATE_PAUSED);
replay_gdb_attached();
gdb_has_xml = false;
+gdbserver_is_connected = true;
+break;
+case CHR_EVENT_CLOSED:
+gdbserver_is_connected = false;
break;
default:
break;
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index a024a0350d..0ef54cdeb5 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -188,4 +188,12 @@ extern bool gdb_has_xml;
/* in gdbstub-xml.c, generated by scripts/feature_to_c.sh */
extern const char *const xml_builtin[][2];
+/**
+ * gdb_is_connected: Check whether gdb is currently connected.
+ * This function is used to determine if gdb is currently connected to
qemu.
+ * It is used by the WHPX engine to enable interception of debug-related
+ * exceptions, when debugging with gdb, and pass them to the guest
otherwise.
+ */
+bool gdb_is_connected(void);
+
#endif
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 8a8b5d55d1..030988fa51 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -12,6 +12,7 @@
#include "cpu.h"
#include "exec/address-spaces.h"
#include "exec/ioport.h"
+#include "exec/gdbstub.h"
#include "qemu-common.h"
#include "qemu/accel.h"
#include "sysemu/whpx.h"
@@ -148,6 +149,12 @@ struct whpx_register_set {
WHV_REGISTER_VALUE values[RTL_NUMBER_OF(whpx_register_names)];
};
+enum whpx_step_mode {
+whpx_step_none = 0,
+/* Halt other VCPUs */
+whpx_step_exclusive,
+};
+
struct whpx_vcpu {
WHV_EMULATOR_HANDLE emulator;
bool window_registered;
@@ -156,7 +163,6 @@ struct whpx_vcpu {
uint64_t tpr;
uint64_t apic_base;
bool interruption_pending;
-
/* Must be the last field as it may have a tail */
WHV_RUN_VP_EXIT_CONTEXT exit_ctx;
};
@@ -793,6 +799,515 @@ static int whpx_handle_portio(CPUState *cpu,
return 0;
}
+/*
+ * Controls whether we should intercept various exceptions on the guest,
+ * namely breakpoint/single-step events.
+ *
+ * The 'exceptions' argument accepts a bitmask, e.g:
+ * (1 << WHvX64ExceptionTypeDebugTrapOrFault) | (...)
+ */
+static HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions)
+{
+struct whpx_state *whpx = _global;
+WHV_PARTITION_PROPERTY prop = { 0, };
+HRESULT hr;
+
+if (exceptions == whpx->exception_exit_bitmap) {
+return S_OK;
+}
+
+prop.ExceptionExitBitmap = exceptions;
+
+hr = whp_dispatch.WHvSetPartitionProperty(
+whpx->partition,
+WHvPartitionPropertyCodeExceptionExitBitmap,
+,
+sizeof(WHV_PARTITION_PROPERTY));
+
+if (SUCCEEDED(hr)) {
+whpx->exception_exit_bitmap = exceptions;
+}
+
+return hr;
+}
+
+
+/*
+ * This function is called before/after stepping over a single instruction.
+ * It will update the CPU registers to arm/disarm the instruction stepping
+ * accordingly.
+ */
+static HRESULT whpx_vcpu_configure_single_stepping(CPUState *cpu,
+bool set,
+uint64_t *exit_context_rflags)
+{
+WHV_REGISTER_NAME reg_name;
+WHV_REGISTER_VALUE reg_value;
+HRESULT hr;
+struct whpx_state *whpx = _global;
+
+/*
+ * If we are trying to step over a single instruction, we need to set
the
+ * TF bit in rflags. Otherwise, clear it.
+ */
+reg_name = WHvX64RegisterRflags;
+hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
+whpx->partition,
+cpu->cpu_index,
+_name,
+1,
+_value);
+
+if (FAILED(hr)) {
+error_report("WHPX: Failed to get rflags, hr=%08lx", hr);
+return hr;
+}
+
+if (exit_context_rflags) {
+assert(*exit_context_rflags == reg_value.Reg64);
+}
+
+if (set) {
+/* Raise WHvX64ExceptionTypeDebugTrapOrFault after each instruction
*/
+reg_value.Reg64 |= TF_MASK;
+} else {
+reg_value.Reg64 &= ~TF_MASK;
+}
+
+if (exit_context_rflags) {
+*exit_context_rflags = reg_value.Reg64;
+}
+
+hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
+
[PATCH 2/3] whpx: Fixed incorrect CR8/TPR synchronization
This fixes the following error triggered when stopping and resuming a 64-bit
Linux kernel via gdb:
qemu-system-x86_64.exe: WHPX: Failed to set virtual processor context,
hr=c0350005
The previous logic for synchronizing the values did not take into account
that the lower 4 bits of
the CR8 register, containing the priority level, mapped to bits 7:4 of the
APIC.TPR register
(see section 10.8.6.1 of Volume 3 of Intel 64 and IA-32 Architectures
Software Developer's Manual).
The caused WHvSetVirtualProcessorRegisters() to fail with an error,
effectively preventing GDB from
changing the guest context.
Signed-off-by: Ivan Shcherbakov
---
target/i386/whpx/whpx-all.c | 49 +++--
1 file changed, 41 insertions(+), 8 deletions(-)
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index edd4fafbdf..8a8b5d55d1 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -256,6 +256,28 @@ static int whpx_set_tsc(CPUState *cpu)
return 0;
}
+/*
+ * The CR8 register in the CPU is mapped to the TPR register of the APIC,
+ * however, they use a slightly different encoding. Specifically:
+ *
+ * APIC.TPR[bits 7:4] = CR8[bits 3:0]
+ *
+ * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64
+ * and IA-32 Architectures Software Developer's Manual.
+ *
+ * The functions below translate the value of CR8 to TPR and vice versa.
+ */
+
+static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)
+{
+return tpr >> 4;
+}
+
+static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)
+{
+return cr8 << 4;
+}
+
static void whpx_set_registers(CPUState *cpu, int level)
{
struct whpx_state *whpx = _global;
@@ -284,7 +306,7 @@ static void whpx_set_registers(CPUState *cpu, int level)
v86 = (env->eflags & VM_MASK);
r86 = !(env->cr[0] & CR0_PE_MASK);
-vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);
+vcpu->tpr =
whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));
vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);
idx = 0;
@@ -475,6 +497,17 @@ static void whpx_get_registers(CPUState *cpu)
hr);
}
+if (whpx_apic_in_platform()) {
+/*
+ * Fetch the TPR value from the emulated APIC. It may get
overwritten
+ * below with the value from CR8 returned by
+ * WHvGetVirtualProcessorRegisters().
+ */
+whpx_apic_get(x86_cpu->apic_state);
+vcpu->tpr = whpx_apic_tpr_to_cr8(
+cpu_get_apic_tpr(x86_cpu->apic_state));
+}
+
idx = 0;
/* Indexes for first 16 registers match between HV and QEMU definitions
*/
@@ -521,8 +554,12 @@ static void whpx_get_registers(CPUState *cpu)
assert(whpx_register_names[idx] == WHvX64RegisterCr8);
tpr = vcxt.values[idx++].Reg64;
if (tpr != vcpu->tpr) {
+/*
+ * TPR value stored in the CR8 register doesn't match the one
fetched
+ * from the emulated APIC. Override the latter with the former.
+ */
vcpu->tpr = tpr;
-cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
+cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));
}
/* 8 Debug Registers - Skipped */
@@ -600,10 +637,6 @@ static void whpx_get_registers(CPUState *cpu)
assert(idx == RTL_NUMBER_OF(whpx_register_names));
-if (whpx_apic_in_platform()) {
-whpx_apic_get(x86_cpu->apic_state);
-}
-
x86_update_hflags(env);
return;
@@ -865,7 +898,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
}
/* Sync the TPR to the CR8 if was modified during the intercept */
-tpr = cpu_get_apic_tpr(x86_cpu->apic_state);
+tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));
if (tpr != vcpu->tpr) {
vcpu->tpr = tpr;
reg_values[reg_count].Reg64 = tpr;
@@ -914,7 +947,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)
if (vcpu->tpr != tpr) {
vcpu->tpr = tpr;
qemu_mutex_lock_iothread();
-cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);
+cpu_set_apic_tpr(x86_cpu->apic_state,
whpx_cr8_to_apic_tpr(vcpu->tpr));
qemu_mutex_unlock_iothread();
}
--
2.29.2.windows.3
[PATCH 1/3] whpx: Fixed reporting of the CPU context to GDB for 64-bit
Hi All, We have been looking into kernel-debugging Linux VMs running on Windows with Hyper-V enabled (that forces the virtualization software to use WHPX), and it turned out, none of the major virtualization tools supports it properly. I've added the missing parts to QEMU and it looks pretty solid: setting breakpoints in the kernel, running, stepping in/over works reliably and fast. The changes involved 3 parts: 1. Fixing the x64 register reporting to gdb (this patch) 2. Fixing synchronization of CR8 <=> APIC.TPR, that was preventing WHvSetVirtualProcessorRegisters() from working 3. Implementing software breakpoints It would be great if the changes could be integrated into the QEMU repository, allowing other Windows users to debug their VMs. Below is the description of the first patch. This change makes sure that stopping in the 64-bit mode will set the HF_CS64_MASK flag in env->hflags (see x86_update_hflags() in target/i386/cpu.c). Without it, the code in gdbstub.c would only use the 32-bit register values when debugging 64-bit targets, making debugging effectively impossible. Signed-off-by: Ivan Shcherbakov --- target/i386/whpx/whpx-all.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ef896da0a2..edd4fafbdf 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -604,6 +604,8 @@ static void whpx_get_registers(CPUState *cpu) whpx_apic_get(x86_cpu->apic_state); } +x86_update_hflags(env); + return; } --
virtio-blk issue with vIOMMU
Hi Stefan:
Recently I found intel vIOMMU gives the following warning when using
virtio-blk:
qemu-system-x86_64: vtd_iova_to_slpte: detected slpte permission error
(iova=0x7ffde000, level=0x3, slpte=0x0, write=0)
qemu-system-x86_64: vtd_iommu_translate: detected translation failure
(dev=01:00:00, iova=0x7ffde000)
qemu-system-x86_64: New fault is not recorded due to compression of faults
qemu-system-x86_64: virtio: zero sized buffers are not allowed
It happens on the boot (device start), and virtio-blk works well after
this. A quick stack trace is:
Thread 1 "qemu-system-x86" hit Breakpoint 1, vtd_iova_to_slpte
(s=0x57a9f710, ce=0x7fffd6e0, iova=2147344384, is_write=false,
slptep=0x7fffd6b8,
slpte_level=0x7fffd6b0, reads=0x7fffd6aa,
writes=0x7fffd6ab, aw_bits=39 '\'') at ../hw/i386/intel_iommu.c:1055
1055 error_report_once("%s: detected slpte permission error "
(gdb) bt
#0 vtd_iova_to_slpte
(s=0x57a9f710, ce=0x7fffd6e0, iova=2147344384,
is_write=false, slptep=0x7fffd6b8, slpte_level=0x7fffd6b0,
reads=0x7fffd6aa, writes=0x7fffd6ab, aw_bits=39 '\'') at
../hw/i386/intel_iommu.c:1055
#1 0x55b45734 in vtd_do_iommu_translate (vtd_as=0x574cd000,
bus=0x5766e700, devfn=0 '\000', addr=2147344384, is_write=false,
entry=0x7fffd780)
at ../hw/i386/intel_iommu.c:1785
#2 0x55b48543 in vtd_iommu_translate (iommu=0x574cd070,
addr=2147344384, flag=IOMMU_RO, iommu_idx=0) at
../hw/i386/intel_iommu.c:2996
#3 0x55bd3f4d in address_space_translate_iommu
(iommu_mr=0x574cd070, xlat=0x7fffd9f0,
plen_out=0x7fffd9e8, page_mask_out=0x0, is_write=false,
is_mmio=true, target_as=0x7fffd938, attrs=...)
at ../softmmu/physmem.c:433
#4 0x55bdbdd1 in address_space_translate_cached
(cache=0x7fffed3d02e0, addr=0, xlat=0x7fffd9f0, plen=0x7fffd9e8,
is_write=false, attrs=...)
at ../softmmu/physmem.c:3388
#5 0x55bdc519 in address_space_lduw_internal_cached_slow
(cache=0x7fffed3d02e0, addr=0, attrs=..., result=0x0,
endian=DEVICE_LITTLE_ENDIAN)
at /home/devel/git/qemu/memory_ldst.c.inc:209
#6 0x55bdc6ac in address_space_lduw_le_cached_slow
(cache=0x7fffed3d02e0, addr=0, attrs=..., result=0x0) at
/home/devel/git/qemu/memory_ldst.c.inc:253
#7 0x55c71719 in address_space_lduw_le_cached
(cache=0x7fffed3d02e0, addr=0, attrs=..., result=0x0)
at /home/devel/git/qemu/include/exec/memory_ldst_cached.h.inc:35
#8 0x55c7196a in lduw_le_phys_cached (cache=0x7fffed3d02e0,
addr=0) at /home/devel/git/qemu/include/exec/memory_ldst_phys.h.inc:67
#9 0x55c728fd in virtio_lduw_phys_cached (vdev=0x57743720,
cache=0x7fffed3d02e0, pa=0) at
/home/devel/git/qemu/include/hw/virtio/virtio-access.h:166
#10 0x55c73485 in vring_used_flags_set_bit (vq=0x74ee5010,
mask=1) at ../hw/virtio/virtio.c:383
#11 0x55c736a8 in virtio_queue_split_set_notification
(vq=0x74ee5010, enable=0) at ../hw/virtio/virtio.c:433
#12 0x55c73896 in virtio_queue_set_notification
(vq=0x74ee5010, enable=0) at ../hw/virtio/virtio.c:490
#13 0x55c19064 in virtio_blk_handle_vq (s=0x57743720,
vq=0x74ee5010) at ../hw/block/virtio-blk.c:782
#14 0x55c191f5 in virtio_blk_handle_output (vdev=0x57743720,
vq=0x74ee5010) at ../hw/block/virtio-blk.c:819
#15 0x55c78453 in virtio_queue_notify_vq (vq=0x74ee5010) at
../hw/virtio/virtio.c:2315
#16 0x55c7b523 in virtio_queue_host_notifier_aio_poll_ready
(n=0x74ee5084) at ../hw/virtio/virtio.c:3516
#17 0x55eff158 in aio_dispatch_handler (ctx=0x5680fac0,
node=0x7fffeca5bbe0) at ../util/aio-posix.c:350
#18 0x55eff390 in aio_dispatch_handlers (ctx=0x5680fac0) at
../util/aio-posix.c:406
#19 0x55eff3ea in aio_dispatch (ctx=0x5680fac0) at
../util/aio-posix.c:416
#20 0x55f184eb in aio_ctx_dispatch (source=0x5680fac0,
callback=0x0, user_data=0x0) at ../util/async.c:311
#21 0x77b6b17d in g_main_context_dispatch () at
/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0
#22 0x55f299ed in glib_pollfds_poll () at ../util/main-loop.c:232
#23 0x55f29a6b in os_host_main_loop_wait (timeout=0) at
../util/main-loop.c:255
#24 0x55f29b7c in main_loop_wait (nonblocking=0) at
../util/main-loop.c:531
#25 0x55be097c in qemu_main_loop () at ../softmmu/runstate.c:727
#26 0x558367fa in main (argc=26, argv=0x7fffe058,
envp=0x7fffe130) at ../softmmu/main.c:50
The slpte is 0x0 and level is 3 which probably means the device is
kicked before it was attached to any IOMMU domain.
Bisecting points to the first bad commit:
commit 826cc32423db2a99d184dbf4f507c737d7e7a4ae
Author: Stefan Hajnoczi
Date: Tue Dec 7 13:23:31 2021 +
aio-posix: split poll check from ready handler
A wild guess is that this lead some false kick to the device, any
Re: [PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support
On Wed, Feb 23, 2022 at 8:09 AM Atish Patra wrote:
>
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra
Do you mind rebasing this on:
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.h | 5 ++
> target/riscv/cpu_bits.h | 39 +++
> target/riscv/csr.c | 107
> target/riscv/machine.c | 24 +
> 4 files changed, 175 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0741f9822cf0..e5c8694cf081 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -303,6 +303,11 @@ struct CPURISCVState {
> target_ulong spmbase;
> target_ulong upmmask;
> target_ulong upmbase;
> +
> +/* CSRs for execution enviornment configuration */
> +uint64_t menvcfg;
> +target_ulong senvcfg;
> +uint64_t henvcfg;
> #endif
>
> float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 89440241632a..58a0a8d69f72 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -202,6 +202,9 @@
> #define CSR_STVEC 0x105
> #define CSR_SCOUNTEREN 0x106
>
> +/* Supervisor Configuration CSRs */
> +#define CSR_SENVCFG 0x10A
> +
> /* Supervisor Trap Handling */
> #define CSR_SSCRATCH0x140
> #define CSR_SEPC0x141
> @@ -247,6 +250,10 @@
> #define CSR_HTIMEDELTA 0x605
> #define CSR_HTIMEDELTAH 0x615
>
> +/* Hypervisor Configuration CSRs */
> +#define CSR_HENVCFG 0x60A
> +#define CSR_HENVCFGH0x61A
> +
> /* Virtual CSRs */
> #define CSR_VSSTATUS0x200
> #define CSR_VSIE0x204
> @@ -290,6 +297,10 @@
> #define CSR_VSIEH 0x214
> #define CSR_VSIPH 0x254
>
> +/* Machine Configuration CSRs */
> +#define CSR_MENVCFG 0x30A
> +#define CSR_MENVCFGH0x31A
> +
> /* Enhanced Physical Memory Protection (ePMP) */
> #define CSR_MSECCFG 0x747
> #define CSR_MSECCFGH0x757
> @@ -654,6 +665,34 @@ typedef enum RISCVException {
> #define PM_EXT_CLEAN0x0002ULL
> #define PM_EXT_DIRTY0x0003ULL
>
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM BIT(0)
> +#define MENVCFG_CBIE (3UL << 4)
> +#define MENVCFG_CBCFE BIT(6)
> +#define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_PBMTE BIT(62)
> +#define MENVCFG_STCE BIT(63)
> +
> +/* For RV32 */
> +#define MENVCFGH_PBMTE BIT(30)
> +#define MENVCFGH_STCE BIT(31)
> +
> +#define SENVCFG_FIOM MENVCFG_FIOM
> +#define SENVCFG_CBIE MENVCFG_CBIE
> +#define SENVCFG_CBCFE MENVCFG_CBCFE
> +#define SENVCFG_CBZE MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM MENVCFG_FIOM
> +#define HENVCFG_CBIE MENVCFG_CBIE
> +#define HENVCFG_CBCFE MENVCFG_CBCFE
> +#define HENVCFG_CBZE MENVCFG_CBZE
> +#define HENVCFG_PBMTE MENVCFG_PBMTE
> +#define HENVCFG_STCE MENVCFG_STCE
> +
> +/* For RV32 */
> +#define HENVCFGH_PBMTE MENVCFGH_PBMTE
> +#define HENVCFGH_STCE MENVCFGH_STCE
> +
> /* Offsets for every pair of control bits per each priv level */
> #define XS_OFFSET0ULL
> #define U_OFFSET 2ULL
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 18fe17b62f51..ff7e36596447 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1366,6 +1366,101 @@ static RISCVException write_mtval(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +/* Execution environment configuration setup */
> +static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +*val = env->menvcfg;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> +uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
> MENVCFG_CBZE;
> +
> +if (riscv_cpu_mxl(env) == MXL_RV64) {
> +mask |= MENVCFG_PBMTE | MENVCFG_STCE;
> +}
> +env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
> +
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +*val = env->menvcfg >> 32;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> +
Re: [PATCH v1 2/2] riscv: opentitan: Connect opentitan SPI Host
On Wed, Feb 23, 2022 at 7:45 AM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> Conenct spi host[1/0] to opentitan.
>
> Signed-off-by: Wilfred Mallawa
> ---
> hw/riscv/opentitan.c | 42
> include/hw/riscv/opentitan.h | 16 --
> 2 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index aec7cfa33f..abbe08d4d4 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -1,7 +1,7 @@
> /*
> * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
> *
> - * Copyright (c) 2020 Western Digital
> + * Copyright (c) 2022 Western Digital
You don't need to update this
> *
> * Provides a board compatible with the OpenTitan FPGA platform:
> *
> @@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_FLASH] = { 0x2000, 0x8 },
> [IBEX_DEV_UART] = { 0x4000, 0x1000 },
> [IBEX_DEV_GPIO] = { 0x4004, 0x1000 },
> -[IBEX_DEV_SPI] ={ 0x4005, 0x1000 },
> +[IBEX_DEV_SPI_DEVICE] = { 0x4005, 0x1000 },
This will conflict with the latest RISC-V tree as:
"hw: riscv: opentitan: fixup SPI addresses" has been applied.
Alistair
> [IBEX_DEV_I2C] ={ 0x4008, 0x1000 },
> [IBEX_DEV_PATTGEN] ={ 0x400e, 0x1000 },
> [IBEX_DEV_TIMER] = { 0x4010, 0x1000 },
> [IBEX_DEV_SENSOR_CTRL] ={ 0x4011, 0x1000 },
> [IBEX_DEV_OTP_CTRL] = { 0x4013, 0x4000 },
> [IBEX_DEV_USBDEV] = { 0x4015, 0x1000 },
> +[IBEX_DEV_SPI_HOST0] = { 0x4030, 0x1000 },
> +[IBEX_DEV_SPI_HOST1] = { 0x4031, 0x1000 },
> [IBEX_DEV_PWRMGR] = { 0x4040, 0x1000 },
> [IBEX_DEV_RSTMGR] = { 0x4041, 0x1000 },
> [IBEX_DEV_CLKMGR] = { 0x4042, 0x1000 },
> @@ -118,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
> object_initialize_child(obj, "uart", >uart, TYPE_IBEX_UART);
>
> object_initialize_child(obj, "timer", >timer, TYPE_IBEX_TIMER);
> +
> +for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
> +object_initialize_child(obj, "spi_host[*]", >spi_host[i],
> +TYPE_IBEX_SPI_HOST);
> +}
> }
>
> static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> const MemMapEntry *memmap = ibex_memmap;
> +DeviceState *dev;
> +SysBusDevice *busdev;
> MachineState *ms = MACHINE(qdev_get_machine());
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -207,10 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
>qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
> IRQ_M_TIMER));
>
> +/* SPI-Hosts */
> +for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
> +dev = DEVICE(&(s->spi_host[i]));
> +if (!sysbus_realize(SYS_BUS_DEVICE(>spi_host[i]), errp)) {
> +return;
> +}
> +busdev = SYS_BUS_DEVICE(dev);
> +sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
> +
> +switch (i) {
> +case OPENTITAN_SPI_HOST0:
> +sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(>plic),
> +IBEX_SPI_HOST0_ERR_IRQ));
> +sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(>plic),
> +IBEX_SPI_HOST0_SPI_EVENT_IRQ));
> +break;
> +case OPENTITAN_SPI_HOST1:
> +sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(>plic),
> +IBEX_SPI_HOST1_ERR_IRQ));
> +sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(>plic),
> +IBEX_SPI_HOST1_SPI_EVENT_IRQ));
> +break;
> +}
> +}
> +
> create_unimplemented_device("riscv.lowrisc.ibex.gpio",
> memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
> -create_unimplemented_device("riscv.lowrisc.ibex.spi",
> -memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
> +create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
> +memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
> create_unimplemented_device("riscv.lowrisc.ibex.i2c",
> memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
> create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index eac35ef590..3a3f412ef8 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -1,7 +1,7 @@
> /*
> * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
> *
> - * Copyright (c) 2020 Western Digital
> + * Copyright (c) 2022
Re: [PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support
On Wed, Feb 23, 2022 at 8:09 AM Atish Patra wrote:
>
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 5 ++
> target/riscv/cpu_bits.h | 39 +++
> target/riscv/csr.c | 107
> target/riscv/machine.c | 24 +
> 4 files changed, 175 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0741f9822cf0..e5c8694cf081 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -303,6 +303,11 @@ struct CPURISCVState {
> target_ulong spmbase;
> target_ulong upmmask;
> target_ulong upmbase;
> +
> +/* CSRs for execution enviornment configuration */
> +uint64_t menvcfg;
> +target_ulong senvcfg;
> +uint64_t henvcfg;
> #endif
>
> float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 89440241632a..58a0a8d69f72 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -202,6 +202,9 @@
> #define CSR_STVEC 0x105
> #define CSR_SCOUNTEREN 0x106
>
> +/* Supervisor Configuration CSRs */
> +#define CSR_SENVCFG 0x10A
> +
> /* Supervisor Trap Handling */
> #define CSR_SSCRATCH0x140
> #define CSR_SEPC0x141
> @@ -247,6 +250,10 @@
> #define CSR_HTIMEDELTA 0x605
> #define CSR_HTIMEDELTAH 0x615
>
> +/* Hypervisor Configuration CSRs */
> +#define CSR_HENVCFG 0x60A
> +#define CSR_HENVCFGH0x61A
> +
> /* Virtual CSRs */
> #define CSR_VSSTATUS0x200
> #define CSR_VSIE0x204
> @@ -290,6 +297,10 @@
> #define CSR_VSIEH 0x214
> #define CSR_VSIPH 0x254
>
> +/* Machine Configuration CSRs */
> +#define CSR_MENVCFG 0x30A
> +#define CSR_MENVCFGH0x31A
> +
> /* Enhanced Physical Memory Protection (ePMP) */
> #define CSR_MSECCFG 0x747
> #define CSR_MSECCFGH0x757
> @@ -654,6 +665,34 @@ typedef enum RISCVException {
> #define PM_EXT_CLEAN0x0002ULL
> #define PM_EXT_DIRTY0x0003ULL
>
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM BIT(0)
> +#define MENVCFG_CBIE (3UL << 4)
> +#define MENVCFG_CBCFE BIT(6)
> +#define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_PBMTE BIT(62)
> +#define MENVCFG_STCE BIT(63)
> +
> +/* For RV32 */
> +#define MENVCFGH_PBMTE BIT(30)
> +#define MENVCFGH_STCE BIT(31)
> +
> +#define SENVCFG_FIOM MENVCFG_FIOM
> +#define SENVCFG_CBIE MENVCFG_CBIE
> +#define SENVCFG_CBCFE MENVCFG_CBCFE
> +#define SENVCFG_CBZE MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM MENVCFG_FIOM
> +#define HENVCFG_CBIE MENVCFG_CBIE
> +#define HENVCFG_CBCFE MENVCFG_CBCFE
> +#define HENVCFG_CBZE MENVCFG_CBZE
> +#define HENVCFG_PBMTE MENVCFG_PBMTE
> +#define HENVCFG_STCE MENVCFG_STCE
> +
> +/* For RV32 */
> +#define HENVCFGH_PBMTE MENVCFGH_PBMTE
> +#define HENVCFGH_STCE MENVCFGH_STCE
> +
> /* Offsets for every pair of control bits per each priv level */
> #define XS_OFFSET0ULL
> #define U_OFFSET 2ULL
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 18fe17b62f51..ff7e36596447 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1366,6 +1366,101 @@ static RISCVException write_mtval(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +/* Execution environment configuration setup */
> +static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +*val = env->menvcfg;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> +uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
> MENVCFG_CBZE;
> +
> +if (riscv_cpu_mxl(env) == MXL_RV64) {
> +mask |= MENVCFG_PBMTE | MENVCFG_STCE;
> +}
> +env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
> +
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> +*val = env->menvcfg >> 32;
> +return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> +uint64_t mask =
Re: [PATCH 28/31] vdpa: Expose VHOST_F_LOG_ALL on SVQ
On Tue, Feb 22, 2022 at 4:06 PM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 22, 2022 at 8:41 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/17 下午4:22, Eugenio Perez Martin 写道:
> > > On Thu, Feb 17, 2022 at 7:02 AM Jason Wang wrote:
> > >> On Wed, Feb 16, 2022 at 11:54 PM Eugenio Perez Martin
> > >> wrote:
> > >>> On Tue, Feb 8, 2022 at 9:25 AM Jason Wang wrote:
> >
> > 在 2022/2/1 下午7:45, Eugenio Perez Martin 写道:
> > > On Sun, Jan 30, 2022 at 7:50 AM Jason Wang
> > > wrote:
> > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > >>> SVQ is able to log the dirty bits by itself, so let's use it to not
> > >>> block migration.
> > >>>
> > >>> Also, ignore set and clear of VHOST_F_LOG_ALL on set_features if
> > >>> SVQ is
> > >>> enabled. Even if the device supports it, the reports would be
> > >>> nonsense
> > >>> because SVQ memory is in the qemu region.
> > >>>
> > >>> The log region is still allocated. Future changes might skip that,
> > >>> but
> > >>> this series is already long enough.
> > >>>
> > >>> Signed-off-by: Eugenio Pérez
> > >>> ---
> > >>> hw/virtio/vhost-vdpa.c | 20
> > >>> 1 file changed, 20 insertions(+)
> > >>>
> > >>> diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
> > >>> index fb0a338baa..75090d65e8 100644
> > >>> --- a/hw/virtio/vhost-vdpa.c
> > >>> +++ b/hw/virtio/vhost-vdpa.c
> > >>> @@ -1022,6 +1022,9 @@ static int vhost_vdpa_get_features(struct
> > >>> vhost_dev *dev, uint64_t *features)
> > >>> if (ret == 0 && v->shadow_vqs_enabled) {
> > >>> /* Filter only features that SVQ can offer to guest */
> > >>> vhost_svq_valid_guest_features(features);
> > >>> +
> > >>> +/* Add SVQ logging capabilities */
> > >>> +*features |= BIT_ULL(VHOST_F_LOG_ALL);
> > >>> }
> > >>>
> > >>> return ret;
> > >>> @@ -1039,8 +1042,25 @@ static int vhost_vdpa_set_features(struct
> > >>> vhost_dev *dev,
> > >>>
> > >>> if (v->shadow_vqs_enabled) {
> > >>> uint64_t dev_features, svq_features, acked_features;
> > >>> +uint8_t status = 0;
> > >>> bool ok;
> > >>>
> > >>> +ret = vhost_vdpa_call(dev, VHOST_VDPA_GET_STATUS, );
> > >>> +if (unlikely(ret)) {
> > >>> +return ret;
> > >>> +}
> > >>> +
> > >>> +if (status & VIRTIO_CONFIG_S_DRIVER_OK) {
> > >>> +/*
> > >>> + * vhost is trying to enable or disable _F_LOG, and
> > >>> the device
> > >>> + * would report wrong dirty pages. SVQ handles it.
> > >>> + */
> > >> I fail to understand this comment, I'd think there's no way to
> > >> disable
> > >> dirty page tracking for SVQ.
> > >>
> > > vhost_log_global_{start,stop} are called at the beginning and end of
> > > migration. To inform the device that it should start logging, they set
> > > or clean VHOST_F_LOG_ALL at vhost_dev_set_log.
> >
> > Yes, but for SVQ, we can't disable dirty page tracking, isn't it? The
> > only thing is to ignore or filter out the F_LOG_ALL and pretend to be
> > enabled and disabled.
> >
> > >>> Yes, that's what this patch does.
> > >>>
> > > While SVQ does not use VHOST_F_LOG_ALL, it exports the feature bit so
> > > vhost does not block migration. Maybe we need to look for another way
> > > to do this?
> >
> > I'm fine with filtering since it's much more simpler, but I fail to
> > understand why we need to check DRIVER_OK.
> >
> > >>> Ok maybe I can make that part more clear,
> > >>>
> > >>> Since both operations use vhost_vdpa_set_features we must just filter
> > >>> the one that actually sets or removes VHOST_F_LOG_ALL, without
> > >>> affecting other features.
> > >>>
> > >>> In practice, that means to not forward the set features after
> > >>> DRIVER_OK. The device is not expecting them anymore.
> > >> I wonder what happens if we don't do this.
> > >>
> > > If we simply delete the check vhost_dev_set_features will return an
> > > error, failing the start of the migration. More on this below.
> >
> >
> > Ok.
> >
> >
> > >
> > >> So kernel had this check:
> > >>
> > >> /*
> > >> * It's not allowed to change the features after they have
> > >> * been negotiated.
> > >> */
> > >> if (ops->get_status(vdpa) & VIRTIO_CONFIG_S_FEATURES_OK)
> > >> return -EBUSY;
> > >>
> > >> So is it FEATURES_OK actually?
> > >>
> > > Yes, FEATURES_OK seems more appropriate actually so I will switch to
> > > it for the next version.
> > >
> > > But it should be functionally equivalent, since
> > > vhost.c:vhost_dev_start sets both and the setting of _F_LOG_ALL cannot
> > > be concurrent with it.
> >
> >
> >
Re: [PATCH v4 47/47] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Lucas Coutinho Implement the following PowerISA v3.1 instuctions: lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form lxvrwx: Load VSX Vector Rightmost Word Indexed X-form lxvrdx: Load VSX Vector Rightmost Doubleword Indexed X-form stxvrbx: Store VSX Vector Rightmost Byte Indexed X-form stxvrhx: Store VSX Vector Rightmost Halfword Indexed X-form stxvrwx: Store VSX Vector Rightmost Word Indexed X-form stxvrdx: Store VSX Vector Rightmost Doubleword Indexed X-form Signed-off-by: Lucas Coutinho Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 8 +++ target/ppc/translate/vsx-impl.c.inc | 35 + 2 files changed, 43 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 46/47] target/ppc: implement plxssp/pstxssp
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Leandro Lupori Implement instructions plxssp/pstxssp and port lxssp/stxssp to decode tree. Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 + target/ppc/insn64.decode| 6 ++ target/ppc/translate.c | 29 +++-- target/ppc/translate/vsx-impl.c.inc | 93 +++-- 4 files changed, 62 insertions(+), 68 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 45/47] target/ppc: implement plxsd/pstxsd
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Leandro Lupori Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode tree. Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 2 ++ target/ppc/insn64.decode| 10 ++ target/ppc/translate.c | 14 ++-- target/ppc/translate/vsx-impl.c.inc | 55 +++-- 4 files changed, 67 insertions(+), 14 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 44/47] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 21 +++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode| 11 +++---
target/ppc/translate/vsx-impl.c.inc | 31 -
4 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 777bd7..d77900fff1 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2790,6 +2790,27 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64,
VsrH(3), VsrD(0), 1)
VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1),
0)
VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i),
0)
+void helper_XVCVSPBF16(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
+{
+ppc_vsr_t t = { };
+int i;
+
+helper_reset_fpstatus(env);
+for (i = 0; i < 4; i++) {
+if (unlikely(float32_is_signaling_nan(xb->VsrW(i), >fp_status))) {
+float_invalid_op_vxsnan(env, GETPC());
+t.VsrH(2 * i + 1) = float32_to_bfloat16(
+float32_snan_to_qnan(xb->VsrW(i)), >fp_status);
+} else {
+t.VsrH(2 * i + 1) =
+float32_to_bfloat16(xb->VsrW(i), >fp_status);
+}
+}
Do not check for snan first; use float_flag_invalid_snan.
And you can move that check outside the loop, before the
writeback of t to *xt.
r~
Re: [PATCH 18/31] vhost: Shadow virtqueue buffers forwarding
On Tue, Feb 22, 2022 at 4:56 PM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 22, 2022 at 8:26 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/21 下午4:15, Eugenio Perez Martin 写道:
> > > On Mon, Feb 21, 2022 at 8:44 AM Jason Wang wrote:
> > >>
> > >> 在 2022/2/17 下午8:48, Eugenio Perez Martin 写道:
> > >>> On Tue, Feb 8, 2022 at 9:16 AM Jason Wang wrote:
> > 在 2022/2/1 下午7:25, Eugenio Perez Martin 写道:
> > > On Sun, Jan 30, 2022 at 7:47 AM Jason Wang
> > > wrote:
> > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > >>> @@ -272,6 +590,28 @@ void
> > >>> vhost_svq_set_svq_kick_fd(VhostShadowVirtqueue *svq, int
> > >>> svq_kick_fd)
> > >>> void vhost_svq_stop(VhostShadowVirtqueue *svq)
> > >>> {
> > >>> event_notifier_set_handler(>svq_kick, NULL);
> > >>> +g_autofree VirtQueueElement *next_avail_elem = NULL;
> > >>> +
> > >>> +if (!svq->vq) {
> > >>> +return;
> > >>> +}
> > >>> +
> > >>> +/* Send all pending used descriptors to guest */
> > >>> +vhost_svq_flush(svq, false);
> > >> Do we need to wait for all the pending descriptors to be completed
> > >> here?
> > >>
> > > No, this function does not wait, it only completes the forwarding of
> > > the *used* descriptors.
> > >
> > > The best example is the net rx queue in my opinion. This call will
> > > check SVQ's vring used_idx and will forward the last used descriptors
> > > if any, but all available descriptors will remain as available for
> > > qemu's VQ code.
> > >
> > > To skip it would miss those last rx descriptors in migration.
> > >
> > > Thanks!
> > So it's probably to not the best place to ask. It's more about the
> > inflight descriptors so it should be TX instead of RX.
> >
> > I can imagine the migration last phase, we should stop the vhost-vDPA
> > before calling vhost_svq_stop(). Then we should be fine regardless of
> > inflight descriptors.
> >
> > >>> I think I'm still missing something here.
> > >>>
> > >>> To be on the same page. Regarding tx this could cause repeated tx
> > >>> frames (one at source and other at destination), but never a missed
> > >>> buffer not transmitted. The "stop before" could be interpreted as "SVQ
> > >>> is not forwarding available buffers anymore". Would that work?
> > >>
> > >> Right, but this only work if
> > >>
> > >> 1) a flush to make sure TX DMA for inflight descriptors are all completed
> > >>
> > >> 2) just mark all inflight descriptor used
> > >>
> > > It currently trusts on the reverse: Buffers not marked as used (by the
> > > device) will be available in the destination, so expect
> > > retransmissions.
> >
> >
> > I may miss something but I think we do migrate last_avail_idx. So there
> > won't be a re-transmission, since we depend on qemu virtqueue code to
> > deal with vring base?
> >
>
> On stop, vhost_virtqueue_stop calls vhost_vdpa_get_vring_base. In SVQ
> mode, it returns last_used_idx. After that, vhost.c code set VirtQueue
> last_avail_idx == last_used_idx, and it's migrated after that if I'm
> not wrong.
Ok, I miss these details in the review. I suggest mentioning this in
the change log and add a comment in vhost_vdpa_get_vring_base().
>
> vhost kernel migrates last_avail_idx, but it makes rx buffers
> available on-demand, unlike SVQ. So it does not need to unwind buffers
> or anything like that. Because of how SVQ works with the rx queue,
> this is not possible, since the destination will find no available
> buffers for rx. And for tx you already have described the scenario.
>
> In other words, we cannot see SVQ as a vhost device in that regard:
> SVQ looks for total drain (as "make all guest's buffers available for
> the device ASAP") vs the vhost device which can live with a lot of
> available ones and it will use them on demand. Same problem as
> masking. So the difference in behavior is justified in my opinion, and
> it can be improved in the future with the vdpa in-flight descriptors.
>
> If we restore the state that way in a virtio-net device, it will see
> the available ones as expected, not as in-flight.
>
> Another possibility is to transform all of these into in-flight ones,
> but I feel it would create problems. Can we migrate all rx queues as
> in-flight, with 0 bytes written? Is it worth it?
To clarify, for inflight I meant from the device point of view, that
is [last_used_idx, last_avail_idx).
So for RX and SVQ, it should be as simple as stop forwarding buffers
since last_used_idx should be the same as last_avail_idx in this case.
(Though technically the rx buffer might be modified by the NIC).
> I didn't investigate
> that path too much, but I think the virtio-net emulated device does
> not support that at the moment. If I'm not wrong, we should copy
> something like the body of virtio_blk_load_device if we want to go
> that route.
>
> The current approach might be too
Re: [PATCH 18/31] vhost: Shadow virtqueue buffers forwarding
On Wed, Feb 23, 2022 at 3:01 AM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 8, 2022 at 9:11 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/2 上午1:08, Eugenio Perez Martin 写道:
> > > On Sun, Jan 30, 2022 at 5:43 AM Jason Wang wrote:
> > >>
> > >> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > >>> Initial version of shadow virtqueue that actually forward buffers. There
> > >>> is no iommu support at the moment, and that will be addressed in future
> > >>> patches of this series. Since all vhost-vdpa devices use forced IOMMU,
> > >>> this means that SVQ is not usable at this point of the series on any
> > >>> device.
> > >>>
> > >>> For simplicity it only supports modern devices, that expects vring
> > >>> in little endian, with split ring and no event idx or indirect
> > >>> descriptors. Support for them will not be added in this series.
> > >>>
> > >>> It reuses the VirtQueue code for the device part. The driver part is
> > >>> based on Linux's virtio_ring driver, but with stripped functionality
> > >>> and optimizations so it's easier to review.
> > >>>
> > >>> However, forwarding buffers have some particular pieces: One of the most
> > >>> unexpected ones is that a guest's buffer can expand through more than
> > >>> one descriptor in SVQ. While this is handled gracefully by qemu's
> > >>> emulated virtio devices, it may cause unexpected SVQ queue full. This
> > >>> patch also solves it by checking for this condition at both guest's
> > >>> kicks and device's calls. The code may be more elegant in the future if
> > >>> SVQ code runs in its own iocontext.
> > >>>
> > >>> Signed-off-by: Eugenio Pérez
> > >>> ---
> > >>>hw/virtio/vhost-shadow-virtqueue.h | 2 +
> > >>>hw/virtio/vhost-shadow-virtqueue.c | 365
> > >>> -
> > >>>hw/virtio/vhost-vdpa.c | 111 -
> > >>>3 files changed, 462 insertions(+), 16 deletions(-)
> > >>>
> > >>> diff --git a/hw/virtio/vhost-shadow-virtqueue.h
> > >>> b/hw/virtio/vhost-shadow-virtqueue.h
> > >>> index 39aef5ffdf..19c934af49 100644
> > >>> --- a/hw/virtio/vhost-shadow-virtqueue.h
> > >>> +++ b/hw/virtio/vhost-shadow-virtqueue.h
> > >>> @@ -33,6 +33,8 @@ uint16_t vhost_svq_get_num(const VhostShadowVirtqueue
> > >>> *svq);
> > >>>size_t vhost_svq_driver_area_size(const VhostShadowVirtqueue *svq);
> > >>>size_t vhost_svq_device_area_size(const VhostShadowVirtqueue *svq);
> > >>>
> > >>> +void vhost_svq_start(VhostShadowVirtqueue *svq, VirtIODevice *vdev,
> > >>> + VirtQueue *vq);
> > >>>void vhost_svq_stop(VhostShadowVirtqueue *svq);
> > >>>
> > >>>VhostShadowVirtqueue *vhost_svq_new(uint16_t qsize);
> > >>> diff --git a/hw/virtio/vhost-shadow-virtqueue.c
> > >>> b/hw/virtio/vhost-shadow-virtqueue.c
> > >>> index 7c168075d7..a1a404f68f 100644
> > >>> --- a/hw/virtio/vhost-shadow-virtqueue.c
> > >>> +++ b/hw/virtio/vhost-shadow-virtqueue.c
> > >>> @@ -9,6 +9,8 @@
> > >>>
> > >>>#include "qemu/osdep.h"
> > >>>#include "hw/virtio/vhost-shadow-virtqueue.h"
> > >>> +#include "hw/virtio/vhost.h"
> > >>> +#include "hw/virtio/virtio-access.h"
> > >>>#include "standard-headers/linux/vhost_types.h"
> > >>>
> > >>>#include "qemu/error-report.h"
> > >>> @@ -36,6 +38,33 @@ typedef struct VhostShadowVirtqueue {
> > >>>
> > >>>/* Guest's call notifier, where SVQ calls guest. */
> > >>>EventNotifier svq_call;
> > >>> +
> > >>> +/* Virtio queue shadowing */
> > >>> +VirtQueue *vq;
> > >>> +
> > >>> +/* Virtio device */
> > >>> +VirtIODevice *vdev;
> > >>> +
> > >>> +/* Map for returning guest's descriptors */
> > >>> +VirtQueueElement **ring_id_maps;
> > >>> +
> > >>> +/* Next VirtQueue element that guest made available */
> > >>> +VirtQueueElement *next_guest_avail_elem;
> > >>> +
> > >>> +/* Next head to expose to device */
> > >>> +uint16_t avail_idx_shadow;
> > >>> +
> > >>> +/* Next free descriptor */
> > >>> +uint16_t free_head;
> > >>> +
> > >>> +/* Last seen used idx */
> > >>> +uint16_t shadow_used_idx;
> > >>> +
> > >>> +/* Next head to consume from device */
> > >>> +uint16_t last_used_idx;
> > >>> +
> > >>> +/* Cache for the exposed notification flag */
> > >>> +bool notification;
> > >>>} VhostShadowVirtqueue;
> > >>>
> > >>>#define INVALID_SVQ_KICK_FD -1
> > >>> @@ -148,30 +177,294 @@ bool vhost_svq_ack_guest_features(uint64_t
> > >>> dev_features,
> > >>>return true;
> > >>>}
> > >>>
> > >>> -/* Forward guest notifications */
> > >>> -static void vhost_handle_guest_kick(EventNotifier *n)
> > >>> +/**
> > >>> + * Number of descriptors that SVQ can make available from the guest.
> > >>> + *
> > >>> + * @svq The svq
> > >>> + */
> > >>> +static uint16_t vhost_svq_available_slots(const VhostShadowVirtqueue
> > >>> *svq)
> > >>>{
> > >>> -VhostShadowVirtqueue *svq = container_of(n, VhostShadowVirtqueue,
> > >>> -
Re: [PATCH v3] tests/qtest: add qtests for npcm7xx sdhci
On Mon, Feb 21, 2022 at 5:30 AM Peter Maydell wrote: > On Wed, 16 Feb 2022 at 17:30, Peter Maydell > wrote: > > > > On Tue, 8 Feb 2022 at 18:18, Patrick Venture wrote: > > > > > > From: Shengtan Mao > > > > > > Reviewed-by: Hao Wu > > > Reviewed-by: Chris Rauer > > > Signed-off-by: Shengtan Mao > > > Signed-off-by: Patrick Venture > > > --- > > > > > > > > Applied to target-arm.next, thanks. > > This hits assertions in some of the CI jobs, eg: > https://gitlab.com/qemu-project/qemu/-/jobs/2116932769 > > 258/717 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_sdhci-test INTERRUPT > 643.16s killed by signal 6 SIGABRT > ― ✀ > ― > stderr: > ** Message: 06:06:50.205: /tmp/sdhci_F7ETH1 > ** > ERROR:../tests/qtest/npcm7xx_sdhci-test.c:101:sdwrite_read: assertion > failed: (!strcmp(rmsg, msg)) > > ―― > ...terminated. > > so I've dropped it again. > I'm sorry to hear that, I'll have to pick up some cycles in a week or so and see if I can reproduce the issue. > > thanks > -- PMM >
Re: [PATCH v4 43/47] target/ppc: Implement xs{max,min}cqp
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 2 ++ 4 files changed, 9 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 42/47] target/ppc: Refactor VSX_MAX_MINC helper
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
-#define VSX_MAX_MINC(name, max) \
+#define VSX_MAX_MINC(name, op, tp, fld) \
void helper_##name(CPUPPCState *env,
\
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
\
{
\
ppc_vsr_t t = { };
\
bool vxsnan_flag = false, vex_flag = false;
\
\
-if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
- float64_is_any_nan(xb->VsrD(0 { \
-if (float64_is_signaling_nan(xa->VsrD(0), >fp_status) || \
-float64_is_signaling_nan(xb->VsrD(0), >fp_status)) { \
+if (unlikely(tp##_is_any_nan(xa->fld) || \
+ tp##_is_any_nan(xb->fld))) { \
+if (tp##_is_signaling_nan(xa->fld, >fp_status) ||\
+tp##_is_signaling_nan(xb->fld, >fp_status)) {\
vxsnan_flag = true;
\
}
\
-t.VsrD(0) = xb->VsrD(0); \
-} else if ((max &&\
- !float64_lt(xa->VsrD(0), xb->VsrD(0), >fp_status)) || \
- (!max && \
- float64_lt(xa->VsrD(0), xb->VsrD(0), >fp_status))) { \
-t.VsrD(0) = xa->VsrD(0); \
+t.fld = xb->fld; \
} else {
\
-t.VsrD(0) = xb->VsrD(0); \
+t.fld = tp##_##op(xa->fld, xb->fld, >fp_status); \
}
\
\
vex_flag = fpscr_ve & vxsnan_flag;
\
I think this would be simpler to utilize the result of the compare vs nans:
bool first;
if (max) {
first = tp##_le_quiet(xb->fld, xa->fld, status);
} else {
first = tp##_lt_quiet(xa->fld, xb->fld, status);
}
if (first) {
t.fld = xa->fld;
} else {
t.fld = xb->fld;
if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
xt = *t;
r~
Re: [PATCH v4 41/47] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Also, fixes these instructions not being capitalized. Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 8 target/ppc/helper.h | 8 target/ppc/translate/vsx-impl.c.inc | 30 - 3 files changed, 12 insertions(+), 34 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 40/47] target/ppc: Move xscmp{eq, ge, gt}dp to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 7 +++ target/ppc/helper.h | 6 +++--- target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 28 +--- target/ppc/translate/vsx-ops.c.inc | 3 --- 5 files changed, 34 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 39/47] target/ppc: Implement xscmp{eq,ge,gt}qp
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Víctor Colombo Signed-off-by: Víctor Colombo Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 4 target/ppc/helper.h | 3 +++ target/ppc/insn32.decode| 3 +++ target/ppc/translate/vsx-impl.c.inc | 31 + 4 files changed, 41 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 38/47] target/ppc: Refactor VSX_SCALAR_CMP_DP
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and
prepare the helper to be used for quadword comparisons.
Signed-off-by: Víctor Colombo
Signed-off-by: Matheus Ferst
---
target/ppc/fpu_helper.c | 31 ++-
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9b034d1fe4..5ebbcfe3b7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2265,28 +2265,30 @@ VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
/*
- * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
+ * VSX_SCALAR_CMP - VSX scalar floating point compare
* op- instruction mnemonic
+ * tp- type
* cmp - comparison operation
* exp - expected result of comparison
+ * fld - vsr_t field
* svxvc - set VXVC bit
*/
-#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc)\
+#define VSX_SCALAR_CMP(op, tp, cmp, fld, exp, svxvc) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt,
\
ppc_vsr_t *xa, ppc_vsr_t *xb)
\
{
\
-ppc_vsr_t t = *xt;\
+ppc_vsr_t t = { };\
bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false;
\
\
-if (float64_is_signaling_nan(xa->VsrD(0), >fp_status) || \
-float64_is_signaling_nan(xb->VsrD(0), >fp_status)) { \
+if (tp##_is_signaling_nan(xa->fld, >fp_status) ||\
+tp##_is_signaling_nan(xb->fld, >fp_status)) {\
vxsnan_flag = true;
\
if (fpscr_ve == 0 && svxvc) {
\
vxvc_flag = true;
\
}
\
} else if (svxvc) {
\
-vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), >fp_status) || \
-float64_is_quiet_nan(xb->VsrD(0), >fp_status); \
+vxvc_flag = tp##_is_quiet_nan(xa->fld, >fp_status) ||\
+tp##_is_quiet_nan(xb->fld, >fp_status); \
}
Note that this can be simplified further, using the full FloatRelation result and
float_flag_invalid_snan.
Note that do_scalar_cmp gets half-way there, only checking for NaNs once we have
float_relation_unordered as a comparision result. But it could go further and check
float_flag_invalid_snan and drop all of the other checks vs snan and qnan.
r~
Re: [PATCH v4 36/47] target/ppc: Implement xvtlsbb instruction
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: +tcg_gen_and_i64(tmp, mask, xb); +tcg_gen_movcond_i64(TCG_COND_EQ, all_true, tmp, +mask, all_true, zero); + +tcg_gen_andc_i64(tmp, mask, xb); +tcg_gen_movcond_i64(TCG_COND_EQ, all_false, tmp, +mask, all_false, zero); I would unroll this and use fewer conditions. t0 = mask & xb[0] t1 = mask & xb[1] o2 = t0 | t1 a2 = t0 & t1 o2 = (o2 == 0) << 1 a2 = (a2 == mask) << 3 crf = o2 | a2 r~
Re: [PATCH v4 35/47] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Implement the following PowerISA v3.0 instuctions: xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd] xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] xsnmsubqp[o]: VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 42 + target/ppc/helper.h | 9 +++ target/ppc/insn32.decode| 4 +++ target/ppc/translate/vsx-impl.c.inc | 25 + 4 files changed, 80 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 34/47] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: +static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3, +void (gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr)) Missing a * before gen_helper. Somewhat surprised this compiled... +static bool do_xsmadd_XX3(DisasContext *ctx, arg_XX3 *a, bool type_a, +void (gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr)) Likewise. Otherwise, Reviewed-by: Richard Henderson r~
Re: [PATCH v4 33/47] target/ppc: Implement xxgenpcv[bhwd]m instruction
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+#define XXGENPCV(NAME, SZ) \
+void helper_##NAME(ppc_vsr_t *t, ppc_vsr_t *b, target_ulong imm)\
+{ \
+ppc_vsr_t tmp = { .u64 = { 0, 0 } };\
+\
+switch (imm) { \
You should split the helper and not pass down imm.
r~
Re: [PATCH v4 32/47] target/ppc: Implement xxeval
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+tcg_gen_movi_i64(disj, 0);
The init here means there's one more OR generated than necessary. Though perhaps it gets
folded away...
+
+/* Iterate over set bits from the least to the most significant bit */
+while (imm) {
+/*
+ * Get the next bit to be processed with ctz64. Invert the result of
+ * ctz64 to match the indexing used by PowerISA.
+ */
+bit = 7 - ctz64(imm);
+if (bit & 0x4) {
+tcg_gen_mov_i64(conj, a);
+} else {
+tcg_gen_not_i64(conj, a);
+}
+if (bit & 0x2) {
+tcg_gen_and_i64(conj, conj, b);
+} else {
+tcg_gen_andc_i64(conj, conj, b);
+}
+if (bit & 0x1) {
+tcg_gen_and_i64(conj, conj, c);
+} else {
+tcg_gen_andc_i64(conj, conj, c);
+}
+tcg_gen_or_i64(disj, disj, conj);
+
+/* Unset the least significant bit that is set */
+imm &= imm - 1;
I guess this works, though it's not nearly optimal.
It's certainly a good fallback for the out-of-line function.
Table 145 has the folded equivalent functions. Implementing all 256 of them as is, twice,
for both i64 and vec could be tedious. But we could cherry-pick the easiest, or most
commonly used, or something, and let all other imm values go through to out-of-line function.
r~
Re: [PATCH v4 31/47] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Following the implementation of tcg_gen_gvec_3i, add a four-vector and immediate operand expansion method. Signed-off-by: Matheus Ferst --- include/tcg/tcg-op-gvec.h | 22 ++ tcg/tcg-op-gvec.c | 146 ++ 2 files changed, 168 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 30/47] target/ppc: Implement xxpermx instruction
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 1 + target/ppc/insn64.decode| 8 target/ppc/int_helper.c | 20 target/ppc/translate/vsx-impl.c.inc | 22 ++ 4 files changed, 51 insertions(+) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 28/47] target/ppc: move xxperm/xxpermr to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 21 --- target/ppc/helper.h | 2 -- target/ppc/insn32.decode| 5 target/ppc/translate/vsx-impl.c.inc | 42 +++-- target/ppc/translate/vsx-ops.c.inc | 2 -- 5 files changed, 45 insertions(+), 27 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 29/47] target/ppc: Move xxpermdi to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 4 ++ target/ppc/translate/vsx-impl.c.inc | 71 + target/ppc/translate/vsx-ops.c.inc | 2 - 3 files changed, 36 insertions(+), 41 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 27/47] target/ppc: Move xxsel to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 6 target/ppc/insn64.decode| 24 target/ppc/translate/vsx-impl.c.inc | 20 ++ target/ppc/translate/vsx-ops.c.inc | 43 - 4 files changed, 26 insertions(+), 67 deletions(-) Reviewed-by: Richard Henderson r~
[PATCH v3] target/riscv: Add isa extenstion strings to the device tree
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by appending the available ISA extensions
to the "riscv,isa" string if it is enabled so that kernel can process it.
[1] https://lkml.org/lkml/2022/2/15/263
Suggested-by: Heiko Stubner
Signed-off-by: Atish Patra
---
Changes from v2->v3:
1. Used g_strconcat to replace snprintf & a max isa string length as
suggested by Anup.
2. I have not included the Tested-by Tag from Heiko because the
implementation changed from v2 to v3.
Changes from v1->v2:
1. Improved the code redability by using arrays instead of individual check
---
target/riscv/cpu.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0a40b83e7a8..2c7ff6ef555a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,12 @@
/* RISC-V CPU definitions */
+/* This includes the null terminated character '\0' */
+struct isa_ext_data {
+const char *name;
+bool enabled;
+};
+
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
@@ -881,6 +887,28 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
device_class_set_props(dc, riscv_cpu_properties);
}
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int
max_str_len)
+{
+char *old = *isa_str;
+char *new = *isa_str;
+int i;
+struct isa_ext_data isa_edata_arr[] = {
+{ "svpbmt", cpu->cfg.ext_svpbmt },
+{ "svinval", cpu->cfg.ext_svinval },
+{ "svnapot", cpu->cfg.ext_svnapot },
+};
+
+for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+if (isa_edata_arr[i].enabled) {
+new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
+g_free(old);
+old = new;
+}
+}
+
+*isa_str = new;
+}
+
char *riscv_isa_string(RISCVCPU *cpu)
{
int i;
@@ -893,6 +921,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
}
}
*p = '\0';
+riscv_isa_string_ext(cpu, _str, maxlen);
return isa_str;
}
--
2.30.2
Re: [PATCH v4 26/47] target/ppc: Move vsel and vperm/vpermr to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/helper.h | 5 +-- target/ppc/insn32.decode| 5 +++ target/ppc/int_helper.c | 13 +- target/ppc/translate/vmx-impl.c.inc | 69 ++--- target/ppc/translate/vmx-ops.c.inc | 2 - 5 files changed, 62 insertions(+), 32 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 25/47] target/ppc: implement vrlq
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v4: - New in v4. --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 49 + 2 files changed, 50 insertions(+) ... +tcg_gen_andi_i64(n, n, 0x7F); + +tcg_gen_mov_i64(t0, ah); +tcg_gen_movcond_i64(TCG_COND_GE, ah, n, sf, al, ah); +tcg_gen_movcond_i64(TCG_COND_GE, al, n, sf, t0, al); Similar comment re (n & 64) != 0. Otherwise, Reviewed-by: Richard Henderson
Re: [PATCH v4 24/47] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
+ TCGv_vec vrb)
+{
+TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt);
+
+/* Create the mask */
+mask = do_vrl_mask_vec(vece, vrb);
+
+/* Extract n */
+tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
+tcg_gen_and_vec(vece, n, vrb, n);
+
+/* Rotate and mask */
+tcg_gen_rotlv_vec(vece, vrt, vra, n);
Note that rotlv does the masking itself:
/*
* Expand D = A << (B % element bits)
*
* Unlike scalar shifts, where it is easy for the target front end
* to include the modulo as part of the expansion. If the target
* naturally includes the modulo as part of the operation, great!
* If the target has some other behaviour from out-of-range shifts,
* then it could not use this function anyway, and would need to
* do it's own expansion with custom functions.
*/
+static bool do_vrlnm(DisasContext *ctx, arg_VX *a, int vece)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
+INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
+};
Where is sari used?
r~
Re: [PATCH v2] target/riscv: Add isa extenstion strings to the device tree
On Tue, Feb 15, 2022 at 7:19 PM Anup Patel wrote:
>
> On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote:
> >
> > The Linux kernel parses the ISA extensions from "riscv,isa" DT
> > property. It used to parse only the single letter base extensions
> > until now. A generic ISA extension parsing framework was proposed[1]
> > recently that can parse multi-letter ISA extensions as well.
> >
> > Generate the extended ISA string by appending the available ISA extensions
> > to the "riscv,isa" string if it is enabled so that kernel can process it.
> >
> > [1] https://lkml.org/lkml/2022/2/15/263
> >
> > Suggested-by: Heiko Stubner
> > Signed-off-by: Atish Patra
> > ---
> > Changes from v1->v2:
> > 1. Improved the code redability by using arrays instead of individual check
> > ---
> > target/riscv/cpu.c | 35 ++-
> > 1 file changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index b0a40b83e7a8..9bf8923f164b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -34,6 +34,13 @@
> >
> > /* RISC-V CPU definitions */
> >
> > +/* This includes the null terminated character '\0' */
> > +#define MAX_ISA_EXT_LEN 256
> > +struct isa_ext_data {
> > +const char *name;
> > +bool enabled;
> > +};
> > +
> > static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
> >
> > const char * const riscv_int_regnames[] = {
> > @@ -881,10 +888,35 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> > *data)
> > device_class_set_props(dc, riscv_cpu_properties);
> > }
> >
> > +static void riscv_isa_string_ext(RISCVCPU *cpu, char *isa_str, int
> > max_str_len)
> > +{
> > +int offset = strnlen(isa_str, max_str_len);
> > +int i;
> > +struct isa_ext_data isa_edata_arr[] = {
> > +{ "svpbmt", cpu->cfg.ext_svpbmt },
> > +{ "svinval", cpu->cfg.ext_svinval },
> > +{ "svnapot", cpu->cfg.ext_svnapot },
> > +};
> > +
> > +for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> > +if (!isa_edata_arr[i].enabled) {
> > +continue;
> > +}
> > +/* check available space */
> > +if ((offset + strlen(isa_edata_arr[i].name) + 1) > max_str_len) {
> > +qemu_log("No space left to append isa extension");
> > +return;
> > +}
> > +offset += snprintf(isa_str + offset, max_str_len, "_%s",
> > + isa_edata_arr[i].name);
>
> You don't need to use snprintf() and MAX_ISA_EXT_LEN if you
> use g_strconcat() for creating new concat strings and freeing
> original string using g_free().
>
Yeah. That is better. I have reimplemented this part in v3.
> Regards,
> Anup
>
> > +}
> > +}
> > +
> > char *riscv_isa_string(RISCVCPU *cpu)
> > {
> > int i;
> > -const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
> > +const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) +
> > + MAX_ISA_EXT_LEN;
> > char *isa_str = g_new(char, maxlen);
> > char *p = isa_str + snprintf(isa_str, maxlen, "rv%d",
> > TARGET_LONG_BITS);
> > for (i = 0; i < sizeof(riscv_exts); i++) {
> > @@ -893,6 +925,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> > }
> > }
> > *p = '\0';
> > +riscv_isa_string_ext(cpu, isa_str, maxlen);
> > return isa_str;
> > }
> >
> > --
> > 2.30.2
> >
> >
>
--
Regards,
Atish
Re: [PATCH v4 22/47] target/ppc: implement vsraq
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v4: - New in v4. --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 17 + 2 files changed, 14 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 20/47] target/ppc: implement vslq
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
v4:
- New in v4.
---
target/ppc/insn32.decode| 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 88baebe35e..3799065508 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -473,6 +473,7 @@ VSLB000100 . . . 0010100@VX
VSLH000100 . . . 00101000100@VX
VSLW000100 . . . 0011100@VX
VSLD000100 . . . 10111000100@VX
+VSLQ000100 . . . 0010101@VX
VSRB000100 . . . 0100100@VX
VSRH000100 . . . 01001000100@VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index ec4f0e7654..ca98a545ef 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16,
tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64,
tcg_gen_gvec_sarv);
+static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
+{
+TCGv_i64 hi, lo, tmp, n, sf = tcg_constant_i64(64);
+
+REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+REQUIRE_VECTOR(ctx);
+
+n = tcg_temp_new_i64();
+hi = tcg_temp_new_i64();
+lo = tcg_temp_new_i64();
+tmp = tcg_const_i64(0);
+
+get_avr64(lo, a->vra, false);
+get_avr64(hi, a->vra, true);
+
+get_avr64(n, a->vrb, true);
+tcg_gen_andi_i64(n, n, 0x7F);
+
+tcg_gen_movcond_i64(TCG_COND_GE, hi, n, sf, lo, hi);
+tcg_gen_movcond_i64(TCG_COND_GE, lo, n, sf, tmp, lo);
Since you have to mask twice anyway, better use (n & 64) != 0.
Otherwise,
Reviewed-by: Richard Henderson
r~
Re: [PATCH v4 23/47] target/ppc: move vrl[bhwd] to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v4: - New in v4. --- target/ppc/insn32.decode| 5 + target/ppc/translate/vmx-impl.c.inc | 13 + target/ppc/translate/vmx-ops.c.inc | 6 ++ 3 files changed, 12 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v7 2/2] drivers/virt: vmgenid: add vm generation id driver
Hey again,
On Tue, Feb 22, 2022 at 10:24 PM Jason A. Donenfeld wrote:
> This thread seems to be long dead, but I couldn't figure out what
> happened to the ideas in it. I'm specifically interested in this part:
>
> On Wed, Feb 24, 2021 at 9:48 AM Adrian Catangiu wrote:
> > +static void vmgenid_acpi_notify(struct acpi_device *device, u32 event)
> > +{
> > + uuid_t old_uuid;
> > +
> > + if (!device || acpi_driver_data(device) != _data) {
> > + pr_err("VMGENID notify with unexpected driver private
> > data\n");
> > + return;
> > + }
> > +
> > + /* update VM Generation UUID */
> > + old_uuid = vmgenid_data.uuid;
> > + memcpy_fromio(_data.uuid, vmgenid_data.uuid_iomap,
> > sizeof(uuid_t));
> > +
> > + if (memcmp(_uuid, _data.uuid, sizeof(uuid_t))) {
> > + /* HW uuid updated */
> > + sysgenid_bump_generation();
> > + add_device_randomness(_data.uuid, sizeof(uuid_t));
> > + }
> > +}
>
> As Jann mentioned in an earlier email, we probably want this to
> immediately reseed the crng, not just dump it into
> add_device_randomness alone. But either way, the general idea seems
> interesting to me. As far as I can tell, QEMU still supports this. Was
> it not deemed to be sufficiently interesting?
>
> Thanks,
> Jason
Well I cleaned up this v7 and refactored it into something along the
lines of what I'm thinking. I don't yet know enough about this general
problem space to propose the patch and I haven't tested it either, but
in case you're curious, something along the lines of what I'm thinking
about lives at
https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git/commit/?h=jd/vmgenid
if you (or somebody else) feels inclined to pick this up.
Looking forward to learning more from you in general, though, about
what the deal is with the VM gen ID, and if this is a real thing or
not.
Regards,
Jason
[PATCH v4 6/6] target/riscv: Enable privileged spec version 1.12
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8 +---
target/riscv/csr.c | 5 +
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2668f9c358b2..1c72dfffdc61 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
-set_priv_version(env, PRIV_VERSION_1_11_0);
+set_priv_version(env, PRIV_VERSION_1_12_0);
}
#if defined(TARGET_RISCV64)
@@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.priv_spec) {
-if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+priv_version = PRIV_VERSION_1_12_0;
+} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
@@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (priv_version) {
set_priv_version(env, priv_version);
} else if (!env->priv_ver) {
-set_priv_version(env, PRIV_VERSION_1_11_0);
+set_priv_version(env, PRIV_VERSION_1_12_0);
}
if (cpu->cfg.mmu) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ff7e36596447..1c70c19cf9bd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2886,6 +2886,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
int read_only = get_field(csrno, 0xC00) == 3;
+int csr_min_priv = csr_ops[csrno].min_priv_ver;
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
@@ -2918,6 +2919,10 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+if (env->priv_ver < csr_min_priv) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
return csr_ops[csrno].predicate(env, csrno);
}
--
2.30.2
Re: [PATCH v4 21/47] target/ppc: implement vsrq
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v4: - New in v4. --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 40 + 2 files changed, 31 insertions(+), 10 deletions(-) Reviewed-by: Richard Henderson r~
[PATCH v4 3/6] target/riscv: Introduce privilege version field in the CSR ops.
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
However, it doesn't enforce the privilege version in this commit.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 +
target/riscv/csr.c | 103 ++---
2 files changed, 70 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 60b847141db2..0741f9822cf0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -593,6 +593,8 @@ typedef struct {
riscv_csr_op_fn op;
riscv_csr_read128_fn read128;
riscv_csr_write128_fn write128;
+/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
+uint32_t min_priv_ver;
} riscv_csr_operations;
/* CSR function table constants */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8c63caa39245..25a0df498669 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm},
[CSR_FCSR] = { "fcsr", fs, read_fcsr,write_fcsr },
/* Vector CSRs */
-[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
-[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat },
-[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm },
-[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr },
-[CSR_VL] = { "vl", vs, read_vl},
-[CSR_VTYPE]= { "vtype",vs, read_vtype },
-[CSR_VLENB]= { "vlenb",vs, read_vlenb },
+[CSR_VSTART] = { "vstart", vs,read_vstart, write_vstart,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VXSAT]= { "vxsat",vs,read_vxsat, write_vxsat,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VXRM] = { "vxrm", vs,read_vxrm,write_vxrm,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VCSR] = { "vcsr", vs,read_vcsr,write_vcsr,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VL] = { "vl", vs,read_vl,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VTYPE]= { "vtype",vs,read_vtype,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
+[CSR_VLENB]= { "vlenb",vs,read_vlenb,
+ .min_priv_ver = PRIV_VERSION_1_12_0
},
/* User Timers and Counters */
[CSR_CYCLE]= { "cycle",ctr,read_instret },
[CSR_INSTRET] = { "instret", ctr,read_instret },
@@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
-[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
write_hstatus },
-[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
write_hedeleg },
-[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
rmw_hideleg },
-[CSR_HVIP]= { "hvip",hmode, NULL, NULL, rmw_hvip
},
-[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip
},
-[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie
},
-[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
write_hcounteren },
-[CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
write_hgeie },
-[CSR_HTVAL] = { "htval", hmode, read_htval,
write_htval },
-[CSR_HTINST] = { "htinst", hmode, read_htinst,
write_htinst },
-[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
},
-[CSR_HGATP] = { "hgatp", hmode, read_hgatp,
write_hgatp },
-[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta },
-[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
write_htimedeltah },
-
-[CSR_VSSTATUS]= { "vsstatus",hmode, read_vsstatus,
write_vsstatus},
-[CSR_VSIP]= { "vsip",hmode, NULL,NULL,rmw_vsip
},
-[CSR_VSIE]= { "vsie",hmode, NULL,NULL,rmw_vsie
},
-[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
write_vstvec },
-[CSR_VSSCRATCH] = {
[PATCH v4 1/6] target/riscv: Define simpler privileged spec version numbering
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9d24d678e98a..e5ff4c134c86 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,8 +82,11 @@ enum {
RISCV_FEATURE_AIA
};
-#define PRIV_VERSION_1_10_0 0x00011000
-#define PRIV_VERSION_1_11_0 0x00011100
+/* Privileged specification version */
+enum {
+PRIV_VERSION_1_10_0 = 0,
+PRIV_VERSION_1_11_0,
+};
#define VEXT_VERSION_1_00_0 0x0001
--
2.30.2
[PATCH v4 2/6] target/riscv: Add the privileged spec version 1.12.0
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e5ff4c134c86..60b847141db2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,6 +86,7 @@ enum {
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
+PRIV_VERSION_1_12_0,
};
#define VEXT_VERSION_1_00_0 0x0001
--
2.30.2
[PATCH v4 5/6] target/riscv: Add *envcfg* CSRs support
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h | 39 +++
target/riscv/csr.c | 107
target/riscv/machine.c | 24 +
4 files changed, 175 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0741f9822cf0..e5c8694cf081 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -303,6 +303,11 @@ struct CPURISCVState {
target_ulong spmbase;
target_ulong upmmask;
target_ulong upmbase;
+
+/* CSRs for execution enviornment configuration */
+uint64_t menvcfg;
+target_ulong senvcfg;
+uint64_t henvcfg;
#endif
float_status fp_status;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 89440241632a..58a0a8d69f72 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -202,6 +202,9 @@
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
+/* Supervisor Configuration CSRs */
+#define CSR_SENVCFG 0x10A
+
/* Supervisor Trap Handling */
#define CSR_SSCRATCH0x140
#define CSR_SEPC0x141
@@ -247,6 +250,10 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
+/* Hypervisor Configuration CSRs */
+#define CSR_HENVCFG 0x60A
+#define CSR_HENVCFGH0x61A
+
/* Virtual CSRs */
#define CSR_VSSTATUS0x200
#define CSR_VSIE0x204
@@ -290,6 +297,10 @@
#define CSR_VSIEH 0x214
#define CSR_VSIPH 0x254
+/* Machine Configuration CSRs */
+#define CSR_MENVCFG 0x30A
+#define CSR_MENVCFGH0x31A
+
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH0x757
@@ -654,6 +665,34 @@ typedef enum RISCVException {
#define PM_EXT_CLEAN0x0002ULL
#define PM_EXT_DIRTY0x0003ULL
+/* Execution enviornment configuration bits */
+#define MENVCFG_FIOM BIT(0)
+#define MENVCFG_CBIE (3UL << 4)
+#define MENVCFG_CBCFE BIT(6)
+#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_PBMTE BIT(62)
+#define MENVCFG_STCE BIT(63)
+
+/* For RV32 */
+#define MENVCFGH_PBMTE BIT(30)
+#define MENVCFGH_STCE BIT(31)
+
+#define SENVCFG_FIOM MENVCFG_FIOM
+#define SENVCFG_CBIE MENVCFG_CBIE
+#define SENVCFG_CBCFE MENVCFG_CBCFE
+#define SENVCFG_CBZE MENVCFG_CBZE
+
+#define HENVCFG_FIOM MENVCFG_FIOM
+#define HENVCFG_CBIE MENVCFG_CBIE
+#define HENVCFG_CBCFE MENVCFG_CBCFE
+#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_PBMTE MENVCFG_PBMTE
+#define HENVCFG_STCE MENVCFG_STCE
+
+/* For RV32 */
+#define HENVCFGH_PBMTE MENVCFGH_PBMTE
+#define HENVCFGH_STCE MENVCFGH_STCE
+
/* Offsets for every pair of control bits per each priv level */
#define XS_OFFSET0ULL
#define U_OFFSET 2ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 18fe17b62f51..ff7e36596447 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1366,6 +1366,101 @@ static RISCVException write_mtval(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+/* Execution environment configuration setup */
+static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = env->menvcfg;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
+
+if (riscv_cpu_mxl(env) == MXL_RV64) {
+mask |= MENVCFG_PBMTE | MENVCFG_STCE;
+}
+env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = env->menvcfg >> 32;
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+uint64_t valh = (uint64_t)val << 32;
+
+env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+*val = env->senvcfg;
+return RISCV_EXCP_NONE;
+}
+
+static
[PATCH v4 0/6] Privilege version update
RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1]. The privileged specification version is also upgraded to v1.12. It means certain CSRs introduced in v1.12 should only be accessible only if the priv specification version supported is equal or greater than v1.12. Doing this check in predicate function is not scalable as there will be new CSRs introduced in the future versions of the privileged specification. This series tries to address this problem by adding a field in the csr_ops which can be checked in csrrw function before invoking the predicate function. To keep the code churn to minimum, it is assumed that the minimum version of the privilege version supported for any CSR is v1.10 unless specified explicitly in the csr_ops table. Any new CSRs introduced in v1.12 have been updated accordingly. This will work fine for any ratified extensions. However, it is bit unclear what should be done for the stable draft extensions. My suggestion is not to update the priv field in the CSR ops table until the extension is marked experimental (i.e. not frozen/ratified). Once the extension is ratified and graduated from experimental to available stage, the privileged spec version should be updated in the csr table if required. I am open to other suggestions as well. [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions This series is rebased on top of the AIA v8 to avoid conflicts. Changes from v3->v4: 1. Added reviewed-by tags. 2. Improved the commit text in PATCH 3 & 6. Changes from v2->v3: 1. Only update the bits defined in *envcfg CSR Changes from v1->v2: 1. Unified both [m/h]envcfg & [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in the CSR ops. target/riscv: Add support for mconfigptr target/riscv: Add *envcfg* CSRs support target/riscv: Enable privileged spec version 1.12 target/riscv/cpu.c | 8 +- target/riscv/cpu.h | 15 ++- target/riscv/cpu_bits.h | 40 target/riscv/csr.c | 217 +--- target/riscv/machine.c | 24 + 5 files changed, 264 insertions(+), 40 deletions(-) -- 2.30.2
[PATCH v4 4/6] target/riscv: Add support for mconfigptr
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f96d26399607..89440241632a 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -148,6 +148,7 @@
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+#define CSR_MCONFIGPTR 0xf15
/* Machine Trap Setup */
#define CSR_MSTATUS 0x300
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 25a0df498669..18fe17b62f51 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3021,6 +3021,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIMPID]= { "mimpid",any, read_zero},
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
+[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
+.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Machine Trap Setup */
[CSR_MSTATUS] = { "mstatus",any, read_mstatus,
write_mstatus, NULL,
read_mstatus_i128
},
--
2.30.2
Re: [PATCH v4 19/47] target/ppc: move vs[lr][a][bhwd] to decodetree
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- v4: - New in v4. --- target/ppc/insn32.decode| 17 target/ppc/translate/vmx-impl.c.inc | 41 +++-- target/ppc/translate/vmx-ops.c.inc | 13 + 3 files changed, 45 insertions(+), 26 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 18/47] target/ppc: implement vgnb
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Suggested-by: Richard Henderson Signed-off-by: Matheus Ferst --- v4: - Optimized implementation (rth) --- target/ppc/insn32.decode| 5 ++ target/ppc/translate/vmx-impl.c.inc | 135 2 files changed, 140 insertions(+) Reviewed-by: Richard Henderson r~
[PATCH v1 2/2] riscv: opentitan: Connect opentitan SPI Host
From: Wilfred Mallawa
Conenct spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa
---
hw/riscv/opentitan.c | 42
include/hw/riscv/opentitan.h | 16 --
2 files changed, 52 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index aec7cfa33f..abbe08d4d4 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -1,7 +1,7 @@
/*
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
*
- * Copyright (c) 2020 Western Digital
+ * Copyright (c) 2022 Western Digital
*
* Provides a board compatible with the OpenTitan FPGA platform:
*
@@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH] = { 0x2000, 0x8 },
[IBEX_DEV_UART] = { 0x4000, 0x1000 },
[IBEX_DEV_GPIO] = { 0x4004, 0x1000 },
-[IBEX_DEV_SPI] ={ 0x4005, 0x1000 },
+[IBEX_DEV_SPI_DEVICE] = { 0x4005, 0x1000 },
[IBEX_DEV_I2C] ={ 0x4008, 0x1000 },
[IBEX_DEV_PATTGEN] ={ 0x400e, 0x1000 },
[IBEX_DEV_TIMER] = { 0x4010, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] ={ 0x4011, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x4013, 0x4000 },
[IBEX_DEV_USBDEV] = { 0x4015, 0x1000 },
+[IBEX_DEV_SPI_HOST0] = { 0x4030, 0x1000 },
+[IBEX_DEV_SPI_HOST1] = { 0x4031, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x4040, 0x1000 },
[IBEX_DEV_RSTMGR] = { 0x4041, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x4042, 0x1000 },
@@ -118,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "uart", >uart, TYPE_IBEX_UART);
object_initialize_child(obj, "timer", >timer, TYPE_IBEX_TIMER);
+
+for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
+object_initialize_child(obj, "spi_host[*]", >spi_host[i],
+TYPE_IBEX_SPI_HOST);
+}
}
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
const MemMapEntry *memmap = ibex_memmap;
+DeviceState *dev;
+SysBusDevice *busdev;
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
@@ -207,10 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
IRQ_M_TIMER));
+/* SPI-Hosts */
+for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
+dev = DEVICE(&(s->spi_host[i]));
+if (!sysbus_realize(SYS_BUS_DEVICE(>spi_host[i]), errp)) {
+return;
+}
+busdev = SYS_BUS_DEVICE(dev);
+sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
+
+switch (i) {
+case OPENTITAN_SPI_HOST0:
+sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(>plic),
+IBEX_SPI_HOST0_ERR_IRQ));
+sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(>plic),
+IBEX_SPI_HOST0_SPI_EVENT_IRQ));
+break;
+case OPENTITAN_SPI_HOST1:
+sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(>plic),
+IBEX_SPI_HOST1_ERR_IRQ));
+sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(>plic),
+IBEX_SPI_HOST1_SPI_EVENT_IRQ));
+break;
+}
+}
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
-create_unimplemented_device("riscv.lowrisc.ibex.spi",
-memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
+create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
+memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index eac35ef590..3a3f412ef8 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -1,7 +1,7 @@
/*
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
*
- * Copyright (c) 2020 Western Digital
+ * Copyright (c) 2022 Western Digital
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -23,11 +23,16 @@
#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
+#include "hw/ssi/ibex_spi_host.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
[PATCH v1 1/2] hw/ssi: Add Ibex SPI device model
From: Wilfred Mallawa
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host.c | 629 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events| 7 +
include/hw/ssi/ibex_spi_host.h | 91 +
4 files changed, 728 insertions(+)
create mode 100644 hw/ssi/ibex_spi_host.c
create mode 100644 include/hw/ssi/ibex_spi_host.h
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
new file mode 100644
index 00..7343eb0f61
--- /dev/null
+++ b/hw/ssi/ibex_spi_host.c
@@ -0,0 +1,629 @@
+
+/*
+ * QEMU model of the Ibex SPI Controller
+ * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
+ *
+ * Copyright (C) 2022 Western Digital
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/ssi/ibex_spi_host.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+REG32(INTR_STATE, 0x00)
+FIELD(INTR_STATE, ERROR, 0, 1)
+FIELD(INTR_STATE, SPI_EVENT, 1, 1)
+REG32(INTR_ENABLE, 0x04)
+FIELD(INTR_ENABLE, ERROR, 0, 1)
+FIELD(INTR_ENABLE, SPI_EVENT, 1, 1)
+REG32(INTR_TEST, 0x08)
+FIELD(INTR_TEST, ERROR, 0, 1)
+FIELD(INTR_TEST, SPI_EVENT, 1, 1)
+REG32(ALERT_TEST, 0x0c)
+FIELD(ALERT_TEST, FETAL_TEST, 0, 1)
+REG32(CONTROL, 0x10)
+FIELD(CONTROL, RX_WATERMARK, 0, 8)
+FIELD(CONTROL, TX_WATERMARK, 1, 8)
+FIELD(CONTROL, OUTPUT_EN, 29, 1)
+FIELD(CONTROL, SW_RST, 30, 1)
+FIELD(CONTROL, SPIEN, 31, 1)
+REG32(STATUS, 0x14)
+FIELD(STATUS, TXQD, 0, 8)
+FIELD(STATUS, RXQD, 18, 8)
+FIELD(STATUS, CMDQD, 16, 3)
+FIELD(STATUS, RXWM, 20, 1)
+FIELD(STATUS, BYTEORDER, 22, 1)
+FIELD(STATUS, RXSTALL, 23, 1)
+FIELD(STATUS, RXEMPTY, 24, 1)
+FIELD(STATUS, RXFULL, 25, 1)
+FIELD(STATUS, TXWM, 26, 1)
+FIELD(STATUS, TXSTALL, 27, 1)
+FIELD(STATUS, TXEMPTY, 28, 1)
+FIELD(STATUS, TXFULL, 29, 1)
+FIELD(STATUS, ACTIVE, 30, 1)
+FIELD(STATUS, READY, 31, 1)
+REG32(CONFIGOPTS, 0x18)
+FIELD(CONFIGOPTS, CLKDIV_0, 0, 16)
+FIELD(CONFIGOPTS, CSNIDLE_0, 16, 4)
+FIELD(CONFIGOPTS, CSNTRAIL_0, 20, 4)
+FIELD(CONFIGOPTS, CSNLEAD_0, 24, 4)
+FIELD(CONFIGOPTS, FULLCYC_0, 29, 1)
+FIELD(CONFIGOPTS, CPHA_0, 30, 1)
+FIELD(CONFIGOPTS, CPOL_0, 31, 1)
+REG32(CSID, 0x1c)
+FIELD(CSID, CSID, 0, 32)
+REG32(COMMAND, 0x20)
+FIELD(COMMAND, LEN, 0, 8)
+FIELD(COMMAND, CSAAT, 9, 1)
+FIELD(COMMAND, SPEED, 10, 2)
+FIELD(COMMAND, DIRECTION, 12, 2)
+REG32(ERROR_ENABLE, 0x2c)
+FIELD(ERROR_ENABLE, CMDBUSY, 0, 1)
+FIELD(ERROR_ENABLE, OVERFLOW, 1, 1)
+FIELD(ERROR_ENABLE, UNDERFLOW, 2, 1)
+FIELD(ERROR_ENABLE, CMDINVAL, 3, 1)
+FIELD(ERROR_ENABLE, CSIDINVAL, 4, 1)
+REG32(ERROR_STATUS, 0x30)
+FIELD(ERROR_STATUS, CMDBUSY, 0, 1)
+FIELD(ERROR_STATUS, OVERFLOW, 1, 1)
+FIELD(ERROR_STATUS, UNDERFLOW, 2, 1)
+FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
+FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
+FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
+REG32(EVENT_ENABLE, 0x30)
+FIELD(EVENT_ENABLE, RXFULL, 0, 1)
+FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
+FIELD(EVENT_ENABLE, RXWM, 2, 1)
+FIELD(EVENT_ENABLE, TXWM, 3, 1)
+FIELD(EVENT_ENABLE, READY, 4, 1)
+FIELD(EVENT_ENABLE, IDLE, 5, 1)
+
+/*
+ * Used to track the init status, for replicating hw `feature`
+ * TXDATA ghost write word at init.
+ */
+static bool init_status;
+
+#ifndef IBEX_SPI_HOST_ERR_DEBUG
+#define IBEX_SPI_HOST_ERR_DEBUG 0
+#endif
+
+static inline uint8_t div4_round_up(uint8_t dividend)
+{
+return (dividend + 3) / 4;
+}
+
+static void
Re: [PATCH v2 1/2] block/curl.c: Set error message string if curl_init_state() fails
On 22/2/22 16:23, Peter Maydell wrote: In curl_open(), the 'out' label assumes that the state->errmsg string has been set (either by curl_easy_perform() or by manually copying a string into it); however if curl_init_state() fails we will jump to that label without setting the string. Add the missing error string setup. (We can't be specific about the cause of failure: the documentation of curl_easy_init() just says "If this function returns NULL, something went wrong".) Signed-off-by: Peter Maydell --- block/curl.c | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 7/8] Drop qemu_foo() socket API wrapper
On 22/2/22 20:40, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The socket API wrappers were initially introduced in commit
00aa0040 ("Wrap recv to avoid warnings"), but made redundatant with
commit a2d96af4 ("osdep: add wrappers for socket functions") which fixes
the win32 declarations and thus removed the earlier warnings.
Signed-off-by: Marc-André Lureau
---
include/qemu-common.h| 19 ---
crypto/cipher-afalg.c| 4 ++--
crypto/hash-afalg.c | 4 ++--
gdbstub.c| 2 +-
io/channel-socket.c | 6 +++---
net/socket.c | 24
tests/qtest/e1000e-test.c| 4 ++--
tests/qtest/libqtest.c | 4 ++--
tests/qtest/npcm7xx_emc-test.c | 4 ++--
tests/qtest/test-filter-mirror.c | 4 ++--
tests/qtest/test-filter-redirector.c | 8
tests/qtest/virtio-net-test.c| 10 +-
tests/unit/socket-helpers.c | 2 +-
util/osdep.c | 4 ++--
util/qemu-sockets.c | 10 +-
15 files changed, 45 insertions(+), 64 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v7 2/2] drivers/virt: vmgenid: add vm generation id driver
Hi Adrian,
This thread seems to be long dead, but I couldn't figure out what
happened to the ideas in it. I'm specifically interested in this part:
On Wed, Feb 24, 2021 at 9:48 AM Adrian Catangiu wrote:
> +static void vmgenid_acpi_notify(struct acpi_device *device, u32 event)
> +{
> + uuid_t old_uuid;
> +
> + if (!device || acpi_driver_data(device) != _data) {
> + pr_err("VMGENID notify with unexpected driver private
> data\n");
> + return;
> + }
> +
> + /* update VM Generation UUID */
> + old_uuid = vmgenid_data.uuid;
> + memcpy_fromio(_data.uuid, vmgenid_data.uuid_iomap,
> sizeof(uuid_t));
> +
> + if (memcmp(_uuid, _data.uuid, sizeof(uuid_t))) {
> + /* HW uuid updated */
> + sysgenid_bump_generation();
> + add_device_randomness(_data.uuid, sizeof(uuid_t));
> + }
> +}
As Jann mentioned in an earlier email, we probably want this to
immediately reseed the crng, not just dump it into
add_device_randomness alone. But either way, the general idea seems
interesting to me. As far as I can tell, QEMU still supports this. Was
it not deemed to be sufficiently interesting?
Thanks,
Jason
Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops.
On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis wrote:
>
> On Sun, Feb 6, 2022 at 7:19 PM Atish Patra wrote:
> >
> > To allow/disallow the CSR access based on the privilege spec, a new field
> > in the csr_ops is introduced. It also adds the privileged specification
> > version (v1.12) for the CSRs introduced in the v1.12. This includes the
> > new ratified extensions such as Vector, Hypervisor and secconfig CSR.
> >
> > Signed-off-by: Atish Patra
>
> It might be worth mentioning that there is no enforcement in this commit
>
Sure. I will update the commit text and send a v4.
> Reviewed-by: Alistair Francis
>
> Alistair
>
> > ---
> > target/riscv/cpu.h | 2 +
> > target/riscv/csr.c | 103 ++---
> > 2 files changed, 70 insertions(+), 35 deletions(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 60b847141db2..0741f9822cf0 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -593,6 +593,8 @@ typedef struct {
> > riscv_csr_op_fn op;
> > riscv_csr_read128_fn read128;
> > riscv_csr_write128_fn write128;
> > +/* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)
> > */
> > +uint32_t min_priv_ver;
> > } riscv_csr_operations;
> >
> > /* CSR function table constants */
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 8c63caa39245..25a0df498669 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_FRM] = { "frm", fs, read_frm, write_frm},
> > [CSR_FCSR] = { "fcsr", fs, read_fcsr,write_fcsr },
> > /* Vector CSRs */
> > -[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
> > -[CSR_VXSAT]= { "vxsat",vs, read_vxsat, write_vxsat },
> > -[CSR_VXRM] = { "vxrm", vs, read_vxrm,write_vxrm },
> > -[CSR_VCSR] = { "vcsr", vs, read_vcsr,write_vcsr },
> > -[CSR_VL] = { "vl", vs, read_vl},
> > -[CSR_VTYPE]= { "vtype",vs, read_vtype },
> > -[CSR_VLENB]= { "vlenb",vs, read_vlenb },
> > +[CSR_VSTART] = { "vstart", vs,read_vstart, write_vstart,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VXSAT]= { "vxsat",vs,read_vxsat, write_vxsat,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VXRM] = { "vxrm", vs,read_vxrm,write_vxrm,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VCSR] = { "vcsr", vs,read_vcsr,write_vcsr,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VL] = { "vl", vs,read_vl,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VTYPE]= { "vtype",vs,read_vtype,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +[CSR_VLENB]= { "vlenb",vs,read_vlenb,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > /* User Timers and Counters */
> > [CSR_CYCLE]= { "cycle",ctr,read_instret },
> > [CSR_INSTRET] = { "instret", ctr,read_instret },
> > @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> > [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> >
> > -[CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
> > write_hstatus },
> > -[CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
> > write_hedeleg },
> > -[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
> > rmw_hideleg },
> > -[CSR_HVIP]= { "hvip",hmode, NULL, NULL,
> > rmw_hvip },
> > -[CSR_HIP] = { "hip", hmode, NULL, NULL,
> > rmw_hip },
> > -[CSR_HIE] = { "hie", hmode, NULL, NULL,
> > rmw_hie },
> > -[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> > write_hcounteren },
> > -[CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> > write_hgeie },
> > -[CSR_HTVAL] = { "htval", hmode, read_htval,
> > write_htval },
> > -[CSR_HTINST] = { "htinst", hmode, read_htinst,
> > write_htinst },
> > -[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
> >},
> > -[CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> > write_hgatp },
> > -
Re: [PULL 00/25] qtest patches and misc header clean-ups
On Mon, 21 Feb 2022 at 12:00, Thomas Huth wrote: > > Hi! > > The following changes since commit e670f6d825d4dee248b311197fd4048469d6772b: > > Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into > staging (2022-02-20 15:05:41 +) > > are available in the Git repository at: > > https://gitlab.com/thuth/qemu.git tags/pull-request-2022-02-21 > > for you to fetch changes up to 975592f5523fdf8708e4b53da937cf4805b1b79a: > > hw/tricore: Remove unused and incorrect header (2022-02-21 10:36:50 +0100) > > > * Improve virtio-net failover test > * Some small fixes for the qtests > * Misc header cleanups by Philippe Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0 for any user-visible changes. -- PMM
Re: [PATCH v2 20/22] hw/tpm/tpm_tis_isa: Disuse isa_init_irq()
On 2/22/22 14:34, Bernhard Beschow wrote: isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow Reviewed-by: Stefan Berger --- hw/tpm/tpm_tis_isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 10d8a14f19..3477afd735 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -127,7 +127,7 @@ static void tpm_tis_isa_realizefn(DeviceState *dev, Error **errp) return; } -isa_init_irq(ISA_DEVICE(dev), >irq, s->irq_num); +s->irq = isa_get_irq(ISA_DEVICE(dev), s->irq_num); memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), TPM_TIS_ADDR_BASE, >mmio);
[PATCH 7/8] Drop qemu_foo() socket API wrapper
From: Marc-André Lureau
The socket API wrappers were initially introduced in commit
00aa0040 ("Wrap recv to avoid warnings"), but made redundatant with
commit a2d96af4 ("osdep: add wrappers for socket functions") which fixes
the win32 declarations and thus removed the earlier warnings.
Signed-off-by: Marc-André Lureau
---
include/qemu-common.h| 19 ---
crypto/cipher-afalg.c| 4 ++--
crypto/hash-afalg.c | 4 ++--
gdbstub.c| 2 +-
io/channel-socket.c | 6 +++---
net/socket.c | 24
tests/qtest/e1000e-test.c| 4 ++--
tests/qtest/libqtest.c | 4 ++--
tests/qtest/npcm7xx_emc-test.c | 4 ++--
tests/qtest/test-filter-mirror.c | 4 ++--
tests/qtest/test-filter-redirector.c | 8
tests/qtest/virtio-net-test.c| 10 +-
tests/unit/socket-helpers.c | 2 +-
util/osdep.c | 4 ++--
util/qemu-sockets.c | 10 +-
15 files changed, 45 insertions(+), 64 deletions(-)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 0248a324cdcd..6969f957b7c3 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -35,25 +35,6 @@ ssize_t qemu_write_full(int fd, const void *buf, size_t
count)
int qemu_pipe(int pipefd[2]);
#endif
-#ifdef _WIN32
-/* MinGW needs type casts for the 'buf' and 'optval' arguments. */
-#define qemu_getsockopt(sockfd, level, optname, optval, optlen) \
-getsockopt(sockfd, level, optname, (void *)optval, optlen)
-#define qemu_setsockopt(sockfd, level, optname, optval, optlen) \
-setsockopt(sockfd, level, optname, (const void *)optval, optlen)
-#define qemu_recv(sockfd, buf, len, flags) recv(sockfd, (void *)buf, len,
flags)
-#define qemu_sendto(sockfd, buf, len, flags, destaddr, addrlen) \
-sendto(sockfd, (const void *)buf, len, flags, destaddr, addrlen)
-#else
-#define qemu_getsockopt(sockfd, level, optname, optval, optlen) \
-getsockopt(sockfd, level, optname, optval, optlen)
-#define qemu_setsockopt(sockfd, level, optname, optval, optlen) \
-setsockopt(sockfd, level, optname, optval, optlen)
-#define qemu_recv(sockfd, buf, len, flags) recv(sockfd, buf, len, flags)
-#define qemu_sendto(sockfd, buf, len, flags, destaddr, addrlen) \
-sendto(sockfd, buf, len, flags, destaddr, addrlen)
-#endif
-
void cpu_exec_init_all(void);
void cpu_exec_step_atomic(CPUState *cpu);
diff --git a/crypto/cipher-afalg.c b/crypto/cipher-afalg.c
index 052355a8a921..c55cd28bf01c 100644
--- a/crypto/cipher-afalg.c
+++ b/crypto/cipher-afalg.c
@@ -84,8 +84,8 @@ qcrypto_afalg_cipher_ctx_new(QCryptoCipherAlgorithm alg,
g_free(name);
/* setkey */
-if (qemu_setsockopt(afalg->tfmfd, SOL_ALG, ALG_SET_KEY, key,
-nkey) != 0) {
+if (setsockopt(afalg->tfmfd, SOL_ALG, ALG_SET_KEY, key,
+ nkey) != 0) {
error_setg_errno(errp, errno, "Set key failed");
qcrypto_afalg_comm_free(afalg);
return NULL;
diff --git a/crypto/hash-afalg.c b/crypto/hash-afalg.c
index cf34c694af6f..4ac18c7c1db7 100644
--- a/crypto/hash-afalg.c
+++ b/crypto/hash-afalg.c
@@ -88,8 +88,8 @@ qcrypto_afalg_hash_hmac_ctx_new(QCryptoHashAlgorithm alg,
/* HMAC needs setkey */
if (is_hmac) {
-if (qemu_setsockopt(afalg->tfmfd, SOL_ALG, ALG_SET_KEY,
-key, nkey) != 0) {
+if (setsockopt(afalg->tfmfd, SOL_ALG, ALG_SET_KEY,
+ key, nkey) != 0) {
error_setg_errno(errp, errno, "Set hmac key failed");
qcrypto_afalg_comm_free(afalg);
return NULL;
diff --git a/gdbstub.c b/gdbstub.c
index 3c14c6a03831..c8375e3c3ffe 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -426,7 +426,7 @@ static int get_char(void)
int ret;
for(;;) {
-ret = qemu_recv(gdbserver_state.fd, , 1, 0);
+ret = recv(gdbserver_state.fd, , 1, 0);
if (ret < 0) {
if (errno == ECONNRESET)
gdbserver_state.fd = -1;
diff --git a/io/channel-socket.c b/io/channel-socket.c
index 459922c87480..7a8d9f69c92d 100644
--- a/io/channel-socket.c
+++ b/io/channel-socket.c
@@ -681,9 +681,9 @@ qio_channel_socket_set_delay(QIOChannel *ioc,
QIOChannelSocket *sioc = QIO_CHANNEL_SOCKET(ioc);
int v = enabled ? 0 : 1;
-qemu_setsockopt(sioc->fd,
-IPPROTO_TCP, TCP_NODELAY,
-, sizeof(v));
+setsockopt(sioc->fd,
+ IPPROTO_TCP, TCP_NODELAY,
+ , sizeof(v));
}
diff --git a/net/socket.c b/net/socket.c
index 15b410e8d825..c4b80e9228d7 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -120,9 +120,9 @@ static ssize_t net_socket_receive_dgram(NetClientState *nc,
const uint8_t *buf,
do {
if (s->dgram_dst.sin_family != AF_UNIX) {
-ret = qemu_sendto(s->fd, buf, size, 0,
[PATCH 3/8] qga/vss: update informative message about MinGW
From: Marc-André Lureau
The headers are now all available in MinGW master branch.
(commit 13390dbbf885f and earlier) aiming for 10.0.
Signed-off-by: Marc-André Lureau
---
qga/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qga/meson.build b/qga/meson.build
index 54f2da5b0763..62472747f1bb 100644
--- a/qga/meson.build
+++ b/qga/meson.build
@@ -15,7 +15,7 @@ have_qga_vss = get_option('qga_vss') \
If your Visual Studio installation doesn't have the VSS headers,
Please download and install Microsoft VSS SDK:
http://www.microsoft.com/en-us/download/details.aspx?id=23490
-On POSIX-systems, MinGW doesn't yet provide working headers.
+On POSIX-systems, MinGW should provide headers in >=10.0 releases.
you can extract the SDK headers by:
$ scripts/extract-vsssdk-headers setup.exe
The headers are extracted in the directory 'inc/win2003'.
--
2.35.1.273.ge6ebfd0e8cbb
[PATCH 1/8] meson: fix generic location of vss headers
From: Marc-André Lureau
This is a left-over, despite requesting the change before the merge.
Fixes: commit 8821a389 ("configure, meson: replace VSS SDK checks and options
with --enable-vss-sdk")
Signed-off-by: Marc-André Lureau
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 8df40bfac4d7..b871098dbba0 100644
--- a/meson.build
+++ b/meson.build
@@ -1936,7 +1936,7 @@ have_vss = false
if targetos == 'windows' and link_language == 'cpp'
have_vss = cxx.compiles('''
#define __MIDL_user_allocate_free_DEFINED__
-#include
+#include
int main(void) { return VSS_CTX_BACKUP; }''')
endif
--
2.35.1.273.ge6ebfd0e8cbb
[PATCH 5/8] meson: use chardev_ss dependencies
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 40abe86767e8..b1d2fcecbdcf 100644
--- a/meson.build
+++ b/meson.build
@@ -3000,7 +3000,7 @@ libqmp = static_library('qmp', qmp_ss.sources() + genh,
qmp = declare_dependency(link_whole: [libqmp])
libchardev = static_library('chardev', chardev_ss.sources() + genh,
-dependencies: [gnutls],
+dependencies: chardev_ss.dependencies(),
build_by_default: false)
chardev = declare_dependency(link_whole: libchardev)
--
2.35.1.273.ge6ebfd0e8cbb
[PATCH 2/8] qga/vss-win32: check old VSS SDK headers
From: Marc-André Lureau
The VssCoordinator & VssAdmin interfaces have been moved to vsadmin.h in
the Windows SDK.
Signed-off-by: Marc-André Lureau
---
meson.build| 3 +++
qga/vss-win32/vss-common.h | 3 ++-
qga/vss-win32/install.cpp | 4
qga/vss-win32/provider.cpp | 4
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index b871098dbba0..101a3f2d31ee 100644
--- a/meson.build
+++ b/meson.build
@@ -1933,12 +1933,15 @@ config_host_data.set('CONFIG_AF_VSOCK',
cc.compiles(gnu_source_prefix + '''
}'''))
have_vss = false
+have_vss_sdk = false # old xp/2003 SDK
if targetos == 'windows' and link_language == 'cpp'
have_vss = cxx.compiles('''
#define __MIDL_user_allocate_free_DEFINED__
#include
int main(void) { return VSS_CTX_BACKUP; }''')
+ have_vss_sdk = cxx.has_header('vscoordint.h')
endif
+config_host_data.set('HAVE_VSS_SDK', have_vss_sdk)
have_ntddscsi = false
if targetos == 'windows'
diff --git a/qga/vss-win32/vss-common.h b/qga/vss-win32/vss-common.h
index 54f8de8c8851..0e67e7822ce6 100644
--- a/qga/vss-win32/vss-common.h
+++ b/qga/vss-win32/vss-common.h
@@ -64,12 +64,13 @@ const CLSID CLSID_QGAVSSProvider = { 0x6e6a3492, 0x8d4d,
0x440c,
const TCHAR g_szClsid[] = TEXT("{6E6A3492-8D4D-440C-9619-5E5D0CC31CA8}");
const TCHAR g_szProgid[] = TEXT("QGAVSSProvider");
+#ifdef HAVE_VSS_SDK
/* Enums undefined in VSS SDK 7.2 but defined in newer Windows SDK */
enum __VSS_VOLUME_SNAPSHOT_ATTRIBUTES {
VSS_VOLSNAP_ATTR_NO_AUTORECOVERY = 0x0002,
VSS_VOLSNAP_ATTR_TXF_RECOVERY = 0x0200
};
-
+#endif
/* COM pointer utility; call ->Release() when it goes out of scope */
template
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index efc5bb9909c0..8076efe3cbb5 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -13,7 +13,11 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#ifdef HAVE_VSS_SDK
#include
+#else
+#include
+#endif
#include "install.h"
#include
#include
diff --git a/qga/vss-win32/provider.cpp b/qga/vss-win32/provider.cpp
index fd187fb66f67..1b885e24ee17 100644
--- a/qga/vss-win32/provider.cpp
+++ b/qga/vss-win32/provider.cpp
@@ -12,7 +12,11 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#ifdef HAVE_VSS_SDK
#include
+#else
+#include
+#endif
#include
#define VSS_TIMEOUT_MSEC (60*1000)
--
2.35.1.273.ge6ebfd0e8cbb
[PATCH v2 22/22] isa: Remove unused isa_init_irq()
isa_init_irq() had become a trivial one-line wrapper for isa_get_irq().
The previous commits resolved all usages in favor of isa_get_irq().
isa_init_irq() can therefore be removed.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 5 -
include/hw/isa/isa.h | 1 -
2 files changed, 6 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 1e8c102177..0ad1c5fd65 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -85,11 +85,6 @@ qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
return isabus->irqs[isairq];
}
-void isa_init_irq(ISADevice *dev, qemu_irq *p, unsigned isairq)
-{
-*p = isa_get_irq(dev, isairq);
-}
-
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
{
qemu_irq irq = isa_get_irq(isadev, isairq);
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index d80cab5b79..034d706ba1 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -90,7 +90,6 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion
*address_space,
MemoryRegion *address_space_io, Error **errp);
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs);
qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq);
-void isa_init_irq(ISADevice *dev, qemu_irq *p, unsigned isairq);
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq);
void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16);
IsaDma *isa_get_dma(ISABus *bus, int nchan);
--
2.35.1
[PATCH 0/8] Misc build fixes and cleanups
From: Marc-André Lureau Hi, A small collection of patches gleaned while working on different things. Marc-André Lureau (8): meson: fix generic location of vss headers qga/vss-win32: check old VSS SDK headers qga/vss: update informative message about MinGW meson: drop the .fa library suffix meson: use chardev_ss dependencies char: move qemu_openpty_raw from util/ to char/ Drop qemu_foo() socket API wrapper Replace GCC_FMT_ATTR with G_GNUC_PRINTF docs/devel/build-system.rst | 5 - meson.build | 25 ++--- audio/audio.h | 4 +- block/qcow2.h | 2 +- bsd-user/qemu.h | 2 +- hw/display/qxl.h| 2 +- hw/net/rocker/rocker.h | 2 +- hw/xen/xen_pt.h | 2 +- include/chardev/char-fe.h | 2 +- include/disas/dis-asm.h | 2 +- include/hw/acpi/aml-build.h | 12 +- include/hw/core/cpu.h | 2 +- include/hw/hw.h | 2 +- include/hw/virtio/virtio.h | 2 +- include/hw/xen/xen-bus-helper.h | 4 +- include/hw/xen/xen-bus.h| 4 +- include/hw/xen/xen_common.h | 2 +- include/hw/xen/xen_pvdev.h | 2 +- include/monitor/monitor.h | 4 +- include/qapi/error.h| 20 ++-- include/qapi/qmp/qjson.h| 8 +- include/qemu-common.h | 21 include/qemu/buffer.h | 2 +- include/qemu/compiler.h | 11 +- include/qemu/error-report.h | 24 ++-- include/qemu/log-for-trace.h| 2 +- include/qemu/log.h | 2 +- include/qemu/qemu-print.h | 8 +- include/qemu/readline.h | 2 +- qga/guest-agent-core.h | 2 +- qga/vss-win32/requester.h | 2 +- qga/vss-win32/vss-common.h | 3 +- scripts/cocci-macro-file.h | 2 +- tests/qtest/libqos/libqtest.h | 42 +++ tests/qtest/libqtest-single.h | 2 +- tests/qtest/migration-helpers.h | 6 +- audio/alsaaudio.c | 4 +- audio/coreaudio.c | 4 +- audio/dsoundaudio.c | 4 +- audio/ossaudio.c| 4 +- audio/paaudio.c | 2 +- audio/sdlaudio.c| 2 +- block/blkverify.c | 2 +- block/ssh.c | 4 +- chardev/char-pty.c | 104 ++ crypto/cipher-afalg.c | 4 +- crypto/hash-afalg.c | 4 +- fsdev/9p-marshal.c | 2 +- fsdev/virtfs-proxy-helper.c | 2 +- gdbstub.c | 2 +- hw/9pfs/9p.c| 2 +- hw/acpi/aml-build.c | 4 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- hw/net/rtl8139.c| 2 +- hw/virtio/virtio.c | 2 +- io/channel-socket.c | 6 +- io/channel-websock.c| 2 +- monitor/hmp.c | 4 +- nbd/server.c| 10 +- net/socket.c| 24 ++-- qemu-img.c | 4 +- qemu-io.c | 2 +- qobject/json-parser.c | 2 +- softmmu/qtest.c | 4 +- tests/qtest/e1000e-test.c | 4 +- tests/qtest/libqtest.c | 6 +- tests/qtest/npcm7xx_emc-test.c | 4 +- tests/qtest/test-filter-mirror.c| 4 +- tests/qtest/test-filter-redirector.c| 8 +- tests/qtest/virtio-net-test.c | 10 +- tests/unit/socket-helpers.c | 2 +- tests/unit/test-qobject-input-visitor.c | 4 +- util/osdep.c| 4 +- util/qemu-openpty.c | 139 util/qemu-sockets.c | 10 +- chardev/meson.build | 4 +- qga/meson.build | 2 +- qga/vss-win32/install.cpp | 4 + qga/vss-win32/provider.cpp | 4 + scripts/checkpatch.pl | 2 +- tests/qtest/libqos/meson.build | 1 - util/meson.build| 1 - 83 files changed, 300 insertions(+), 370 deletions(-) delete mode 100644 util/qemu-openpty.c -- 2.35.1.273.ge6ebfd0e8cbb
[PATCH v2 16/22] hw/ipmi/isa_ipmi_kcs: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/ipmi/isa_ipmi_kcs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ipmi/isa_ipmi_kcs.c b/hw/ipmi/isa_ipmi_kcs.c
index 3b23ad08b3..afabb95ebe 100644
--- a/hw/ipmi/isa_ipmi_kcs.c
+++ b/hw/ipmi/isa_ipmi_kcs.c
@@ -91,7 +91,7 @@ static void ipmi_isa_realize(DeviceState *dev, Error **errp)
}
if (iik->isairq > 0) {
-isa_init_irq(isadev, >irq, iik->isairq);
+iik->irq = isa_get_irq(isadev, iik->isairq);
iik->kcs.use_irq = 1;
iik->kcs.raise_irq = isa_ipmi_kcs_raise_irq;
iik->kcs.lower_irq = isa_ipmi_kcs_lower_irq;
--
2.35.1
[PATCH v2 13/22] hw/ide/isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/ide/isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ide/isa.c b/hw/ide/isa.c index 24bbde24c2..8bedbd13f1 100644 --- a/hw/ide/isa.c +++ b/hw/ide/isa.c @@ -75,7 +75,7 @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp) ide_bus_init(>bus, sizeof(s->bus), dev, 0, 2); ide_init_ioport(>bus, isadev, s->iobase, s->iobase2); -isa_init_irq(isadev, >irq, s->isairq); +s->irq = isa_get_irq(isadev, s->isairq); ide_init2(>bus, s->irq); vmstate_register(VMSTATE_IF(dev), 0, _ide_isa, s); ide_register_restart_cb(>bus); -- 2.35.1
[PATCH 8/8] Replace GCC_FMT_ATTR with G_GNUC_PRINTF
From: Marc-André Lureau
One less qemu-specific macro. It also helps to make some headers/units
only depend on glib, and thus moved in standalone projects eventually.
Signed-off-by: Marc-André Lureau
---
audio/audio.h | 4 +--
block/qcow2.h | 2 +-
bsd-user/qemu.h | 2 +-
hw/display/qxl.h| 2 +-
hw/net/rocker/rocker.h | 2 +-
hw/xen/xen_pt.h | 2 +-
include/chardev/char-fe.h | 2 +-
include/disas/dis-asm.h | 2 +-
include/hw/acpi/aml-build.h | 12 +++
include/hw/core/cpu.h | 2 +-
include/hw/hw.h | 2 +-
include/hw/virtio/virtio.h | 2 +-
include/hw/xen/xen-bus-helper.h | 4 +--
include/hw/xen/xen-bus.h| 4 +--
include/hw/xen/xen_common.h | 2 +-
include/hw/xen/xen_pvdev.h | 2 +-
include/monitor/monitor.h | 4 +--
include/qapi/error.h| 20 ++--
include/qapi/qmp/qjson.h| 8 ++---
include/qemu/buffer.h | 2 +-
include/qemu/compiler.h | 11 ++-
include/qemu/error-report.h | 24 +++---
include/qemu/log-for-trace.h| 2 +-
include/qemu/log.h | 2 +-
include/qemu/qemu-print.h | 8 ++---
include/qemu/readline.h | 2 +-
qga/guest-agent-core.h | 2 +-
qga/vss-win32/requester.h | 2 +-
scripts/cocci-macro-file.h | 2 +-
tests/qtest/libqos/libqtest.h | 42 -
tests/qtest/libqtest-single.h | 2 +-
tests/qtest/migration-helpers.h | 6 ++--
audio/alsaaudio.c | 4 +--
audio/coreaudio.c | 4 +--
audio/dsoundaudio.c | 4 +--
audio/ossaudio.c| 4 +--
audio/paaudio.c | 2 +-
audio/sdlaudio.c| 2 +-
block/blkverify.c | 2 +-
block/ssh.c | 4 +--
fsdev/9p-marshal.c | 2 +-
fsdev/virtfs-proxy-helper.c | 2 +-
hw/9pfs/9p.c| 2 +-
hw/acpi/aml-build.c | 4 +--
hw/mips/fuloong2e.c | 2 +-
hw/mips/malta.c | 2 +-
hw/net/rtl8139.c| 2 +-
hw/virtio/virtio.c | 2 +-
io/channel-websock.c| 2 +-
monitor/hmp.c | 4 +--
nbd/server.c| 10 +++---
qemu-img.c | 4 +--
qemu-io.c | 2 +-
qobject/json-parser.c | 2 +-
softmmu/qtest.c | 4 +--
tests/qtest/libqtest.c | 2 +-
tests/unit/test-qobject-input-visitor.c | 4 +--
scripts/checkpatch.pl | 2 +-
58 files changed, 130 insertions(+), 137 deletions(-)
diff --git a/audio/audio.h b/audio/audio.h
index c8bde536b5cd..cbb10f4816e5 100644
--- a/audio/audio.h
+++ b/audio/audio.h
@@ -91,8 +91,8 @@ typedef struct QEMUAudioTimeStamp {
uint64_t old_ts;
} QEMUAudioTimeStamp;
-void AUD_vlog (const char *cap, const char *fmt, va_list ap) GCC_FMT_ATTR(2,
0);
-void AUD_log (const char *cap, const char *fmt, ...) GCC_FMT_ATTR(2, 3);
+void AUD_vlog (const char *cap, const char *fmt, va_list ap) G_GNUC_PRINTF(2,
0);
+void AUD_log (const char *cap, const char *fmt, ...) G_GNUC_PRINTF(2, 3);
void AUD_register_card (const char *name, QEMUSoundCard *card);
void AUD_remove_card (QEMUSoundCard *card);
diff --git a/block/qcow2.h b/block/qcow2.h
index fd48a89d452c..ba436a8d0d68 100644
--- a/block/qcow2.h
+++ b/block/qcow2.h
@@ -838,7 +838,7 @@ int qcow2_update_header(BlockDriverState *bs);
void qcow2_signal_corruption(BlockDriverState *bs, bool fatal, int64_t offset,
int64_t size, const char *message_format, ...)
- GCC_FMT_ATTR(5, 6);
+ G_GNUC_PRINTF(5, 6);
int qcow2_validate_table(BlockDriverState *bs, uint64_t offset,
uint64_t entries, size_t entry_len,
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 02921ac8b3b7..9c8237dbbce2 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -181,7 +181,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_long
arg1,
abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6);
-void gemu_log(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
+void gemu_log(const char *fmt, ...) G_GNUC_PRINTF(1, 2);
extern __thread CPUState *thread_cpu;
void
[PATCH v2 20/22] hw/tpm/tpm_tis_isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/tpm/tpm_tis_isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 10d8a14f19..3477afd735 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -127,7 +127,7 @@ static void tpm_tis_isa_realizefn(DeviceState *dev, Error **errp) return; } -isa_init_irq(ISA_DEVICE(dev), >irq, s->irq_num); +s->irq = isa_get_irq(ISA_DEVICE(dev), s->irq_num); memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), TPM_TIS_ADDR_BASE, >mmio); -- 2.35.1
[PATCH v2 18/22] hw/net/ne2000-isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/net/ne2000-isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/ne2000-isa.c b/hw/net/ne2000-isa.c index dd6f6e34d3..6ced6775ff 100644 --- a/hw/net/ne2000-isa.c +++ b/hw/net/ne2000-isa.c @@ -68,7 +68,7 @@ static void isa_ne2000_realizefn(DeviceState *dev, Error **errp) ne2000_setup_io(s, DEVICE(isadev), 0x20); isa_register_ioport(isadev, >io, isa->iobase); -isa_init_irq(isadev, >irq, isa->isairq); +s->irq = isa_get_irq(isadev, isa->isairq); qemu_macaddr_default_if_unset(>c.macaddr); ne2000_reset(s); -- 2.35.1
[PATCH v2 17/22] hw/isa/piix4: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index cb291d121c..0fd6756dcf 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -197,7 +197,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
return;
}
-isa_init_irq(ISA_DEVICE(>rtc), >rtc.irq, s->rtc.isairq);
+s->rtc.irq = isa_get_irq(ISA_DEVICE(>rtc), s->rtc.isairq);
piix4_dev = dev;
}
--
2.35.1
[PATCH 6/8] char: move qemu_openpty_raw from util/ to char/
From: Marc-André Lureau
It is only needed by char-pty.
Signed-off-by: Marc-André Lureau
---
include/qemu-common.h | 2 -
chardev/char-pty.c| 104 +++
util/qemu-openpty.c | 139 --
chardev/meson.build | 4 +-
util/meson.build | 1 -
5 files changed, 106 insertions(+), 144 deletions(-)
delete mode 100644 util/qemu-openpty.c
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 68b2e3bc1091..0248a324cdcd 100644
--- a/include/qemu-common.h
+++ b/include/qemu-common.h
@@ -33,8 +33,6 @@ ssize_t qemu_write_full(int fd, const void *buf, size_t count)
#ifndef _WIN32
int qemu_pipe(int pipefd[2]);
-/* like openpty() but also makes it raw; return master fd */
-int qemu_openpty_raw(int *aslave, char *pty_name);
#endif
#ifdef _WIN32
diff --git a/chardev/char-pty.c b/chardev/char-pty.c
index a2d1e7c985bc..f28779bcc9d2 100644
--- a/chardev/char-pty.c
+++ b/chardev/char-pty.c
@@ -197,6 +197,110 @@ static void char_pty_finalize(Object *obj)
qemu_chr_be_event(chr, CHR_EVENT_CLOSED);
}
+#if defined HAVE_PTY_H
+# include
+#elif defined CONFIG_BSD
+# include
+# if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) ||
defined(__DragonFly__)
+# include
+# else
+# include
+# endif
+#elif defined CONFIG_SOLARIS
+# include
+# include
+#else
+# include
+#endif
+
+#ifdef __sun__
+
+#if !defined(HAVE_OPENPTY)
+/* Once illumos has openpty(), this is going to be removed. */
+static int openpty(int *amaster, int *aslave, char *name,
+ struct termios *termp, struct winsize *winp)
+{
+const char *slave;
+int mfd = -1, sfd = -1;
+
+*amaster = *aslave = -1;
+
+mfd = open("/dev/ptmx", O_RDWR | O_NOCTTY);
+if (mfd < 0)
+goto err;
+
+if (grantpt(mfd) == -1 || unlockpt(mfd) == -1)
+goto err;
+
+if ((slave = ptsname(mfd)) == NULL)
+goto err;
+
+if ((sfd = open(slave, O_RDONLY | O_NOCTTY)) == -1)
+goto err;
+
+if (ioctl(sfd, I_PUSH, "ptem") == -1 ||
+(termp != NULL && tcgetattr(sfd, termp) < 0))
+goto err;
+
+*amaster = mfd;
+*aslave = sfd;
+
+if (winp)
+ioctl(sfd, TIOCSWINSZ, winp);
+
+return 0;
+
+err:
+if (sfd != -1)
+close(sfd);
+close(mfd);
+return -1;
+}
+#endif
+
+static void cfmakeraw (struct termios *termios_p)
+{
+termios_p->c_iflag &=
+~(IGNBRK|BRKINT|PARMRK|ISTRIP|INLCR|IGNCR|ICRNL|IXON);
+termios_p->c_oflag &= ~OPOST;
+termios_p->c_lflag &= ~(ECHO|ECHONL|ICANON|ISIG|IEXTEN);
+termios_p->c_cflag &= ~(CSIZE|PARENB);
+termios_p->c_cflag |= CS8;
+
+termios_p->c_cc[VMIN] = 0;
+termios_p->c_cc[VTIME] = 0;
+}
+#endif
+
+/* like openpty() but also makes it raw; return master fd */
+static int qemu_openpty_raw(int *aslave, char *pty_name)
+{
+int amaster;
+struct termios tty;
+#if defined(__OpenBSD__) || defined(__DragonFly__)
+char pty_buf[PATH_MAX];
+#define q_ptsname(x) pty_buf
+#else
+char *pty_buf = NULL;
+#define q_ptsname(x) ptsname(x)
+#endif
+
+if (openpty(, aslave, pty_buf, NULL, NULL) < 0) {
+return -1;
+}
+
+/* Set raw attributes on the pty. */
+tcgetattr(*aslave, );
+cfmakeraw();
+tcsetattr(*aslave, TCSAFLUSH, );
+
+if (pty_name) {
+strcpy(pty_name, q_ptsname(amaster));
+}
+
+return amaster;
+}
+
static void char_pty_open(Chardev *chr,
ChardevBackend *backend,
bool *be_opened,
diff --git a/util/qemu-openpty.c b/util/qemu-openpty.c
deleted file mode 100644
index 427f43a76973..
--- a/util/qemu-openpty.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * qemu-openpty.c
- *
- * Copyright (c) 2003-2008 Fabrice Bellard
- * Copyright (c) 2010 Red Hat, Inc.
- *
- * Wrapper function qemu_openpty() implementation.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF
[PATCH v2 10/22] hw/block/fdc-isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c
index ab663dce93..fa20450747 100644
--- a/hw/block/fdc-isa.c
+++ b/hw/block/fdc-isa.c
@@ -94,7 +94,7 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
isa->iobase, fdc_portio_list, fdctrl,
"fdc");
-isa_init_irq(isadev, >irq, isa->irq);
+fdctrl->irq = isa_get_irq(isadev, isa->irq);
fdctrl->dma_chann = isa->dma;
if (fdctrl->dma_chann != -1) {
IsaDmaClass *k;
--
2.35.1
[PATCH v2 12/22] hw/char/serial-isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/char/serial-isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index 1b8b303079..7a7ed239cd 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -75,7 +75,7 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp) } index++; -isa_init_irq(isadev, >irq, isa->isairq); +s->irq = isa_get_irq(isadev, isa->isairq); qdev_realize(DEVICE(s), NULL, errp); qdev_set_legacy_instance_id(dev, isa->iobase, 3); -- 2.35.1
[PATCH v2 19/22] hw/rtc/m48t59-isa: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/rtc/m48t59-isa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c
index cd63138e1e..990ea15bce 100644
--- a/hw/rtc/m48t59-isa.c
+++ b/hw/rtc/m48t59-isa.c
@@ -106,7 +106,7 @@ static void m48t59_isa_realize(DeviceState *dev, Error
**errp)
s->model = u->info.model;
s->size = u->info.size;
-isa_init_irq(isadev, >IRQ, d->isairq);
+s->IRQ = isa_get_irq(isadev, d->isairq);
m48t59_realize_common(s, errp);
memory_region_init_io(>io, OBJECT(dev), _io_ops, s, "m48t59", 4);
if (d->io_base != 0) {
--
2.35.1
[PATCH 4/8] meson: drop the .fa library suffix
From: Marc-André Lureau
The .fa suffix was a temporary hack introduced in commit
1f0a1d8a51 ("build-sys hack: link with whole .fa archives") when the
build system was mixed between meson & makefiles. It is no longer
needed.
Signed-off-by: Marc-André Lureau
---
docs/devel/build-system.rst| 5 -
meson.build| 18 +++---
tests/qtest/libqos/meson.build | 1 -
3 files changed, 3 insertions(+), 21 deletions(-)
diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst
index 431caba7aa06..75c30b819799 100644
--- a/docs/devel/build-system.rst
+++ b/docs/devel/build-system.rst
@@ -154,15 +154,10 @@ Subsystem sourcesets:
are then turned into static libraries as follows::
libchardev = static_library('chardev', chardev_ss.sources(),
-name_suffix: 'fa',
build_by_default: false)
chardev = declare_dependency(link_whole: libchardev)
- As of Meson 0.55.1, the special ``.fa`` suffix should be used for everything
- that is used with ``link_whole``, to ensure that the link flags are placed
- correctly in the command line.
-
Target-independent emulator sourcesets:
Various general purpose helper code is compiled only once and
the .o files are linked into all output binaries that need it.
diff --git a/meson.build b/meson.build
index 101a3f2d31ee..40abe86767e8 100644
--- a/meson.build
+++ b/meson.build
@@ -2940,15 +2940,13 @@ qemu_syms = custom_target('qemu.syms', output:
'qemu.syms',
qom_ss = qom_ss.apply(config_host, strict: false)
libqom = static_library('qom', qom_ss.sources() + genh,
-dependencies: [qom_ss.dependencies()],
-name_suffix: 'fa')
+dependencies: [qom_ss.dependencies()])
qom = declare_dependency(link_whole: libqom)
authz_ss = authz_ss.apply(config_host, strict: false)
libauthz = static_library('authz', authz_ss.sources() + genh,
dependencies: [authz_ss.dependencies()],
- name_suffix: 'fa',
build_by_default: false)
authz = declare_dependency(link_whole: libauthz,
@@ -2957,7 +2955,6 @@ authz = declare_dependency(link_whole: libauthz,
crypto_ss = crypto_ss.apply(config_host, strict: false)
libcrypto = static_library('crypto', crypto_ss.sources() + genh,
dependencies: [crypto_ss.dependencies()],
- name_suffix: 'fa',
build_by_default: false)
crypto = declare_dependency(link_whole: libcrypto,
@@ -2967,13 +2964,11 @@ io_ss = io_ss.apply(config_host, strict: false)
libio = static_library('io', io_ss.sources() + genh,
dependencies: [io_ss.dependencies()],
link_with: libqemuutil,
- name_suffix: 'fa',
build_by_default: false)
io = declare_dependency(link_whole: libio, dependencies: [crypto, qom])
libmigration = static_library('migration', sources: migration_files + genh,
- name_suffix: 'fa',
build_by_default: false)
migration = declare_dependency(link_with: libmigration,
dependencies: [zlib, qom, io])
@@ -2983,7 +2978,6 @@ block_ss = block_ss.apply(config_host, strict: false)
libblock = static_library('block', block_ss.sources() + genh,
dependencies: block_ss.dependencies(),
link_depends: block_syms,
- name_suffix: 'fa',
build_by_default: false)
block = declare_dependency(link_whole: [libblock],
@@ -2993,7 +2987,6 @@ block = declare_dependency(link_whole: [libblock],
blockdev_ss = blockdev_ss.apply(config_host, strict: false)
libblockdev = static_library('blockdev', blockdev_ss.sources() + genh,
dependencies: blockdev_ss.dependencies(),
- name_suffix: 'fa',
build_by_default: false)
blockdev = declare_dependency(link_whole: [libblockdev],
@@ -3002,13 +2995,11 @@ blockdev = declare_dependency(link_whole: [libblockdev],
qmp_ss = qmp_ss.apply(config_host, strict: false)
libqmp = static_library('qmp', qmp_ss.sources() + genh,
dependencies: qmp_ss.dependencies(),
-name_suffix: 'fa',
build_by_default: false)
qmp = declare_dependency(link_whole: [libqmp])
libchardev = static_library('chardev', chardev_ss.sources() + genh,
-name_suffix: 'fa',
dependencies: [gnutls],
build_by_default: false)
@@ -3016,7 +3007,6 @@ chardev = declare_dependency(link_whole: libchardev)
hwcore_ss = hwcore_ss.apply(config_host, strict: false)
libhwcore = static_library('hwcore', sources:
[PATCH v2 14/22] hw/input/pckbd: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/input/pckbd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 56c55c5768..4988403f7c 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -749,8 +749,8 @@ static void i8042_realizefn(DeviceState *dev, Error **errp) return; } -isa_init_irq(isadev, >irq_kbd, isa_s->kbd_irq); -isa_init_irq(isadev, >irq_mouse, isa_s->mouse_irq); +s->irq_kbd = isa_get_irq(isadev, isa_s->kbd_irq); +s->irq_mouse = isa_get_irq(isadev, isa_s->mouse_irq); isa_register_ioport(isadev, isa_s->io + 0, 0x60); isa_register_ioport(isadev, isa_s->io + 1, 0x64); -- 2.35.1
[PATCH v2 06/22] isa: Drop unused attributes from ISADevice
Now that the last users of ISADevice::isairq[] have been resolved during the
previous commits, it can be removed for good.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 13 -
include/hw/isa/isa.h | 2 --
2 files changed, 15 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index af5add6a26..c64a14120b 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -87,11 +87,7 @@ qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
void isa_init_irq(ISADevice *dev, qemu_irq *p, unsigned isairq)
{
-assert(dev->nirqs < ARRAY_SIZE(dev->isairq));
-assert(isairq < ISA_NUM_IRQS);
-dev->isairq[dev->nirqs] = isairq;
*p = isa_get_irq(dev, isairq);
-dev->nirqs++;
}
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
@@ -150,14 +146,6 @@ int isa_register_portio_list(ISADevice *dev,
return 0;
}
-static void isa_device_init(Object *obj)
-{
-ISADevice *dev = ISA_DEVICE(obj);
-
-dev->isairq[0] = -1;
-dev->isairq[1] = -1;
-}
-
ISADevice *isa_new(const char *name)
{
return ISA_DEVICE(qdev_new(name));
@@ -244,7 +232,6 @@ static const TypeInfo isa_device_type_info = {
.name = TYPE_ISA_DEVICE,
.parent = TYPE_DEVICE,
.instance_size = sizeof(ISADevice),
-.instance_init = isa_device_init,
.abstract = true,
.class_size = sizeof(ISADeviceClass),
.class_init = isa_device_class_init,
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index d4417b34b6..d80cab5b79 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -83,8 +83,6 @@ struct ISADevice {
DeviceState parent_obj;
/*< public >*/
-int8_t isairq[2]; /* -1 = unassigned */
-int nirqs;
int ioport_id;
};
--
2.35.1
[PATCH v2 21/22] hw/isa/isa-bus: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index c64a14120b..1e8c102177 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -92,8 +92,7 @@ void isa_init_irq(ISADevice *dev, qemu_irq *p, unsigned
isairq)
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
{
-qemu_irq irq;
-isa_init_irq(isadev, , isairq);
+qemu_irq irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, irq);
}
--
2.35.1
[PATCH v2 11/22] hw/char/parallel: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/char/parallel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/parallel.c b/hw/char/parallel.c index b45e67bfbb..adb9bd9be3 100644 --- a/hw/char/parallel.c +++ b/hw/char/parallel.c @@ -553,7 +553,7 @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp) index++; base = isa->iobase; -isa_init_irq(isadev, >irq, isa->isairq); +s->irq = isa_get_irq(isadev, isa->isairq); qemu_register_reset(parallel_reset, s); qemu_chr_fe_set_handlers(>chr, parallel_can_receive, NULL, -- 2.35.1
[PATCH v2 05/22] hw/ppc/pnv: Determine ns16550's IRQ number from QOM property
Determine the IRQ number in the same way as for isa-ipmi-bt. This resolves
the last usage of ISADevice::isairq[] which allows it to be removed.
Signed-off-by: Bernhard Beschow
---
hw/ppc/pnv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 837146a2fb..1e9f6b0690 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -380,9 +380,12 @@ static void pnv_dt_serial(ISADevice *d, void *fdt, int
lpc_off)
cpu_to_be32(io_base),
cpu_to_be32(8)
};
+uint32_t irq;
char *name;
int node;
+irq = object_property_get_int(OBJECT(d), "irq", _fatal);
+
name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
node = fdt_add_subnode(fdt, lpc_off, name);
_FDT(node);
@@ -394,7 +397,7 @@ static void pnv_dt_serial(ISADevice *d, void *fdt, int
lpc_off)
_FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
_FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
-_FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
+_FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
_FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
fdt_get_phandle(fdt, lpc_off;
--
2.35.1
[PATCH v2 07/22] hw/audio/cs4231a: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/audio/cs4231a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c index 7d60ce6f0e..0723e39430 100644 --- a/hw/audio/cs4231a.c +++ b/hw/audio/cs4231a.c @@ -677,7 +677,7 @@ static void cs4231a_realizefn (DeviceState *dev, Error **errp) return; } -isa_init_irq(d, >pic, s->irq); +s->pic = isa_get_irq(d, s->irq); k = ISADMA_GET_CLASS(s->isa_dma); k->register_channel(s->isa_dma, s->dma, cs_dma_read, s); -- 2.35.1
[PATCH v2 08/22] hw/audio/gus: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/audio/gus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/gus.c b/hw/audio/gus.c index e8719ee117..42f010b671 100644 --- a/hw/audio/gus.c +++ b/hw/audio/gus.c @@ -282,7 +282,7 @@ static void gus_realizefn (DeviceState *dev, Error **errp) s->emu.himemaddr = s->himem; s->emu.gusdatapos = s->emu.himemaddr + 1024 * 1024 + 32; s->emu.opaque = s; -isa_init_irq (d, >pic, s->emu.gusirq); +s->pic = isa_get_irq(d, s->emu.gusirq); AUD_set_active_out (s->voice, 1); } -- 2.35.1
[PATCH v2 15/22] hw/ipmi/isa_ipmi_bt: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
Use the original instead such that isa_init_irq() can be removed
eventually.
Signed-off-by: Bernhard Beschow
---
hw/ipmi/isa_ipmi_bt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c
index 02625eb94e..88aa734e9e 100644
--- a/hw/ipmi/isa_ipmi_bt.c
+++ b/hw/ipmi/isa_ipmi_bt.c
@@ -92,7 +92,7 @@ static void isa_ipmi_bt_realize(DeviceState *dev, Error
**errp)
}
if (iib->isairq > 0) {
-isa_init_irq(isadev, >irq, iib->isairq);
+iib->irq = isa_get_irq(isadev, iib->isairq);
iib->bt.use_irq = 1;
iib->bt.raise_irq = isa_ipmi_bt_raise_irq;
iib->bt.lower_irq = isa_ipmi_bt_lower_irq;
--
2.35.1
[PATCH v2 02/22] hw/rtc/m48t59-isa: QOM'ify IRQ number
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/rtc/m48t59-isa.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c
index dc21fb10a5..cd63138e1e 100644
--- a/hw/rtc/m48t59-isa.c
+++ b/hw/rtc/m48t59-isa.c
@@ -42,6 +42,7 @@ struct M48txxISAState {
ISADevice parent_obj;
M48t59State state;
uint32_t io_base;
+uint32_t isairq;
MemoryRegion io;
};
@@ -79,6 +80,7 @@ static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
static Property m48t59_isa_properties[] = {
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
+DEFINE_PROP_UINT32("irq", M48txxISAState, isairq, 8),
DEFINE_PROP_END_OF_LIST(),
};
@@ -97,9 +99,14 @@ static void m48t59_isa_realize(DeviceState *dev, Error
**errp)
M48txxISAState *d = M48TXX_ISA(dev);
M48t59State *s = >state;
+if (d->isairq >= ISA_NUM_IRQS) {
+error_setg(errp, "Maximum value for \"irq\" is: %d", ISA_NUM_IRQS - 1);
+return;
+}
+
s->model = u->info.model;
s->size = u->info.size;
-isa_init_irq(isadev, >IRQ, 8);
+isa_init_irq(isadev, >IRQ, d->isairq);
m48t59_realize_common(s, errp);
memory_region_init_io(>io, OBJECT(dev), _io_ops, s, "m48t59", 4);
if (d->io_base != 0) {
--
2.35.1
[PATCH v2 09/22] hw/audio/sb16: Disuse isa_init_irq()
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). Use the original instead such that isa_init_irq() can be removed eventually. Signed-off-by: Bernhard Beschow --- hw/audio/sb16.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/sb16.c b/hw/audio/sb16.c index 60f1f75e3a..2215386ddb 100644 --- a/hw/audio/sb16.c +++ b/hw/audio/sb16.c @@ -1408,7 +1408,7 @@ static void sb16_realizefn (DeviceState *dev, Error **errp) return; } -isa_init_irq (isadev, >pic, s->irq); +s->pic = isa_get_irq(isadev, s->irq); s->mixer_regs[0x80] = magic_of_irq (s->irq); s->mixer_regs[0x81] = (1 << s->dma) | (1 << s->hdma); -- 2.35.1
[PATCH v2 03/22] hw/input/pckbd: QOM'ify IRQ numbers
Exposing the IRQ numbers as a QOM properties not only allows them to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/input/pckbd.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index baba62f357..56c55c5768 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -26,6 +26,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/timer.h"
+#include "qapi/error.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "hw/acpi/aml-build.h"
@@ -671,6 +672,8 @@ struct ISAKBDState {
KBDState kbd;
bool kbd_throttle;
MemoryRegion io[2];
+uint32_t kbd_irq;
+uint32_t mouse_irq;
};
void i8042_isa_mouse_fake_event(ISAKBDState *isa)
@@ -734,8 +737,20 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
ISAKBDState *isa_s = I8042(dev);
KBDState *s = _s->kbd;
-isa_init_irq(isadev, >irq_kbd, 1);
-isa_init_irq(isadev, >irq_mouse, 12);
+if (isa_s->kbd_irq >= ISA_NUM_IRQS) {
+error_setg(errp, "Maximum value for \"kbd-irq\" is: %d",
+ ISA_NUM_IRQS - 1);
+return;
+}
+
+if (isa_s->mouse_irq >= ISA_NUM_IRQS) {
+error_setg(errp, "Maximum value for \"mouse-irq\" is: %d",
+ ISA_NUM_IRQS - 1);
+return;
+}
+
+isa_init_irq(isadev, >irq_kbd, isa_s->kbd_irq);
+isa_init_irq(isadev, >irq_mouse, isa_s->mouse_irq);
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
@@ -754,6 +769,7 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
static void i8042_build_aml(ISADevice *isadev, Aml *scope)
{
+ISAKBDState *isa_s = I8042(isadev);
Aml *kbd;
Aml *mou;
Aml *crs;
@@ -761,7 +777,7 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
-aml_append(crs, aml_irq_no_flags(1));
+aml_append(crs, aml_irq_no_flags(isa_s->kbd_irq));
kbd = aml_device("KBD");
aml_append(kbd, aml_name_decl("_HID", aml_eisaid("PNP0303")));
@@ -769,7 +785,7 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
aml_append(kbd, aml_name_decl("_CRS", crs));
crs = aml_resource_template();
-aml_append(crs, aml_irq_no_flags(12));
+aml_append(crs, aml_irq_no_flags(isa_s->mouse_irq));
mou = aml_device("MOU");
aml_append(mou, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
@@ -783,6 +799,8 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
static Property i8042_properties[] = {
DEFINE_PROP_BOOL("extended-state", ISAKBDState, kbd.extended_state, true),
DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState, kbd_throttle, false),
+DEFINE_PROP_UINT32("kbd-irq", ISAKBDState, kbd_irq, 1),
+DEFINE_PROP_UINT32("mouse-irq", ISAKBDState, mouse_irq, 12),
DEFINE_PROP_END_OF_LIST(),
};
--
2.35.1
[PATCH v2 01/22] hw/rtc/mc146818rtc: QOM'ify IRQ number
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 2 +-
hw/rtc/mc146818rtc.c | 13 +++--
include/hw/rtc/mc146818rtc.h | 1 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0fe7b69bc4..cb291d121c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -197,7 +197,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(>rtc), BUS(isa_bus), errp)) {
return;
}
-isa_init_irq(ISA_DEVICE(>rtc), >rtc.irq, RTC_ISA_IRQ);
+isa_init_irq(ISA_DEVICE(>rtc), >rtc.irq, s->rtc.isairq);
piix4_dev = dev;
}
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index e61a0cced4..eda9af65c4 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -911,6 +911,11 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
s->base_year = 0;
}
+if (s->isairq >= ISA_NUM_IRQS) {
+error_setg(errp, "Maximum value for \"irq\" is: %d", ISA_NUM_IRQS - 1);
+return;
+}
+
rtc_set_date_from_host(isadev);
switch (s->lost_tick_policy) {
@@ -956,15 +961,17 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq)
{
DeviceState *dev;
ISADevice *isadev;
+RTCState *s;
isadev = isa_new(TYPE_MC146818_RTC);
dev = DEVICE(isadev);
+s = MC146818_RTC(isadev);
qdev_prop_set_int32(dev, "base_year", base_year);
isa_realize_and_unref(isadev, bus, _fatal);
if (intercept_irq) {
qdev_connect_gpio_out(dev, 0, intercept_irq);
} else {
-isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
+isa_connect_gpio_out(isadev, 0, s->isairq);
}
object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
@@ -975,6 +982,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq)
static Property mc146818rtc_properties[] = {
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
+DEFINE_PROP_UINT32("irq", RTCState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
lost_tick_policy, LOST_TICK_POLICY_DISCARD),
DEFINE_PROP_END_OF_LIST(),
@@ -1010,6 +1018,7 @@ static void rtc_reset_hold(Object *obj)
static void rtc_build_aml(ISADevice *isadev, Aml *scope)
{
+RTCState *s = MC146818_RTC(isadev);
Aml *dev;
Aml *crs;
@@ -1020,7 +1029,7 @@ static void rtc_build_aml(ISADevice *isadev, Aml *scope)
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
0x01, 0x08));
-aml_append(crs, aml_irq_no_flags(RTC_ISA_IRQ));
+aml_append(crs, aml_irq_no_flags(s->isairq));
dev = aml_device("RTC");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h
index 5b45b22924..c7586589ad 100644
--- a/include/hw/rtc/mc146818rtc.h
+++ b/include/hw/rtc/mc146818rtc.h
@@ -26,6 +26,7 @@ struct RTCState {
uint8_t cmos_data[128];
uint8_t cmos_index;
int32_t base_year;
+uint32_t isairq;
uint64_t base_rtc;
uint64_t last_update;
int64_t offset;
--
2.35.1
[PATCH v2 04/22] hw/isa/isa-bus: Remove isabus_dev_print()
All isabus_dev_print() did was to print up to two IRQ numbers per
device. This is redundant if the IRQ numbers are present as QOM
properties (see e.g. the modified tests/qemu-iotests/172.out).
Now that the last devices relying on isabus_dev_print() had their IRQ
numbers QOM'ified, the contribution of this function ultimately became
redundant. Remove it.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 16
tests/qemu-iotests/172.out | 26 --
2 files changed, 42 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 6c31398dda..af5add6a26 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -21,21 +21,18 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qapi/error.h"
-#include "monitor/monitor.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "hw/isa/isa.h"
static ISABus *isabus;
-static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *isabus_get_fw_dev_path(DeviceState *dev);
static void isa_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
-k->print_dev = isabus_dev_print;
k->get_fw_dev_path = isabus_get_fw_dev_path;
}
@@ -222,19 +219,6 @@ void isa_build_aml(ISABus *bus, Aml *scope)
}
}
-static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent)
-{
-ISADevice *d = ISA_DEVICE(dev);
-
-if (d->isairq[1] != -1) {
-monitor_printf(mon, "%*sisa irqs %d,%d\n", indent, "",
- d->isairq[0], d->isairq[1]);
-} else if (d->isairq[0] != -1) {
-monitor_printf(mon, "%*sisa irq %d\n", indent, "",
- d->isairq[0]);
-}
-}
-
static void isabus_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/tests/qemu-iotests/172.out b/tests/qemu-iotests/172.out
index 4cf4d536b4..9479b92185 100644
--- a/tests/qemu-iotests/172.out
+++ b/tests/qemu-iotests/172.out
@@ -15,7 +15,6 @@ Testing:
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -43,7 +42,6 @@ Testing: -fda TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -81,7 +79,6 @@ Testing: -fdb TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -135,7 +132,6 @@ Testing: -fda TEST_DIR/t.qcow2 -fdb TEST_DIR/t.qcow2.2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -190,7 +186,6 @@ Testing: -fdb
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -230,7 +225,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -268,7 +262,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2,index=1
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -322,7 +315,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2 -drive
if=floppy,file=TEST_DIR/t
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -380,7 +372,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device
floppy,drive=none0
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -418,7 +409,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device
floppy,drive=none0,unit=1
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -456,7 +446,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -drive
if=none,file=TEST_DIR/t.qco
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
-isa irq 6
[PATCH v2 00/22] isa: Resolve unneeded IRQ attributes from ISADevice
v2:
The newly QOM'ified devices now report an error to the user in their realize
functions if the configured IRQ number is greater than 15.
v1:
The IRQ attributes of ISADevice are hardcoded to support up to two IRQs per
device which creates an artificial limit. By not having the attributes in the
first place, this limitation can be avoided altogether.
The IRQ attributes are mostly used for printing ('info qtree') and there is one
user, hw/ppc/pnv, to use the attributes directly. As it turns out, the printing
is redundant if the IRQ numbers are exposed as QOM properties and hw/ppc/pnv
can be easily ported away.
The patch series is structured as follows: Patch 1-3 QOM'ify the last devices
which rely on printing their IRQ numbers via the ISADevice attributes. Patch
4 and 5 remove the last users of the ISADevice attributes such that they can be
removed in patch 6. The remainder of the patch series is cleanup.
Patch 6 turns isa_init_irq() into a trivial wrapper for isa_get_irq(). That is,
the former function becomes redundant. All users are therefore converted to use
isa_get_irq() directly. Finally, the last patch removes the now unused
isa_init_irq().
Bernhard Beschow (22):
hw/rtc/mc146818rtc: QOM'ify IRQ number
hw/rtc/m48t59-isa: QOM'ify IRQ number
hw/input/pckbd: QOM'ify IRQ numbers
hw/isa/isa-bus: Remove isabus_dev_print()
hw/ppc/pnv: Determine ns16550's IRQ number from QOM property
isa: Drop unused attributes from ISADevice
hw/audio/cs4231a: Disuse isa_init_irq()
hw/audio/gus: Disuse isa_init_irq()
hw/audio/sb16: Disuse isa_init_irq()
hw/block/fdc-isa: Disuse isa_init_irq()
hw/char/parallel: Disuse isa_init_irq()
hw/char/serial-isa: Disuse isa_init_irq()
hw/ide/isa: Disuse isa_init_irq()
hw/input/pckbd: Disuse isa_init_irq()
hw/ipmi/isa_ipmi_bt: Disuse isa_init_irq()
hw/ipmi/isa_ipmi_kcs: Disuse isa_init_irq()
hw/isa/piix4: Disuse isa_init_irq()
hw/net/ne2000-isa: Disuse isa_init_irq()
hw/rtc/m48t59-isa: Disuse isa_init_irq()
hw/tpm/tpm_tis_isa: Disuse isa_init_irq()
hw/isa/isa-bus: Disuse isa_init_irq()
isa: Remove unused isa_init_irq()
hw/audio/cs4231a.c | 2 +-
hw/audio/gus.c | 2 +-
hw/audio/sb16.c | 2 +-
hw/block/fdc-isa.c | 2 +-
hw/char/parallel.c | 2 +-
hw/char/serial-isa.c | 2 +-
hw/ide/isa.c | 2 +-
hw/input/pckbd.c | 26 +
hw/ipmi/isa_ipmi_bt.c| 2 +-
hw/ipmi/isa_ipmi_kcs.c | 2 +-
hw/isa/isa-bus.c | 37 +---
hw/isa/piix4.c | 2 +-
hw/net/ne2000-isa.c | 2 +-
hw/ppc/pnv.c | 5 -
hw/rtc/m48t59-isa.c | 9 -
hw/rtc/mc146818rtc.c | 13 +++--
hw/tpm/tpm_tis_isa.c | 2 +-
include/hw/isa/isa.h | 3 ---
include/hw/rtc/mc146818rtc.h | 1 +
tests/qemu-iotests/172.out | 26 -
20 files changed, 59 insertions(+), 85 deletions(-)
--
2.35.1
Re: [PATCH v4 16/47] target/ppc: implement vclrrb
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote: From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode| 1 + target/ppc/translate/vmx-impl.c.inc | 32 + 2 files changed, 25 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH v4 15/47] target/ppc: implement vclrlb
On 2/22/22 04:36, matheus.fe...@eldorado.org.br wrote:
+static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
+{
+TCGv_i64 rb, mh, ml, tmp,
+ ones = tcg_constant_i64(-1),
+ zero = tcg_constant_i64(0);
+
+rb = tcg_temp_new_i64();
+mh = tcg_temp_new_i64();
+ml = tcg_temp_new_i64();
+tmp = tcg_temp_new_i64();
+
+tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
+tcg_gen_andi_i64(tmp, rb, 7);
+tcg_gen_shli_i64(tmp, tmp, 3);
+tcg_gen_shl_i64(tmp, tcg_constant_i64(-1), tmp);
Reuse ones here. Otherwise,
Reviewed-by: Richard Henderson
r~
