Re: [PULL 0/3] OpenRISC FPU Updates for 8.1
On 5/13/23 01:05, Stafford Horne wrote: The following changes since commit c1eb2ddf0f8075faddc5f7c3d39feae3e8e9d6b4: Update version for v8.0.0 release (2023-04-19 17:27:13 +0100) are available in the Git repository at: https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20230513 for you to fetch changes up to 874c52991e1fbe020812b4b15440b6875369aacf: target/openrisc: Setup FPU for detecting tininess before rounding (2023-05-11 15:40:28 +0100) OpenRISC FPU Updates for 8.1 A few fixes and updates to bring OpenRISC inline with the latest architecture spec updates: - Allow FPCSR to be accessed in user mode - Select tininess detection before rounding - Fix FPE Exception PC value Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~
[PATCH qemu] hw: add ATmega16u4 and ATmega32u4 MCUs
From: rmsyn
Adds support for ATmega16u4 and ATmega32u4 MCU definitions.
Defines interrupts, memory layout, and machine types for generic
ATmega16u4 and ATmega32u4 MCUs.
Signed-off-by: rmsyn
---
hw/avr/arduino.c | 36 ++
hw/avr/atmega.c | 122 +++
hw/avr/atmega.h | 2 +
3 files changed, 160 insertions(+)
diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c
index 48ef478346..be04e412e6 100644
--- a/hw/avr/arduino.c
+++ b/hw/avr/arduino.c
@@ -129,6 +129,34 @@ static void arduino_mega2560_class_init(ObjectClass *oc,
void *data)
amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
};
+static void arduino_mega16u4_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
+
+/*
+ *
https://ww1.microchip.com/downloads/en/devicedoc/atmel-7766-8-bit-avr-atmega16u4-32u4_datasheet.pdf
+ */
+mc->desc= "Arduino Mega 16u4 (ATmega16u4)";
+mc->alias = "mega16u4";
+amc->mcu_type = TYPE_ATMEGA16U4_MCU;
+amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
+};
+
+static void arduino_mega32u4_class_init(ObjectClass *oc, void *data)
+{
+MachineClass *mc = MACHINE_CLASS(oc);
+ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
+
+/*
+ *
https://ww1.microchip.com/downloads/en/devicedoc/atmel-7766-8-bit-avr-atmega16u4-32u4_datasheet.pdf
+ */
+mc->desc= "Arduino Mega 32u4 (ATmega32u4)";
+mc->alias = "mega32u4";
+amc->mcu_type = TYPE_ATMEGA32U4_MCU;
+amc->xtal_hz= 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */
+};
+
static const TypeInfo arduino_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("arduino-duemilanove"),
@@ -146,6 +174,14 @@ static const TypeInfo arduino_machine_types[] = {
.name = MACHINE_TYPE_NAME("arduino-mega-2560-v3"),
.parent= TYPE_ARDUINO_MACHINE,
.class_init= arduino_mega2560_class_init,
+}, {
+.name = MACHINE_TYPE_NAME("arduino-mega-16u4"),
+.parent= TYPE_ARDUINO_MACHINE,
+.class_init= arduino_mega16u4_class_init,
+}, {
+.name = MACHINE_TYPE_NAME("arduino-mega-32u4"),
+.parent= TYPE_ARDUINO_MACHINE,
+.class_init= arduino_mega32u4_class_init,
}, {
.name = TYPE_ARDUINO_MACHINE,
.parent = TYPE_MACHINE,
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index a34803e642..292ad9a447 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -27,6 +27,17 @@ enum AtmegaPeripheral {
GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK, GPIOL,
USART0, USART1, USART2, USART3,
TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5,
+RESET,
+INT0, INT1, INT2, INT3, INT4, INT5, INT6,
+PCINT0,
+USB_GEN, USB_EP,
+WDT,
+SPI,
+ANALOG_COMP,
+ADC,
+EE_READY,
+TWI,
+SPM_READY,
PERIFMAX
};
@@ -98,6 +109,30 @@ static const peripheral_cfg dev168_328[PERIFMAX] = {
[GPIOC] = { 0x26 },
[GPIOB] = { 0x23 },
[GPIOA] = { 0x20 },
+}, dev16u4_32u4[PERIFMAX] = {
+[POWER1]= { 0x65 },
+[POWER0]= { 0x64 },
+[TIMER4]= { 0x4c, POWER1, 4, 0x72, 0x39, true },
+[SPM_READY] = { 0x4a },
+[TWI] = { 0x48 },
+[TIMER3]= { 0x3e, POWER1, 3, 0x71, 0x38, true },
+[EE_READY] = { 0x3c },
+[ADC] = { 0x3a },
+[ANALOG_COMP] = { 0x38 },
+[USART1]= { 0x32, POWER1, 0 },
+[SPI] = { 0x30 },
+[TIMER0]= { 0x2a, POWER0, 5, 0x6e, 0x35, true },
+[TIMER1]= { 0x20, POWER0, 3, 0x6f, 0x36, true },
+[WDT] = { 0x18 },
+[USB_GEN] = { 0x14 },
+[USB_EP]= { 0x16 },
+[PCINT0]= { 0x12 },
+[INT6] = { 0x0e },
+[INT3] = { 0x08 },
+[INT2] = { 0x06 },
+[INT1] = { 0x04 },
+[INT0] = { 0x02 },
+[RESET] = { 0x00 },
};
enum AtmegaIrq {
@@ -117,6 +152,17 @@ enum AtmegaIrq {
TIMER4_COMPC_IRQ, TIMER4_OVF_IRQ,
TIMER5_CAPT_IRQ, TIMER5_COMPA_IRQ, TIMER5_COMPB_IRQ,
TIMER5_COMPC_IRQ, TIMER5_OVF_IRQ,
+RESET_IRQ,
+INT0_IRQ, INT1_IRQ, INT2_IRQ, INT3_IRQ, INT4_IRQ, INT5_IRQ, INT6_IRQ,
+PCINT0_IRQ,
+USB_GEN_IRQ, USB_EP_IRQ,
+WDT_IRQ,
+SPI_IRQ,
+ANALOG_COMP_IRQ,
+ADC_IRQ,
+EE_READY_IRQ,
+TWI_IRQ,
+SPM_READY_IRQ,
IRQ_COUNT
};
@@ -184,6 +230,44 @@ static const uint8_t irq168_328[IRQ_COUNT] = {
[USART3_RXC_IRQ]= 55,
[USART3_DRE_IRQ]= 56,
[USART3_TXC_IRQ]= 57,
+}, irq16u4_32u4[IRQ_COUNT] = {
+[RESET_IRQ] = 1,
+[INT0_IRQ] = 2,
+[INT1_IRQ] = 3,
+[INT2_IRQ] = 4,
+[INT3_IRQ] = 5,
+
Re: [PATCH] configure: make clear that VirtFS is 9p
On Thursday, May 11, 2023 4:12:34 PM CEST Christian Schoenebeck wrote:
> Add '9P' to the summary output section of 'VirtFS' to avoid being
> confused with virtiofs.
>
> Based-on: <20230503130757.863824-1-pefo...@google.com>
> Signed-off-by: Christian Schoenebeck
> ---
> meson.build | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Queued on 9p.next:
https://github.com/cschoenebeck/qemu/commits/9p.next
Thanks!
Best regards,
Christian Schoenebeck
> diff --git a/meson.build b/meson.build
> index 5d8373b608..5d65f53fec 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -3922,8 +3922,8 @@ if have_block
>summary_info += {'Block whitelist (rw)':
> get_option('block_drv_rw_whitelist')}
>summary_info += {'Block whitelist (ro)':
> get_option('block_drv_ro_whitelist')}
>summary_info += {'Use block whitelist in tools':
> get_option('block_drv_whitelist_in_tools')}
> - summary_info += {'VirtFS support':have_virtfs}
> - summary_info += {'VirtFS Proxy Helper support': have_virtfs_proxy_helper}
> + summary_info += {'VirtFS (9P) support':have_virtfs}
> + summary_info += {'VirtFS (9P) Proxy Helper support':
> have_virtfs_proxy_helper}
>summary_info += {'Live block migration':
> config_host_data.get('CONFIG_LIVE_BLOCK_MIGRATION')}
>summary_info += {'replication support':
> config_host_data.get('CONFIG_REPLICATION')}
>summary_info += {'bochs support': get_option('bochs').allowed()}
>
Re: QEMU developers fortnightly call for agenda for 2023-05-16
Am 12. Mai 2023 12:04:07 UTC schrieb Juan Quintela : >Bernhard Beschow wrote: >> Am 12. Mai 2023 07:35:27 UTC schrieb Juan Quintela : >>>juan.quint...@gmail.com wrote: Hi If you are interested in any topic, please let me know. Later, Juan. >>> >>>Hi folks >>> >>>So far what we have in the agenda is: >>> >>>questions from Mark: >>>- Update on single binary? >>>- What’s the status on the “icount” plugin ? >>>- Also I could do with some help on a specific issue on KVM/HVF memory >>>handling >>> >>>From me: >>>- Small update on what is going on with all the migration changes >>> >>>Later, Juan. >>> >>> QEMU developers fortnightly conference call Tuesday 2023-05-16 ⋅ 15:00 – 16:00 Central European Time - Madrid Location https://meet.jit.si/kvmcallmeeting >> >> Hi Juan, >> >> Would it be possible to offer a public calendar entry -- perhaps in >> .ics format -- with above information? Which can be conveniently >> subscribed to via a smartphone app? Which gets updated regularly under >> the same link? Which doesn't (needlessly, anyway) require >> authentcation? > >This is enough? > >https://calendar.google.com/calendar/event?action=TEMPLATE=NWR0NWppODdqNXFyYzAwbzYza3RxN2dob3VfMjAyMzA1MTZUMTMwMDAwWiBlZ2VkN2NraTA1bG11MXRuZ3ZrbDN0aGlkc0Bn=eged7cki05lmu1tngvkl3thids%40group.calendar.google.com=ALL > >If that is not enough, if you know the knob to convince google calendar >to do it I am all ears. The links still asks annoying questions. I'll check for that knob. Best regards, Bernhard > >Later, Juan. >
Re: [PATCH v6 6/7] igb: packet-split descriptors support
On 2023/05/13 0:43, Tomasz Dzieciol wrote:
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 360 ++--
hw/net/igb_regs.h | 9 ++
hw/net/trace-events | 2 +-
3 files changed, 328 insertions(+), 43 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 6d95cccea3..51cd62cedd 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -267,6 +267,29 @@ igb_rx_use_legacy_descriptor(IGBCore *core)
return false;
}
+typedef struct E1000ERingInfo {
+int dbah;
+int dbal;
+int dlen;
+int dh;
+int dt;
+int idx;
+} E1000ERingInfo;
+
+static uint32_t
+igb_rx_queue_desctyp_get(IGBCore *core, const E1000ERingInfo *r)
+{
+return core->mac[E1000_SRRCTL(r->idx) >> 2] & E1000_SRRCTL_DESCTYPE_MASK;
+}
+
+static bool
+igb_rx_use_ps_descriptor(IGBCore *core, const E1000ERingInfo *r)
+{
+uint32_t desctyp = igb_rx_queue_desctyp_get(core, r);
+return desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT ||
+ desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
+}
+
static inline bool
igb_rss_enabled(IGBCore *core)
{
@@ -694,15 +717,6 @@ static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
}
-typedef struct E1000ERingInfo {
-int dbah;
-int dbal;
-int dlen;
-int dh;
-int dt;
-int idx;
-} E1000ERingInfo;
-
static inline bool
igb_ring_empty(IGBCore *core, const E1000ERingInfo *r)
{
@@ -1233,12 +1247,25 @@ igb_read_lgcy_rx_descr(IGBCore *core, struct
e1000_rx_desc *desc,
}
static inline void
-igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
- hwaddr *buff_addr)
+igb_read_adv_rx_single_buf_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
+ hwaddr *buff_addr)
{
*buff_addr = le64_to_cpu(desc->read.pkt_addr);
}
+static inline void
+igb_read_adv_rx_split_buf_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
+hwaddr *buff_addr)
+{
+buff_addr[0] = le64_to_cpu(desc->read.hdr_addr);
+buff_addr[1] = le64_to_cpu(desc->read.pkt_addr);
+}
+
+typedef struct IGBBAState {
+uint16_t written[IGB_MAX_PS_BUFFERS];
+uint8_t cur_idx;
+} IGBBAState;
+
typedef struct IGBPacketRxDMAState {
size_t size;
size_t total_size;
@@ -1249,20 +1276,41 @@ typedef struct IGBPacketRxDMAState {
uint32_t rx_desc_header_buf_size;
struct iovec *iov;
size_t iov_ofs;
+bool do_ps;
bool is_first;
-uint16_t written;
-hwaddr ba;
+IGBBAState bastate;
+hwaddr ba[IGB_MAX_PS_BUFFERS];
} IGBPacketRxDMAState;
static inline void
-igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
- hwaddr *buff_addr)
+igb_read_rx_descr(IGBCore *core,
+ union e1000_rx_desc_union *desc,
+ IGBPacketRxDMAState *pdma_st,
+ const E1000ERingInfo *r)
{
+uint32_t desc_type;
+
if (igb_rx_use_legacy_descriptor(core)) {
-igb_read_lgcy_rx_descr(core, >legacy, buff_addr);
-} else {
-igb_read_adv_rx_descr(core, >adv, buff_addr);
+igb_read_lgcy_rx_descr(core, >legacy, _st->ba[1]);
+pdma_st->ba[0] = 0;
+return;
+}
+
+/* advanced header split descriptor */
+if (igb_rx_use_ps_descriptor(core, r)) {
+igb_read_adv_rx_split_buf_descr(core, >adv, _st->ba[0]);
+return;
+}
+
+/* descriptor replication modes not supported */
+desc_type = igb_rx_queue_desctyp_get(core, r);
+if (desc_type != E1000_SRRCTL_DESCTYPE_ADV_ONEBUF) {
+trace_igb_wrn_rx_desc_modes_not_supp(desc_type);
}
+
+/* advanced single buffer descriptor */
+igb_read_adv_rx_single_buf_descr(core, >adv, _st->ba[1]);
+pdma_st->ba[0] = 0;
}
static void
@@ -1405,6 +1453,13 @@ igb_write_lgcy_rx_descr(IGBCore *core, struct
e1000_rx_desc *desc,
desc->status = (uint8_t) le32_to_cpu(status_flags);
}
+static bool
+igb_rx_ps_descriptor_split_always(IGBCore *core, const E1000ERingInfo *r)
+{
+uint32_t desctyp = igb_rx_queue_desctyp_get(core, r);
+return desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
+}
+
static uint16_t
igb_rx_desc_get_packet_type(IGBCore *core, struct NetRxPkt *pkt, uint16_t
etqf)
{
@@ -1492,16 +1547,67 @@ igb_write_adv_rx_descr(IGBCore *core,
d->wb.lower.lo_dword.pkt_info = cpu_to_le16(rss_type | (pkt_type << 4));
}
+typedef struct IGBSplitDescriptorData {
+bool sph;
+bool hbo;
+size_t hdr_len;
+} IGBSplitDescriptorData;
+
static inline void
-igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
- struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
- uint16_t etqf, bool ts, uint16_t length)
+igb_write_adv_ps_rx_descr(IGBCore
Re: [PATCH 10/13] hw/ide/piix: Reuse PCIIDEState::{cmd,data}_ops
Am 3. Mai 2023 19:52:41 UTC schrieb Mark Cave-Ayland
:
>On 27/04/2023 19:15, Bernhard Beschow wrote:
>
>> Am 27. April 2023 10:52:17 UTC schrieb Mark Cave-Ayland
>> :
>>> On 26/04/2023 21:14, Bernhard Beschow wrote:
>>>
Am 26. April 2023 18:18:35 UTC schrieb Bernhard Beschow
:
>
>
> Am 26. April 2023 11:37:48 UTC schrieb Mark Cave-Ayland
> :
>> On 22/04/2023 16:07, Bernhard Beschow wrote:
>>
>>> Now that PCIIDEState::{cmd,data}_ops are initialized in the base class
>>> constructor there is an opportunity for PIIX to reuse these attributes.
>>> This
>>> resolves usage of ide_init_ioport() which would fall back internally to
>>> using
>>> the isabus global due to NULL being passed as ISADevice by PIIX.
>>>
>>> Signed-off-by: Bernhard Beschow
>>> ---
>>> hw/ide/piix.c | 30 +-
>>> 1 file changed, 13 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/hw/ide/piix.c b/hw/ide/piix.c
>>> index a3a15dc7db..406a67fa0f 100644
>>> --- a/hw/ide/piix.c
>>> +++ b/hw/ide/piix.c
>>> @@ -104,34 +104,32 @@ static void piix_ide_reset(DeviceState *dev)
>>> pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
>>> }
>>> -static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus
>>> *isa_bus,
>>> - Error **errp)
>>> +static void pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus
>>> *isa_bus)
>>> {
>>> static const struct {
>>> int iobase;
>>> int iobase2;
>>> int isairq;
>>> } port_info[] = {
>>> -{0x1f0, 0x3f6, 14},
>>> -{0x170, 0x376, 15},
>>> +{0x1f0, 0x3f4, 14},
>>> +{0x170, 0x374, 15},
>>> };
>>> -int ret;
>>> +MemoryRegion *address_space_io =
>>> pci_address_space_io(PCI_DEVICE(d));
>>> ide_bus_init(>bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
>>> -ret = ide_init_ioport(>bus[i], NULL, port_info[i].iobase,
>>> - port_info[i].iobase2);
>>> -if (ret) {
>>> -error_setg_errno(errp, -ret, "Failed to realize %s port %u",
>>> - object_get_typename(OBJECT(d)), i);
>>> -return false;
>>> -}
>>> +memory_region_add_subregion(address_space_io, port_info[i].iobase,
>>> +>data_ops[i]);
>>> +/*
>>> + * PIIX forwards the last byte of cmd_ops to ISA. Model this using
>>> a low
>>> + * prio so competing memory regions take precedence.
>>> + */
>>> +memory_region_add_subregion_overlap(address_space_io,
>>> port_info[i].iobase2,
>>> +>cmd_ops[i], -1);
>>
>> Interesting. Is this behaviour documented somewhere and/or used in one
>> of your test images at all? If I'd have seen this myself, I probably
>> thought that the addresses were a typo...
>
> I first stumbled upon this and wondered why this code was working with
> VIA_IDE (through my pc-via branch). Then I found the correct offsets
> there which are confirmed in the piix datasheet, e.g.: "Secondary Control
> Block Offset: 0374h"
In case you were wondering about the forwarding of the last byte the
datasheet says: "Accesses to byte 3 of the Control Block are forwarded to
ISA where the floppy disk controller responds."
>>>
>>> Ahhh okay okay I see what's happening here: the PIIX IDE is assuming that
>>> the legacy ioport semantics are in operation here, which as you note above
>>> is where the FDC controller is also accessed via the above byte in the IDE
>>> control block. This is also why you need to change the address above from
>>> 0x3f6/0x376 to 0x3f4/0x374 when trying to use the MemoryRegions used for
>>> the PCI BARs since the PCI IDE controller specification requires a 4 byte
>>> allocation for the Control Block - see sections 2.0 and 2.2.
>>
>> Yes, PIIX assuming that might be the case. Why does it contradict the PCI
>> IDE specification? PIIX seems to apply the apprppriate "workarounds" here.
>
>Can you explain a bit more about where you see the contradiction? At first
>glance it looks okay to me.
>
>>> And that's fine, because the portio_lists used in ide_init_ioport() set up
>>> the legacy IDE ioports so that FDC accesses done in this way can succeed,
>>> and the PIIX IDE is hard-coded to legacy mode. So in fact PIIX IDE should
>>> keep using ide_init_ioport() rather than trying to re-use the BAR
>>> MemoryRegions so I think this patch should just be dropped.
>>
>> I was hoping to keep that patch...
>
>Perhaps a different way to think about it is that from QEMU's perspective a
>BAR is a MemoryRegion that can be dynamically assigned/updated and cannot
Re: [PATCH] linux-user: fix incorrect alignment of pretcode
On 5/12/23 16:38, fa...@mail.ustc.edu.cn wrote:
sigframe::pretcode & rt_sigframe::pretcode must align of 16n-sizeof(void*) instead of 16n, Because rsp align
of 16n before instruction "call" in caller, After "call", push address of "call" in
caller. sp of begin in callee is 16n-sizeof(void*)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1648
Signed-off-by: Fan WenJie
---
linux-user/i386/signal.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
index 60fa07d6f9c..1f019689ae7 100644
--- a/linux-user/i386/signal.c
+++ b/linux-user/i386/signal.c
@@ -197,7 +197,8 @@ struct sigframe {
* to it ensures that the base of the frame has an appropriate alignment
* too.
*/
-struct target_fpstate fpstate QEMU_ALIGNED(8);
+abi_ulong unused QEMU_ALIGNED(8);
+struct target_fpstate fpstate;
};
This is not the correct way to fix this problem.
You need to adjust get_sigframe(), for one, to give you the allocation desired.
r~
Re: [PATCH 09/13] hw/ide/piix: Disuse isa_get_irq()
Am 27. April 2023 12:31:10 UTC schrieb Mark Cave-Ayland
:
>On 26/04/2023 19:25, Bernhard Beschow wrote:
>
>> Am 26. April 2023 11:33:40 UTC schrieb Mark Cave-Ayland
>> :
>>> On 22/04/2023 16:07, Bernhard Beschow wrote:
>>>
isa_get_irq() asks for an ISADevice which piix-ide doesn't provide.
Passing a NULL pointer works but causes the isabus global to be used
then. By fishing out TYPE_ISA_BUS from the QOM tree it is possible to
achieve the same as using isa_get_irq().
This is an alternative solution to commit 9405d87be25d 'hw/ide: Fix
crash when plugging a piix3-ide device into the x-remote machine' which
allows for cleaning up the ISA API while keeping PIIX IDE functions
user-createable.
Signed-off-by: Bernhard Beschow
---
hw/ide/piix.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 6942b484f9..a3a15dc7db 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -104,7 +104,8 @@ static void piix_ide_reset(DeviceState *dev)
pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
}
-static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
+static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus,
+ Error **errp)
{
static const struct {
int iobase;
@@ -124,7 +125,8 @@ static bool pci_piix_init_bus(PCIIDEState *d, unsigned
i, Error **errp)
object_get_typename(OBJECT(d)), i);
return false;
}
-ide_bus_init_output_irq(>bus[i], isa_get_irq(NULL,
port_info[i].isairq));
+ide_bus_init_output_irq(>bus[i],
+isa_bus_get_irq(isa_bus,
port_info[i].isairq));
>>>
>>> I don't think is the right solution here, since ultimately we want to move
>>> the IRQ routing out of the device itself and into the PCI-ISA bridge. I'd
>>> go for the same solution as you've done for VIA IDE in patch 2, i.e. update
>>> the PIIX interrupt handler to set the legacy_irqs in PCIIDEState, and then
>>> wire them up to the ISA IRQs 14 and 15 similar to as Phil as done in his
>>> patches:
>>
>> The problem is user-creatable PIIX-IDE. IMO we should stick to our
>> deprecation process before going this step because this will break it.
>
>Thomas posted some links from previous discussions where it seems that this
>hack is still in use:
>
>https://lists.nongnu.org/archive/html/qemu-block/2019-07/msg00780.html
>https://lists.gnu.org/archive/html/qemu-block/2021-04/msg00746.html
>
>So it seems we can't even deprecate this, as it's working around missing
>functionality in q35 :(
>
>Certainly it seems that we should add a check that will fail the machine if
>there is more than one -device piix3-ide on the command line, since I can't
>see that could ever work properly.
>
>I'm leaning towards adding a device property that must be set to enabled in
>order for PIIX IDE realize() to succeed, leave it disabled by default and only
>enable it for the q35 machine. Does that seem like a reasonable solution?
I'd rather declare this to be out of scope of this series. First, this series
contains a lot of material already. Second, this patch attempts to preserve
current behavior.
This patch is actually a preparation for the next one. In the next patch the
(non-obvious) check for presence of the ISABus get removed so we need this
patch to preserve behavior. Otherwise machines without an ISA bus will crash if
piix3-ide gets user-created. One machine that would crash is the "remote"
machine IIRC.
Best regards,
Bernhard
>
>>> https://patchew.org/QEMU/20230302224058.43315-1-phi...@linaro.org/20230302224058.43315-4-phi...@linaro.org/
>>>
>>> https://patchew.org/QEMU/20230302224058.43315-1-phi...@linaro.org/20230302224058.43315-5-phi...@linaro.org/
>>>
>>> This also reminds me, given that the first patch above is doing wiring in
>>> pc_init1() then we are still missing part of your tidy-up series :/
>>>
bmdma_init(>bus[i], >bmdma[i], d);
ide_bus_register_restart_cb(>bus[i]);
@@ -136,14 +138,29 @@ static void pci_piix_ide_realize(PCIDevice *dev,
Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
+ISABus *isa_bus;
+bool ambiguous;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
bmdma_init_ops(d, _bmdma_ops);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, >bmdma_ops);
+isa_bus = ISA_BUS(object_resolve_path_type("", TYPE_ISA_BUS,
));
+if (ambiguous) {
+error_setg(errp,
+ "More than one ISA bus found while %s supports only
one",
+
Re: [PATCH v4 0/7] Resolve TYPE_PIIX3_XEN_DEVICE
Am 21. April 2023 07:38:10 UTC schrieb "Michael S. Tsirkin" : >On Mon, Apr 03, 2023 at 09:41:17AM +0200, Bernhard Beschow wrote: >> There is currently a dedicated PIIX3 device model for use under Xen. By >> reusing >> existing PCI API during initialization this device model can be eliminated >> and >> the plain PIIX3 device model can be used instead. >> >> Resolving TYPE_PIIX3_XEN_DEVICE results in less code while also making Xen >> agnostic towards the precise south bridge being used in the PC machine. The >> latter might become particularily interesting once PIIX4 becomes usable in >> the >> PC machine, avoiding the "Frankenstein" use of PIIX4_ACPI in PIIX3. > >xen stuff so I assume that tree? Ping > >> Testing done: >> - `make check` >> - Run `xl create` with the following config: >> name = "Manjaro" >> type = 'hvm' >> memory = 1536 >> apic = 1 >> usb = 1 >> disk = [ "file:manjaro-kde-21.2.6-220416-linux515.iso,hdc:cdrom,r" ] >> device_model_override = "/usr/bin/qemu-system-x86_64" >> vga = "stdvga" >> sdl = 1 >> - `qemu-system-x86_64 -M pc -m 2G -cpu host -accel kvm \ >> -cdrom manjaro-kde-21.2.6-220416-linux515.iso` >> >> v4: >> - Add patch fixing latent memory leak in pci_bus_irqs() (Anthony) >> >> v3: >> - Rebase onto master >> >> v2: >> - xen_piix3_set_irq() is already generic. Just rename it. (Chuck) >> >> Tested-by: Chuck Zmudzinski >> >> Bernhard Beschow (7): >> include/hw/xen/xen: Rename xen_piix3_set_irq() to xen_intx_set_irq() >> hw/pci/pci.c: Don't leak PCIBus::irq_count[] in pci_bus_irqs() >> hw/isa/piix3: Reuse piix3_realize() in piix3_xen_realize() >> hw/isa/piix3: Wire up Xen PCI IRQ handling outside of PIIX3 >> hw/isa/piix3: Avoid Xen-specific variant of piix3_write_config() >> hw/isa/piix3: Resolve redundant k->config_write assignments >> hw/isa/piix3: Resolve redundant TYPE_PIIX3_XEN_DEVICE >> >> include/hw/southbridge/piix.h | 1 - >> include/hw/xen/xen.h | 2 +- >> hw/i386/pc_piix.c | 36 +++-- >> hw/i386/xen/xen-hvm.c | 2 +- >> hw/isa/piix3.c| 60 +-- >> hw/pci/pci.c | 2 ++ >> stubs/xen-hw-stub.c | 2 +- >> 7 files changed, 39 insertions(+), 66 deletions(-) >> >> -- >> 2.40.0 >> >
Re: [PATCH 20/20] target/arm: Convert ERET, ERETAA, ERETAB to decodetree
On 5/12/23 15:41, Peter Maydell wrote:
+static bool trans_ERETA(DisasContext *s, arg_reta *a)
+{
+TCGv_i64 dst;
+
+if (!dc_isar_feature(aa64_pauth, s)) {
+return false;
+}
+/* The FGT trap takes precedence over an auth trap. */
+if (s->fgt_eret) {
+gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2);
+return true;
+}
Missing el0 exception, before fgt trap.
Otherwise,
Reviewed-by: Richard Henderson
r~
Re: [PATCH 19/20] target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree
On 5/12/23 15:41, Peter Maydell wrote: Convert the last four BR-with-pointer-auth insns to decodetree. The remaining cases in the outer switch in disas_uncond_b_reg() all return early rather than leaving the case statement, so we can delete the now-unused code at the end of that function. Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 97 ++ 2 files changed, 43 insertions(+), 58 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 18/20] target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree
On 5/12/23 15:41, Peter Maydell wrote: Convert the single-register pointer-authentication variants of BR, BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of the legacy decoder and will be dealt with in the next commit.) Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 7 ++ target/arm/tcg/translate-a64.c | 132 +++-- 2 files changed, 84 insertions(+), 55 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 17/20] target/arm: Convert BR, BLR, RET to decodetree
On 5/12/23 15:41, Peter Maydell wrote: Convert the simple (non-pointer-auth) BR, BLR and RET insns to decodetree. Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 5 target/arm/tcg/translate-a64.c | 55 ++ 2 files changed, 54 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PULL 00/44] Hexagon update
On 5/12/23 22:46, Taylor Simpson wrote:
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
Merge tag 'pull-tcg-20230511-2' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230512-1
for you to fetch changes up to a1c042e1cc4c1da209f7c3e04aec5e622c7bcdc0:
Hexagon (linux-user/hexagon): handle breakpoints (2023-05-12 14:43:14 -0700)
This PR can be broken down into the following parts
- Add support for new architecture versions v68/v69/v71/v73
- Short-circuit writes to temporaries when packet semantics permit this
- Move bookkeeping items from CPUHexagonState to DisasContext
- Correct '-cpu help' output and handling of unknown Hexagon versions
- Enable LLDB debugging
- Miscellaneous fixes and improvements
Please always test 32-bit host. You have a CI failure:
https://gitlab.com/qemu-project/qemu/-/jobs/4279656830#L873
/builds/qemu-project/qemu/target/hexagon/idef-parser/idef-parser.lex: In
function 'yylex':
/builds/qemu-project/qemu/target/hexagon/idef-parser/idef-parser.lex:435:38: error: format
'%lx' expects argument of type 'long unsigned int', but argument 2 has type 'int64_t' {aka
'long long int'} [-Werror=format=]
435 | printf("value = 0x%lx\n", value);
| ^ ~
| |
| int64_t {aka
long long int}
r~
[PATCH 4/4] hw/isa/i82378: Remove unused "io" attribute
The attribute isn't used since commit 5c9736789b79ea49cd236ac326f0a414f63b1015
"i82378: Cleanup implementation".
Signed-off-by: Bernhard Beschow
---
hw/isa/i82378.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c
index 5432ab5065..63e0857208 100644
--- a/hw/isa/i82378.c
+++ b/hw/isa/i82378.c
@@ -34,7 +34,6 @@ struct I82378State {
qemu_irq cpu_intr;
qemu_irq *isa_irqs_in;
-MemoryRegion io;
};
static const VMStateDescription vmstate_i82378 = {
--
2.40.1
[PATCH 0/4] Trivial cleanups
This series: * Removes dead code from omap_uart and i82378 * Resolves redundant code in the i8254 timer devices * Replaces string literals by macro usage for TYPE_ISA_PARALLEL devices Bernhard Beschow (4): hw/timer/i8254_common: Share "iobase" property via base class hw/arm/omap: Remove unused omap_uart_attach() hw/char/parallel: Export TYPE_ISA_PARALLEL macro hw/isa/i82378: Remove unused "io" attribute include/hw/arm/omap.h | 1 - include/hw/char/parallel.h | 2 ++ hw/char/omap_uart.c| 9 - hw/char/parallel-isa.c | 2 +- hw/char/parallel.c | 1 - hw/i386/kvm/i8254.c| 1 - hw/isa/i82378.c| 1 - hw/isa/isa-superio.c | 3 ++- hw/timer/i8254.c | 6 -- hw/timer/i8254_common.c| 6 ++ 10 files changed, 11 insertions(+), 21 deletions(-) -- 2.40.1
[PATCH 3/4] hw/char/parallel: Export TYPE_ISA_PARALLEL macro
Rather than using a string literal which is prone to typos let's use a macro
instead which is caught by the compiler if mistyped.
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel.h | 2 ++
hw/char/parallel-isa.c | 2 +-
hw/char/parallel.c | 1 -
hw/isa/isa-superio.c | 3 ++-
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/hw/char/parallel.h b/include/hw/char/parallel.h
index 0a23c0f57e..29d2876d00 100644
--- a/include/hw/char/parallel.h
+++ b/include/hw/char/parallel.h
@@ -4,6 +4,8 @@
#include "hw/isa/isa.h"
#include "chardev/char.h"
+#define TYPE_ISA_PARALLEL "isa-parallel"
+
void parallel_hds_isa_init(ISABus *bus, int n);
bool parallel_mm_init(MemoryRegion *address_space,
diff --git a/hw/char/parallel-isa.c b/hw/char/parallel-isa.c
index 1ccbb96e70..547ae69304 100644
--- a/hw/char/parallel-isa.c
+++ b/hw/char/parallel-isa.c
@@ -21,7 +21,7 @@ static void parallel_init(ISABus *bus, int index, Chardev
*chr)
DeviceState *dev;
ISADevice *isadev;
-isadev = isa_new("isa-parallel");
+isadev = isa_new(TYPE_ISA_PARALLEL);
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "index", index);
qdev_prop_set_chr(dev, "chardev", chr);
diff --git a/hw/char/parallel.c b/hw/char/parallel.c
index af551e7864..3d32589bb3 100644
--- a/hw/char/parallel.c
+++ b/hw/char/parallel.c
@@ -93,7 +93,6 @@ typedef struct ParallelState {
PortioList portio_list;
} ParallelState;
-#define TYPE_ISA_PARALLEL "isa-parallel"
OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL)
struct ISAParallelState {
diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c
index c81bfe58ef..53b80de0ce 100644
--- a/hw/isa/isa-superio.c
+++ b/hw/isa/isa-superio.c
@@ -20,6 +20,7 @@
#include "hw/isa/superio.h"
#include "hw/qdev-properties.h"
#include "hw/input/i8042.h"
+#include "hw/char/parallel.h"
#include "hw/char/serial.h"
#include "trace.h"
@@ -51,7 +52,7 @@ static void isa_superio_realize(DeviceState *dev, Error
**errp)
} else {
name = g_strdup_printf("parallel%d", i);
}
-isa = isa_new("isa-parallel");
+isa = isa_new(TYPE_ISA_PARALLEL);
d = DEVICE(isa);
qdev_prop_set_uint32(d, "index", i);
if (k->parallel.get_iobase) {
--
2.40.1
[PATCH 2/4] hw/arm/omap: Remove unused omap_uart_attach()
The function is unused since commit
bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove
invalid/unnecessary n8x0_uart_setup()').
Signed-off-by: Bernhard Beschow
---
include/hw/arm/omap.h | 1 -
hw/char/omap_uart.c | 9 -
2 files changed, 10 deletions(-)
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index c275d9b681..067e9419f7 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -724,7 +724,6 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
qemu_irq txdma, qemu_irq rxdma,
const char *label, Chardev *chr);
void omap_uart_reset(struct omap_uart_s *s);
-void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
struct omap_mpuio_s;
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
index 1c890b9201..6848bddb4e 100644
--- a/hw/char/omap_uart.c
+++ b/hw/char/omap_uart.c
@@ -175,12 +175,3 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
return s;
}
-
-void omap_uart_attach(struct omap_uart_s *s, Chardev *chr)
-{
-/* TODO: Should reuse or destroy current s->serial */
-s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
- omap_clk_getrate(s->fclk) / 16,
- chr ?: qemu_chr_new("null", "null", NULL),
- DEVICE_NATIVE_ENDIAN);
-}
--
2.40.1
[PATCH 1/4] hw/timer/i8254_common: Share "iobase" property via base class
Both TYPE_KVM_I8254 and TYPE_I8254 have their own but same implementation of
the "iobase" property. The storage for the property already resides in
PITCommonState, so also move the property definition there.
Signed-off-by: Bernhard Beschow
---
hw/i386/kvm/i8254.c | 1 -
hw/timer/i8254.c| 6 --
hw/timer/i8254_common.c | 6 ++
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c
index 191a26fa57..6a7383d877 100644
--- a/hw/i386/kvm/i8254.c
+++ b/hw/i386/kvm/i8254.c
@@ -301,7 +301,6 @@ static void kvm_pit_realizefn(DeviceState *dev, Error
**errp)
}
static Property kvm_pit_properties[] = {
-DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", KVMPITState,
lost_tick_policy, LOST_TICK_POLICY_DELAY),
DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c
index c8388ea432..c235496fc9 100644
--- a/hw/timer/i8254.c
+++ b/hw/timer/i8254.c
@@ -350,11 +350,6 @@ static void pit_realizefn(DeviceState *dev, Error **errp)
pc->parent_realize(dev, errp);
}
-static Property pit_properties[] = {
-DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
-DEFINE_PROP_END_OF_LIST(),
-};
-
static void pit_class_initfn(ObjectClass *klass, void *data)
{
PITClass *pc = PIT_CLASS(klass);
@@ -366,7 +361,6 @@ static void pit_class_initfn(ObjectClass *klass, void *data)
k->get_channel_info = pit_get_channel_info_common;
k->post_load = pit_post_load;
dc->reset = pit_reset;
-device_class_set_props(dc, pit_properties);
}
static const TypeInfo pit_info = {
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 050875b497..e4093e2904 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -240,6 +240,11 @@ static const VMStateDescription vmstate_pit_common = {
}
};
+static Property pit_common_properties[] = {
+DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
+DEFINE_PROP_END_OF_LIST(),
+};
+
static void pit_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -252,6 +257,7 @@ static void pit_common_class_init(ObjectClass *klass, void
*data)
* done by board code.
*/
dc->user_creatable = false;
+device_class_set_props(dc, pit_common_properties);
}
static const TypeInfo pit_common_type = {
--
2.40.1
[PATCH] virtio: Prepend "virtio" prefix in virtio_error
Rename virtio_error function to virtio_error_impl and wrap it with
virtio_error macro, it adds the "virtio" prefix to the error message.
Remove redundant "virtio" prefixes in virtio_error calls.
Signed-off-by: Maxim Kostin
---
hw/virtio/virtio.c | 10 +-
include/hw/virtio/virtio.h | 6 +-
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 272d930721..efdc425063 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1375,15 +1375,14 @@ static bool virtqueue_map_desc(VirtIODevice *vdev,
unsigned int *p_num_sg,
assert(num_sg <= max_num_sg);
if (!sz) {
-virtio_error(vdev, "virtio: zero sized buffers are not allowed");
+virtio_error(vdev, "zero sized buffers are not allowed");
goto out;
}
while (sz) {
hwaddr len = sz;
-
if (num_sg == max_num_sg) {
-virtio_error(vdev, "virtio: too many write descriptors in "
+virtio_error(vdev, "too many write descriptors in "
"indirect table");
goto out;
}
@@ -1394,7 +1393,7 @@ static bool virtqueue_map_desc(VirtIODevice *vdev,
unsigned int *p_num_sg,
DMA_DIRECTION_TO_DEVICE,
MEMTXATTRS_UNSPECIFIED);
if (!iov[num_sg].iov_base) {
-virtio_error(vdev, "virtio: bogus descriptor or out of resources");
+virtio_error(vdev, "bogus descriptor or out of resources");
goto out;
}
@@ -3563,7 +3562,8 @@ void virtio_device_set_child_bus_name(VirtIODevice *vdev,
char *bus_name)
vdev->bus_name = g_strdup(bus_name);
}
-void G_GNUC_PRINTF(2, 3) virtio_error(VirtIODevice *vdev, const char *fmt, ...)
+G_GNUC_PRINTF(2, 3)
+void virtio_error_impl(VirtIODevice *vdev, const char *fmt, ...)
{
va_list ap;
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index f6b38f7e9c..7022b67c72 100644
--- a/include/hw/virtio/virtio.h
+++ b/include/hw/virtio/virtio.h
@@ -221,7 +221,11 @@ void virtio_init(VirtIODevice *vdev, uint16_t device_id,
size_t config_size);
void virtio_cleanup(VirtIODevice *vdev);
-void virtio_error(VirtIODevice *vdev, const char *fmt, ...) G_GNUC_PRINTF(2,
3);
+#define virtio_error(vdev, fmt, ...) \
+virtio_error_impl(vdev, "%s: " fmt, "virtio", ## __VA_ARGS__)
+
+void virtio_error_impl(VirtIODevice *vdev, const char *fmt, ...)
+G_GNUC_PRINTF(2, 3);
/* Set the child bus name. */
void virtio_device_set_child_bus_name(VirtIODevice *vdev, char *bus_name);
--
2.25.1
Re: [PULL 00/12] target-arm queue
On 5/12/23 16:34, Peter Maydell wrote: Hi; here's a relatively small target-arm queue, pretty much all bug fixes. (There are a few non-arm patches that I've thrown in there too for my convenience :-)) thanks -- PMM The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1: Merge tag 'pull-tcg-20230511-2' ofhttps://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512 for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537: target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100) target-arm queue: * More refactoring of files into tcg/ * Don't allow stage 2 page table walks to downgrade to NS * Fix handling of SW and NSW bits for stage 2 walks * MAINTAINERS: Update Akihiko Odaki's email address * ui: Fix pixel colour channel order for PNG screenshots * docs: Remove unused weirdly-named cross-reference targets * hw/mips/malta: Fix minor dead code issue * Fixes for the "allow CONFIG_TCG=n" changes * tests/qtest: Don't run cdrom boot tests if no accelerator is present * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~
[PULL 0/3] OpenRISC FPU Updates for 8.1
The following changes since commit c1eb2ddf0f8075faddc5f7c3d39feae3e8e9d6b4: Update version for v8.0.0 release (2023-04-19 17:27:13 +0100) are available in the Git repository at: https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20230513 for you to fetch changes up to 874c52991e1fbe020812b4b15440b6875369aacf: target/openrisc: Setup FPU for detecting tininess before rounding (2023-05-11 15:40:28 +0100) OpenRISC FPU Updates for 8.1 A few fixes and updates to bring OpenRISC inline with the latest architecture spec updates: - Allow FPCSR to be accessed in user mode - Select tininess detection before rounding - Fix FPE Exception PC value Stafford Horne (3): target/openrisc: Allow fpcsr access in user mode target/openrisc: Set PC to cpu state on FPU exception target/openrisc: Setup FPU for detecting tininess before rounding target/openrisc/cpu.c| 4 +++ target/openrisc/fpu_helper.c | 13 ++-- target/openrisc/sys_helper.c | 45 --- target/openrisc/translate.c | 72 4 files changed, 81 insertions(+), 53 deletions(-)
[PULL 3/3] target/openrisc: Setup FPU for detecting tininess before rounding
OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..61d748cfdc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(>env, 0); +set_float_detect_tininess(float_tininess_before_rounding, + >env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x; cpu->env.picsr = 0x; -- 2.39.1
[PULL 1/3] target/openrisc: Allow fpcsr access in user mode
As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
Update mtspr and mfspr helpers to support this by moving the is_user
check into the helper.
Link:
https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/sys_helper.c | 45 --
target/openrisc/translate.c | 72
2 files changed, 66 insertions(+), 51 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index ec145960e3..ccdee3b8be 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -29,17 +29,37 @@
#define TO_SPR(group, number) (((group) << 11) + (number))
+static inline bool is_user(CPUOpenRISCState *env)
+{
+#ifdef CONFIG_USER_ONLY
+return true;
+#else
+return (env->sr & SR_SM) == 0;
+#endif
+}
+
void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
-#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = env_archcpu(env);
+#ifndef CONFIG_USER_ONLY
CPUState *cs = env_cpu(env);
target_ulong mr;
int idx;
#endif
+/* Handle user accessible SPRs first. */
switch (spr) {
+case TO_SPR(0, 20): /* FPCSR */
+cpu_set_fpcsr(env, rb);
+return;
+}
+
+if (is_user(env)) {
+raise_exception(cpu, EXCP_ILLEGAL);
+}
+
#ifndef CONFIG_USER_ONLY
+switch (spr) {
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -187,27 +207,33 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
spr, target_ulong rb)
cpu_openrisc_timer_update(cpu);
qemu_mutex_unlock_iothread();
break;
-#endif
-
-case TO_SPR(0, 20): /* FPCSR */
-cpu_set_fpcsr(env, rb);
-break;
}
+#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
{
+OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY
uint64_t data[TARGET_INSN_START_WORDS];
MachineState *ms = MACHINE(qdev_get_machine());
-OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
int idx;
#endif
+/* Handle user accessible SPRs first. */
switch (spr) {
+case TO_SPR(0, 20): /* FPCSR */
+return env->fpcsr;
+}
+
+if (is_user(env)) {
+raise_exception(cpu, EXCP_ILLEGAL);
+}
+
#ifndef CONFIG_USER_ONLY
+switch (spr) {
case TO_SPR(0, 0): /* VR */
return env->vr;
@@ -324,11 +350,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
cpu_openrisc_count_update(cpu);
qemu_mutex_unlock_iothread();
return cpu_openrisc_count_get(cpu);
-#endif
-
-case TO_SPR(0, 20): /* FPCSR */
-return env->fpcsr;
}
+#endif
/* for rd is passed in, if rd unchanged, just keep it back. */
return rd;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 76e53c78d4..43ba0cc1ad 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a)
static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
{
-check_r0_write(dc, a->d);
-
-if (is_user(dc)) {
-gen_illegal_exception(dc);
-} else {
-TCGv spr = tcg_temp_new();
-
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-if (dc->delayed_branch) {
-tcg_gen_mov_tl(cpu_pc, jmp_pc);
-tcg_gen_discard_tl(jmp_pc);
-} else {
-tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
-}
-dc->base.is_jmp = DISAS_EXIT;
-}
+TCGv spr = tcg_temp_new();
-tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
-gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
-}
-return true;
-}
-
-static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
-{
-if (is_user(dc)) {
-gen_illegal_exception(dc);
-} else {
-TCGv spr;
+check_r0_write(dc, a->d);
-if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
-/* For SR, we will need to exit the TB to recognize the new
- * exception state. For NPC, in theory this counts as a branch
- * (although the SPR only exists for use by an ICE). Save all
- * of the cpu state first, allowing it to be overwritten.
- */
+if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+gen_io_start();
if (dc->delayed_branch) {
tcg_gen_mov_tl(cpu_pc, jmp_pc);
tcg_gen_discard_tl(jmp_pc);
@@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr
*a)
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
}
dc->base.is_jmp = DISAS_EXIT;
+}
+
+tcg_gen_ori_tl(spr, cpu_R(dc, a->a),
[PULL 2/3] target/openrisc: Set PC to cpu state on FPU exception
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne
Reviewed-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..8b81d2f62f 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -20,8 +20,8 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "exception.h"
#include "fpu/softfloat.h"
static int ieee_ex_to_openrisc(int fexcp)
@@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp)
return ret;
}
+static G_NORETURN
+void do_fpe(CPUOpenRISCState *env, uintptr_t pc)
+{
+CPUState *cs = env_cpu(env);
+
+cs->exception_index = EXCP_FPE;
+cpu_loop_exit_restore(cs, pc);
+}
+
void HELPER(update_fpcsr)(CPUOpenRISCState *env)
{
int tmp = get_float_exception_flags(>fp_status);
@@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
if (tmp) {
env->fpcsr |= tmp;
if (env->fpcsr & FPCSR_FPEE) {
-helper_exception(env, EXCP_FPE);
+do_fpe(env, GETPC());
}
}
}
--
2.39.1
Re: [PATCH 15/20] target/arm: Convert TBZ, TBNZ to decodetree
On 5/12/23 15:41, Peter Maydell wrote: Convert the test-and-branch-immediate insns TBZ and TBNZ to decodetree. Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 25 + 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 86220569e13..68dc820ece0 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -121,3 +121,10 @@ BL 1 00101 .. @branch @cbzsf:1 .. nz:1 ... rt:5 imm=%imm19 CBZ . 011010 . ... . @cbz + +%imm14 5:s14 !function=times_4 +%imm31_19 31:1 19:5 + rt imm nz bitpos +@tbz. .. nz:1 . .. rt:5 imm=%imm14 bitpos=%imm31_19 + +TBZ . 011011 . . .. . @tbz Similarly with the single-use @format. -tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); +tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, a->rt), (1ULL << a->bitpos)); Can we drop the () around the bit, or use BIT()?. Otherwise, Reviewed-by: Richard Henderson r~
Re: [PATCH 16/20] target/arm: Convert conditional branch insns to decodetree
On 5/12/23 15:41, Peter Maydell wrote: Convert the immediate conditional branch insn B.cond to decodetree. Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 30 ++ 2 files changed, 8 insertions(+), 24 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 14/20] target/arm: Convert CBZ, CBNZ to decodetree
On 5/12/23 15:41, Peter Maydell wrote: +@cbzsf:1 .. nz:1 ... rt:5 imm=%imm19 + +CBZ . 011010 . ... . @cbz Similarly re the single-use @format. Either way, Reviewed-by: Richard Henderson r~
Re: [PULL 45/51] hw/acpi/aml-build: Only generate cluster node in PPTT when specified
Hi Philippe,
On 2023/5/10 18:13, Philippe Mathieu-Daudé wrote:
> Hi Yang,
>
> On 5/1/23 10:16, Michael S. Tsirkin wrote:
>> From: Yicong Yang
>>
>> Currently we'll always generate a cluster node no matter user has
>> specified '-smp clusters=X' or not. Cluster is an optional level
>> and will participant the building of Linux scheduling domains and
>> only appears on a few platforms. It's unncessary to always build
>> it when it cannot reflect the real topology on platforms having no
>> cluster implementation and to avoid affecting the linux scheduling
>> domains in the VM. So only generate the cluster topology in ACPI
>> PPTT when the user has specified it explicitly in -smp.
>>
>> Tested qemu-system-aarch64 with `-smp 8` and linux 6.1-rc1, without
>> this patch:
>> estuary:/sys/devices/system/cpu/cpu0/topology$ cat cluster_*
>> ff # cluster_cpus
>> 0-7 # cluster_cpus_list
>> 56 # cluster_id
>>
>> with this patch:
>> estuary:/sys/devices/system/cpu/cpu0/topology$ cat cluster_*
>> ff # cluster_cpus
>> 0-7 # cluster_cpus_list
>> 36 # cluster_id, with no cluster node kernel will make it to
>> physical package id
>>
>> Acked-by: Michael S. Tsirkin
>> Reviewed-by: Yanan Wang
>> Tested-by: Yanan Wang
>> Signed-off-by: Yicong Yang
>> Message-Id: <20221229065513.55652-3-yangyic...@huawei.com>
>> Reviewed-by: Michael S. Tsirkin
>> Signed-off-by: Michael S. Tsirkin
>> ---
>> include/hw/boards.h | 3 +++
>> hw/acpi/aml-build.c | 2 +-
>> hw/core/machine-smp.c | 2 ++
>> qemu-options.hx | 3 +++
>> 4 files changed, 9 insertions(+), 1 deletion(-)
>
>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 42feb4d4d7..ea331a20d1 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -2030,7 +2030,7 @@ void build_pptt(GArray *table_data, BIOSLinker
>> *linker, MachineState *ms,
>> 0, socket_id, NULL, 0);
>> }
>> - if (mc->smp_props.clusters_supported) {
>> + if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters)
>> {
>> if (cpus->cpus[n].props.cluster_id != cluster_id) {
>> assert(cpus->cpus[n].props.cluster_id > cluster_id);
>> cluster_id = cpus->cpus[n].props.cluster_id;
>> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
>> index b39ed21e65..c3dab007da 100644
>> --- a/hw/core/machine-smp.c
>> +++ b/hw/core/machine-smp.c
>> @@ -158,6 +158,8 @@ void machine_parse_smp_config(MachineState *ms,
>> ms->smp.threads = threads;
>> ms->smp.max_cpus = maxcpus;
>> + mc->smp_props.has_clusters = config->has_clusters;
>
> In another patch Bernhard noticed a QOM class field updated from
> a QOM object, which is an anti-OOP pattern:
> https://lore.kernel.org/qemu-devel/6e514b4b-9185-424e-832e-01813de8e...@gmail.com/
>
> Looking at the codebase I noticed this is what you are doing here.
> By doing so, updating the class field from this particular instance
> results in all other instances being affected.
>
Is it suggested to move this to machinestat so we won't touch the machineclass
members
in the initialization here? In the initial version the has_clusters is placed
in the
ms->smp structure but it's suggested that's not a good place, see the
discussion [1]
[1]
https://lore.kernel.org/qemu-devel/6fa8a6ca-765a-8a55-76fb-91714b740...@huawei.com/
Thanks.
> Currently this isn't really an issue because there are at most 2
> MachineState instances (in a migration case, where we want the same
> machine). However it would be nice to have this bad code example
> cleaned. (Also eventually this could become an issue with heterogeneous
> machines, but I'm not sure yet).
>
> Do you mind sending a patch?
>
> Thanks,
>
> Phil.
>
>> /* sanity-check of the computed topology */
>> if (sockets * dies * clusters * cores * threads != maxcpus) {
>> g_autofree char *topo_msg = cpu_hierarchy_to_string(ms);
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 7f99d15b23..8662568324 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -343,6 +343,9 @@ SRST
>> ::
>> -smp 2
>> +
>> + Note: The cluster topology will only be generated in ACPI and exposed
>> + to guest if it's explicitly specified in -smp.
>> ERST
>> DEF("numa", HAS_ARG, QEMU_OPTION_numa,
>
> .
Re: [PATCH 13/20] target/arm: Convert unconditional branch immediate to decodetree
On 5/12/23 15:40, Peter Maydell wrote: Convert the unconditional branch immediate insns B and BL to decodetree. Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 9 + target/arm/tcg/translate-a64.c | 31 +++ 2 files changed, 20 insertions(+), 20 deletions(-) Reviewed-by: Richard Henderson r~
Re: [PATCH 12/20] target/arm: Convert Extract instructions to decodetree
On 5/12/23 15:40, Peter Maydell wrote: +# Extract + +rd rn rm imm sf +@extract_64 1 .. .. 1 . rm:5 imm:6 rn:5 rd:5 sf=1 +@extract_32 0 .. .. 0 . rm:5 0 imm:5 rn:5 rd:5 sf=0 + +EXTR. 00 100111 . 0 . .. . . @extract_64 +EXTR. 00 100111 . 0 . .. . . @extract_32 When there's exactly one use of the @format, it might be clearer to just merge the two EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 sf=1 Either way, Reviewed-by: Richard Henderson r~
Re: [PATCH 03/20] target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder
On 5/12/23 15:40, Peter Maydell wrote: +!disas_sme(s,insn) && Space after comma. Otherwise, Reviewed-by: Richard Henderson r~
Re: [PATCH 02/20] target/arm: Create decodetree skeleton for A64
On 5/12/23 15:40, Peter Maydell wrote: The A64 translator uses a hand-written decoder for everything except SVE or SME. It's fairly well structured, but it's becoming obvious that it's still more painful to add instructions to than the A32 translator, because putting a new instruction into the right place in a hand-written decoder is much harder than adding new instruction patterns to a decodetree file. As the first step in conversion to decodetree, create the skeleton of the decodetree decoder; where it does not handle instructions we will fall back to the legacy decoder (which will be for everything at the moment, since there are no patterns in a64.decode). Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 20 target/arm/tcg/translate-a64.c | 18 +++--- target/arm/tcg/meson.build | 1 + 3 files changed, 32 insertions(+), 7 deletions(-) create mode 100644 target/arm/tcg/a64.decode Reviewed-by: Richard Henderson r~
Re: [PULL 0/9] Linux user for 8.1 patches
On 5/12/23 12:22, Laurent Vivier wrote: The following changes since commit 7c18f2d663521f1b31b821a13358ce38075eaf7d: Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2023-04-29 23:07:17 +0100) are available in the Git repository at: https://github.com/vivier/qemu.git tags/linux-user-for-8.1-pull-request for you to fetch changes up to 3e7f6c76d529dd4096d043cbd16593e40b469e70: linux-user: fix getgroups/setgroups allocations (2023-05-05 14:37:05 +0200) linux-user pull request 20230512 add open_tree(), move_mount() add /proc/cpuinfo for riscv fixes and cleanup Has CI failures: https://gitlab.com/qemu-project/qemu/-/jobs/4277490874#L884 9191 | ret = get_errno(move_mount(arg1, p2, arg3, p4, arg5)); | ^~ ../linux-user/syscall.c:9191:29: error: nested extern declaration of 'move_mount' [-Werror=nested-externs] ../linux-user/syscall.c:9219:29: error: implicit declaration of function 'open_tree' [-Werror=implicit-function-declaration] 9219 | ret = get_errno(open_tree(arg1, p2, host_flags)); | ^ r~
