Re: [Qemu-devel] [PPC] FPIMM macro and mtfsfi instruction
On Mon, 2007-12-17 at 15:52 +0100, claude vittoria wrote: Hi everybody, I think that I get a wrong result with mtfsfi instruction. I think to get a solution, see below. Could you confirm my opinion ? Seems there have been (once again) a confusion between IBM bit notation (0 is MSB...) and standard one. You're right, FPIMM should be taken using EXTRACT_HELPER(FPIMM, 12, 4); Thanks for the report. translate.c l344:EXTRACT_HELPER(crbD, 21, 5); ... l375:EXTRACT_HELPER(FPIMM, 20, 4); ==FPIMM must be (FPIMM, 12, 4) or crbB 1 for mtfsfi; IMM is bits[16-19] of the instruction in PPC programming environnement 32bit (p8-135). IMM is not one bit before crbD. ... [...] -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/12/10 08:13:10 Modified files: target-ppc : cpu.h Log message: Cleanup: remove useless TARGET_GPR_BITS definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.109r2=1.110
[Qemu-devel] qemu/linux-user socket.h syscall_defs.h ppc/sys...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/12/10 08:24:59 Modified files: linux-user : socket.h syscall_defs.h linux-user/ppc : syscall.h target_signal.h Log message: Various linux-user structures and definitions fixes for PowerPC targets. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/socket.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall_defs.h?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/ppc/syscall.h?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/ppc/target_signal.h?cvsroot=qemur1=1.3r2=1.4
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/12/10 07:40:16 Modified files: target-ppc : cpu.h translate_init.c Log message: Fix PowerPC 74xx definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.108r2=1.109 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.70r2=1.71
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op_helper...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/24 02:03:56 Modified files: target-ppc : cpu.h exec.h helper.c op_helper.c translate.c Log message: Fix incorrect debug prints (reported by Paul Brook). Remove obsolete / duplicated debug prints and improve output consistency. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.107r2=1.108 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.32r2=1.33 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.97r2=1.98 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.72r2=1.73 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.114r2=1.115
Re: [Qemu-devel] qemu hw/ppc_oldworld.c target-ppc/cpu.h target-...
On Fri, 2007-11-23 at 18:22 +, Paul Brook wrote: Furthermore this patch was made in a brainless way, it will be reverted asap. If you think there is a bug in someone else code, submit it a patch, if it's cleaver and addresses a real bug (which is not the case here) it will be accepted and merged. The old code before the patch is obviously broken. It's mixing 64-bit (ppc_gpr_t) and 32-bit (target_ulong) values. It seems you do not understand that what was done was correct. It's not mixing two different types. GPR are of ppc_gpr_t type and should be displayed this way. The only case which is incorrect is not addressed by your patch. But your patch breaks the general case which was OK. As implied by the comments aboce the definition of ppc_gpt_t, and now explicitly in the above the definition of REGX, printing a ppc_gpr_t is obviously not meaningful. I don't claim that my patch is perfect, the code is still a bit of a mess. However, unlike the original code, it is at least self-consistent, and won't crash 64-bit hosts (The fact that it usually prints garbage rather than crashing is an accident of the x64-64 ABI). It's not garbage. On 64 bits hosts, the 64 bits GPR dump is correct. GPR _are 64 bits_ when compiling the ppcemb target and should be displayed as 64 bits value. It's not correct on 32 bits targets, because the highest 32 bits of the GPR should be printed and they are not. Here's the real bug. Your patch break the first case, which was OK, and does not fix any actual bug.
[Qemu-devel] qemu/hw ppc.c ppc405_uc.c ppc4xx_devs.c ppc_chr...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/24 02:56:36 Modified files: hw : ppc.c ppc405_uc.c ppc4xx_devs.c ppc_chrp.c ppc_oldworld.c ppc_prep.c Log message: More PowerPC debug print fixes - hardware emulation pass. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.39r2=1.40 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc405_uc.c?cvsroot=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc4xx_devs.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.53r2=1.54 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.57r2=1.58
Re: [Qemu-devel] qemu hw/ppc_oldworld.c target-ppc/cpu.h target-...
On Fri, 2007-11-23 at 17:33 +, Paul Brook wrote: CVSROOT: /sources/qemu Module name: qemu Changes by: Paul Brook pbrook 07/11/23 17:33:13 Modified files: hw : ppc_oldworld.c target-ppc : cpu.h helper.c op_helper.c Log message: Fix ppc32 register dumps on 64-bit hosts. HOW MANY WILL WE HAVE TO ASK PEOPLE TO RESPECT OTHER WORK ??? Furthermore this patch was made in a brainless way, it will be reverted asap. If you think there is a bug in someone else code, submit it a patch, if it's cleaver and addresses a real bug (which is not the case here) it will be accepted and merged. DOT DO NOT COMMIT AND BREAK OTHER PEOPLE'S WORK ? Is there another way to say it in order to be understood by everyone here ? -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] qemu hw/ppc_oldworld.c target-ppc/cpu.h target-...
On Fri, 2007-11-23 at 19:42 +0100, Jocelyn Mayer wrote: On Fri, 2007-11-23 at 18:22 +, Paul Brook wrote: Furthermore this patch was made in a brainless way, it will be reverted asap. If you think there is a bug in someone else code, submit it a patch, if it's cleaver and addresses a real bug (which is not the case here) it will be accepted and merged. The old code before the patch is obviously broken. It's mixing 64-bit (ppc_gpr_t) and 32-bit (target_ulong) values. It seems you do not understand that what was done was correct. It's not mixing two different types. GPR are of ppc_gpr_t type and should be displayed this way. The only case which is incorrect is not addressed by your patch. But your patch breaks the general case which was OK. As implied by the comments aboce the definition of ppc_gpt_t, and now explicitly in the above the definition of REGX, printing a ppc_gpr_t is obviously not meaningful. I don't claim that my patch is perfect, the code is still a bit of a mess. However, unlike the original code, it is at least self-consistent, and won't crash 64-bit hosts (The fact that it usually prints garbage rather than crashing is an accident of the x64-64 ABI). It's not garbage. On 64 bits hosts, the 64 bits GPR dump is correct. GPR _are 64 bits_ when compiling the ppcemb target and should be displayed as 64 bits value. It's not correct on 32 bits targets Sorry, I meant 32 bits _hosts_ here... , because the highest 32 bits of the GPR should be printed and they are not. Here's the real bug. Your patch break the first case, which was OK, and does not fix any actual bug. -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] qemu hw/ppc_oldworld.c target-ppc/cpu.h target-...
On Fri, 2007-11-23 at 19:10 +, Paul Brook wrote:
The old code before the patch is obviously broken. It's mixing 64-bit
(ppc_gpr_t) and 32-bit (target_ulong) values.
It seems you do not understand that what was done was correct. It's not
mixing two different types. GPR are of ppc_gpr_t type and should be
displayed this way.
It's not garbage. On 64 bits hosts, the 64 bits GPR dump is correct. GPR
_are 64 bits_ when compiling the ppcemb target and should be displayed
as 64 bits value.
Really? Where exactly is the code that uses a 64-bit ppc_gpr_t ?
I don't see any evidence that the high bits of the value is ever used.
Then I took a closer look to the code, to ensure I was not wrong.
The PowerPC 32 on 64 bits hosts is implemented the same way that the
specification says a PowerPC in 32 bits mode should be. Then higher bits
are not garbage. They are what the PowerPC specification say they should
be (apart if they are some bugs in the implementation). The fact that
they are or not used by computations is another point. The fact is the
registers values are correct.
And the fact is that printing a uint64_t on any 64 bits host (x86_64 or
any other) using PRIx64 is exactly what is to be done, according to ISO
C. Then, pretending that it would crash on any host is completelly
pointless.
I see the SPE stuff that uses T0_64 et al, however this still uses
stores the value in the low 32 bits of the {gpr,gprth} pair.
SPE dump is the case that does not work properly. Your patch does not solve
anything here, just breaks the main stream case.
[Qemu-devel] qemu/target-ppc op_helper.h op_helper_mem.h op_...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/22 11:00:46 Modified files: target-ppc : op_helper.h op_helper_mem.h op_mem.h translate.c Added files: target-ppc : op_mem_access.h Log message: Add new sane low-level memory accessors for PowerPC that do proper size or zero extension, with homogenous names. Fix load store strings: those are now endian-sensitive, by definition. Fix dcbz: must always align the target address to a cache line boundary. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.29r2=1.30 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_mem.h?cvsroot=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.113r2=1.114 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem_access.h?cvsroot=qemurev=1.1
[Qemu-devel] qemu/linux-user syscall_defs.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/21 13:06:54 Modified files: linux-user : syscall_defs.h Log message: Fix PowerPC 64 stat and statfs structures definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall_defs.h?cvsroot=qemur1=1.46r2=1.47
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/21 13:08:23 Modified files: target-ppc : cpu.h translate_init.c Log message: Fix PowerPC 7xx definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.104r2=1.105 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.69r2=1.70
[Qemu-devel] qemu/target-ppc op_mem.h translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 11:39:30 Modified files: target-ppc : op_mem.h translate.c Log message: PowerPC instruction fixes: - hrfid is part of the hypervisor extension - fix stfiwx naming CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.112r2=1.113
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 11:41:10 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: PowerPC 620 MMU do not have the same exact behavior as standard 64 bits PowerPC ones. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.102r2=1.103 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.94r2=1.95 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.67r2=1.68
Re: [Qemu-devel] [PATCH] allow setting static devfn values for pci devices from the command line
On Mon, 2007-11-19 at 18:53 +0200, Izik Eidus wrote: Izik Eidus wrote: hi, this patch make it possible to define from the command line a static devfn value for each pci device. it was wrote for addressing a problem that right now qemu devices get their devfn in random way (almost random) the problem with this is that with adding and removing devices some devfn values can be changed for each device. this make (at least) windows unable to understand what happned to your device and mark it in yellow color. (and will want you to reinstall it) in this patch i simply use the device name that was registred with the pci device registration function. in case you have few devices from the same type (same name), it will simply increase each by one so in this case all you have to do is give long enough offset for the devfns from each other. thanks ok here is a fix to two issues that i noticed: 1.in one place i declared static_devfns[MAX_PCI_DEVICS][64] and in other place: static_devfns[MAX_PCI_DEVICS][128] 2.in one place i did a calculation on a pointer line before i checked if it is vaild pointer... anyway here it is again and fixed. It seems that you cannot impose the PCI device numbers mapping, which is likely to be architecture dependant. What you could however change is the PCI bus slot the device is inserted into, the same way you can choose the PCI slot you put a PCI card into on a real machine. The architecture could then determine what is the corresponding PCI device number, given this PCI bus slot numbers. For other PCI devices, like PCI bridges or other internal devices, the PCI slots / devfn are fixed by the architecture. You cannot change them in any way, then it seems pointless to have an option that would change the behavior for any of those devices. The last problem I see is that it seems very ugly to hardcode the device names the way you did in vl.c. This is even false in most cases, as most of those devices are only available for a few machines and are not tunable at all (for example macio or uninorth are only available in some Apple Mac machines, not even all). -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu dyngen.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/18 15:50:41 Modified files: . : dyngen.h Log message: Fix for ISO C compliance: function qualifiers must always come before the return type. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen.h?cvsroot=qemur1=1.17r2=1.18
[Qemu-devel] qemu exec-all.h osdep.h qemu-common.h translate...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 00:38:33 Modified files: . : exec-all.h osdep.h qemu-common.h translate-op.c darwin-user: qemu.h Log message: Avoid duplicated definitions: move common definitions from exec-all.h and qemu-common.h to osdep.h. Include this header in translate-op.c. Make sure it's included first in darwin-user/qemu.h. To avoid discarded inlining bug, define inline as always_inline and always_inline as (( attribute (always_inline) )) __inline__. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/exec-all.h?cvsroot=qemur1=1.71r2=1.72 http://cvs.savannah.gnu.org/viewcvs/qemu/osdep.h?cvsroot=qemur1=1.10r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/qemu-common.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-op.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/darwin-user/qemu.h?cvsroot=qemur1=1.1r2=1.2
[Qemu-devel] qemu vl.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 01:05:22 Modified files: . : vl.c Log message: Mark hex_dump as unused to avoid compilation warnings. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.368r2=1.369
[Qemu-devel] qemu thunk.c thunk.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 01:06:24 Modified files: . : thunk.c thunk.h Log message: Fix attempt to inline recursive functions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/thunk.c?cvsroot=qemur1=1.10r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/thunk.h?cvsroot=qemur1=1.15r2=1.16
[Qemu-devel] qemu hw/ppc_prep.c target-ppc/cpu.h target-ppc/...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 01:48:13 Modified files: hw : ppc_prep.c target-ppc : cpu.h translate_init.c Log message: New PowerPC CPU flag to define the decrementer and time-base source clock. Use it to properly initialize the clock for the PreP target. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.56r2=1.57 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.101r2=1.102 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.66r2=1.67
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/19 01:48:52 Modified files: target-ppc : translate.c Log message: Fix another collision in PowerPC instructions definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.111r2=1.112
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 12:01:45 Modified files: target-ppc : translate.c Log message: Fix collision in PowerPC instructions definitions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.109r2=1.110
[Qemu-devel] qemu/target-ppc cpu.h helper.c helper_regs.h op...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 21:14:09 Modified files: target-ppc : cpu.h helper.c helper_regs.h op_helper.c Log message: PowerPC hypervisor mode is not fundamentally available only for PowerPC 64. Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.97r2=1.98 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.92r2=1.93 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.69r2=1.70
[Qemu-devel] qemu/target-ppc translate.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 22:26:51 Modified files: target-ppc : translate.c translate_init.c Log message: A little more granularity in PowerPC instructions definition is needed in order to implement Freescale cores. Fix efsadd / efssub opcodes. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.110r2=1.111 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.62r2=1.63
[Qemu-devel] qemu/target-ppc cpu.h helper.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 22:42:36 Modified files: target-ppc : cpu.h helper.c translate_init.c Log message: Define Freescale cores specific MMU model, exceptions and input bus. (but do not provide any actual implementation). CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.98r2=1.99 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.93r2=1.94 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.63r2=1.64
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 23:02:21 Modified files: target-ppc : cpu.h translate_init.c Log message: Add definitions for Freescale PowerPC implementations, ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores. Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.99r2=1.100 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.64r2=1.65
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 23:14:54 Modified files: target-ppc : cpu.h translate_init.c Log message: Improve PowerPC instructions set dump. Remove meaningless define from cpu.h Misc cleanups. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.100r2=1.101 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.65r2=1.66
Re: [Qemu-devel] RFC: fix for random Qemu crashes
On Fri, 2007-11-16 at 17:06 +0200, Heikki Lindholm wrote: J. Mayer kirjoitti: Some may have experienced of having some Qemu builds crashing, apparently at random places, but in a reproducable way. I found one reason for this crashes: it appears that with the growth of the op.c file, there may be cases where we could reach the inlining limits of gcc. In such a case, gcc would not inline some declared inline function but would emit a call and provide a separate function. Unfortunately, this is not acceptable in op.o context as it will slowdown the emulation and because the call is likely to break the specific compilation rules (ie reserved registers) used while compiling op.o Does -winline give a warning when this happens? I did not check this, but getting a warning won't help us a lot. The generated Qemu executable would still crash. -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] RFC: fix for random Qemu crashes
On Fri, 2007-11-16 at 15:52 +, Paul Brook wrote: Then, I choosed to replace 'inline' by 'always_inline', which is more invasive but have less risks of side effects. The diff is attached in always_inline.diff. The last thing that helps solve the problem is to change the inlining limits of gcc, at least to compile the op.o file. Presumably we only need one of the last two patches? It seems rather pointless to have always_inline *and* change the inlining heuristics. From the tests I made, it seems that adding always_inline helps but unfortunatelly does not solve all cases. Should check in the gcc source code why it is so... I'm ok with using always_inline for op.o (and things it uses directly) as this is required for correctness. I'm not convinced that that using always_inline everywhere is such a good idea. That's exactly what I did: I changed 'inline' to 'always_inline' in headers that are included by op.c, I did not made any change in other headers. If some of the functions I changed should not be changed, that means that there is another bug, ie those functions should not be used by op.c in any way then should be moved to other headers, or maybe some of those headers should not be included directly or indirectly in op.c... If you see such cases, then we may better fix those issues first... -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] RFC: fix for random Qemu crashes
On Fri, 2007-11-16 at 15:59 +, Jamie Lokier wrote: Heikki Lindholm wrote: J. Mayer kirjoitti: Some may have experienced of having some Qemu builds crashing, apparently at random places, but in a reproducable way. I found one reason for this crashes: it appears that with the growth of the op.c file, there may be cases where we could reach the inlining limits of gcc. In such a case, gcc would not inline some declared inline function but would emit a call and provide a separate function. Unfortunately, this is not acceptable in op.o context as it will slowdown the emulation and because the call is likely to break the specific compilation rules (ie reserved registers) used while compiling op.o Does -winline give a warning when this happens? And can it be repaired with __attribute__((__always_inline__))? As I already reported in the previous message, this helps solve the problem but is not sufficient. Please refer to the proposed patches and the rest of the discussion. Further invastigation also showed me that there may be problems while compiling translate-op.c. It seems the solution would be to change the gcc inlining limits into the BASE_CFLAGS too _and_ define functions in dyngen.h as always_inline. This would also avoid most inline related warnings during the compilation (but maybe not solve all cases, as seen in the op.c case). Reading gcc source code showed me there are cases where a function could be not inline when marked 'inline' without generating any warning message. What I don't know is if those cases are likely to happen during normal compilations, but as the op.c compilation seems to be buggy and never emit those warnings, I guess we can reach those cases. -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu target-ppc/cpu.h target-ppc/op.c target-pp...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/16 14:11:29 Modified files: target-ppc : cpu.h op.c op_helper.c op_helper.h translate.c . : translate-all.c Log message: Always make PowerPC hypervisor mode memory accesses and instructions available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator. Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.93r2=1.94 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.67r2=1.68 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.68r2=1.69 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.28r2=1.29 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.108r2=1.109 http://cvs.savannah.gnu.org/viewcvs/qemu/translate-all.c?cvsroot=qemur1=1.21r2=1.22
[Qemu-devel] qemu/darwin-user main.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 01:52:38 Modified files: darwin-user: main.c Log message: Resynchronize darwin-user target with linux-user: add CPU selection feature, choose the correct default CPU and set the 32/64 bits computation mode properly. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/darwin-user/main.c?cvsroot=qemur1=1.12r2=1.13
[Qemu-devel] qemu configure
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 01:54:46 Modified files: . : configure Log message: Remove ppc64h CPUs definitions from the configure script. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/configure?cvsroot=qemur1=1.172r2=1.173
[Qemu-devel] qemu hw/ppc.c target-ppc/cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 02:04:00 Modified files: hw : ppc.c target-ppc : cpu.h Log message: Add missing definition for number of input pins for the PowerPC 970 bus. Use proper INPUT_NB definitions to allocate PowerPC input pins structure, fixing a buffer overflow in the 6xx bus case. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.37r2=1.38 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.95r2=1.96
[Qemu-devel] qemu darwin-user/main.c hw/ppc.c linux-user/mai...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 01:37:44 Modified files: darwin-user: main.c hw : ppc.c linux-user : main.c target-ppc : cpu.h helper.c helper_regs.h translate_init.c Log message: Always make all PowerPC exception definitions visible. Always make the hypervisor timers available. Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases that cannot be properly handled with the current PowerPC CPU definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/darwin-user/main.c?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.36r2=1.37 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.154r2=1.155 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.94r2=1.95 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.91r2=1.92 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.60r2=1.61
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/17 02:16:14 Modified files: target-ppc : cpu.h translate_init.c Log message: Make the PowerPC MMU model, exception model and input bus model typedefed enums. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.96r2=1.97 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.61r2=1.62
Re: [Qemu-devel] [PATCH] target_posix_types.h
On Wed, 2007-11-14 at 17:36 +, Thiemo Seufer wrote: Jocelyn Mayer wrote: On Wed, 2007-11-14 at 08:59 -0700, Thayne Harbaugh wrote: This patch, 44_target_posix_types.patch provides target specific posix types. These types improve target structure creation, code similarity to kernel code and improve type casting for assignment between target and host. Hi, This seems not OK for ppc/ppc64. There is no ppc64 subdirectory anymore in the linux-user directory. ppc and ppc64 targets have been merged, as it is in recent kernels, so all the definitions should go in the ppc subdirectory, using #ifdef TARGET_PPC64 when there are differences; but there should be very few: there are only 2 ifdef __powerpc64__ in the linux-2.6.23/include/asm-powerpc/posix_types.h file. I figure some conditionals went missing, on 32-bit Linux/ppc it fails to compile. [...] Ooops... Thanks for the report, it looks like T0_64, ..., are not properly declared in this case. I'll take a look. -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu/target-ppc cpu.h exec.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/14 18:45:53 Modified files: target-ppc : cpu.h exec.h Log message: Fix PowerPC targets compilation on 32 bits hosts: now that the SPE extension is available for all targets, we always need to have some 64 bits temporary registers. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.92r2=1.93 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.31r2=1.32
[Qemu-devel] qemu/target-ppc translate.c translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/14 01:08:45 Modified files: target-ppc : translate.c translate_init.c Log message: Reorganize PowerPC instructions categories, add icbi separate case. Fix frsqrtes instruction opcode. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.106r2=1.107 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.59r2=1.60
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/14 05:26:46 Modified files: target-ppc : translate.c Log message: Fix invalid PowerPC 64 rldimi optimized case. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.107r2=1.108
[Qemu-devel] qemu/target-ppc translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 23:40:49 Modified files: target-ppc : translate_init.c Log message: Add PVR and SPR definition for most embedded PowerPC from Freescale. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.58r2=1.59
[Qemu-devel] qemu/target-ppc cpu.h op_template.h translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 23:29:14 Modified files: target-ppc : cpu.h op_template.h translate.c Log message: PowerPC SPE extension fix: must always preserve GPR high bits when running in 32 bits mode. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.91r2=1.92 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.14r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.105r2=1.106
[Qemu-devel] qemu/hw ppc_chrp.c ppc_oldworld.c ppc_prep.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/11 14:44:28 Modified files: hw : ppc_chrp.c ppc_oldworld.c ppc_prep.c Log message: Fix PowerPC boot device selection. Fix gcc warning in PowerPC PreP machine init routine. Add second IDE channel to Heathrow Mac machine (still not handled by OHW). CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.50r2=1.51 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.53r2=1.54
[Qemu-devel] qemu/target-ppc helper.c op.c op_helper.c trans...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 00:04:48 Modified files: target-ppc : helper.c op.c op_helper.c translate.c Log message: Fix usage of the -1 constant in the PowerPC target code: fix invalid size casts and/or sign-extensions. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.89r2=1.90 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.64r2=1.65 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.66r2=1.67 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.103r2=1.104
[Qemu-devel] qemu/target-ppc op.c op_mem.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 00:50:50 Modified files: target-ppc : op.c op_mem.h Log message: More PowerPC target -1 usage fixes (reservation address). CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.65r2=1.66 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.23r2=1.24
[Qemu-devel] qemu configure darwin-user/main.c linux-user/ma...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/12 01:56:19 Modified files: . : configure darwin-user: main.c linux-user : main.c target-ppc : cpu.h helper.c op.c op_helper.c op_helper.h op_mem.h op_template.h translate.c Log message: Allow use of SPE extension by all PowerPC targets, adding gprh registers to store GPR MSBs when GPRs are 32 bits. Remove not-needed-anymore ppcemb-linux-user target. Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/configure?cvsroot=qemur1=1.171r2=1.172 http://cvs.savannah.gnu.org/viewcvs/qemu/darwin-user/main.c?cvsroot=qemur1=1.10r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.148r2=1.149 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.90r2=1.91 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.90r2=1.91 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.66r2=1.67 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.67r2=1.68 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.27r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.24r2=1.25 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.13r2=1.14 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.104r2=1.105
[Qemu-devel] qemu/target-ppc cpu.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/10 23:51:03 Modified files: target-ppc : cpu.h translate_init.c Log message: Allow selection of PowerPC CPU giving a PVR. Remove unused pvr_mask field from CPU definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.89r2=1.90 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.57r2=1.58
[Qemu-devel] qemu/target-ppc op.c op_helper.c op_helper.h tr...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/11 00:18:34 Modified files: target-ppc : op.c op_helper.c op_helper.h translate.c Log message: Optimize PowerPC overflow flag computation in most useful cases. Use the same routines to check overflow for addo, subfo and PowerPC 405 multiply and add cases. Fix carry reset in addme(o) and subfme(o) cases. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.62r2=1.63 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.63r2=1.64 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.26r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.102r2=1.103
[Qemu-devel] qemu/target-ppc op.c op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/11 00:33:09 Modified files: target-ppc : op.c op_helper.c Log message: Fix POWER abs abso computation. Fix PowerPC SPE evabs evneg (thanks to Fabrice Bellard for reporting the bug) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.63r2=1.64 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.64r2=1.65
[Qemu-devel] qemu vl.c hw/pc.c hw/ppc_chrp.c hw/ppc_oldworld...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/11 01:50:45 Modified files: . : vl.c hw : pc.c ppc_chrp.c ppc_oldworld.c ppc_prep.c Log message: More generic boot devices specification, allowing more devices to be specified and avoiding per-target hardcoded limitations. The machine implementations can then check if the given devices match the actual hardware implementation and firmware API. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.358r2=1.359 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pc.c?cvsroot=qemur1=1.91r2=1.92 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.49r2=1.50 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.52r2=1.53
Re: [Qemu-devel] Removal of some target CPU macros
On Wed, 2007-11-07 at 19:32 +0100, Fabrice Bellard wrote: I noticed that some target CPUs macros have been added while they do not seem necessary. I don't like that because it introduces more #ifdefs which prevent making a version supporting simultaneously all the CPUs. In particular I saw the following: - TARGET_MIPSN32 : it is always combined with TARGET_MIPS64 in target-mips/. If its only usage is to select a different Linux ABI, then I suggest keeping TARGET_MIPS64 and using another define to choose that. - TARGET_PPC64H, TARGET_PPCEMB : I see no reason why they cannot be handled dynamically as the other PowerPC CPU types, provided that TARGET_PPC64 is defined. Is it the long term plan ? PowerPC embedded models are already available (should say should be as none are actually implemented) when PPC64 is defined. But as those are mainly PowerPC 32 with some extensions to manipulate the 64 bits GPR, it's a great help if we can avoid doing all operations in 64 bits when running on a 32 bits host (which would greatly decrease performances by at least a factor of two, which is not acceptable). Then having a specific 32 bits target using 64 bits register is very useful if one want to use those features, but may be disabled if the host is 64 bits. Note that most (all ?) embedded Freescale PowerPC microcontrollers implement those extensions and that some ones are greatly interrested with having an usable emulation avaible for those CPUs. The PowerPC 64 with hypervisor mode support could be removed only if: - the fact of emulating hypervisor feature do not slowdown the emulator (which I greatly doubt, but there may be great surprises) - someone provide an open-source hypervisor, compatible with the ones used on real machines, that would allow at least Linux to be able to run on a CPU with hypervisor mode available. Most 64 bits PowerPC, including the 970 (ie G5) have the hypervisor mode support implemented. If the hypervisor mode emulation is present, the OS won't be allowed to access most SPR and some exceptions will need to have some specific handlers in the hypervisor firmware. As I don't know such a software available, the hypervisor mode can not be enabled for standard PowerPC 64 emulation; or no-one will be able to actually use the emulator, except if using the venerable but mostly undocumented (and nearly impossible to find on real hardware) PowerPC 620 CPU. Furthermore, running (or emulating) a SMP machine on a 64 bits PowerPC with hypervisor features without hypervisor software is exactly impossible. Then I don't see how we can do without a separated target for hypervisor features support.
[Qemu-devel] qemu host-utils.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/05 13:01:41 Modified files: . : host-utils.c Log message: Code used by the linux-user targets should not use vl.h. Include exec.h instead. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/host-utils.c?cvsroot=qemur1=1.5r2=1.6
[Qemu-devel] qemu host-utils.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/05 13:16:24 Modified files: . : host-utils.h Log message: Fix muls64 prototype to match the actual implementation. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/host-utils.h?cvsroot=qemur1=1.3r2=1.4
[Qemu-devel] qemu/hw grackle_pci.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 08:49:01 Modified files: hw : grackle_pci.c Log message: Fix grackle (in fact MPC106) PCI host bridge header to avoid confusing firmwares and OSes. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/grackle_pci.c?cvsroot=qemur1=1.7r2=1.8
[Qemu-devel] qemu/hw fdc.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 17:17:09 Modified files: hw : fdc.c Log message: Fix memory corruption: bdrv_read/write API has been changed to take nb_sectors instead of len in bytes but the fdc driver has never been fixed. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/fdc.c?cvsroot=qemur1=1.30r2=1.31
[Qemu-devel] qemu/hw fdc.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/05 03:11:37 Modified files: hw : fdc.c Log message: No functional changes: remove dead code and fix indentation wrapping lines. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/fdc.c?cvsroot=qemur1=1.31r2=1.32
[Qemu-devel] qemu/linux-user main.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/03 13:22:08 Modified files: linux-user : main.c Log message: Fix incorrect PowerPC instruction fetch exception dump. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.139r2=1.140
[Qemu-devel] qemu/target-ppc cpu.h exec.h helper.c op_helper...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/03 13:37:12 Modified files: target-ppc : cpu.h exec.h helper.c op_helper.c translate_init.c Log message: PowerPC MMU and exception fixes: * PowerPC 601 (and probably POWER/POWER2) uses a different BAT format than later PowerPC implementation. * Bugfix in BATs check: must not stop after 4 BATs when more are provided. * Enable POWER 'rac' instruction. * Fix exception prefix for all supported PowerPC implementations. * Fix exceptions, MMU model and bus model for PowerPC 601 620. * Enable PowerPC 620 as it could mostly boot a PreP target. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.86r2=1.87 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.30r2=1.31 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.86r2=1.87 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.61r2=1.62 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.53r2=1.54
[Qemu-devel] qemu/target-ppc translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/03 14:23:08 Modified files: target-ppc : translate_init.c Log message: Fix PowerPC high BATs access: BAT number was incorrect. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.54r2=1.55
[Qemu-devel] qemu/hw macio.c mac_nvram.c ppc_chrp.c ppc_mac....
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 01:16:04 Modified files: hw : macio.c mac_nvram.c ppc_chrp.c ppc_mac.h ppc_oldworld.c Log message: Fix PowerMac NVRAM device. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/macio.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mac_nvram.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_mac.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemur1=1.3r2=1.4
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 01:57:29 Modified files: target-ppc : translate.c Log message: Improve PowerPC CPU state dump. Dump NIP on SPR access faults. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.100r2=1.101
[Qemu-devel] qemu/target-ppc cpu.h helper.c helper_regs.h op...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/11/04 02:55:34 Modified files: target-ppc : cpu.h helper.c helper_regs.h op.c op_helper.c op_helper.h translate.c translate_init.c Log message: PowerPC 601 need specific callbacks for its BATs setup. Implement PowerPC 601 HID0 register, needed for little-endian mode support. As a consequence, we need to merge hflags coming from MSR with other ones. Use little-endian mode from hflags instead of MSR during code translation. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.87r2=1.88 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.61r2=1.62 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.62r2=1.63 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.25r2=1.26 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.101r2=1.102 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.55r2=1.56
Re: [Qemu-devel] qemu-system-ppc problem with PVR access from user space
On Fri, 2007-11-02 at 08:57 -0500, Jason Wessel wrote: J. Mayer wrote: On Fri, 2007-11-02 at 08:04 -0500, Jason Wessel wrote: The typical kernel + user space I boot on the prep machine no longer boots due to an issue accessing the PVR special purpose register. When the PVR is accessed from user space, it should generate an exception with the PC set to the instruction that it occurred at when it saves to the stack. In the latest CVS, it is off by 4 bytes. With out the fix /sbin/init gets killed because the kernel's trap handler which does the userspace emulation of the instruction does not clean up the trap. I am using the attached patch to work around the problem, but I wonder if there is a more generic problem that was introduced as a regression with all ppc merges in the last month or so, given this used to work fine through the generic handler. Any insight into this would certainly be useful. Seems like I made a mistake for program exception generation while fixing floating-point ones, I'm sorry. Your patch is incorrect but the one attached should fix the problem. Could you please check it in your case ? That worked quite well. Now my patch is back to normal. I use the attached patch to silence the warning about the privileged access else it prints every time the glibc processor feature check is used. The only difference of course from the last one is that the PC no longer needs to be adjusted, much like before. The other option would be for you to remove the printf of the debug information? Perhaps that was something accidentally left behind? No, it's not accidental. An application accessing priviledged SPR, including the PVR, is likely to be buggy. I checked in the kernel (2.6.23), trapping the mfpvr instruction is a huge bug because it breaks the virtualisation features of the PowerPC architecture. Application like mol will suffer of this, not being able to pretend the virtualized CPU is not the same as the host CPU. The PowerPC architecture has been designed to be fully virtualisable but the vanilla Linux kernel breaks this useful feature. The bug is then to be fixed in the kernel (and the glibc if it really uses mfpvr). The kernel may provide informations about the CPU features to the userland (but this is absolutelly not PowerPC specific) but it's very important that it never shows priviledge resources directly to user programs, or the model is broken and virtualisation application won't be able to run properly anymore. -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] qemu Makefile.target vl.h hw/cuda.c hw/grackle_...
On Fri, 2007-11-02 at 17:18 +0200, Blue Swirl wrote: On 11/2/07, J. Mayer [EMAIL PROTECTED] wrote: On Thu, 2007-11-01 at 23:13 +0100, J. Mayer wrote: On Thu, 2007-11-01 at 21:53 +0200, Blue Swirl wrote: On 11/1/07, Blue Swirl [EMAIL PROTECTED] wrote: On 10/29/07, Jocelyn Mayer [EMAIL PROTECTED] wrote: CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 23:42:18 Modified files: . : Makefile.target vl.h hw : cuda.c grackle_pci.c heathrow_pic.c ppc.c ppc_chrp.c ppc_prep.c Added files: hw : mac_dbdma.c mac_nvram.c macio.c ppc_mac.h ppc_oldworld.c Log message: * sort the PowerPC target object files * make PowerPC NVRAM accessors generic to be able to use a MacIO NVRAM instead of the M48T59 one * split PowerMac targets code: - move all PowerMac related definitions and prototypes into hw/ppc_mac.h - add hw/mac_dbdma.c, hw/mac_nvram.c and macio.c which implements shared PowerMac devices - define the g3bw machine in a new hw/ppc_oldworld.c file * Fix the g3bw target: - fix the Grackle host PCI device - connect the Heathrow PIC to the PowerPC 6xx bus pins CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemur1=1.212r2=1.213 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.280r2=1.281 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/cuda.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/grackle_pci.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/heathrow_pic.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.34r2=1.35 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.44r2=1.45 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mac_dbdma.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mac_nvram.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/macio.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_mac.h?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemurev=1.1 You broke sparc64-softmmu build with this patch. I am missing something ? I rebuilt all available targets before commiting... but I now see sparc64-softmmu seems not to be in the available targets, which could explain I cannot check if it compiles or not... As it been removed by mistake ? I think the best solution to fix this is to put the nvram helpers to m48t59.h as inline functions instead of duplicating the code in several places. You mean the NVRAM_set / get_xxx ? I was to remove the definitions from vl.h, I have to say, because those are supposed to be PowerPC (in fact OpenHack'Ware) related hacks. Those functions will never go in m48t59.h as they are not related with m48t59. Apple machine don't have such a device (even if Qemu pretend it has, this is to be removed in the days to come) but need those functions to pass arguments to the firmware. What I needed to do (and that what I did commit) is make those routines independant from m48t59 so I can remove this device from ppc_chrp.c and ppc_oldworld.c and use the real Mac nvram instead (but ppc_prep.c still uses m48t59...). I see. Should sun4m use these functions too? On the other hand, there is no need to be too independent on Sparc, because I think all Sun4u machines use m48t59 and sun4m machines have either m48t08 or older m48t02 (not supported yet). So if you prefer, sun4u could use the same approach as sun4m and not use these functions? Depends on how you feel about it... If there is a real need to have a generic devices registers and/or internal memory accessor used during the target machine initialisation (the model I propose could be used not only for NVRAM...), then the code should be made more generic (ie renaming the nvram_t type with a more generic name) and only one implementation should be kept. If this is only useful for the PowerPC target initialisation, then you should keep using the m48t59 only implementation you have now for Sparc64 and the PowerPC NVRAM_xxx functions should not be declared in vl.h. I would say that having a generic accessor for devices during machine init can be useful and the implementation I provided may be sufficient for most usages. But it may also be not so useful ? ... [...] -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] Re: emu errors for creqv,crnand,crnor,crorc ?
On Wed, 2007-10-31 at 12:37 +0100, Julian Seward wrote: Hi Jocelyn Hi, I ran valgrind's ppc32 insn set tests and got the impression that the above insns are not correctly implemented. It seems like 7 bits of CR are set to 1 and one is set to 0, when it should be the other way around. Below is a simple test case. On QEMU it prints result is 000fc000 and on a real 7447 result is 4000 Similar behaviour for creqv, crnand, crnor. But cror, crand, crxor work OK. So maybe it is related to the inverted-result-sense? But the strange thing is, ~0xFC != 0x04. Thanks for testing and for the report ! I have to admit I never did extensive test on CR operations the same way I did for arithmetic and logical ones. What is strange is that 0xFC + 0x04... I will have to check all the CR ops, I guess... I also got a 74xx CPU at home, then I will try to compare running step-by-step, if needed. I'll tell you when I'll find the bug... -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] Re: emu errors for creqv,crnand,crnor,crorc ?
On Wed, 2007-10-31 at 14:39 +0100, Julian Seward wrote: way around. Below is a simple test case. On QEMU it prints result is 000fc000 and on a real 7447 result is 4000 What is strange is that 0xFC + 0x04... I will have to check all the CR ops, I guess... Another strange thing is that 000fc000 does not have 'fc' byte-aligned inside CR, if you see what I mean. If it was fc00 or 00fc, some byte-inversion mistake would seem likely. This isn't a 74xx specific result. I'm sure any ppc should produce 4000. The test is very simple: make CR=0 then do crorc 17,14,15. So only 1 bit in CR will then be set - all others are zero. I guess the problem is the CRops are implemented this way: - get the bit from crfA - get the bit from crfB - do the logical operation - store the result bit As the faulting ops are the one that do a complement, it's quite sure that the problem is that the result bit is not properly masked before being stored. Then the '4' bit is OK, but you also get 'noisy' other bits that should have been masked before the store. As the condition register is stored as 8 4 bits registers, this would affect only the updated CR field.
Re: [Qemu-devel] How to split vl.h
On Wed, 2007-10-31 at 20:12 +0200, Blue Swirl wrote: Hi, Hi, With the automatic dependency rule installed, modifying vl.h causes all files to be recompiled. This is of course the correct action, but it's a major slowdown for development too. How should we split vl.h into smaller pieces? Give each device a header file, like m48t59? What about other stuff exported from vl.c? It seems to me that a lot of things could go back in headers in the hw subdirectory. A quick and simple approach could be to create a hw/hw.h file and move everything from vl.h that is only used in the hw subdirectory. This way, we would break the strong compile-time dependencies between the hardware library and the rest of the emulation code. I think there are some things, like PC serial, USB, ... that could be left in this kind of header without any issue: they're widely used and are not likely to change too often. Some other architecture specific devices would better have their own header (like the m48t59.h file) or maybe a target dependant header could be sufficient (quite like the ppc_mac.h I added a few days ago). Having this kind of header could also be great so we could put the machines extern definition in it and only include this header file in vl.c (not vl.h !) to get, for example, the defined machine list for the current target architecture (and not all possible machines as it is now)... It also seems that some hardware dependent stuffs are currently implemented in vl.c, like the bloc devices or USB registration code, that prevent the related definitions to be isolated in the hw subdirectory. Splitting vl.c to move those functions into separate file(s) in hw would allow moving a lot of definitions in the hw subdirectory. Ideally, vl.c should be hw / target independant and call the proper routines to do all hardware implementation dependant initialisations, imho. Those are just ideas, maybe some are too complicated to be done in a short timeline; and there may be better solutions... if any other ideas... -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu/target-ppc op.c op_template.h translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/31 22:02:17 Modified files: target-ppc : op.c op_template.h translate.c Log message: Fix CR ops with complement, thanks to Julian Seward for testing and reporting the bug : * remove bugged CR ops specific micro-ops * use standard and / or / shift operations instead * comment not-used-anymore op_store_T1_crf_crf micro-op template. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.60r2=1.61 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_template.h?cvsroot=qemur1=1.12r2=1.13 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.98r2=1.99
[Qemu-devel] qemu vl.h hw/ppc_chrp.c hw/ppc_oldworld.c hw/pp...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/29 10:19:50 Modified files: . : vl.h hw : ppc_chrp.c ppc_oldworld.c ppc_prep.c Log message: PowerPC 601 / 620 / 970 need a 1MB firmware. This option is not allowed for PowerMac, as it would overlap with NVRAM. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.281r2=1.282 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.45r2=1.46 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.48r2=1.49
[Qemu-devel] qemu/hw ppc.c ppc405_uc.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/29 10:22:58 Modified files: hw : ppc.c ppc405_uc.c Log message: Temporary hack to avoid Qemu crash at PowerPC reset time. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.35r2=1.36 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc405_uc.c?cvsroot=qemur1=1.13r2=1.14
[Qemu-devel] qemu/hw prep_pci.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/29 10:24:59 Modified files: hw : prep_pci.c Log message: Fix PreP PCI IRQ mapping. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/prep_pci.c?cvsroot=qemur1=1.6r2=1.7
[Qemu-devel] qemu/hw ppc_prep.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/29 10:21:12 Modified files: hw : ppc_prep.c Log message: Implement PreP reset port. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.49r2=1.50
[Qemu-devel] qemu/target-ppc op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/29 21:54:35 Modified files: target-ppc : op_helper.c Log message: Fix two PowerPC FPU emulation bugs (thanks to Aurelien Jarno) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.60r2=1.61
[Qemu-devel] qemu host-utils.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 12:52:39 Modified files: . : host-utils.h Log message: Add shared ctz32, cto32, ctz64, cto64, ctpop8, ctpop16, ctpop32 and ctpop64 helpers. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/host-utils.h?cvsroot=qemur1=1.1r2=1.2
[Qemu-devel] qemu target-alpha/op_helper.c target-ppc/op.c t...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 12:54:53 Modified files: target-alpha : op_helper.c target-ppc : op.c op_helper.c op_helper.h Log message: Make Alpha and PowerPC targets use shared helpers for clz, clo, ctz, cto and ctpop. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_helper.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.59r2=1.60 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.58r2=1.59 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.24r2=1.25
[Qemu-devel] qemu Makefile.target
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 13:07:13 Modified files: . : Makefile.target Log message: Use cpp to generate correct build dependencies for target objects instead of using incomplete hardcoded ones. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemur1=1.211r2=1.212
[Qemu-devel] qemu/hw m48t59.c m48t59.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 23:33:05 Modified files: hw : m48t59.c m48t59.h Log message: Give an opaque to the m48t59 direct access routines to make it easier to use another NVRAM with the same API. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.c?cvsroot=qemur1=1.15r2=1.16 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.h?cvsroot=qemur1=1.7r2=1.8
[Qemu-devel] qemu Makefile.target vl.h hw/cuda.c hw/grackle_...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 23:42:18 Modified files: . : Makefile.target vl.h hw : cuda.c grackle_pci.c heathrow_pic.c ppc.c ppc_chrp.c ppc_prep.c Added files: hw : mac_dbdma.c mac_nvram.c macio.c ppc_mac.h ppc_oldworld.c Log message: * sort the PowerPC target object files * make PowerPC NVRAM accessors generic to be able to use a MacIO NVRAM instead of the M48T59 one * split PowerMac targets code: - move all PowerMac related definitions and prototypes into hw/ppc_mac.h - add hw/mac_dbdma.c, hw/mac_nvram.c and macio.c which implements shared PowerMac devices - define the g3bw machine in a new hw/ppc_oldworld.c file * Fix the g3bw target: - fix the Grackle host PCI device - connect the Heathrow PIC to the PowerPC 6xx bus pins CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemur1=1.212r2=1.213 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.280r2=1.281 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/cuda.c?cvsroot=qemur1=1.16r2=1.17 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/grackle_pci.c?cvsroot=qemur1=1.6r2=1.7 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/heathrow_pic.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc.c?cvsroot=qemur1=1.34r2=1.35 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_chrp.c?cvsroot=qemur1=1.44r2=1.45 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.47r2=1.48 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mac_dbdma.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mac_nvram.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/macio.c?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_mac.h?cvsroot=qemurev=1.1 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_oldworld.c?cvsroot=qemurev=1.1
[Qemu-devel] qemu/target-ppc op_mem.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/27 17:18:49 Modified files: target-ppc : op_mem.h Log message: Fix endianness bug for PowerPC stfiwx instruction. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h?cvsroot=qemur1=1.22r2=1.23
[Qemu-devel] qemu/linux-user elfload.c main.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/27 17:29:35 Modified files: linux-user : elfload.c main.c Log message: PowerPC user-mode fix: MSR is now entirelly set-up in the cpu_reset routine. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/elfload.c?cvsroot=qemur1=1.53r2=1.54 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.136r2=1.137
[Qemu-devel] qemu/target-ppc op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/27 17:59:46 Modified files: target-ppc : op_helper.c Log message: PowerPC float bugfix: 64 bits float mantissa is 52 bits long. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.55r2=1.56
[Qemu-devel] qemu/target-ppc op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/27 23:34:30 Modified files: target-ppc : op_helper.c Log message: PowerPC floating-point helper typo. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.56r2=1.57
[Qemu-devel] qemu/target-ppc helper.c op_helper.c translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 00:55:05 Modified files: target-ppc : helper.c op_helper.c translate.c Log message: PowerPC coding style and inlining fixes. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.84r2=1.85 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.57r2=1.58 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.97r2=1.98
[Qemu-devel] qemu/target-alpha cpu.h exec.h op_helper.c op_m...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/28 00:56:24 Modified files: target-alpha : cpu.h exec.h op_helper.c op_mem.h translate.c Log message: Alpha coding style and inlining fixes. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/cpu.h?cvsroot=qemur1=1.9r2=1.10 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/exec.h?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_helper.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_mem.h?cvsroot=qemur1=1.2r2=1.3 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/translate.c?cvsroot=qemur1=1.6r2=1.7
[Qemu-devel] qemu gdbstub.c monitor.c linux-user/main.c targ...
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 21:35:50 Modified files: . : gdbstub.c monitor.c linux-user : main.c target-ppc : cpu.h exec.h helper.c op.c op_helper.c op_helper.h translate.c Added files: target-ppc : helper_regs.h Log message: Gprof prooved the PowerPC emulation spent too much time in MSR load and store routines. Coming back to a raw MSR storage model then speed-up the emulation. Improve fast MSR updates (wrtee wrteei and mtriee cases). Share rfi family instructions helpers code to avoid bug in duplicated code. Allow entering halt mode as the result of a rfi instruction. Add a new helper_regs.h file to avoid duplication of special registers manipulation routines (currently XER and MSR). CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemur1=1.67r2=1.68 http://cvs.savannah.gnu.org/viewcvs/qemu/monitor.c?cvsroot=qemur1=1.83r2=1.84 http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemur1=1.135r2=1.136 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.83r2=1.84 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemur1=1.29r2=1.30 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.80r2=1.81 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op.c?cvsroot=qemur1=1.56r2=1.57 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.51r2=1.52 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.h?cvsroot=qemur1=1.21r2=1.22 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.93r2=1.94 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemurev=1.1
[Qemu-devel] qemu/target-ppc helper_regs.h translate_init.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 23:14:51 Modified files: target-ppc : helper_regs.h translate_init.c Log message: Implement power-management for all defined PowerPC CPUs. Fix PowerPC 970MP definition. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper_regs.h?cvsroot=qemur1=1.1r2=1.2 http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate_init.c?cvsroot=qemur1=1.52r2=1.53
[Qemu-devel] qemu/target-ppc cpu.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 23:27:04 Modified files: target-ppc : cpu.h Log message: Add PowerPC power-management state check callback. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemur1=1.84r2=1.85
[Qemu-devel] qemu/target-alpha op.c op_helper.c op_helper.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 23:34:44 Modified files: target-alpha : op.c op_helper.c op_helper.h Log message: Use host-utils for Alpha 64x64 bits multiplications. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op.c?cvsroot=qemur1=1.3r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_helper.c?cvsroot=qemur1=1.4r2=1.5 http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_helper.h?cvsroot=qemur1=1.2r2=1.3
[Qemu-devel] qemu/target-ppc op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/25 23:36:08 Modified files: target-ppc : op_helper.c Log message: Fix PowerPC 64x64 bits multiplication overflow check. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemur1=1.53r2=1.54
[Qemu-devel] qemu/target-ppc helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/26 00:37:04 Modified files: target-ppc : helper.c Log message: Bugfix: PowerPC 64 slbia never invalidates the first segment entry. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemur1=1.81r2=1.82
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/26 00:46:07 Modified files: target-ppc : translate.c Log message: Pretty dump for specific PowerPC instructions names. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.94r2=1.95
[Qemu-devel] qemu/target-ppc translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/26 00:48:01 Modified files: target-ppc : translate.c Log message: Bugfix in PowerPC dcbi instruction: we must do a load before the store, or we'll store random data. Update cache instructions comments. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemur1=1.95r2=1.96
[Qemu-devel] qemu/target-ppc op_helper_mem.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/26 00:55:17 Modified files: target-ppc : op_helper_mem.h Log message: For consistency, align the address to the cache line before using it, when invalidating the instruction cache. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper_mem.h?cvsroot=qemur1=1.14r2=1.15
Re: [Qemu-devel] qemu host-utils.c
On Wed, 2007-10-24 at 18:37 +0100, Thiemo Seufer wrote: J. Mayer wrote: On Wed, 2007-10-24 at 12:20 +0200, Fabrice Bellard wrote: I strongly suggest to reuse my code which was in target-i386/helper.c revision 1.80 which was far easier to validate. Moreover, integer divisions from target-i386/helper.c should be put in the same file. I fully agree with this. I still use the same code in the PowerPC op_helper.c file because I never conviced myself that the host_utils version was bug-free. I would likely switch to the common version if I could be sure it cannot lead to any regression. Like this? Questions/Comments I have: - Is the BSD-style copyright still ok for this version? This I cannot tell. Fabrice should say how he feels about it. 1 detail: I just copied Fabrice code from i386 target, then I don't own any copyright on it... - The x86-64 assembler is untested for this version, could you check it works for you? I could check this, as I got an amd64 host. As the optimized version may lead to emit only one or a few host instructions, it may be great to have them be static inline to make gcc able to fully optimize the code. One other point: you may prefer not to change the host-utils API to avoid changes i386 and Mips. It may also be safer, to keep the x86_64 optimized code unchanged. I don't care about the argument order, I can adapt and optimize the code in the PowerPC target for this later. - SPARC and Alpha look like they will break on 32bit hosts, they should do multiplications the same way as the other 64bit targets. I don't think Alpha would not work on 32 bits hosts but I fully agree it should use the same helpers. Especially because it's obvious that umulh is bugged ! -- Jocelyn Mayer [EMAIL PROTECTED]
Re: [Qemu-devel] PreP kernels boot using Qemu
On Mon, 2007-10-22 at 09:36 +0200, J. Mayer wrote: Hi all, I've been investigating more about PreP kernel boot using Qemu and I achieved to boot 2.4.35, 2.6.12 and 2.6.22 kernels using Qemu CVS and unmodified OHW. The issues I found in the kernel are: - the OpenFirmware video console driver is broken in recent 2.4 kernels and have been removed from recent 2.6 kernel - I then decided to use the vga16fb console driver but needed to do some patches in order to make it compile properly - the CMOS RTC driver is not available for PPC architecture in 2.6 kernels and need some patches in order to be usable - I discovered that the mkprep utility is bugged in 2.4.35 and 2.6.12 kernels. The bugs are visible only when cross-compiling from a little-endian and/or 64 bits host. - I got issues (ie process freezing) when using the 2.6.22 kernel with HZ 100. It seems to run properly when the system timer is set to 100 Hz but this needs more tests for confirmation. - I got the 2.6.22 kernel crashing (ie kernel Oops in workqueue code) when it has no RTC available. There is no problem when the RTC is present. This is likely to be a kernel bug: when no RTC is available, it cannot calibrate its timers properly and the kernel timer seems to run very fast. Forcing (with hacks...) the timer to run at nearly real-time seems to prevent the bug to happen. I then generated some kernels that allow me to boot and use those 3 kernels. Here are 3 tarballs with: - a patch to be applied to the vanilla kernel sources to fix the mentionned bugs - the .config file I used to build the kernel - the zImage.prep image http://perso.magic.fr/l_indien/qemu-ppc/linux-tests/linux-2.4.35-prep.tar.bz2 http://perso.magic.fr/l_indien/qemu-ppc/linux-tests/linux-2.6.12-prep.tar.bz2 http://perso.magic.fr/l_indien/qemu-ppc/linux-tests/linux-2.6.22-prep.tar.bz2 I then run Qemu with the following command line template: ./ppc-softmmu/qemu-system-ppc -serial stdio -net nic,model=ne2k_isa -net tap -net nic,model=ne2k_pci -net tap -net nic,model=rtl8139 -net tap -cpu 604 -M prep -L pc-bios/ -hda my_first_disk -cdrom my_cdrom -kernel src_base/linux-kversion.patched/arch/ppc/boot/images/zImage.prep Hope this helps. Two points I forgot: - there is no way to make Qemu stop when the PreP kernel displays Power down because the prep_halt routine just does an infinite loop. - the board reset would not work with the current code. I will fix this soon. -- Jocelyn Mayer [EMAIL PROTECTED]
[Qemu-devel] qemu/target-alpha STATUS
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/21 09:46:04 Added files: target-alpha : STATUS Log message: New status file for Alpha emulation target. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/STATUS?cvsroot=qemurev=1.1
[Qemu-devel] qemu/hw ppc_prep.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/21 12:29:36 Modified files: hw : ppc_prep.c Log message: Allow use of PCI NICs on PowerPC PreP platform. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.45r2=1.46
[Qemu-devel] qemu/hw ppc_prep.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/21 15:53:01 Modified files: hw : ppc_prep.c Log message: Bugfix: now PCI NICs really work on PowerPC PreP platform. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/ppc_prep.c?cvsroot=qemur1=1.46r2=1.47
[Qemu-devel] qemu/hw i8259.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Jocelyn Mayer j_mayer 07/10/20 09:13:55 Modified files: hw : i8259.c Log message: Avoid PreP target kernel freeze waiting for IRQs. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/i8259.c?cvsroot=qemur1=1.25r2=1.26
