Re: [Qemu-devel] question: guest will hang when call system function in migration thread.

[Li Guang]

Hi,

which version you tested?
do you let vm continue to run after migration?
can you provide more info?

can't reproduce it on latest version.


Thanks!

On 12/04/2014 11:14 PM, 陈梁 wrote:
> Hi all
>
> guest will hang when call system function in migration thread. The cpu usage 
> of vcpu thread is 100%.
>
> the code like this:
>
> static void *migration_thread(void *opaque)
> {
> MigrationState *s = opaque;
> int64_t initial_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
> int64_t setup_start = qemu_clock_get_ms(QEMU_CLOCK_HOST);
> int64_t initial_bytes = 0;
> int64_t max_size = 0;
> int64_t start_time = initial_time;
> bool old_vm_running = false;
>
> //test code
> system("df -h”);
>
> qemu_savevm_state_begin(s->file, &s->params);
> …
>
> Is it anything wrong?  or it is not allow to call system in migration thread?
>  
>

[Qemu-devel] 答复: [PATCH] vnc: add additional key up event before repeated key down

[Li, Guang]

> -邮件原件-
> 发件人: qemu-devel-bounces+lig.fnst=cn.fujitsu@nongnu.org
> [mailto:qemu-devel-bounces+lig.fnst=cn.fujitsu@nongnu.org] 代表 Peter
> Maydell
> 发送时间: 2014年9月18日 0:09
> 收件人: Gerd Hoffmann
> 抄送: Stefano Stabellini; Markus Armbruster; qemu-devel;
> xen-de...@lists.xen.org; Anthony Liguori; Chun Yan Liu
> 主题: Re: [Qemu-devel] [PATCH] vnc: add additional key up event before
> repeated key down
> 
> On 17 September 2014 04:24, Gerd Hoffmann  wrote:
> >> Which brings us to the other half of this: what does our UI layer
> >> specify should be the behaviour for key repeat?
> >> Gerd, can you clarify what the common input layer's expectation is
> >> here? Should UI front ends call qemu_input_event_send_key() with
> >> 'down/down/down/up' or 'down/up/down/up' semantics?
> >
> > It isn't formally specified anywhere.  The UIs usually simply pass
> > through the key events they get.  IMO it is more useful to go for
> > down/down/down/up.  This is how PS/2 works, and this allows the guest
> > to figure whenever it's autorepeat or really multiple key presses.
> 
> Makes sense. It would be nice to have a comment somewhere (include file near
> the prototype for the 'deliver key event'
> function?) saying this is the required key-repeat behaviour.
> 
> I wouldn't be totally surprised if some of our UIs weren't getting this 
> right, but
> I'm not sure I care enough to audit them all :-)
> 
> Anyway, I think this reinforces Markus's conclusion that TigerVNC is correct
> and our VNC server implementation is correct and the bug is in whichever PV
> guest is not handling the key-repeat info it gets out of PS/2. (At least I 
> assume
> that the Xen config in question is going to send key events via emulated 
> PS/2; if
> it's something else I guess that something else could potentially be buggy.)

Confirmed, we surely do right things now to collect make,break keycode and 
handle repeat case,
But, seems forgot to handle typematic.

Thanks!

Re: [Qemu-devel] [PATCH v3 3/7] allwinner-a10-pit: avoid generation of spurious interrupts

[Li Guang]

在 2014-03-15六的 14:01 +0100，Beniamino Galvani写道：
> The model was generating interrupts for all enabled timers after the
> expiration of one of them. Avoid this by passing explicitly the timer
> index to the callback function.
> 
> Signed-off-by: Beniamino Galvani 

Reviewed-by: Li Guang 

> ---
>  hw/timer/allwinner-a10-pit.c |   25 ++---
>  include/hw/timer/allwinner-a10-pit.h |8 
>  2 files changed, 22 insertions(+), 11 deletions(-)
> 
> diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
> index b27fce8..696b7d9 100644
> --- a/hw/timer/allwinner-a10-pit.c
> +++ b/hw/timer/allwinner-a10-pit.c
> @@ -193,18 +193,17 @@ static void a10_pit_reset(DeviceState *dev)
>  
>  static void a10_pit_timer_cb(void *opaque)
>  {
> -AwA10PITState *s = AW_A10_PIT(opaque);
> -uint8_t i;
> +AwA10TimerContext *tc = opaque;
> +AwA10PITState *s = tc->container;
> +uint8_t i = tc->index;
>  
> -for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
> -if (s->control[i] & AW_A10_PIT_TIMER_EN) {
> -s->irq_status |= 1 << i;
> -if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
> -ptimer_stop(s->timer[i]);
> -s->control[i] &= ~AW_A10_PIT_TIMER_EN;
> -}
> -qemu_irq_pulse(s->irq[i]);
> +if (s->control[i] & AW_A10_PIT_TIMER_EN) {
> +s->irq_status |= 1 << i;
> +if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
> +ptimer_stop(s->timer[i]);
> +s->control[i] &= ~AW_A10_PIT_TIMER_EN;
>  }
> +qemu_irq_pulse(s->irq[i]);
>  }
>  }
>  
> @@ -223,7 +222,11 @@ static void a10_pit_init(Object *obj)
>  sysbus_init_mmio(sbd, &s->iomem);
>  
>  for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
> -bh[i] = qemu_bh_new(a10_pit_timer_cb, s);
> +AwA10TimerContext *tc = &s->timer_context[i];
> +
> +tc->container = s;
> +tc->index = i;
> +bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
>  s->timer[i] = ptimer_init(bh[i]);
>  ptimer_set_freq(s->timer[i], 24);
>  }
> diff --git a/include/hw/timer/allwinner-a10-pit.h 
> b/include/hw/timer/allwinner-a10-pit.h
> index 15efab8..a48d3c7 100644
> --- a/include/hw/timer/allwinner-a10-pit.h
> +++ b/include/hw/timer/allwinner-a10-pit.h
> @@ -35,12 +35,20 @@
>  
>  #define AW_A10_PIT_DEFAULT_CLOCK   0x4
>  
> +typedef struct AwA10PITState AwA10PITState;
> +
> +typedef struct AwA10TimerContext {
> +AwA10PITState *container;
> +int index;
> +} AwA10TimerContext;
> +
>  typedef struct AwA10PITState {
>  /*< private >*/
>  SysBusDevice parent_obj;
>  /*< public >*/
>  qemu_irq irq[AW_A10_PIT_TIMER_NR];
>  ptimer_state * timer[AW_A10_PIT_TIMER_NR];
> +AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
>  MemoryRegion iomem;
>  
>  uint32_t irq_enable;

Re: [Qemu-devel] [PATCH v3 5/7] allwinner-a10-pit: implement prescaler and source selection

[Li Guang]

在 2014-03-15六的 14:01 +0100，Beniamino Galvani写道：
> This implements the prescaler and source fields of the timer control
> register as described in the A10 user manual.
> 
> Signed-off-by: Beniamino Galvani 

Reviewed-by: Li Guang 

> ---
>  hw/timer/allwinner-a10-pit.c |   30 +-
>  include/hw/timer/allwinner-a10-pit.h |8 
>  2 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
> index f8c9236..a448689 100644
> --- a/hw/timer/allwinner-a10-pit.c
> +++ b/hw/timer/allwinner-a10-pit.c
> @@ -74,6 +74,34 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, 
> unsigned size)
>  return 0;
>  }
>  
> +static void a10_pit_set_freq(AwA10PITState *s, int index)
> +{
> +uint32_t prescaler, source;
> +uint32_t source_freq = AW_A10_PIT_OSC24M_FREQ;
> +
> +prescaler = 1 << extract32(s->control[index], 4, 3);
> +source = extract32(s->control[index], 2, 2);
> +
> +switch (source) {
> +case AW_A10_PIT_SOURCE_LS_OSC:
> +source_freq = AW_A10_PIT_LS_OSC_FREQ;
> +break;
> +case AW_A10_PIT_SOURCE_OSC24M:
> +source_freq = AW_A10_PIT_OSC24M_FREQ;
> +break;
> +case AW_A10_PIT_SOURCE_PLL6:
> +qemu_log_mask(LOG_UNIMP, "%s: unimplemented clock source %u", 
> __func__,
> +  source);
> +break;
> +case AW_A10_PIT_SOURCE_UNDEF:
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid clock source %u", 
> __func__,
> +  source);
> +break;
> +}
> +
> +ptimer_set_freq(s->timer[index], source_freq / prescaler);
> +}
> +
>  static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
>  unsigned size)
>  {
> @@ -96,6 +124,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, 
> uint64_t value,
>  switch (offset & 0x0f) {
>  case AW_A10_PIT_TIMER_CONTROL:
>  s->control[index] = value;
> +a10_pit_set_freq(s, index);
>  if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
>  ptimer_set_count(s->timer[index], s->interval[index]);
>  }
> @@ -239,7 +268,6 @@ static void a10_pit_init(Object *obj)
>  tc->index = i;
>  bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
>  s->timer[i] = ptimer_init(bh[i]);
> -ptimer_set_freq(s->timer[i], 24);
>  }
>  }
>  
> diff --git a/include/hw/timer/allwinner-a10-pit.h 
> b/include/hw/timer/allwinner-a10-pit.h
> index a48d3c7..37a2662 100644
> --- a/include/hw/timer/allwinner-a10-pit.h
> +++ b/include/hw/timer/allwinner-a10-pit.h
> @@ -33,6 +33,14 @@
>  #define AW_A10_PIT_TIMER_BASE_END  \
>  (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
>  
> +#define AW_A10_PIT_SOURCE_LS_OSC   0
> +#define AW_A10_PIT_SOURCE_OSC24M   1
> +#define AW_A10_PIT_SOURCE_PLL6 2
> +#define AW_A10_PIT_SOURCE_UNDEF3
> +
> +#define AW_A10_PIT_LS_OSC_FREQ 32768
> +#define AW_A10_PIT_OSC24M_FREQ 2400
> +
>  #define AW_A10_PIT_DEFAULT_CLOCK   0x4
>  
>  typedef struct AwA10PITState AwA10PITState;

Re: [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending

[Li Guang]

在 2014-03-15六的 14:01 +0100，Beniamino Galvani写道：
> This patch implements proper updating of the vector register which
> should hold, according to the A10 user manual, the vector address for
> the interrupt currently active on the CPU IRQ input.
> 
> Interrupt priority is not implemented at the moment and thus the first
> pending interrupt is returned.
> 
> Signed-off-by: Beniamino Galvani 
> Reviewed-by: Peter Crosthwaite 

Reviewed-by: Li Guang 

> ---
>  hw/intc/allwinner-a10-pic.c |   14 ++
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> index 407d563..00f3c11 100644
> --- a/hw/intc/allwinner-a10-pic.c
> +++ b/hw/intc/allwinner-a10-pic.c
> @@ -23,11 +23,20 @@
>  static void aw_a10_pic_update(AwA10PICState *s)
>  {
>  uint8_t i;
> -int irq = 0, fiq = 0;
> +int irq = 0, fiq = 0, pending;
> +
> +s->vector = 0;
>  
>  for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
>  irq |= s->irq_pending[i] & ~s->mask[i];
>  fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
> +
> +if (!s->vector) {
> +pending = ffs(s->irq_pending[i] & ~s->mask[i]);
> +if (pending) {
> +s->vector = (i * 32 + pending - 1) * 4;
> +}
> +}
>  }
>  
>  qemu_set_irq(s->parent_irq, !!irq);
> @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, 
> uint64_t value,
>  uint8_t index = (offset & 0xc) / 4;
>  
>  switch (offset) {
> -case AW_A10_PIC_VECTOR:
> -s->vector = value & ~0x3;
> -break;
>  case AW_A10_PIC_BASE_ADDR:
>  s->base_addr = value & ~0x3;
>  case AW_A10_PIC_PROTECT:

Re: [Qemu-devel] [PATCH v3 2/7] allwinner-a10-pic: fix behaviour of pending register

[Li Guang]

在 2014-03-15六的 14:01 +0100，Beniamino Galvani写道：
> The pending register is read-only and the value returned upon a read
> reflects the state of irq input pins (interrupts are level triggered).
> This patch implements such behaviour.
> 
> Signed-off-by: Beniamino Galvani 

Reviewed-by: Li Guang 

> ---
>  hw/intc/allwinner-a10-pic.c |8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> index 00f3c11..0924d98 100644
> --- a/hw/intc/allwinner-a10-pic.c
> +++ b/hw/intc/allwinner-a10-pic.c
> @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int 
> level)
>  
>  if (level) {
>  set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
> +} else {
> +clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
>  }
>  aw_a10_pic_update(s);
>  }
> @@ -102,7 +104,11 @@ static void aw_a10_pic_write(void *opaque, hwaddr 
> offset, uint64_t value,
>  s->nmi = value;
>  break;
>  case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
> -s->irq_pending[index] &= ~value;
> +/*
> + * The register is read-only; nevertheless, Linux (including
> + * the version originally shipped by Allwinner) pretends to
> + * write to the register. Just ignore it.
> + */
>  break;
>  case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
>  s->fiq_pending[index] &= ~value;

Re: [Qemu-devel] [RFC PATCH v2 06/12] mc: introduce state machine changes for MC

[Li Guang]

Li Guang wrote:

Michael R. Hines wrote:

On 02/19/2014 09:00 AM, Li Guang wrote:

Hi,

mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

This patch sets up the initial changes to the migration state
machine and prototypes to be used by the checkpointing code
to interact with the state machine so that we can later handle
failure and recovery scenarios.

Signed-off-by: Michael R. Hines
---
  arch_init.c   | 29 -
  include/migration/migration.h |  2 ++
  migration.c   | 37 
+

  3 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/arch_init.c b/arch_init.c
index db75120..e9d4d9e 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -658,13 +658,13 @@ static void ram_migration_cancel(void *opaque)
  migration_end();
  }

-static void reset_ram_globals(void)
+static void reset_ram_globals(bool reset_bulk_stage)
  {
  last_seen_block = NULL;
  last_sent_block = NULL;
  last_offset = 0;
  last_version = ram_list.version;
-ram_bulk_stage = true;
+ram_bulk_stage = reset_bulk_stage;
  }



here is a chance that ram_save_block will never break while loop
if loat_seen_block be reset for mc when there are no dirty pages
to be migrated.

Thanks!



This bug is fixed now - you can re-pull from github.com.

Believe it or not, when there is no network devices attached to the
guest whatsoever, the initial bootup process can be extremely slow,
where there are almost no processes dirtying memory at all or
only occasionally except for maybe a DHCP client. This results in
some 100ms periods of time where there are actually *no* dirty
pages - hard to believe, but it does happen.


sorry, seems all my pull requests for github was blocked,
let me check it later.

Thanks!



tested, works well for me.

Thanks!



ram_save_block() really doesn't understand this possibility,
surprisingly. It results in an infinite loop because it was 
expecting

last_seen_block to always be non-NULL, when in fact, we have reset
the value to start from the beginning of the guest can scan the
entire VM for dirty memory.



  #define MAX_WAIT 50 /* ms, half buffered_file limit */
@@ -674,6 +674,15 @@ static int ram_save_setup(QEMUFile *f, void 
*opaque)

  RAMBlock *block;
  int64_t ram_pages = last_ram_offset()>> TARGET_PAGE_BITS;

+/*
+ * RAM stays open during micro-checkpointing for the next 
transaction.

+ */
+if (migration_is_mc(migrate_get_current())) {
+qemu_mutex_lock_ramlist();
+reset_ram_globals(false);
+goto skip_setup;
+}
+
  migration_bitmap = bitmap_new(ram_pages);
  bitmap_set(migration_bitmap, 0, ram_pages);
  migration_dirty_pages = ram_pages;
@@ -710,12 +719,14 @@ static int ram_save_setup(QEMUFile *f, void 
*opaque)

  qemu_mutex_lock_iothread();
  qemu_mutex_lock_ramlist();
  bytes_transferred = 0;
-reset_ram_globals();
+reset_ram_globals(true);

  memory_global_dirty_log_start();
  migration_bitmap_sync();
  qemu_mutex_unlock_iothread();

+skip_setup:
+
  qemu_put_be64(f, ram_bytes_total() | RAM_SAVE_FLAG_MEM_SIZE);

  QTAILQ_FOREACH(block,&ram_list.blocks, next) {
@@ -744,7 +755,7 @@ static int ram_save_iterate(QEMUFile *f, void 
*opaque)

  qemu_mutex_lock_ramlist();

  if (ram_list.version != last_version) {
-reset_ram_globals();
+reset_ram_globals(true);
  }

  ram_control_before_iterate(f, RAM_CONTROL_ROUND);
@@ -825,7 +836,15 @@ static int ram_save_complete(QEMUFile *f, void 
*opaque)

  }

  ram_control_after_iterate(f, RAM_CONTROL_FINISH);
-migration_end();
+
+/*
+ * Only cleanup at the end of normal migrations
+ * or if the MC destination failed and we got an error.
+ * Otherwise, we are (or will soon be) in 
MIG_STATE_CHECKPOINTING.

+ */
+if(!migrate_use_mc() || 
migration_has_failed(migrate_get_current())) {

+migration_end();
+}

  qemu_mutex_unlock_ramlist();
  qemu_put_be64(f, RAM_SAVE_FLAG_EOS);
diff --git a/include/migration/migration.h 
b/include/migration/migration.h

index a7c54fe..e876a2c 100644
--- a/include/migration/migration.h
+++ b/include/migration/migration.h
@@ -101,7 +101,9 @@ int migrate_fd_close(MigrationState *s);

  void add_migration_state_change_notifier(Notifier *notify);
  void remove_migration_state_change_notifier(Notifier *notify);
+bool migration_is_active(MigrationState *);
  bool migration_in_setup(MigrationState *);
+bool migration_is_mc(MigrationState *s);
  bool migration_has_finished(MigrationState *);
  bool migration_has_failed(MigrationState *);
  MigrationState *migrate_get_current(void);
diff --git a/migration.c b/migration.c
index 25add6f..f42dae4 100644
--- a/migration.c
+++ b/migration.c
@@ -36,16 +36,6 @@
  do { } while (0)
  #endif

-enum {
-MIG_STATE_ERROR 

Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour

[Li Guang]

Beniamino Galvani wrote:

On Mon, Feb 24, 2014 at 02:45:06PM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

On Wed, Feb 19, 2014 at 10:02:36AM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

According to this mail thread [1], writing to pending register seems
to have no effect on actual pending status of interrupts. This means
that the only way to clear a pending interrupt is to clear the
interrupt source. This patch implements such behaviour.

[1] http://lkml.org/lkml/2013/7/6/59

Signed-off-by: Beniamino Galvani
---
  hw/intc/allwinner-a10-pic.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index bb2351f..afd57ef 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int 
level)

  if (level) {
  set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
+} else {
+clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  }
  aw_a10_pic_update(s);
  }
@@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, 
uint64_t value,
  s->nmi = value;
  break;
  case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
-s->irq_pending[index]&= ~value;
+/* Nothing to do */
  break;
  case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
-s->fiq_pending[index]&= ~value;
+/* Ditto */
  break;
  case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  s->select[index] = value;
   

pending registers are also clear registers by a10 datasheet,
also you found bits are marked as 'R', so, ..., contradict itself.
 

Yes, the datasheet is inconsistent about this because the register
can't be read-only and 'clear' at the same time.

Unfortunately at the moment I cannot test if the clearing
functionality of the pending register works on real hardware but the
idea I got from the linked discussion is that it's either not
implemented or broken and therefore interrupts remain pending until
they are disabled at the source.

Do you have a chance to try it on a real board?

   

Ah? even kernel code from allwinner wrote pending registers
to clear pending interrupt, didn't you see it?
so should be no doubt that these registers are writable.
 

Well, if you look closely at that code, it's a bit strange:

void sw_irq_ack(struct irq_data *irqd)
{
 unsigned int irq = irqd->irq;

 [...]
 writel(readl(SW_INT_IRQ_PENDING_REG0) | (1<   

Hmm..., sorry,  I also can't test this operation on A10 board now,
but why not they just wipe out these writings(kernel 3.12)?
 

I don't know, there was a proposed patch that removed those writes in
the lkml discussion but probably it never reached mainline.

To be on the safe side I can restore the writability of the register
and then, when we will figure out how it really works, correct it if
needed.


   


Agreed,

Thanks!

Re: [Qemu-devel] [RFC PATCH v2 06/12] mc: introduce state machine changes for MC

[Li Guang]

Michael R. Hines wrote:

On 02/19/2014 09:00 AM, Li Guang wrote:

Hi,

mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

This patch sets up the initial changes to the migration state
machine and prototypes to be used by the checkpointing code
to interact with the state machine so that we can later handle
failure and recovery scenarios.

Signed-off-by: Michael R. Hines
---
  arch_init.c   | 29 -
  include/migration/migration.h |  2 ++
  migration.c   | 37 
+

  3 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/arch_init.c b/arch_init.c
index db75120..e9d4d9e 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -658,13 +658,13 @@ static void ram_migration_cancel(void *opaque)
  migration_end();
  }

-static void reset_ram_globals(void)
+static void reset_ram_globals(bool reset_bulk_stage)
  {
  last_seen_block = NULL;
  last_sent_block = NULL;
  last_offset = 0;
  last_version = ram_list.version;
-ram_bulk_stage = true;
+ram_bulk_stage = reset_bulk_stage;
  }



here is a chance that ram_save_block will never break while loop
if loat_seen_block be reset for mc when there are no dirty pages
to be migrated.

Thanks!



This bug is fixed now - you can re-pull from github.com.

Believe it or not, when there is no network devices attached to the
guest whatsoever, the initial bootup process can be extremely slow,
where there are almost no processes dirtying memory at all or
only occasionally except for maybe a DHCP client. This results in
some 100ms periods of time where there are actually *no* dirty
pages - hard to believe, but it does happen.


sorry, seems all my pull requests for github was blocked,
let me check it later.

Thanks!



ram_save_block() really doesn't understand this possibility,
surprisingly. It results in an infinite loop because it was expecting
last_seen_block to always be non-NULL, when in fact, we have reset
the value to start from the beginning of the guest can scan the
entire VM for dirty memory.



  #define MAX_WAIT 50 /* ms, half buffered_file limit */
@@ -674,6 +674,15 @@ static int ram_save_setup(QEMUFile *f, void 
*opaque)

  RAMBlock *block;
  int64_t ram_pages = last_ram_offset()>> TARGET_PAGE_BITS;

+/*
+ * RAM stays open during micro-checkpointing for the next 
transaction.

+ */
+if (migration_is_mc(migrate_get_current())) {
+qemu_mutex_lock_ramlist();
+reset_ram_globals(false);
+goto skip_setup;
+}
+
  migration_bitmap = bitmap_new(ram_pages);
  bitmap_set(migration_bitmap, 0, ram_pages);
  migration_dirty_pages = ram_pages;
@@ -710,12 +719,14 @@ static int ram_save_setup(QEMUFile *f, void 
*opaque)

  qemu_mutex_lock_iothread();
  qemu_mutex_lock_ramlist();
  bytes_transferred = 0;
-reset_ram_globals();
+reset_ram_globals(true);

  memory_global_dirty_log_start();
  migration_bitmap_sync();
  qemu_mutex_unlock_iothread();

+skip_setup:
+
  qemu_put_be64(f, ram_bytes_total() | RAM_SAVE_FLAG_MEM_SIZE);

  QTAILQ_FOREACH(block,&ram_list.blocks, next) {
@@ -744,7 +755,7 @@ static int ram_save_iterate(QEMUFile *f, void 
*opaque)

  qemu_mutex_lock_ramlist();

  if (ram_list.version != last_version) {
-reset_ram_globals();
+reset_ram_globals(true);
  }

  ram_control_before_iterate(f, RAM_CONTROL_ROUND);
@@ -825,7 +836,15 @@ static int ram_save_complete(QEMUFile *f, void 
*opaque)

  }

  ram_control_after_iterate(f, RAM_CONTROL_FINISH);
-migration_end();
+
+/*
+ * Only cleanup at the end of normal migrations
+ * or if the MC destination failed and we got an error.
+ * Otherwise, we are (or will soon be) in MIG_STATE_CHECKPOINTING.
+ */
+if(!migrate_use_mc() || 
migration_has_failed(migrate_get_current())) {

+migration_end();
+}

  qemu_mutex_unlock_ramlist();
  qemu_put_be64(f, RAM_SAVE_FLAG_EOS);
diff --git a/include/migration/migration.h 
b/include/migration/migration.h

index a7c54fe..e876a2c 100644
--- a/include/migration/migration.h
+++ b/include/migration/migration.h
@@ -101,7 +101,9 @@ int migrate_fd_close(MigrationState *s);

  void add_migration_state_change_notifier(Notifier *notify);
  void remove_migration_state_change_notifier(Notifier *notify);
+bool migration_is_active(MigrationState *);
  bool migration_in_setup(MigrationState *);
+bool migration_is_mc(MigrationState *s);
  bool migration_has_finished(MigrationState *);
  bool migration_has_failed(MigrationState *);
  MigrationState *migrate_get_current(void);
diff --git a/migration.c b/migration.c
index 25add6f..f42dae4 100644
--- a/migration.c
+++ b/migration.c
@@ -36,16 +36,6 @@
  do { } while (0)
  #endif

-enum {
-MIG_STATE_ERROR = -1,
-MIG_STATE_NONE,
-MIG_STATE_SETUP,

Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour

[Li Guang]

Beniamino Galvani wrote:

On Wed, Feb 19, 2014 at 10:02:36AM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

According to this mail thread [1], writing to pending register seems
to have no effect on actual pending status of interrupts. This means
that the only way to clear a pending interrupt is to clear the
interrupt source. This patch implements such behaviour.

[1] http://lkml.org/lkml/2013/7/6/59

Signed-off-by: Beniamino Galvani
---
  hw/intc/allwinner-a10-pic.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index bb2351f..afd57ef 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int 
level)

  if (level) {
  set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
+} else {
+clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  }
  aw_a10_pic_update(s);
  }
@@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, 
uint64_t value,
  s->nmi = value;
  break;
  case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
-s->irq_pending[index]&= ~value;
+/* Nothing to do */
  break;
  case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
-s->fiq_pending[index]&= ~value;
+/* Ditto */
  break;
  case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  s->select[index] = value;
   

pending registers are also clear registers by a10 datasheet,
also you found bits are marked as 'R', so, ..., contradict itself.
 

Yes, the datasheet is inconsistent about this because the register
can't be read-only and 'clear' at the same time.

Unfortunately at the moment I cannot test if the clearing
functionality of the pending register works on real hardware but the
idea I got from the linked discussion is that it's either not
implemented or broken and therefore interrupts remain pending until
they are disabled at the source.

Do you have a chance to try it on a real board?

   

Ah? even kernel code from allwinner wrote pending registers
to clear pending interrupt, didn't you see it?
so should be no doubt that these registers are writable.
 

Well, if you look closely at that code, it's a bit strange:

void sw_irq_ack(struct irq_data *irqd)
{
 unsigned int irq = irqd->irq;

 [...]
 writel(readl(SW_INT_IRQ_PENDING_REG0) | (1<   


Hmm..., sorry,  I also can't test this operation on A10 board now,
but why not they just wipe out these writings(kernel 3.12)?

Re: [Qemu-devel] [RFC PATCH v2 01/12] mc: add documentation for micro-checkpointing

[Li Guang]

Dr. David Alan Gilbert wrote:

* Michael R. Hines (mrhi...@linux.vnet.ibm.com) wrote:
   

On 02/19/2014 07:27 PM, Dr. David Alan Gilbert wrote:
 

I was just wondering if a separate 'max buffer size' knob would allow
you to more reasonably bound memory without setting policy; I don't think
people like having potentially x2 memory.
   

Note: Checkpoint memory is not monotonic in this patchset (which
is unique to this implementation). Only if the guest actually dirties
100% of it's memory between one checkpoint to the next will
the host experience 2x memory usage for a short period of time.
 

Right, but that doesn't really help - if someone comes along and says
'How much memory do I need to be able to run an mc system?' the only
safe answer is 2x, otherwise we're adding a reason why the previously
stable guest might OOM.

   


so we may have to involve some disk operations
to handle memory exhaustion.

Thanks!


The patch has a 'slab' mechanism built in to it which implements
a water-mark style policy that throws away unused portions of
the 2x checkpoint memory if later checkpoints are much smaller
(which is likely to be the case if the writable working set size changes).

However, to answer your question: Such a knob could be achieved, but
the same could be achieved simply by tuning the checkpoint frequency
itself. Memory usage would thus be a function of the checkpoint frequency.
 
   

If the guest application was maniacal, banging away at all the memory,
there's very little that can be done in the first place, but if the
guest application
was mildly busy, you don't want to throw away your ability to be fault
tolerant - you would just need more frequent checkpoints to keep up with
the dirty rate.
 

I'm not convinced; I can tune my checkpoint frequency until normal operation
makes a reasonable trade off between mc frequency and RAM usage,
but that doesn't prevent it running away when a garbage collect or some
other thing suddenly dirties a load of ram in one particular checkpoint.
Some management tool that watches ram usage etc can also help tune
it, but in the end it can't stop it taking loads of RAM.

   

Once the application died down - the water-mark policy would kick in
and start freeing checkpoint memory. (Note: this policy happens on
both sides in the patchset because the patch has to be fully compatible
with RDMA memory pinning).

What is *not* exposed, however, is the watermark knobs themselves,
I definitely think that needs to be exposed - that would also get
you a similar
control to 'max buffer size' - you could place a time limit on the
slab list in the patch or something like that...


 

Good question in general - I'll add it to the FAQ. The patch implements
a basic 'transaction' mechanism in coordination with an outbound I/O
buffer (documented further down). With these two things in
places, split-brain is not possible because the destination is not running.
We don't allow the destination to resume execution until a committed
transaction has been acknowledged by the destination and only until
then do we allow any outbound network traffic to be release to the
outside world.
 

Yeh I see the IO buffer, what I've not figured out is how:
   1) MC over TCP/IP gets an acknowledge on the source to know when
  it can unplug it's buffer.
   

Only partially correct (See the steps on the wiki). There are two I/O
buffers at any given time which protect against a split-brain scenario:
One buffer for the current checkpoint that is being generated (running VM)
and one buffer for the checkpoint that is being committed in a transaction.

 

   2) Lets say the MC connection fails, so that ack never arrives,
  the source must assume the destination has failed and release it's
  packets and carry on.
   

Only the packets for Buffer A are released for the current committed
checkpoint after a completed transaction. The packets for Buffer B
(the current running VM) are still being held up until the next
transaction starts.
Later once the transaction completes and A is released, B becomes the
new A and a new buffer is installed to become the new Buffer B for
the current running VM.


 

  The destination must assume the source has failed and take over.
   

The destination must also receive an ACK. The ack goes both ways.

Once the source and destination both acknowledge a completed
transation does the source VM resume execution - and even then
it's packets are still being buffered until the next transaction starts.
(That's why it's important to checkpoint as frequently as possible).
 

I think I understand normal operation - my question here is about failure;
what happens when neither side gets any ACKs.

   

   3) If we're relying on TCP/IP timeout that's quite long.

   

Actually, my experience is been that TCP seems to have more than
one kind of timeout - if receiver is not responding *at all* - it seems that
TCP has a ded

Re: [Qemu-devel] [RFC PATCH v2 08/12] mc: core logic

[Li Guang]

Michael R. Hines wrote:

On 02/19/2014 09:07 AM, Li Guang wrote:

Hi,
mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

This implements the core logic,
all described in the first patch (docs/mc.txt).

Signed-off-by: Michael R. Hines
---
  migration-checkpoint.c | 1565 


  1 file changed, 1565 insertions(+)
  create mode 100644 migration-checkpoint.c



[big snip] ...


+
+/*
+ * Stop the VM, generate the micro checkpoint,
+ * but save the dirty memory into staging memory until
+ * we can re-activate the VM as soon as possible.
+ */
+static int capture_checkpoint(MCParams *mc, MigrationState *s)
+{
+MCCopyset *copyset;
+int idx, ret = 0;
+uint64_t start, stop, copies = 0;
+int64_t start_time;
+
+mc->total_copies = 0;
+qemu_mutex_lock_iothread();
+vm_stop_force_state(RUN_STATE_CHECKPOINT_VM);
+start = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+
+/*
+ * If buffering is enabled, insert a Qdisc plug here
+ * to hold packets for the *next* MC, (not this one,
+ * the packets for this one have already been plugged
+ * and will be released after the MC has been transmitted.
+ */
+mc_start_buffer();


actually, I have a special request,
if QEMU started without netdev,
then don't bother me by Qdisc for network buffering. :-)

Thanks!



That ability is already available in the patchset.
It is called "mc-net-disable" capability. (See the wiki or docs/mc.txt).

Did you try it?



I don't mean disable it manually, I say even don't start buffering
for network when no netdev.

Thanks!

Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour

[Li Guang]

Beniamino Galvani wrote:

On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

According to this mail thread [1], writing to pending register seems
to have no effect on actual pending status of interrupts. This means
that the only way to clear a pending interrupt is to clear the
interrupt source. This patch implements such behaviour.

[1] http://lkml.org/lkml/2013/7/6/59

Signed-off-by: Beniamino Galvani
---
  hw/intc/allwinner-a10-pic.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index bb2351f..afd57ef 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int 
level)

  if (level) {
  set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
+} else {
+clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  }
  aw_a10_pic_update(s);
  }
@@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, 
uint64_t value,
  s->nmi = value;
  break;
  case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
-s->irq_pending[index]&= ~value;
+/* Nothing to do */
  break;
  case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
-s->fiq_pending[index]&= ~value;
+/* Ditto */
  break;
  case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  s->select[index] = value;
   

pending registers are also clear registers by a10 datasheet,
also you found bits are marked as 'R', so, ..., contradict itself.
 

Yes, the datasheet is inconsistent about this because the register
can't be read-only and 'clear' at the same time.

Unfortunately at the moment I cannot test if the clearing
functionality of the pending register works on real hardware but the
idea I got from the linked discussion is that it's either not
implemented or broken and therefore interrupts remain pending until
they are disabled at the source.

Do you have a chance to try it on a real board?

   

Ah? even kernel code from allwinner wrote pending registers
to clear pending interrupt, didn't you see it?
so should be no doubt that these registers are writable.

Thanks!

Re: [Qemu-devel] [PATCH 3/7] allwinner-a10-pit: avoid generation of spurious interrupts

[Li Guang]

Beniamino Galvani wrote:

On Tue, Feb 18, 2014 at 12:17:04PM +0800, Li Guang wrote:
   

Beniamino Galvani wrote:
 

The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing to the timer callback
function a structure containing the index of the expired timer.

   

did you detect spurious?
didn't by my limited test,
code will disable any expired timer, unless be re-armed,
so it will never generate interrupt any more.
 

Yes, when both timer0 and timer1 were enabled and timer0 expired, the
previous implementation raised two interrupts because the callback
function iterated over the array of timers. Instead it should consider
only the timer that generated the event.

   


Ok, I like it this if it really can eliminate spurious interrupts.

Thanks!

   

Signed-off-by: Beniamino Galvani
---
  hw/timer/allwinner-a10-pit.c |   30 +++---
  1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index b27fce8..3e1c183 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -19,6 +19,11 @@
  #include "sysemu/sysemu.h"
  #include "hw/timer/allwinner-a10-pit.h"

+typedef struct TimerContext {
+AwA10PITState *state;
+int index;
+} TimerContext;
+
  static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
  {
  AwA10PITState *s = AW_A10_PIT(opaque);
@@ -193,18 +198,17 @@ static void a10_pit_reset(DeviceState *dev)

  static void a10_pit_timer_cb(void *opaque)
  {
-AwA10PITState *s = AW_A10_PIT(opaque);
-uint8_t i;
+TimerContext *tc = opaque;
+AwA10PITState *s = tc->state;
+uint8_t i = tc->index;

-for (i = 0; i<   AW_A10_PIT_TIMER_NR; i++) {
-if (s->control[i]&   AW_A10_PIT_TIMER_EN) {
-s->irq_status |= 1<<   i;
-if (s->control[i]&   AW_A10_PIT_TIMER_MODE) {
-ptimer_stop(s->timer[i]);
-s->control[i]&= ~AW_A10_PIT_TIMER_EN;
-}
-qemu_irq_pulse(s->irq[i]);
+if (s->control[i]&   AW_A10_PIT_TIMER_EN) {
+s->irq_status |= 1<<   i;
+if (s->control[i]&   AW_A10_PIT_TIMER_MODE) {
+ptimer_stop(s->timer[i]);
+s->control[i]&= ~AW_A10_PIT_TIMER_EN;
  }
+qemu_irq_pulse(s->irq[i]);
  }
  }

@@ -213,6 +217,7 @@ static void a10_pit_init(Object *obj)
  AwA10PITState *s = AW_A10_PIT(obj);
  SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  QEMUBH * bh[AW_A10_PIT_TIMER_NR];
+TimerContext *tc;
  uint8_t i;

  for (i = 0; i<   AW_A10_PIT_TIMER_NR; i++) {
@@ -223,7 +228,10 @@ static void a10_pit_init(Object *obj)
  sysbus_init_mmio(sbd,&s->iomem);

  for (i = 0; i<   AW_A10_PIT_TIMER_NR; i++) {
-bh[i] = qemu_bh_new(a10_pit_timer_cb, s);
+tc = g_malloc(sizeof(TimerContext));
+tc->state = s;
+tc->index = i;
+bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
  s->timer[i] = ptimer_init(bh[i]);
  ptimer_set_freq(s->timer[i], 24);
  }
   
 


   

Re: [Qemu-devel] [RFC PATCH v2 08/12] mc: core logic

[Li Guang]

Hi,
mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

This implements the core logic,
all described in the first patch (docs/mc.txt).

Signed-off-by: Michael R. Hines
---
  migration-checkpoint.c | 1565 
  1 file changed, 1565 insertions(+)
  create mode 100644 migration-checkpoint.c


   

[big snip] ...


+
+/*
+ * Stop the VM, generate the micro checkpoint,
+ * but save the dirty memory into staging memory until
+ * we can re-activate the VM as soon as possible.
+ */
+static int capture_checkpoint(MCParams *mc, MigrationState *s)
+{
+MCCopyset *copyset;
+int idx, ret = 0;
+uint64_t start, stop, copies = 0;
+int64_t start_time;
+
+mc->total_copies = 0;
+qemu_mutex_lock_iothread();
+vm_stop_force_state(RUN_STATE_CHECKPOINT_VM);
+start = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+
+/*
+ * If buffering is enabled, insert a Qdisc plug here
+ * to hold packets for the *next* MC, (not this one,
+ * the packets for this one have already been plugged
+ * and will be released after the MC has been transmitted.
+ */
+mc_start_buffer();
   


actually, I have a special request,
if QEMU started without netdev,
then don't bother me by Qdisc for network buffering. :-)

Thanks!


+
+qemu_savevm_state_begin(mc->staging,&s->params);
+ret = qemu_file_get_error(s->file);
+
+if (ret<  0) {
+migrate_set_state(s, MIG_STATE_CHECKPOINTING, MIG_STATE_ERROR);
+}
+
+qemu_savevm_state_complete(mc->staging);
+
+ret = qemu_file_get_error(s->file);
+if (ret<  0) {
+migrate_set_state(s, MIG_STATE_CHECKPOINTING, MIG_STATE_ERROR);
+goto out;
+}
+
+/*
+ * The copied memory gets appended to the end of the snapshot, so let's
+ * remember where its going to go first and start a new slab.
+ */
+mc_slab_next(mc, mc->curr_slab);
+mc->start_copyset = mc->curr_slab->idx;
+
+start_time = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+
+/*
+ * Now perform the actual copy of memory into the tail end of the slab 
list.
+ */
+QTAILQ_FOREACH(copyset,&mc->copy_head, node) {
+if (!copyset->nb_copies) {
+break;
+}
+
+copies += copyset->nb_copies;
+
+DDDPRINTF("copyset %d copies: %" PRIu64 " total: %" PRIu64 "\n",
+copyset->idx, copyset->nb_copies, copies);
+
+for (idx = 0; idx<  copyset->nb_copies; idx++) {
+uint8_t *addr;
+long size;
+mc->copy =©set->copies[idx];
+addr = (uint8_t *) (mc->copy->host_addr + mc->copy->offset);
+size = mc_put_buffer(mc, addr, mc->copy->offset, mc->copy->size);
+if (size != mc->copy->size) {
+fprintf(stderr, "Failure to initiate copyset %d index %d\n",
+copyset->idx, idx);
+migrate_set_state(s, MIG_STATE_CHECKPOINTING, MIG_STATE_ERROR);
+vm_start();
+goto out;
+}
+
+DDDPRINTF("Success copyset %d index %d\n", copyset->idx, idx);
+}
+
+copyset->nb_copies = 0;
+}
+
+s->ram_copy_time = (qemu_clock_get_ms(QEMU_CLOCK_REALTIME) - start_time);
+
+mc->copy = NULL;
+ram_control_before_iterate(mc->file, RAM_CONTROL_FLUSH);
+assert(mc->total_copies == copies);
+
+stop = qemu_clock_get_ms(QEMU_CLOCK_REALTIME);
+
+/*
+ * MC is safe in staging area. Let the VM go.
+ */
+vm_start();
+qemu_fflush(mc->staging);
+
+s->downtime = stop - start;
+out:
+qemu_mutex_unlock_iothread();
+return ret;
+}
+
+/*
+ * Synchronously send a micro-checkpointing command
+ */
+static int mc_send(QEMUFile *f, uint64_t request)
+{
+int ret = 0;
+
+qemu_put_be64(f, request);
+
+ret = qemu_file_get_error(f);
+if (ret) {
+fprintf(stderr, "transaction: send error while sending %" PRIu64 ", "
+"bailing: %s\n", request, strerror(-ret));
+} else {
+DDPRINTF("transaction: sent: %s (%" PRIu64 ")\n",
+mc_desc[request], request);
+}
+
+qemu_fflush(f);
+
+return ret;
+}
+
+/*
+ * Synchronously receive a micro-checkpointing command
+ */
+static int mc_recv(QEMUFile *f, uint64_t request, uint64_t *action)
+{
+int ret = 0;
+uint64_t got;
+
+got = qemu_get_be64(f);
+
+ret = qemu_file_get_error(f);
+if (ret) {
+fprintf(stderr, "transaction: recv error while expecting %s (%"
+PRIu64 "), bailing: %s\n", mc_desc[request],
+request, strerror(-ret));
+} else {
+if ((request != MC_TRANSACTION_ANY)&&  request != got) {
+fprintf(stderr, "transaction: was expecting %s (%" PRIu64
+") but got %" PRIu64 " instead\n",
+mc_desc[request], request, got);
+ret = -EINVAL;
+} else {
+DDPRINTF("transaction: recv: %s (%" PRIu64 ")\n",
+ 

Re: [Qemu-devel] [RFC PATCH v2 06/12] mc: introduce state machine changes for MC

[Li Guang]

Hi,

mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

This patch sets up the initial changes to the migration state
machine and prototypes to be used by the checkpointing code
to interact with the state machine so that we can later handle
failure and recovery scenarios.

Signed-off-by: Michael R. Hines
---
  arch_init.c   | 29 -
  include/migration/migration.h |  2 ++
  migration.c   | 37 +
  3 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/arch_init.c b/arch_init.c
index db75120..e9d4d9e 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -658,13 +658,13 @@ static void ram_migration_cancel(void *opaque)
  migration_end();
  }

-static void reset_ram_globals(void)
+static void reset_ram_globals(bool reset_bulk_stage)
  {
  last_seen_block = NULL;
  last_sent_block = NULL;
  last_offset = 0;
  last_version = ram_list.version;
-ram_bulk_stage = true;
+ram_bulk_stage = reset_bulk_stage;
  }

   


here is a chance that ram_save_block will never break while loop
if loat_seen_block be reset for mc when there are no dirty pages
to be migrated.

Thanks!


  #define MAX_WAIT 50 /* ms, half buffered_file limit */
@@ -674,6 +674,15 @@ static int ram_save_setup(QEMUFile *f, void *opaque)
  RAMBlock *block;
  int64_t ram_pages = last_ram_offset()>>  TARGET_PAGE_BITS;

+/*
+ * RAM stays open during micro-checkpointing for the next transaction.
+ */
+if (migration_is_mc(migrate_get_current())) {
+qemu_mutex_lock_ramlist();
+reset_ram_globals(false);
+goto skip_setup;
+}
+
  migration_bitmap = bitmap_new(ram_pages);
  bitmap_set(migration_bitmap, 0, ram_pages);
  migration_dirty_pages = ram_pages;
@@ -710,12 +719,14 @@ static int ram_save_setup(QEMUFile *f, void *opaque)
  qemu_mutex_lock_iothread();
  qemu_mutex_lock_ramlist();
  bytes_transferred = 0;
-reset_ram_globals();
+reset_ram_globals(true);

  memory_global_dirty_log_start();
  migration_bitmap_sync();
  qemu_mutex_unlock_iothread();

+skip_setup:
+
  qemu_put_be64(f, ram_bytes_total() | RAM_SAVE_FLAG_MEM_SIZE);

  QTAILQ_FOREACH(block,&ram_list.blocks, next) {
@@ -744,7 +755,7 @@ static int ram_save_iterate(QEMUFile *f, void *opaque)
  qemu_mutex_lock_ramlist();

  if (ram_list.version != last_version) {
-reset_ram_globals();
+reset_ram_globals(true);
  }

  ram_control_before_iterate(f, RAM_CONTROL_ROUND);
@@ -825,7 +836,15 @@ static int ram_save_complete(QEMUFile *f, void *opaque)
  }

  ram_control_after_iterate(f, RAM_CONTROL_FINISH);
-migration_end();
+
+/*
+ * Only cleanup at the end of normal migrations
+ * or if the MC destination failed and we got an error.
+ * Otherwise, we are (or will soon be) in MIG_STATE_CHECKPOINTING.
+ */
+if(!migrate_use_mc() || migration_has_failed(migrate_get_current())) {
+migration_end();
+}

  qemu_mutex_unlock_ramlist();
  qemu_put_be64(f, RAM_SAVE_FLAG_EOS);
diff --git a/include/migration/migration.h b/include/migration/migration.h
index a7c54fe..e876a2c 100644
--- a/include/migration/migration.h
+++ b/include/migration/migration.h
@@ -101,7 +101,9 @@ int migrate_fd_close(MigrationState *s);

  void add_migration_state_change_notifier(Notifier *notify);
  void remove_migration_state_change_notifier(Notifier *notify);
+bool migration_is_active(MigrationState *);
  bool migration_in_setup(MigrationState *);
+bool migration_is_mc(MigrationState *s);
  bool migration_has_finished(MigrationState *);
  bool migration_has_failed(MigrationState *);
  MigrationState *migrate_get_current(void);
diff --git a/migration.c b/migration.c
index 25add6f..f42dae4 100644
--- a/migration.c
+++ b/migration.c
@@ -36,16 +36,6 @@
  do { } while (0)
  #endif

-enum {
-MIG_STATE_ERROR = -1,
-MIG_STATE_NONE,
-MIG_STATE_SETUP,
-MIG_STATE_CANCELLING,
-MIG_STATE_CANCELLED,
-MIG_STATE_ACTIVE,
-MIG_STATE_COMPLETED,
-};
-
  #define MAX_THROTTLE  (32<<  20)  /* Migration speed throttling */

  /* Amount of time to allocate to each "chunk" of bandwidth-throttled
@@ -273,7 +263,7 @@ void 
qmp_migrate_set_capabilities(MigrationCapabilityStatusList *params,
  MigrationState *s = migrate_get_current();
  MigrationCapabilityStatusList *cap;

-if (s->state == MIG_STATE_ACTIVE || s->state == MIG_STATE_SETUP) {
+if (migration_is_active(s)) {
  error_set(errp, QERR_MIGRATION_ACTIVE);
  return;
  }
@@ -285,7 +275,13 @@ void 
qmp_migrate_set_capabilities(MigrationCapabilityStatusList *params,

  /* shared migration helpers */

-static void migrate_set_state(MigrationState *s, int old_state, int new_state)
+bool migration_is_active(MigrationState *s)
+{
+return (s->state == MIG_STATE_ACTIVE) || s->state == MIG_STATE_SETUP
+|| s->state == MIG_STATE

Re: [Qemu-devel] [RFC PATCH v2 00/12] mc: fault tolerante through micro-checkpointing

[Li Guang]

Hi, Michael

this patch-set will break normal build(without --enable-mc):

migration.c: In function ‘migrate_rdma_pin_all’:
migration.c:564: error: ‘MIGRATION_CAPABILITY_X_RDMA_PIN_ALL’ undeclared 
(first use in this function)

migration.c:564: error: for each function it appears in.)

Thanks!
Li Guang

mrhi...@linux.vnet.ibm.com wrote:

From: "Michael R. Hines"

Changes since v1:

1. Re-based against Juan's improved migration_bitmap performance changes
2. Overhauled RDMA support to prepare for better usage of RDMA in
other parts of the QEMU code base (such as storage).
3. Fix for netlink issues that failed to cleanup the network buffer
device for development testing.

Michael R. Hines (12):
   mc: add documentation for micro-checkpointing
   mc: timestamp migration_bitmap and KVM logdirty usage
   mc: introduce a 'checkpointing' status check into the VCPU states
   mc: support custom page loading and copying
   rdma: accelerated memcpy() support and better external RDMA user
 interfaces
   mc: introduce state machine changes for MC
   mc: introduce additional QMP statistics for micro-checkpointing
   mc: core logic
   mc: configure and makefile support
   mc: expose tunable parameter for checkpointing frequency
   mc: introduce new capabilities to control micro-checkpointing
   mc: activate and use MC if requested

  Makefile.objs |1 +
  arch_init.c   |   72 +-
  configure |   45 +
  cpus.c|9 +-
  docs/mc.txt   |  222 
  hmp-commands.hx   |   16 +-
  hmp.c |   23 +
  hmp.h |1 +
  include/migration/migration.h |   70 +-
  include/migration/qemu-file.h |   55 +-
  migration-checkpoint.c| 1565 +
  migration-rdma.c  | 2605 +++--
  migration.c   |  156 ++-
  qapi-schema.json  |   86 +-
  qemu-file.c   |   80 +-
  qmp-commands.hx   |   23 +
  vl.c  |9 +
  17 files changed, 4097 insertions(+), 941 deletions(-)
  create mode 100644 docs/mc.txt
  create mode 100644 migration-checkpoint.c

   

Re: [Qemu-devel] [PATCH 3/7] allwinner-a10-pit: avoid generation of spurious interrupts

[Li Guang]

did you detect spurious?
didn't by my limited test,
code will disable any expired timer, unless be re-armed,
so it will never generate interrupt any more.

Thanks!

Beniamino Galvani wrote:

The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing to the timer callback
function a structure containing the index of the expired timer.

Signed-off-by: Beniamino Galvani
---
  hw/timer/allwinner-a10-pit.c |   30 +++---
  1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index b27fce8..3e1c183 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -19,6 +19,11 @@
  #include "sysemu/sysemu.h"
  #include "hw/timer/allwinner-a10-pit.h"

+typedef struct TimerContext {
+AwA10PITState *state;
+int index;
+} TimerContext;
+
  static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
  {
  AwA10PITState *s = AW_A10_PIT(opaque);
@@ -193,18 +198,17 @@ static void a10_pit_reset(DeviceState *dev)

  static void a10_pit_timer_cb(void *opaque)
  {
-AwA10PITState *s = AW_A10_PIT(opaque);
-uint8_t i;
+TimerContext *tc = opaque;
+AwA10PITState *s = tc->state;
+uint8_t i = tc->index;

-for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
-if (s->control[i]&  AW_A10_PIT_TIMER_EN) {
-s->irq_status |= 1<<  i;
-if (s->control[i]&  AW_A10_PIT_TIMER_MODE) {
-ptimer_stop(s->timer[i]);
-s->control[i]&= ~AW_A10_PIT_TIMER_EN;
-}
-qemu_irq_pulse(s->irq[i]);
+if (s->control[i]&  AW_A10_PIT_TIMER_EN) {
+s->irq_status |= 1<<  i;
+if (s->control[i]&  AW_A10_PIT_TIMER_MODE) {
+ptimer_stop(s->timer[i]);
+s->control[i]&= ~AW_A10_PIT_TIMER_EN;
  }
+qemu_irq_pulse(s->irq[i]);
  }
  }

@@ -213,6 +217,7 @@ static void a10_pit_init(Object *obj)
  AwA10PITState *s = AW_A10_PIT(obj);
  SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  QEMUBH * bh[AW_A10_PIT_TIMER_NR];
+TimerContext *tc;
  uint8_t i;

  for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
@@ -223,7 +228,10 @@ static void a10_pit_init(Object *obj)
  sysbus_init_mmio(sbd,&s->iomem);

  for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
-bh[i] = qemu_bh_new(a10_pit_timer_cb, s);
+tc = g_malloc(sizeof(TimerContext));
+tc->state = s;
+tc->index = i;
+bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
  s->timer[i] = ptimer_init(bh[i]);
  ptimer_set_freq(s->timer[i], 24);
  }
   

Re: [Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered interrupts

[Li Guang]

Beniamino Galvani wrote:

Converts the interrupt generation logic to the use of level triggered
interrupts.

   


any real difference, or block something?


Signed-off-by: Beniamino Galvani
---
  hw/timer/allwinner-a10-pit.c |   13 -
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index 3e1c183..4723b25 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -24,6 +24,15 @@ typedef struct TimerContext {
  int index;
  } TimerContext;

+static void a10_pit_update_irq(AwA10PITState *s)
+{
+int i;
+
+for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
+qemu_set_irq(s->irq[i], s->irq_status&  s->irq_enable&  (1<<  i));
+}
+}
+
  static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
  {
  AwA10PITState *s = AW_A10_PIT(opaque);
@@ -79,9 +88,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, 
uint64_t value,
  switch (offset) {
  case AW_A10_PIT_TIMER_IRQ_EN:
  s->irq_enable = value;
+a10_pit_update_irq(s);
  break;
  case AW_A10_PIT_TIMER_IRQ_ST:
  s->irq_status&= ~value;
+a10_pit_update_irq(s);
  break;
  case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
  index = offset&  0xf0;
@@ -208,7 +219,7 @@ static void a10_pit_timer_cb(void *opaque)
  ptimer_stop(s->timer[i]);
  s->control[i]&= ~AW_A10_PIT_TIMER_EN;
  }
-qemu_irq_pulse(s->irq[i]);
+a10_pit_update_irq(s);
  }
  }

   

Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour

[Li Guang]

pending registers are also clear registers by a10 datasheet,
also you found bits are marked as 'R', so, ..., contradict itself.

Beniamino Galvani wrote:

According to this mail thread [1], writing to pending register seems
to have no effect on actual pending status of interrupts. This means
that the only way to clear a pending interrupt is to clear the
interrupt source. This patch implements such behaviour.

[1] http://lkml.org/lkml/2013/7/6/59

Signed-off-by: Beniamino Galvani
---
  hw/intc/allwinner-a10-pic.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index bb2351f..afd57ef 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int 
level)

  if (level) {
  set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
+} else {
+clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
  }
  aw_a10_pic_update(s);
  }
@@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, 
uint64_t value,
  s->nmi = value;
  break;
  case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
-s->irq_pending[index]&= ~value;
+/* Nothing to do */
  break;
  case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
-s->fiq_pending[index]&= ~value;
+/* Ditto */
  break;
  case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
  s->select[index] = value;
   

Re: [Qemu-devel] [PATCH 1/7] allwinner-a10-pic: set vector address when an interrupt is pending

[Li Guang]

Hi,

Beniamino Galvani wrote:

This patch implements proper updating of the vector register which
should hold, according to the A10 user manual, the vector address for
the interrupt currently active on the CPU IRQ input.

Interrupt priority is not implemented at the moment and thus the first
pending interrupt is returned.

Signed-off-by: Beniamino Galvani
---
  hw/intc/allwinner-a10-pic.c |   11 ++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..bb2351f 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -23,11 +23,20 @@
  static void aw_a10_pic_update(AwA10PICState *s)
  {
  uint8_t i;
-int irq = 0, fiq = 0;
+int irq = 0, fiq = 0, pending;
+
+s->vector = 0;

  for (i = 0; i<  AW_A10_PIC_REG_NUM; i++) {
  irq |= s->irq_pending[i]&  ~s->mask[i];
  fiq |= s->select[i]&  s->irq_pending[i]&  ~s->mask[i];
+
+if (!s->vector) {
+pending = ffs(s->irq_pending[i]&  ~s->mask[i]);
+if (pending) {
+s->vector = (i * 32 + pending - 1) * 4;
   


this maybe should determined also by interrupt priority,
and you should also remove s->vector assignment at register write phase.

Thanks!

+}
+}
  }

  qemu_set_irq(s->parent_irq, !!irq);
   

Re: [Qemu-devel] [PATCH v2] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Jan 15, 2014 at 5:06 PM, Li Guang  wrote:
   

ping ...

any other comments?
or new suggestions?

 

No new suggestions from me, but PMM has a point about
load_image_targphys@realize doing exactly whats needed, so something
closer to V1 WRT to that may actually be best.


   


but I still don't be clear with the direction, as PMM also said 
"unconvinced by the general

approach of having a device with an address property".
or, I should extend the "-machine firmware=xxx" interface
to be general?

Thanks!
Li Guang

   

Thanks!



Li Guang wrote:
 

this blob loader will be used to load a specified
blob into a specified RAM address.

Signed-off-by: Li Guang
Suggested-by: Peter Crosthwaite
---
   hw/misc/Makefile.objs |2 +
   hw/misc/blob-loader.c |  112
+
   include/hw/misc/blob-loader.h |   17 ++
   3 files changed, 131 insertions(+), 0 deletions(-)
   create mode 100644 hw/misc/blob-loader.c
   create mode 100644 include/hw/misc/blob-loader.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..3edbd5c 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
   obj-$(CONFIG_ZYNQ) += zynq_slcr.o

   obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+common-obj-y += blob-loader.o
diff --git a/hw/misc/blob-loader.c b/hw/misc/blob-loader.c
new file mode 100644
index 000..4f790e5
--- /dev/null
+++ b/hw/misc/blob-loader.c
@@ -0,0 +1,112 @@
+/*
+ * generic blob loader
+ *
+ * Copyright (C) 2014 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify
it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/loader.h"
+#include "hw/misc/blob-loader.h"
+#include "qemu/error-report.h"
+
+static Property blob_loader_props[] = {
+DEFINE_PROP_UINT64("addr", BlobLoaderState, addr, 0),
+DEFINE_PROP_STRING("file", BlobLoaderState, file),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static int load_blob_into_ram(const char *file,  uint64_t addr,  int
count)
+{
+int fd = -1, size;
+uint8_t *data;
+
+fd = open(file, O_RDONLY | O_BINARY);
+if (fd == -1) {
+error_report("can't open file %s\n", file);
+return -1;
+}
+lseek(fd, 0, SEEK_SET);
+data = g_malloc0(count);
+size = read(fd, data, count);
+if (count != size) {
+error_report("%s: read error: %d (expected %d)\n", file, size,
count);
+return -1;
+}
+close(fd);
+
+cpu_physical_memory_write_rom(addr, data, size);
+
+g_free(data);
+data = NULL;
+
+return 0;
+}
+
+static void blob_loader_reset(DeviceState *dev)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+int file_size;
+
+file_size = get_image_size(s->file);
+if (file_size<   0) {
+error_report("can't get file size of %s\n", s->file);
+exit(1);
+}
+
+if (load_blob_into_ram(s->file, s->addr, file_size)<   0) {
+error_report("can't load %s\n", s->file);
+exit(1);
+}
+}
+
+static void blob_loader_realize(DeviceState *dev, Error **errp)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+char *file_name;
+
+if (s->file == NULL) {
+error_setg(errp, "please spicify a file for blob loader.\n");
+return;
+}
+file_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->file);
+if (file_name == NULL) {
+error_setg(errp, "can't find %s\n", s->file);
+return;
+}
+}
+
+static void blob_loader_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->reset = blob_loader_reset;
+dc->realize = blob_loader_realize;
+dc->props = blob_loader_props;
+dc->desc = "blob loader";
+}
+
+static TypeInfo blob_loader_info = {
+.name = TYPE_BLOB_LOADER,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(BlobLoaderState),
+.class_init = blob_loader_class_init,
+};
+
+static void blob_loader_register_type(void)
+{
+type_register_static(&blob_loader_info);
+}
+
+type_init(blob_loader_register_type)
diff --git a/include/hw/misc/blob-loader.h b/include/hw/misc/blob-loader.h
new file mode 100644
index 000..478fd8d
--- /dev/null
+++ b/include/hw/misc/blob-loader.h
@@ -0,0 +

Re: [Qemu-devel] [PATCH v2] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

ping ...

any other comments?
or new suggestions?

Thanks!


Li Guang wrote:

this blob loader will be used to load a specified
blob into a specified RAM address.

Signed-off-by: Li Guang
Suggested-by: Peter Crosthwaite
---
  hw/misc/Makefile.objs |2 +
  hw/misc/blob-loader.c |  112 +
  include/hw/misc/blob-loader.h |   17 ++
  3 files changed, 131 insertions(+), 0 deletions(-)
  create mode 100644 hw/misc/blob-loader.c
  create mode 100644 include/hw/misc/blob-loader.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..3edbd5c 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
  obj-$(CONFIG_ZYNQ) += zynq_slcr.o

  obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+common-obj-y += blob-loader.o
diff --git a/hw/misc/blob-loader.c b/hw/misc/blob-loader.c
new file mode 100644
index 000..4f790e5
--- /dev/null
+++ b/hw/misc/blob-loader.c
@@ -0,0 +1,112 @@
+/*
+ * generic blob loader
+ *
+ * Copyright (C) 2014 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/loader.h"
+#include "hw/misc/blob-loader.h"
+#include "qemu/error-report.h"
+
+static Property blob_loader_props[] = {
+DEFINE_PROP_UINT64("addr", BlobLoaderState, addr, 0),
+DEFINE_PROP_STRING("file", BlobLoaderState, file),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static int load_blob_into_ram(const char *file,  uint64_t addr,  int count)
+{
+int fd = -1, size;
+uint8_t *data;
+
+fd = open(file, O_RDONLY | O_BINARY);
+if (fd == -1) {
+error_report("can't open file %s\n", file);
+return -1;
+}
+lseek(fd, 0, SEEK_SET);
+data = g_malloc0(count);
+size = read(fd, data, count);
+if (count != size) {
+error_report("%s: read error: %d (expected %d)\n", file, size, count);
+return -1;
+}
+close(fd);
+
+cpu_physical_memory_write_rom(addr, data, size);
+
+g_free(data);
+data = NULL;
+
+return 0;
+}
+
+static void blob_loader_reset(DeviceState *dev)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+int file_size;
+
+file_size = get_image_size(s->file);
+if (file_size<  0) {
+error_report("can't get file size of %s\n", s->file);
+exit(1);
+}
+
+if (load_blob_into_ram(s->file, s->addr, file_size)<  0) {
+error_report("can't load %s\n", s->file);
+exit(1);
+}
+}
+
+static void blob_loader_realize(DeviceState *dev, Error **errp)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+char *file_name;
+
+if (s->file == NULL) {
+error_setg(errp, "please spicify a file for blob loader.\n");
+return;
+}
+file_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->file);
+if (file_name == NULL) {
+error_setg(errp, "can't find %s\n", s->file);
+return;
+}
+}
+
+static void blob_loader_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->reset = blob_loader_reset;
+dc->realize = blob_loader_realize;
+dc->props = blob_loader_props;
+dc->desc = "blob loader";
+}
+
+static TypeInfo blob_loader_info = {
+.name = TYPE_BLOB_LOADER,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(BlobLoaderState),
+.class_init = blob_loader_class_init,
+};
+
+static void blob_loader_register_type(void)
+{
+type_register_static(&blob_loader_info);
+}
+
+type_init(blob_loader_register_type)
diff --git a/include/hw/misc/blob-loader.h b/include/hw/misc/blob-loader.h
new file mode 100644
index 000..478fd8d
--- /dev/null
+++ b/include/hw/misc/blob-loader.h
@@ -0,0 +1,17 @@
+#ifndef BLOB_LOADER_H
+#define BLOB_LOADER_H
+
+typedef struct BlobLoaderState {
+/*<  private>*/
+DeviceState parent_obj;
+/*<  public>*/
+
+uint64_t addr;
+char *file;
+} BlobLoaderState;
+
+#define TYPE_BLOB_LOADER "blob-loader"
+#define BLOB_LOADER(obj) OBJECT_CHECK(BlobLoaderState, (obj), TYPE_BLOB_LOADER)
+
+#endif
+
   

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Jan 6, 2014 at 10:13 PM, Paolo Bonzini  wrote:
   

Il 06/01/2014 08:56, Peter Crosthwaite ha scritto:
 

What are the guidelines for when to use one or the other?
 

"-machine firmware=" if you want to load a firmware blob in a board
specific way. This if you want to place a blob in memory at an
arbitrary location on reset.
   

"-machine firmware=" is also a pretty bad design because it's not
extensible and doesn't apply to most boards.  We really should get
per-board -machine options, so that you can have a less generic name
than "firmware".

 

Then we have even more divergence in boot flow between boards. It's
already a bit of a Zoo out there when it comes to bootloaders.

We expressed dislike for the Allwinner/FEX board specific bootloader
due it its mainline Linux non-acceptance. This generic solution
facilitates this case among many others and the reason its able to
achieve that goal is it has no reliance on software policy. OTOH if we
need to do everything board specific then we need to start deciding
software policy for each and every board. For allwinner, FEX was a
nack, which pretty much hangs out users of that linux kernel to dry.

Looking at QEMU ARM, we are in a position now where you can only boot
systems two ways:

1: Exactly as real HW (have to use your boards bootrom, BIOS, storage
media etc).
2. ARM Linux exactly to the letter of the mainline boot process.

With generic tools like this device, you at least let the users do a
few flexible things for boots that do not fit these two limited use
cases. And the device is completely unobtrusive on existing code. If
developers in the future come along with their weird and wonderful
board specific bootflows that we don't like we can now tell them to
use the generic blob loader for their bits and pieces and everybody
wins.

If anything, the boards implementing -machine firware="" should
implement it by layer ontop of this device.


   

agree,

further more,  "-machine firmware=" is really not generic,
we may have to deprecate it.
because if use it, every boards should do specific things for it.

Thanks!

   

Paolo

 


   

Re: [Qemu-devel] [PATCH 2/2] hw/arm/allwinner-a10: initialize EMAC

[Li Guang]

Beniamino Galvani wrote:

On Mon, Jan 06, 2014 at 08:49:18AM +0800, Li Guang wrote:
   

Hi,
please use prefix AwA10 for names instead of Aw,
also PATCH 1/2.
 

Hi,

I agree with you that there is an inconsistency in the naming of EMAC
and other A10 devices (timer, interrupt controller).

But the EMAC core is used not only on the A10; since it can be found
on other SoC of the Allwinner family, shouldn't the name be generic so
that it can be reused more easily in the future by other SoC
implementations?

   


logic is:
we emulated devices in A10, then when emulate other chips
with same devices can freely use them.

Thanks!

[Qemu-devel] [PATCH v2] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

this blob loader will be used to load a specified
blob into a specified RAM address.

Signed-off-by: Li Guang 
Suggested-by: Peter Crosthwaite 
---
 hw/misc/Makefile.objs |2 +
 hw/misc/blob-loader.c |  112 +
 include/hw/misc/blob-loader.h |   17 ++
 3 files changed, 131 insertions(+), 0 deletions(-)
 create mode 100644 hw/misc/blob-loader.c
 create mode 100644 include/hw/misc/blob-loader.h

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..3edbd5c 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+common-obj-y += blob-loader.o
diff --git a/hw/misc/blob-loader.c b/hw/misc/blob-loader.c
new file mode 100644
index 000..4f790e5
--- /dev/null
+++ b/hw/misc/blob-loader.c
@@ -0,0 +1,112 @@
+/*
+ * generic blob loader
+ *
+ * Copyright (C) 2014 Li Guang
+ * Written by Li Guang 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/loader.h"
+#include "hw/misc/blob-loader.h"
+#include "qemu/error-report.h"
+
+static Property blob_loader_props[] = {
+DEFINE_PROP_UINT64("addr", BlobLoaderState, addr, 0),
+DEFINE_PROP_STRING("file", BlobLoaderState, file),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static int load_blob_into_ram(const char *file,  uint64_t addr,  int count)
+{
+int fd = -1, size;
+uint8_t *data;
+
+fd = open(file, O_RDONLY | O_BINARY);
+if (fd == -1) {
+error_report("can't open file %s\n", file);
+return -1;
+}
+lseek(fd, 0, SEEK_SET);
+data = g_malloc0(count);
+size = read(fd, data, count);
+if (count != size) {
+error_report("%s: read error: %d (expected %d)\n", file, size, count);
+return -1;
+}
+close(fd);
+
+cpu_physical_memory_write_rom(addr, data, size);
+
+g_free(data);
+data = NULL;
+
+return 0;
+}
+
+static void blob_loader_reset(DeviceState *dev)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+int file_size;
+
+file_size = get_image_size(s->file);
+if (file_size < 0) {
+error_report("can't get file size of %s\n", s->file);
+exit(1);
+}
+
+if (load_blob_into_ram(s->file, s->addr, file_size) < 0) {
+error_report("can't load %s\n", s->file);
+exit(1);
+}
+}
+
+static void blob_loader_realize(DeviceState *dev, Error **errp)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+char *file_name;
+
+if (s->file == NULL) {
+error_setg(errp, "please spicify a file for blob loader.\n");
+return;
+}
+file_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->file);
+if (file_name == NULL) {
+error_setg(errp, "can't find %s\n", s->file);
+return;
+}
+}
+
+static void blob_loader_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->reset = blob_loader_reset;
+dc->realize = blob_loader_realize;
+dc->props = blob_loader_props;
+dc->desc = "blob loader";
+}
+
+static TypeInfo blob_loader_info = {
+.name = TYPE_BLOB_LOADER,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(BlobLoaderState),
+.class_init = blob_loader_class_init,
+};
+
+static void blob_loader_register_type(void)
+{
+type_register_static(&blob_loader_info);
+}
+
+type_init(blob_loader_register_type)
diff --git a/include/hw/misc/blob-loader.h b/include/hw/misc/blob-loader.h
new file mode 100644
index 000..478fd8d
--- /dev/null
+++ b/include/hw/misc/blob-loader.h
@@ -0,0 +1,17 @@
+#ifndef BLOB_LOADER_H
+#define BLOB_LOADER_H
+
+typedef struct BlobLoaderState {
+/*< private >*/
+DeviceState parent_obj;
+/*< public >*/
+
+uint64_t addr;
+char *file;
+} BlobLoaderState;
+
+#define TYPE_BLOB_LOADER "blob-loader"
+#define BLOB_LOADER(obj) OBJECT_CHECK(BlobLoaderState, (obj), TYPE_BLOB_LOADER)
+
+#endif
+
-- 
1.7.2.5

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Jan 6, 2014 at 3:24 PM, Li Guang  wrote:
   

Li Guang wrote:
 

Peter Crosthwaite wrote:
   

On Mon, Jan 6, 2014 at 2:22 PM, Li Guang   wrote:
 

Peter Crosthwaite wrote:
   

On Mon, Jan 6, 2014 at 1:55 PM, Li Guang
wrote:

 

Li Guang wrote:

   

Paolo Bonzini wrote:

 

Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:

   

No, please use "realize" and avoid init.  This way you can use an
Error*
to report the error.

Also, the actual load_image_targphys call probably should be done
in
a
reset handler, not at realize time.


 

Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as
possible
(file-path / address sanitsation etc) at realize time, then only
the
actual blob load happens at reset. Going on what Paolo said, I
think
for this device ::init is actually a nop.

 

Yeah, also because init is in fact a legacy interface to realize.

Paolo


   

Ok, thanks!



 

Sorry, seems load blob at reset handler can't do the right job,
while the same action can play very well at init or realize.

   

What's the exact problem with the reset idea?



 

code snippet:
static void blob_loader_reset(DeviceState *dev)
{
  BlobLoaderState *s = BLOB_LOADER(dev);

  if (load_image_targphys(s->file, s->hwaddr, MAX_BLOB_SIZE)<   0) {
  error_report("can't load %s\n", s->file);
  exit(1);
  }
}

if it is device reset handler, no result,
kernel doesn't find and parse blob,
if it is called at device realize phase,
it works.

   

Need to figure out why I think. There's no fundamental problem here
AFAIK. It must be a bug somewhere.

 

Thanks!


   

any suggestion to figure out this problem?
   

Run QEMU in GDB and break on your new reset function to see if it is
ever called. If not have a look into QOM/qdev to see how resets work
and how that plays with -device args. If yes, have a look into
load_image_targphys and see why that's not working.


 

reset handler definitely be called, and
load_image_targphys has no problem,
I guess it may be impacted by other RAM related codes,
just can't figure out it quickly.

   

Ok, I found the problem finally,
load_image_targphys depends on rom_reset to take effect,
if it's located at reset handler, rom_reset is called before it,
it surely failed to do the right job.

so, I have to write my own code to load blob into RAM.

 

dma_memory_write() work?


   


what about cpu_physical_memory_write_rom ?


Thanks!


 


   

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Li Guang wrote:

Peter Crosthwaite wrote:
On Mon, Jan 6, 2014 at 2:22 PM, Li Guang  
wrote:

Peter Crosthwaite wrote:
On Mon, Jan 6, 2014 at 1:55 PM, Li Guang   
wrote:



Li Guang wrote:


Paolo Bonzini wrote:


Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:

No, please use "realize" and avoid init.  This way you can 
use an

Error*
to report the error.

Also, the actual load_image_targphys call probably should be 
done in

a
reset handler, not at realize time.



Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as 
possible
(file-path / address sanitsation etc) at realize time, then 
only the
actual blob load happens at reset. Going on what Paolo said, I 
think

for this device ::init is actually a nop.


Yeah, also because init is in fact a legacy interface to realize.

Paolo



Ok, thanks!




Sorry, seems load blob at reset handler can't do the right job,
while the same action can play very well at init or realize.


What's the exact problem with the reset idea?




code snippet:
static void blob_loader_reset(DeviceState *dev)
{
 BlobLoaderState *s = BLOB_LOADER(dev);

 if (load_image_targphys(s->file, s->hwaddr, MAX_BLOB_SIZE)<  0) {
 error_report("can't load %s\n", s->file);
 exit(1);
 }
}

if it is device reset handler, no result,
kernel doesn't find and parse blob,
if it is called at device realize phase,
it works.


Need to figure out why I think. There's no fundamental problem here
AFAIK. It must be a bug somewhere.


Thanks!



any suggestion to figure out this problem?

Run QEMU in GDB and break on your new reset function to see if it is
ever called. If not have a look into QOM/qdev to see how resets work
and how that plays with -device args. If yes, have a look into
load_image_targphys and see why that's not working.




reset handler definitely be called, and
load_image_targphys has no problem,
I guess it may be impacted by other RAM related codes,
just can't figure out it quickly.



Ok, I found the problem finally,
load_image_targphys depends on rom_reset to take effect,
if it's located at reset handler, rom_reset is called before it,
it surely failed to do the right job.

so, I have to write my own code to load blob into RAM.

Thanks!

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Jan 6, 2014 at 2:22 PM, Li Guang  wrote:
   

Peter Crosthwaite wrote:
 

On Mon, Jan 6, 2014 at 1:55 PM, Li Guang   wrote:

   

Li Guang wrote:

 

Paolo Bonzini wrote:

   

Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:

 

No, please use "realize" and avoid init.  This way you can use an
Error*
to report the error.

Also, the actual load_image_targphys call probably should be done in
a
reset handler, not at realize time.


   

Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as possible
(file-path / address sanitsation etc) at realize time, then only the
actual blob load happens at reset. Going on what Paolo said, I think
for this device ::init is actually a nop.

   

Yeah, also because init is in fact a legacy interface to realize.

Paolo


 

Ok, thanks!



   

Sorry, seems load blob at reset handler can't do the right job,
while the same action can play very well at init or realize.

 

What's the exact problem with the reset idea?



   

code snippet:
static void blob_loader_reset(DeviceState *dev)
{
 BlobLoaderState *s = BLOB_LOADER(dev);

 if (load_image_targphys(s->file, s->hwaddr, MAX_BLOB_SIZE)<  0) {
 error_report("can't load %s\n", s->file);
 exit(1);
 }
}

if it is device reset handler, no result,
kernel doesn't find and parse blob,
if it is called at device realize phase,
it works.

 

Need to figure out why I think. There's no fundamental problem here
AFAIK. It must be a bug somewhere.

   

Thanks!


 

any suggestion to figure out this problem?
 

Run QEMU in GDB and break on your new reset function to see if it is
ever called. If not have a look into QOM/qdev to see how resets work
and how that plays with -device args. If yes, have a look into
load_image_targphys and see why that's not working.


   


reset handler definitely be called, and
load_image_targphys has no problem,
I guess it may be impacted by other RAM related codes,
just can't figure out it quickly.

Thanks!


Thanks!




 



   



 


   

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Jan 6, 2014 at 1:55 PM, Li Guang  wrote:
   

Li Guang wrote:
 

Paolo Bonzini wrote:
   

Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:
 

No, please use "realize" and avoid init.  This way you can use an
Error*
to report the error.

Also, the actual load_image_targphys call probably should be done in a
reset handler, not at realize time.

   

Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as possible
(file-path / address sanitsation etc) at realize time, then only the
actual blob load happens at reset. Going on what Paolo said, I think
for this device ::init is actually a nop.
   

Yeah, also because init is in fact a legacy interface to realize.

Paolo

 

Ok, thanks!


   

Sorry, seems load blob at reset handler can't do the right job,
while the same action can play very well at init or realize.
 

What's the exact problem with the reset idea?


   

code snippet:
static void blob_loader_reset(DeviceState *dev)
{
BlobLoaderState *s = BLOB_LOADER(dev);

if (load_image_targphys(s->file, s->hwaddr, MAX_BLOB_SIZE) < 0) {
error_report("can't load %s\n", s->file);
exit(1);
}
}

if it is device reset handler, no result,
kernel doesn't find and parse blob,
if it is called at device realize phase,
it works.

Thanks!


any suggestion to figure out this problem?

Thanks!



 


   

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Li Guang wrote:

Paolo Bonzini wrote:

Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:
No, please use "realize" and avoid init.  This way you can use an 
Error*

to report the error.

Also, the actual load_image_targphys call probably should be done 
in a

reset handler, not at realize time.


Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as possible
(file-path / address sanitsation etc) at realize time, then only the
actual blob load happens at reset. Going on what Paolo said, I think
for this device ::init is actually a nop.

Yeah, also because init is in fact a legacy interface to realize.

Paolo


Ok, thanks!



Sorry, seems load blob at reset handler can't do the right job,
while the same action can play very well at init or realize.
any suggestion to figure out this problem?

Thanks!

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Paolo Bonzini wrote:

Il 02/01/2014 11:51, Peter Crosthwaite ha scritto:
   

No, please use "realize" and avoid init.  This way you can use an Error*
to report the error.

Also, the actual load_image_targphys call probably should be done in a
reset handler, not at realize time.

 

Ok I think that settles it. The actual blobbing needs to happen at
reset time. Perhaps the correct approach is to do as much as possible
(file-path / address sanitsation etc) at realize time, then only the
actual blob load happens at reset. Going on what Paolo said, I think
for this device ::init is actually a nop.
 

Yeah, also because init is in fact a legacy interface to realize.

Paolo

   

Ok, thanks!

Re: [Qemu-devel] [PATCH 2/2] hw/arm/allwinner-a10: initialize EMAC

[Li Guang]

Hi,
please use prefix AwA10 for names instead of Aw,
also PATCH 1/2.
Thanks for your effort on this!

Beniamino Galvani wrote:

Signed-off-by: Beniamino Galvani
---
  hw/arm/allwinner-a10.c |   20 
  include/hw/arm/allwinner-a10.h |4 
  2 files changed, 24 insertions(+)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 4658e19..155e026 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -22,6 +22,7 @@
  static void aw_a10_init(Object *obj)
  {
  AwA10State *s = AW_A10(obj);
+DeviceState *dev;

  object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
  object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
@@ -31,6 +32,14 @@ static void aw_a10_init(Object *obj)

  object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
  qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+
+if (nd_table[0].used) {
+qemu_check_nic_model(&nd_table[0], "allwinner_emac");
+object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
+dev = DEVICE(&s->emac);
+qdev_set_nic_properties(dev,&nd_table[0]);
+qdev_set_parent_bus(dev, sysbus_get_default());
+}
  }

  static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -76,6 +85,17 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
  sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
  sysbus_connect_irq(sysbusdev, 5, s->irq[68]);

+if (nd_table[0].used) {
+object_property_set_bool(OBJECT(&s->emac), true, "realized",&err);
+if (err != NULL) {
+error_propagate(errp, err);
+return;
+}
+sysbusdev = SYS_BUS_DEVICE(&s->emac);
+sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
+sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
+}
+
  serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
  }
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index da36647..6ea5988 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -6,6 +6,7 @@
  #include "hw/arm/arm.h"
  #include "hw/timer/allwinner-a10-pit.h"
  #include "hw/intc/allwinner-a10-pic.h"
+#include "hw/net/allwinner_emac.h"

  #include "sysemu/sysemu.h"
  #include "exec/address-spaces.h"
@@ -14,9 +15,11 @@
  #define AW_A10_PIC_REG_BASE 0x01c20400
  #define AW_A10_PIT_REG_BASE 0x01c20c00
  #define AW_A10_UART0_REG_BASE   0x01c28000
+#define AW_A10_EMAC_BASE0x01c0b000

  #define AW_A10_SDRAM_BASE   0x4000

+
  #define TYPE_AW_A10 "allwinner-a10"
  #define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)

@@ -29,6 +32,7 @@ typedef struct AwA10State {
  qemu_irq irq[AW_A10_PIC_INT_NR];
  AwA10PITState timer;
  AwA10PICState intc;
+AwEmacState emac;
  } AwA10State;

  #define ALLWINNER_H_
   

Re: [Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

Peter Crosthwaite wrote:

On Thu, Jan 2, 2014 at 3:35 PM, Li Guang  wrote:
   

this blob loader will be used to load a specified
blob into a specified RAM address.

 

Suggested-by: Peter Crosthwaite

   

Signed-off-by: Li Guang
---
it can be used now for allwinner-a10, like:
"-device blob-loader,addr=0x4300,file=/path/script.bin"

reference:
http://linux-sunxi.org/Sunxi-tools

script file address:
http://dl.dbank.com/c00aonvlmw

Thanks to Peter Crosthwaite for the idea!
---
  default-configs/arm-softmmu.mak |2 +
  hw/misc/Makefile.objs   |2 +
  hw/misc/blob-loader.c   |   75 +++
  3 files changed, 79 insertions(+), 0 deletions(-)
  create mode 100644 hw/misc/blob-loader.c

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ce1d620..50c71a6 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -87,3 +87,5 @@ CONFIG_INTEGRATOR_DEBUG=y
  CONFIG_ALLWINNER_A10_PIT=y
  CONFIG_ALLWINNER_A10_PIC=y
  CONFIG_ALLWINNER_A10=y
+
+CONFIG_BLOB_LOADER=y
 

This shouldn't be arm specific. I would make the argument that the
blob loader has global validity.

   

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..df28288 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
  obj-$(CONFIG_ZYNQ) += zynq_slcr.o

  obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+obj-$(CONFIG_BLOB_LOADER) += blob-loader.o
diff --git a/hw/misc/blob-loader.c b/hw/misc/blob-loader.c
new file mode 100644
index 000..d7f1408
--- /dev/null
+++ b/hw/misc/blob-loader.c
@@ -0,0 +1,75 @@
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/loader.h"
+#include "qemu/error-report.h"
+
+typedef struct BlobLoaderState {
 

/*<  private>/*

   

+DeviceState qdev;
 

parent_obj;

/*<  public>/*

   

+uint32_t addr;
 

uint64_t or hwaddr. Blob loading shouldn't be limited to 32 bit.

   

+char *file;
+} BlobLoaderState;
+
+#define TYPE_BLOB_LOADER "blob-loader"
+#define BLOB_LOADER(obj) OBJECT_CHECK(BlobLoaderState, (obj), TYPE_BLOB_LOADER)
+
+static Property blob_loader_props[] = {
+DEFINE_PROP_UINT32("addr", BlobLoaderState, addr, 0),
+DEFINE_PROP_STRING("file", BlobLoaderState, file),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void do_blob_load(BlobLoaderState *s)
+{
+char *file_name;
+int file_size;
+
+if  (s->file == NULL) {
+error_report("please spicify a file for blob loader\n");
+return;
 

Should you exit(1)? Better yet, return true for error and ..

   

+}
+file_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->file);
+if (file_name == NULL) {
+error_report("can't find %s\n", s->file);
+return;
+}
+file_size = get_image_size(file_name);
+if (file_size<  0) {
+error_report("can't get file size of %s\n", file_name);
+return;
+}
+if (load_image_targphys(file_name, s->addr, file_size)<  0) {
+error_report("can't load %s\n", file_name);
+return;
+}
+}
+
+static int blob_loader_init(DeviceState *dev)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+
+do_blob_load(s);
 

exit(1) here.

   

+return 0;
+}
+
+static void blob_loader_class_init(ObjectClass *klass, void *data)
 

s/klass/oc.

   

will fix all above,

+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->props = blob_loader_props;
+dc->desc = "blob loader";
+dc->init = blob_loader_init;
 

I'm wondering whether blob loading is actually a reset step not an
init. Will doing it at init will play foul with VMSD, as your blob
loader will trample non-reset state on machine restore?


   


why will trample non-reset state on machine restore?

Thanks!


+}
+
+static TypeInfo blob_loader_info = {
+.name  = TYPE_BLOB_LOADER,
+.parent= TYPE_DEVICE,
+.instance_size = sizeof(BlobLoaderState),
+.class_init= blob_loader_class_init,
+};
+
+static void blob_loader_register_type(void)
+{
+type_register_static(&blob_loader_info);
+}
+
+type_init(blob_loader_register_type)
--
1.7.2.5


 


   

[Qemu-devel] [PATCH] hw/misc/blob-loader: add a generic blob loader

[Li Guang]

this blob loader will be used to load a specified
blob into a specified RAM address.

Signed-off-by: Li Guang 
---
it can be used now for allwinner-a10, like:
"-device blob-loader,addr=0x4300,file=/path/script.bin"

reference:
http://linux-sunxi.org/Sunxi-tools

script file address:
http://dl.dbank.com/c00aonvlmw

Thanks to Peter Crosthwaite for the idea!
---
 default-configs/arm-softmmu.mak |2 +
 hw/misc/Makefile.objs   |2 +
 hw/misc/blob-loader.c   |   75 +++
 3 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 hw/misc/blob-loader.c

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index ce1d620..50c71a6 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -87,3 +87,5 @@ CONFIG_INTEGRATOR_DEBUG=y
 CONFIG_ALLWINNER_A10_PIT=y
 CONFIG_ALLWINNER_A10_PIC=y
 CONFIG_ALLWINNER_A10=y
+
+CONFIG_BLOB_LOADER=y
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f674365..df28288 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -42,3 +42,5 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
+
+obj-$(CONFIG_BLOB_LOADER) += blob-loader.o
diff --git a/hw/misc/blob-loader.c b/hw/misc/blob-loader.c
new file mode 100644
index 000..d7f1408
--- /dev/null
+++ b/hw/misc/blob-loader.c
@@ -0,0 +1,75 @@
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/loader.h"
+#include "qemu/error-report.h"
+
+typedef struct BlobLoaderState {
+DeviceState qdev;
+uint32_t addr;
+char *file;
+} BlobLoaderState;
+
+#define TYPE_BLOB_LOADER "blob-loader"
+#define BLOB_LOADER(obj) OBJECT_CHECK(BlobLoaderState, (obj), TYPE_BLOB_LOADER)
+
+static Property blob_loader_props[] = {
+DEFINE_PROP_UINT32("addr", BlobLoaderState, addr, 0),
+DEFINE_PROP_STRING("file", BlobLoaderState, file),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void do_blob_load(BlobLoaderState *s)
+{
+char *file_name;
+int file_size;
+
+if  (s->file == NULL) {
+error_report("please spicify a file for blob loader\n");
+return;
+}
+file_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->file);
+if (file_name == NULL) {
+error_report("can't find %s\n", s->file);
+return;
+}
+file_size = get_image_size(file_name);
+if (file_size < 0) {
+error_report("can't get file size of %s\n", file_name);
+return;
+}
+if (load_image_targphys(file_name, s->addr, file_size) < 0) {
+error_report("can't load %s\n", file_name);
+return;
+}
+}
+
+static int blob_loader_init(DeviceState *dev)
+{
+BlobLoaderState *s = BLOB_LOADER(dev);
+
+do_blob_load(s);
+return 0;
+}
+
+static void blob_loader_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+dc->props = blob_loader_props;
+dc->desc = "blob loader";
+dc->init = blob_loader_init;
+}
+
+static TypeInfo blob_loader_info = {
+.name  = TYPE_BLOB_LOADER,
+.parent= TYPE_DEVICE,
+.instance_size = sizeof(BlobLoaderState),
+.class_init= blob_loader_class_init,
+};
+
+static void blob_loader_register_type(void)
+{
+type_register_static(&blob_loader_info);
+}
+
+type_init(blob_loader_register_type)
-- 
1.7.2.5

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Maydell wrote:

On 26 December 2013 19:40, Hans de Goede  wrote:
   

I'm one of the linux-sunxi developers, the only reason we've
this fex file abomination, is because we've inherited it
from the android-allwinner sources.
 

Thanks for the clarification; I suspected that might be the case.

   

Currently most of the linux-sunxi developers are no longer
focusing on the 3.4 android/allwinner derived sources we
maintain. They are currently in a "good enough for everyday
use" state.

So now most of us are focusing on getting *proper* sunxi
SoC support upstream. This is using device-tree. Currently
we've working timers, interrupt-controller, uarts, mmc,
sata, nic (both 100mbit and Gbit variants), ehci controller
and builtin rtc support with upstream kernels. Which I
believe likely covers everything the qemu emulation offers
atm. For those interested, see:
https://github.com/linux-sunxi/linux-sunxi/commits/sunxi-devel

And the mailinglist reports about progress in that branch.

 From the linux-sunxi pov fex files are a legacy thing which
will go away in the future.
 

Given that, my preference would be to not support fex
file loading in QEMU.


   


that means we don't care legacy script which already be used
in most of cases?

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Maydell wrote:

On 26 December 2013 01:09, Peter Crosthwaite
  wrote:
   

Can you just provide a generic solution to the "blob some random data
into RAM" problem (If one doesn't exist already)?
 

Well, we do already have that (see -machine firmware=whatever), but...

   


Yes, right.


I think your binary file here can then just be treated as any other
binary boot product and kept outside of QEMU.
 

...it's much easier to keep the blob outside QEMU because otherwise
it has to have a git submodule and be built somehow and is generally
a bit of a faff.

Is this FEX stuff actually supported by the upstream Linux kernel?
Googling mostly produced a bunch of stuff from a mid-year flamewar.
I definitely don't think we should add any special support for it in
QEMU if it's just some random thing that isn't going to be upstreamed.

   


OK, I will use firmware=script.bin option,
thanks!

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Crosthwaite wrote:

On Thu, Dec 26, 2013 at 10:47 AM, Peter Maydell
  wrote:
   

On 26 December 2013 00:39, Li Guang  wrote:
 

Peter Maydell wrote:
   

On 26 December 2013 00:14, Li Guang   wrote:
 

it's the approach sunxi-linux kernel config hardware,
the binary is actually a transformed text script,
and context of script is like:

[card0_boot_para]
card_ctrl = 0
card_high_speed = 1
card_line = 4
sdc_d1 = port:PF00<2><1>
sdc_d0 = port:PF01<2><1>
sdc_clk = port:PF02<2><1>
sdc_cmd = port:PF03<2><1>
sdc_d3 = port:PF04<2><1>
sdc_d2 = port:PF05<2><1>

   

So what sets this up on real hardware? Is this part of
a firmware blob? Is it in ROM or flash?
 
 

it's generally in /boot, bootloader will load it
into ram address 0x4300, kernel will find it
at this fixed address, and parse it, learn the hardware
related configuration, mostly property of devices, and
GPIOes used.
   

Weird. Why isn't this just using devicetree?
I'd rather not have to add support to QEMU's bootloader
for weird things like this if I can avoid it...

 

Can you just provide a generic solution to the "blob some random data
into RAM" problem (If one doesn't exist already)? I toyed with the
Idea of a bootloader as a device a while back, which would allow you
to implement multiple bootloaders unaware of each other, with
arbitrary command line args:

http://lists.gnu.org/archive/html/qemu-devel/2012-02/msg00858.html

That patch demonstrates creating a bootloader as a QOM object. Its
ancient, so the style is way out of date, but the idea is still there.

So you could use the ARM linux loader as is, then blob your firmware
in on the side something like:

qemu-system-arm -device blob-loader,addr=0x4300,file=/path/to/blob
-kernel ...

   


that's a good option.


I think your binary file here can then just be treated as any other
binary boot product and kept outside of QEMU.
   


Yes, I would like to keep it outside of QEMU,
what's about directly add an abstract device called "blob"?
and the device has it's properties like path, address...

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Maydell wrote:

On 26 December 2013 00:39, Li Guang  wrote:
   

Peter Maydell wrote:
 

On 26 December 2013 00:14, Li Guang   wrote:
   

it's the approach sunxi-linux kernel config hardware,
the binary is actually a transformed text script,
and context of script is like:

[card0_boot_para]
card_ctrl = 0
card_high_speed = 1
card_line = 4
sdc_d1 = port:PF00<2><1>
sdc_d0 = port:PF01<2><1>
sdc_clk = port:PF02<2><1>
sdc_cmd = port:PF03<2><1>
sdc_d3 = port:PF04<2><1>
sdc_d2 = port:PF05<2><1>

 

So what sets this up on real hardware? Is this part of
a firmware blob? Is it in ROM or flash?
   
   

it's generally in /boot, bootloader will load it
into ram address 0x4300, kernel will find it
at this fixed address, and parse it, learn the hardware
related configuration, mostly property of devices, and
GPIOes used.
 

Weird. Why isn't this just using devicetree?
   


don't know the exactly reason linux-sunxi community
do this(actually, the script parsing code mostly wrote
by engineer from Allwinner).


I'd rather not have to add support to QEMU's bootloader
for weird things like this if I can avoid it...

Who provides this file? The board manufacturer?
Where's the source? How do you create the blob?
What license are the sources under?

   


the file will vary for different board,
we can created by our-self,
just write the formatted text script, and
transform it to binary by a tool,
refer to:
http://linux-sunxi.org/Sunxi-tools

Thanks!

Re: [Qemu-devel] [PATCH] hw/sd: move sdhci.h to include/hw

[Li Guang]

Peter Maydell wrote:

On 26 December 2013 00:22, Li Guang  wrote:
   

Peter Maydell wrote:
 

On 25 December 2013 07:21, liguang   wrote:
This is where your patch should have had an explanation
for why you're making this change. What is the user outside
of hw/sd/ that needs this header that means we should
move it into include/ ?
   
   

I don't mean someone will include it outside of hw/sd, just in the
sense of "header files be better in a directory called include",
 

QEMU's policy is that header files used only by other C files within
that directory can live in that directory; include is for headers which
define functions to be used between modules.

   

A10's SDHC(really an odd controller, without public datasheet) emulation
will use some of definitions in this file, and I think many other standard
SDHC will also be happy to include this file.
 

I think all of these will live inside hw/sd so there's no need to move
the header.

   


OK, thanks!

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Maydell wrote:

On 26 December 2013 00:14, Li Guang  wrote:
   

Peter Maydell wrote:
 

On 25 December 2013 08:35, liguang   wrote:

   

sunxi-linux kernel parse config script
to do hardware configurations

Signed-off-by: liguang
---
   hw/arm/allwinner-a10.c |   18 ++
   hw/arm/cubieboard.c|2 ++
   include/hw/arm/allwinner-a10.h |5 +
   pc-bios/aw-script.bin  |  Bin 0 ->   50188 bytes

 

What is this? You can't just stick a 50K binary into the
tree with no explanation, I'm afraid.


   


it's the approach sunxi-linux kernel config hardware,
the binary is actually a transformed text script,
and context of script is like:

[card0_boot_para]
card_ctrl = 0
card_high_speed = 1
card_line = 4
sdc_d1 = port:PF00<2><1>
sdc_d0 = port:PF01<2><1>
sdc_clk = port:PF02<2><1>
sdc_cmd = port:PF03<2><1>
sdc_d3 = port:PF04<2><1>
sdc_d2 = port:PF05<2><1>
 

So what sets this up on real hardware? Is this part of
a firmware blob? Is it in ROM or flash?

   

it's generally in /boot, bootloader will load it
into ram address 0x4300, kernel will find it
at this fixed address, and parse it, learn the hardware
related configuration, mostly property of devices, and
GPIOes used.

Thanks and Merry Christmas!
Li Guang

Re: [Qemu-devel] [PATCH] hw/sd: move sdhci.h to include/hw

[Li Guang]

Peter Maydell wrote:

On 25 December 2013 07:21, liguang  wrote:

This is where your patch should have had an explanation
for why you're making this change. What is the user outside
of hw/sd/ that needs this header that means we should
move it into include/ ?

   


I don't mean someone will include it outside of hw/sd, just in the
sense of "header files be better in a directory called include",

A10's SDHC(really an odd controller, without public datasheet) emulation
will use some of definitions in this file, and I think many other standard
SDHC will also be happy to include this file.

Re: [Qemu-devel] [PATCH] allwinner-a10: add config script support

[Li Guang]

Peter Maydell wrote:

On 25 December 2013 08:35, liguang  wrote:
   

sunxi-linux kernel parse config script
to do hardware configurations

Signed-off-by: liguang
---
  hw/arm/allwinner-a10.c |   18 ++
  hw/arm/cubieboard.c|2 ++
  include/hw/arm/allwinner-a10.h |5 +
  pc-bios/aw-script.bin  |  Bin 0 ->  50188 bytes
 

What is this? You can't just stick a 50K binary into the
tree with no explanation, I'm afraid.

   


it's the approach sunxi-linux kernel config hardware,
the binary is actually a transformed text script,
and context of script is like:

[card0_boot_para]
card_ctrl = 0
card_high_speed = 1
card_line = 4
sdc_d1 = port:PF00<2><1>
sdc_d0 = port:PF01<2><1>
sdc_clk = port:PF02<2><1>
sdc_cmd = port:PF03<2><1>
sdc_d3 = port:PF04<2><1>
sdc_d2 = port:PF05<2><1>

[card2_boot_para]
card_ctrl = 2
card_high_speed = 1
card_line = 4
sdc_cmd = port:PC06<3><1>
sdc_clk = port:PC07<3><1>
sdc_d0 = port:PC08<3><1>
sdc_d1 = port:PC09<3><1>
sdc_d2 = port:PC10<3><1>
sdc_d3 = port:PC11<3><1>

[twi_para]
twi_port = 0
twi_scl = port:PB00<2>
twi_sda = port:PB01<2>

[uart_para]
uart_debug_port = 0
uart_debug_tx = port:PB22<2><1>
uart_debug_rx = port:PB23<2><1>

Re: [Qemu-devel] [PULL 00/13] QMP queue

[Li Guang]

Peter Maydell wrote:

On 18 December 2013 16:59, Luiz Capitulino  wrote:
   

   qerror: Remove assert_no_error()
 

This broke my target-arm pullreq :-(
   


Yes, QMP queue and qemu-arm queue will conflict,
because patch "target-arm/cpu: Convert reset CBAR to a property"
used assert_no_error, and here, assert_no_error removed.

-- PMM


   

Re: [Qemu-devel] [PATCH v12 2/5] hw/timer: add allwinner a10 timer

[Li Guang]

Antony Pavlov wrote:

On Fri, 13 Dec 2013 09:19:08 +0800
liguang  wrote:

   

Signed-off-by: liguang
Reviewed-by: Peter Crosthwaite
---
  default-configs/arm-softmmu.mak  |2 +
  hw/timer/Makefile.objs   |2 +
  hw/timer/allwinner-a10-pit.c |  254 ++
  include/hw/timer/allwinner-a10-pit.h |   59 
  4 files changed, 317 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/allwinner-a10-pit.c
  create mode 100644 include/hw/timer/allwinner-a10-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7858abf 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_ALLWINNER_A10_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f6ace47 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,5 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+
+obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
new file mode 100644
index 000..8bba5e2
--- /dev/null
+++ b/hw/timer/allwinner-a10-pit.c
@@ -0,0 +1,254 @@
+/*
+ * Allwinner A10 timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/allwinner-a10-pit.h"
+
+static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PITState *s = AW_A10_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+return s->irq_enable;
+case AW_A10_PIT_TIMER_IRQ_ST:
+return s->irq_status;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+return s->control[index];
+case AW_A10_PIT_TIMER_INTERVAL:
+return s->interval[index];
+case AW_A10_PIT_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+case AW_A10_PIT_WDOG_CONTROL:
+break;
+case AW_A10_PIT_WDOG_MODE:
+break;
+case AW_A10_PIT_COUNT_LO:
+return s->count_lo;
+case AW_A10_PIT_COUNT_HI:
+return s->count_hi;
+case AW_A10_PIT_COUNT_CTL:
+return s->count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ AwA10PITState *s = AW_A10_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case AW_A10_PIT_TIMER_IRQ_ST:
+s->irq_status&= ~value;
+break;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  AW_A10_PIT_TIMER_RELOAD) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
+if (s->control[index]&  AW_A10_PIT_TIMER_EN) {
+int oneshot = 0;
+if (s->control[index]&  AW_A10_PIT_TIMER_MODE) {
+oneshot = 1;
+}
+ptimer_run(s->timer[index], oneshot);
+} else {
+ptimer_stop(s->timer[index]);
+}
+break;
+case AW_A10_PIT_TIMER_INTERVAL:
+s->interval[index] = value;
+ptimer_set_limit(s->timer[index], s->interval[index], 1);
+break;
+case AW_A10_PIT_TIMER_COUNT:

Re: [Qemu-devel] [PATCH v12 1/5] vmstate: Add support for an array of ptimer_state *

[Li Guang]

Peter Crosthwaite wrote:

On Fri, Dec 13, 2013 at 11:19 AM, liguang  wrote:
   

From: Peter Maydell

Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state*
to be used by devices.

Signed-off-by: Peter Maydell
 

If you are intending someones else patch for merge as part of your own
series, you should sign it off yourself. Considering it's only one
patch, you probably can just do this on list (just like a review)
rather than a respin.

   


Ok, here's a

Signed-off-by: liguang

Thanks!




Regards,
Peter

   

---
  include/hw/ptimer.h |4 
  include/migration/vmstate.h |   10 ++
  2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index 28fcaf1..a33edf4 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -36,4 +36,8 @@ extern const VMStateDescription vmstate_ptimer;
  .offset = vmstate_offset_pointer(_state, _field, ptimer_state), \
  }

+#define VMSTATE_PTIMER_ARRAY(_f, _s, _n)\
+VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(_f, _s, _n, 0,   \
+   vmstate_ptimer, ptimer_state)
+
  #endif
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 9d09e60..be193ba 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -339,6 +339,16 @@ extern const VMStateInfo vmstate_info_bitmap;
  .offset = vmstate_offset_array(_state, _field, _type, _num), \
  }

+#define VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(_f, _s, _n, _v, _vmsd, _type) { \
+.name   = (stringify(_f)),   \
+.version_id = (_v),  \
+.num= (_n),  \
+.vmsd   =&(_vmsd),  \
+.size   = sizeof(_type *),\
+.flags  = VMS_ARRAY|VMS_STRUCT|VMS_ARRAY_OF_POINTER, \
+.offset = vmstate_offset_array(_s, _f, _type*, _n),  \
+}
+
  #define VMSTATE_STRUCT_ARRAY_TEST(_field, _state, _num, _test, _version, 
_vmsd, _type) { \
  .name = (stringify(_field)), \
  .num  = (_num),  \
--
1.7.2.5


 


   

Re: [Qemu-devel] [PATCH v11 3/5] hw/intc: add allwinner A10 interrupt controller

[Li Guang]

Peter Maydell wrote:

On 11 December 2013 08:08, liguang  wrote:
   

+static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
+{
+AwA10PICState *s = opaque;
+
+if (level) {
+set_bit(irq%32, (void *)&s->irq_pending[irq/32]);
 

The % and / operators here should have spaces round them.

   

+}
+aw_a10_pic_update(s);
+}
+
+static uint64_t aw_a10_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PICState *s = opaque;
+uint8_t index = (offset&  0xc)/4;
 

Spaces.
   


will fix,
thanks!


Otherwise
Reviewed-by: Peter Maydell

-- PMM

   

Re: [Qemu-devel] [PATCH v11 1/5] vmstate: add VMSTATE_PTIMER_ARRAY

[Li Guang]

Peter Maydell wrote:

On 11 December 2013 08:08, liguang  wrote:
   

+static int get_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = qemu_get_be64(f);
+if (count != -1) {
+ptimer_set_count(v, count);
+} else {
+ptimer_stop(v);
+}
+
+return 0;
+}
+
+static void put_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = ptimer_get_count(v);
+qemu_put_be64(f, count);
+}
+
+const VMStateInfo vmstate_info_ptimer = {
+.name = "ptimer",
+.get  = get_ptimer,
+.put  = put_ptimer,
+};
 

Sorry, I led you a bit astray with my last review comment;
this is definitely wrong because it isn't saving and
restoring each ptimer_state according to the vmstate_ptimer
definition, it's only saving a single 64 bit count.
Doing this right isn't quite as obvious as I thought
because we haven't needed to do "array of pointers to
structures" yet, so there's a missing macro.

I've written a patch which does this correctly -- I'll
send it out shortly and you can add it to your patch
series in place of this one.

   


Ok, thanks!

Re: [Qemu-devel] [PATCH v11 1/5] vmstate: add VMSTATE_PTIMER_ARRAY

[Li Guang]

ping ...
this patch is not changed since v8,
can it get some comments?

Thanks!

liguang wrote:

Signed-off-by: liguang
---
  include/migration/vmstate.h |4 
  savevm.c|   31 +++
  2 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 9d09e60..f5d6e81 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -165,6 +165,7 @@ extern const VMStateInfo vmstate_info_timer;
  extern const VMStateInfo vmstate_info_buffer;
  extern const VMStateInfo vmstate_info_unused_buffer;
  extern const VMStateInfo vmstate_info_bitmap;
+extern const VMStateInfo vmstate_info_ptimer;

  #define type_check_2darray(t1,t2,n,m) ((t1(*)[n][m])0 - (t2*)0)
  #define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
@@ -613,6 +614,9 @@ extern const VMStateInfo vmstate_info_bitmap;
  #define VMSTATE_TIMER_ARRAY(_f, _s, _n)  \
  VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_timer, QEMUTimer *)

+#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
+VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_ptimer, ptimer_state*)
+
  #define VMSTATE_BOOL_ARRAY_V(_f, _s, _n, _v) \
  VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_bool, bool)

diff --git a/savevm.c b/savevm.c
index 2f631d4..54dbb33 100644
--- a/savevm.c
+++ b/savevm.c
@@ -30,6 +30,7 @@
  #include "monitor/monitor.h"
  #include "sysemu/sysemu.h"
  #include "qemu/timer.h"
+#include "hw/ptimer.h"
  #include "audio/audio.h"
  #include "migration/migration.h"
  #include "qemu/sockets.h"
@@ -1362,6 +1363,36 @@ const VMStateInfo vmstate_info_timer = {
  .put  = put_timer,
  };

+static int get_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = qemu_get_be64(f);
+if (count != -1) {
+ptimer_set_count(v, count);
+} else {
+ptimer_stop(v);
+}
+
+return 0;
+}
+
+static void put_ptimer(QEMUFile *f, void *pv, size_t size)
+{
+ptimer_state *v = pv;
+uint64_t count;
+
+count = ptimer_get_count(v);
+qemu_put_be64(f, count);
+}
+
+const VMStateInfo vmstate_info_ptimer = {
+.name = "ptimer",
+.get  = get_ptimer,
+.put  = put_ptimer,
+};
+
  /* uint8_t buffers */

  static int get_buffer(QEMUFile *f, void *pv, size_t size)
   

Re: [Qemu-devel] [PATCH v10 5/5] hw/arm: add cubieboard support

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Dec 11, 2013 at 8:31 PM, Peter Maydell  wrote:
   

On 11 December 2013 10:24, Peter Crosthwaite
  wrote:
 

On Wed, Dec 11, 2013 at 7:56 PM, Peter Maydell  wrote:
   

On 11 December 2013 05:59, Peter Crosthwaite
  wrote:
 

On Mon, Dec 9, 2013 at 10:10 AM, liguang  wrote:
   

Signed-off-by: liguang
 

Acked-by: Peter Crosthwaite
   

Why Acked-by rather than Reviewed-by ?

 

Not 100% myself on the new QOM styles and standards around boards and
SoC. But it is reviewed by me to the best of my knowledge. If that is
enough, please feel free to promote to Reviewed-by.
   

I'd call that Reviewed-by, yes. Acked-by is just "I don't object to this"
which is a sufficiently weak statement that it's not often used...

 

Ok,

Liguang, please drop the acks on p4 and p5 and replace by Reviewed-by
on next spin.

Reviewed-by: Peter Crosthwaite
   


Ok, thanks!

Re: [Qemu-devel] [PATCH v10 2/5] hw/timer: add allwinner a10 timer

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Dec 9, 2013 at 10:10 AM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak  |2 +
  hw/timer/Makefile.objs   |2 +
  hw/timer/allwinner-a10-pit.c |  254 ++
  include/hw/timer/allwinner-a10-pit.h |   59 
  4 files changed, 317 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/allwinner-a10-pit.c
  create mode 100644 include/hw/timer/allwinner-a10-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7858abf 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_ALLWINNER_A10_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f6ace47 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,5 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+
+obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
new file mode 100644
index 000..9f898e7
--- /dev/null
+++ b/hw/timer/allwinner-a10-pit.c
@@ -0,0 +1,254 @@
+/*
+ * Allwinner A10 timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/allwinner-a10-pit.h"
+
+static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PITState *s = AW_A10_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+return s->irq_enable;
+case AW_A10_PIT_TIMER_IRQ_ST:
+return s->irq_status;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+return s->control[index];
+case AW_A10_PIT_TIMER_INTERVAL:
+return s->interval[index];
+case AW_A10_PIT_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+case AW_A10_PIT_WDOG_CONTROL:
+break;
+case AW_A10_PIT_WDOG_MODE:
+break;
+case AW_A10_PIT_COUNT_LO:
+return s->count_lo;
+case AW_A10_PIT_COUNT_HI:
+return s->count_hi;
+case AW_A10_PIT_COUNT_CTL:
+return s->count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ AwA10PITState *s = AW_A10_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case AW_A10_PIT_TIMER_IRQ_ST:
+s->irq_status&= ~value;
+break;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  AW_A10_PIT_TIMER_RELOAD) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
+if (s->control[index]&  AW_A10_PIT_TIMER_EN) {
+int oneshot = 0;
+if (s->control[index]&  AW_A10_PIT_TIMER_MODE) {
+oneshot = 1;
+}
+ptimer_run(s->timer[index], oneshot);
+} else {
+ptimer_stop(s->timer[index]);
+}
+break;
+case AW_A10_PIT_TIMER_INTERVAL:
+s->interval[index] = value;
+ptimer_set_limit(s->timer[index], s->interval[index], 1);
+break;
+case AW_A10_PIT_TIMER_COUNT:
+s->count

Re: [Qemu-devel] [PATCH v10 3/5] hw/intc: add allwinner A10 interrupt controller

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Dec 9, 2013 at 10:10 AM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |1 +
  hw/intc/Makefile.objs   |1 +
  hw/intc/allwinner-a10-pic.c |  217 +++
  include/hw/intc/allwinner-a10-pic.h |   40 +++
  4 files changed, 259 insertions(+), 0 deletions(-)
  create mode 100644 hw/intc/allwinner-a10-pic.c
  create mode 100644 include/hw/intc/allwinner-a10-pic.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7858abf..e965068 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y

  CONFIG_ALLWINNER_A10_PIT=y
+CONFIG_ALLWINNER_A10_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..60eb936 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -24,3 +24,4 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
  obj-$(CONFIG_SH4) += sh_intc.o
  obj-$(CONFIG_XICS) += xics.o
  obj-$(CONFIG_XICS_KVM) += xics_kvm.o
+obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
new file mode 100644
index 000..9345741
--- /dev/null
+++ b/hw/intc/allwinner-a10-pic.c
@@ -0,0 +1,217 @@
+/*
+ * Allwinner A10 interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/allwinner-a10-pic.h"
+
+static void aw_a10_pic_update(AwA10PICState *s)
+{
+uint8_t i, j;
+bool irq = false, fiq = false;
+
+for (i = 0, j = 0; i<  AW_A10_PIC_REG_NUM; i++) {
+if (s->irq_pending[i] == 0&&  s->fiq_pending[i] == 0) {
+continue;
+}
+for (j = 0; j<  32; j++) {
+if (test_bit(j, (void *)&s->mask[i])) {
+continue;
+}
+if (test_bit(j, (void *)&s->irq_pending[i])) {
+irq = true;
+}
+if (test_bit(j, (void *)&s->fiq_pending[i])&&
+test_bit(j, (void *)&s->select[i])) {
+fiq = true;
+}
+if (irq&&  fiq) {
+goto out;
+}
+}
 

So looking at this more closely, why not just:

irq ||= s->mask[i]&  s->irq_pending[i];
fiq ||= s->mask[i]&  s->fiq_pending[i]&  s->select[i];

Instead of this inner for loop? Drop the fast path if above it as well.

I remember getting rid of the word-wise&  | logic in an earlier
version because of cross-over between the three regs. But thats now
resolved here with the outer loop. This inner loop should be able to
be done with word-wise&  | logic.

   


fine, fixed like this:
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 9345741..49a0fd1 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
@@ -22,31 +22,14 @@

 static void aw_a10_pic_update(AwA10PICState *s)
 {
-uint8_t i, j;
-bool irq = false, fiq = false;
-
-for (i = 0, j = 0; i < AW_A10_PIC_REG_NUM; i++) {
-if (s->irq_pending[i] == 0 && s->fiq_pending[i] == 0) {
-continue;
-}
-for (j = 0; j < 32; j++) {
-if (test_bit(j, (void *)&s->mask[i])) {
-continue;
-}
-if (test_bit(j, (void *)&s->irq_pending[i])) {
-irq = true;
-}
-if (test_bit(j, (void *)&s->fiq_pending[i]) &&
-test_bit(j, (void *)&s->select[i])) {
-fiq = true;
-}
-if (irq && fiq) {
-goto out;
-}
-}
+uint8_t i;
+int irq = 0, fiq = 0;
+
+for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
+irq |= s->irq_pending[i] & ~s->mask[i];
+fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
 }

-out:
 qemu_set_irq(s->parent_irq, irq);
 qemu_set_irq(s->parent_fiq, fiq);

Thanks!


+}
+
+out:
+qemu_set_irq(s->parent_irq, irq);
+qemu_set_irq(s->parent_fiq, fiq);
+}
+
+static void aw_a10_pic_set_irq(void *opaque, int irq, int level)
+{
+A

Re: [Qemu-devel] [PATCH 1/7] define hotplug interface

[Li Guang]

Hi, Igor

Igor Mammedov wrote:

Provide generic hotplug interface for devices.
Intended for replacing hotplug mechanism used by
PCI/PCIE/SHPC code.

Signed-off-by: Igor Mammedov
---
it's scsi-bus like interface, but abstracted from bus altogether
since all current users care about in hotplug handlers, it's
hotplug device and hotplugged device and bus only serves
as a means to get access to hotplug device and it's callbacks.
---
  hw/core/Makefile.objs |1 +
  hw/core/hotplug.c |   25 
  include/hw/hotplug.h  |   50 +
  3 files changed, 76 insertions(+), 0 deletions(-)
  create mode 100644 hw/core/hotplug.c
  create mode 100644 include/hw/hotplug.h

diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 950146c..47f6555 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -10,4 +10,5 @@ common-obj-$(CONFIG_SOFTMMU) += sysbus.o
  common-obj-$(CONFIG_SOFTMMU) += null-machine.o
  common-obj-$(CONFIG_SOFTMMU) += loader.o
  common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
+common-obj-$(CONFIG_SOFTMMU) += hotplug.o

diff --git a/hw/core/hotplug.c b/hw/core/hotplug.c
new file mode 100644
index 000..3e84d9c
--- /dev/null
+++ b/hw/core/hotplug.c
@@ -0,0 +1,25 @@
+/*
+ * Hotplug device interface.
+ *
+ * Copyright (c) 2013 Red Hat Inc.
+ *
+ * Authors:
+ *  Igor Mammedov,
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw/hotplug.h"
+
+static const TypeInfo hotplug_device_info = {
+.name  = TYPE_HOTPLUG_DEVICE,
+.parent= TYPE_INTERFACE,
+.class_size = sizeof(HotplugDeviceClass),
+};
+
+static void hotplug_device_register_types(void)
+{
+type_register_static(&hotplug_device_info);
+}
+
+type_init(hotplug_device_register_types)
diff --git a/include/hw/hotplug.h b/include/hw/hotplug.h
new file mode 100644
index 000..cfa79bb
--- /dev/null
+++ b/include/hw/hotplug.h
@@ -0,0 +1,50 @@
+/*
+ * Hotplug device interface.
+ *
+ * Copyright (c) 2013 Red Hat Inc.
+ *
+ * Authors:
+ *  Igor Mammedov,
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef HOTPLUG_H
+#define HOTPLUG_H
+
+#include "hw/qdev-core.h"
+
+#define TYPE_HOTPLUG_DEVICE "hotplug-device"
+
+#define HOTPLUG_DEVICE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(HotplugDeviceClass, (klass), TYPE_HOTPLUG_DEVICE)
+#define HOTPLUG_DEVICE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(HotplugDeviceClass, (obj), TYPE_HOTPLUG_DEVICE)
+
   


Hmm..., this is interface, but device, a bold opinion,
can have something like TYPE_HOTPLUG_INTERFACE ... ?


+/**
+ * hotplug_fn:
+ * @hotplug_dev: a device performing hotplug/uplug action
   


s/uplug/unplug


Thanks!
Li Guang


+ * @hotplugged_dev: a device that has been hotplugged
+ * @errp: returns an error if this function fails
+ */
+typedef void (*hotplug_fn)(DeviceState *hotplug_dev,
+   DeviceState *hotplugged_dev, Error **errp);
+
+/**
+ * HotplugDeviceClass:
+ *
+ * Interface to be implemented by a device performing
+ * hardware hotplug/unplug functions.
+ *
+ * @parent: Opaque parent interface.
+ * @hotplug: hotplug callback.
+ * @hot_unplug: hot unplug callback.
+ */
+typedef struct HotplugDeviceClass {
+InterfaceClass parent;
+
+hotplug_fn hotplug;
+hotplug_fn hot_unplug;
+} HotplugDeviceClass;
+
+#endif
   

Re: [Qemu-devel] [PATCH v9 0/5] add allwinner A10 SoC support

[Li Guang]

Peter Crosthwaite wrote:

Hi Liguang,

V9 has some checkpatch errors:

[pcrost@xsjandreislx qemu]$ git format-patch HEAD~5
0001-vmstate-add-VMSTATE_PTIMER_ARRAY.patch
0002-hw-timer-add-allwinner-a10-timer.patch
0003-hw-intc-add-allwinner-A10-interrupt-controller.patch
0004-hw-arm-add-allwinner-a10-SoC-support.patch
0005-hw-arm-add-cubieboard-support.patch
[pcrost@xsjandreislx qemu]$ ./scripts/checkpatch.pl 00*
ERROR: need consistent spacing around '*' (ctx:WxB)
#30: FILE: include/migration/vmstate.h:618:
+VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_ptimer,
ptimer_state *)

^

total: 1 errors, 0 warnings, 59 lines checked

0001-vmstate-add-VMSTATE_PTIMER_ARRAY.patch has style problems, please
review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
WARNING: line over 80 characters
#75: FILE: hw/timer/allwinner-a10-pit.c:33:
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 +
AW_A10_PIT_TIMER_COUNT:

WARNING: line over 80 characters
#124: FILE: hw/timer/allwinner-a10-pit.c:82:
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 +
AW_A10_PIT_TIMER_COUNT:

total: 0 errors, 2 warnings, 320 lines checked

0002-hw-timer-add-allwinner-a10-timer.patch has style problems, please
review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 266 lines checked

0003-hw-intc-add-allwinner-A10-interrupt-controller.patch has no
obvious style problems and is ready for submission.
total: 0 errors, 0 warnings, 130 lines checked

0004-hw-arm-add-allwinner-a10-SoC-support.patch has no obvious style
problems and is ready for submission.
total: 0 errors, 0 warnings, 58 lines checked

0005-hw-arm-add-cubieboard-support.patch has no obvious style problems
and is ready for submission.

Please include checkpatch in your pre-send checklist for each version.

   


I surely will run checkpatch.pl,
but you know, the result is just a reference.

the error here seems subtle,
2 rules used,
1. should a space both before and after '*'
2. shouldn't a space before ')'

so, a dilemma.


I'm still looking trough the series though (now that I have it am'ed
locally), so don't respin on me just yet!


   

OK.
Thanks!


On Thu, Dec 5, 2013 at 10:51 AM, liguang  wrote:
   

lay a foundation for allwinner A10 SoC with a cortex-a8
processor, and will add more devices later.

v2: split timer and interrupt controller emulation into
 their corresponding files.

v3:
1. change loader_start address
2. add 64-bit counter
3. fixup fail to clear interrup status issue

v4:
1. add VMSD
2. use defines of magic number for readability
3. code cleanup

v5:
1. add VMSTATE_PTIMER_ARRAY
2. code cleanup

v6:
1. fix a fiq lost issue pointed out by Peter Crosthwaite
2. code cleanup

v7:
model allwinner A10 as a SoC device,
and add cubieboard.

v8:
1. A10 be QOMified as a device
2. add AW as prefix of A10

v9:
code cleanup for PATCH 4/5 A10 SoC support


TODO:
1. add BROM support
2. add more devices

test:
can boot-up officially released linux kernel build with
PLL disabled.
can find test zImage url at:
http://dl.dbank.com/c0jaibr54s

reference:
http://linux-sunxi.org/Main_Page


Li Guang (5)
  vmstate: add VMSTATE_PTIMER_ARRAY
  hw/timer: add allwinner a10 timer
  hw/intc: add allwinner A10 interrupt controller
  hw/arm: add allwinner a10 SoC support
  hw/arm: add cubieboard support

default-configs/arm-softmmu.mak  |   2 +
hw/arm/Makefile.objs |   4 +-
hw/arm/allwinner-a10.c   |  39 
+++
hw/arm/cubieboard.c  |  33 +
hw/intc/Makefile.objs|   1 +
hw/intc/allwinner-a10_pic.c  | 218 +++
hw/timer/Makefile.objs   |   2 +
hw/timer/allwinner-a10_pit.c | 253 ++
include/hw/arm/allwinner-a10.h   |  27 +++
include/hw/intc/allwinner-a10_pic.h  |  40 +++
include/hw/timer/allwinner-a10_pit.h |  57 
include/migration/vmstate.h  |   4 
savevm.c |  31 +++
13 files changed, 709 insertions(+), 2 deletions(-)
  create mode 100644 hw/timer/allwinner-a10_pit.c
  create mode 100644 include/hw/timer/allwinner-a10_pit.h
  create mode 100644 hw/intc/allwinner-a10_pic.c
  create mode 100644 include/hw/intc/allwinner-a10_pic.h
  create mode 100644 hw/arm/allwinner-a10.c
  create mode 100644 include/hw/arm/allwinner-a10.h
  create mode 100644 hw/arm/cubieboard.c



 
   

Re: [Qemu-devel] [PATCH v9 0/5] add allwinner A10 SoC support

[Li Guang]

I think with your suggestion
of new definition will remove the warnings,
and I will fix the error report.

Thanks!


Peter Crosthwaite wrote:

Hi Liguang,

V9 has some checkpatch errors:

[pcrost@xsjandreislx qemu]$ git format-patch HEAD~5
0001-vmstate-add-VMSTATE_PTIMER_ARRAY.patch
0002-hw-timer-add-allwinner-a10-timer.patch
0003-hw-intc-add-allwinner-A10-interrupt-controller.patch
0004-hw-arm-add-allwinner-a10-SoC-support.patch
0005-hw-arm-add-cubieboard-support.patch
[pcrost@xsjandreislx qemu]$ ./scripts/checkpatch.pl 00*
ERROR: need consistent spacing around '*' (ctx:WxB)
#30: FILE: include/migration/vmstate.h:618:
+VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_info_ptimer,
ptimer_state *)

^

total: 1 errors, 0 warnings, 59 lines checked

0001-vmstate-add-VMSTATE_PTIMER_ARRAY.patch has style problems, please
review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
WARNING: line over 80 characters
#75: FILE: hw/timer/allwinner-a10-pit.c:33:
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 +
AW_A10_PIT_TIMER_COUNT:

WARNING: line over 80 characters
#124: FILE: hw/timer/allwinner-a10-pit.c:82:
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 +
AW_A10_PIT_TIMER_COUNT:

total: 0 errors, 2 warnings, 320 lines checked

0002-hw-timer-add-allwinner-a10-timer.patch has style problems, please
review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 266 lines checked

0003-hw-intc-add-allwinner-A10-interrupt-controller.patch has no
obvious style problems and is ready for submission.
total: 0 errors, 0 warnings, 130 lines checked

0004-hw-arm-add-allwinner-a10-SoC-support.patch has no obvious style
problems and is ready for submission.
total: 0 errors, 0 warnings, 58 lines checked

0005-hw-arm-add-cubieboard-support.patch has no obvious style problems
and is ready for submission.

Please include checkpatch in your pre-send checklist for each version.

I'm still looking trough the series though (now that I have it am'ed
locally), so don't respin on me just yet!

Regards,
Peter

On Thu, Dec 5, 2013 at 10:51 AM, liguang  wrote:
   

lay a foundation for allwinner A10 SoC with a cortex-a8
processor, and will add more devices later.

v2: split timer and interrupt controller emulation into
 their corresponding files.

v3:
1. change loader_start address
2. add 64-bit counter
3. fixup fail to clear interrup status issue

v4:
1. add VMSD
2. use defines of magic number for readability
3. code cleanup

v5:
1. add VMSTATE_PTIMER_ARRAY
2. code cleanup

v6:
1. fix a fiq lost issue pointed out by Peter Crosthwaite
2. code cleanup

v7:
model allwinner A10 as a SoC device,
and add cubieboard.

v8:
1. A10 be QOMified as a device
2. add AW as prefix of A10

v9:
code cleanup for PATCH 4/5 A10 SoC support


TODO:
1. add BROM support
2. add more devices

test:
can boot-up officially released linux kernel build with
PLL disabled.
can find test zImage url at:
http://dl.dbank.com/c0jaibr54s

reference:
http://linux-sunxi.org/Main_Page


Li Guang (5)
  vmstate: add VMSTATE_PTIMER_ARRAY
  hw/timer: add allwinner a10 timer
  hw/intc: add allwinner A10 interrupt controller
  hw/arm: add allwinner a10 SoC support
  hw/arm: add cubieboard support

default-configs/arm-softmmu.mak  |   2 +
hw/arm/Makefile.objs |   4 +-
hw/arm/allwinner-a10.c   |  39 
+++
hw/arm/cubieboard.c  |  33 +
hw/intc/Makefile.objs|   1 +
hw/intc/allwinner-a10_pic.c  | 218 +++
hw/timer/Makefile.objs   |   2 +
hw/timer/allwinner-a10_pit.c | 253 ++
include/hw/arm/allwinner-a10.h   |  27 +++
include/hw/intc/allwinner-a10_pic.h  |  40 +++
include/hw/timer/allwinner-a10_pit.h |  57 
include/migration/vmstate.h  |   4 
savevm.c |  31 +++
13 files changed, 709 insertions(+), 2 deletions(-)
  create mode 100644 hw/timer/allwinner-a10_pit.c
  create mode 100644 include/hw/timer/allwinner-a10_pit.h
  create mode 100644 hw/intc/allwinner-a10_pic.c
  create mode 100644 include/hw/intc/allwinner-a10_pic.h
  create mode 100644 hw/arm/allwinner-a10.c
  create mode 100644 include/hw/arm/allwinner-a10.h
  create mode 100644 hw/arm/cubieboard.c



 


   

Re: [Qemu-devel] [PATCH v8 2/5] hw/timer: add allwinner a10 timer

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Dec 4, 2013 at 6:09 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak  |2 +
  hw/timer/Makefile.objs   |2 +
  hw/timer/allwinner-a10-pit.c |  253 ++
  include/hw/timer/allwinner-a10-pit.h |   57 
  4 files changed, 314 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/allwinner-a10-pit.c
  create mode 100644 include/hw/timer/allwinner-a10-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..0029596 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_ALLWINNER_A10=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..3020388 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,5 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+
+obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10-pit.o
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
new file mode 100644
index 000..2305813
--- /dev/null
+++ b/hw/timer/allwinner-a10-pit.c
@@ -0,0 +1,253 @@
+/*
+ * Allwinner A10 timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/allwinner-a10-pit.h"
+
+
 

Not sure of the motivation for extra blank lines.

   


can strip


+static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+AwA10PITState *s = AW_A10_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+return s->irq_enable;
+case AW_A10_PIT_TIMER_IRQ_ST:
+return s->irq_status;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 + 
AW_A10_PIT_TIMER_COUNT:
 

It's strange to me that AW_A10_PIT_TIMER_BASE is used as both an
offset and a stride. It's only co-incidence that 0x10 is both the
offset of the first timers' individual registers as well as the diff
between timer register offsets. I think you could just simplify by
putting it all in the header, something like:

#define AW_A10_PIT_TIMER_BASE_END (AW_A10_PIT_TIMER_BASE * 6 + 0x10).

   


good suggestion!


+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+return s->control[index];
+case AW_A10_PIT_TIMER_INTERVAL:
+return s->interval[index];
+case AW_A10_PIT_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+case AW_A10_PIT_WDOG_CONTROL:
+break;
+case AW_A10_PIT_WDOG_MODE:
+break;
+case AW_A10_PIT_COUNT_LO:
+return s->count_lo;
+case AW_A10_PIT_COUNT_HI:
+return s->count_hi;
+case AW_A10_PIT_COUNT_CTL:
+return s->count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ AwA10PITState *s = AW_A10_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case AW_A10_PIT_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case AW_A10_PIT_TIMER_IRQ_ST:
+s->irq_status&= ~value;
+break;
+case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE * 6 + 
AW_A10_PIT_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case AW_A10_PIT_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  AW_A10_PIT_TIMER_RELOAD) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
+if (s->control[index]& 

Re: [Qemu-devel] [PATCH v8 4/5] hw/arm: add allwinner a10 SoC support

[Li Guang]

(obj), TYPE_AW_A10)
+
+typedef struct AwA10State {
+/*<  private>*/
+DeviceState parent_obj;
+/*<  public>*/
+
+ARMCPU cpu;
+qemu_irq irq[AW_A10_PIC_INT_NR];
+qemu_irq cpu_irq[2];
 

I dont see the need to keep these as device state. They appear to be
just local variables to realize().

   

+AwA10PITState timer;
+AwA10PICState intc;
+} AwA10State;
+
+#define ALLWINNER_H_
+#endif
--
1.7.2.5


 
   

OK, will fix.

Thanks!
Li Guang

Re: [Qemu-devel] [PATCH 2/5] hw/timer: add allwinner a10 timer

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Dec 3, 2013 at 7:11 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak  |2 +
  hw/timer/Makefile.objs   |2 +
  hw/timer/allwinner-a10_pit.c |  253 ++
 

Mix of _ and - in filename is ugly. I think all - in filename is best.

   


OK , will fix,
though I think '_' and '-' have different meanings here.
'_' is for separation,
'-' is for concatenation.

  include/hw/timer/allwinner-a10_pit.h |   57 
  4 files changed, 314 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/allwinner-a10_pit.c
  create mode 100644 include/hw/timer/allwinner-a10_pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..0029596 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_ALLWINNER_A10=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..4ff2e1f 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,5 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+
+obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10_pit.o
diff --git a/hw/timer/allwinner-a10_pit.c b/hw/timer/allwinner-a10_pit.c
new file mode 100644
index 000..2f9b458
--- /dev/null
+++ b/hw/timer/allwinner-a10_pit.c
@@ -0,0 +1,253 @@
+/*
+ * Allwinner A10 timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/allwinner-a10_pit.h"
+
+
+static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+A10PITState *s = A10_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case A10PIT_TIMER_IRQ_EN:
 

Its odd to have no _ between A10 and PIT. Does that match your documentation?

   


hmm, OK, will fix


+return s->irq_enable;
+case A10PIT_TIMER_IRQ_ST:
+return s->irq_status;
+case A10PIT_TIMER_BASE ...  A10PIT_TIMER_BASE * 6 + A10PIT_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case A10PIT_TIMER_CONTROL:
+return s->control[index];
+case A10PIT_TIMER_INTERVAL:
+return s->interval[index];
+case A10PIT_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+case A10PIT_WDOG_CONTROL:
+break;
+case A10PIT_WDOG_MODE:
+break;
+case A10PIT_COUNT_LO:
+return s->count_lo;
+case A10PIT_COUNT_HI:
+return s->count_hi;
+case A10PIT_COUNT_CTL:
+return s->count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ A10PITState *s = A10_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case A10PIT_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case A10PIT_TIMER_IRQ_ST:
+s->irq_status&= ~value;
+break;
+case A10PIT_TIMER_BASE ...  A10PIT_TIMER_BASE * 6 + A10PIT_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case A10PIT_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  A10PIT_TIMER_RELOAD) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
 

Why? Doesn't the count just always stay up to date when writing TIMER_INTERVAL?

   


just do as datasheet says, "Reload timer Interval value"


+if (s->control[index]&  A10PIT_TIMER_EN) {
+ptimer_run(s->timer[index], 1);
+} else {
+pt

Re: [Qemu-devel] [PATCH 5/5] hw/arm: add cubieboard support

[Li Guang]

Andreas Färber wrote:

Am 03.12.2013 13:01, schrieb Peter Crosthwaite:
   

On Tue, Dec 3, 2013 at 7:11 PM, liguang  wrote:
 

Signed-off-by: liguang
---
  hw/arm/Makefile.objs |2 +-
  hw/arm/cubieboard.c  |   33 +
  2 files changed, 34 insertions(+), 1 deletions(-)
  create mode 100644 hw/arm/cubieboard.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index b9e5983..8be8d8e 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -4,4 +4,4 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
  obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o

  obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
-obj-y += omap1.o omap2.o strongarm.o allwinner-a10.o
+obj-y += omap1.o omap2.o strongarm.o allwinner-a10.o cubieboard.o
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
new file mode 100644
index 000..a5be21c
--- /dev/null
+++ b/hw/arm/cubieboard.c
@@ -0,0 +1,33 @@
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/allwinner-a10.h"
+
+
+static struct arm_boot_info cubieboard_binfo = {
+.loader_start = A10_SDRAM_BASE,
+.board_id = 0x1008,
+};
+
+static void cubieboard_init(QEMUMachineInitArgs *args)
+{
+A10State *s = a10_init(get_system_memory(), args->ram_size);
+
+cubieboard_binfo.ram_size = args->ram_size;
+cubieboard_binfo.kernel_filename = args->kernel_filename;
+cubieboard_binfo.kernel_cmdline = args->kernel_cmdline;
   

I cant help but think that serial attachment needs to happen on the
board level. but im not sure how this can be made to work with the
un-qomified serial_mm_init, so no block from me unless Andreas has a
better idea.
 

I don't have an immediate solution, same problem in Tegra2 code.

If someone is willing to convert serial_mm into QOM-friendly form that
would be nice but I will be unavailable for review the next ~two weeks.

What I do wonder here is why this is calling a new a10_init() rather
than object_new() and related QOM APIs. get_system_memory() can without
problems be called inside the device. If RAM is really on the SoC (it is
for Tegra2/3) then it could become a property of the device with
MemoryRegion initialization in realize - that is still unclean in my
code IIRC.

   

+arm_load_kernel(s->cpu,&cubieboard_binfo);
+}
   

[...]
   

+machine_init(cubieboard_machine_init);
   

No semicolon here please, it's a function.

   


Yes, thanks!

Re: [Qemu-devel] [PATCH 5/5] hw/arm: add cubieboard support

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Dec 3, 2013 at 7:11 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  hw/arm/Makefile.objs |2 +-
  hw/arm/cubieboard.c  |   33 +
  2 files changed, 34 insertions(+), 1 deletions(-)
  create mode 100644 hw/arm/cubieboard.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index b9e5983..8be8d8e 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -4,4 +4,4 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
  obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o

  obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
-obj-y += omap1.o omap2.o strongarm.o allwinner-a10.o
+obj-y += omap1.o omap2.o strongarm.o allwinner-a10.o cubieboard.o
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
new file mode 100644
index 000..a5be21c
--- /dev/null
+++ b/hw/arm/cubieboard.c
@@ -0,0 +1,33 @@
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/allwinner-a10.h"
+
+
+static struct arm_boot_info cubieboard_binfo = {
+.loader_start = A10_SDRAM_BASE,
+.board_id = 0x1008,
+};
+
+static void cubieboard_init(QEMUMachineInitArgs *args)
+{
+A10State *s = a10_init(get_system_memory(), args->ram_size);
+
+cubieboard_binfo.ram_size = args->ram_size;
+cubieboard_binfo.kernel_filename = args->kernel_filename;
+cubieboard_binfo.kernel_cmdline = args->kernel_cmdline;
 

I cant help but think that serial attachment needs to happen on the
board level. but im not sure how this can be made to work with the
un-qomified serial_mm_init, so no block from me unless Andreas has a
better idea.

   

+arm_load_kernel(s->cpu,&cubieboard_binfo);
+}
+
+static QEMUMachine cubieboard_machine = {
+.name = "cubieboard",
+.init = cubieboard_init,
 

I think you should add at least the long descriptor so -M help plays nice.

   


OK, thanks!

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Andreas Färber wrote:

Am 29.11.2013 09:06, schrieb Li Guang:
   

Andreas Färber wrote:
 

Am 29.11.2013 01:46, schrieb Li Guang:

   

Andreas Färber wrote:

 

Am 27.11.2013 10:22, schrieb Andreas Färber:

   

[...] To my understanding, "sunxi" is the name of a
community effort [1] to clean up and upstream the BSP kernels from
Allwinner, so it sounds as if this was an attempt to write an
emulation
for that kernel family while naming everything "sunxi" when in fact
the
SoCs are called Axx [2] (with A1x = sun4i, A2x = sun5i, A3x = sun6i
but


 

My interpolation was incorrect: A10 = sun4i, A13 = sun5i, A3x = sun6i,
A20 = sun7i

   

no literal "sunxi" AFAIK) and boards include Cubieboard, Cubieboard2,
Cubieboard3/Cubietruck [3] and whatever tablets etc. are out there.
(CC'ing Bamvor)

That's a lesson we learned from the old "prep" machine: Please name
things after real hardware, only then can it later be verified whether
the modeling is actually correct or which changes need to be
performed.



 

well, sunxi maybe be representation of Axx series,
but, what's wrong?

 

You're modeling too general IMO and thereby you're creating a
virtual-only machine (despite parallel efforts by Linaro to introduce
mach-virt for that purpose). Please model an actual piece of hardware -
SoC and board - and not something random that happens to run with the
"sunxi" kernel flavor but will leave us puzzled in the future. Should be
pretty easy to avoid.

My example was qemu-system-ppc -M prep. Today no one knows what hardware
that was supposed to match (possibly none) because there are a number of
different PReP based machines from IBM and Motorola out there; switching
from OpenHack'Ware to OpenBIOS became difficult because among other
things we don't have a device tree dump from a physical machine to
compare to, and Hervé thus set out to create new machines such as 40P
where we actually know which components the hardware contains rather
than which drivers are available in the kernel and happened to have
matching QEMU device implementations at the time.
A slightly similar problem occurred with -M pc, where we now have an
i440fx based one and the new q35 based one. It's easier to abstract
commonalities and share code between different devices/machines than
turning a generic machine/device into a less generic one, in particular
for backwards compatibility for guests, command line and QMP.

When the difference between two devices is just a value or an offset,
then you can use static properties to set them and have the realize
function take them into account. If the composition tree differs
significantly or if you want to facilitate reuse, then different types
will be needed. Multiple machines can call a shared helper function with
some parameter; examples include PC, Versatile Express and DIGIC.


   

we can't track Axx hardware changes? why?

 

Sorry, I don't get that? The Sunxi, Allwinner and Wikipedia pages all
document some key differences, in particular Cortex-A8 in A10/A13 vs.
Cortex-A7 in A20/A31. Cortex-A7 has MPCore, which drags along some key
differences that cannot easily fit in a single SunxiState SoC device.

   

right, A10/20... seem have similar devices except CPU

 

At least from my understanding of Cortex-A9 and Cortex-A15 being much
closer than Cortex-A8, that is. For example, you have your own PIC for
the Cortex-A8 in this series whereas Cortex-A7 will use ARM's GIC and
may be able to reuse the "a15mpcore_priv" composite device.
http://en.wikipedia.org/wiki/List_of_ARM_microprocessor_cores#Designed_by_ARM



   

and also, this patch-set is also community effort just like
sunxi in linux kernel.

 

My whole point is, try to design the model forward from hardware and
less backwards from kernel. Whether it's sun4i or A10 is less relevant.
Kernels may contain bugs. Hardware doesn't change except for new revs,
but definitely not depending on who writes a kernel to run on it. :)


   

of course, I am aiming to emulate the real hardware,
so name is not the problem, right?
 

It is. The x in sunxi appears to be a wildcard.

Quoting http://linux-sunxi.org/Main_Page:
"sunxi represents the family of ARM SoC [...] made by Allwinner Tech."

The Boxship F20 is named as "sun3i", so it's even ARM9, Cortex-A8 and
Cortex-A7 all within that family. That goes beyond what we can model by
some revision property on a "sunxi" device or with -cpu, and we cannot
today create some deep detail device such as MPCore and wire that up to
containing devices. You can only instantiate devices from the command
line that sit on a bus that supports automatic wiring-up based on device
properties and knowledge of peers on the bus. In particular you cannot
initialize IRQs or m

Re: [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY

[Li Guang]

Peter Maydell wrote:

On 29 November 2013 11:01, Peter Maydell  wrote:
   

On 27 November 2013 08:23, liguang  wrote:
 

Signed-off-by: liguang
---
  include/hw/ptimer.h |3 +++
  1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index 28fcaf1..a9b8f1d 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -27,6 +27,9 @@ void ptimer_stop(ptimer_state *s);

  extern const VMStateDescription vmstate_ptimer;

+#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
+VMSTATE_STRUCT_ARRAY(_f, _s, _n, 0, vmstate_ptimer, ptimer_state*)
   

The final parameter here should just be the struct type
("ptimer_state"), not a pointer-to-it.
 

Actually, looking at the patch where you've used this,
you do actually want to deal with an
array-of-pointers-to-ptimers. For that you need

#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
 VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_ptimer, ptimer_state *)

(compare VMSTATE_TIMER_ARRAY in vmstate.h)


   


OK, thanks!

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Bamvor Jian Zhang wrote:

Hi,

  >>>Li Guang  wrote:
   

Andreas Färber wrote:
 

Am 29.11.2013 01:46, schrieb Li Guang:

   

Andreas Färber wrote:

 

Am 27.11.2013 10:22, schrieb Andreas Färber:


   

Hi,

Am 26.11.2013 10:22, schrieb Peter Crosthwaite:


 

On Tue, Nov 26, 2013 at 5:22 PM, liguang
wrote:


   

Signed-off-by: liguang
---
hw/arm/Makefile.objs |1 +
hw/arm/sunxi-soc.c   |   98
++
2 files changed, 99 insertions(+), 0 deletions(-)
create mode 100644 hw/arm/sunxi-soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..f9f3071 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o
xilinx_zynq.o z2.o

obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
+obj-y += sunxi-soc.o
diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
new file mode 100644
index 000..b45af6d
--- /dev/null
+++ b/hw/arm/sunxi-soc.c
@@ -0,0 +1,98 @@
+/*
+ * Allwinner sunxi series SoC emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as published
by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "hw/ptimer.h"
+#include "hw/char/serial.h"
+#include "hw/timer/sunxi-pit.h"
+#include "hw/intc/sunxi-pic.h"
+
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+
+
+#define SUNXI_PIC_REG_BASE 0x01c20400
+#define SUNXI_PIT_REG_BASE 0x01c20c00
+#define SUNXI_UART0_REG_BASE 0x01c28000
+
+static struct arm_boot_info sunxi_binfo = {
+.loader_start = 0x4000,
+.board_id = 0x1008,
+};
+
+static void sunxi_init(QEMUMachineInitArgs *args)


 

I would check with Andreas/PMM on what the go is with SoCs regarding
container devices and boards. My (vague) understanding is that SoCs
should be container devices and boards instantiate those containers
with off-chip connectivity. This seems flat to me, with everything on
board level.


   

Yes, thanks, that matches what I was going to comment. But I think it's
even more complicated: To my understanding, "sunxi" is the name of a
community effort [1] to clean up and upstream the BSP kernels from
Allwinner, so it sounds as if this was an attempt to write an emulation
for that kernel family while naming everything "sunxi" when in fact the
SoCs are called Axx [2] (with A1x = sun4i, A2x = sun5i, A3x = sun6i but


 

My interpolation was incorrect: A10 = sun4i, A13 = sun5i, A3x = sun6i,
A20 = sun7i

Andreas



   

no literal "sunxi" AFAIK) and boards include Cubieboard, Cubieboard2,
Cubieboard3/Cubietruck [3] and whatever tablets etc. are out there.
(CC'ing Bamvor)

That's a lesson we learned from the old "prep" machine: Please name
things after real hardware, only then can it later be verified whether
the modeling is actually correct or which changes need to be performed.



 

well, sunxi maybe be representation of Axx series,
but, what's wrong?

 

You're modeling too general IMO and thereby you're creating a
virtual-only machine (despite parallel efforts by Linaro to introduce
mach-virt for that purpose). Please model an actual piece of hardware -
SoC and board - and not something random that happens to run with the
"sunxi" kernel flavor but will leave us puzzled in the future. Should be
pretty easy to avoid.

My example was qemu-system-ppc -M prep. Today no one knows what hardware
that was supposed to match (possibly none) because there are a number of
different PReP based machines from IBM and Motorola out there; switching
from OpenHack'Ware to OpenBIOS became difficult because among other
things we don't have a device tree dump from a physical machine to
compare to, and Hervé thus set out to create new machines such as 40P
where we actually know which components the hardware contains rather
than which drivers are available in the kernel and happened to have
matching QEMU device implementations at the time.
A slightly similar problem occurred with -M pc, where we now have an
i440fx based one and the new q35 based one. It's easier to abstract
commonalities and share cod

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Peter Maydell wrote:

On 29 November 2013 08:06, Li Guang  wrote:
   

what I design is:
we have a sunxi series as a machine, then
for sunx4i, we specify -M sunxi -cpu cortex-a8 -device x1 ...
for sunx5i, we specify -M sunxi -cpu cortex-a8 -device x2 ...
for sunx7i, we specify -M sunxi -cpu cortex-a7 -devcie x3 ...
for cubieboard, we specify -M sunxi -cpu -cortex-a8 -device x1 -device p1
 

No, QEMU doesn't work this way. "-M whatever" specifies a board
model, so in this example it should be "-M cubieboard" and so on.
That then gives you a particular CPU and set of devices. Obviously
where we have several board models that share a single SoC they
share implementation (by instantiating the same SoC object).
If we have several SoCs that share common subcomponents like
a UART, then they share implementation by having all those SoCs
instantiate the same UART object.

-cpu is really only intended where you have a situation like the
PC where just the CPU can be plugged and unplugged into a
board; it doesn't fit for SoC-based systems.
Similarly, -device is really (currently) for pluggable devices like
ISA or PCI cards -- where the device is a non-removable
part of the SoC it doesn't work.
   


why not just say this SoC is a board?
and other board like cubieboard are only
this SoC + several devices,
I think is reasonable, at least in this case.

A10 and A13 both have a cortex-a8, different in HDMI and SATA,
suppose we modeled A10, A10State,
if we add cubieboard, we realize A10,
then we have a board called demoboard based on A13,
what we will do here?
also realize A10?  unlucky, we miss HDMI and SATA difference,
model A13? new a A13State?
but we have most devices the same for A10 & A13.



As Andreas says, we need to model real actual hardware,
not some abstraction that kind of matches the kernel's
abstractions.
   


I never aimed to do what you said abstraction,
I just specified a represented of real hardware.


Is "sunxi" what the hardware is actually called, or only
what the kernel port has been called? More information
about where this name comes from might make it easier
to tell if it is the correct one for the QEMU SoC models.


   


I tried to contact Allwinner's engineer,
no response until now.

Thanks!
Li Guang

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Andreas Färber wrote:

Am 29.11.2013 01:46, schrieb Li Guang:
   

Andreas Färber wrote:
 

Am 27.11.2013 10:22, schrieb Andreas Färber:

   

Hi,

Am 26.11.2013 10:22, schrieb Peter Crosthwaite:

 

On Tue, Nov 26, 2013 at 5:22 PM, liguang
wrote:

   

Signed-off-by: liguang
---
   hw/arm/Makefile.objs |1 +
   hw/arm/sunxi-soc.c   |   98
++
   2 files changed, 99 insertions(+), 0 deletions(-)
   create mode 100644 hw/arm/sunxi-soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..f9f3071 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o
xilinx_zynq.o z2.o

   obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
   obj-y += omap1.o omap2.o strongarm.o
+obj-y += sunxi-soc.o
diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
new file mode 100644
index 000..b45af6d
--- /dev/null
+++ b/hw/arm/sunxi-soc.c
@@ -0,0 +1,98 @@
+/*
+ * Allwinner sunxi series SoC emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as published
by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "hw/ptimer.h"
+#include "hw/char/serial.h"
+#include "hw/timer/sunxi-pit.h"
+#include "hw/intc/sunxi-pic.h"
+
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+
+
+#define SUNXI_PIC_REG_BASE 0x01c20400
+#define SUNXI_PIT_REG_BASE 0x01c20c00
+#define SUNXI_UART0_REG_BASE 0x01c28000
+
+static struct arm_boot_info sunxi_binfo = {
+.loader_start = 0x4000,
+.board_id = 0x1008,
+};
+
+static void sunxi_init(QEMUMachineInitArgs *args)

 

I would check with Andreas/PMM on what the go is with SoCs regarding
container devices and boards. My (vague) understanding is that SoCs
should be container devices and boards instantiate those containers
with off-chip connectivity. This seems flat to me, with everything on
board level.

   

Yes, thanks, that matches what I was going to comment. But I think it's
even more complicated: To my understanding, "sunxi" is the name of a
community effort [1] to clean up and upstream the BSP kernels from
Allwinner, so it sounds as if this was an attempt to write an emulation
for that kernel family while naming everything "sunxi" when in fact the
SoCs are called Axx [2] (with A1x = sun4i, A2x = sun5i, A3x = sun6i but

 

My interpolation was incorrect: A10 = sun4i, A13 = sun5i, A3x = sun6i,
A20 = sun7i

Andreas


   

no literal "sunxi" AFAIK) and boards include Cubieboard, Cubieboard2,
Cubieboard3/Cubietruck [3] and whatever tablets etc. are out there.
(CC'ing Bamvor)

That's a lesson we learned from the old "prep" machine: Please name
things after real hardware, only then can it later be verified whether
the modeling is actually correct or which changes need to be performed.


 

well, sunxi maybe be representation of Axx series,
but, what's wrong?
 

You're modeling too general IMO and thereby you're creating a
virtual-only machine (despite parallel efforts by Linaro to introduce
mach-virt for that purpose). Please model an actual piece of hardware -
SoC and board - and not something random that happens to run with the
"sunxi" kernel flavor but will leave us puzzled in the future. Should be
pretty easy to avoid.

My example was qemu-system-ppc -M prep. Today no one knows what hardware
that was supposed to match (possibly none) because there are a number of
different PReP based machines from IBM and Motorola out there; switching
from OpenHack'Ware to OpenBIOS became difficult because among other
things we don't have a device tree dump from a physical machine to
compare to, and Hervé thus set out to create new machines such as 40P
where we actually know which components the hardware contains rather
than which drivers are available in the kernel and happened to have
matching QEMU device implementations at the time.
A slightly similar problem occurred with -M pc, where we now have an
i440fx based one and the new q35 based one. It's easier to abstract
commonalities and share code between different devices/machines than
turning a generic machine/device into a less generic one, in particular
for backwards compa

Re: [Qemu-devel] [fixed-up][PATCH v6 2/5] hw/timer: add sunxi timer device

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Nov 27, 2013 at 11:35 PM, Peter Crosthwaite
  wrote:
   

On Wed, Nov 27, 2013 at 6:29 PM, liguang  wrote:
 

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |2 +
  hw/timer/Makefile.objs  |1 +
  hw/timer/sunxi-pit.c|  254 +++
  include/hw/timer/sunxi-pit.h|   56 +
  4 files changed, 313 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/sunxi-pit.c
  create mode 100644 include/hw/timer/sunxi-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 000..19bc16c
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,254 @@
+/*
+ * Allwinner sunxi timer device emulation
   

May need to do global find/replace on sunxi, depending on outcoming of
the naming discussion.

 

+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPITState *s = SUNXI_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+return s->irq_enable;
+case SUNXI_TIMER_IRQ_ST:
+return s->irq_status;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+return s->control[index];
+case SUNXI_TIMER_INTERVAL:
+return s->interval[index];
+case SUNXI_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+case SUNXI_WDOG_CONTROL:
+break;
+case SUNXI_WDOG_MODE:
+break;
+case SUNXI_COUNT_LO:
+return s->count_lo;
+break;
   

break after return.

git diff | grep "return" -A 1 | grep "break"

It's crude, but will find any you missed.

 

+case SUNXI_COUNT_HI:
+return s->count_hi;
+break;
+case SUNXI_COUNT_CTL:
+return s->count_ctl;
+default:
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Bad offset 0x%x\n",  __func__, (int)offset);
+break;
+}
+
+return 0;
+}
+
+static void sunxi_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t index;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case SUNXI_TIMER_IRQ_ST:
+s->irq_status&= ~value;
+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  SUNXI_TIMER_RELOAD) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
+if (s->control[index]&  SUNXI_TIMER_EN) {
+ptimer_run(s->timer[index], 1);
+} else {
+ptimer_stop(s->timer[index]);
+}
+break;
+case SUNXI_TIMER_INTERVAL:
+s->interval[index] = value;
+ptimer_set_count(s->timer[index], s-&g

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Andreas Färber wrote:

Am 27.11.2013 10:22, schrieb Andreas Färber:
   

Hi,

Am 26.11.2013 10:22, schrieb Peter Crosthwaite:
 

On Tue, Nov 26, 2013 at 5:22 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  hw/arm/Makefile.objs |1 +
  hw/arm/sunxi-soc.c   |   98 ++
  2 files changed, 99 insertions(+), 0 deletions(-)
  create mode 100644 hw/arm/sunxi-soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..f9f3071 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o

  obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
  obj-y += omap1.o omap2.o strongarm.o
+obj-y += sunxi-soc.o
diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
new file mode 100644
index 000..b45af6d
--- /dev/null
+++ b/hw/arm/sunxi-soc.c
@@ -0,0 +1,98 @@
+/*
+ * Allwinner sunxi series SoC emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "hw/ptimer.h"
+#include "hw/char/serial.h"
+#include "hw/timer/sunxi-pit.h"
+#include "hw/intc/sunxi-pic.h"
+
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+
+
+#define SUNXI_PIC_REG_BASE 0x01c20400
+#define SUNXI_PIT_REG_BASE 0x01c20c00
+#define SUNXI_UART0_REG_BASE 0x01c28000
+
+static struct arm_boot_info sunxi_binfo = {
+.loader_start = 0x4000,
+.board_id = 0x1008,
+};
+
+static void sunxi_init(QEMUMachineInitArgs *args)
 

I would check with Andreas/PMM on what the go is with SoCs regarding
container devices and boards. My (vague) understanding is that SoCs
should be container devices and boards instantiate those containers
with off-chip connectivity. This seems flat to me, with everything on
board level.
   

Yes, thanks, that matches what I was going to comment. But I think it's
even more complicated: To my understanding, "sunxi" is the name of a
community effort [1] to clean up and upstream the BSP kernels from
Allwinner, so it sounds as if this was an attempt to write an emulation
for that kernel family while naming everything "sunxi" when in fact the
SoCs are called Axx [2] (with A1x = sun4i, A2x = sun5i, A3x = sun6i but
 

My interpolation was incorrect: A10 = sun4i, A13 = sun5i, A3x = sun6i,
A20 = sun7i

Andreas

   

no literal "sunxi" AFAIK) and boards include Cubieboard, Cubieboard2,
Cubieboard3/Cubietruck [3] and whatever tablets etc. are out there.
(CC'ing Bamvor)

That's a lesson we learned from the old "prep" machine: Please name
things after real hardware, only then can it later be verified whether
the modeling is actually correct or which changes need to be performed.

 


well, sunxi maybe be representation of Axx series,
but, what's wrong?
we can't track Axx hardware changes? why?
and also, this patch-set is also community effort just like
sunxi in linux kernel.


A practical aspect of modeling SoCs correctly is that they can more
easily be reused across boards or modules, and you don't need to mess
with machine-level cpu_model if you have a fixed SoC-CPU mapping.
 


modeling SoC is good, but
sorry, I can't assure that fixed mapping.


You may want to consult the recent DIGIC or earlier Faraday series or my
Tegra2 repository for examples of how to implement this paradigm.
I believe the composition tree naming wrt "cortex" and the MPCore was
still open, hopefully PMM can comment on his current preferences.

And thanks for your efforts, from a distribution viewpoint I am looking
forward to testing our kernels and images with this.
 


currently, I can only provide linux kernel build for sunxi-4i,
where I can up-load it to?


Regards,
Andreas

[1] http://linux-sunxi.org/Main_Page
[2] http://www.allwinnertech.com/en/product/A-Serial.html
 


this page is can't accessed for me.

Thanks for your comment!

Li Guang


[3] http://cubieboard.org/

 


   

Re: [Qemu-devel] [PATCH v6 0/5] add sunxi machine type

[Li Guang]

Peter Crosthwaite wrote:

Hi Liguang,

On Wed, Nov 27, 2013 at 6:23 PM, liguang  wrote:
   

this patch-set implemented a device-reduced
machine type for Allwinner's sunxi series SoC,
like sunxi-4i/5i/7i ...

now, It can support sunxi-4i with a cortex-a8 processor.
and will support more later, like sunxi-7i with cortex-a7,
and will add more devices.

v2: split timer and interrupt controller emulation into
 their corresponding files.

v3:
1. change loader_start address
2. add 64-bit counter
3. fixup fail to clear interrup status issue

v4:
1. add VMSD
2. use defines of magic number for readability
3. code cleanup

v5:
1. add VMSTATE_PTIMER_ARRAY
2. code cleanup

v6:
1. fix a fiq lost issue pointed out by Peter Crosthwaite
2. code cleanup

 

These respins are getting pretty thick and fast. You should give the
other maintainers at least overnight (if not a few days) to weigh in
as well.


   

OK,  thanks!
just a little busy on other jobs, :-)
   

TODO:
1. add BROM support
2. add more devices
3. add sunxi-7i support

test:
can boot-up officially released linux kernel.

reference:
http://linux-sunxi.org/Main_Page

Li Guang (5)
  hw/ptimer: add VMSTATE_PTIMER_ARRAY
  hw/timer: add sunxi timer device
  hw/intc: add sunxi interrupt controller device
  hw/arm: add sunxi machine type
  MAINTAINERS: add myself to maintain sunxi machine

MAINTAINERS |   9 +
default-configs/arm-softmmu.mak |   3 +
hw/arm/Makefile.objs|   1 +
hw/arm/sunxi-soc.c  |  98 
++
hw/intc/Makefile.objs   |   1 +
hw/intc/sunxi-pic.c | 244 +++
hw/timer/Makefile.objs  |   1 +
hw/timer/sunxi-pit.c| 276 +++
include/hw/intc/sunxi-pic.h |  20 +++
include/hw/ptimer.h |   3 +++
include/hw/timer/sunxi-pit.h|  37 +
11 files changed, 693 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/sunxi-pit.c
  create mode 100644 include/hw/timer/sunxi-pit.h
  create mode 100644 hw/intc/sunxi-pic.c
  create mode 100644 include/hw/intc/sunxi-pic.h
  create mode 100644 hw/arm/sunxi-soc.c



 
   

Re: [Qemu-devel] [fixed-up][PATCH v5 3/5] hw/intc: add sunxi interrupt controller device

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Nov 27, 2013 at 4:12 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |1 +
  hw/intc/Makefile.objs   |1 +
  hw/intc/sunxi-pic.c |  247 +++
  include/hw/intc/sunxi-pic.h |   20 +++
  4 files changed, 269 insertions(+), 0 deletions(-)
  create mode 100644 hw/intc/sunxi-pic.c
  create mode 100644 include/hw/intc/sunxi-pic.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7bf5ad0..bbe00e4 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y

  CONFIG_SUNXI_PIT=y
+CONFIG_SUNXI_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..dad8c43 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
  common-obj-$(CONFIG_OPENPIC) += openpic.o
+common-obj-$(CONFIG_SUNXI_PIC) += sunxi-pic.o

  obj-$(CONFIG_APIC) += apic.o apic_common.o
  obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
new file mode 100644
index 000..a588c30
--- /dev/null
+++ b/hw/intc/sunxi-pic.c
@@ -0,0 +1,247 @@
+/*
+ * Allwinner sunxi interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/sunxi-pic.h"
+
+
+typedef struct SunxiPICState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+MemoryRegion iomem;
+qemu_irq parent_fiq;
+qemu_irq parent_irq;
+
+uint32_t vector;
+uint32_t base_addr;
+uint32_t protect;
+uint32_t nmi;
+uint32_t irq_pending[SUNXI_PIC_REG_IDX];
 

IDX is a wierd choice of suffix here. Is this really a "_NUM". I'm
happy as is though.

   


maybe, does this struct need to move to sunxi-pic.h?


+uint32_t fiq_pending[SUNXI_PIC_REG_IDX];
+uint32_t select[SUNXI_PIC_REG_IDX];
+uint32_t enable[SUNXI_PIC_REG_IDX];
+uint32_t mask[SUNXI_PIC_REG_IDX];
+/*priority setting here*/
+} SunxiPICState;
+
+static void sunxi_pic_update(SunxiPICState *s)
+{
+uint8_t i, j;
+bool irq = false, fiq = false;
+
+for (i = 0, j = 0; i<  SUNXI_PIC_REG_IDX; i++) {
+if (s->irq_pending[i] == 0&&  s->fiq_pending[i] == 0) {
+continue;
+}
+for (j = 0; j<  32; j++) {
+if (test_bit(j, (void *)&s->mask[i])) {
+continue;
+}
+if (test_bit(j, (void *)&s->irq_pending[i])) {
+irq = true;
+}
+if (test_bit(j, (void *)&s->fiq_pending[i])&&
+test_bit(j, (void *)&s->select[i])) {
+fiq = true;
+}
+if (irq || fiq) {
 

This should be an&&  - the missed fiq problem i mentioned last time
still isnt solved. If an early iteration of this loop sets irq then no
latter iterations are given the chance to set fiq. You can only bail
out of the loop if both irq and fix are set. You could just ditch this
escape logic completely as I doubt its too much of a performance hit.

   

+goto out;
+}
+}
+}
+
+out:
+qemu_set_irq(s->parent_irq, irq);
+qemu_set_irq(s->parent_fiq, fiq);
+}
+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+SunxiPICState *s = opaque;
+
+if (level) {
+set_bit(irq%32, (void *)&s->irq_pending[irq/32]);
+}
+sunxi_pic_update(s);
+}
+
+static uint64_t sunxi_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPICState *s = opaque;
+uint8_t index = (offset&  0xc)/4;
+
+switch (offset) {
+case SUNXI_PIC_VECTOR:
+return s->vector;
+break;
 

Breaks after return. Fix globally.

Regards,
Peter


   

Re: [Qemu-devel] [PATCH v5 2/5] hw/timer: add sunxi timer device

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Nov 27, 2013 at 3:36 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |2 +
  hw/timer/Makefile.objs  |1 +
  hw/timer/sunxi-pit.c|  276 +++
  include/hw/timer/sunxi-pit.h|   37 +
  4 files changed, 316 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/sunxi-pit.c
  create mode 100644 include/hw/timer/sunxi-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 000..36eb13c
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,276 @@
+/*
+ * Allwinner sunxi timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+typedef struct SunxiPITState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+qemu_irq irq[SUNXI_TIMER_NR];
+ptimer_state *timer[SUNXI_TIMER_NR];
+MemoryRegion iomem;
+
+uint32_t  irq_enable;
+uint32_t irq_status;
+uint32_t control[SUNXI_TIMER_NR];
+uint32_t interval[SUNXI_TIMER_NR];
+uint32_t count[SUNXI_TIMER_NR];
+uint32_t watch_dog_mode;
+uint32_t watch_dog_control;
+uint32_t count_lo;
+uint32_t count_hi;
+uint32_t count_ctl;
+} SunxiPITState;
 

So i've done some more list reasearch. If you want this to work with
the latest SoC style device model layout, you need to move this struct
definition to the device header file, so container object can embed it
with their container state structs. Check the arm mpcore and its
subcomponents (e.g. mptimer) for a very modern example.

   

+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPITState *s = SUNXI_PIT(opaque);
+uint8_t index;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+return s->irq_enable;
+break;
 

break after return not needed. Does this throw a werror? Fix globally.

   

+case SUNXI_TIMER_IRQ_ST:
+return s->irq_status;
+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+return s->control[index];
+break;
+case SUNXI_TIMER_INTERVAL:
+return s->interval[index];
+break;
+case SUNXI_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+break;
     

This is also a guest error condition. Same in write().


   


will fix all.

Thanks!
Li Guang

Re: [Qemu-devel] [PATCH v4 2/4] hw/intc: add sunxi interrupt controller device

[Li Guang]

Peter Crosthwaite wrote:

On Wed, Nov 27, 2013 at 1:36 PM, Li Guang  wrote:
   

Li Guang wrote:
 

Peter Crosthwaite wrote:
   

On Tue, Nov 26, 2013 at 5:22 PM, liguang   wrote:
 

Signed-off-by: liguang
---
   default-configs/arm-softmmu.mak |1 +
   hw/intc/Makefile.objs   |1 +
   hw/intc/sunxi-pic.c |  238
+++
   include/hw/intc/sunxi-pic.h |   20 
   
   

+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+SunxiPICState *s = opaque;
+
+if (level) {
+set_bit(irq, (void *)&s->irq_pending[irq/32]);
   

set_bit(irq % 32, ...)

 

OK
   


No, it is wrong,
irq/32 is right.

 

The irq/32 is right I agree. This issue is the first arugment.
Shouln't the whole thing be:

set_bit(irq%32, (void *)&s->irq_pending[irq/32]);


   


OK, fix like this

diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
index 5fd86f9..ea75f84 100644
--- a/hw/intc/sunxi-pic.c
+++ b/hw/intc/sunxi-pic.c
@@ -77,7 +77,7 @@ static void sunxi_pic_set_irq(void *opaque, int irq, 
int level)

 SunxiPICState *s = opaque;

 if (level) {
-set_bit(irq, (void *)&s->irq_pending[irq/32]);
+set_bit(irq%32, (void *)&s->irq_pending[irq/32]);
 }
     sunxi_pic_update(s);

thanks!
Li Guang

Re: [Qemu-devel] [PATCH v4 2/4] hw/intc: add sunxi interrupt controller device

[Li Guang]

Li Guang wrote:

Peter Crosthwaite wrote:
On Tue, Nov 26, 2013 at 5:22 PM, liguang  
wrote:

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |1 +
  hw/intc/Makefile.objs   |1 +
  hw/intc/sunxi-pic.c |  238 
+++

  include/hw/intc/sunxi-pic.h |   20 
  4 files changed, 260 insertions(+), 0 deletions(-)
  create mode 100644 hw/intc/sunxi-pic.c
  create mode 100644 include/hw/intc/sunxi-pic.h

diff --git a/default-configs/arm-softmmu.mak 
b/default-configs/arm-softmmu.mak

index 7bf5ad0..bbe00e4 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y

  CONFIG_SUNXI_PIT=y
+CONFIG_SUNXI_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..dad8c43 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
  common-obj-$(CONFIG_OPENPIC) += openpic.o
+common-obj-$(CONFIG_SUNXI_PIC) += sunxi-pic.o

  obj-$(CONFIG_APIC) += apic.o apic_common.o
  obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
new file mode 100644
index 000..e84fc55
--- /dev/null
+++ b/hw/intc/sunxi-pic.c
@@ -0,0 +1,238 @@
+/*
+ * Allwinner sunxi interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or 
modify it
+ * under the terms of the GNU General Public License as published 
by the

+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, 
but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of 
MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 
License

+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/sunxi-pic.h"
+
+
+typedef struct SunxiPICState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+MemoryRegion iomem;
+qemu_irq parent_fiq;
+qemu_irq parent_irq;

Blank line here for readability.



OK

+uint32_t vector;
+uint32_t base_addr;
+uint32_t protect;
+uint32_t nmi;
+uint32_t irq_pending[SUNXI_PIC_REG_IDX];
+uint32_t fiq_pending[SUNXI_PIC_REG_IDX];
this appears to be constant 0. I cant find anywhere that sets 
fiq_pending.




here, only NMI can generate fiq,
and I did take care NMI now,
so there's no real case to set fiq.


+uint32_t select[SUNXI_PIC_REG_IDX];
+uint32_t enable[SUNXI_PIC_REG_IDX];
+uint32_t mask[SUNXI_PIC_REG_IDX];
+/*priority setting here*/
+} SunxiPICState;
+
+static void sunxi_pic_update(SunxiPICState *s)
+{
+uint8_t i = 0, j = 0;

Initialisers un-needed.


OK

+bool irq = false;
+
+for (i = 0, j = 0; i<  SUNXI_PIC_REG_IDX; i++) {
+for (j = 0; j<  32; j++) {
+if (!test_bit(j, (void *)&s->mask[i])) {

You can save on a level of indentation here with:

if (test_bit(j, (void *)&s->mask[i])) {
 continue;
}


OK

+if (test_bit(j, (void *)&s->irq_pending[i])) {
+qemu_set_irq(s->parent_irq, 1);

qemu_irq_raise() is simpler.

I can't find anywhere in the code where the interrupts are lowered.
How do they come down, once they are up?






+irq = true;
+}
+if (test_bit(j, (void *)&s->fiq_pending[i])&&
+test_bit(j, (void *)&s->select[i])) {
+qemu_set_irq(s->parent_fiq, 1);
+irq = true;
+}
+if (irq) {
+goto out;

What happens if two interrupts are both active, the first setting IRQ
the second FIQ? Wont this escape logic cause FIQ raising to
potentionally be missed?


+}
+}
+}
+}
+out:
+return;
+}
+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+SunxiPICState *s = opaque;
+
+if (level) {
+set_bit(irq, (void *)&s->irq_pending[irq/32]);

set_bit(irq % 32, ...)



OK


No, it is wrong,
irq/32 is right.




+}

Is this supposed to set either fiq_pending or irq_pending depending on
the select bit?



Yes, but, I as I stated before, maybe I will take NMI later.

+sunxi_pic_update(s);
+}
+
+static uint64_t sunxi_pic_read(void *opaque, hwaddr offset, 
unsigned size)

+{
+SunxiPICState *s = opaque;
+uint8_t index = (offset&  0xc)/4;
+
+switch (offset) {
+case SUNXI_PIC_VECTOR:
+return s->vector;
+break;
+case SUNXI_P

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Igor Mammedov wrote:

On Wed, 27 Nov 2013 08:15:31 +0800
Li Guang  wrote:

   

Igor Mammedov wrote:
 

On Tue, 26 Nov 2013 08:29:27 +0800
Li Guang   wrote:


   

Igor Mammedov wrote:

 

On Fri, 22 Nov 2013 08:57:40 +0800
Li Guangwrote:



   

Michael S. Tsirkin wrote:


 

On Thu, Nov 21, 2013 at 04:32:27PM +0800, Li Guang wrote:



   

Michael S. Tsirkin wrote:



 

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:



   

Hu Tao wrote:



 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:



   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:



 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov



   

The storm is only on memory hotplug right?



 

IIRC, it happens on cpu hotplug, too.






   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.



 

Hmm you are saying let's use EC for memory hotplug?





   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.





 

I'd like to see that. Can you write a document (just text)
for an imaginary EC support for memory hotplug?






   

Hmm..., with EC,

For memory hotplug, at least,
ASL at [PATCH 27/27] can be replaced
by a simple Method(_Qx) under EC device,
IO base operations at [PATCH 15/27]
are dispensable,  we can relay data
by standard operations of EC space

and also for SCI, all device changes want to
notify guest OS can share same SCI with EC,
and the operations are specified at ACPI SPEC.

likewise, for CPU hotplug, pvpanic,
and even debugcon.

and, for odd devices, like pvpanic, guest OS may complain
about it, and we may also have to bother on maintaining state of
it at QEMU, and writing a driver for guest OS,
with EC, functions of device like pvpanic may be implemented silently,
and EC is ACPI standard device, each ACPI compatible OS will
have a driver for it natively.



 

 From what I remember about them EC was adding essentially another
side-channel but more sophisticated for OSPM communication with
platform but for not benefit so far, since what we need from ACPI
for hotplug could be implemented by using GPE handlers without
adding any EC.

I think there was EC patches on list (perhaps yours) but I couldn't
find them. Could you point me to them if they are demonstrating
how hotplug could be done with EC approach.





   

you can find my previous raw patch-set here,
http://lists.gnu.org/archive/html/qemu-devel/2013-05/msg02845.html

 

There you are trying to overcome linux kernel limitation with help of EC
AND additional guest driver to online CPU.
Memory hotplug essentially has the same issue, UDEV is responsible for
onlining hot added ranges. So it's upto userspace policy whether to do
it automatically or not.

   

really?
AFAIK, all hotplug-able  memory can be described at SRAT,
and you can plug and unplug, just need a GPE.
 

Just try it :)
kernel creates entries for hotplugged memory but userspace has to online
it manually, issue doesn't have any relation to SRAT table.

   

But even discarding qemu specific kernel driver, it boils down to using
_Qxx handler vs _Exx one with basically the same ASL code.

So question becomes: Why using EC would be better than using already
present GPE registers for handling event?


   

1. we didn't need to bother IO memory operations,
   because we relay data via EC
 

I guess we will have to write/read EC's IO memory instead,


the premise is supposed EC is implemented already.


serializing data
into byte stream [as in proposed earlier impl.], which will complicate
ACPI interface part of memory hotplug. On QEMU side reader/writer handler might
look different but will implement the same logic as now, EC will not implement
it magically for us.

   


Yes, of course, but, as you can see,  info relay will turn into standard
EC r/w operations.


2. we didn't need to bother GPE handling,
   because EC can do it for us
 

It will do EC handling instead, aren't it?
   

Yes.

Looks like discussion turned into just arguing.
   


:-),  I just answer your questions.


You have on hand this series, would you demonstrate with patches that EC
allows to implement series simpler/better so we could evaluate alternative?

   


I am never going say EC is deemed to be simpler or better,
for me,  it's just flexible.

The mainly approach be demoed at my previous patch-set
for cpu-hotplug.

Thanks!
Li Guang

3. for exten

Re: [Qemu-devel] [PATCH v4 3/4] hw/arm: add sunxi machine type

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Nov 26, 2013 at 5:22 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  hw/arm/Makefile.objs |1 +
  hw/arm/sunxi-soc.c   |   98 ++
  2 files changed, 99 insertions(+), 0 deletions(-)
  create mode 100644 hw/arm/sunxi-soc.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..f9f3071 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o

  obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
  obj-y += omap1.o omap2.o strongarm.o
+obj-y += sunxi-soc.o
diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
new file mode 100644
index 000..b45af6d
--- /dev/null
+++ b/hw/arm/sunxi-soc.c
@@ -0,0 +1,98 @@
+/*
+ * Allwinner sunxi series SoC emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "hw/ptimer.h"
+#include "hw/char/serial.h"
+#include "hw/timer/sunxi-pit.h"
+#include "hw/intc/sunxi-pic.h"
+
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+
+
+#define SUNXI_PIC_REG_BASE 0x01c20400
+#define SUNXI_PIT_REG_BASE 0x01c20c00
+#define SUNXI_UART0_REG_BASE 0x01c28000
+
+static struct arm_boot_info sunxi_binfo = {
+.loader_start = 0x4000,
+.board_id = 0x1008,
+};
+
+static void sunxi_init(QEMUMachineInitArgs *args)
 

I would check with Andreas/PMM on what the go is with SoCs regarding
container devices and boards. My (vague) understanding is that SoCs
should be container devices and boards instantiate those containers
with off-chip connectivity. This seems flat to me, with everything on
board level.

   

well, interesting thought.

IMO, SoC is a board.


+{
+ram_addr_t ram_size = args->ram_size;
+const char *cpu_model = args->cpu_model;
+const char *kernel_filename = args->kernel_filename;
+const char *kernel_cmdline = args->kernel_cmdline;
+ARMCPU *cpu;
+MemoryRegion *address_space_mem = get_system_memory();
+MemoryRegion *ram = g_new(MemoryRegion, 1);
+MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
+qemu_irq pic[95];
 

[SUNXI_PIC_INT_NR]


   

yes, will fix.

Thanks!
Li Guang
   

+DeviceState *dev;
+uint8_t i;
+
+/*here we currently support sunxi-4i*/
+cpu_model = "cortex-a8";
+cpu = cpu_arm_init(cpu_model);
+if (!cpu) {
+fprintf(stderr, "Unable to find CPU definition\n");
+exit(1);
+}
+
+memory_region_init_ram(ram, NULL, "sunxi-soc.ram", ram_size);
+memory_region_add_subregion(address_space_mem, 0, ram);
+memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
+memory_region_add_subregion(address_space_mem, 0x4000, ram_alias);
+
+dev = sysbus_create_varargs(TYPE_SUNXI_PIC, SUNXI_PIC_REG_BASE,
+qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
+qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
+NULL);
+for (i = 0; i<  SUNXI_PIC_INT_NR; i++) {
+pic[i] = qdev_get_gpio_in(dev, i);
+}
+
+sysbus_create_varargs(TYPE_SUNXI_PIT, SUNXI_PIT_REG_BASE, pic[22], pic[23],
+  pic[24], pic[25], pic[67], pic[68], NULL);
+
+serial_mm_init(address_space_mem, SUNXI_UART0_REG_BASE, 2, pic[1], 115200,
+serial_hds[0], DEVICE_NATIVE_ENDIAN);
+
+sunxi_binfo.ram_size = ram_size;
+sunxi_binfo.kernel_filename = kernel_filename;
+sunxi_binfo.kernel_cmdline = kernel_cmdline;
+arm_load_kernel(cpu,&sunxi_binfo);
+}
+
+static QEMUMachine sunxi_machine = {
+.name = "sunxi",
+.desc = "Allwinner's SoC (sunxi series)",
+.init = sunxi_init,
+};
+
+static void sunxi_machine_init(void)
+{
+qemu_register_machine(&sunxi_machine);
+}
+
+machine_init(sunxi_machine_init);
--
1.7.2.5


 
   

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Igor Mammedov wrote:

On Tue, 26 Nov 2013 08:29:27 +0800
Li Guang  wrote:

   

Igor Mammedov wrote:
 

On Fri, 22 Nov 2013 08:57:40 +0800
Li Guang   wrote:


   

Michael S. Tsirkin wrote:

 

On Thu, Nov 21, 2013 at 04:32:27PM +0800, Li Guang wrote:


   

Michael S. Tsirkin wrote:


 

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:


   

Hu Tao wrote:


 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:


   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:


 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov


   

The storm is only on memory hotplug right?


 

IIRC, it happens on cpu hotplug, too.





   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.


 

Hmm you are saying let's use EC for memory hotplug?




   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.




 

I'd like to see that. Can you write a document (just text)
for an imaginary EC support for memory hotplug?





   

Hmm..., with EC,

For memory hotplug, at least,
ASL at [PATCH 27/27] can be replaced
by a simple Method(_Qx) under EC device,
IO base operations at [PATCH 15/27]
are dispensable,  we can relay data
by standard operations of EC space

and also for SCI, all device changes want to
notify guest OS can share same SCI with EC,
and the operations are specified at ACPI SPEC.

likewise, for CPU hotplug, pvpanic,
and even debugcon.

and, for odd devices, like pvpanic, guest OS may complain
about it, and we may also have to bother on maintaining state of
it at QEMU, and writing a driver for guest OS,
with EC, functions of device like pvpanic may be implemented silently,
and EC is ACPI standard device, each ACPI compatible OS will
have a driver for it natively.


 

   From what I remember about them EC was adding essentially another
side-channel but more sophisticated for OSPM communication with
platform but for not benefit so far, since what we need from ACPI
for hotplug could be implemented by using GPE handlers without
adding any EC.

I think there was EC patches on list (perhaps yours) but I couldn't
find them. Could you point me to them if they are demonstrating
how hotplug could be done with EC approach.




   

you can find my previous raw patch-set here,
http://lists.gnu.org/archive/html/qemu-devel/2013-05/msg02845.html
 

There you are trying to overcome linux kernel limitation with help of EC
AND additional guest driver to online CPU.
Memory hotplug essentially has the same issue, UDEV is responsible for
onlining hot added ranges. So it's upto userspace policy whether to do
it automatically or not.
   


really?
AFAIK, all hotplug-able  memory can be described at SRAT,
and you can plug and unplug, just need a GPE.


But even discarding qemu specific kernel driver, it boils down to using
_Qxx handler vs _Exx one with basically the same ASL code.

So question becomes: Why using EC would be better than using already
present GPE registers for handling event?

   

1. we didn't need to bother IO memory operations,
 because we relay data via EC
2. we didn't need to bother GPE handling,
 because EC can do it for us
3. for extension, if need like pvpanic device, can be satisfied
by EC operations easily

Re: [Qemu-devel] [PATCH v4 1/4] hw/timer: add sunxi timer device

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Nov 26, 2013 at 6:59 PM, Li Guang  wrote:
   

Peter Crosthwaite wrote:
 

On Tue, Nov 26, 2013 at 5:22 PM, liguang   wrote:

   

Signed-off-by: liguang
---
   default-configs/arm-softmmu.mak |2 +
   hw/timer/Makefile.objs  |1 +
   hw/timer/sunxi-pit.c|  295
+++
   include/hw/timer/sunxi-pit.h|   37 +
   4 files changed, 335 insertions(+), 0 deletions(-)
   create mode 100644 hw/timer/sunxi-pit.c
   create mode 100644 include/hw/timer/sunxi-pit.h

diff --git a/default-configs/arm-softmmu.mak
b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

   CONFIG_SDHCI=y
   CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
   obj-$(CONFIG_TUSB6010) += tusb6010.o

   obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 000..39b84ab
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,295 @@
+/*
+ * Allwinner sunxi timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify
it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+typedef struct SunxiTimer {
+ptimer_state *timer;
+} SunxiTimer;
+

 

I don't understand the need for this struct. What was wrong with the
direct array of ptimers you had before?

   


because I have to pack timer array into VMSD,
and there's no VMSTATE_PTIMER_ARRAY for ptimer_state.

 

Anyway you can just use VMSTATE_STRUCT_ARRAY on ptimers own VMSD definition?

If you cant, then I think you make a reasonable case for moving the
relevant bits and pieces to headers so they are visible. That or
implement VMSTATE_PTIMER_ARRAY.

   


right, but that seems be in a separated patch,
I consider to use current way, can I?
 
   

+typedef struct SunxiPITState {
+/*<   private>*/
+SysBusDevice parent_obj;
+/*<   public>*/
+qemu_irq irq[SUNXI_TIMER_NR];
+SunxiTimer timer[SUNXI_TIMER_NR];
+MemoryRegion iomem;
+
+uint32_t  irq_enable;
+uint32_t irq_status;
+uint32_t control[SUNXI_TIMER_NR];
+uint32_t interval[SUNXI_TIMER_NR];
+uint32_t count[SUNXI_TIMER_NR];
+uint32_t watch_dog_mode;
+uint32_t watch_dog_control;
+uint32_t count_lo;
+uint32_t count_hi;
+uint32_t count_ctl;
+} SunxiPITState;
+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned
size)
+{
+SunxiPITState *s = SUNXI_PIT(opaque);
+uint8_t index = 0;

 

initializer to 0 un-needed.


   


OK.
 

+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+return s->irq_enable;
+break;
+case SUNXI_TIMER_IRQ_ST:
+return s->irq_status;
+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&   0xf0;

+index>>= 4;
+index -= 1;
+switch (offset&   0x0f) {

+case SUNXI_TIMER_CONTROL:
+return s->control[index];
+break;
+case SUNXI_TIMER_INTERVAL:
+return s->interval[index];
+break;
+case SUNXI_TIMER_COUNT: {
+SunxiTimer *t =&s->timer[index];

+s->count[index] = ptimer_get_count(t->timer);
+return s->count[index];
+}
+default:
+break;
+}
+break;
+case SUNXI_WDOG_CONTROL:
+break;
+case SUNXI_WDOG_MODE:
+break;
+case SUNXI_COUNT_LO:
+return s->count_lo;
+break;
+case SUNXI_COUNT_HI:
+return s->count_hi;
+break;
+case SUNXI_COUNT_CTL:
+return s->count_ctl;
+default:
+break;

 

Usual to do a log_guest error here. Same for writes below.

   


OK.
 


   

+}
+
+return 0;
+}
+
+static void sunxi_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ Sun

Re: [Qemu-devel] [PATCH v4 2/4] hw/intc: add sunxi interrupt controller device

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Nov 26, 2013 at 5:22 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |1 +
  hw/intc/Makefile.objs   |1 +
  hw/intc/sunxi-pic.c |  238 +++
  include/hw/intc/sunxi-pic.h |   20 
  4 files changed, 260 insertions(+), 0 deletions(-)
  create mode 100644 hw/intc/sunxi-pic.c
  create mode 100644 include/hw/intc/sunxi-pic.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7bf5ad0..bbe00e4 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y

  CONFIG_SUNXI_PIT=y
+CONFIG_SUNXI_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..dad8c43 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
  common-obj-$(CONFIG_OPENPIC) += openpic.o
+common-obj-$(CONFIG_SUNXI_PIC) += sunxi-pic.o

  obj-$(CONFIG_APIC) += apic.o apic_common.o
  obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
new file mode 100644
index 000..e84fc55
--- /dev/null
+++ b/hw/intc/sunxi-pic.c
@@ -0,0 +1,238 @@
+/*
+ * Allwinner sunxi interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/sunxi-pic.h"
+
+
+typedef struct SunxiPICState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+MemoryRegion iomem;
+qemu_irq parent_fiq;
+qemu_irq parent_irq;
 

Blank line here for readability.

   


OK

+uint32_t vector;
+uint32_t base_addr;
+uint32_t protect;
+uint32_t nmi;
+uint32_t irq_pending[SUNXI_PIC_REG_IDX];
+uint32_t fiq_pending[SUNXI_PIC_REG_IDX];
 

this appears to be constant 0. I cant find anywhere that sets fiq_pending.

   


here, only NMI can generate fiq,
and I did take care NMI now,
so there's no real case to set fiq.


+uint32_t select[SUNXI_PIC_REG_IDX];
+uint32_t enable[SUNXI_PIC_REG_IDX];
+uint32_t mask[SUNXI_PIC_REG_IDX];
+/*priority setting here*/
+} SunxiPICState;
+
+static void sunxi_pic_update(SunxiPICState *s)
+{
+uint8_t i = 0, j = 0;
 

Initialisers un-needed.

   

OK

+bool irq = false;
+
+for (i = 0, j = 0; i<  SUNXI_PIC_REG_IDX; i++) {
+for (j = 0; j<  32; j++) {
+if (!test_bit(j, (void *)&s->mask[i])) {
 

You can save on a level of indentation here with:

if (test_bit(j, (void *)&s->mask[i])) {
 continue;
}

   

OK

+if (test_bit(j, (void *)&s->irq_pending[i])) {
+qemu_set_irq(s->parent_irq, 1);
 

qemu_irq_raise() is simpler.

I can't find anywhere in the code where the interrupts are lowered.
How do they come down, once they are up?

   





+irq = true;
+}
+if (test_bit(j, (void *)&s->fiq_pending[i])&&
+test_bit(j, (void *)&s->select[i])) {
+qemu_set_irq(s->parent_fiq, 1);
+irq = true;
+}
+if (irq) {
+goto out;
 

What happens if two interrupts are both active, the first setting IRQ
the second FIQ? Wont this escape logic cause FIQ raising to
potentionally be missed?

   

+}
+}
+}
+}
+out:
+return;
+}
+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+SunxiPICState *s = opaque;
+
+if (level) {
+set_bit(irq, (void *)&s->irq_pending[irq/32]);
 

set_bit(irq % 32, ...)

   


OK


+}
 

Is this supposed to set either fiq_pending or irq_pending depending on
the select bit?

   


Yes, but, I as I stated before, maybe I will take NMI later.

+sunxi_pic_update(s);
+}
+
+static uint64_t sunxi_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPICState *s = opaque;
+uint8_t index = (offset&  0xc)/4;
+
+switch (offset) {
+case SUNXI_PIC_VECTOR:
+return s->vector;
+break;
+

Re: [Qemu-devel] [PATCH v4 1/4] hw/timer: add sunxi timer device

[Li Guang]

Peter Crosthwaite wrote:

On Tue, Nov 26, 2013 at 5:22 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |2 +
  hw/timer/Makefile.objs  |1 +
  hw/timer/sunxi-pit.c|  295 +++
  include/hw/timer/sunxi-pit.h|   37 +
  4 files changed, 335 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/sunxi-pit.c
  create mode 100644 include/hw/timer/sunxi-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 000..39b84ab
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,295 @@
+/*
+ * Allwinner sunxi timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+typedef struct SunxiTimer {
+ptimer_state *timer;
+} SunxiTimer;
+
 

I don't understand the need for this struct. What was wrong with the
direct array of ptimers you had before?
   


because I have to pack timer array into VMSD,
and there's no VMSTATE_PTIMER_ARRAY for ptimer_state.

   

+typedef struct SunxiPITState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+qemu_irq irq[SUNXI_TIMER_NR];
+SunxiTimer timer[SUNXI_TIMER_NR];
+MemoryRegion iomem;
+
+uint32_t  irq_enable;
+uint32_t irq_status;
+uint32_t control[SUNXI_TIMER_NR];
+uint32_t interval[SUNXI_TIMER_NR];
+uint32_t count[SUNXI_TIMER_NR];
+uint32_t watch_dog_mode;
+uint32_t watch_dog_control;
+uint32_t count_lo;
+uint32_t count_hi;
+uint32_t count_ctl;
+} SunxiPITState;
+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPITState *s = SUNXI_PIT(opaque);
+uint8_t index = 0;
 

initializer to 0 un-needed.

   


OK.

+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+return s->irq_enable;
+break;
+case SUNXI_TIMER_IRQ_ST:
+return s->irq_status;
+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+return s->control[index];
+break;
+case SUNXI_TIMER_INTERVAL:
+return s->interval[index];
+break;
+case SUNXI_TIMER_COUNT: {
+SunxiTimer *t =&s->timer[index];
+s->count[index] = ptimer_get_count(t->timer);
+return s->count[index];
+}
+default:
+break;
+}
+break;
+case SUNXI_WDOG_CONTROL:
+break;
+case SUNXI_WDOG_MODE:
+break;
+case SUNXI_COUNT_LO:
+return s->count_lo;
+break;
+case SUNXI_COUNT_HI:
+return s->count_hi;
+break;
+case SUNXI_COUNT_CTL:
+return s->count_ctl;
+default:
+break;
 

Usual to do a log_guest error here. Same for writes below.
   


OK.
   

+}
+
+return 0;
+}
+
+static void sunxi_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t index = 0;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case SUNXI_TIMER_IRQ_ST:
+s->irq_status&= value;
 

Are you missing a ~ ? This is a clear-to-clear semantic rather than
write-to-clear.
   


yes

Also shouldn't this de-assert the relevant interrupt lines?

   


there's no related tips in sunxi SoC data-sheet,
and test is fine until now.


+   

Re: [Qemu-devel] [PATCH v3 1/4] hw/timer: add sunxi timer device

[Li Guang]

Peter Crosthwaite wrote:

Hi,

On Mon, Nov 25, 2013 at 5:41 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |2 +
  hw/timer/Makefile.objs  |1 +
  hw/timer/sunxi-pit.c|  260 +++
  include/hw/timer/sunxi-pit.h|   26 
  4 files changed, 289 insertions(+), 0 deletions(-)
  create mode 100644 hw/timer/sunxi-pit.c
  create mode 100644 include/hw/timer/sunxi-pit.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y

  CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
  obj-$(CONFIG_TUSB6010) += tusb6010.o

  obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 000..6220b60
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,260 @@
+/*
+ * Allwinner sunxi timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+typedef struct SunxiPITState {
+SysBusDevice busdev;
 

parent_obj

   

+qemu_irq irq[SUNXI_TIMER_NR];
+ptimer_state *timer[6];
+ptimer_state *counter;
+MemoryRegion iomem;
 

blank line here (to demarcate start of registers) would improve readability.

   

+uint32_t  irq_enable;
+uint32_t irq_status;
+uint32_t control[6];
+uint32_t interval[6];
+uint32_t count[6];
+uint32_t watch_dog_mode;
+uint32_t watch_dog_control;
+uint32_t count_lo;
+uint32_t count_hi;
+uint32_t count_ctl;
+} SunxiPITState;
+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+SunxiPITState *s = SUNXI_PIT(opaque);
+uint8_t index = 0;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+return s->irq_enable;
+break;
+case SUNXI_TIMER_IRQ_ST:
+return s->irq_status;
+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+return s->control[index];
+break;
+case SUNXI_TIMER_INTERVAL:
+return s->interval[index];
+break;
+case SUNXI_TIMER_COUNT:
+s->count[index] = ptimer_get_count(s->timer[index]);
+return s->count[index];
+default:
+break;
+}
+break;
+case SUNXI_WDOG_CONTROL:
+break;
+case SUNXI_WDOG_MODE:
+break;
+case SUNXI_COUNT_LO:
+return s->count_lo;
+break;
+case SUNXI_COUNT_HI:
+return s->count_hi;
+break;
+case SUNXI_COUNT_CTL:
+return s->count_ctl;
+default:
+break;
+}
+
+return 0;
+}
+
+static void sunxi_pit_write(void *opaque, hwaddr offset, uint64_t value,
+unsigned size)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t index = 0;
+
+switch (offset) {
+case SUNXI_TIMER_IRQ_EN:
+s->irq_enable = value;
+break;
+case SUNXI_TIMER_IRQ_ST:
+for (index = 0; index<  32; index++) {
+if (test_bit(index, (void *)&value)) {
+clear_bit(index, (void *)&s->irq_status);
+}
+}
 

s->irq_status&= ~value;

Is probably a simpler and more common way to implement write-to-clear semantic.

   

+break;
+case SUNXI_TIMER_BASE ...  SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+index = offset&  0xf0;
+index>>= 4;
+index -= 1;
+switch (offset&  0x0f) {
+case SUNXI_TIMER_CONTROL:
+s->control[index] = value;
+if (s->control[index]&  0x2) {
+ptimer_set_count(s->timer[index], s->interval[index]);
+}
+if (s-&

Re: [Qemu-devel] [PATCH v3 2/4] hw/intc: add sunxi interrupt controller device

[Li Guang]

Peter Crosthwaite wrote:

On Mon, Nov 25, 2013 at 5:41 PM, liguang  wrote:
   

Signed-off-by: liguang
---
  default-configs/arm-softmmu.mak |1 +
  hw/intc/Makefile.objs   |1 +
  hw/intc/sunxi-pic.c |  301 +++
  include/hw/intc/sunxi-pic.h |   27 
  4 files changed, 330 insertions(+), 0 deletions(-)
  create mode 100644 hw/intc/sunxi-pic.c
  create mode 100644 include/hw/intc/sunxi-pic.h

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7bf5ad0..bbe00e4 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
  CONFIG_INTEGRATOR_DEBUG=y

  CONFIG_SUNXI_PIT=y
+CONFIG_SUNXI_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..dad8c43 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
  common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
  common-obj-$(CONFIG_OPENPIC) += openpic.o
+common-obj-$(CONFIG_SUNXI_PIC) += sunxi-pic.o

  obj-$(CONFIG_APIC) += apic.o apic_common.o
  obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
new file mode 100644
index 000..09a3d09
--- /dev/null
+++ b/hw/intc/sunxi-pic.c
@@ -0,0 +1,301 @@
+/*
+ * Allwinner sunxi interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/sunxi-pic.h"
+
+
+typedef struct SunxiPICState {
+/*<  private>*/
+SysBusDevice parent_obj;
+/*<  public>*/
+MemoryRegion iomem;
+qemu_irq parent_fiq;
+qemu_irq parent_irq;
+uint32_t vector;
+uint32_t base_addr;
+uint32_t protect;
+uint32_t nmi;
+uint32_t irq_pending0;
+uint32_t irq_pending1;
+uint32_t irq_pending2;
+uint32_t select0;
+uint32_t select1;
+uint32_t select2;
+uint32_t enable0;
+uint32_t enable1;
+uint32_t enable2;
+uint32_t mask0;
+uint32_t mask1;
+uint32_t mask2;
+/*priority setting here*/
+} SunxiPICState;
+
+static void sunxi_pic_update(SunxiPICState *s)
+{
+uint32_t flags = 0;
 

initializer to 0 not needed.

   

+
+flags = s->irq_pending0 | s->irq_pending1 | s->irq_pending0;
+qemu_set_irq(s->parent_irq, flags != 0);
+flags&= s->select0 | s->select1 | s->select2;
+qemu_set_irq(s->parent_fiq, flags != 0);
 

This logic seems strange to me, in that that behavior of individual
interrupts is not self contained.

e.g. if interrupt 0 (bit 0 of irq_pending0) is pending and interrupt
32 is selected (bit 0 of select1) then flags is non-zero regardless of
state of bit 0 of s->select0). Whats the intended behavior of the
select bits?

If an interrupt is "selected" it will also route to both IRQ and FIQ it seems.

   

+}
+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+SunxiPICState *s = opaque;
+bool allow_irq = false;
+
+if (level) {
+if (irq<  32) {
+set_bit(irq, (void *)&s->irq_pending0);
+if (test_bit(irq, (void *)&s->enable0)&&
+!test_bit(irq, (void *)&s->mask0)) {
+allow_irq = true;
 

this check inhibits immediate interrupt generation of masked intr, but
it doesnt stop a future event from triggering the IRQ. Should the
enable and mask checks be in the interrupt generation code?

For example, your bus write handler calls sunxi_pic_update() which
means these pending-but-masked interrupts will potentially cause the
irq to raise at bus write time.

   

+}
+} else if (irq<  64) {
+irq -= 32;
+set_bit(irq, (void *)&s->irq_pending1);
+if (test_bit(irq, (void *)&s->enable1)&&
+!test_bit(irq, (void *)&s->mask1)) {
+allow_irq = true;
+}
+} else if (irq<  95) {
+irq -= 64;
+set_bit(irq, (void *)&s->irq_pending2);
+if (test_bit(irq, (void *)&s->enable2)&&
+!test_bit(irq, (void *)&s->mask2)) {
+allow_irq = true;
+}
+

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Igor Mammedov wrote:

On Fri, 22 Nov 2013 08:57:40 +0800
Li Guang  wrote:

   

Michael S. Tsirkin wrote:
 

On Thu, Nov 21, 2013 at 04:32:27PM +0800, Li Guang wrote:

   

Michael S. Tsirkin wrote:

 

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:

   

Hu Tao wrote:

 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:

   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:

 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov

   

The storm is only on memory hotplug right?

 

IIRC, it happens on cpu hotplug, too.




   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.

 

Hmm you are saying let's use EC for memory hotplug?



   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.



 

I'd like to see that. Can you write a document (just text)
for an imaginary EC support for memory hotplug?




   

Hmm..., with EC,

For memory hotplug, at least,
ASL at [PATCH 27/27] can be replaced
by a simple Method(_Qx) under EC device,
IO base operations at [PATCH 15/27]
are dispensable,  we can relay data
by standard operations of EC space

and also for SCI, all device changes want to
notify guest OS can share same SCI with EC,
and the operations are specified at ACPI SPEC.

likewise, for CPU hotplug, pvpanic,
and even debugcon.

and, for odd devices, like pvpanic, guest OS may complain
about it, and we may also have to bother on maintaining state of
it at QEMU, and writing a driver for guest OS,
with EC, functions of device like pvpanic may be implemented silently,
and EC is ACPI standard device, each ACPI compatible OS will
have a driver for it natively.

 

 From what I remember about them EC was adding essentially another
side-channel but more sophisticated for OSPM communication with
platform but for not benefit so far, since what we need from ACPI
for hotplug could be implemented by using GPE handlers without
adding any EC.

I think there was EC patches on list (perhaps yours) but I couldn't
find them. Could you point me to them if they are demonstrating
how hotplug could be done with EC approach.



   

you can find my previous raw patch-set here,
http://lists.gnu.org/archive/html/qemu-devel/2013-05/msg02845.html

Thanks!
Li Guang

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Igor Mammedov wrote:

On Thu, 21 Nov 2013 16:32:27 +0800
Li Guang  wrote:

   

Michael S. Tsirkin wrote:
 

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:

   

Hu Tao wrote:

 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:

   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:

 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov

   

The storm is only on memory hotplug right?

 

IIRC, it happens on cpu hotplug, too.




   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.

 

Hmm you are saying let's use EC for memory hotplug?



   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.

 

Wouldn't it require guest driver though?
Beauty of ASL/GPE it's that it supported by Windows and Linux
out of box.

   


it did require guest driver, but as a ACPI standard device,
the driver is natively implemented by ACPI compatible OS.

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Michael S. Tsirkin wrote:

On Thu, Nov 21, 2013 at 04:32:27PM +0800, Li Guang wrote:
   

Michael S. Tsirkin wrote:
 

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:
   

Hu Tao wrote:
 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:
   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:
 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov
   

The storm is only on memory hotplug right?
 

IIRC, it happens on cpu hotplug, too.



   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.
 

Hmm you are saying let's use EC for memory hotplug?


   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.


 


I'd like to see that. Can you write a document (just text)
for an imaginary EC support for memory hotplug?



   


Hmm..., with EC,

For memory hotplug, at least,
ASL at [PATCH 27/27] can be replaced
by a simple Method(_Qx) under EC device,
IO base operations at [PATCH 15/27]
are dispensable,  we can relay data
by standard operations of EC space

and also for SCI, all device changes want to
notify guest OS can share same SCI with EC,
and the operations are specified at ACPI SPEC.

likewise, for CPU hotplug, pvpanic,
and even debugcon.

and, for odd devices, like pvpanic, guest OS may complain
about it, and we may also have to bother on maintaining state of
it at QEMU, and writing a driver for guest OS,
with EC, functions of device like pvpanic may be implemented silently,
and EC is ACPI standard device, each ACPI compatible OS will
have a driver for it natively.

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Michael S. Tsirkin wrote:

On Thu, Nov 21, 2013 at 04:18:45PM +0800, Li Guang wrote:
   

Hu Tao wrote:
 

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:
   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:
 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov
   

The storm is only on memory hotplug right?
 

IIRC, it happens on cpu hotplug, too.



   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.
 

Hmm you are saying let's use EC for memory hotplug?


   

It can be a bridge between guest and QEMU,
with it, we may don't have to bother ASL writing
and south-bridge hardware related work(or very
little) if we implement EC correctly.

Re: [Qemu-devel] [PATCH 16/27] acpi: ich9: allow guest to clear SCI rised by GPE

[Li Guang]

Hu Tao wrote:

On Thu, Nov 21, 2013 at 09:14:18AM +0200, Michael S. Tsirkin wrote:
   

On Thu, Nov 21, 2013 at 03:38:37AM +0100, Igor Mammedov wrote:
 

it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.

Signed-off-by: Igor Mammedov
   

The storm is only on memory hotplug right?
 

IIRC, it happens on cpu hotplug, too.



   

:-), that made remember EC implementation,
with EC, SCI will be safer, I think.

Re: [Qemu-devel] [PATCH 04/27] vl: convert -m to qemu_opts_parse()

[Li Guang]

Igor Mammedov wrote:

Along with conversion extend -m option to support following parameters
   

...

+if (!opts) {
  exit(1);
  }
-sz = QEMU_ALIGN_UP((uint64_t)value, 8192);
+
+/* fixup legacy sugffix-less format */
   

s/sugffix/suffix


+end = qemu_opt_get(opts, "mem");
+if (g_ascii_isdigit(end[strlen(end) - 1])) {
+s = g_strconcat(end, "M", NULL);
+qemu_opt_set(opts, "mem", s);
+g_free(s);
+}
+
+sz = QEMU_ALIGN_UP(qemu_opt_get_size(opts, "mem", ram_size),
+   8192);
+/* compatibility behaviour for case "-m 0" */
+if (sz == 0) {
+sz = DEFAULT_RAM_SIZE * 1024 * 1024;
+}
+
  ram_size = sz;
  if (ram_size != sz) {
  fprintf(stderr, "qemu: ram size too large\n");
  exit(1);
  }
+/* store aligned value for future use */
+qemu_opt_set_number(opts, "mem", ram_size);
+
+sz = qemu_opt_get_size(opts, "maxmem", ram_size);
+if (sz<  ram_size) {
+qemu_opt_set_number(opts, "maxmem", ram_size);
+}
  break;
  }
  #ifdef CONFIG_TPM
@@ -4029,11 +4083,6 @@ int main(int argc, char **argv, char **envp)
  exit(1);
  }

-/* init the memory */
-if (ram_size == 0) {
-ram_size = DEFAULT_RAM_SIZE * 1024 * 1024;
-}
-
  if (qemu_opts_foreach(qemu_find_opts("device"), device_help_func, NULL, 0)
  != 0) {
  exit(0);
   

Re: [Qemu-devel] [PATCH 21/27] pc: add memory hotplug 440fx machine

[Li Guang]

Hi, Igor

Igor Mammedov wrote:

Add DimmBus for memory hotplug below 4Gb or above 4Gb depending
on initial memory size and hotplug memory size.
   

...

+static
+void pc_hotplug_memory_init_impl(Object *owner,
+ MemoryRegion *system_memory,
+ ram_addr_t low_hotplug_mem_start,
+ ram_addr_t low_hotplug_mem_end,
+ DimmBus *hotplug_mem_bus,
+ ram_addr_t *high_mem_end)
+{
+QemuOpts *opts = qemu_opts_find(qemu_find_opts("memory-opts"), NULL);
+ram_addr_t ram_size = qemu_opt_get_size(opts, "mem", 0);
+ram_addr_t maxmem = qemu_opt_get_size(opts, "maxmem", 0);
+ram_addr_t hotplug_mem_size;
+
+if (maxmem<= ram_size) {
+/* Disable ACPI migration code and creation of memory devices in SSDT 
*/
   


Why not give the memory that not be hot-added a chance to be placed on 
one memory slot?
if all memory can be hot-added and hot-removed, then we can bring in 
more flexibility for

memory hotplug feature.

Thanks!


+qemu_opt_set_number(opts, "slots", 0);
+return;
+}
+
+hotplug_mem_size = maxmem - ram_size;
+if (hotplug_mem_size<= (low_hotplug_mem_end - low_hotplug_mem_start)) {
+hotplug_mem_bus->base = low_hotplug_mem_start;
+} else {
+hotplug_mem_bus->base = ROUND_UP(*high_mem_end, 1ULL<<  30);
+*high_mem_end = hotplug_mem_bus->base + hotplug_mem_size;
+}
+
   

...

Re: [Qemu-devel] [PATCH 0/4] add sunxi machine

[Li Guang]

Hi, Peter

Peter Maydell wrote:

On 20 November 2013 07:53, liguang  wrote:
   

this patch-set implemented a device-reduced
machine type for Allwinner's sunxi series SoC,
like sunxi-4i/5i/7i ...
 
   

Li Guang (4)
  hw/arm: add new machine type sunxi
  hw/arm/sunxi-soc: add interrupt controller
  hw/arm/sunxi-soc: add sunxi timer
  hw/arm/sunxi-soc: really initialize sunxi machine
 

Hi. Thanks for this patch set. I see you've put all the code
into one file in hw/arm, but we prefer each device model
to go in its own file in the right subdirectory of hw/. So
you put the interrupt controller under hw/intc/, the
timer under hw/timer/, and only the top level board model
lives under hw/arm. If you could restructure the
patches this way that would be great.

You'll also need to add VMState descriptions to your
devices so they can be migrated.

   

OK, let me split it into 3 files, and try to add VMstate.

Thanks!

Re: [Qemu-devel] Prohibit Windows from running in QEMU

[Li Guang]

Michael S. Tsirkin wrote:

On Tue, Oct 29, 2013 at 10:48:07AM +0100, Peter Lieven wrote:
   

Hi all,

this question might seem a bit weird, but does anyone see a good way to avoid
that Windows is able to boot inside qemu?

We have defined several profiles for different operation systems and I want
to avoid that someone chooses Linux and then installs Windows within
a VM. Reason is licensing.

Thanks,
Peter
 

- create a device
- write a linux driver
- if driver is not enabled crash guest

   

another option:
_OSI() in ACPI, for ACPI compatible cases.

Re: [Qemu-devel] [PATCH] exec: avoid tcg_commit when kvm_enabled

[Li Guang]

在 2013-09-04三的 08:23 +0200，Paolo Bonzini写道：
> Il 04/09/2013 03:07, Li Guang ha scritto:
> > 在 2013-09-03二的 10:39 +0200，Andreas Färber写道：
> >> Am 03.09.2013 08:59, schrieb liguang:
> >>> Signed-off-by: liguang 
> >>> ---
> >>>  exec.c |4 +++-
> >>>  1 files changed, 3 insertions(+), 1 deletions(-)
> >>>
> >>> diff --git a/exec.c b/exec.c
> >>> index 3ca9381..4509daa 100644
> >>> --- a/exec.c
> >>> +++ b/exec.c
> >>> @@ -1824,7 +1824,9 @@ static void memory_map_init(void)
> >>>  address_space_init(&address_space_io, system_io, "I/O");
> >>>  
> >>>  memory_listener_register(&core_memory_listener, 
> >>> &address_space_memory);
> >>> -memory_listener_register(&tcg_memory_listener, 
> >>> &address_space_memory);
> >>> +if (!kvm_enabled()) {
> >>
> >> if (tcg_enabled())? I'm guessing Xen and QTest don't need it either?
> >>
> > 
> > can't assure that currently, 
> > anybody can help to assure whether Xen & QTest need tcg_commit?
> 

OK, Thanks!

> 
> >>
> >>> +memory_listener_register(&tcg_memory_listener, 
> >>> &address_space_memory);
> >>> +}
> >>>  }
> >>>  
> >>>  MemoryRegion *get_system_memory(void)
> >>
> > 
> 

Re: [Qemu-devel] [Qemu-trivial] [PATCH] cputlb: remove dead function tlb_update_dirty

[Li Guang]

在 2013-09-03二的 18:54 +0200，Andreas Färber写道：
> Am 03.09.2013 13:17, schrieb Michael Tokarev:
> > 03.09.2013 12:35, Andreas Färber wrote:
> >> I also don't understand why qemu-trivial is suddenly picking up Stefan's
> >> arm translation patch, it used to be for unmaintained areas only. But
> >> arm is not my problem.
> > 
> > Which patch you're talking about?  Is it "target-arm: Report unimplemented
> > opcodes (LOG_UNIMP)" ?
> 
> Yes.
> 
> >  If yes, that one appears to be trivial as it just
> > adds some logging before failing an instruction and should not conflict
> > with other work being done in this area.  Perhaps I was too aggressive
> > while picking up the backlog.  We should just draw the line *somewhere*, --
> 
> Right, that line is what I'm reminding about here. I feel that lately an
> increasing number of contributors and reviewers are deferring patches to
> qemu-trivial that don't really belong there IMO. That Anthony doesn't
> scale to cover Blue's maintainer work as well shouldn't lead to a surge
> on qemu-trivial.
> 
> > eg, it sure is possible to reject spelling fixes for maintained areas
> > from -trivial (like this arm tree), - will this be productive?
> 
> No, spelling fixes are not a concern to me as they are rather unlikely
> to cause conflicts with patches being queued by submaintainers. :)
> 
> > This change (cputlb: remove dead function) appears to be "trivial enough"
> > for me (after looking at the usage history of this function), and I'd
> > pick it up without this Andreas's request, too.
> 
> Yes. This one here would've been okay usually, as there is no official
> maintainer for cputlb.c and it's trivial in the sense that a git-grep
> confirms it to be okay. I was just annoyed that I had to defer my pull
> twice (sent it out now) because s390x added two CPU loops and then once
> that was merged ppc added another loop, too. My upcoming 35+ patch
> series qom-cpu-13 may hopefully explain the rest once you see it.
> 
> > As for the "suddenly" - it's not really suddenly, it's because it
> > has been Cc'd to -trivial (by someone who submitted lots of good
> > trivial patches before) and actually looks trivial, too.  And also
> > because subsystem maintainer added his Reviewed-by, apparently (or
> > hopefully) after noticing it's submitted to -trivial.  I also Cc'd
> > both maintainers in my notice that it's been applied to -trivial.
> 
> "Suddenly" in the sense that the prupose of qemu-trivial used to be
> handling patches that would otherwise fall through the cracks.
> 
> So by my understanding, e.g., "target-arm:" => !trivial, and I would've
> expected there to be some on-list communication between PMM and you
> before CC'ing someone on a "thanks, applied" after the fact.
> By contrast, if there's a change to configure or "Fix spelling of" etc.
> then you picking it up is highly appreciated. I just don't want
> qemu-trivial becoming the least-resistance way of getting patches into
> qemu.git that might otherwise get bounced/changed by submaintainers.
> 
> Also, I am seeing Paolo pull in huge memory changes but now pinging the
> breakage fixes rather than assembling a pull to fix the fallout. ;)
> 
> Similarly target-i386 TCG is not suited for qemu-trivial IMO, instead
> rth or someone who works on and/or reviews it (rth?) should volunteer as
> proper maintainer. 

 I'd like to maintain cputlb.c, can I?

> With the larger part of the community using KVM these
> days, we simply can't have that be handled by the community at large any
> more.
> 
> So yes, I know you were on vacation and you seem eager to take up work
> again, that's great; I'm just cautioning that CC'ing everything on
> qemu-trivial (not your fault, you're on the receiving end) can't be the
> new solution, so feel encouraged to push back a little. :)
> 
> Cheers,
> Andreas
> 

-- 
Thanks!

Li Guang

Re: [Qemu-devel] [PATCH] exec: avoid tcg_commit when kvm_enabled

[Li Guang]

在 2013-09-03二的 10:39 +0200，Andreas Färber写道：
> Am 03.09.2013 08:59, schrieb liguang:
> > Signed-off-by: liguang 
> > ---
> >  exec.c |4 +++-
> >  1 files changed, 3 insertions(+), 1 deletions(-)
> > 
> > diff --git a/exec.c b/exec.c
> > index 3ca9381..4509daa 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -1824,7 +1824,9 @@ static void memory_map_init(void)
> >  address_space_init(&address_space_io, system_io, "I/O");
> >  
> >  memory_listener_register(&core_memory_listener, &address_space_memory);
> > -memory_listener_register(&tcg_memory_listener, &address_space_memory);
> > +if (!kvm_enabled()) {
> 
> if (tcg_enabled())? I'm guessing Xen and QTest don't need it either?
> 

can't assure that currently, 
anybody can help to assure whether Xen & QTest need tcg_commit?

> 
> > +memory_listener_register(&tcg_memory_listener, 
> > &address_space_memory);
> > +}
> >  }
> >  
> >  MemoryRegion *get_system_memory(void)
> 

-- 
Thanks!

Li Guang

Re: [Qemu-devel] [PATCH v2 1/2] tcg/mips: detect available host instructions at runtime

[li guang]

Hi, Aurelien,

to nitpick, 
use_mips32r2_instructions may already indicate
use_mips32_instructions,right?
so during ISA detection, we may first do mips32r2, then mips32
detection is unnecessary, I think.


在 2013-08-28三的 00:11 +0200，Aurelien Jarno写道：
> Now that TCG supports enabling and disabling ops at runtime, it's
> possible to detect the available host instructions at runtime, and
> enable the corresponding ops accordingly.
> 
> Unfortunately it's not easy to probe for available instructions on
> MIPS, the information is partially available in /proc/cpuinfo, and
> not available in AUXV. This patch therefore probes for the instructions
> by trying to execute them and by catching a possible SIGILL signal.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  tcg/mips/tcg-target.c |  211 
> -
>  tcg/mips/tcg-target.h |   50 +++-
>  2 files changed, 169 insertions(+), 92 deletions(-)
> 
> diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
> index 793532e..a994b11 100644
> --- a/tcg/mips/tcg-target.c
> +++ b/tcg/mips/tcg-target.c
> @@ -422,83 +422,83 @@ static inline void tcg_out_movi(TCGContext *s, TCGType 
> type,
>  
>  static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
>  {
> -#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
> -tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> -#else
> -/* ret and arg can't be register at */
> -if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
> -tcg_abort();
> -}
> +if (use_mips32r2_instructions) {
> +tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> +} else {
> +/* ret and arg can't be register at */
> +if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
> +tcg_abort();
> +}
>  
> -tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
> -tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
> -tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
> -tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> -#endif
> +tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
> +tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
> +tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
> +tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> +}
>  }
>  
>  static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
>  {
> -#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
> -tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> -tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
> -#else
> -/* ret and arg can't be register at */
> -if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
> -tcg_abort();
> -}
> +if (use_mips32r2_instructions) {
> +tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> +tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
> +} else {
> +/* ret and arg can't be register at */
> +if (ret == TCG_REG_AT || arg == TCG_REG_AT) {
> +tcg_abort();
> +}
>  
> -tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
> -tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
> -tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
> -tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> -#endif
> +tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
> +tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
> +tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
> +tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> +}
>  }
>  
>  static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
>  {
> -#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
> -tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> -tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
> -#else
> -/* ret and arg must be different and can't be register at */
> -if (ret == arg || ret == TCG_REG_AT || arg == TCG_REG_AT) {
> -tcg_abort();
> -}
> +if (use_mips32r2_instructions) {
> +tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> +tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
> +} else {
> +/* ret and arg must be different and can't be register at */
> +if (ret == arg || ret == TCG_REG_AT || arg == TCG_REG_AT) {
> +tcg_abort();
> +}
>  
> -tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
> +tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
>  
> -tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 24);
> -tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> +tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 24);
> +tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
>  
> -tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_AT, arg, 0xff00);
> -tcg_out_opc_sa(s, OPC_SLL, TCG_REG_AT, TCG_REG_AT, 8);
> -tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
> +tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_AT, arg, 0xff00);
> +tcg_out_opc_sa(s, OPC_SLL, TCG_REG_AT, TCG_REG_AT, 8);
> +tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT);
>  
> -tcg_out_opc_sa(s, OPC_SRL, TCG_REG_AT, arg, 8);
> -tcg_out_opc_imm(s, OPC_ANDI, TCG_

Re: [Qemu-devel] [PATCH] i386: Use #defines instead of magic numbers for CPUID cache information

[li guang]

在 2013-08-26一的 19:23 -0300，Eduardo Habkost写道：
> This is an attempt to make the CPUID cache topology code clearer, by
> replacing the magic numbers in the code with #defines, and moving all
> the cache information to the same place in the file.
> 
> I took care of comparing the assembly output of compiling
> target-i386/cpu.c before and after applying this change, to make sure
> not a single bit was changed on cpu_x86_cpuid() before and after
> applying this patch (unfortunately I had to manually check existing
> differences, because of __LINE__ expansions on
> object_class_dynamic_cast_assert() calls).
> 
> This even keeps the code bug-compatible with the previous version: today
> the cache information returned on AMD cache information leaves (CPUID
> 0x8005 & 0x8006) do not match the information returned on CPUID
> leaves 2 and 4. The L2 cache information on CPUID leaf 2 also doesn't
> match the information on CPUID leaf 2. The new constants should make it
> easier to eventually fix those inconsistencies. All inconsistencies I
> have found are documented in code comments.
> 
> Signed-off-by: Eduardo Habkost 
> ---
>  target-i386/cpu.c | 184 
> +++---
>  1 file changed, 162 insertions(+), 22 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 6e38252..478923b 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -48,6 +48,118 @@
>  #include "hw/i386/apic_internal.h"
>  #endif
>  
> +
> +/* Cache topology CPUID constants: */
> +
> +/* CPUID Leaf 2 Descriptors */
> +
> +#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
> +#define CPUID_2_L1I_32KB_8WAY_64B 0x30
> +#define CPUID_2_L2_2MB_8WAY_64B   0x7d
> +
> +
> +/* CPUID Leaf 4 constants: */
> +
> +/* EAX: */
> +#define CPUID_4_TYPE_DCACHE  1
> +#define CPUID_4_TYPE_ICACHE  2
> +#define CPUID_4_TYPE_UNIFIED 3
> +
> +#define CPUID_4_LEVEL(l)  ((l) << 5)
> +
> +#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
> +#define CPUID_4_FULLY_ASSOC (1 << 9)
> +
> +/* EDX: */
> +#define CPUID_4_NO_INVD_SHARING (1 << 0)
> +#define CPUID_4_INCLUSIVE   (1 << 1)
> +#define CPUID_4_COMPLEX_IDX (1 << 2)
> +
> +#define ASSOC_FULL 0xFF
> +
> +/* AMD associativity encoding used on CPUID Leaf 0x8006: */
> +#define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
> +  a ==   2 ? 0x2 : \
> +  a ==   4 ? 0x4 : \
> +  a ==   8 ? 0x6 : \
> +  a ==  16 ? 0x8 : \
> +  a ==  32 ? 0xA : \
> +  a ==  48 ? 0xB : \
> +  a ==  64 ? 0xC : \
> +  a ==  96 ? 0xD : \
> +  a == 128 ? 0xE : \
> +  a == ASSOC_FULL ? 0xF : \
> +  0 /* invalid value */)
> +
> +
> +/* Definitions of the hardcoded cache entries we expose: */
> +
> +/* L1 data cache: */
> +#define L1D_LINE_SIZE 64
> +#define L1D_ASSOCIATIVITY  8
> +#define L1D_SETS  64
> +#define L1D_PARTITIONS 1
> +/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
> +#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
> +/*FIXME: CPUID leaf 0x8005 is inconsistent with leafs 2 & 4 */

s/leafs/leaves, and following 2,
with these fixed, 
Reviewed-by: liguang 

Thanks!

> +#define L1D_LINES_PER_TAG  1
> +#define L1D_SIZE_KB_AMD   64
> +#define L1D_ASSOCIATIVITY_AMD  2
> +
> +/* L1 instruction cache: */
> +#define L1I_LINE_SIZE 64
> +#define L1I_ASSOCIATIVITY  8
> +#define L1I_SETS  64
> +#define L1I_PARTITIONS 1
> +/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
> +#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
> +/*FIXME: CPUID leaf 0x8005 is inconsistent with leafs 2 & 4 */
> +#define L1I_LINES_PER_TAG  1
> +#define L1I_SIZE_KB_AMD   64
> +#define L1I_ASSOCIATIVITY_AMD  2
> +
> +/* Level 2 unified cache: */
> +#define L2_LINE_SIZE  64
> +#define L2_ASSOCIATIVITY  16
> +#define L2_SETS 4096
> +#define L2_PARTITIONS  1
> +/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
> +/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
> +#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
> +/*FIXME: CPUID leaf 0x8006 is inconsistent with leafs 2 & 4 */
> +#define L2_LINES_PER_TAG   1
> +#define L2_SIZE_KB_AMD   512
> +
> +/* No L3 cache: */
> +#define L3_SIZE_KB 0 /* disabled */
> +#define L3_ASSOCIATIVITY   0 /* disabled */
> +#define L3_LINES_PER_TAG   0 /* disabled */
> +#define L3_LINE_SIZE   0 /* disabled */
> +
> +/* TLB definitions: */
> +
> +#define L1_DTLB_2M_ASSOC   1
> +#define L1_DTLB_2M_ENTRIES   255
> +#define L1_DTLB_4K_ASSOC   1
> +#define L1_DTLB_4K_ENTRIES   255
> +
> +#define L1_ITLB_2M_ASSOC   1
> +#define L1_ITLB_2M_ENTRIES   255
> +#define L1_ITLB_4K_ASSOC   1
> +#define L1_ITLB_4K_ENTR

Re: [Qemu-devel] [Qemu-trivial] [PATCH v2 3/5] qemu-char: use bool in qemu_chr_open_socket

[li guang]

在 2013-06-19三的 12:28 +0400，Michael Tokarev写道：
> 18.06.2013 07:45, liguang wrote:
> > local variables is_* should be bool by usage,
> > and last parameter of qemu_opt_get_bool is bool,
> > so pass true/false for it.
> > 
> > Signed-off-by: liguang 
> > ---
> >  qemu-char.c |   20 ++--
> >  1 files changed, 10 insertions(+), 10 deletions(-)
> > 
> > diff --git a/qemu-char.c b/qemu-char.c
> > index 2c3cfe6..0d695e0 100644
> > --- a/qemu-char.c
> > +++ b/qemu-char.c
> > @@ -2679,16 +2679,16 @@ static CharDriverState 
> > *qemu_chr_open_socket(QemuOpts *opts)
> >  CharDriverState *chr = NULL;
> >  Error *local_err = NULL;
> >  int fd = -1;
> > -int is_listen;
> > -int is_waitconnect;
> > -int do_nodelay;
> > -int is_unix;
> > -int is_telnet;
> > -
> > -is_listen  = qemu_opt_get_bool(opts, "server", 0);
> > -is_waitconnect = qemu_opt_get_bool(opts, "wait", 1);
> > -is_telnet  = qemu_opt_get_bool(opts, "telnet", 0);
> > -do_nodelay = !qemu_opt_get_bool(opts, "delay", 1);
> > +bool is_listen;
> > +bool is_waitconnect;
> > +bool do_nodelay;
> > +bool is_unix;
> > +bool is_telnet;
> > +
> > +is_listen  = qemu_opt_get_bool(opts, "server", false);
> > +is_waitconnect = qemu_opt_get_bool(opts, "wait", true);
> > +is_telnet  = qemu_opt_get_bool(opts, "telnet", false);
> > +do_nodelay = !qemu_opt_get_bool(opts, "delay", true);
> >  is_unix= qemu_opt_get(opts, "path") != NULL;
> >  if (!is_listen)
> >  is_waitconnect = 0;
> 
> So is is_waitconnect a booleand or integer? :)

Oh, I'm so lazy to find more...
following is fine for me.

Thanks!

> 
> How about this (I'm unsure about the author anymore ):
> 
> commit c5b775f85f5049d7315b8f8643a65ea1cc7107eb
> Author: liguang 
> Date:   Tue Jun 18 11:45:35 2013 +0800
> 
> qemu-char: use bool in qemu_chr_open_socket and simplify code a bit
> 
> Local variables is_* should be bool by usage.
> While at it, simplify the logic/code a bit.
> 
> Signed-off-by: liguang 
> Signed-off-by: Michael Tokarev 
> 
> diff --git a/qemu-char.c b/qemu-char.c
> index 2c3cfe6..a030e6b 100644
> --- a/qemu-char.c
> +++ b/qemu-char.c
> @@ -2679,19 +2679,12 @@ static CharDriverState *qemu_chr_open_socket(QemuOpts 
> *opts)
>  CharDriverState *chr = NULL;
>  Error *local_err = NULL;
>  int fd = -1;
> -int is_listen;
> -int is_waitconnect;
> -int do_nodelay;
> -int is_unix;
> -int is_telnet;
> -
> -is_listen  = qemu_opt_get_bool(opts, "server", 0);
> -is_waitconnect = qemu_opt_get_bool(opts, "wait", 1);
> -is_telnet  = qemu_opt_get_bool(opts, "telnet", 0);
> -do_nodelay = !qemu_opt_get_bool(opts, "delay", 1);
> -is_unix= qemu_opt_get(opts, "path") != NULL;
> -if (!is_listen)
> -is_waitconnect = 0;
> +
> +bool is_listen  = qemu_opt_get_bool(opts, "server", false);
> +bool is_waitconnect = is_listen && qemu_opt_get_bool(opts, "wait", true);
> +bool is_telnet  = qemu_opt_get_bool(opts, "telnet", false);
> +bool do_nodelay = !qemu_opt_get_bool(opts, "delay", true);
> +bool is_unix= qemu_opt_get(opts, "path") != NULL;
> 
>  if (is_unix) {
>  if (is_listen) {
> 

Re: [Qemu-devel] [PATCH RFC v2 0/7] coordinate cpu hotplug/unplug bewteen QEMU and kernel by EC

[li guang]

在 2013-06-18二的 11:14 +0200，Igor Mammedov写道：
> On Tue, 18 Jun 2013 10:47:15 +0800
> li guang  wrote:
> 
> > Hi, Igor and Micheal
> > 
> > 在 2013-06-06四的 16:33 +0800，li guang写道：
> > > 在 2013-06-06四的 11:13 +0300，Michael S. Tsirkin写道：
> > > > On Thu, Jun 06, 2013 at 11:16:53AM +0800, liguang wrote:
> > > > > v2: 
> > > > > 1.remove PIIX4_PROC_BASE operations for cpu hotplug
> > > > > 2.fix wrong description fo cpu-del
> > > > > 
> > > > > patch 1 adds ACPI Embedded Controller (EC),
> > > > > refer-to:
> > > > > ACPI SPEC v5 chapter 12
> > > > > "ACPI Embedded Controller Interface Specification"
> > > > > 
> > > > > EC is a standard ACPI device, it plays flexible roles,
> > > > > especially be event carrier, it can pass events between platform
> > > > > and OS, so OS can execute _Qxx method which defined
> > > > > by yourself and query EC's ACPI space which can be a buffer for
> > > > > many purposes
> > > > > 
> > > > > here, I want to deliver CPU online/offline event between
> > > > > OS and QEMU for CPU hotplug feature, then we will don't
> > > > > need to "echo 1 > /sys/devices/system/cpu/cpu1/online"
> > > > > again after 'cpu-add' and also for offline to do real cpu
> > > > > removal.
> > > > 
> > > > So, it's another channel to the guest.
> > > > Can't qemu-ga do this in userspace, using the existing channel?
> > > 
> > > Sorry, I'm not familiar with qemu-ga,
> > > anyway, maybe we don't want to do things like
> > > 'exec("echo 1 > /sys/devices/system/cpu/cpu1/online")'
> > > in userspace.
> > > 
> > > BTW, Michael,
> > > do you think if we use EC space to pass info between
> > > platform(QEMU) and OS(PM) instead of 'PIIX4_PROC_BASE' and
> > > something like it can bring some convenience?
> > > for we can directly operate on EC space, we don't have to
> > > register memory regions and ops for them any more, and also,
> > > these regions are mostly not exist in real platforms,
> > > this a motivation that I add this device.
> > > 
> > 
> > does this approach have some benefit?
> 
> Replacing CPUs bitmap with a select window as it's done in this series
> could be done in PIIX4 in similar manner and would be much simpler
> than introducing whole new device. 

Cool! but I can't figure out the way to do that now,
could you tell me a little details about this manner?

and also, as I stated before, this device is not only can be used
in our cpu hotplug case, it can also be used in many other cases
like pvpanic, by it, we can do pvpanic like things without introducing
pvpanic like devices, isn't it an important advantage?



> That however would require introducing
> locking in bios's ACPI code to avoid concurrent handler execution which
> is not needed in case of bitmap.
> 

Sorry, did not consider the lock, but for real platform, we also
didn't do lock for this operation, so why it's required here?

> > 
> > > > 
> > > > > what I am trying to do is emulated physical addition/removal
> > > > > (like described by linux kernel document for cpu hotplug --
> > > > > linux-2.6/Documentation/cpu-hotplug.txt) for QEMU.
> > > > > 
> > > > > these RFC patches are sent for demo what I am trying to do.
> > > > > 
> > > > > the design process simply like following:
> > > > > 
> > > > > hotplug
> > > > > qemu::ec::sci -> kernel::ec::gpe::notifier->
> > > > > kernel::cpu_physic_hotplug::handler->kernel::cpu_up
> > > > > 
> > > > > unplug
> > > > > kernel::cpu_down::kernel::cpu_physic_hotplug::handler->
> > > > > kernel::ec::ec_write->qemu::ec::->qemu::cpu-unplug
> > > > > 
> > > > > sorry, I should poll cpu-unplug cmd sent from kernel,
> > > > > but, it's a little trivial, I want do it later.
> > > > > 
> > > > > for kernel patches:
> > > > > http://comments.gmane.org/gmane.linux.kernel/1503460
> > > > > 
> > > > > 
> > > > > Li Guang (8)
> > > > >acpi: add ACPI Embedded Controller support
> > > > > 

Re: [Qemu-devel] [Qemu-trivial] [PATCH 4/5] memory: use '=' instead of '|=' for memory_region_update_pending

[li guang]

在 2013-06-18二的 07:50 +0400，Michael Tokarev写道：
> 18.06.2013 06:32, li guang пишет:
> > 在 2013-06-11二的 15:34 +0400，Michael Tokarev写道：
> >> 11.06.2013 09:15, liguang wrote:
> >>> because memory_region_update_pending is bool
> >>>
> >>> Signed-off-by: liguang 
> >>> ---
> >>>  memory.c |   18 +-
> >>>  1 files changed, 9 insertions(+), 9 deletions(-)
> >>>
> >>> diff --git a/memory.c b/memory.c
> >>> index 5cb8f4a..d99eecd 100644
> >>> --- a/memory.c
> >>> +++ b/memory.c
> >>> @@ -1114,7 +1114,7 @@ void memory_region_set_log(MemoryRegion *mr, bool 
> >>> log, unsigned client)
> >>>  
> >>>  memory_region_transaction_begin();
> >>>  mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
> >>> -memory_region_update_pending |= mr->enabled;
> >>> +memory_region_update_pending = mr->enabled;
> >>
> >> This is wrong, and the original code was right.  Here and in all other 
> >> places.
> > 
> > Is it valid to do '|' operation for boolean?
> 
> Yes it is.  Why do you think it might be problematic?
> 

No problem now,

Thanks!

Re: [Qemu-devel] [PATCH RFC v2 0/7] coordinate cpu hotplug/unplug bewteen QEMU and kernel by EC

[li guang]

Hi, Igor and Micheal

在 2013-06-06四的 16:33 +0800，li guang写道：
> 在 2013-06-06四的 11:13 +0300，Michael S. Tsirkin写道：
> > On Thu, Jun 06, 2013 at 11:16:53AM +0800, liguang wrote:
> > > v2: 
> > > 1.remove PIIX4_PROC_BASE operations for cpu hotplug
> > > 2.fix wrong description fo cpu-del
> > > 
> > > patch 1 adds ACPI Embedded Controller (EC),
> > > refer-to:
> > > ACPI SPEC v5 chapter 12
> > > "ACPI Embedded Controller Interface Specification"
> > > 
> > > EC is a standard ACPI device, it plays flexible roles,
> > > especially be event carrier, it can pass events between platform
> > > and OS, so OS can execute _Qxx method which defined
> > > by yourself and query EC's ACPI space which can be a buffer for
> > > many purposes
> > > 
> > > here, I want to deliver CPU online/offline event between
> > > OS and QEMU for CPU hotplug feature, then we will don't
> > > need to "echo 1 > /sys/devices/system/cpu/cpu1/online"
> > > again after 'cpu-add' and also for offline to do real cpu
> > > removal.
> > 
> > So, it's another channel to the guest.
> > Can't qemu-ga do this in userspace, using the existing channel?
> 
> Sorry, I'm not familiar with qemu-ga,
> anyway, maybe we don't want to do things like
> 'exec("echo 1 > /sys/devices/system/cpu/cpu1/online")'
> in userspace.
> 
> BTW, Michael,
> do you think if we use EC space to pass info between
> platform(QEMU) and OS(PM) instead of 'PIIX4_PROC_BASE' and
> something like it can bring some convenience?
> for we can directly operate on EC space, we don't have to
> register memory regions and ops for them any more, and also,
> these regions are mostly not exist in real platforms,
> this a motivation that I add this device.
> 

does this approach have some benefit?

> > 
> > > what I am trying to do is emulated physical addition/removal
> > > (like described by linux kernel document for cpu hotplug --
> > > linux-2.6/Documentation/cpu-hotplug.txt) for QEMU.
> > > 
> > > these RFC patches are sent for demo what I am trying to do.
> > > 
> > > the design process simply like following:
> > > 
> > > hotplug
> > > qemu::ec::sci -> kernel::ec::gpe::notifier->
> > > kernel::cpu_physic_hotplug::handler->kernel::cpu_up
> > > 
> > > unplug
> > > kernel::cpu_down::kernel::cpu_physic_hotplug::handler->
> > > kernel::ec::ec_write->qemu::ec::->qemu::cpu-unplug
> > > 
> > > sorry, I should poll cpu-unplug cmd sent from kernel,
> > > but, it's a little trivial, I want do it later.
> > > 
> > > for kernel patches:
> > > http://comments.gmane.org/gmane.linux.kernel/1503460
> > > 
> > > 
> > > Li Guang (8)
> > >acpi: add ACPI Embedded Controller support
> > >ich9: add notifer for ec to generate sci
> > >ec: add operations for _Qxx events
> > >piix4: add notifer for ec to generate sci
> > >piix4: add events for cpu hotplug
> > >qmp: add 'cpu-del' command
> > >pc: add EC qdev init for piix & q35
> > >cpu-hotplug: remove memory regison for cpu hotplug
> > > 
> > > default-configs/x86_64-softmmu.mak |   1 +
> > > hw/acpi/Makefile.objs  |   1 +
> > > hw/acpi/ec.c   | 225 
> > > 
> > > hw/acpi/ich9.c |  15 +++
> > > hw/acpi/piix4.c|  68 ++
> > > hw/i386/pc.c   |  46 --
> > > hw/i386/pc_piix.c  |   7 +
> > > hw/i386/pc_q35.c   |   6 +
> > > include/hw/acpi/ec.h   |  44 ++
> > > include/hw/acpi/ich9.h |   1 +
> > > include/hw/boards.h|   5 +++--
> > > include/hw/i386/pc.h   |   1 +
> > > qapi-schema.json   |  13 +
> > > qmp-commands.hx|  23 +++
> > > qmp.c  |   9 +
> > > 15 files changed, 411 insertions(+), 54 deletions(-)
> > >  create mode 100644 hw/acpi/ec.c
> > >  create mode 100644 include/hw/acpi/ec.h
> 
> 
> 

Re: [Qemu-devel] [Qemu-trivial] [PATCH 1/5] vnc: pass bool pararmeter for vnc_connect

[li guang]

在 2013-06-18二的 06:35 +0400，Michael Tokarev写道：
> 11.06.2013 15:50, Michael Tokarev wrote:
> > 11.06.2013 09:15, liguang wrote:
> >> type last parameter of vnc_connect if bool,
> >> so pass 'false' instead of '0' for it.
> > 
> > There's another parameter in here, `skipauth', which should be
> > bool in vnc_connect(), and should be bool in vnc_display_add_client()
> > too.
> > 
> > Also, there's no big point in splitting 1/5 and 2/5 (vnc_listen_read),
> > I think.
> > 
> > Does something like the below look ok? (not even compile-tested)
> > (and I'd really rename `skipauth' to `doauth' everywhere, to mean
> > exactly the opposite so that we don't have double negatives, but
> > it is too late already)
> 
> Hello.
> 
> Do you want/plan to respin the series, addressing comments?
> Are you okay with my version?
> 

Yes, I'm little busy now, but I'll re-spin as soon as possible.

Re: [Qemu-devel] [Qemu-trivial] [PATCH 1/5] vnc: pass bool pararmeter for vnc_connect

[li guang]

在 2013-06-11二的 15:50 +0400，Michael Tokarev写道：
> 11.06.2013 09:15, liguang wrote:
> > type last parameter of vnc_connect if bool,
> > so pass 'false' instead of '0' for it.
> 
> There's another parameter in here, `skipauth', which should be
> bool in vnc_connect(), and should be bool in vnc_display_add_client()
> too.
> 
> Also, there's no big point in splitting 1/5 and 2/5 (vnc_listen_read),
> I think.
> 
> Does something like the below look ok? (not even compile-tested)

OK for me.

> (and I'd really rename `skipauth' to `doauth' everywhere, to mean
> exactly the opposite so that we don't have double negatives, but
> it is too late already)
> 
> From: Michael Tokarev 
> Date:   Tue Jun 11 15:42:44 2013 +0400
> 
> vnc: use booleans for vnc_connect, vnc_listen_read and 
> vnc_display_add_client
> 
> Some arguments to these functions are booleans - either by declaration,
> or by actual usage, but sometimes value of 0 or 1 is passed for a bool,
> and sometimes it is declared as int but a bool value, or true/false,
> is passed to it instead.  Clean it up a bit.
> 
> Cc: liguang 
> Signed-off-by: Michael Tokarev 
> 
> diff --git a/include/ui/console.h b/include/ui/console.h
> index f1d79f9..98edf41 100644
> --- a/include/ui/console.h
> +++ b/include/ui/console.h
> @@ -314,7 +314,7 @@ void cocoa_display_init(DisplayState *ds, int 
> full_screen);
>  /* vnc.c */
>  void vnc_display_init(DisplayState *ds);
>  void vnc_display_open(DisplayState *ds, const char *display, Error **errp);
> -void vnc_display_add_client(DisplayState *ds, int csock, int skipauth);
> +void vnc_display_add_client(DisplayState *ds, int csock, bool skipauth);
>  char *vnc_display_local_addr(DisplayState *ds);
>  #ifdef CONFIG_VNC
>  int vnc_display_password(DisplayState *ds, const char *password);
> diff --git a/ui/vnc.c b/ui/vnc.c
> index dfc7459..5601cc3 100644
> --- a/ui/vnc.c
> +++ b/ui/vnc.c
> @@ -2771,7 +2771,8 @@ static void vnc_refresh(DisplayChangeListener *dcl)
>  }
>  }
> 
> -static void vnc_connect(VncDisplay *vd, int csock, int skipauth, bool 
> websocket)
> +static void vnc_connect(VncDisplay *vd, int csock,
> +bool skipauth, bool websocket)
>  {
>  VncState *vs = g_malloc0(sizeof(VncState));
>  int i;
> @@ -2883,19 +2884,19 @@ static void vnc_listen_read(void *opaque, bool 
> websocket)
>  }
> 
>  if (csock != -1) {
> -vnc_connect(vs, csock, 0, websocket);
> +vnc_connect(vs, csock, false, websocket);
>  }
>  }
> 
>  static void vnc_listen_regular_read(void *opaque)
>  {
> -vnc_listen_read(opaque, 0);
> +vnc_listen_read(opaque, false);
>  }
> 
>  #ifdef CONFIG_VNC_WS
>  static void vnc_listen_websocket_read(void *opaque)
>  {
> -vnc_listen_read(opaque, 1);
> +vnc_listen_read(opaque, true);
>  }
>  #endif /* CONFIG_VNC_WS */
> 
> @@ -3283,7 +3284,7 @@ void vnc_display_open(DisplayState *ds, const char 
> *display, Error **errp)
>  if (csock < 0) {
>  goto fail;
>  }
> -vnc_connect(vs, csock, 0, 0);
> +vnc_connect(vs, csock, false, false);
>  } else {
>  /* listen for connects */
>  char *dpy;
> @@ -3341,9 +3342,9 @@ fail:
>  #endif /* CONFIG_VNC_WS */
>  }
> 
> -void vnc_display_add_client(DisplayState *ds, int csock, int skipauth)
> +void vnc_display_add_client(DisplayState *ds, int csock, bool skipauth)
>  {
>  VncDisplay *vs = vnc_display;
> 
> -vnc_connect(vs, csock, skipauth, 0);
> +vnc_connect(vs, csock, skipauth, false);
>  }
> 
>