Tap adapter and whpx accelerator in Windows host makes network issues
Dear Support team, I am facing an issue with running Qemu guest running in Windows host and here the details: - Windows 10 host - hyper-v is enabled - openvpn tap-windows v9 adapter is installed and network interface is named to QEMU_TAP -Qemu 8.1.0 is installed While running in cmd terminal: qemu-system-x86_64 -accel whpx -m 2G -cdrom image.iso -netdev tap,ifname=QEMU_TAP,id=net0 -device e1000,netdev=net0 I am facing an issue and I cannot ping the Qemu guest from windows host but I remove the accelerator everything is working fine. Can you please let me know is there any way to make the accelerator whpx and tap adapter working together? Thank you in advance for your support. Best regards, Mohamed Amine
[PATCH 3/8] tiva c gpio implementation
Signed-off-by: Mohamed ElSayed
---
hw/gpio/tm4c123_gpio.c | 372 +
hw/gpio/trace-events | 4 +
include/hw/gpio/tm4c123_gpio.h | 127 +++
3 files changed, 503 insertions(+)
create mode 100644 hw/gpio/tm4c123_gpio.c
create mode 100644 include/hw/gpio/tm4c123_gpio.h
diff --git a/hw/gpio/tm4c123_gpio.c b/hw/gpio/tm4c123_gpio.c
new file mode 100644
index 00..9a27e0664e
--- /dev/null
+++ b/hw/gpio/tm4c123_gpio.c
@@ -0,0 +1,372 @@
+/*
+ * TM4C123 GPIO
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/gpio/tm4c123_gpio.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/tm4c123_sysctl.h"
+#include "qemu/bitops.h"
+#include "trace.h"
+
+#define LOG(mask, fmt, args...) qemu_log_mask(mask, "%s: " fmt, __func__, ##
args)
+#define READONLY LOG(LOG_GUEST_ERROR, "0x%"HWADDR_PRIx" is a readonly
field\n.", addr)
+
+static bool gpio_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch(addr) {
+case GPIO_A:
+return test_bit(0, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_B:
+return test_bit(1, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_C:
+return test_bit(2, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_D:
+return test_bit(3, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_E:
+return test_bit(4, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_F:
+return test_bit(5, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+}
+return false;
+}
+
+static void tm4c123_gpio_reset(DeviceState *dev)
+{
+TM4C123GPIOState *s = TM4C123_GPIO(dev);
+
+s->gpio_data = 0x;
+s->gpio_dir = 0x;
+s->gpio_is = 0x;
+s->gpio_ibe = 0x;
+s->gpio_iev = 0x;
+s->gpio_im = 0x;
+s->gpio_ris = 0x;
+s->gpio_mis = 0x;
+s->gpio_icr = 0x;
+s->gpio_afsel = 0x;
+s->gpio_dr2r = 0x00FF;
+s->gpio_dr4r = 0x;
+s->gpio_dr8r = 0x;
+s->gpio_odr = 0x;
+s->gpio_pur = 0x;
+s->gpio_pdr = 0x;
+s->gpio_slr = 0x;
+s->gpio_den = 0x;
+s->gpio_lock = 0x0001;
+s->gpio_ocr = 0x;
+s->gpio_amsel = 0x;
+s->gpio_pctl = 0x;
+s->gpio_adcctl = 0x;
+s->gpio_dmactl = 0x;
+s->gpio_per_id4 = 0x;
+s->gpio_per_id5 = 0x;
+s->gpio_per_id6 = 0x;
+s->gpio_per_id7 = 0x;
+s->gpio_per_id0 = 0x0061;
+s->gpio_per_id1 = 0x;
+s->gpio_per_id2 = 0x0018;
+s->gpio_per_id3 = 0x0001;
+s->gpio_pcell_id0 = 0x000D;
+s->gpio_pcell_id1 = 0x00F0;
+s->gpio_pcell_id2 = 0x0005;
+s->gpio_pcell_id3 = 0x00B1;
+}
+
+static void tm4c123_gpio_write(void *opaque, hwaddr addr, uint64_t val64,
unsigned int size)
+{
+TM4C123GPIOState *s = opaque;
+uint32_t val32 = val64;
+
+if (!gpio_clock_enabled(s->sysctl, s->mmio.addr)) {
+hw_error("GPIO module clock is not enabled");
+}
+trace_tm4c123_gpio_write(addr, val32);
+
+switch(addr) {
+case GPIO_DATA:
+{
+uint32_t rising_edge = (val32 ^ s->gpio_data) & val32;
+//level detection
+s->gpio_mis = s->gpio_is & s->gpio_iev & val32;
[PATCH 8/8] adding tiva c to the qemu build system and adding my info to the maintainers list
Signed-off-by: Mohamed ElSayed
---
MAINTAINERS | 9 +
configs/devices/arm-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 3 +++
hw/char/Kconfig | 3 +++
hw/char/meson.build | 1 +
hw/gpio/Kconfig | 3 +++
hw/gpio/meson.build | 1 +
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 1 +
hw/timer/Kconfig| 3 +++
hw/timer/meson.build| 1 +
hw/watchdog/Kconfig | 3 +++
hw/watchdog/meson.build | 1 +
14 files changed, 46 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b22b85bc3a..dcd902fadf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1008,6 +1008,15 @@ F: include/hw/misc/zynq_slcr.h
F: include/hw/adc/zynq-xadc.h
X: hw/ssi/xilinx_*
+Tiva C
+M: Mohamed ElSayed
+L: qemu-...@nongnu.org
+S: Maintained
+F: hw/*/tm4c123*
+F: include/hw/*/tm4c123*
+F: hw/arm/tivac.c
+F: docs/system/arm/tivac.rst
+
Xilinx ZynqMP and Versal
M: Alistair Francis
M: Edgar E. Iglesias
diff --git a/configs/devices/arm-softmmu/default.mak
b/configs/devices/arm-softmmu/default.mak
index 1b49a7830c..d3490f6d11 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -43,3 +43,4 @@ CONFIG_FSL_IMX6UL=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
+CONFIG_TIVAC=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b53bd7f0b2..ef8046ab1b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -581,3 +581,16 @@ config ARMSSE
select UNIMP
select SSE_COUNTER
select SSE_TIMER
+
+config TM4C123GH6PM_SOC
+bool
+select ARM_V7M
+select TM4C123_USART
+select TM4C123_SYSCTL
+select TM4C123_GPIO
+select TM4C123_WDT
+select TM4C123_GPTM
+
+config TIVAC
+bool
+select TM4C123GH6PM_SOC
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index b545ba0e4f..29503388a5 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -62,10 +62,13 @@ arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true:
files('fsl-imx7.c', 'mcimx7d-sabre.
arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c',
'mcimx6ul-evk.c'))
arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
+arm_ss.add(when: 'CONFIG_TM4C123GH6PM_SOC', if_true:
files('tm4c123gh6pm_soc.c'))
+arm_ss.add(when: 'CONFIG_TIVAC', if_true: files('tivac.c'))
softmmu_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
softmmu_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
+
hw_arch += {'arm': arm_ss}
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 6b6cf2fc1d..88da979b75 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -71,3 +71,6 @@ config GOLDFISH_TTY
config SHAKTI_UART
bool
+
+config TM4C123_USART
+bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 0807e00ae4..8461748c8d 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -33,6 +33,7 @@ softmmu_ss.add(when: 'CONFIG_SH_SCI', if_true:
files('sh_serial.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true:
files('stm32f2xx_usart.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true:
files('mchp_pfsoc_mmuart.c'))
softmmu_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
+softmmu_ss.add(when: 'CONFIG_TM4C123_USART', if_true: files('tm4c123_usart.c'))
softmmu_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'))
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index d2cf3accc8..1b843d669a 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -16,3 +16,6 @@ config GPIO_PWR
config SIFIVE_GPIO
bool
+
+config TM4C123_GPIO
+bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index b726e6d27a..b253e8ce67 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -12,3 +12,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true:
files('omap_gpio.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_TM4C123_GPIO', if_true: files('tm4c123_gpio.c'))
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 2ef5781ef8..c8be9ae285 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -180,4 +180,7 @@ config AXP209_PMU
bool
depends on I2C
+config TM4C123_SYSCTL
+bool
+
source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc
[PATCH 4/8] tiva c sysctl implementation
Signed-off-by: Mohamed ElSayed
---
hw/misc/tm4c123_sysctl.c | 989 +++
hw/misc/trace-events | 5 +
include/hw/misc/tm4c123_sysctl.h | 307 ++
3 files changed, 1301 insertions(+)
create mode 100644 hw/misc/tm4c123_sysctl.c
create mode 100644 include/hw/misc/tm4c123_sysctl.h
diff --git a/hw/misc/tm4c123_sysctl.c b/hw/misc/tm4c123_sysctl.c
new file mode 100644
index 00..c996609fc7
--- /dev/null
+++ b/hw/misc/tm4c123_sysctl.c
@@ -0,0 +1,989 @@
+/*
+ * TM4C123 SYSCTL
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/tm4c123_sysctl.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "trace.h"
+
+#define LOG(mask, fmt, args...) qemu_log_mask(mask, "%s: " fmt, __func__, ##
args)
+#define READONLY LOG(LOG_GUEST_ERROR, "0x%"HWADDR_PRIx" is a readonly
field\n.", addr)
+
+static void tm4c123_sysctl_update_system_clock(void *opaque)
+{
+TM4C123SysCtlState *s = opaque;
+
+uint32_t RCC_Val = s->sysctl_rcc;
+uint32_t RCC2_Val = s->sysctl_rcc2;
+
+uint32_t __CORE_CLK_PRE;
+uint32_t __CORE_CLK;
+
+if (RCC2_Val & (1UL << 31)) { /* is rcc2 used? */
+if (RCC2_Val & (1UL << 11)) { /* check BYPASS */
+if (((RCC2_Val >> 4) & 0x07) == 0x0) {
+if (((RCC_Val >> 6) & 0x1F) == 0x0) {
+__CORE_CLK_PRE = 100UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x1) {
+__CORE_CLK_PRE = 1843200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x2) {
+__CORE_CLK_PRE = 200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x3) {
+__CORE_CLK_PRE = 2457600UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x4) {
+__CORE_CLK_PRE = 3579545UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x5) {
+__CORE_CLK_PRE = 3686400UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x6) {
+__CORE_CLK_PRE = 400UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x7) {
+__CORE_CLK_PRE = 4096000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x8) {
+__CORE_CLK_PRE = 4915200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x9) {
+__CORE_CLK_PRE = 500UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xA) {
+__CORE_CLK_PRE = 512UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xB) {
+__CORE_CLK_PRE = 600UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xC) {
+__CORE_CLK_PRE = 6144000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xD) {
+__CORE_CLK_PRE = 7372800UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xE) {
+__CORE_CLK_PRE = 800UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xF) {
+__CORE_CLK_PRE = 8192000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x10) {
+__CORE_CLK_PRE = 1000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x11) {
+__CORE_CLK_PRE = 1200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x12) {
+__CORE_CLK_PRE = 12288000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x13) {
+__CORE_CLK_PRE = 1356UL;
+} else if
[PATCH 7/8] tiva c board documentation
Signed-off-by: Mohamed ElSayed --- docs/system/arm/tivac.rst | 47 +++ 1 file changed, 47 insertions(+) create mode 100644 docs/system/arm/tivac.rst diff --git a/docs/system/arm/tivac.rst b/docs/system/arm/tivac.rst new file mode 100644 index 00..8e78726c01 --- /dev/null +++ b/docs/system/arm/tivac.rst @@ -0,0 +1,47 @@ +Texas Instruments EK-TM4C123GXL Evaluation Board, ``Tiva C`` + + +The `Tiva C`_ board is an evaluation platform for ARM Cortex-M4-based microcontrollers. +Its based on the `TM4C123GH6PM`_ microcontroller by Texas Instruments. + +.. _Tiva C: https://www.ti.com/tool/EK-TM4C123GXL +.. _TM4C123GH6PM: https://www.ti.com/product/TM4C123GH6PM + +Supported modules +- + + * ARM Cortex-M4 + * General Purpose Input/Output (GPIO) + * General Purpose Timers (GPTM) + * Serial Ports (USART) + * System Control (SYSCTL) + * Watchdog Timers (WDT) + +Missing modules +--- + + * Dynamic Memory Access (uDMA) + * Analog to Digital Converter (ADC) + * Synchronous Serial Interface (SSI) + * Inter-Integrated Circuit Interface (I2C) + * Controller Area Network (CAN) + * USB Controller + * Analog Comparators + * Pulse Width Modulator (PWM) + * Quadrature Encoder Interface (QEI) + +Boot options + + +The Tiva C machines could be started using the ``-kernel`` option to load a binary file. + +.. code-block:: bash + + $ qemu-system-arm -M tivac -kernel binary.elf -s -S + +The ``-s -S`` switches are for debugging, in another terminal window you can do: + +.. code-block:: bash + + $ arm-none-eabi-gdb binary.elf + (gdb) target remote :1234 -- 2.34.1
[PATCH 6/8] tiva c general purpose timers implementation
Signed-off-by: Mohamed ElSayed
---
hw/timer/tm4c123_gptm.c | 495
hw/timer/trace-events | 5 +
include/hw/timer/tm4c123_gptm.h | 131 +
3 files changed, 631 insertions(+)
create mode 100644 hw/timer/tm4c123_gptm.c
create mode 100644 include/hw/timer/tm4c123_gptm.h
diff --git a/hw/timer/tm4c123_gptm.c b/hw/timer/tm4c123_gptm.c
new file mode 100644
index 00..bdbaff776c
--- /dev/null
+++ b/hw/timer/tm4c123_gptm.c
@@ -0,0 +1,495 @@
+/*
+ * TM4C123 General purpose timers
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/timer/tm4c123_gptm.h"
+#include "hw/irq.h"
+#include "trace.h"
+#include "qemu/timer.h"
+#include
+
+#define LOG(mask, fmt, args...) qemu_log_mask(mask, "%s: " fmt, __func__, ##
args)
+#define READONLY LOG(LOG_GUEST_ERROR, "0x%"HWADDR_PRIx" is a readonly
field\n.", addr)
+
+static uint64_t ns_to_ticks(void *opaque, uint64_t ns, uint32_t prescaler)
+{
+TM4C123GPTMState *s = opaque;
+
+uint32_t freq = clock_get_hz(s->clk) / prescaler;
+float sec = (float)ns / (float)NANOSECONDS_PER_SECOND;
+return sec * freq;
+}
+
+static unsigned long ticks_to_time_ns(void *opaque, uint64_t ticks, uint32_t
prescaler)
+{
+TM4C123GPTMState *s = opaque;
+uint32_t freq = clock_get_hz(s->clk) / prescaler;
+return ((float)ticks / (float)freq) * NANOSECONDS_PER_SECOND;
+}
+
+static uint16_t get_timer_width(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+switch (s->mmio.addr) {
+case TIMER0_32...TIMER5_32:
+return TIMER_WIDTH_32;
+case TIMER0_64...TIMER5_64:
+return TIMER_WIDTH_64;
+}
+return 0;
+}
+
+static uint64_t build_interval_value(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+uint16_t timer_width = get_timer_width(s);
+uint64_t interval_value = 0;
+if (timer_width == TIMER_WIDTH_32) {
+/* timer is in 32 bit mode or 32bit rtc*/
+uint16_t upper16 = extract32(s->gptm_talir, 16, 16);
+uint16_t lower16 = extract32(s->gptm_tblir, 0, 16);
+interval_value = ((uint32_t)lower16 << 16) + upper16;
+} else if (timer_width == TIMER_WIDTH_64) {
+interval_value = ((uint64_t)s->gptm_talir << 32) + s->gptm_tblir;
+}
+
+trace_tm4c123_gptm_build_interval_value(s->gptm_talir, s->gptm_tblir,
interval_value);
+return interval_value;
+}
+
+static void set_timers(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+uint64_t interval_value;
+uint16_t timer_width;
+if (s->gptm_ctl & GPTM_TACTL_EN) {
+timer_width = get_timer_width(s);
+if (timer_width == TIMER_WIDTH_32) {
+/* What is the mode of the timer? 16/32 */
+if (s->gptm_cfg == 0x4) {
+/* 16 bit mode */
+interval_value = extract32(s->gptm_talir, 0, 16);
+/* Start the timer? */
+timer_mod(s->a, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
ticks_to_time_ns(s, interval_value, s->gptm_tapr));
+} else if (s->gptm_cfg == 0x1) {
+/* 32 bit mode rtc */
+interval_value = build_interval_value(s);
+timer_mod(s->a, qemu_clock_get_ns(QEMU_CLOCK_REALTIME) +
ticks_to_time_ns(s, interval_value, s->gptm_tapr));
+} else if (s->gptm_cfg == 0x0) {
+/* 32 bit mode rtc */
+interval_value = build_interval_value(s);
+timer_mod(s->a, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
ticks_to_time_ns(s, interval_value, s->gptm_tapr));
+}
+} else if (timer_width == TIMER_WIDTH_64) {
+/* What is the mode of the timer? 32/64 */
+if (s->gptm_cfg ==
[PATCH 2/8] tiva c usart module implementation
Signed-off-by: Mohamed ElSayed
---
hw/char/tm4c123_usart.c | 381
hw/char/trace-events| 4 +
include/hw/char/tm4c123_usart.h | 124 +++
3 files changed, 509 insertions(+)
create mode 100644 hw/char/tm4c123_usart.c
create mode 100644 include/hw/char/tm4c123_usart.h
diff --git a/hw/char/tm4c123_usart.c b/hw/char/tm4c123_usart.c
new file mode 100644
index 00..21bfe781b0
--- /dev/null
+++ b/hw/char/tm4c123_usart.c
@@ -0,0 +1,381 @@
+/*
+ * TM4C123 USART
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/tm4c123_usart.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "trace.h"
+
+#define LOG(mask, fmt, args...) qemu_log_mask(mask, "%s: " fmt, __func__, ##
args)
+#define READONLY LOG(LOG_GUEST_ERROR, "0x%"HWADDR_PRIx" is a readonly
field\n.", addr)
+
+static bool usart_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch (addr) {
+case USART_0:
+return s->sysctl_rcgcuart & (1 << 0);
+break;
+case USART_1:
+return s->sysctl_rcgcuart & (1 << 1);
+break;
+case USART_2:
+return s->sysctl_rcgcuart & (1 << 2);
+break;
+case USART_3:
+return s->sysctl_rcgcuart & (1 << 3);
+break;
+case USART_4:
+return s->sysctl_rcgcuart & (1 << 4);
+break;
+case USART_5:
+return s->sysctl_rcgcuart & (1 << 5);
+break;
+case USART_6:
+return s->sysctl_rcgcuart & (1 << 6);
+break;
+case USART_7:
+return s->sysctl_rcgcuart & (1 << 7);
+break;
+}
+return false;
+}
+
+
+static int tm4c123_usart_can_receive(void *opaque)
+{
+TM4C123USARTState *s = opaque;
+
+if (!(s->usart_fr & USART_FR_RXFF)) {
+return 1;
+}
+return 0;
+}
+
+static void tm4c123_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+TM4C123USARTState *s = opaque;
+
+if (!(s->usart_ctl & USART_CR_EN && s->usart_ctl & USART_CR_RXE)) {
+LOG(LOG_GUEST_ERROR, "The module is not enbled\n");
+return;
+}
+
+s->usart_dr = *buf;
+s->usart_ctl &= ~USART_FR_RXFE;
+
+if (s->usart_im & USART_IM_RXIM) {
+qemu_set_irq(s->irq, 1);
+}
+}
+
+static void tm4c123_usart_reset(DeviceState *dev)
+{
+TM4C123USARTState *s = TM4C123_USART(dev);
+
+s->usart_dr = 0x;
+s->usart_rsr = 0x;
+s->usart_fr = 0x0090;
+s->usart_ilpr = 0x;
+s->usart_ibrd = 0x;
+s->usart_fbrd = 0x;
+s->usart_lcrh = 0x;
+s->usart_ctl = 0x0300;
+s->usart_ifls = 0x0012;
+s->usart_im = 0x;
+s->usart_ris = 0x;
+s->usart_mis = 0x;
+s->usart_icr = 0x;
+s->usart_dma_ctl = 0x;
+s->usart_9bit_addr = 0x;
+s->usart_9bit_mask = 0x00FF;
+s->usart_pp = 0x0003;
+s->usart_cc = 0x;
+s->usart_per_id4 = 0x;
+s->usart_per_id5 = 0x;
+s->usart_per_id6 = 0x;
+s->usart_per_id7 = 0x;
+s->usart_per_id0 = 0x0060;
+s->usart_per_id1 = 0x;
+s->usart_per_id2 = 0x0018;
+s->usart_per_id3 = 0x0001;
+s->usart_pcell_id0 = 0x000D;
+s->
[PATCH 1/8] The tivac board initial machine definition
Signed-off-by: Mohamed ElSayed
---
hw/arm/tivac.c| 56 ++
hw/arm/tm4c123gh6pm_soc.c | 275 ++
include/hw/arm/tm4c123gh6pm_soc.h | 71
3 files changed, 402 insertions(+)
create mode 100644 hw/arm/tivac.c
create mode 100644 hw/arm/tm4c123gh6pm_soc.c
create mode 100644 include/hw/arm/tm4c123gh6pm_soc.h
diff --git a/hw/arm/tivac.c b/hw/arm/tivac.c
new file mode 100644
index 00..5d917a8f9e
--- /dev/null
+++ b/hw/arm/tivac.c
@@ -0,0 +1,56 @@
+/*
+ * TivaC Board Implementation
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "qemu/error-report.h"
+#include "hw/arm/tm4c123gh6pm_soc.h"
+#include "hw/arm/boot.h"
+
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 2400ULL
+
+static void tivac_init(MachineState *machine)
+{
+DeviceState *dev;
+dev = qdev_new(TYPE_TM4C123GH6PM_SOC);
+
+qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
+
+armv7m_load_kernel(ARM_CPU(first_cpu),
+machine->kernel_filename,
+0, FLASH_SIZE);
+}
+
+static void tivac_machine_init(MachineClass *mc)
+{
+mc->desc = "Tiva C (Cortex-M4)";
+mc->init = tivac_init;
+}
+DEFINE_MACHINE("tivac", tivac_machine_init)
diff --git a/hw/arm/tm4c123gh6pm_soc.c b/hw/arm/tm4c123gh6pm_soc.c
new file mode 100644
index 00..3e61911bba
--- /dev/null
+++ b/hw/arm/tm4c123gh6pm_soc.c
@@ -0,0 +1,275 @@
+/*
+ * TM4C123GH6PM SoC
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/tm4c123gh6pm_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+static const uint32_t gpio_addrs[GPIO_COUNT] = {
+0x40004000,
+0x40005000,
+0x40006000,
+0x40007000,
+0x40024000,
+0x40025000
+};
+
+static const uint32_t usart_addrs[USART_COUNT] = {
+0x4000C000,
+0x4000D000,
+0x4000E000,
+0x4000F000,
+0x4001,
+0x40011000,
+0x40012000,
+0x40013000
+};
+
+static const uint32_t wdt_addrs[WDT_COUNT] = {
+0x4000,
+0x40001000
+};
+
+static const uint32_t gptm_addrs[GPTM_COUNT] = {
+0x4003,
+0x40031000,
+
[PATCH 0/8] Tiva C Implementation
This contribution aims to add the Tiva C support into QEMU. The code could be found at https://github.com/moesay/qemu_TivaC Mohamed ElSayed (8): The tivac board initial machine definition tiva c usart module implementation tiva c gpio implementation tiva c sysctl implementation tiva c watchdog timers implementation tiva c general purpose timers implementation tiva c board documentation adding tiva c to the qemu build system and adding my info to the maintainers list MAINTAINERS | 9 + configs/devices/arm-softmmu/default.mak | 1 + docs/system/arm/tivac.rst | 47 ++ hw/arm/Kconfig | 13 + hw/arm/meson.build | 3 + hw/arm/tivac.c | 56 ++ hw/arm/tm4c123gh6pm_soc.c | 275 +++ hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/tm4c123_usart.c | 381 + hw/char/trace-events| 4 + hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/tm4c123_gpio.c | 372 + hw/gpio/trace-events| 4 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/tm4c123_sysctl.c| 989 hw/misc/trace-events| 5 + hw/timer/Kconfig| 3 + hw/timer/meson.build| 1 + hw/timer/tm4c123_gptm.c | 495 hw/timer/trace-events | 5 + hw/watchdog/Kconfig | 3 + hw/watchdog/meson.build | 1 + hw/watchdog/tm4c123_watchdog.c | 297 +++ hw/watchdog/trace-events| 3 + include/hw/arm/tm4c123gh6pm_soc.h | 71 ++ include/hw/char/tm4c123_usart.h | 124 +++ include/hw/gpio/tm4c123_gpio.h | 127 +++ include/hw/misc/tm4c123_sysctl.h| 307 include/hw/timer/tm4c123_gptm.h | 131 include/hw/watchdog/tm4c123_watchdog.h | 97 +++ 33 files changed, 3836 insertions(+) create mode 100644 docs/system/arm/tivac.rst create mode 100644 hw/arm/tivac.c create mode 100644 hw/arm/tm4c123gh6pm_soc.c create mode 100644 hw/char/tm4c123_usart.c create mode 100644 hw/gpio/tm4c123_gpio.c create mode 100644 hw/misc/tm4c123_sysctl.c create mode 100644 hw/timer/tm4c123_gptm.c create mode 100644 hw/watchdog/tm4c123_watchdog.c create mode 100644 include/hw/arm/tm4c123gh6pm_soc.h create mode 100644 include/hw/char/tm4c123_usart.h create mode 100644 include/hw/gpio/tm4c123_gpio.h create mode 100644 include/hw/misc/tm4c123_sysctl.h create mode 100644 include/hw/timer/tm4c123_gptm.h create mode 100644 include/hw/watchdog/tm4c123_watchdog.h -- 2.34.1
[PATCH 5/8] tiva c watchdog timers implementation
Signed-off-by: Mohamed ElSayed
---
hw/watchdog/tm4c123_watchdog.c | 297 +
hw/watchdog/trace-events | 3 +
include/hw/watchdog/tm4c123_watchdog.h | 97
3 files changed, 397 insertions(+)
create mode 100644 hw/watchdog/tm4c123_watchdog.c
create mode 100644 include/hw/watchdog/tm4c123_watchdog.h
diff --git a/hw/watchdog/tm4c123_watchdog.c b/hw/watchdog/tm4c123_watchdog.c
new file mode 100644
index 00..ea0a41f3c0
--- /dev/null
+++ b/hw/watchdog/tm4c123_watchdog.c
@@ -0,0 +1,297 @@
+/*
+ * TM4C123 Watchdog Timers
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/watchdog/tm4c123_watchdog.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/nmi.h"
+#include "trace.h"
+
+#define LOG(mask, fmt, args...) qemu_log_mask(mask, "%s: " fmt, __func__, ##
args)
+#define READONLY LOG(LOG_GUEST_ERROR, "0x%"HWADDR_PRIx" is a readonly
field\n.", addr)
+
+static bool locked;
+
+static void tm4c123_wdt_expired(void *opaque)
+{
+TM4C123WatchdogState *s = opaque;
+/*if this is the first timeout/the ris is not cleared */
+if (!test_bit(0, (const unsigned long *)>wdt_mis)) {
+set_bit(0, (unsigned long *)>wdt_mis);
+nmi_monitor_handle(0, NULL);
+qemu_irq_pulse(s->irq);
+} else {
+if (test_bit(1, (const unsigned long *)>wdt_ctl))
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+else {
+nmi_monitor_handle(0, NULL);
+qemu_irq_pulse(s->irq);
+}
+}
+}
+
+static bool wdt_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch (addr) {
+case WDT_0:
+return s->sysctl_rcgcwd & (1 << 0);
+break;
+case WDT_1:
+return s->sysctl_rcgcwd & (1 << 1);
+break;
+}
+return false;
+}
+
+static void tm4c123_wdt_reset(DeviceState *dev)
+{
+TM4C123WatchdogState *s = TM4C123_WATCHDOG(dev);
+
+s->wdt_load = 0x;
+s->wdt_value = 0x;
+s->wdt_ctl = (s->mmio.addr == WDT_0 ? 0x : 0x8000);
+s->wdt_icr = 0x;
+s->wdt_ris = 0x;
+s->wdt_mis = 0x;
+s->wdt_test = 0x;
+s->wdt_lock = 0x;
+s->wdt_per_id4 = 0x;
+s->wdt_per_id5 = 0x;
+s->wdt_per_id6 = 0x;
+s->wdt_per_id7 = 0x;
+s->wdt_per_id0 = 0x0005;
+s->wdt_per_id1 = 0x0018;
+s->wdt_per_id2 = 0x0018;
+s->wdt_per_id3 = 0x0001;
+s->wdt_pcell_id0 = 0x000D;
+s->wdt_pcell_id1 = 0x00F0;
+s->wdt_pcell_id2 = 0x0006;
+s->wdt_pcell_id3 = 0x00B1;
+}
+
+static uint64_t tm4c123_wdt_read(void *opaque, hwaddr addr, unsigned int size)
+{
+TM4C123WatchdogState *s = opaque;
+
+if (!wdt_clock_enabled(s->sysctl, s->mmio.addr)) {
+hw_error("Watchdog timer module clock is not enabled");
+}
+
+switch (addr) {
+case WDT_LOAD:
+return s->wdt_load;
+case WDT_VALUE:
+return ptimer_get_count(s->timer);
+case WDT_CTL:
+return s->wdt_ctl;
+case WDT_ICR:
+return s->wdt_icr;
+case WDT_RIS:
+return s->wdt_ris;
+case WDT_MIS:
+return s->wdt_mis;
+case WDT_TEST:
+return s->wdt_test;
+case WDT_LOCK:
+return s->wdt_lock;
+case WDT_PER_ID4:
+return
[PULL 3/8] tivac gpio module implementation
Signed-off-by: Mohamed ElSayed
---
hw/gpio/tm4c123_gpio.c | 372 +
include/hw/gpio/tm4c123_gpio.h | 127 +++
2 files changed, 499 insertions(+)
create mode 100644 hw/gpio/tm4c123_gpio.c
create mode 100644 include/hw/gpio/tm4c123_gpio.h
diff --git a/hw/gpio/tm4c123_gpio.c b/hw/gpio/tm4c123_gpio.c
new file mode 100644
index 00..7fbe04bd77
--- /dev/null
+++ b/hw/gpio/tm4c123_gpio.c
@@ -0,0 +1,372 @@
+/*
+ * TM4C123 GPIO
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/gpio/tm4c123_gpio.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/tm4c123_sysctl.h"
+#include "qemu/bitops.h"
+#include "trace.h"
+
+#define LOG(fmt, args...) qemu_log("%s: " fmt, __func__, ## args)
+#define READONLY LOG("0x%"HWADDR_PRIx" is a readonly field\n.", addr)
+
+static bool gpio_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch(addr) {
+case GPIO_A:
+return test_bit(0, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_B:
+return test_bit(1, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_C:
+return test_bit(2, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_D:
+return test_bit(3, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_E:
+return test_bit(4, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+case GPIO_F:
+return test_bit(5, (const unsigned long*)>sysctl_rcgcgpio);
+break;
+}
+return false;
+}
+
+static void tm4c123_gpio_reset(DeviceState *dev)
+{
+TM4C123GPIOState *s = TM4C123_GPIO(dev);
+
+s->gpio_data = 0x;
+s->gpio_dir = 0x;
+s->gpio_is = 0x;
+s->gpio_ibe = 0x;
+s->gpio_iev = 0x;
+s->gpio_im = 0x;
+s->gpio_ris = 0x;
+s->gpio_mis = 0x;
+s->gpio_icr = 0x;
+s->gpio_afsel = 0x;
+s->gpio_dr2r = 0x00FF;
+s->gpio_dr4r = 0x;
+s->gpio_dr8r = 0x;
+s->gpio_odr = 0x;
+s->gpio_pur = 0x;
+s->gpio_pdr = 0x;
+s->gpio_slr = 0x;
+s->gpio_den = 0x;
+s->gpio_lock = 0x0001;
+s->gpio_ocr = 0x;
+s->gpio_amsel = 0x;
+s->gpio_pctl = 0x;
+s->gpio_adcctl = 0x;
+s->gpio_dmactl = 0x;
+s->gpio_per_id4 = 0x;
+s->gpio_per_id5 = 0x;
+s->gpio_per_id6 = 0x;
+s->gpio_per_id7 = 0x;
+s->gpio_per_id0 = 0x0061;
+s->gpio_per_id1 = 0x;
+s->gpio_per_id2 = 0x0018;
+s->gpio_per_id3 = 0x0001;
+s->gpio_pcell_id0 = 0x000D;
+s->gpio_pcell_id1 = 0x00F0;
+s->gpio_pcell_id2 = 0x0005;
+s->gpio_pcell_id3 = 0x00B1;
+}
+
+static void tm4c123_gpio_write(void *opaque, hwaddr addr, uint64_t val64,
unsigned int size)
+{
+TM4C123GPIOState *s = opaque;
+uint32_t val32 = val64;
+
+if (!gpio_clock_enabled(s->sysctl, s->mmio.addr)) {
+hw_error("GPIO module clock is not enabled");
+}
+trace_tm4c123_gpio_write(addr, val32);
+
+switch(addr) {
+case GPIO_DATA:
+{
+uint32_t rising_edge = (val32 ^ s->gpio_data) & val32;
+//level detection
+s->gpio_mis = s->gpio_is & s->gpio_iev & val32;
+s->gpio_mis |= s->gpio_is & ~(s->gpio_iev |
[PULL 5/8] tivac general purpose timers implementation
Signed-off-by: Mohamed ElSayed
---
hw/timer/tm4c123_gptm.c | 529
include/hw/timer/tm4c123_gptm.h | 131
2 files changed, 660 insertions(+)
create mode 100644 hw/timer/tm4c123_gptm.c
create mode 100644 include/hw/timer/tm4c123_gptm.h
diff --git a/hw/timer/tm4c123_gptm.c b/hw/timer/tm4c123_gptm.c
new file mode 100644
index 00..69f84ee0ec
--- /dev/null
+++ b/hw/timer/tm4c123_gptm.c
@@ -0,0 +1,529 @@
+/*
+ * TM4C123 General purpose timers
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/timer/tm4c123_gptm.h"
+#include "hw/irq.h"
+#include "trace.h"
+#include "qemu/timer.h"
+#include
+
+#define LOG(fmt, args...) qemu_log("%s: " fmt, __func__, ## args)
+#define READONLY LOG("0x%"HWADDR_PRIx" is a readonly field\n.", addr)
+
+static uint64_t ns_to_ticks(void *opaque, uint64_t ns, uint32_t prescaler)
+{
+TM4C123GPTMState *s = opaque;
+
+uint32_t freq = clock_get_hz(s->clk) / prescaler;
+float sec = (float)ns / (float)NANOSECONDS_PER_SECOND;
+return sec * freq;
+}
+
+static unsigned long ticks_to_time_ns(void *opaque, uint64_t ticks, uint32_t
prescaler)
+{
+TM4C123GPTMState *s = opaque;
+uint32_t freq = clock_get_hz(s->clk) / prescaler;
+return (((float)ticks / (float)freq) * NANOSECONDS_PER_SECOND);
+}
+
+static void log_message(const char *message)
+{
+uint64_t ns = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
+time_t seconds = ns / 10;
+struct tm *timeinfo = localtime();
+char buffer[80];
+strftime(buffer, sizeof(buffer), "%Y-%m-%d %H:%M:%S", timeinfo);
+LOG("[%s] %s\n", buffer, message);
+}
+
+static uint16_t get_timer_width(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+switch(s->mmio.addr) {
+case TIMER0_32...TIMER5_32:
+return TIMER_WIDTH_32;
+case TIMER0_64...TIMER5_64:
+return TIMER_WIDTH_64;
+}
+return 0;
+}
+
+static uint64_t build_interval_value(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+uint16_t timer_width = get_timer_width(s);
+uint64_t interval_value = 0;
+if (timer_width == TIMER_WIDTH_32) {
+/* timer is in 32 bit mode or 32bit rtc*/
+uint16_t upper16 = extract32(s->gptm_talir, 16, 16);
+uint16_t lower16 = extract32(s->gptm_tblir, 0, 16);
+interval_value = ((uint32_t)lower16 << 16) + upper16;
+}
+else if (timer_width == TIMER_WIDTH_64) {
+interval_value = ((uint64_t)s->gptm_talir << 32) + s->gptm_tblir;
+}
+
+trace_tm4c123_gptm_build_interval_value(s->gptm_talir, s->gptm_tblir,
interval_value);
+return interval_value;
+}
+
+static void set_timers(void *opaque)
+{
+TM4C123GPTMState *s = opaque;
+uint64_t interval_value;
+uint16_t timer_width;
+if (s->gptm_ctl & GPTM_TACTL_EN) {
+timer_width = get_timer_width(s);
+if (timer_width == TIMER_WIDTH_32) {
+/* What is the mode of the timer? 16/32 */
+if (s->gptm_cfg == 0x4) {
+/* 16 bit mode */
+interval_value = extract32(s->gptm_talir, 0, 16);
+/* Start the timer? */
+timer_mod(s->a, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
ticks_to_time_ns(s, interval_value, s->gptm_tapr));
+LOG("Timer A/16 is running\n");
+}
+else if (s->gptm_cfg == 0x1) {
+/* 32 bit mode rtc */
+interval_value = build_interval_value(s);
+timer_mod(s->a, qemu_clock_get_ns(QEMU_CLOCK_REALTIME) +
ticks_to_time_ns(s, interval_value, s->gptm_tapr));
+LOG("Timer A/32 RTC is running\n");
+}
+e
[PULL 8/8] code style fixes
Signed-off-by: Mohamed ElSayed
---
hw/arm/tm4c123gh6pm_soc.c | 14 ++--
hw/char/tm4c123_usart.c| 28 +++
hw/misc/tm4c123_sysctl.c | 6 +-
hw/timer/tm4c123_gptm.c| 134 -
hw/watchdog/tm4c123_watchdog.c | 25 +++---
5 files changed, 85 insertions(+), 122 deletions(-)
diff --git a/hw/arm/tm4c123gh6pm_soc.c b/hw/arm/tm4c123gh6pm_soc.c
index da08eefc33..7afaa6653b 100644
--- a/hw/arm/tm4c123gh6pm_soc.c
+++ b/hw/arm/tm4c123gh6pm_soc.c
@@ -89,7 +89,8 @@ static void tm4c123gh6pm_soc_initfn(Object *obj)
object_initialize_child(obj, "sysctl", >sysctl, TYPE_TM4C123_SYSCTL);
for (i = 0; i < USART_COUNT; i++) {
-object_initialize_child(obj, "usart[*]", >usart[i],
TYPE_TM4C123_USART);
+object_initialize_child(obj, "usart[*]",
+>usart[i], TYPE_TM4C123_USART);
}
for (i = 0; i < GPIO_COUNT; i++) {
@@ -97,7 +98,8 @@ static void tm4c123gh6pm_soc_initfn(Object *obj)
}
for (i = 0; i < WDT_COUNT; i++) {
-object_initialize_child(obj, "watchdog-timer[*]", >wdt[i],
TYPE_TM4C123_WATCHDOG);
+object_initialize_child(obj, "watchdog-timer[*]",
+>wdt[i], TYPE_TM4C123_WATCHDOG);
}
for (i = 0; i < GPTM_COUNT; i++) {
@@ -115,14 +117,14 @@ static void tm4c123gh6pm_soc_realize(DeviceState
*dev_soc, Error **errp)
MemoryRegion *system_memory = get_system_memory();
-//init flash memory
+/* init flash memory */
memory_region_init_rom(
>flash, OBJECT(dev_soc),
"TM4C123GH6PM.flash", FLASH_SIZE, _fatal
);
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, >flash);
-//init sram and the sram alias region
+/* init sram and the sram alias region */
memory_region_init_ram(
>sram, OBJECT(dev_soc),
"TM4C123GH6PM.sram", SRAM_SIZE, _fatal);
@@ -181,7 +183,7 @@ static void tm4c123gh6pm_soc_realize(DeviceState *dev_soc,
Error **errp)
/* General purpose timers */
int j = 0;
-for (i = 0, j = 0; i < GPTM_COUNT; i++, j+=2) {
+for (i = 0, j = 0; i < GPTM_COUNT; i++, j += 2) {
dev = DEVICE(&(s->gptm[i]));
s->gptm[i].sysctl = >sysctl;
if (!sysbus_realize(SYS_BUS_DEVICE(>gptm[i]), errp)) {
@@ -190,7 +192,7 @@ static void tm4c123gh6pm_soc_realize(DeviceState *dev_soc,
Error **errp)
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, gptm_addrs[i]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, gptm_irqs[j]));
-sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(armv7m,
gptm_irqs[j+1]));
+sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(armv7m, gptm_irqs[j +
1]));
}
/* SYSCTL */
diff --git a/hw/char/tm4c123_usart.c b/hw/char/tm4c123_usart.c
index cafca02b97..ed20eedb4c 100644
--- a/hw/char/tm4c123_usart.c
+++ b/hw/char/tm4c123_usart.c
@@ -36,42 +36,41 @@
static bool usart_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
{
-switch(addr) {
+switch (addr) {
case USART_0:
-return (s->sysctl_rcgcuart & (1 << 0));
+return s->sysctl_rcgcuart & (1 << 0);
break;
case USART_1:
-return (s->sysctl_rcgcuart & (1 << 1));
+return s->sysctl_rcgcuart & (1 << 1);
break;
case USART_2:
-return (s->sysctl_rcgcuart & (1 << 2));
+return s->sysctl_rcgcuart & (1 << 2);
break;
case USART_3:
-return (s->sysctl_rcgcuart & (1 << 3));
+return s->sysctl_rcgcuart & (1 << 3);
break;
case USART_4:
-return (s->sysctl_rcgcuart & (1 << 4));
+return s->sysctl_rcgcuart & (1 << 4);
break;
case USART_5:
-return (s->sysctl_rcgcuart & (1 << 5));
+return s->sysctl_rcgcuart & (1 << 5);
break;
case USART_6:
-return (s->sysctl_rcgcuart & (1 << 6));
+return s->sysctl_rcgcuart & (1 << 6);
break;
case USART_7:
-return (s->sysctl_rcgcuart & (1 << 7));
+return s->sysctl_rcgcuart & (1 << 7);
break;
}
return false;
}
-static int tm4c123_usart_can_receive(void* opaque)
+static int tm4c123_usart_can_receive(void *opaque)
{
TM4C123USARTState *s = opaque;
if (!(s->usart_fr & USART_FR_RXFF)) {
-//the module can receive data.
return 1;
}
return 0;
@@ -82,7 +81,6 @@ static void tm4c123_usart_receive(void *opaque,
[PULL 2/8] tivac usart module implementation
Signed-off-by: Mohamed ElSayed
---
hw/char/tm4c123_usart.c | 387
include/hw/char/tm4c123_usart.h | 124 ++
2 files changed, 511 insertions(+)
create mode 100644 hw/char/tm4c123_usart.c
create mode 100644 include/hw/char/tm4c123_usart.h
diff --git a/hw/char/tm4c123_usart.c b/hw/char/tm4c123_usart.c
new file mode 100644
index 00..cafca02b97
--- /dev/null
+++ b/hw/char/tm4c123_usart.c
@@ -0,0 +1,387 @@
+/*
+ * TM4C123 USART
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/tm4c123_usart.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "trace.h"
+
+#define LOG(fmt, args...) qemu_log("%s: " fmt, __func__, ## args)
+#define READONLY LOG("0x%"HWADDR_PRIx" is a readonly field\n.", addr)
+
+static bool usart_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch(addr) {
+case USART_0:
+return (s->sysctl_rcgcuart & (1 << 0));
+break;
+case USART_1:
+return (s->sysctl_rcgcuart & (1 << 1));
+break;
+case USART_2:
+return (s->sysctl_rcgcuart & (1 << 2));
+break;
+case USART_3:
+return (s->sysctl_rcgcuart & (1 << 3));
+break;
+case USART_4:
+return (s->sysctl_rcgcuart & (1 << 4));
+break;
+case USART_5:
+return (s->sysctl_rcgcuart & (1 << 5));
+break;
+case USART_6:
+return (s->sysctl_rcgcuart & (1 << 6));
+break;
+case USART_7:
+return (s->sysctl_rcgcuart & (1 << 7));
+break;
+}
+return false;
+}
+
+
+static int tm4c123_usart_can_receive(void* opaque)
+{
+TM4C123USARTState *s = opaque;
+
+if (!(s->usart_fr & USART_FR_RXFF)) {
+//the module can receive data.
+return 1;
+}
+return 0;
+}
+
+static void tm4c123_usart_receive(void *opaque, const uint8_t *buf, int size)
+{
+TM4C123USARTState *s = opaque;
+
+if (!(s->usart_ctl & USART_CR_EN && s->usart_ctl & USART_CR_RXE)) {
+//the module is not enabled
+LOG("The module is not enbled\n");
+return;
+}
+
+s->usart_dr = *buf;
+s->usart_ctl &= ~USART_FR_RXFE;
+
+if (s->usart_im & USART_IM_RXIM) {
+qemu_set_irq(s->irq, 1);
+}
+
+LOG("Receiving: %c\n", s->usart_dr);
+}
+
+static void tm4c123_usart_reset(DeviceState *dev)
+{
+TM4C123USARTState *s = TM4C123_USART(dev);
+
+s->usart_dr = 0x;
+s->usart_rsr = 0x;
+s->usart_fr = 0x0090;
+s->usart_ilpr = 0x;
+s->usart_ibrd = 0x;
+s->usart_fbrd = 0x;
+s->usart_lcrh = 0x;
+s->usart_ctl = 0x0300;
+s->usart_ifls = 0x0012;
+s->usart_im = 0x;
+s->usart_ris = 0x;
+s->usart_mis = 0x;
+s->usart_icr = 0x;
+s->usart_dma_ctl = 0x;
+s->usart_9bit_addr = 0x;
+s->usart_9bit_mask = 0x00FF;
+s->usart_pp = 0x0003;
+s->usart_cc = 0x;
+s->usart_per_id4 = 0x;
+s->usart_per_id5 = 0x;
+s->usart_per_id6 = 0x;
+s->usart_per_id7 = 0x;
+s->usart_per_id0 = 0x0060;
+s->usart_per_id1 = 0x;
+s->usart_per_id2 = 0x0018;
+s->usart_per_id3 = 0x0001;
+s->usart_p
[PULL 7/8] editing the meson and KConfig files to add tivac to qemu build system
Signed-off-by: Mohamed ElSayed --- .gitignore | 1 + README.rst | 150 ++-- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 13 ++ hw/arm/meson.build | 3 + hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/trace-events| 4 + hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/trace-events| 4 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/trace-events| 5 + hw/timer/Kconfig| 3 + hw/timer/meson.build| 1 + hw/timer/trace-events | 5 + hw/watchdog/Kconfig | 3 + hw/watchdog/meson.build | 1 + hw/watchdog/trace-events| 3 + 20 files changed, 72 insertions(+), 137 deletions(-) diff --git a/.gitignore b/.gitignore index 1ea59f4819..009ab2ee4b 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ .gdb_history cscope.* tags +compile_commands.json TAGS GPATH GRTAGS diff --git a/README.rst b/README.rst index 21df79ef43..37ea8cb56c 100644 --- a/README.rst +++ b/README.rst @@ -1,46 +1,8 @@ === -QEMU README +QEMU_TivaC README === -QEMU is a generic and open source machine & userspace emulator and -virtualizer. - -QEMU is capable of emulating a complete machine in software without any -need for hardware virtualization support. By using dynamic translation, -it achieves very good performance. QEMU can also integrate with the Xen -and KVM hypervisors to provide emulated hardware while allowing the -hypervisor to manage the CPU. With hypervisor support, QEMU can achieve -near native performance for CPUs. When QEMU emulates CPUs directly it is -capable of running operating systems made for one machine (e.g. an ARMv7 -board) on a different machine (e.g. an x86_64 PC board). - -QEMU is also capable of providing userspace API virtualization for Linux -and BSD kernel interfaces. This allows binaries compiled against one -architecture ABI (e.g. the Linux PPC64 ABI) to be run on a host using a -different architecture ABI (e.g. the Linux x86_64 ABI). This does not -involve any hardware emulation, simply CPU and syscall emulation. - -QEMU aims to fit into a variety of use cases. It can be invoked directly -by users wishing to have full control over its behaviour and settings. -It also aims to facilitate integration into higher level management -layers, by providing a stable command line interface and monitor API. -It is commonly invoked indirectly via the libvirt library when using -open source applications such as oVirt, OpenStack and virt-manager. - -QEMU as a whole is released under the GNU General Public License, -version 2. For full licensing details, consult the LICENSE file. - - -Documentation -= - -Documentation can be found hosted online at -`<https://www.qemu.org/documentation/>`_. The documentation for the -current development version that is available at -`<https://www.qemu.org/docs/master/>`_ is generated from the ``docs/`` -folder in the source tree, and is built by `Sphinx -<https://www.sphinx-doc.org/en/master/>`_. - +QEMU_TivaC aims to provide a TivaC support for the QEMU project. The project is far from being complete (so far) but im working on it. Building @@ -52,9 +14,11 @@ of other UNIX targets. The simple steps to build QEMU are: .. code-block:: shell + git clone g...@github.com:moesay/qemu_TivaC.git + cd qemu_TivaC mkdir build cd build - ../configure + ../configure --target-list=arm-softmmu make Additional information can also be found online via the QEMU website: @@ -64,108 +28,20 @@ Additional information can also be found online via the QEMU website: * `<https://wiki.qemu.org/Hosts/W32>`_ -Submitting patches -== - -The QEMU source code is maintained under the GIT version control system. - -.. code-block:: shell - - git clone https://gitlab.com/qemu-project/qemu.git - -When submitting patches, one common approach is to use 'git -format-patch' and/or 'git send-email' to format & send the mail to the -qemu-devel@nongnu.org mailing list. All patches submitted must contain -a 'Signed-off-by' line from the author. Patches should follow the -guidelines set out in the `style section -<https://www.qemu.org/docs/master/devel/style.html>`_ of -the Developers Guide. - -Additional information on submitting patches can be found online via -the QEMU website - -* `<https://wiki.qemu.org/Contribute/SubmitAPatch>`_ -* `<https://wiki.qemu.org/Contribute/TrivialPatches>`_ +Usage += -The QEMU website is also maintained under source control. +After building QEMU_T
[PULL 6/8] tivac watchdog timers implementation
Signed-off-by: Mohamed ElSayed
---
hw/watchdog/tm4c123_watchdog.c | 298 +
include/hw/watchdog/tm4c123_watchdog.h | 97
2 files changed, 395 insertions(+)
create mode 100644 hw/watchdog/tm4c123_watchdog.c
create mode 100644 include/hw/watchdog/tm4c123_watchdog.h
diff --git a/hw/watchdog/tm4c123_watchdog.c b/hw/watchdog/tm4c123_watchdog.c
new file mode 100644
index 00..cd064c5343
--- /dev/null
+++ b/hw/watchdog/tm4c123_watchdog.c
@@ -0,0 +1,298 @@
+/*
+ * TM4C123 Watchdog Timers
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/watchdog/tm4c123_watchdog.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "sysemu/runstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/nmi.h"
+#include "trace.h"
+
+#define READONLY LOG("0x%"HWADDR_PRIx" is a readonly field\n.", addr)
+#define LOG(fmt, args...) qemu_log("%s: " fmt, __func__, ## args)
+
+static bool locked = false;
+
+static void tm4c123_wdt_expired(void *opaque)
+{
+TM4C123WatchdogState *s = opaque;
+/*if this is the first timeout/the ris is not cleared */
+if (!test_bit(0, (const unsigned long*)>wdt_mis)) {
+set_bit(0, (unsigned long*)>wdt_mis);
+nmi_monitor_handle(0, NULL);
+qemu_irq_pulse(s->irq);
+}
+else {
+if (test_bit(1, (const unsigned long*)>wdt_ctl))
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+else {
+nmi_monitor_handle(0, NULL);
+qemu_irq_pulse(s->irq);
+}
+}
+}
+
+static bool wdt_clock_enabled(TM4C123SysCtlState *s, hwaddr addr)
+{
+switch(addr) {
+case WDT_0:
+return (s->sysctl_rcgcwd & (1 << 0));
+break;
+case WDT_1:
+return (s->sysctl_rcgcwd & (1 << 1));
+break;
+}
+return false;
+}
+
+static void tm4c123_wdt_reset(DeviceState *dev)
+{
+TM4C123WatchdogState *s = TM4C123_WATCHDOG(dev);
+
+s->wdt_load = 0x;
+s->wdt_value = 0x;
+s->wdt_ctl = (s->mmio.addr == WDT_0 ? 0x : 0x8000);
+s->wdt_icr = 0x;
+s->wdt_ris = 0x;
+s->wdt_mis = 0x;
+s->wdt_test = 0x;
+s->wdt_lock = 0x;
+s->wdt_per_id4 = 0x;
+s->wdt_per_id5 = 0x;
+s->wdt_per_id6 = 0x;
+s->wdt_per_id7 = 0x;
+s->wdt_per_id0 = 0x0005;
+s->wdt_per_id1 = 0x0018;
+s->wdt_per_id2 = 0x0018;
+s->wdt_per_id3 = 0x0001;
+s->wdt_pcell_id0 = 0x000D;
+s->wdt_pcell_id1 = 0x00F0;
+s->wdt_pcell_id2 = 0x0006;
+s->wdt_pcell_id3 = 0x00B1;
+}
+
+static uint64_t tm4c123_wdt_read(void *opaque, hwaddr addr, unsigned int size)
+{
+TM4C123WatchdogState *s = opaque;
+
+if (!wdt_clock_enabled(s->sysctl, s->mmio.addr)) {
+hw_error("Watchdog timer module clock is not enabled");
+}
+
+switch(addr) {
+case WDT_LOAD:
+return s->wdt_load;
+case WDT_VALUE:
+return ptimer_get_count(s->timer);
+case WDT_CTL:
+return s->wdt_ctl;
+case WDT_ICR:
+return s->wdt_icr;
+case WDT_RIS:
+return s->wdt_ris;
+case WDT_MIS:
+return s->wdt_mis;
+case WDT_TEST:
+return s->wdt_test;
+case WDT_LOCK:
+return s->wdt_lock;
+case WDT_PER_ID4:
+return s->wdt_per_id4;
+case WDT_PER_ID5:
+return s->wdt_per_id5;
[PULL 4/8] tivac system control implementation
Signed-off-by: Mohamed ElSayed
---
hw/misc/tm4c123_sysctl.c | 989 +++
include/hw/misc/tm4c123_sysctl.h | 307 ++
2 files changed, 1296 insertions(+)
create mode 100644 hw/misc/tm4c123_sysctl.c
create mode 100644 include/hw/misc/tm4c123_sysctl.h
diff --git a/hw/misc/tm4c123_sysctl.c b/hw/misc/tm4c123_sysctl.c
new file mode 100644
index 00..9bce30eb73
--- /dev/null
+++ b/hw/misc/tm4c123_sysctl.c
@@ -0,0 +1,989 @@
+/*
+ * TM4C123 SYSCTL
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/tm4c123_sysctl.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "trace.h"
+
+#define LOG(fmt, args...) qemu_log("%s: " fmt, __func__, ## args)
+#define READONLY LOG("0x%"HWADDR_PRIx" is a readonly field\n.", addr)
+
+static void tm4c123_sysctl_update_system_clock(void *opaque)
+{
+TM4C123SysCtlState *s = opaque;
+
+uint32_t RCC_Val = s->sysctl_rcc;
+uint32_t RCC2_Val = s->sysctl_rcc2;
+
+uint32_t __CORE_CLK_PRE;
+uint32_t __CORE_CLK;
+
+if (RCC2_Val & (1UL << 31)) { /* is rcc2 used? */
+if (RCC2_Val & (1UL << 11)) { /* check BYPASS */
+if (((RCC2_Val >> 4) & 0x07) == 0x0) {
+if (((RCC_Val >> 6) & 0x1F) == 0x0) {
+__CORE_CLK_PRE = 100UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x1) {
+__CORE_CLK_PRE = 1843200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x2) {
+__CORE_CLK_PRE = 200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x3) {
+__CORE_CLK_PRE = 2457600UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x4) {
+__CORE_CLK_PRE = 3579545UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x5) {
+__CORE_CLK_PRE = 3686400UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x6) {
+__CORE_CLK_PRE = 400UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x7) {
+__CORE_CLK_PRE = 4096000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x8) {
+__CORE_CLK_PRE = 4915200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x9) {
+__CORE_CLK_PRE = 500UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xA) {
+__CORE_CLK_PRE = 512UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xB) {
+__CORE_CLK_PRE = 600UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xC) {
+__CORE_CLK_PRE = 6144000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xD) {
+__CORE_CLK_PRE = 7372800UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xE) {
+__CORE_CLK_PRE = 800UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0xF) {
+__CORE_CLK_PRE = 8192000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x10) {
+__CORE_CLK_PRE = 1000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x11) {
+__CORE_CLK_PRE = 1200UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x12) {
+__CORE_CLK_PRE = 12288000UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x13) {
+__CORE_CLK_PRE = 1356UL;
+} else if (((RCC_Val >> 6) & 0x1F) == 0x14) {
+__CORE_CLK_PRE = 143
[PULL 1/8] the tivac machine def init commit
Signed-off-by: Mohamed ElSayed
---
hw/arm/tivac.c| 56 ++
hw/arm/tm4c123gh6pm_soc.c | 274 ++
include/hw/arm/tm4c123gh6pm_soc.h | 71
3 files changed, 401 insertions(+)
create mode 100644 hw/arm/tivac.c
create mode 100644 hw/arm/tm4c123gh6pm_soc.c
create mode 100644 include/hw/arm/tm4c123gh6pm_soc.h
diff --git a/hw/arm/tivac.c b/hw/arm/tivac.c
new file mode 100644
index 00..5d917a8f9e
--- /dev/null
+++ b/hw/arm/tivac.c
@@ -0,0 +1,56 @@
+/*
+ * TivaC Board Implementation
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "qemu/error-report.h"
+#include "hw/arm/tm4c123gh6pm_soc.h"
+#include "hw/arm/boot.h"
+
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 2400ULL
+
+static void tivac_init(MachineState *machine)
+{
+DeviceState *dev;
+dev = qdev_new(TYPE_TM4C123GH6PM_SOC);
+
+qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
+
+armv7m_load_kernel(ARM_CPU(first_cpu),
+machine->kernel_filename,
+0, FLASH_SIZE);
+}
+
+static void tivac_machine_init(MachineClass *mc)
+{
+mc->desc = "Tiva C (Cortex-M4)";
+mc->init = tivac_init;
+}
+DEFINE_MACHINE("tivac", tivac_machine_init)
diff --git a/hw/arm/tm4c123gh6pm_soc.c b/hw/arm/tm4c123gh6pm_soc.c
new file mode 100644
index 00..da08eefc33
--- /dev/null
+++ b/hw/arm/tm4c123gh6pm_soc.c
@@ -0,0 +1,274 @@
+/*
+ * TM4C123GH6PM SoC
+ *
+ * Copyright (c) 2023 Mohamed ElSayed
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/tm4c123gh6pm_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+static const uint32_t gpio_addrs[GPIO_COUNT] = {
+0x40004000,
+0x40005000,
+0x40006000,
+0x40007000,
+0x40024000,
+0x40025000
+};
+
+static const uint32_t usart_addrs[USART_COUNT] = {
+0x4000C000,
+0x4000D000,
+0x4000E000,
+0x4000F000,
+0x4001,
+0x40011000,
+0x40012000,
+0x40013000
+};
+
+static const uint32_t wdt_addrs[WDT_COUNT] = {
+0x4000,
+0x40001000
+};
+
+static const uint32_t gptm_addrs[GPTM_COUNT] = {
+0x4003,
+0x40031000,
+
[PULL SUBSYSTEM arm 0/8] TivaC Implementation
*** This is an implementation for the TivaC board. For now it models the system control block, the general purpose I/O, the general purpose timers, the watchdog timers and the usart module. The code is available at https://github.com/moesay/qemu_TivaC.git *** Mohamed ElSayed (8): the tivac machine def initial commit tivac usart module implementation tivac gpio module implementation tivac system control implementation tivac general purpose timers implementation tivac watchdog timers implementation editing the meson and KConfig files to add tivac to qemu build system code style fixes .gitignore | 1 + README.rst | 150 +--- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 13 + hw/arm/meson.build | 3 + hw/arm/tivac.c | 56 ++ hw/arm/tm4c123gh6pm_soc.c | 276 +++ hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/tm4c123_usart.c | 383 + hw/char/trace-events| 4 + hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/tm4c123_gpio.c | 372 + hw/gpio/trace-events| 4 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/tm4c123_sysctl.c| 989 hw/misc/trace-events| 5 + hw/timer/Kconfig| 3 + hw/timer/meson.build| 1 + hw/timer/tm4c123_gptm.c | 495 hw/timer/trace-events | 5 + hw/watchdog/Kconfig | 3 + hw/watchdog/meson.build | 1 + hw/watchdog/tm4c123_watchdog.c | 297 +++ hw/watchdog/trace-events| 3 + include/hw/arm/tm4c123gh6pm_soc.h | 71 ++ include/hw/char/tm4c123_usart.h | 124 +++ include/hw/gpio/tm4c123_gpio.h | 127 +++ include/hw/misc/tm4c123_sysctl.h| 307 include/hw/timer/tm4c123_gptm.h | 131 include/hw/watchdog/tm4c123_watchdog.h | 97 +++ 33 files changed, 3797 insertions(+), 137 deletions(-) create mode 100644 hw/arm/tivac.c create mode 100644 hw/arm/tm4c123gh6pm_soc.c create mode 100644 hw/char/tm4c123_usart.c create mode 100644 hw/gpio/tm4c123_gpio.c create mode 100644 hw/misc/tm4c123_sysctl.c create mode 100644 hw/timer/tm4c123_gptm.c create mode 100644 hw/watchdog/tm4c123_watchdog.c create mode 100644 include/hw/arm/tm4c123gh6pm_soc.h create mode 100644 include/hw/char/tm4c123_usart.h create mode 100644 include/hw/gpio/tm4c123_gpio.h create mode 100644 include/hw/misc/tm4c123_sysctl.h create mode 100644 include/hw/timer/tm4c123_gptm.h create mode 100644 include/hw/watchdog/tm4c123_watchdog.h -- 2.34.1
Development request
Hello there, We are 6 students from Egypt and now We are in our last year and We need to build a project as a graduation project. And We are interested in the area of runtime systems, operating systems and compilers. We are going to work 40-60 hrs a week Can We help with some tools you need as a graduation project given that We have a professor to mentor us. If not, Can you suggest some tools you need to build and We will work on it. The project takes one academic year Thanks
[Bug 1921280] [NEW] OpenIndiana stuck in boot loop when using hvf
Public bug reported: I'm using QEMU version 5.2.0 on macOS, and running the "OpenIndiana Hipster 2020.10 Text Install DVD (64-bit x86)" ISO: qemu-system-x86_64 -cdrom ~/Downloads/OI-hipster-text-20201031.iso -m 2048 -accel hvf -cpu host It gets to "Booting...", stays there for a bit, and then restarts. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1921280 Title: OpenIndiana stuck in boot loop when using hvf Status in QEMU: New Bug description: I'm using QEMU version 5.2.0 on macOS, and running the "OpenIndiana Hipster 2020.10 Text Install DVD (64-bit x86)" ISO: qemu-system-x86_64 -cdrom ~/Downloads/OI-hipster-text-20201031.iso -m 2048 -accel hvf -cpu host It gets to "Booting...", stays there for a bit, and then restarts. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1921280/+subscriptions
Questions regarding the usage of the QIO API
Hi, (Not sure if this is the right place to ask such a question. Please redirect me if it is the case.) I am currently debugging a problem related to the usage of the QIO interface (qio_channel_closee, qio_channel_add_watch, ...). Where can I find more information on the internal working of this queues? How does the "watch" work. Is there a thread in the background handling these operations? Regards, Mohamed
