Re: Call for GSoC/Outreachy internship project ideas
On Thu, 01 Feb 2024 10:57:00 PST (-0800), alex.ben...@linaro.org wrote: Palmer Dabbelt writes: On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote: Palmer Dabbelt writes: On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote: On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote: On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: > Dear QEMU and KVM communities, > QEMU will apply for the Google Summer of Code and Outreachy internship > programs again this year. Regular contributors can submit project > ideas that they'd like to mentor by replying to this email before > January 30th. It's the 30th, sorry if this is late but I just saw it today. +Alistair and Daniel, as I didn't sync up with anyone about this so not sure if someone else is looking already (we're not internally). Hi Palmer, Performance optimization can be challenging for newcomers. I wouldn't recommend it for a GSoC project unless you have time to seed the project idea with specific optimizations to implement based on your experience and profiling. That way the intern has a solid starting point where they can have a few successes before venturing out to do their own performance analysis. Ya, I agree. That's part of the reason why I wasn't sure if it's a good idea. At least for this one I think there should be some easy to understand performance issue, as the loops that go very slowly consist of a small number of instructions and go a lot slower. I'm actually more worried about this running into a rabbit hole of adding new TCG operations or even just having no well defined mappings between RVV and AVX, those might make the project really hard. You shouldn't have a hard guest-target mapping. But are you already using the TCGVec types and they are not expanding to AVX when its available? Ya, sorry, I guess that was an odd way to describe it. IIUC we're doing sane stuff, it's just that RISC-V has a very different vector masking model than other ISAs. I just said AVX there because I only care about the performance on Intel servers, since that's what I run QEMU on. I'd asssume we have similar performance problems on other targets, I just haven't looked. So my worry would be that the RVV things we're doing slowly just don't have fast implementations via AVX and thus we run into some intractable problems. That sort of stuff can be really frusturating for an intern, as everything's new to them so it can be hard to know when something's an optimization dead end. That said, we're seeing 100x slowdows in microbenchmarks and 10x slowdowns in real code, so I think there sholud be some way to do better. It would be nice if you could convert that micro-benchmark to plain C for a tcg/multiarch test case. It would be a useful tool for testing changes. Yep. I actually gave it a shot before posting the C++ version and it seems kind of fragile, just poking it boring looknig ways changes the behavior. Some of that was tied up in me trying to get GCC to generate similar code to clang, though, so hopefully that's all manageable. I certainly wouldn't want to throw something that wacky at an intern for their first project, though. So I don't have a good version yet. I'm also hoping the fuzzer reproduces some nice small examples, but no luck yet... Remember for anything float we will end up with softfloat anyway so we can't use SIMD on the backend. Yep, but we have a handful of integer slowdowns too so I think there's some meat to chew on here. The softfloat stuff should be equally slow for scalar/vector, so we shouldn't be tripping false positives there. Do you have the time to profile and add specifics to the project idea by Feb 21st? If that sounds good to you, I'll add it to the project ideas list and you can add more detailed tasks in the coming weeks. I can at least dig up some of the examples I ran into, there's been a handful filtering in over the last year or so. This one <https://gist.github.com/compnerd/daa7e68f7b4910cb6b27f856e6c2beba> still has a much more than 10x slowdown (73ms -> 13s) with vectorization, for example. Thanks, Stefan -- Alex Bennée Virtualisation Tech Lead @ Linaro -- Alex Bennée Virtualisation Tech Lead @ Linaro
Re: Call for GSoC/Outreachy internship project ideas
On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote: Palmer Dabbelt writes: On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote: On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote: On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: > Dear QEMU and KVM communities, > QEMU will apply for the Google Summer of Code and Outreachy internship > programs again this year. Regular contributors can submit project > ideas that they'd like to mentor by replying to this email before > January 30th. It's the 30th, sorry if this is late but I just saw it today. +Alistair and Daniel, as I didn't sync up with anyone about this so not sure if someone else is looking already (we're not internally). Hi Palmer, Performance optimization can be challenging for newcomers. I wouldn't recommend it for a GSoC project unless you have time to seed the project idea with specific optimizations to implement based on your experience and profiling. That way the intern has a solid starting point where they can have a few successes before venturing out to do their own performance analysis. Ya, I agree. That's part of the reason why I wasn't sure if it's a good idea. At least for this one I think there should be some easy to understand performance issue, as the loops that go very slowly consist of a small number of instructions and go a lot slower. I'm actually more worried about this running into a rabbit hole of adding new TCG operations or even just having no well defined mappings between RVV and AVX, those might make the project really hard. You shouldn't have a hard guest-target mapping. But are you already using the TCGVec types and they are not expanding to AVX when its available? Ya, sorry, I guess that was an odd way to describe it. IIUC we're doing sane stuff, it's just that RISC-V has a very different vector masking model than other ISAs. I just said AVX there because I only care about the performance on Intel servers, since that's what I run QEMU on. I'd asssume we have similar performance problems on other targets, I just haven't looked. So my worry would be that the RVV things we're doing slowly just don't have fast implementations via AVX and thus we run into some intractable problems. That sort of stuff can be really frusturating for an intern, as everything's new to them so it can be hard to know when something's an optimization dead end. That said, we're seeing 100x slowdows in microbenchmarks and 10x slowdowns in real code, so I think there sholud be some way to do better. Remember for anything float we will end up with softfloat anyway so we can't use SIMD on the backend. Yep, but we have a handful of integer slowdowns too so I think there's some meat to chew on here. The softfloat stuff should be equally slow for scalar/vector, so we shouldn't be tripping false positives there. Do you have the time to profile and add specifics to the project idea by Feb 21st? If that sounds good to you, I'll add it to the project ideas list and you can add more detailed tasks in the coming weeks. I can at least dig up some of the examples I ran into, there's been a handful filtering in over the last year or so. This one <https://gist.github.com/compnerd/daa7e68f7b4910cb6b27f856e6c2beba> still has a much more than 10x slowdown (73ms -> 13s) with vectorization, for example. Thanks, Stefan -- Alex Bennée Virtualisation Tech Lead @ Linaro
[PATCH] RISC-V: Report the QEMU vendor/arch IDs on virtual CPUs
Right now we just report 0 for marchid/mvendorid in QEMU. That's legal, but it's tricky for users that want to check if they're running on QEMU to do so. This sets marchid to 42, which I've proposed as the QEMU architecture ID (mvendorid remains 0, just explicitly set, as that's how the ISA handles open source implementations). Link: https://github.com/riscv/riscv-isa-manual/pull/1213 Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 16 target/riscv/cpu_vendorid.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..1aef186f87 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -415,6 +415,9 @@ static void riscv_any_cpu_init(Object *obj) cpu->cfg.ext_zicsr = true; cpu->cfg.mmu = true; cpu->cfg.pmp = true; + +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } static void riscv_max_cpu_init(Object *obj) @@ -432,6 +435,8 @@ static void riscv_max_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? VM_1_10_SV32 : VM_1_10_SV57); #endif +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } #if defined(TARGET_RISCV64) @@ -445,6 +450,8 @@ static void rv64_base_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } static void rv64_sifive_u_cpu_init(Object *obj) @@ -569,6 +576,8 @@ static void rv128_base_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } static void rv64i_bare_cpu_init(Object *obj) @@ -591,6 +600,8 @@ static void rv64i_bare_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); #endif +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } #else static void rv32_base_cpu_init(Object *obj) @@ -603,6 +614,8 @@ static void rv32_base_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } static void rv32_sifive_u_cpu_init(Object *obj) @@ -672,6 +685,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_zifencei = true; cpu->cfg.ext_zicsr = true; cpu->cfg.pmp = true; + +cpu->cfg.mvendorid = QEMU_MVENDORID; +cpu->cfg.marchid = QEMU_MARCHID; } #endif diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h index 96b6b9c2cb..486832cd53 100644 --- a/target/riscv/cpu_vendorid.h +++ b/target/riscv/cpu_vendorid.h @@ -7,4 +7,7 @@ #define VEYRON_V1_MIMPID0x111 #define VEYRON_V1_MVENDORID 0x61f +#define QEMU_VIRT_MVENDORID 0 +#define QEMU_VIRT_MARCHID 42 + #endif /* TARGET_RISCV_CPU_VENDORID_H */ -- 2.43.0
Re: Call for GSoC/Outreachy internship project ideas
On Wed, 31 Jan 2024 06:39:25 PST (-0800), stefa...@gmail.com wrote: On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote: On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and might have some tricky parts. That said it's tripping some people up and as far as I know nobody's started looking at it, so I figrued I'd write something up. Hi Palmer, Your idea has been added: https://wiki.qemu.org/Google_Summer_of_Code_2024#RISC-V_Vector_TCG_Frontend_Optimization I added links to the vector extension specification and the RISC-V TCG frontend source code. Please add concrete tasks (e.g. specific optimizations the intern should implement and benchmark) by Feb 21st. Thank you! OK. We've got a few examples starting to filter in, I'll keep updating the bug until we get some nice concrete reproducers for slowdows of decent vectorized code. Then I'll take a look and what's inside them, with any luck it'll be simple to figure out which vector instructions are commonly used and slow -- there's a bunch of stuff in the RVV translation that doesn't map cleanly, so I'm guessing it'll be in there. If that all goes smoothly then I think we should have a reasonably actionable intern project, but LMK if you were thinking of something else? Stefan
Re: Call for GSoC/Outreachy internship project ideas
On Tue, 30 Jan 2024 17:26:11 PST (-0800), alistai...@gmail.com wrote: On Wed, Jan 31, 2024 at 10:30 AM Palmer Dabbelt wrote: On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote: > On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote: >> >> On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: >> > Dear QEMU and KVM communities, >> > QEMU will apply for the Google Summer of Code and Outreachy internship >> > programs again this year. Regular contributors can submit project >> > ideas that they'd like to mentor by replying to this email before >> > January 30th. >> >> It's the 30th, sorry if this is late but I just saw it today. +Alistair >> and Daniel, as I didn't sync up with anyone about this so not sure if >> someone else is looking already (we're not internally). >> >> > Internship programs >> > --- >> > GSoC (https://summerofcode.withgoogle.com/) and Outreachy >> > (https://www.outreachy.org/) offer paid open source remote work >> > internships to eligible people wishing to participate in open source >> > development. QEMU has been part of these internship programs for many >> > years. Our mentors have enjoyed helping talented interns make their >> > first open source contributions and some former interns continue to >> > participate today. >> > >> > Who can mentor >> > -- >> > Regular contributors to QEMU and KVM can participate as mentors. >> > Mentorship involves about 5 hours of time commitment per week to >> > communicate with the intern, review their patches, etc. Time is also >> > required during the intern selection phase to communicate with >> > applicants. Being a mentor is an opportunity to help someone get >> > started in open source development, will give you experience with >> > managing a project in a low-stakes environment, and a chance to >> > explore interesting technical ideas that you may not have time to >> > develop yourself. >> > >> > How to propose your idea >> > -- >> > Reply to this email with the following project idea template filled in: >> > >> > === TITLE === >> > >> > '''Summary:''' Short description of the project >> > >> > Detailed description of the project that explains the general idea, >> > including a list of high-level tasks that will be completed by the >> > project, and provides enough background for someone unfamiliar with >> > the codebase to do research. Typically 2 or 3 paragraphs. >> > >> > '''Links:''' >> > * Wiki links to relevant material >> > * External links to mailing lists or web sites >> > >> > '''Details:''' >> > * Skill level: beginner or intermediate or advanced >> > * Language: C/Python/Rust/etc >> >> I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and >> might have some tricky parts. That said it's tripping some people up >> and as far as I know nobody's started looking at it, so I figrued I'd >> write something up. >> >> I can try and dig up some more links if folks thing it's interesting, >> IIRC there's been a handful of bug reports related to very small loops >> that run ~10x slower when vectorized. Large benchmarks like SPEC have >> also shown slowdowns. > > Hi Palmer, > Performance optimization can be challenging for newcomers. I wouldn't > recommend it for a GSoC project unless you have time to seed the > project idea with specific optimizations to implement based on your > experience and profiling. That way the intern has a solid starting > point where they can have a few successes before venturing out to do > their own performance analysis. Ya, I agree. That's part of the reason why I wasn't sure if it's a good idea. At least for this one I think there should be some easy to understand performance issue, as the loops that go very slowly consist of a small number of instructions and go a lot slower. I'm actually more worried about this running into a rabbit hole of adding new TCG operations or even just having no well defined mappings between RVV and AVX, those might make the project really hard. > Do you have the time to profile and add specifics to the project idea > by Feb 21st? If that sounds good to you, I'll add it to the project > ideas list and you can add more detailed tasks in the coming weeks. I can at least dig up some of the examples I ran into, there's been a handful filtering in over the last year or so. This one <https://gist.github.com/compnerd/daa7e68f7b4910cb6b27f856e6c2beba> still has a much more than 10x slowdown (73ms -> 13s) with vectorization, for example. It's probably worth creating a Gitlab issue for this and adding all of the examples there. That way we have a single place to store them all Makes sense. I think I'd been telling people to make bug reports for them, so there might be some in there already -- I just dug this one out of some history. Here's a start: https://gitlab.com/qemu-project/qemu/-/issues/2137 Alistair > Thanks, > Stefan
Re: Call for GSoC/Outreachy internship project ideas
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote: On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote: On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: > Dear QEMU and KVM communities, > QEMU will apply for the Google Summer of Code and Outreachy internship > programs again this year. Regular contributors can submit project > ideas that they'd like to mentor by replying to this email before > January 30th. It's the 30th, sorry if this is late but I just saw it today. +Alistair and Daniel, as I didn't sync up with anyone about this so not sure if someone else is looking already (we're not internally). > Internship programs > --- > GSoC (https://summerofcode.withgoogle.com/) and Outreachy > (https://www.outreachy.org/) offer paid open source remote work > internships to eligible people wishing to participate in open source > development. QEMU has been part of these internship programs for many > years. Our mentors have enjoyed helping talented interns make their > first open source contributions and some former interns continue to > participate today. > > Who can mentor > -- > Regular contributors to QEMU and KVM can participate as mentors. > Mentorship involves about 5 hours of time commitment per week to > communicate with the intern, review their patches, etc. Time is also > required during the intern selection phase to communicate with > applicants. Being a mentor is an opportunity to help someone get > started in open source development, will give you experience with > managing a project in a low-stakes environment, and a chance to > explore interesting technical ideas that you may not have time to > develop yourself. > > How to propose your idea > -- > Reply to this email with the following project idea template filled in: > > === TITLE === > > '''Summary:''' Short description of the project > > Detailed description of the project that explains the general idea, > including a list of high-level tasks that will be completed by the > project, and provides enough background for someone unfamiliar with > the codebase to do research. Typically 2 or 3 paragraphs. > > '''Links:''' > * Wiki links to relevant material > * External links to mailing lists or web sites > > '''Details:''' > * Skill level: beginner or intermediate or advanced > * Language: C/Python/Rust/etc I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and might have some tricky parts. That said it's tripping some people up and as far as I know nobody's started looking at it, so I figrued I'd write something up. I can try and dig up some more links if folks thing it's interesting, IIRC there's been a handful of bug reports related to very small loops that run ~10x slower when vectorized. Large benchmarks like SPEC have also shown slowdowns. Hi Palmer, Performance optimization can be challenging for newcomers. I wouldn't recommend it for a GSoC project unless you have time to seed the project idea with specific optimizations to implement based on your experience and profiling. That way the intern has a solid starting point where they can have a few successes before venturing out to do their own performance analysis. Ya, I agree. That's part of the reason why I wasn't sure if it's a good idea. At least for this one I think there should be some easy to understand performance issue, as the loops that go very slowly consist of a small number of instructions and go a lot slower. I'm actually more worried about this running into a rabbit hole of adding new TCG operations or even just having no well defined mappings between RVV and AVX, those might make the project really hard. Do you have the time to profile and add specifics to the project idea by Feb 21st? If that sounds good to you, I'll add it to the project ideas list and you can add more detailed tasks in the coming weeks. I can at least dig up some of the examples I ran into, there's been a handful filtering in over the last year or so. This one <https://gist.github.com/compnerd/daa7e68f7b4910cb6b27f856e6c2beba> still has a much more than 10x slowdown (73ms -> 13s) with vectorization, for example. Thanks, Stefan
Re: Call for GSoC/Outreachy internship project ideas
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote: Dear QEMU and KVM communities, QEMU will apply for the Google Summer of Code and Outreachy internship programs again this year. Regular contributors can submit project ideas that they'd like to mentor by replying to this email before January 30th. It's the 30th, sorry if this is late but I just saw it today. +Alistair and Daniel, as I didn't sync up with anyone about this so not sure if someone else is looking already (we're not internally). Internship programs --- GSoC (https://summerofcode.withgoogle.com/) and Outreachy (https://www.outreachy.org/) offer paid open source remote work internships to eligible people wishing to participate in open source development. QEMU has been part of these internship programs for many years. Our mentors have enjoyed helping talented interns make their first open source contributions and some former interns continue to participate today. Who can mentor -- Regular contributors to QEMU and KVM can participate as mentors. Mentorship involves about 5 hours of time commitment per week to communicate with the intern, review their patches, etc. Time is also required during the intern selection phase to communicate with applicants. Being a mentor is an opportunity to help someone get started in open source development, will give you experience with managing a project in a low-stakes environment, and a chance to explore interesting technical ideas that you may not have time to develop yourself. How to propose your idea -- Reply to this email with the following project idea template filled in: === TITLE === '''Summary:''' Short description of the project Detailed description of the project that explains the general idea, including a list of high-level tasks that will be completed by the project, and provides enough background for someone unfamiliar with the codebase to do research. Typically 2 or 3 paragraphs. '''Links:''' * Wiki links to relevant material * External links to mailing lists or web sites '''Details:''' * Skill level: beginner or intermediate or advanced * Language: C/Python/Rust/etc I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and might have some tricky parts. That said it's tripping some people up and as far as I know nobody's started looking at it, so I figrued I'd write something up. I can try and dig up some more links if folks thing it's interesting, IIRC there's been a handful of bug reports related to very small loops that run ~10x slower when vectorized. Large benchmarks like SPEC have also shown slowdowns. --- === RISC-V Vector TCG Frontend Optimization === '''Summary:''' The RISC-V vector extension has been implemented in QEMU, but we have some performance pathologies mapping it to existing TCG backends. This project would aim to improve the performance of the RISC-V vector ISA's mappings to TCG. The RISC-V TCG frontend (ie, decoding RISC-V instructions and emitting TCG calls to emulate them) has some inefficient mappings to TCG, which results in binaries that have vector instructions frequently performing worse than those without, sometimes even up to 10x slower. This causes various headaches for users, including running toolchain regressions and doing distro work. This project's aim would be to bring the performance of vectorized RISC-V code to a similar level as the corresponding scalar code. This will definitely require changing the RISC-V TCG frontend. It's likely there is some remaining optimization work that can be done without adding TCG primitives, but it may be necessary to do some core TCG work in order to improve performance sufficiently. '''Links:''' * https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg04495.html '''Details''' * Skill level: intermediate * Language: C, RISC-V assembly More information -- You can find out about the process we follow here: Video: https://www.youtube.com/watch?v=xNVCX7YMUL8 Slides (PDF): https://vmsplice.net/~stefan/stefanha-kvm-forum-2016.pdf The QEMU wiki page for GSoC 2024 is now available: https://wiki.qemu.org/Google_Summer_of_Code_2024 Thanks, Stefan
Re: [PULL 15/21] linux-user/riscv: Add vdso
On Fri, 12 Jan 2024 13:35:39 PST (-0800), Richard Henderson wrote: > On 1/12/24 08:49, Vineet Gupta wrote: >> Hi Richard, Alistair >> >> On 10/30/23 14:17, Richard Henderson wrote: >>> diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso >>> new file mode 100644 >>> index 00..2c257dbfda >>> --- /dev/null >>> +++ b/linux-user/riscv/Makefile.vdso >>> @@ -0,0 +1,15 @@ >>> +include $(BUILD_DIR)/tests/tcg/riscv64-linux-user/config-target.mak >>> + >>> +SUBDIR = $(SRC_PATH)/linux-user/riscv >>> +VPATH += $(SUBDIR) >>> + >>> +all: $(SUBDIR)/vdso-32.so $(SUBDIR)/vdso-64.so >>> + >>> +LDFLAGS = -nostdlib -shared -fpic -Wl,-h,linux-vdso.so.1 >>> -Wl,--build-id=sha1 \ >>> + -Wl,--hash-style=both -Wl,-T,$(SUBDIR)/vdso.ld >>> + >>> +$(SUBDIR)/vdso-32.so: vdso.S vdso.ld vdso-asmoffset.h >>> + $(CC) -o $@ $(LDFLAGS) -mabi=ilp32d -march=rv32g $< >>> + >>> +$(SUBDIR)/vdso-64.so: vdso.S vdso.ld vdso-asmoffset.h >>> + $(CC) -o $@ $(LDFLAGS) -mabi=lp64d -march=rv64g $< >> >> So by default qemu ships the vdso binary. How can one rebuild it ? >> >> From skimming the build files it seems following ought to do it >>    make update-linux-vdso >> >> with a prior configure cmd like below with PATH pointing to the cross >> compiler. >> ../configure --target-list=riscv64-linux-user >> --cross-cc-riscv64=riscv64-unknown-linux-gnu-gcc > > Yes, that should do it. > >> But it doesn't, I'm sure we are missing something basis here. > > Do you get an error message? > Did $(BUILD_DIR)/tests/tcg/riscv64-linux-user/config-target.mak get created > properly? > >> For starters we saw something that seems like a thinko in >> >> diff --git a/linux-user/riscv/vdso.S b/linux-user/riscv/vdso.S >> -#define sizeof_reg    (__riscv_xlen / 4) >> +#define sizeof_reg    (__riscv_xlen / 8) > > Oops. > >> As as aside, we also see that rt_sigreturn in kernel vdso elides the >> explicit the call frame information. Again we naively don't know if that >> is required in qemu. >> >>    .text >> ENTRY(__vdso_rt_sigreturn) >>    .cfi_startproc >>    .cfi_signal_frame >>    li a7, __NR_rt_sigreturn >>    ecall >>    .cfi_endproc >> ENDPROC(__vdso_rt_sigreturn) > > Perhaps it's not required, no. But I'd consider the lack of info from the > kernel to be a > bug. Lack of it means places like gcc have to have special cases. Ya, I agree. We've tried to avoid too many RISC-V-specific hacks for this, but it's bitten me a few times in embedded codebases and it's always a headache. Reviewed-by: Palmer Dabbelt Thanks! Looks like we've got essentially the same thing in Linux already, so I think we're safe over there. > > > > r~ > > -- > You received this message because you are subscribed to the Google Groups > "gnu-toolchain" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to gnu-toolchain+unsubscr...@rivosinc.com. > To view this discussion on the web visit > https://groups.google.com/a/rivosinc.com/d/msgid/gnu-toolchain/119848b9-0cd7-4d33-bc43-385c86069388%40linaro.org. > For more options, visit https://groups.google.com/a/rivosinc.com/d/optout.
Re: [PATCH] linux-user: Fixed cpu restore with pc 0 on SIGBUS
On Fri, 12 Jan 2024 12:57:22 PST (-0800), r...@rivosinc.com wrote:
Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler)
introduced a bug, when returning from host_sigbus_handler the PC is
So we should probably have a
Fixes: f4e1168198 ("linux-user: Split out host_sig{segv,bus}_handler")
never set. Thus cpu_loop_exit_restore is called with a zero PC and
we immediate get a SIGSEGV.
Signed-off-by: Robbin Ehn
---
linux-user/signal.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index b35d1e512f..c9527adfa3 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -925,7 +925,7 @@ static void host_sigsegv_handler(CPUState *cpu, siginfo_t
*info,
cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
}
-static void host_sigbus_handler(CPUState *cpu, siginfo_t *info,
+static uintptr_t host_sigbus_handler(CPUState *cpu, siginfo_t *info,
host_sigcontext *uc)
{
uintptr_t pc = host_signal_pc(uc);
@@ -947,6 +947,7 @@ static void host_sigbus_handler(CPUState *cpu, siginfo_t
*info,
sigprocmask(SIG_SETMASK, host_signal_mask(uc), NULL);
cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc);
}
+return pc;
}
static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
@@ -974,7 +975,7 @@ static void host_signal_handler(int host_sig, siginfo_t
*info, void *puc)
host_sigsegv_handler(cpu, info, uc);
Do we have the same problem for SEGV? They both used to set
pc = host_signal_pc(uc);
but with this it's only SIGBUS. Maybe the same for the others, so just
something like
diff --git a/linux-user/signal.c b/linux-user/signal.c
index b35d1e512f..55840bdf31 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -968,6 +968,8 @@ static void host_signal_handler(int host_sig, siginfo_t
*info, void *puc)
* SIGFPE, SIGTRAP are always host bugs.
*/
if (info->si_code > 0) {
+pc = host_signal_pc(uc);
+
switch (host_sig) {
case SIGSEGV:
/* Only returns on handle_sigsegv_accerr_write success. */
as it just does the PC chasing for everyone?
return;
case SIGBUS:
-host_sigbus_handler(cpu, info, uc);
+pc = host_sigbus_handler(cpu, info, uc);
sync_sig = true;
break;
case SIGILL:
--
2.40.1
Either way,
Reviewed-by: Palmer Dabbelt
Thanks!
[PATCH] linux-user/riscv: Add Zicboz block size to hwprobe
Support for probing the Zicboz block size landed in Linux 6.6, which was
released a few weeks ago. This provides the user-configured block size
when Zicboz is enabled.
Signed-off-by: Palmer Dabbelt
---
linux-user/syscall.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 65ac3ac796..7caacf43d6 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8808,6 +8808,8 @@ static int do_getdents64(abi_long dirfd, abi_long arg2,
abi_long count)
#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
#define RISCV_HWPROBE_MISALIGNED_MASK(7 << 0)
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
+
struct riscv_hwprobe {
abi_llong key;
abi_ullong value;
@@ -8860,6 +8862,10 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
case RISCV_HWPROBE_KEY_CPUPERF_0:
__put_user(RISCV_HWPROBE_MISALIGNED_FAST, >value);
break;
+case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
+value = cfg->ext_zicboz ? cfg->cboz_blocksize : 0;
+__put_user(value, >value);
+break;
default:
__put_user(-1, >key);
break;
--
2.42.1
Re: [PATCH] Support for the RISCV Zalasr extension
On Thu, 26 Oct 2023 16:03:28 PDT (-0700), turt...@utexas.edu wrote:
From 4af1fca6e5c99578a5b80b834c22b70f6419639f Mon Sep 17 00:00:00 2001
From: Brendan Sweeney
Date: Thu, 26 Oct 2023 17:01:29 -0500
Subject: [PATCH] Support for the RISCV Zalasr extension
This doesn't have a commit body. At least pointing to the extension doc
over at https://github.com/mehnadnerd/riscv-zalasr would be super
helpful, there's so many extensions these days even Google is having
trouble finding them.
Signed-off-by: Brendan Sweeney
---
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 15 +++
target/riscv/insn_trans/trans_rvzalasr.c.inc | 112 +++
target/riscv/translate.c | 1 +
5 files changed, 131 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzalasr.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac4a6c7eec..a0414bd956 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -85,6 +85,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
+ ISA_EXT_DATA_ENTRY(zalasr, PRIV_VERSION_1_12_0, ext_zalasr),
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
@@ -1248,6 +1249,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =
{
MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
+ MULTI_EXT_CFG_BOOL("zalasr", ext_zalasr, true),
MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 0e6a0f245c..8e4f9282fd 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -76,6 +76,7 @@ struct RISCVCPUConfig {
bool ext_svpbmt;
bool ext_zdinx;
bool ext_zawrs;
+ bool ext_zalasr;
bool ext_zfa;
bool ext_zfbfmin;
bool ext_zfh;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 33597fe2bb..ba95cdf964 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -70,6 +70,9 @@
@atom_ld . aq:1 rl:1 . . ... rs2=0 %rs1 %rd
@atom_st . aq:1 rl:1 . . ... %rs2 %rs1 %rd
+@l_aq . . rl:1 . . ... rs2=0 %rs1 %rd aq=1
+@s_rl . aq:1 . . . ... %rs2 %rs1 rd=0 rl=1
+
@r4_rm . .. . . ... . ... %rs3 %rs2 %rs1 %rm %rd
@r_rm ... . . ... . ... %rs2 %rs1 %rm %rd
@@ -739,6 +742,18 @@ vsetvl 100 . . 111 . 1010111 @r
wrs_nto 1101 0 000 0 1110011
wrs_sto 00011101 0 000 0 1110011
+# *** RV32 Zalasr Standard Extension ***
+lb_aq 00110 1 . 0 . 000 . 010 @l_aq
+lh_aq 00110 1 . 0 . 001 . 010 @l_aq
+lw_aq 00110 1 . 0 . 010 . 010 @l_aq
+sb_rl 00111 . 1 . . 000 0 010 @s_rl
+sh_rl 00111 . 1 . . 001 0 010 @s_rl
+sw_rl 00111 . 1 . . 010 0 010 @s_rl
+
+# *** RV64 Zalasr Standard Extension (in addition to RV32 Zalasr) ***
+ld_aq 00110 1 . 0 . 011 . 010 @l_aq
+sd_rl 00111 . 1 . . 011 0 010 @s_rl
+
# *** RV32 Zba Standard Extension ***
sh1add 001 .. 010 . 0110011 @r
sh2add 001 .. 100 . 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc
b/target/riscv/insn_trans/trans_rvzalasr.c.inc
new file mode 100644
index 00..cee81ce8b8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -0,0 +1,112 @@
+/*
+ * RISC-V translation routines for the Zzlasr Standard Extension.
+ *
+ * Copyright (c) 2023 Brendan Sweeney, b...@berkeley.edu
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
with
+ * this program. If not, see
Re: [RESEND] qemu/timer: Add host ticks function for RISC-V
On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonz...@redhat.com wrote: Il sab 9 set 2023, 03:35 Atish Patra ha scritto: On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini wrote: > > Queued, thanks. > I didn't realize it was already queued. Gmail threads failed me this time. @Paolo Bonzini : Can you please drop this one as this will break as soon as the host riscv system has the latest kernel ? I have provided more details in the original thread. https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg01941.html If you have dynamic clock adjustment, does rdcycle increase with a fixed frequency or does it provide the raw number of clock cycles? If the latter, I agree that it should be provided by perf; but if the frequency is fixed then it would be the same as rdtsc on Intel. That really depends on exactly how the system is set up, but there are systems for which the rdcycle frequency changes when clock speeds change and thus will produce surprising answers for users trying to use rdcycle as a RTC. We have rdtime for that, but it has other problems (it's trapped and emulated in M-mode on some systems, so it's slow and noisy). So we're steering folks towards perf where we can, as at least that way we've got a higher-level interface we can use to describe these quirks. Paolo > Paolo > > -- Regards, Atish
Re: [PATCH] disas/riscv: Further correction to LUI disassembly
On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajo...@ventanamicro.com wrote:
On Mon, Jul 31, 2023 at 11:33:20AM -0700, Richard Bagley wrote:
The recent commit 36df75a0a9 corrected one aspect of LUI disassembly
by recovering the immediate argument from the result of LUI with a
shift right by 12. However, the shift right will left-fill with the
sign. By applying a mask we recover an unsigned representation of the
20-bit field (which includes a sign bit).
Example:
0xf000 >> 12 = 0x
0xf000 >> 12 & 0xf = 0x000f
Fixes: 36df75a0a9 ("riscv/disas: Fix disas output of upper immediates")
Signed-off-by: Richard Bagley
---
disas/riscv.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 4023e3fc65..690eb4a1ac 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4723,9 +4723,12 @@ static void format_inst(char *buf, size_t buflen, size_t
tab, rv_decode *dec)
break;
case 'U':
fmt++;
-snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12);
-append(buf, tmp, buflen);
-if (*fmt == 'o') {
+if (*fmt == 'i') {
+snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12 & 0xf);
Why are we correcting LUI's output, but still outputting sign-extended
values for AUIPC?
We can't assemble 'auipc a1, 0x' or 'auipc a1, -1' without getting
Error: lui expression not in range 0..1048575
(and additionally for 0x)
Error: value of 0000 too large for field of 4 bytes at
either.
(I see that the assembler's error messages state 'lui', but I was trying
'auipc'.)
I'm using as from gnu binutils 2.40.0.20230214.
(And, FWIW, I agree with Richard Henderson that these instructions should
accept negative values.)
I'm kind of lost here, and you saying binutils rejects this syntax? If
that's the case it's probably just an oversight, can you file a bug in
binutils land so folks can see?
Thanks,
drew
+append(buf, tmp, buflen);
+} else if (*fmt == 'o') {
+snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12);
+append(buf, tmp, buflen);
while (strlen(buf) < tab * 2) {
append(buf, " ", buflen);
}
--
2.34.1
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote:
On 8/8/23 17:52, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right, its been frozen since April though and with support trickling in
rest of tooling it becomes harder to test.
I don't know what exactly QEMU's policy is on this ?
IIUC we'd historically marked stuff as non-experimental when it's frozen, largely because
ratification is such a nebulous process. There's obviously risk there, but there's risk to
anything. Last I can find is 260b594d8a ("RISC-V: Add Zawrs ISA extension support"),
which specifically calls out Zawrs as frozen and IIUC adds support without the "x-"
prefix.
If that's the case then I think it's sensible to remove the 'experimental'
status
of zicond as well.
I can't find anything written down about it, though...
As soon as we agree on an official policy I'll do a doc update. Thanks,
Thanks. We should probably give Alistair some time to chime in, it's
still pretty early there.
Daniel
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right, its been frozen since April though and with support trickling in
rest of tooling it becomes harder to test.
I don't know what exactly QEMU's policy is on this ?
IIUC we'd historically marked stuff as non-experimental when it's
frozen, largely because ratification is such a nebulous process.
There's obviously risk there, but there's risk to anything. Last I can
find is 260b594d8a ("RISC-V: Add Zawrs ISA extension support"), which
specifically calls out Zawrs as frozen and IIUC adds support without the
"x-" prefix.
I can't find anything written down about it, though...
Re: riscv kvm breakage
On Tue, 11 Jul 2023 09:43:48 PDT (-0700), Richard Henderson wrote:
Hiya,
This breakage crept in while cross-riscv64-system was otherwise broken in
configure:
https://gitlab.com/qemu-project/qemu/-/jobs/4633277557#L4165
../target/riscv/kvm.c:209:38: error: ‘KVM_RISCV_ISA_EXT_ZICBOZ’ undeclared here
(not in a
function); did you mean ‘KVM_RISCV_ISA_EXT_ZICBOM’?
209 | KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
| ^~~~
../target/riscv/kvm.c:205:20: note: in definition of macro ‘KVM_EXT_CFG’
205 | .kvm_reg_id = _reg_id}
|^~~
../target/riscv/kvm.c:211:33: error: ‘KVM_RISCV_ISA_EXT_ZBB’ undeclared here
(not in a
function); did you mean ‘KVM_RISCV_ISA_EXT_MAX’?
211 | KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
| ^
../target/riscv/kvm.c:205:20: note: in definition of macro ‘KVM_EXT_CFG’
205 | .kvm_reg_id = _reg_id}
|^~~
../target/riscv/kvm.c:212:37: error: ‘KVM_RISCV_ISA_EXT_SSAIA’ undeclared here
(not in a
function); did you mean ‘KVM_RISCV_ISA_EXT_SSTC’?
212 | KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
| ^~~
../target/riscv/kvm.c:205:20: note: in definition of macro ‘KVM_EXT_CFG’
205 | .kvm_reg_id = _reg_id}
|^~~
In file included from /usr/riscv64-linux-gnu/include/rpc/netdb.h:42,
from /usr/riscv64-linux-gnu/include/netdb.h:32,
from /builds/qemu-project/qemu/include/sysemu/os-posix.h:34,
from /builds/qemu-project/qemu/include/qemu/osdep.h:151,
from ../target/riscv/kvm.c:19:
../target/riscv/kvm.c:288:44: error: ‘struct kvm_riscv_config’ has no member
named
‘zicboz_block_size’; did you mean ‘zicbom_block_size’?
288 | .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
|^
Can someone have a look asap? Thanks,
+Phillippe and Michael, there's already a discussion on IRC and sounds
like there's a fix?
r~
Re: [PATCH 1/1] linux-user: add support for big endian variants of riscv
On Fri, 30 Jun 2023 04:14:09 PDT (-0700), rory.opensou...@gmail.com wrote:
RISCV architecture supports an optional big endian mode of operation.
In this mode, data accesses are treated as big endian, while code is
always in little endian format. This is similar to how the ARM
architecture treats it's optional bi-endian support. This patch adds
support for big endian RISCV operation to linux-user.
We don't have BE support in Linux yet. IIRC we've had some other
linux-user stuff go in with a "we'll change it to match whatever uABI
Linux ends up with" sort of caveat, but I might be mistaken. I'm not
opposed to doing that sort of thing for BE as well. I don't remember
what the right way to indicate that is, though.
Signed-off-by: rory.opensou...@gmail.com
---
configs/targets/riscv64be-linux-user.mak| 7 +++
configure | 1 +
linux-user/elfload.c| 10 ++
linux-user/include/host/riscv/host-signal.h | 3 +++
linux-user/riscv/signal.c | 5 +
linux-user/riscv/target_syscall.h | 8
scripts/probe-gdb-support.py| 4 ++--
scripts/qemu-binfmt-conf.sh | 12 ++--
target/riscv/cpu.c | 5 +
target/riscv/translate.c| 13 +
10 files changed, 64 insertions(+), 4 deletions(-)
create mode 100644 configs/targets/riscv64be-linux-user.mak
diff --git a/configs/targets/riscv64be-linux-user.mak
b/configs/targets/riscv64be-linux-user.mak
new file mode 100644
index 00..f22f5f0971
--- /dev/null
+++ b/configs/targets/riscv64be-linux-user.mak
@@ -0,0 +1,7 @@
+TARGET_ARCH=riscv64
+TARGET_BASE_ARCH=riscv
+TARGET_ABI_DIR=riscv
+TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configure b/configure
index 2b41c49c0d..90795a0e9f 100755
--- a/configure
+++ b/configure
@@ -1190,6 +1190,7 @@ fi
: ${cross_prefix_ppc64="powerpc64-linux-gnu-"}
: ${cross_prefix_ppc64le="$cross_prefix_ppc64"}
: ${cross_prefix_riscv64="riscv64-linux-gnu-"}
+: ${cross_prefix_riscv64be="riscv64be-linux-gnu-"}
: ${cross_prefix_s390x="s390x-linux-gnu-"}
: ${cross_prefix_sh4="sh4-linux-gnu-"}
: ${cross_prefix_sparc64="sparc64-linux-gnu-"}
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 9a2ec568b0..e0204c7069 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1681,8 +1681,18 @@ static void elf_core_copy_regs(target_elf_gregset_t
*regs,
#ifdef TARGET_RISCV32
#define ELF_CLASS ELFCLASS32
+#if TARGET_BIG_ENDIAN
+#define ELF_PLATFORM "riscv32be"
+#else
+#define ELF_PLATFORM "riscv32"
+#endif
#else
#define ELF_CLASS ELFCLASS64
+#if TARGET_BIG_ENDIAN
+#define ELF_PLATFORM "riscv64be"
+#else
+#define ELF_PLATFORM "riscv64"
+#endif
#endif
#define ELF_HWCAP get_elf_hwcap()
diff --git a/linux-user/include/host/riscv/host-signal.h
b/linux-user/include/host/riscv/host-signal.h
index decacb2325..b3f2735261 100644
--- a/linux-user/include/host/riscv/host-signal.h
+++ b/linux-user/include/host/riscv/host-signal.h
@@ -38,6 +38,9 @@ static inline bool host_signal_write(siginfo_t *info,
host_sigcontext *uc)
*/
const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc);
uint16_t insn = pinsn[0];
+#if TARGET_BIG_ENDIAN
+insn = (insn << 8) | (insn >> 8);
+#endif
/* 16-bit instructions */
switch (insn & 0xe003) {
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index eaa168199a..1d9e3413fb 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -199,8 +199,13 @@ void setup_sigtramp(abi_ulong sigtramp_page)
uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 8, 0);
assert(tramp != NULL);
+#if TARGET_BIG_ENDIAN
+__put_user(0x9308b008, tramp + 0); /* li a7, 139 = __NR_rt_sigreturn */
+__put_user(0x7300, tramp + 1); /* ecall */
+#else
__put_user(0x08b00893, tramp + 0); /* li a7, 139 = __NR_rt_sigreturn */
__put_user(0x0073, tramp + 1); /* ecall */
+#endif
default_rt_sigreturn = sigtramp_page;
unlock_user(tramp, sigtramp_page, 8);
diff --git a/linux-user/riscv/target_syscall.h
b/linux-user/riscv/target_syscall.h
index 7601f10c28..88c0ac1351 100644
--- a/linux-user/riscv/target_syscall.h
+++ b/linux-user/riscv/target_syscall.h
@@ -44,10 +44,18 @@ struct target_pt_regs {
};
#ifdef TARGET_RISCV32
+#if TARGET_BIG_ENDIAN
+#define UNAME_MACHINE "riscv32be"
+#else
#define UNAME_MACHINE "riscv32"
+#endif
#define UNAME_MINIMUM_RELEASE "5.4.0"
#else
+#if TARGET_BIG_ENDIAN
+#define UNAME_MACHINE "riscv64be"
+#else
#define UNAME_MACHINE "riscv64"
+#endif
#define UNAME_MINIMUM_RELEASE "4.15.0"
#endif
diff --git a/scripts/probe-gdb-support.py b/scripts/probe-gdb-support.py
index 5755255966..a1e0905a10 100644
---
Re: [RFC v3] linux-user/riscv: Add syscall riscv_hwprobe
__put_user(-1, >key);
> +break;
> +}
> +}
> +}
> +
> +static int cpu_set_valid(abi_long arg3, abi_long arg4)
> +{
> +int ret, i, tmp;
> +size_t host_mask_size, target_mask_size;
> +unsigned long *host_mask;
> +
> +/*
> + * cpu_set_t represent CPU masks as bit masks of type unsigned long *.
> + * arg3 contains the cpu count.
> + */
> +tmp = (8 * sizeof(abi_ulong));
> +target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong);
> +host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) &
> + ~(sizeof(*host_mask) - 1);
> +
> +host_mask = alloca(host_mask_size);
> +
> +ret = target_to_host_cpu_mask(host_mask, host_mask_size,
> + arg4, target_mask_size);
> +if (ret != 0) {
> +return ret;
> +}
> +
> +for (i = 0 ; i < host_mask_size / sizeof(*host_mask); i++) {
> +if (host_mask[i] != 0) {
> +return 0;
> +}
> +}
> +return -TARGET_EINVAL;
> +}
> +
> +static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1,
> + abi_long arg2, abi_long arg3,
> + abi_long arg4, abi_long arg5)
> +{
> +int ret;
> +struct riscv_hwprobe *host_pairs;
> +
> +/* flags must be 0 */
> +if (arg5 != 0) {
> +return -TARGET_EINVAL;
> +}
> +
> +/* check cpu_set */
> +if (arg3 != 0) {
> +ret = cpu_set_valid(arg3, arg4);
> +if (ret != 0) {
> +return ret;
> +}
> +} else if (arg4 != 0) {
> +return -TARGET_EINVAL;
> +}
> +
> +/* no pairs */
> +if (arg2 == 0) {
> +return 0;
> +}
> +
> +host_pairs = lock_user(VERIFY_WRITE, arg1,
> + sizeof(*host_pairs) * (size_t)arg2, 0);
> +if (host_pairs == NULL) {
> +return -TARGET_EFAULT;
> +}
> +risc_hwprobe_fill_pairs(cpu_env, host_pairs, arg2);
> +unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2);
> +return 0;
> +}
> +#endif /* TARGET_NR_riscv_hwprobe */
> +
> #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root)
> _syscall2(int, pivot_root, const char *, new_root, const char *, put_old)
> #endif
> @@ -13571,6 +13712,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env,
> int num, abi_long arg1,
> return ret;
> #endif
>
> +#if defined(TARGET_NR_riscv_hwprobe)
> +case TARGET_NR_riscv_hwprobe:
> +return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5);
> +#endif
> +
> default:
> qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num);
> return -TARGET_ENOSYS;
> --
> 2.39.2
Reviewed-by: Palmer Dabbelt
riscv_hwprobe() hasn't been released yet, but it's in Linus' tree so
unless something unforseen happens it should show up in 6.4 in a few
weeks.
Re: [PATCH v3] linux-user: Add /proc/cpuinfo handler for RISC-V
On Wed, 03 May 2023 08:30:12 PDT (-0700), sch...@suse.de wrote:
From 912af433fa5d93ce81d2054135ed475ab7462d2d Mon Sep 17 00:00:00 2001
From: Andreas Schwab
Date: Tue, 18 Apr 2023 11:54:01 +0200
Signed-off-by: Andreas Schwab
---
v3: fix isa order
linux-user/syscall.c | 55 ++--
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 69f740ff98..5207259b56 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8231,7 +8231,8 @@ void target_exception_dump(CPUArchState *env, const char
*fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
-defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8309,6 +8310,56 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+int i, num_cpus;
+char isa[32];
+
+#if defined(TARGET_RISCV32)
+strcpy (isa, "rv32");
+#endif
+#if defined(TARGET_RISCV64)
+strcpy (isa, "rv64");
+#endif
+i = strlen (isa);
+if (riscv_has_ext (cpu_env, RVI))
+isa[i++] = 'i';
+if (riscv_has_ext (cpu_env, RVE))
+isa[i++] = 'e';
+if (riscv_has_ext (cpu_env, RVM))
+isa[i++] = 'm';
+if (riscv_has_ext (cpu_env, RVA))
+isa[i++] = 'a';
+if (riscv_has_ext (cpu_env, RVF))
+isa[i++] = 'f';
+if (riscv_has_ext (cpu_env, RVD))
+isa[i++] = 'd';
+if (riscv_has_ext (cpu_env, RVC))
+isa[i++] = 'c';
+if (riscv_has_ext (cpu_env, RVV))
+isa[i++] = 'v';
+isa[i] = 0;
+
+num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+for (i = 0; i < num_cpus; i++) {
+dprintf(fd, "processor\t: %d\n", i);
+dprintf(fd, "hart\t\t: %d\n", i);
+dprintf(fd, "isa\t\t: %s\n", isa);
+#if defined(TARGET_RISCV32)
+dprintf(fd, "mmu\t\t: sv32\n");
+#endif
+#if defined(TARGET_RISCV64)
+dprintf(fd, "mmu\t\t: sv57\n");
+#endif
+dprintf(fd, "mvendorid\t: 0x0\n");
+dprintf(fd, "marchid\t\t: 0x0\n");
+dprintf(fd, "mimpid\t\t: 0x0\n\n");
+}
+return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8333,7 +8384,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
Reviewed-by: Palmer Dabbelt
Thanks!
Re: [PATCH v2] linux-user: Add /proc/cpuinfo handler for RISC-V
On Wed, 03 May 2023 04:20:09 PDT (-0700), sch...@suse.de wrote:
Signed-off-by: Andreas Schwab
---
v2: dynmically compute the isa string
linux-user/syscall.c | 55 ++--
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 69f740ff98..6df138c8b6 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8231,7 +8231,8 @@ void target_exception_dump(CPUArchState *env, const char
*fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
-defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8309,6 +8310,56 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+int i, num_cpus;
+char isa[32];
+
+#if defined(TARGET_RISCV32)
+strcpy (isa, "rv32");
+#endif
+#if defined(TARGET_RISCV64)
+strcpy (isa, "rv64");
+#endif
+i = strlen (isa);
+if (riscv_has_ext (cpu_env, RVI))
+isa[i++] = 'i';
+if (riscv_has_ext (cpu_env, RVE))
+isa[i++] = 'e';
+if (riscv_has_ext (cpu_env, RVM))
+isa[i++] = 'm';
+if (riscv_has_ext (cpu_env, RVA))
+isa[i++] = 'a';
+if (riscv_has_ext (cpu_env, RVF))
+isa[i++] = 'f';
+if (riscv_has_ext (cpu_env, RVD))
+isa[i++] = 'd';
+if (riscv_has_ext (cpu_env, RVV))
+isa[i++] = 'v';
+if (riscv_has_ext (cpu_env, RVC))
+isa[i++] = 'c';
Oddly enough, pretty much the only "must" in the ISA string rules is the
ordering of extensions and it's C before V
\caption{Standard ISA extension names. The table also defines the
canonical order in which extension names must appear in the name
string, with top-to-bottom in table indicating first-to-last in the
name string, e.g., RV32IMACV is legal, whereas RV32IMAVC is not.}
I guess that assumes figure captions are normative? I'm not sure we get
into that level of detail, though.
+isa[i] = 0;
+
+num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+for (i = 0; i < num_cpus; i++) {
+dprintf(fd, "processor\t: %d\n", i);
+dprintf(fd, "hart\t\t: %d\n", i);
+dprintf(fd, "isa\t\t: %s\n", isa);
+#if defined(TARGET_RISCV32)
+dprintf(fd, "mmu\t\t: sv32\n");
+#endif
+#if defined(TARGET_RISCV64)
+dprintf(fd, "mmu\t\t: sv57\n");
+#endif
+dprintf(fd, "mvendorid\t: 0x0\n");
+dprintf(fd, "marchid\t\t: 0x0\n");
+dprintf(fd, "mimpid\t\t: 0x0\n\n");
+}
+return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8333,7 +8384,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
Aside from that,
Reviewed-by: Palmer Dabbelt
Thanks!
Re: [PATCH] linux-user: Add /proc/cpuinfo handler for RISC-V
On Wed, 03 May 2023 04:13:55 PDT (-0700), sch...@suse.de wrote: On Mai 02 2023, Andreas Schwab wrote: None of the currently defined cpus are non-GC cpus (except sifive_e, but that is not suitable for user-space anyway), and there doesn't appear to be any properties defined for changing the supported extensions. Actually, modifying the extensions is possible for the base cpus (rv32 and rv64). Ya, though I think you're right about the VA width in userspace.
Re: [PATCH] linux-user: Add /proc/cpuinfo handler for RISC-V
On Tue, 02 May 2023 06:44:00 PDT (-0700), sch...@suse.de wrote:
Signed-off-by: Andreas Schwab
---
linux-user/syscall.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 69f740ff98..c72456a34b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8231,7 +8231,8 @@ void target_exception_dump(CPUArchState *env, const char
*fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
-defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8309,6 +8310,31 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+int i, num_cpus;
+
+num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+for (i = 0; i < num_cpus; i++) {
+dprintf(fd, "processor\t: %d\n", i);
+dprintf(fd, "hart\t\t: %d\n", i);
+#if defined(TARGET_RISCV32)
+dprintf(fd, "isa\t\t: rv32imafdc\n");
+dprintf(fd, "mmu\t\t: sv32\n");
+#endif
+#if defined(TARGET_RISCV64)
+dprintf(fd, "isa\t\t: rv64imafdc\n");
+dprintf(fd, "mmu\t\t: sv57\n");
Unless I'm misunderstanding something, we've got support for both
non-sv57 system (via sv* CPU properties) and non-GC systems (also via
CPU properties). Not sure how much userspace cares about that, but at
least dropping FD when those instructions aren't emulated by QEMEU seems
reasonable.
+#endif
+dprintf(fd, "mvendorid\t: 0x0\n");
+dprintf(fd, "marchid\t\t: 0x0\n");
+dprintf(fd, "mimpid\t\t: 0x0\n\n");
+}
+return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8333,7 +8359,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
Aside from that this looks great. Thanks for fixing this, it's been a
headache for folks for a while.
Re: [PATCH 0/2] target/riscv: RVV 1-fill tail element changes
On Thu, 27 Apr 2023 13:57:06 PDT (-0700), dbarb...@ventanamicro.com wrote: Hi, This series makes changes in vext_set_tail_elements_1s() to be a little nicer to the emulation. First patch makes the function a no-op when vta == 0. Aside from the logic simplification we also have a little performance boost. Second patch makes the function debug only. The logic is explained in the commit message, but long story short: we don't have to implement any tail-agnostic policy at all to be spec compliant, but this function has its uses for debug purposes, so keeping it as a debug option allow users to disable it on demand. Patches are based on top of Alistair's riscv-to-apply.next. Daniel Henrique Barboza (2): target/riscv/vector_helper.c: skip set tail when vta is zero target/riscv/vector_helper.c: make vext_set_tail_elems_1s() debug only target/riscv/vector_helper.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) Reviewed-by: Palmer Dabbelt Though this made me think: it'd be nice to have some sort of "aggressively do odd things for VTA/VMA" mode in QEMU, as that could help shake out bugs in software.
Re: [PATCH v2 01/10] contrib/gitdm: Add Rivos Inc to the domain map
On Fri, 10 Mar 2023 10:03:23 PST (-0800), alex.ben...@linaro.org wrote: Whatever they are up to a number of people for the company are contributing to QEMU so lets group them together. Signed-off-by: Alex Bennée Cc: Atish Patra Cc: Dao Lu Cc: Andrew Bresticker Cc: Palmer Dabbelt Cc: Vineet Gupta --- contrib/gitdm/domain-map | 1 + 1 file changed, 1 insertion(+) diff --git a/contrib/gitdm/domain-map b/contrib/gitdm/domain-map index 8913a886c9..7a8077e241 100644 --- a/contrib/gitdm/domain-map +++ b/contrib/gitdm/domain-map @@ -32,6 +32,7 @@ oracle.com Oracle proxmox.com Proxmox quicinc.com Qualcomm Innovation Center redhat.com Red Hat +rivosinc.comRivos Inc rt-rk.com RT-RK samsung.com Samsung siemens.com Siemens Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Thanks!
[PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool
From: Alexandre Ghiti
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Message-ID: <20230303131252.892893-3-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3106f96212..d93d481bd6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1141,16 +1141,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
-static const char valid_vm_1_10_32[16] = {
-[VM_1_10_MBARE] = 1,
-[VM_1_10_SV32] = 1
+static const bool valid_vm_1_10_32[16] = {
+[VM_1_10_MBARE] = true,
+[VM_1_10_SV32] = true
};
-static const char valid_vm_1_10_64[16] = {
-[VM_1_10_MBARE] = 1,
-[VM_1_10_SV39] = 1,
-[VM_1_10_SV48] = 1,
-[VM_1_10_SV57] = 1
+static const bool valid_vm_1_10_64[16] = {
+[VM_1_10_MBARE] = true,
+[VM_1_10_SV39] = true,
+[VM_1_10_SV48] = true,
+[VM_1_10_SV57] = true
};
/* Machine Information Registers */
@@ -1230,7 +1230,7 @@ static RISCVException read_mstatus(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
-static int validate_vm(CPURISCVState *env, target_ulong vm)
+static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
if (riscv_cpu_mxl(env) == MXL_RV32) {
return valid_vm_1_10_32[vm & 0xf];
@@ -2669,7 +2669,8 @@ static RISCVException read_satp(CPURISCVState *env, int
csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
-target_ulong vm, mask;
+target_ulong mask;
+bool vm;
if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE;
--
2.39.2
[PULL 05/22] disas/riscv Fix ctzw disassemble
From: Ivan Klokov
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230217151459.54649-1-ivan.klo...@syntacore.com>
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..544558 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
--
2.39.2
[PULL 01/22] target/riscv: implement Zicboz extension
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Block Zero extension, Zicboz. It
uses the cbo.zero instruction that, as with all CBO instructions that
will be added later, needs to be implemented in an overlap group with
the LQ instruction due to overlapping patterns.
cbo.zero throws a Illegal Instruction/Virtual Instruction exception
depending on CSR state. This is also the case for the remaining cbo
instructions we're going to add next, so create a check_zicbo_envcfg()
that will be used by all Zicbo[mz] instructions.
[1]
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf
Reviewed-by: Richard Henderson
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++
target/riscv/cpu.h | 2 +
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 10 ++-
target/riscv/insn_trans/trans_rvzicbo.c.inc | 30 +
target/riscv/op_helper.c| 68 +
target/riscv/translate.c| 1 +
7 files changed, 117 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5bc0005cc7..ab6c127859 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -75,6 +75,7 @@ struct isa_ext_data {
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
+ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
@@ -1167,6 +1168,9 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
+DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
+
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* Vendor-specific custom extensions */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 665b4c60b0..73c9832fb7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -434,6 +434,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+bool ext_icboz;
bool ext_zicond;
bool ext_zihintpause;
bool ext_smstateen;
@@ -486,6 +487,7 @@ struct RISCVCPUConfig {
char *vext_spec;
uint16_t vlen;
uint16_t elen;
+uint16_t cboz_blocksize;
bool mmu;
bool pmp;
bool epmp;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0497370afd..ce165821b8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -97,6 +97,9 @@ DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64)
+/* Cache-block operations */
+DEF_HELPER_2(cbo_zero, void, env, tl)
+
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fb537e922e..a471adcea0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -179,7 +179,15 @@ sraw 010 . . 101 . 0111011 @r
# *** RV128I Base Instruction Set (in addition to RV64I) ***
ldu . 111 . 011 @i
-lq . 010 . 000 @i
+{
+ [
+# *** RV32 Zicboz Standard Extension ***
+cbo_zero 000 00100 . 010 0 000 @sfence_vm
+ ]
+
+ # *** RVI128 lq ***
+ lq . 010 . 000 @i
+}
sq . 100 . 0100011 @s
addid . 000 . 1011011 @i
sllid00 .. . 001 . 1011011 @sh6
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
new file mode 100644
index 00..feabc28342
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -0,0 +1,30 @@
+/*
+ * RISC-V translation routines for the RISC-V CBO Extension.
+ *
+ * Copyright (c) 2021 Philipp Tomsich, philipp.toms...@vrull.eu
+ *
[PULL 12/22] riscv: Allow user to set the satp mode
From: Alexandre Ghiti
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply setting the
"highest" supported mode and the bare mode is always supported.
You can set the satp mode using the new properties "sv32", "sv39", "sv48",
"sv57" and "sv64" as follows:
-cpu rv64,sv57=on # Linux will boot using sv57 scheme
-cpu rv64,sv39=on # Linux will boot using sv39 scheme
-cpu rv64,sv57=off # Linux will boot using sv48 scheme
-cpu rv64 # Linux will boot using sv57 scheme by default
We take the highest level set by the user:
-cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme
We make sure that invalid configurations are rejected:
-cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are
# enabled
We accept "redundant" configurations:
-cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme
And contradictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Frank Chang
Message-ID: <20230303131252.892893-4-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 214 +
target/riscv/cpu.h | 21 +
target/riscv/csr.c | 12 ++-
3 files changed, 240 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1c4d8aaa74..e1e8057836 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -28,6 +28,7 @@
#include "time_helper.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "qemu/error-report.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@@ -249,6 +250,82 @@ static void set_vext_version(CPURISCVState *env, int
vext_ver)
env->vext_ver = vext_ver;
}
+#ifndef CONFIG_USER_ONLY
+static uint8_t satp_mode_from_str(const char *satp_mode_str)
+{
+if (!strncmp(satp_mode_str, "mbare", 5)) {
+return VM_1_10_MBARE;
+}
+
+if (!strncmp(satp_mode_str, "sv32", 4)) {
+return VM_1_10_SV32;
+}
+
+if (!strncmp(satp_mode_str, "sv39", 4)) {
+return VM_1_10_SV39;
+}
+
+if (!strncmp(satp_mode_str, "sv48", 4)) {
+return VM_1_10_SV48;
+}
+
+if (!strncmp(satp_mode_str, "sv57", 4)) {
+return VM_1_10_SV57;
+}
+
+if (!strncmp(satp_mode_str, "sv64", 4)) {
+return VM_1_10_SV64;
+}
+
+g_assert_not_reached();
+}
+
+uint8_t satp_mode_max_from_map(uint32_t map)
+{
+/* map here has at least one bit set, so no problem with clz */
+return 31 - __builtin_clz(map);
+}
+
+const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
+{
+if (is_32_bit) {
+switch (satp_mode) {
+case VM_1_10_SV32:
+return "sv32";
+case VM_1_10_MBARE:
+return "none";
+}
+} else {
+switch (satp_mode) {
+case VM_1_10_SV64:
+return "sv64";
+case VM_1_10_SV57:
+return "sv57";
+case VM_1_10_SV48:
+return "sv48";
+case VM_1_10_SV39:
+return "sv39";
+case VM_1_10_MBARE:
+return "none";
+}
+}
+
+g_assert_not_reached();
+}
+
+/* Sets the satp mode to the max supported */
+static void set_satp_mode_default_map(RISCVCPU *cpu)
+{
+bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+
+if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
+cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57));
+} else {
+cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE);
+}
+}
+#endif
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
@@ -918,6 +995,87 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
set_misa(env, env->misa_mxl, ext);
}
+#ifndef CONFIG_USER_ONLY
+static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
+{
+bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
+uint8_t satp_mode_max;
+
+if (cpu->cfg.satp_mode.map == 0) {
+if (cpu->cfg.satp_mode.init == 0) {
+/* If unset by the user, we fallback to the default satp mode. */
+set_satp_mode_default_map(cpu);
+
[PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
From: Sunil V L
ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields
in the RISCVVirtState structure and initialize with default values.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-2-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 5 +
include/hw/riscv/virt.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 26eb81d036..5a059489b5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -49,6 +49,7 @@
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+#include "hw/acpi/aml-build.h"
/*
* The virt machine physical address space used by some of the devices
@@ -1528,6 +1529,10 @@ static void virt_machine_init(MachineState *machine)
static void virt_machine_instance_init(Object *obj)
{
+RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
+s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
}
static char *virt_get_aia_guests(Object *obj, Error **errp)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b3d26135c0..6c7885bf89 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -56,6 +56,8 @@ struct RISCVVirtState {
bool have_aclint;
RISCVVirtAIAType aia_type;
int aia_guests;
+char *oem_id;
+char *oem_table_id;
};
enum {
--
2.39.2
[PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
From: Anup Patel
The cbom-block-size fdt property property is used to inform the OS about
the blocksize in bytes for the Zicbom cache operations. Linux documents
it in Documentation/devicetree/bindings/riscv/cpus.yaml
as:
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicbom cache operations.
cboz-block-size has the same role but for the Zicboz extension, i.e.
informs the size in bytes for Zicboz cache operations. Linux support
for it is under review/approval in [1]. Patch 3 of that series describes
cboz-block-size as:
riscv,cboz-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicboz cache operations.
[1] https://lore.kernel.org/all/20230224162631.405473-1-ajo...@ventanamicro.com/
Cc: Andrew Jones
Signed-off-by: Anup Patel
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Bin Meng
Message-ID: <20230302091406.407824-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4f8191860b..7f70fa11a1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -249,6 +249,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
+
+if (cpu_ptr->cfg.ext_icbom) {
+qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
+ cpu_ptr->cfg.cbom_blocksize);
+}
+
+if (cpu_ptr->cfg.ext_icboz) {
+qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
+ cpu_ptr->cfg.cboz_blocksize);
+}
+
qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
--
2.39.2
[PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
From: Christoph Muellner
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 282e41aa3e..73d5d1b045 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -134,6 +134,7 @@ addi . 000 . 0010011 @i
slti . 010 . 0010011 @i
sltiu . 011 . 0010011 @i
xori . 100 . 0010011 @i
+# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
ori . 110 . 0010011 @i
andi . 111 . 0010011 @i
slli 0. ... 001 . 0010011 @sh
--
2.39.2
[PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type'
From: Alexandre Ghiti
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Message-ID: <20230303131252.892893-6-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f70fa11a1..26eb81d036 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -228,8 +228,9 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
int cpu;
uint32_t cpu_phandle;
MachineState *ms = MACHINE(s);
-char *name, *cpu_name, *core_name, *intc_name;
+char *name, *cpu_name, *core_name, *intc_name, *sv_name;
bool is_32_bit = riscv_is_32bit(>soc[0]);
+uint8_t satp_mode_max;
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
RISCVCPU *cpu_ptr = >soc[socket].harts[cpu];
@@ -239,13 +240,15 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
-if (cpu_ptr->cfg.mmu) {
-qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
-(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
-} else {
-qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
-"riscv,none");
-}
+
+satp_mode_max = satp_mode_max_from_map(
+s->soc[socket].harts[cpu].cfg.satp_mode.map);
+sv_name = g_strdup_printf("riscv,%s",
+ satp_mode_str(satp_mode_max, is_32_bit));
+qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
+g_free(sv_name);
+
+
name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.39.2
[PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure
From: Sunil V L
Add basic ACPI infrastructure for RISC-V with below tables.
1) DSDT with below basic objects
- CPUs
- fw_cfg
2) FADT revision 6 with HW_REDUCED flag
3) XSDT
4) RSDP
Add this functionality in a new file virt-acpi-build.c and enable
building this infrastructure.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-5-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 304 +
include/hw/riscv/virt.h| 1 +
4 files changed, 307 insertions(+)
create mode 100644 hw/riscv/virt-acpi-build.c
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 4550b3b938..6528ebfa3a 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV_VIRT
select VIRTIO_MMIO
select FW_CFG_DMA
select PLATFORM_BUS
+select ACPI
config SHAKTI_C
bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index ab6cae57ea..2f7ee81be3 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -9,5 +9,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true:
files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true:
files('microchip_pfsoc.c'))
+riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
hw_arch += {'riscv': riscv_ss}
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
new file mode 100644
index 00..d6947fdc74
--- /dev/null
+++ b/hw/riscv/virt-acpi-build.c
@@ -0,0 +1,304 @@
+/*
+ * Support for generating ACPI tables and passing them to Guests
+ *
+ * RISC-V virt ACPI generation
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ * Copyright (C) 2021-2023 Ventana Micro Systems Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/utils.h"
+#include "qapi/error.h"
+#include "sysemu/reset.h"
+#include "migration/vmstate.h"
+#include "hw/riscv/virt.h"
+
+#define ACPI_BUILD_TABLE_SIZE 0x2
+
+typedef struct AcpiBuildState {
+/* Copy of table in RAM (for patching) */
+MemoryRegion *table_mr;
+MemoryRegion *rsdp_mr;
+MemoryRegion *linker_mr;
+/* Is table patched? */
+bool patched;
+} AcpiBuildState;
+
+static void acpi_align_size(GArray *blob, unsigned align)
+{
+/*
+ * Align size to multiple of given size. This reduces the chance
+ * we need to change size in the future (breaking cross version migration).
+ */
+g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
+}
+
+static void riscv_acpi_madt_add_rintc(uint32_t uid,
+ const CPUArchIdList *arch_ids,
+ GArray *entry)
+{
+uint64_t hart_id = arch_ids->cpus[uid].arch_id;
+
+build_append_int_noprefix(entry, 0x18, 1); /* Type */
+build_append_int_noprefix(entry, 20, 1); /* Length */
+build_append_int_noprefix(entry, 1, 1); /* Version */
+build_append_int_noprefix(entry, 0, 1); /* Reserved */
+build_append_int_noprefix(entry, 0x1, 4);/* Flags*/
+build_append_int_noprefix(entry, hart_id, 8);/* Hart ID */
+build_append_int_noprefix(entry, uid, 4);/* ACPI Processor UID */
+}
+
+static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
+{
+MachineClass *mc = MACHINE_GET_CLASS(s);
+MachineState *ms = MACHINE(s);
+const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+
+for (int i = 0; i < arch_ids->len; i++) {
+Aml *dev;
+GArray *madt_buf = g_array_new(0, 1, 1);
+
+dev = aml_device("C%.03X", i);
+aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
+
[PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state
From: Mayuresh Chitale
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the
CPU state. However APLIC, IMSIC and ACLINT contain registers and states
which are specific to physical hart Ids. The hart Ids in any given system
might be sparse and hence calls to qemu_get_cpu need to be replaced by
cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-3-mchit...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/intc/riscv_aclint.c | 16
hw/intc/riscv_aplic.c | 4 ++--
hw/intc/riscv_imsic.c | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index eee04643cb..b466a6abaf 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque,
hwaddr addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
-CPUState *cpu = qemu_get_cpu(hartid);
+CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr
addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
-CPUState *cpu = qemu_get_cpu(hartid);
+CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -231,7 +231,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr
addr,
/* Check if timer interrupt is triggered for each hart. */
for (i = 0; i < mtimer->num_harts; i++) {
-CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
+CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
continue;
@@ -292,7 +292,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev,
Error **errp)
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
-RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
error_report("MTIP already claimed");
exit(1);
@@ -372,7 +372,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr
size,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
-CPUState *cpu = qemu_get_cpu(hartid_base + i);
+CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
riscv_aclint_mtimer_callback *cb =
@@ -407,7 +407,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr
addr,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
-CPUState *cpu = qemu_get_cpu(hartid);
+CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -430,7 +430,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr
addr, uint64_t value,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
-CPUState *cpu = qemu_get_cpu(hartid);
+CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -545,7 +545,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t
hartid_base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
-CPUState *cpu = qemu_get_cpu(hartid_base + i);
+CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
qdev_connect_gpio_out(dev, i,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index cfd007e629..cd7efc4ad4 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -833,7 +833,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error
**errp)
/* Claim the CPU interrupt to be triggered by this APLIC */
for (i = 0; i < aplic-&
[PULL 00/22] Sixth RISC-V PR for 8.0
The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0:
configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46 +)
are available in the Git repository at:
https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306
for you to fetch changes up to 47fc340010335bc2549bc1f07e5fd85d86a2b9f9:
MAINTAINERS: Add entry for RISC-V ACPI (2023-03-06 11:35:08 -0800)
Sixth RISC-V PR for 8.0
* Support for the Zicbiom, ZCicboz, and Zicbop extensions.
* OpenSBI has been updated to version 1.2, see
<https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for
the release notes.
* Support for setting the virtual address width (ie, sv39/sv48/sv57) on
the command line.
* Support for ACPI on RISC-V.
Sorry for the flurry of late pull requests, but we had a few stragglers
(ACPI due to reviews and OpenSBI due to the CI failures, the others I'd
largely just missed). I don't intend on sending anything else for the
soft freeze, this is already well past late enough for me ;)
I'm not exactly sure what happened, but this tag managed to pass CI
<https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/797833683> despite
me not really doing anything to fix the timeouts -- hopefully that was
just a result of me having gotten unlucky or missing a larger timeout in
my fork, but sorry if I've managed to screw something up.
I have no merge conflicts and the tests are passing locally. I've got a
CI run here
<https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/79790>, but I
figured I'd just send this now given that I had one pass from just the
tag.
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set the satp mode
riscv: Introduce satp mode hw capabilities
riscv: Correctly set the device-tree entry 'mmu-type'
Anup Patel (1):
hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
Bin Meng (1):
roms/opensbi: Upgrade from v1.1 to v1.2
Christoph Muellner (3):
target/riscv: implement Zicboz extension
target/riscv: implement Zicbom extension
target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
Ivan Klokov (1):
disas/riscv Fix ctzw disassemble
Mayuresh Chitale (2):
target/riscv: cpu: Implement get_arch_id callback
hw: intc: Use cpu_by_arch_id to fetch CPU state
Palmer Dabbelt (1):
gitlab/opensbi: Move to docker:stable
Sunil V L (8):
hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
hw/riscv/virt: Add a switch to disable ACPI
hw/riscv/virt: Add memmap pointer to RiscVVirtState
hw/riscv/virt: Enable basic ACPI infrastructure
hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
hw/riscv/virt.c: Initialize the ACPI tables
MAINTAINERS: Add entry for RISC-V ACPI
.gitlab-ci.d/opensbi.yml | 4 +-
.gitlab-ci.d/opensbi/Dockerfile| 1 +
MAINTAINERS| 18 +-
disas/riscv.c | 2 +-
hw/intc/riscv_aclint.c | 16 +-
hw/intc/riscv_aplic.c | 4 +-
hw/intc/riscv_imsic.c | 6 +-
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 416 +
hw/riscv/virt.c| 70 -
include/hw/riscv/virt.h| 6 +
pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 117704 -> 123072 bytes
pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 115344 -> 121800 bytes
roms/opensbi | 2 +-
target/riscv/cpu.c | 303 +-
target/riscv/cpu.h | 29 ++
target/riscv/csr.c | 29 +-
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 16 +-
target/riscv/insn_trans/trans_rvzicbo.c.inc| 57
target/riscv/op_helper.c | 135
target/riscv/translate.c | 1 +
23 files changed, 1061 insertions(+), 61 deletions(-)
create mode 100644 hw/riscv/virt-acpi-build.c
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
[PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
From: Sunil V L
Add Multiple APIC Description Table (MADT) with the
RINTC structure for each cpu.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-6-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt-acpi-build.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d6947fdc74..026d1eaf88 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -32,6 +32,7 @@
#include "sysemu/reset.h"
#include "migration/vmstate.h"
#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
@@ -160,6 +161,36 @@ static void build_dsdt(GArray *table_data,
free_aml_allocator();
}
+/*
+ * ACPI spec, Revision 6.5+
+ * 5.2.12 Multiple APIC Description Table (MADT)
+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
+ * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ */
+static void build_madt(GArray *table_data,
+ BIOSLinker *linker,
+ RISCVVirtState *s)
+{
+MachineClass *mc = MACHINE_GET_CLASS(s);
+MachineState *ms = MACHINE(s);
+const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+
+AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
+.oem_table_id = s->oem_table_id };
+
+acpi_table_begin(, table_data);
+/* Local Interrupt Controller Address */
+build_append_int_noprefix(table_data, 0, 4);
+build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */
+
+/* RISC-V Local INTC structures per HART */
+for (int i = 0; i < arch_ids->len; i++) {
+riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+}
+
+acpi_table_end(linker, );
+}
+
static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
{
GArray *table_offsets;
@@ -181,6 +212,9 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_fadt_rev6(tables_blob, tables->linker, s, dsdt);
+acpi_add_table(table_offsets, tables_blob);
+build_madt(tables_blob, tables->linker, s);
+
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
--
2.39.2
[PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
From: Sunil V L
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-7-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt-acpi-build.c | 78 ++
1 file changed, 78 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 026d1eaf88..82da0a238c 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -33,6 +33,7 @@
#include "migration/vmstate.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/numa.h"
+#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x2
@@ -111,6 +112,80 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const
MemMapEntry *fw_cfg_memmap)
aml_append(scope, dev);
}
+/* RHCT Node[N] starts at offset 56 */
+#define RHCT_NODE_ARRAY_OFFSET 56
+
+/*
+ * ACPI spec, Revision 6.5+
+ * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
+ * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ */
+static void build_rhct(GArray *table_data,
+ BIOSLinker *linker,
+ RISCVVirtState *s)
+{
+MachineClass *mc = MACHINE_GET_CLASS(s);
+MachineState *ms = MACHINE(s);
+const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+size_t len, aligned_len;
+uint32_t isa_offset, num_rhct_nodes;
+RISCVCPU *cpu;
+char *isa;
+
+AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
+.oem_table_id = s->oem_table_id };
+
+acpi_table_begin(, table_data);
+
+build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */
+
+/* Time Base Frequency */
+build_append_int_noprefix(table_data,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);
+
+/* ISA + N hart info */
+num_rhct_nodes = 1 + ms->smp.cpus;
+
+/* Number of RHCT nodes*/
+build_append_int_noprefix(table_data, num_rhct_nodes, 4);
+
+/* Offset to the RHCT node array */
+build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);
+
+/* ISA String Node */
+isa_offset = table_data->len - table.table_offset;
+build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
+
+cpu = >soc[0].harts[0];
+isa = riscv_isa_string(cpu);
+len = 8 + strlen(isa) + 1;
+aligned_len = (len % 2) ? (len + 1) : len;
+
+build_append_int_noprefix(table_data, aligned_len, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+
+/* ISA string length including NUL */
+build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
+g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */
+
+if (aligned_len != len) {
+build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
+}
+
+/* Hart Info Node */
+for (int i = 0; i < arch_ids->len; i++) {
+build_append_int_noprefix(table_data, 0x, 2); /* Type */
+build_append_int_noprefix(table_data, 16, 2); /* Length */
+build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+build_append_int_noprefix(table_data, 1, 2);/* Number of offsets */
+build_append_int_noprefix(table_data, i, 4);/* ACPI Processor UID
*/
+build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+}
+
+acpi_table_end(linker, );
+}
+
/* FADT */
static void build_fadt_rev6(GArray *table_data,
BIOSLinker *linker,
@@ -215,6 +290,9 @@ static void virt_acpi_build(RISCVVirtState *s,
AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, s);
+acpi_add_table(table_offsets, tables_blob);
+build_rhct(tables_blob, tables->linker, s);
+
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
--
2.39.2
[PULL 06/22] target/riscv: cpu: Implement get_arch_id callback
From: Mayuresh Chitale
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-2-mchit...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3e8f21a47d..0ad8f94a42 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1301,6 +1301,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState
*cs, const char *xmlname)
}
#ifndef CONFIG_USER_ONLY
+static int64_t riscv_get_arch_id(CPUState *cs)
+{
+RISCVCPU *cpu = RISCV_CPU(cs);
+
+return cpu->env.mhartid;
+}
+
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
@@ -1355,6 +1362,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = _sysemu_ops;
+cc->get_arch_id = riscv_get_arch_id;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
--
2.39.2
[PULL 02/22] target/riscv: implement Zicbom extension
From: Christoph Muellner
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].
The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group as LQ and
cbo.zero due to overlapping patterns.
All these instructions can throw a Illegal Instruction/Virtual
Instruction exception, similar to the existing cbo.zero. The same
check_zicbo_envcfg() is used to handle these exceptions.
Aside from that, these instructions also need to handle page faults and
guest page faults. This is done in a new check_zicbom_access() helper.
As with Zicboz, the cache block size for Zicbom is also configurable.
Note that the spec determines that Zicbo[mp] and Zicboz can have
different cache sizes (Section 2.7 of [1]), so we also include a
'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They
are set to the same size, so unless users want to play around with the
settings both sizes will be the same.
[1]
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20230224132536.552293-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 2 +
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvzicbo.c.inc | 27 +
target/riscv/op_helper.c| 67 +
6 files changed, 106 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab6c127859..3e8f21a47d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -75,6 +75,7 @@ struct isa_ext_data {
static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
+ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
@@ -1168,6 +1169,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
+DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 73c9832fb7..b5b5425b99 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -434,6 +434,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+bool ext_icbom;
bool ext_icboz;
bool ext_zicond;
bool ext_zihintpause;
@@ -487,6 +488,7 @@ struct RISCVCPUConfig {
char *vext_spec;
uint16_t vlen;
uint16_t elen;
+uint16_t cbom_blocksize;
uint16_t cboz_blocksize;
bool mmu;
bool pmp;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ce165821b8..37b54e0991 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -98,6 +98,8 @@ DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64)
/* Cache-block operations */
+DEF_HELPER_2(cbo_clean_flush, void, env, tl)
+DEF_HELPER_2(cbo_inval, void, env, tl)
DEF_HELPER_2(cbo_zero, void, env, tl)
/* Special functions */
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a471adcea0..282e41aa3e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -181,6 +181,11 @@ sraw 010 . . 101 . 0111011 @r
ldu . 111 . 011 @i
{
[
+# *** RV32 Zicbom Standard Extension ***
+cbo_clean 000 1 . 010 0 000 @sfence_vm
+cbo_flush 000 00010 . 010 0 000 @sfence_vm
+cbo_inval 000 0 . 010 0 000 @sfence_vm
+
# *** RV32 Zicboz Standard Extension ***
cbo_zero 000 00100 . 010 0 000 @sfence_vm
]
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index feabc28342..7df9c30b58 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -16,12 +16,39 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
[PULL 13/22] riscv: Introduce satp mode hw capabilities
From: Alexandre Ghiti
Currently, the max satp mode is set with the only constraint that it must be
implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode which is incompatible with the cpu's sv39 max
capability.
So add a new bitmap to RISCVSATPMap which contains this capability and
initialize it in every XXX_cpu_init.
Finally:
- valid_vm_1_10_[32|64] constrains which satp mode the CPU can use
- the CPU hw capabilities constrains what the user may select
- the user's selection then constrains what's available to the guest
OS.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-ID: <20230303131252.892893-5-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 93 ++
target/riscv/cpu.h | 8 +++-
2 files changed, 75 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e1e8057836..1e97473af2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -313,17 +313,24 @@ const char *satp_mode_str(uint8_t satp_mode, bool
is_32_bit)
g_assert_not_reached();
}
-/* Sets the satp mode to the max supported */
-static void set_satp_mode_default_map(RISCVCPU *cpu)
+static void set_satp_mode_max_supported(RISCVCPU *cpu,
+uint8_t satp_mode)
{
bool rv32 = riscv_cpu_mxl(>env) == MXL_RV32;
+const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
-if (riscv_feature(>env, RISCV_FEATURE_MMU)) {
-cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57));
-} else {
-cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE);
+for (int i = 0; i <= satp_mode; ++i) {
+if (valid_vm[i]) {
+cpu->cfg.satp_mode.supported |= (1 << i);
+}
}
}
+
+/* Set the satp mode to the max supported */
+static void set_satp_mode_default_map(RISCVCPU *cpu)
+{
+cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
+}
#endif
static void riscv_any_cpu_init(Object *obj)
@@ -334,6 +341,13 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
+
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(RISCV_CPU(obj),
+riscv_cpu_mxl(_CPU(obj)->env) == MXL_RV32 ?
+VM_1_10_SV32 : VM_1_10_SV57);
+#endif
+
set_priv_version(env, PRIV_VERSION_1_12_0);
register_cpu_props(obj);
}
@@ -347,6 +361,9 @@ static void rv64_base_cpu_init(Object *obj)
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
+#endif
}
static void rv64_sifive_u_cpu_init(Object *obj)
@@ -355,6 +372,9 @@ static void rv64_sifive_u_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
+#endif
}
static void rv64_sifive_e_cpu_init(Object *obj)
@@ -366,6 +386,9 @@ static void rv64_sifive_e_cpu_init(Object *obj)
register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
+#endif
}
static void rv64_thead_c906_cpu_init(Object *obj)
@@ -395,6 +418,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.ext_xtheadsync = true;
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+#endif
}
static void rv128_base_cpu_init(Object *obj)
@@ -411,6 +437,9 @@ static void rv128_base_cpu_init(Object *obj)
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
+#endif
}
#else
static void rv32_base_cpu_init(Object *obj)
@@ -421,6 +450,9 @@ static void rv32_base_cpu_init(Object *obj)
register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
+#ifndef CONFIG_USER_ONLY
+set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
+#endif
}
static void rv32_sifive_u_cpu_init(Object *obj)
@@ -429,6 +461,9 @@ static void rv32_sifive_u_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | R
[PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables
From: Sunil V L
Initialize the ACPI tables if the acpi option is not
disabled.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-8-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index aed303e1e6..4e3efbee16 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1323,6 +1323,10 @@ static void virt_machine_done(Notifier *notifier, void
*data)
if (kvm_enabled()) {
riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
}
+
+if (virt_is_acpi_enabled(s)) {
+virt_acpi_setup(s);
+}
}
static void virt_machine_init(MachineState *machine)
--
2.39.2
[PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI
From: Sunil V L
ACPI will be enabled by default. Add a switch to turn off
for testing and debug purposes.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-3-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 29 +
include/hw/riscv/virt.h | 2 ++
2 files changed, 31 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5a059489b5..90579a4c0e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -50,6 +50,7 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
#include "hw/acpi/aml-build.h"
+#include "qapi/qapi-visit-common.h"
/*
* The virt machine physical address space used by some of the devices
@@ -1533,6 +1534,7 @@ static void virt_machine_instance_init(Object *obj)
s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
+s->acpi = ON_OFF_AUTO_AUTO;
}
static char *virt_get_aia_guests(Object *obj, Error **errp)
@@ -1607,6 +1609,28 @@ static void virt_set_aclint(Object *obj, bool value,
Error **errp)
s->have_aclint = value;
}
+bool virt_is_acpi_enabled(RISCVVirtState *s)
+{
+return s->acpi != ON_OFF_AUTO_OFF;
+}
+
+static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+OnOffAuto acpi = s->acpi;
+
+visit_type_OnOffAuto(v, name, , errp);
+}
+
+static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+visit_type_OnOffAuto(v, name, >acpi, errp);
+}
+
static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
DeviceState *dev)
{
@@ -1678,6 +1702,11 @@ static void virt_machine_class_init(ObjectClass *oc,
void *data)
sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
"should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
object_class_property_set_description(oc, "aia-guests", str);
+object_class_property_add(oc, "acpi", "OnOffAuto",
+ virt_get_acpi, virt_set_acpi,
+ NULL, NULL);
+object_class_property_set_description(oc, "acpi",
+ "Enable ACPI");
}
static const TypeInfo virt_machine_typeinfo = {
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 6c7885bf89..62efebaa32 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -58,6 +58,7 @@ struct RISCVVirtState {
int aia_guests;
char *oem_id;
char *oem_table_id;
+OnOffAuto acpi;
};
enum {
@@ -123,4 +124,5 @@ enum {
#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
1 + FDT_APLIC_INT_CELLS)
+bool virt_is_acpi_enabled(RISCVVirtState *s);
#endif
--
2.39.2
[PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState
From: Sunil V L
memmap needs to be exported outside of virt.c so that
modules like acpi can use it. Hence, add a pointer field
in RiscVVirtState structure and initialize it with the
memorymap.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-4-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 ++
include/hw/riscv/virt.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 90579a4c0e..aed303e1e6 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1458,6 +1458,8 @@ static void virt_machine_init(MachineState *machine)
ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
}
+s->memmap = virt_memmap;
+
/* register system main memory (actual RAM) */
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
machine->ram);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 62efebaa32..379501edcc 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -59,6 +59,7 @@ struct RISCVVirtState {
char *oem_id;
char *oem_table_id;
OnOffAuto acpi;
+const MemMapEntry *memmap;
};
enum {
--
2.39.2
[PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI
From: Sunil V L RISC-V ACPI related functionality for virt machine is added in virt-acpi-build.c. Add the maintainer entry after moving the ARM ACPI entry under the main ACPI entry. Signed-off-by: Sunil V L Reviewed-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230302091212.999767-9-suni...@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 011fd85a09..26bf14b57b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -999,12 +999,6 @@ S: Maintained F: hw/ssi/xlnx-versal-ospi.c F: include/hw/ssi/xlnx-versal-ospi.h -ARM ACPI Subsystem -M: Shannon Zhao -L: qemu-...@nongnu.org -S: Maintained -F: hw/arm/virt-acpi-build.c - STM32F100 M: Alexandre Iooss L: qemu-...@nongnu.org @@ -1892,6 +1886,18 @@ F: docs/specs/acpi_nvdimm.rst F: docs/specs/acpi_pci_hotplug.rst F: docs/specs/acpi_hw_reduced_hotplug.rst +ARM ACPI Subsystem +M: Shannon Zhao +L: qemu-...@nongnu.org +S: Maintained +F: hw/arm/virt-acpi-build.c + +RISC-V ACPI Subsystem +M: Sunil V L +L: qemu-ri...@nongnu.org +S: Maintained +F: hw/riscv/virt-acpi-build.c + ACPI/VIOT M: Jean-Philippe Brucker S: Supported -- 2.39.2
[PULL 08/22] gitlab/opensbi: Move to docker:stable
The OpenSBI build has been using docker:19.03.1, which appears to be old enough that v2 of the manifest is no longer supported. Something has started serving us those manifests, resulting in errors along the lines of $ docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA --tag $IMAGE_TAG .gitlab-ci.d/opensbi Step 1/7 : FROM ubuntu:18.04 18.04: Pulling from library/ubuntu mediaType in manifest should be 'application/vnd.docker.distribution.manifest.v2+json' not 'application/vnd.oci.image.manifest.v1+json' This moves to docker:stable, as was suggested by the template. It also adds the python3 package via apt, as OpenSBI requires that to build. Reviewed-by: Bin Meng Message-ID: <20230303202448.11911-2-pal...@rivosinc.com> Signed-off-by: Palmer Dabbelt --- .gitlab-ci.d/opensbi.yml| 4 ++-- .gitlab-ci.d/opensbi/Dockerfile | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml index 04ed5a3ea1..9a651465d8 100644 --- a/.gitlab-ci.d/opensbi.yml +++ b/.gitlab-ci.d/opensbi.yml @@ -42,9 +42,9 @@ docker-opensbi: extends: .opensbi_job_rules stage: containers - image: docker:19.03.1 + image: docker:stable services: -- docker:19.03.1-dind +- docker:stable-dind variables: GIT_DEPTH: 3 IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerfile index 4ba8a4de86..5ccf4151f4 100644 --- a/.gitlab-ci.d/opensbi/Dockerfile +++ b/.gitlab-ci.d/opensbi/Dockerfile @@ -15,6 +15,7 @@ RUN apt update \ ca-certificates \ git \ make \ + python3 \ wget \ && \ \ -- 2.39.2
[PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState
From: Alexandre Ghiti
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Message-ID: <20230303131252.892893-2-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0ad8f94a42..1c4d8aaa74 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -220,7 +220,7 @@ static const char * const riscv_intr_names[] = {
"reserved"
};
-static void register_cpu_props(DeviceState *dev);
+static void register_cpu_props(Object *obj);
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
@@ -258,7 +258,7 @@ static void riscv_any_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
set_priv_version(env, PRIV_VERSION_1_12_0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
}
#if defined(TARGET_RISCV64)
@@ -267,7 +267,7 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -276,7 +276,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@@ -286,7 +286,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -331,7 +331,7 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -341,7 +341,7 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = _CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
/* Set latest version of privileged specification */
set_priv_version(env, PRIV_VERSION_1_12_0);
}
@@ -350,7 +350,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = _CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
@@ -360,7 +360,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -371,7 +371,7 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
cpu->cfg.epmp = true;
@@ -383,7 +383,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
@@ -398,7 +398,7 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
-register_cpu_props(DEVICE(obj));
+register_cpu_props(obj);
}
#endif
@@ -1210,11 +1210,12 @@ static Property riscv_cpu_extensions[] = {
* properties and leave. env.misa_ext = 0 means that we want
* all the default properties to be registered.
*/
-static void register_cpu_props(DeviceState *dev)
+static void register_cpu_props(Object *obj)
{
-RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
+RISCVCPU *cpu = RISCV_CPU(obj);
uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
+DeviceState *dev = DEVICE(obj);
/*
* If misa_ext is not zero, set cfg properties now to
--
2.39.2
Re: [PATCH V5 0/8] Add basic ACPI support for risc-v virt
On Sun, 05 Mar 2023 15:45:05 PST (-0800), Palmer Dabbelt wrote: On Thu, 02 Mar 2023 01:12:04 PST (-0800), suni...@ventanamicro.com wrote: This series adds the basic ACPI support for the RISC-V virt machine. Currently only RINTC interrupt controller specification is approved by the UEFI forum. External interrupt controller support in ACPI is in progress. This adds support for RINTC and RHCT tables as specified in below ECR links which are approved by UEFI forum. RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view These changes are also available @ https://github.com/vlsunil/qemu/tree/acpi_b1_us_review_V5 Changes since V4: 1) Used possible_cpus to create cpu topology in DSDT, MADT and RHCT as per Igor's feedback. Thanks. These all look good to me, but given that Igor had some feedback on the v4 and it's pretty much just been weekend since t hese went out I'm going to hold off until tomorrow before merging anything. They're all staged and passing the tests on my end, so everything's good as far as I'm concerned. I've queued these up on riscv-to-apply.next. I know it's pretty last minute, but IMO we're better off having these a cycle earlier as a lot of the dependencies here are cross-project and it'll be better tested if released. If anyone has an issue please say something, I'll be tagging a PR soon. 2) Moved MAINTAINER entries below ACPI/SMBIOS entry as per Drew's feedback Changes since V3: 1) Added back acpi_align_size() wrapper as per Drew's feedback 2) Updated RB tags Changes since V2: 1) Squashed commits and updated commit message as per feedback from Daniel. 2) Addressed comments from Drew. 3) Updated tags. Changes since V1: 1) Addressed comments from Bin Meng. 2) Made acpi switch default AUTO similar to other architectures. 3) Re-based and added RB and ACKs. The series is tested using SBI HVC console and initrd. Test instructions: 1) Build Qemu with ACPI support (this series) 2) Build EDK2 as per instructions in https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support 3) Build Linux with ACPI support using below branch https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17_V2 after enabling SBI HVC and SBI earlycon options. CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y 4) Build buildroot. Run with below command. qemu-system-riscv64 -nographic \ -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ -machine virt -smp 16 -m 2G \ -kernel arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" Sunil V L (8): hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields hw/riscv/virt: Add a switch to disable ACPI hw/riscv/virt: Add memmap pointer to RiscVVirtState hw/riscv/virt: Enable basic ACPI infrastructure hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT hw/riscv/virt: virt-acpi-build.c: Add RHCT Table hw/riscv/virt.c: Initialize the ACPI tables MAINTAINERS: Add entry for RISC-V ACPI MAINTAINERS| 18 +- hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 + hw/riscv/virt-acpi-build.c | 416 + hw/riscv/virt.c| 40 include/hw/riscv/virt.h| 6 + 6 files changed, 476 insertions(+), 6 deletions(-) create mode 100644 hw/riscv/virt-acpi-build.c
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
On Mon, 06 Mar 2023 09:50:49 PST (-0800), dbarb...@ventanamicro.com wrote:
On 3/5/23 20:34, Palmer Dabbelt wrote:
On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexgh...@rivosinc.com wrote:
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 4).
base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
https://gitlab.com/bonzini/qemu into staging")
I have that, but I still got some merge conflicts. I've put that here
<https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
Daniel's response below.
v11:
- rebase on top of master
- Added RB/AB from Frank and Alistair
- Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
- Set satp mode max for thead c906 to sv39
Daniel: It looks like the feedback on v10 included dropping the first patch
<https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91f...@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
Sorry if I'm just misunderstanding, but it looks to me like that patch is still
useful and the v11 doesn't even build without it.
I believe I mentioned that patch 1 was obsolete in the context of version 10,
where
I think I also mentioned that a rebase would be good.
Alexandre rebased it and, from what I can see, patch 1 looks good to go.
Sounds good, thanks.
Thanks,
Daniel
v10:
- Fix user mode build by surrounding satp handling with #ifndef
CONFIG_USER_ONLY, Frank
- Fix AB/RB from Frank and Alistair
v9:
- Move valid_vm[i] up, Andrew
- Fixed expansion of the bitmap map, Bin
- Rename set_satp_mode_default into set_satp_mode_default_map, Bin
- Remove outer parenthesis and alignment, Bin
- Fix qemu32 build failure, Bin
- Fixed a few typos, Bin
- Add RB from Andrew and Bin
v8:
- Remove useless !map check, Andrew
- Add RB from Andrew
v7:
- Expand map to contain all valid modes, Andrew
- Fix commit log for patch 3, Andrew
- Remove is_32_bit argument from set_satp_mode_default, Andrew
- Move and fixed comment, Andrew
- Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
too early, Alex
- Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
- Use satp_mode directly instead of a string in
set_satp_mode_max_supported, Andrew
- Swap the patch introducing supported bitmap and the patch that sets
sv57 in the dt, Andrew
- Add various RB from Andrew and Alistair, thanks
v6:
- Remove the valid_vm check in validate_vm and add it to the finalize function
so that map already contains the constraint, Alex
- Add forgotten mbare to satp_mode_from_str, Alex
- Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
- Only add satp mode properties corresponding to the cpu, and then remove the
check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
Andrew/Alistair/Alex
- Move mmu-type setting to its own patch, Andrew
- patch 5 is new and is a fix, Alex
v5:
- Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
suggested by Andrew
- Split the v4 patch into 2 patches as suggested by Andrew
- Lot of other minor corrections, from Andrew
- Set the satp mode N by disabling the satp mode N + 1
- Add a helper to set satp mode from a string, as suggested by Frank
v4:
- Use custom boolean properties instead of OnOffAuto properties, based
on ARMVQMap, as suggested by Andrew
v3:
- Free sv_name as pointed by Bin
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set the satp mode
riscv: Introduce satp mode hw capabilities
riscv: Correctly set the device-tree entry 'mmu-type'
hw/riscv/virt.c | 19 +--
target/riscv/cpu.c | 288 ++---
target/riscv/cpu.h | 25
target/riscv/csr.c | 29 +++--
4 files changed, 323 insertions(+), 38 deletions(-)
Re: [PATCH qemu] linux-user: Emulate /proc/cpuinfo output for riscv
On Sun, 05 Mar 2023 06:34:37 PST (-0800), abord...@git.sr.ht wrote:
From: Afonso Bordado
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a basic /proc/cpuinfo file
with mmu info and an ISA sting.
Kind of an orthogonal issue, but maybe we should default to having no
/proc/cpuinfo (or an empty one, or something that can be detected as
obviously QEMU) on systems that don't otherwise provide one (maybe when
target != host)? I'd bet that there's a lot of subtle oddness when
trying to parse other systems' /proc/cpuinfo all over the software
stack, and defaulting to something obvious could be easier for folks to
debug.
That doesn't need to block this one, though.
Signed-off-by: Afonso Bordado
---
linux-user/syscall.c | 32 +--
tests/tcg/riscv64/Makefile.target | 1 +
tests/tcg/riscv64/cpuinfo.c | 30 +
3 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/riscv64/cpuinfo.c
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index a6c426d73c..eda2bc5df0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -8183,7 +8183,8 @@ void target_exception_dump(CPUArchState *env, const char
*fmt, int code)
}
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
-defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
+defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
+defined(TARGET_RISCV)
static int is_proc(const char *filename, const char *entry)
{
return strcmp(filename, entry) == 0;
@@ -8261,6 +8262,33 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
}
#endif
+#if defined(TARGET_RISCV)
+static int open_cpuinfo(CPUArchState *cpu_env, int fd)
+{
+int i;
+int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
+RISCVCPU *cpu = env_archcpu(cpu_env);
+char *isa_string = riscv_isa_string(cpu);
+bool is_32_bit = riscv_cpu_xlen(>env) == 32;
+const char *mmu;
+
+if (cpu->cfg.mmu) {
+mmu = (is_32_bit) ? "sv32" : "sv48";
+} else {
+mmu = "none";
+}
+
+for (i = 0; i < num_cpus; i++) {
+dprintf(fd, "processor\t: %d\n", i);
+dprintf(fd, "hart\t\t: %d\n", i);
+dprintf(fd, "isa\t\t: %s\n", isa_string);
+dprintf(fd, "mmu\t\t: %s\n", mmu);
+dprintf(fd, "uarch\t\t: qemu\n\n");
+}
+return 0;
+}
+#endif
+
#if defined(TARGET_M68K)
static int open_hardware(CPUArchState *cpu_env, int fd)
{
@@ -8285,7 +8313,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname, int
#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
diff --git a/tests/tcg/riscv64/Makefile.target
b/tests/tcg/riscv64/Makefile.target
index cc3ed65ffd..df93a2ce1f 100644
--- a/tests/tcg/riscv64/Makefile.target
+++ b/tests/tcg/riscv64/Makefile.target
@@ -4,6 +4,7 @@
VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div
TESTS += noexec
+TESTS += cpuinfo
# Disable compressed instructions for test-noc
TESTS += test-noc
diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
new file mode 100644
index 00..296abd0a8c
--- /dev/null
+++ b/tests/tcg/riscv64/cpuinfo.c
@@ -0,0 +1,30 @@
+#include
+#include
+#include
+#include
+
+#define BUFFER_SIZE 1024
+
+int main(void)
+{
+char buffer[BUFFER_SIZE];
+FILE *fp = fopen("/proc/cpuinfo", "r");
+assert(fp != NULL);
+
+while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
+if (strstr(buffer, "processor") != NULL) {
+assert(strstr(buffer, "processor\t: ") == buffer);
+} else if (strstr(buffer, "hart") != NULL) {
+assert(strstr(buffer, "hart\t\t: ") == buffer);
+} else if (strstr(buffer, "isa") != NULL) {
+assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
0);
+} else if (strstr(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+ } else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+return 0;
+}
--
2.34.7
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
I know this might sound weird as I'm aiming to still take those ACPI
patches, but I'm going to call it too late for 8
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
On Mon, 06 Mar 2023 00:33:20 PST (-0800), alexgh...@rivosinc.com wrote:
Hi Palmer,
On Mon, Mar 6, 2023 at 12:34 AM Palmer Dabbelt wrote:
On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexgh...@rivosinc.com wrote:
> This introduces new properties to allow the user to set the satp mode,
> see patch 3 for full syntax. In addition, it prevents cpus to boot in a
> satp mode they do not support (see patch 4).
>
> base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
> https://gitlab.com/bonzini/qemu into staging")
I have that, but I still got some merge conflicts. I've put that here
<https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
Daniel's response below.
Weird, I have just tried again and it applied cleanly on the
base-commit I mentioned, I tried to cherry-pick a few patches, even
commit d4ea71170432 ("target/riscv: introduce riscv_cpu_cfg()") does
not break the merge.
Weird, I'm just using b4 to pick up the patches from lore so not sure
what's up.
Anyway, FWIW I checked the patches on the set-satp branch again, and
your merge seems ok.
OK, I picked those onto riscv-to-apply.next and everything looks fine on
my end.
>
> v11:
> - rebase on top of master
> - Added RB/AB from Frank and Alistair
> - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
> - Set satp mode max for thead c906 to sv39
Daniel: It looks like the feedback on v10 included dropping the first
patch
<https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91f...@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
Sorry if I'm just misunderstanding, but it looks to me like that patch
is still useful and the v11 doesn't even build without it.
No, the first commit is a preparatory commit for the series, it is required.
Ya, that's what I'm seeing too. It's in the queue before the rest.
Thanks!
>
> v10:
> - Fix user mode build by surrounding satp handling with #ifndef
> CONFIG_USER_ONLY, Frank
> - Fix AB/RB from Frank and Alistair
>
> v9:
> - Move valid_vm[i] up, Andrew
> - Fixed expansion of the bitmap map, Bin
> - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
> - Remove outer parenthesis and alignment, Bin
> - Fix qemu32 build failure, Bin
> - Fixed a few typos, Bin
> - Add RB from Andrew and Bin
>
> v8:
> - Remove useless !map check, Andrew
> - Add RB from Andrew
>
> v7:
> - Expand map to contain all valid modes, Andrew
> - Fix commit log for patch 3, Andrew
> - Remove is_32_bit argument from set_satp_mode_default, Andrew
> - Move and fixed comment, Andrew
> - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
> too early, Alex
> - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
> - Use satp_mode directly instead of a string in
> set_satp_mode_max_supported, Andrew
> - Swap the patch introducing supported bitmap and the patch that sets
> sv57 in the dt, Andrew
> - Add various RB from Andrew and Alistair, thanks
>
> v6:
> - Remove the valid_vm check in validate_vm and add it to the finalize function
> so that map already contains the constraint, Alex
> - Add forgotten mbare to satp_mode_from_str, Alex
> - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
> - Only add satp mode properties corresponding to the cpu, and then remove the
> check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
> Andrew/Alistair/Alex
> - Move mmu-type setting to its own patch, Andrew
> - patch 5 is new and is a fix, Alex
>
> v5:
> - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
> suggested by Andrew
> - Split the v4 patch into 2 patches as suggested by Andrew
> - Lot of other minor corrections, from Andrew
> - Set the satp mode N by disabling the satp mode N + 1
> - Add a helper to set satp mode from a string, as suggested by Frank
>
> v4:
> - Use custom boolean properties instead of OnOffAuto properties, based
> on ARMVQMap, as suggested by Andrew
>
> v3:
> - Free sv_name as pointed by Bin
> - Replace satp-mode with boolean properties as suggested by Andrew
> - Removed RB from Atish as the patch considerably changed
>
> v2:
> - Use error_setg + return as suggested by Alistair
> - Add RB from Atish
> - Fixed checkpatch issues missed in v1
> - Replaced Ludovic email address with the rivos one
>
> Alexandre Ghiti (5):
> riscv: Pass Object to register_cpu_props instead of DeviceState
> riscv: Change type of valid_vm_1_10_[32|64] to bool
> riscv: Allow user to set the satp mode
> riscv: Introduce satp mode hw capabilities
> riscv: Correctly set the device-tree entry 'mmu-type'
>
> hw/riscv/virt.c| 19 +--
> target/riscv/cpu.c | 288 ++---
> target/riscv/cpu.h | 25
> target/riscv/csr.c | 29 +++--
> 4 files changed, 323 insertions(+), 38 deletions(-)
Re: [PATCH V5 0/8] Add basic ACPI support for risc-v virt
On Thu, 02 Mar 2023 01:12:04 PST (-0800), suni...@ventanamicro.com wrote: This series adds the basic ACPI support for the RISC-V virt machine. Currently only RINTC interrupt controller specification is approved by the UEFI forum. External interrupt controller support in ACPI is in progress. This adds support for RINTC and RHCT tables as specified in below ECR links which are approved by UEFI forum. RINTC - https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view RHCT - https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view These changes are also available @ https://github.com/vlsunil/qemu/tree/acpi_b1_us_review_V5 Changes since V4: 1) Used possible_cpus to create cpu topology in DSDT, MADT and RHCT as per Igor's feedback. Thanks. These all look good to me, but given that Igor had some feedback on the v4 and it's pretty much just been weekend since t hese went out I'm going to hold off until tomorrow before merging anything. They're all staged and passing the tests on my end, so everything's good as far as I'm concerned. 2) Moved MAINTAINER entries below ACPI/SMBIOS entry as per Drew's feedback Changes since V3: 1) Added back acpi_align_size() wrapper as per Drew's feedback 2) Updated RB tags Changes since V2: 1) Squashed commits and updated commit message as per feedback from Daniel. 2) Addressed comments from Drew. 3) Updated tags. Changes since V1: 1) Addressed comments from Bin Meng. 2) Made acpi switch default AUTO similar to other architectures. 3) Re-based and added RB and ACKs. The series is tested using SBI HVC console and initrd. Test instructions: 1) Build Qemu with ACPI support (this series) 2) Build EDK2 as per instructions in https://github.com/vlsunil/riscv-uefi-edk2-docs/wiki/RISC-V-Qemu-Virt-support 3) Build Linux with ACPI support using below branch https://github.com/vlsunil/linux/commits/acpi_b1_us_review_ipi17_V2 after enabling SBI HVC and SBI earlycon options. CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y 4) Build buildroot. Run with below command. qemu-system-riscv64 -nographic \ -drive file=Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 \ -machine virt -smp 16 -m 2G \ -kernel arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" Sunil V L (8): hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields hw/riscv/virt: Add a switch to disable ACPI hw/riscv/virt: Add memmap pointer to RiscVVirtState hw/riscv/virt: Enable basic ACPI infrastructure hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT hw/riscv/virt: virt-acpi-build.c: Add RHCT Table hw/riscv/virt.c: Initialize the ACPI tables MAINTAINERS: Add entry for RISC-V ACPI MAINTAINERS| 18 +- hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 + hw/riscv/virt-acpi-build.c | 416 + hw/riscv/virt.c| 40 include/hw/riscv/virt.h| 6 + 6 files changed, 476 insertions(+), 6 deletions(-) create mode 100644 hw/riscv/virt-acpi-build.c
Re: [PATCH v2 1/2] gitlab/opensbi: Move to docker:stable
On Fri, 03 Mar 2023 15:28:14 PST (-0800), Bin Meng wrote: On Sat, Mar 4, 2023 at 4:25 AM Palmer Dabbelt wrote: The OpenSBI build has been using docker:19.03.1, which appears to be old enough that v2 of the manifest is no longer supported. Something has started serving us those manifests, resulting in errors along the lines of $ docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA --tag $IMAGE_TAG .gitlab-ci.d/opensbi Step 1/7 : FROM ubuntu:18.04 18.04: Pulling from library/ubuntu mediaType in manifest should be 'application/vnd.docker.distribution.manifest.v2+json' not 'application/vnd.oci.image.manifest.v1+json' This moves to docker:stable, as was suggested by the template. It also adds the python3 package via apt, as OpenSBI requires that to build. Signed-off-by: Palmer Dabbelt --- .gitlab-ci.d/opensbi.yml| 4 ++-- .gitlab-ci.d/opensbi/Dockerfile | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml index 04ed5a3ea1..9a651465d8 100644 --- a/.gitlab-ci.d/opensbi.yml +++ b/.gitlab-ci.d/opensbi.yml @@ -42,9 +42,9 @@ docker-opensbi: extends: .opensbi_job_rules stage: containers - image: docker:19.03.1 + image: docker:stable services: -- docker:19.03.1-dind +- docker:stable-dind variables: GIT_DEPTH: 3 IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerfile index 4ba8a4de86..2d151a6bc8 100644 --- a/.gitlab-ci.d/opensbi/Dockerfile +++ b/.gitlab-ci.d/opensbi/Dockerfile @@ -16,6 +16,7 @@ RUN apt update \ git \ make \ wget \ + python3 \ nits: this should be inserted before wget to follow the alphabetical order Thanks, I just squashed that in and stuck these on riscv-to-apply.next. && \ \ rm -rf /var/lib/apt/lists/* -- Reviewed-by: Bin Meng
Re: [PATCH 0/2] Risc-V CPU state by hart ID
On Thu, 02 Mar 2023 22:50:53 PST (-0800), mchit...@ventanamicro.com wrote: Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the contiguous logical CPU ID to fetch per CPU state. This patchset implements cpu_by_arch_id for Risc-V to get the CPU state by hart ID which may be sparse instead of the contigous logical CPU id. Mayuresh Chitale (2): target/riscv: cpu: Implement get_arch_id callback hw: intc: Use cpu_by_arch_id to fetch CPU state hw/intc/riscv_aclint.c | 16 hw/intc/riscv_aplic.c | 4 ++-- hw/intc/riscv_imsic.c | 6 +++--- target/riscv/cpu.c | 8 4 files changed, 21 insertions(+), 13 deletions(-) Thanks, these are queue up on riscv-to-apply.next.
Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode
On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexgh...@rivosinc.com wrote:
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 4).
base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
https://gitlab.com/bonzini/qemu into staging")
I have that, but I still got some merge conflicts. I've put that here
<https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
Daniel's response below.
v11:
- rebase on top of master
- Added RB/AB from Frank and Alistair
- Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
- Set satp mode max for thead c906 to sv39
Daniel: It looks like the feedback on v10 included dropping the first
patch
<https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91f...@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
Sorry if I'm just misunderstanding, but it looks to me like that patch
is still useful and the v11 doesn't even build without it.
v10:
- Fix user mode build by surrounding satp handling with #ifndef
CONFIG_USER_ONLY, Frank
- Fix AB/RB from Frank and Alistair
v9:
- Move valid_vm[i] up, Andrew
- Fixed expansion of the bitmap map, Bin
- Rename set_satp_mode_default into set_satp_mode_default_map, Bin
- Remove outer parenthesis and alignment, Bin
- Fix qemu32 build failure, Bin
- Fixed a few typos, Bin
- Add RB from Andrew and Bin
v8:
- Remove useless !map check, Andrew
- Add RB from Andrew
v7:
- Expand map to contain all valid modes, Andrew
- Fix commit log for patch 3, Andrew
- Remove is_32_bit argument from set_satp_mode_default, Andrew
- Move and fixed comment, Andrew
- Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
too early, Alex
- Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
- Use satp_mode directly instead of a string in
set_satp_mode_max_supported, Andrew
- Swap the patch introducing supported bitmap and the patch that sets
sv57 in the dt, Andrew
- Add various RB from Andrew and Alistair, thanks
v6:
- Remove the valid_vm check in validate_vm and add it to the finalize function
so that map already contains the constraint, Alex
- Add forgotten mbare to satp_mode_from_str, Alex
- Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
- Only add satp mode properties corresponding to the cpu, and then remove the
check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
Andrew/Alistair/Alex
- Move mmu-type setting to its own patch, Andrew
- patch 5 is new and is a fix, Alex
v5:
- Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
suggested by Andrew
- Split the v4 patch into 2 patches as suggested by Andrew
- Lot of other minor corrections, from Andrew
- Set the satp mode N by disabling the satp mode N + 1
- Add a helper to set satp mode from a string, as suggested by Frank
v4:
- Use custom boolean properties instead of OnOffAuto properties, based
on ARMVQMap, as suggested by Andrew
v3:
- Free sv_name as pointed by Bin
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed
v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one
Alexandre Ghiti (5):
riscv: Pass Object to register_cpu_props instead of DeviceState
riscv: Change type of valid_vm_1_10_[32|64] to bool
riscv: Allow user to set the satp mode
riscv: Introduce satp mode hw capabilities
riscv: Correctly set the device-tree entry 'mmu-type'
hw/riscv/virt.c| 19 +--
target/riscv/cpu.c | 288 ++---
target/riscv/cpu.h | 25
target/riscv/csr.c | 29 +++--
4 files changed, 323 insertions(+), 38 deletions(-)
Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
On Fri, 17 Feb 2023 07:14:59 PST (-0800), ivan.klo...@syntacore.com wrote:
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..d0639cd047 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1644,7 +1644,7 @@ const rv_opcode_data opcode_data[] = {
{ "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
-{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
Thanks, this is queue up on riscv-to-apply.next -- I think I managed to
get all the reviews and such from the mailing list, it got a bit
confused.
Here's what I've got:
commit 270629024df1f9f4e704ce8325f958858c5cbff7
gpg: Signature made Sun 05 Mar 2023 12:43:52 PM PST
gpg:using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
gpg:issuer "pal...@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt " [ultimate]
gpg: aka "Palmer Dabbelt " [ultimate]
Author: Ivan Klokov
Date: Fri Feb 17 18:14:59 2023 +0300
disas/riscv Fix ctzw disassemble
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Signed-off-by: Ivan Klokov
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230217151459.54649-1-ivan.klo...@syntacore.com>
Signed-off-by: Palmer Dabbelt
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..544558 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
Re: [PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions
On Fri, 24 Feb 2023 05:25:32 PST (-0800), dbarb...@ventanamicro.com wrote:
Hi,
This version has a change in patch 2, proposed by Weiwei Li, where we're
now triggering virt_instruction_fault before triggering illegal_insn
fault from S mode.
Richard already queued patch 1 is queued in tcg-next already. I'm still
including it here to allow for easier testing of the remaining patches.
Changes from v7:
- patch 1: queued in tcg-next, included here to facilitate testing the
other patches
- patch 2:
- changed check_zicbo_envcfg() to trigger the virtual faults
before triggering the illegal exception from S mode.
- v7 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg07041.html
Christoph Muellner (3):
target/riscv: implement Zicboz extension
target/riscv: implement Zicbom extension
target/riscv: add Zicbop cbo.prefetch{i,r,m} placeholder
Daniel Henrique Barboza (1):
tcg: add 'size' param to probe_access_flags()
accel/stubs/tcg-stub.c | 2 +-
accel/tcg/cputlb.c | 17 ++-
accel/tcg/user-exec.c | 5 +-
include/exec/exec-all.h | 3 +-
semihosting/uaccess.c | 2 +-
target/arm/ptw.c| 2 +-
target/arm/sve_helper.c | 2 +-
target/riscv/cpu.c | 7 +
target/riscv/cpu.h | 4 +
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 16 ++-
target/riscv/insn_trans/trans_rvzicbo.c.inc | 57 +
target/riscv/op_helper.c| 135
target/riscv/translate.c| 1 +
target/s390x/tcg/mem_helper.c | 6 +-
15 files changed, 250 insertions(+), 14 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
Thanks, 2-4 are queued up in riscv-to-apply.next (1 made it already via
the TCG tree).
Re: [PATCH 1/1] hw/riscv/virt.c: add cbom-block-size fdt property
On Thu, 02 Mar 2023 00:37:10 PST (-0800), ben.do...@codethink.co.uk wrote:
On 01/03/2023 21:59, Daniel Henrique Barboza wrote:
From: Anup Patel
The cbom-block-size fdt property property is used to inform the OS about
the blocksize in bytes for the Zicbom cache operations.
Linux documents it in Documentation/devicetree/bindings/riscv/cpus.yaml
as:
riscv,cbom-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The blocksize in bytes for the Zicbom cache operations.
Signed-off-by: Anup Patel
---
hw/riscv/virt.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 49acb57da4..31b55cc62f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -244,6 +244,12 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
+
+if (cpu_ptr->cfg.ext_icbom) {
+qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
+ cpu_ptr->cfg.cbom_blocksize);
+}
+
qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
You'll need the same for riscv,cboz-block-size as well.
Thanks. There's a v2 over here
Re: [PATCH v2 0/1] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
On Thu, 02 Mar 2023 01:14:05 PST (-0800), dbarb...@ventanamicro.com wrote:
Based-on: 20230224132536.552293-1-dbarb...@ventanamicro.com
("[PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions")
Hi,
This second version, which is still dependent on:
[PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions
Is adding the cboz FDT property as well as requested by Ben Dooks. First
version refrain from adding it since it's still under review in the
kernel but, given that we have cboz_blocksize already available, it
makes sense to also expose it like we're already doing for
cbom-block-size.
Changes from v1:
- also add riscv,cboz-block-size for Zicboz
- v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg00368.html
Cc: Ben Dooks
Anup Patel (1):
hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
hw/riscv/virt.c | 11 +++
1 file changed, 11 insertions(+)
Thanks, this is in the queue.
[PATCH v2 1/2] gitlab/opensbi: Move to docker:stable
The OpenSBI build has been using docker:19.03.1, which appears to be old enough that v2 of the manifest is no longer supported. Something has started serving us those manifests, resulting in errors along the lines of $ docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA --tag $IMAGE_TAG .gitlab-ci.d/opensbi Step 1/7 : FROM ubuntu:18.04 18.04: Pulling from library/ubuntu mediaType in manifest should be 'application/vnd.docker.distribution.manifest.v2+json' not 'application/vnd.oci.image.manifest.v1+json' This moves to docker:stable, as was suggested by the template. It also adds the python3 package via apt, as OpenSBI requires that to build. Signed-off-by: Palmer Dabbelt --- .gitlab-ci.d/opensbi.yml| 4 ++-- .gitlab-ci.d/opensbi/Dockerfile | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml index 04ed5a3ea1..9a651465d8 100644 --- a/.gitlab-ci.d/opensbi.yml +++ b/.gitlab-ci.d/opensbi.yml @@ -42,9 +42,9 @@ docker-opensbi: extends: .opensbi_job_rules stage: containers - image: docker:19.03.1 + image: docker:stable services: -- docker:19.03.1-dind +- docker:stable-dind variables: GIT_DEPTH: 3 IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerfile index 4ba8a4de86..2d151a6bc8 100644 --- a/.gitlab-ci.d/opensbi/Dockerfile +++ b/.gitlab-ci.d/opensbi/Dockerfile @@ -16,6 +16,7 @@ RUN apt update \ git \ make \ wget \ + python3 \ && \ \ rm -rf /var/lib/apt/lists/* -- 2.39.2
[PATCH v2 0/2] Fix the OpenSBI CI job and bump to v1.2
I missed the second-stage OpenSBI job when debugging the v1. It turns out that the Docker update dropped python3, so this adds it back in via apt. I ran the whole CI this time (via push-ci-now from the docs) and I'm getting two errors: clang-system: 46/96 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_timer-test ERROR 1.14s exit status 1 4321 pages: htags: Negative exec line limit = -4825 37 As far as I can tell those aren't failing upstream, but they also don't look related. I'm not sure if this has something to do with my fork, I'll try and poke around a bit but figured I'd send it out in case someone else has seen something similar. Changes since v1 <20230224212543.20462-1-pal...@rivosinc.com>: * Installs python3, which OpenSBI depends on (via kconfiglib). Link: https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/795696098 Link: https://gitlab.com/qemu-project/qemu/-/pipelines/795635851 Signed-off-by: Palmer Dabbelt
[PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
From: Daniel Henrique Barboza
Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg
can be avoided by using riscv_cpu_cfg().
Suggested-by: LIU Zhiwei
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 32 +---
1 file changed, 9 insertions(+), 23 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 86e183feb3..78c3b6d5f6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -213,9 +213,7 @@ static RISCVException any32(CPURISCVState *env, int csrno)
static int aia_any(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_smaia) {
+if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -224,9 +222,7 @@ static int aia_any(CPURISCVState *env, int csrno)
static int aia_any32(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_smaia) {
+if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -253,9 +249,7 @@ static int smode32(CPURISCVState *env, int csrno)
static int aia_smode(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_ssaia) {
+if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -264,9 +258,7 @@ static int aia_smode(CPURISCVState *env, int csrno)
static int aia_smode32(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_ssaia) {
+if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -380,9 +372,7 @@ static RISCVException pointer_masking(CPURISCVState *env,
int csrno)
static int aia_hmode(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_ssaia) {
+if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -391,9 +381,7 @@ static int aia_hmode(CPURISCVState *env, int csrno)
static int aia_hmode32(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_ssaia) {
+if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -430,9 +418,7 @@ static RISCVException debug(CPURISCVState *env, int csrno)
static RISCVException seed(CPURISCVState *env, int csrno)
{
-RISCVCPU *cpu = env_archcpu(env);
-
-if (!cpu->cfg.ext_zkr) {
+if (!riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -555,7 +541,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{
-*val = env_archcpu(env)->cfg.vlen >> 3;
+*val = riscv_cpu_cfg(env)->vlen >> 3;
return RISCV_EXCP_NONE;
}
@@ -610,7 +596,7 @@ static RISCVException write_vstart(CPURISCVState *env, int
csrno,
* The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits.
*/
-env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
+env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
return RISCV_EXCP_NONE;
}
--
2.39.2
[PULL 17/59] target/riscv: Indent fixes in cpu.c
From: Weiwei Li
Fix indent problems in vector related check.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-8-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 49ac368662..9b8747ab15 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -798,7 +798,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
}
if (cpu->cfg.ext_f) {
error_setg(errp,
-"Zfinx cannot be supported together with F extension");
+ "Zfinx cannot be supported together with F extension");
return;
}
}
@@ -861,40 +861,40 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
-"Vector extension VLEN must be power of 2");
+ "Vector extension VLEN must be power of 2");
return;
}
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
error_setg(errp,
-"Vector extension implementation only supports VLEN "
-"in the range [128, %d]", RV_VLEN_MAX);
+ "Vector extension implementation only supports VLEN "
+ "in the range [128, %d]", RV_VLEN_MAX);
return;
}
if (!is_power_of_2(cpu->cfg.elen)) {
error_setg(errp,
-"Vector extension ELEN must be power of 2");
+ "Vector extension ELEN must be power of 2");
return;
}
-if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
-error_setg(errp,
-"Vector extension implementation only supports ELEN "
-"in the range [8, 64]");
-return;
-}
-if (cpu->cfg.vext_spec) {
-if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
-vext_version = VEXT_VERSION_1_00_0;
-} else {
+if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
+ "Vector extension implementation only supports ELEN "
+ "in the range [8, 64]");
return;
}
-} else {
-qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-}
-set_vext_version(env, vext_version);
+if (cpu->cfg.vext_spec) {
+if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+vext_version = VEXT_VERSION_1_00_0;
+} else {
+error_setg(errp,
+ "Unsupported vector spec version '%s'",
+ cpu->cfg.vext_spec);
+return;
+}
+} else {
+qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
+}
+set_vext_version(env, vext_version);
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
--
2.39.2
[PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate()
From: Bin Meng
riscv_csrrw_check() already does the generic privilege level check
hence there is no need to do the specific M-mode access check in
the mseccfg predicate().
With this change debugger can access the mseccfg CSR anytime.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-18-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 020c3f524f..785f6f4d45 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -451,7 +451,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
-if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
+if (riscv_cpu_cfg(env)->epmp) {
return RISCV_EXCP_NONE;
}
--
2.39.2
[PULL 01/59] target/riscv: introduce riscv_cpu_cfg()
From: Daniel Henrique Barboza
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Bin Meng
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230222185205.355361-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..7ee22cbfa1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
#endif
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
+static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+{
+return _archcpu(env)->cfg;
+}
+
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
--
2.39.2
[PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU
From: Daniel Henrique Barboza
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
the flag directly instead.
With this change the enum is also removed. It is worth noticing that
this enum, and all the RISCV_FEATURES_* that were contained in it,
predates the existence of the cpu->cfg object. Today, using cpu->cfg is
an easier way to retrieve all the features and extensions enabled in the
hart.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-10-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 7 ---
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 4 ++--
target/riscv/monitor.c| 2 +-
target/riscv/pmp.c| 2 +-
6 files changed, 5 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d321ad28d2..11da920915 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
-if (cpu->cfg.mmu) {
-riscv_set_feature(env, RISCV_FEATURE_MMU);
-}
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3f9f29f4c..ac33362525 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,13 +81,6 @@
#define RVH RV('H')
#define RVJ RV('J')
-/* S extension denotes that Supervisor mode exists, however it is possible
- to have a core that support S mode but does not have an MMU and there
- is currently no bit in misa to indicate whether an MMU exists or not
- so a cpu features bitfield is required, likewise for optional PMP support */
-enum {
-RISCV_FEATURE_MMU,
-};
/* Privileged specification version */
enum {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57d20c605b..2b731a8c7f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
mode = PRV_U;
}
-if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
+if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf33494945..75a540bfcb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2621,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int
csrno,
static RISCVException read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
{
-if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+if (!riscv_cpu_cfg(env)->mmu) {
*val = 0;
return RISCV_EXCP_NONE;
}
@@ -2640,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int
csrno,
{
target_ulong vm, mask;
-if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 236f93b9f5..f36ddfa967 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
-if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+if (!riscv_cpu_cfg(env)->mmu) {
monitor_printf(mon, "S-mode MMU unavailable\n");
return;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 205bfbe090..a08cd95658 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
}
if (size == 0) {
-if (riscv_feature(env, RISCV_FEATURE_MMU)) {
+if (riscv_cpu_cfg(env)->mmu) {
/*
* If size is unknown (0), assume that all bytes
* from addr to the end of the page will be accessed.
--
2.39.2
[PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
From: Weiwei Li
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-2-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..b20b00a9a7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env,
int csrno,
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
+RISCVCPUConfig *cfg = _archcpu(env)->cfg;
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
-mask |= MENVCFG_PBMTE | MENVCFG_STCE;
+mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+(cfg->ext_sstc ? MENVCFG_STCE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env,
int csrno,
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
-uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+RISCVCPUConfig *cfg = _archcpu(env)->cfg;
+uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+(cfg->ext_sstc ? MENVCFG_STCE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
--
2.39.2
[PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends
From: Daniel Henrique Barboza
The attribute is no longer used since we can retrieve all the enabled
features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also
need to bump vmstate_riscv_cpu version_id and minimal_version_id since
'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-11-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 12
target/riscv/machine.c | 5 ++---
2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ac33362525..b9f69a134b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -175,8 +175,6 @@ struct CPUArchState {
/* 128-bit helpers upper part return value */
target_ulong retxh;
-uint32_t features;
-
#ifdef CONFIG_USER_ONLY
uint32_t elf_flags;
#endif
@@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env,
target_ulong ext)
return (env->misa_ext & ext) != 0;
}
-static inline bool riscv_feature(CPURISCVState *env, int feature)
-{
-return env->features & (1ULL << feature);
-}
-
-static inline void riscv_set_feature(CPURISCVState *env, int feature)
-{
-env->features |= (1ULL << feature);
-}
-
#include "cpu_user.h"
extern const char * const riscv_int_regnames[];
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 67e9e56853..9c455931d8 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
-.version_id = 6,
-.minimum_version_id = 6,
+.version_id = 7,
+.minimum_version_id = 7,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT32(env.misa_ext, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
-VMSTATE_UINT32(env.features, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_UINTTL(env.virt, RISCVCPU),
VMSTATE_UINT64(env.resetvec, RISCVCPU),
--
2.39.2
[PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs
From: Bin Meng
At present {h,s}stateen CSRs are not reported in the CSR XML
hence gdb cannot access them.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-16-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 15b23b9b5a..a0e70f5ba0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -337,13 +337,22 @@ static RISCVException hstateen_pred(CPURISCVState *env,
int csrno, int base)
return RISCV_EXCP_ILLEGAL_INST;
}
+RISCVException ret = hmode(env, csrno);
+if (ret != RISCV_EXCP_NONE) {
+return ret;
+}
+
+if (env->debugger) {
+return RISCV_EXCP_NONE;
+}
+
if (env->priv < PRV_M) {
if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
-return hmode(env, csrno);
+return RISCV_EXCP_NONE;
}
static RISCVException hstateen(CPURISCVState *env, int csrno)
@@ -366,6 +375,15 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+RISCVException ret = smode(env, csrno);
+if (ret != RISCV_EXCP_NONE) {
+return ret;
+}
+
+if (env->debugger) {
+return RISCV_EXCP_NONE;
+}
+
if (env->priv < PRV_M) {
if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -378,7 +396,7 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
}
}
-return smode(env, csrno);
+return RISCV_EXCP_NONE;
}
/* Checks if PointerMasking registers could be accessed */
--
2.39.2
[PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
From: Bin Meng
There is no need to generate the CSR XML if the Zicsr extension
is not enabled.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-6-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 704f3d6922..294f0ceb1c 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -406,7 +406,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
g_assert_not_reached();
}
-gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
- "riscv-csr.xml", 0);
+if (cpu->cfg.ext_icsr) {
+int base_reg = cs->gdb_num_regs;
+gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ riscv_gen_dynamic_csr_xml(cs, base_reg),
+ "riscv-csr.xml", 0);
+}
}
--
2.39.2
[PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation
From: Weiwei Li
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-6-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 6 --
target/riscv/cpu_helper.c | 6 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c8580f0c80..32cb297cfe 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj)
env->bins = 0;
env->two_stage_lookup = false;
-env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
-env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
+env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
+env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 44a8f267ae..7b7df01935 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,9 +937,11 @@ restart:
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+bool hade = env->menvcfg & MENVCFG_HADE;
if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+hade = hade && (env->henvcfg & HENVCFG_HADE);
}
if (riscv_cpu_sxl(env) == MXL_RV32) {
@@ -998,6 +1000,10 @@ restart:
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte) {
+if (!hade) {
+return TRANSLATE_FAIL;
+}
+
/*
* - if accessed or dirty bits need updating, and the PTE is
* in RAM, then we do so atomically with a compare and swap.
--
2.39.2
[PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit
From: Bin Meng
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-9-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9264db6110..a3e0e5755c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3360,7 +3360,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int
csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
-*val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
+*val = pmpcfg_csr_read(env, reg_index);
return RISCV_EXCP_NONE;
}
@@ -3372,7 +3372,7 @@ static RISCVException write_pmpcfg(CPURISCVState *env,
int csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
-pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+pmpcfg_csr_write(env, reg_index, val);
return RISCV_EXCP_NONE;
}
--
2.39.2
[PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
From: Shaobo Song
This bug has a noticeable behavior of falling back to the main loop and
respawning a redundant translation block including a single instruction
when the end address of the compressive instruction is exactly on a page
boundary, and slows down running system performance.
Signed-off-by: Shaobo Song
Reviewed-by: Richard Henderson
Message-ID: <20230220072732.568-1-songsha...@eswincomputing.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 772f9d7973..8ffa2116e0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1261,7 +1261,7 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next);
int len = insn_len(next_insn);
-if (!is_same_page(>base, ctx->base.pc_next + len)) {
+if (!is_same_page(>base, ctx->base.pc_next + len - 1)) {
ctx->base.is_jmp = DISAS_TOO_MANY;
}
}
--
2.39.2
[PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB
From: Bin Meng
Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt'
machines, QEMU complains:
qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS
The whole DT generation logic should be skipped when a given DTB is
present.
Fixes: b1f19f238cae ("hw/riscv: write bootargs 'chosen' FDT after
riscv_load_kernel()")
Signed-off-by: Bin Meng
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230228074522.1845007-1-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 +
hw/riscv/virt.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ad3bb35b34..76db5ed3dd 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -118,6 +118,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
error_report("load_device_tree() failed");
exit(1);
}
+return;
} else {
fdt = ms->fdt = create_device_tree(_size);
if (!fdt) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 49f2c157f7..981392c0bb 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1015,6 +1015,7 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap)
error_report("load_device_tree() failed");
exit(1);
}
+return;
} else {
ms->fdt = create_device_tree(>fdt_size);
if (!ms->fdt) {
--
2.39.2
[PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
From: Daniel Henrique Barboza
A common trend in this file is to retrieve a RISCVCPU pointer by first
retrieving a CPUState pointer via env_cpu(). The CPU pointer is used
only to access the RISCVCPUConfig object and nothing else.
Let's use riscv_cpu_cfg() to access what we need directly without these
2 pointers.
Suggested-by: LIU Zhiwei
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 50 +++---
1 file changed, 12 insertions(+), 38 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bf456fe87c..86e183feb3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,10 +46,8 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env,
int index,
uint64_t bit)
{
bool virt = riscv_cpu_virt_enabled(env);
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
+if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_NONE;
}
@@ -81,7 +79,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
-!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
+!riscv_cpu_cfg(env)->ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
@@ -90,11 +88,9 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
if (env->misa_ext & RVV ||
-cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+riscv_cpu_cfg(env)->ext_zve32f ||
+riscv_cpu_cfg(env)->ext_zve64f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -193,10 +189,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-if (!cpu->cfg.ext_sscofpmf) {
+if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -319,10 +312,7 @@ static RISCVException umode32(CPURISCVState *env, int
csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-if (!cpu->cfg.ext_smstateen) {
+if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -331,10 +321,7 @@ static RISCVException mstateen(CPURISCVState *env, int
csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-if (!cpu->cfg.ext_smstateen) {
+if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -361,10 +348,8 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-if (!cpu->cfg.ext_smstateen) {
+if (!riscv_cpu_cfg(env)->ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -916,11 +901,9 @@ static RISCVException read_timeh(CPURISCVState *env, int
csrno,
static RISCVException sstc(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
bool hmode_check = false;
-if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -1150,30 +1133,21 @@ static RISCVException write_ignore(CPURISCVState *env,
int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-*val = cpu->cfg.mvendorid;
+*val = riscv_cpu_cfg(env)->mvendorid;
return RISCV_EXCP_NONE;
}
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-*val = cpu->cfg.marchid;
+*val = riscv_cpu_cfg(env)->marchid;
return RISCV_EXCP_NONE;
}
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
-
-*val = cpu->cfg.mimpid;
+*val = riscv_cpu_cfg(env)->mimpid;
return RISCV_EXCP_NONE;
}
--
2.39.2
[PULL 50/59] target/riscv: Add csr support for svadu
From: Weiwei Li
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-4-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 4
target/riscv/csr.c | 17 +++--
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..3991eab5e5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -450,6 +450,7 @@ struct RISCVCPUConfig {
bool ext_zihintpause;
bool ext_smstateen;
bool ext_sstc;
+bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8b0d7e20ea..fca7ef0cef 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -747,10 +747,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_HADE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
/* For RV32 */
+#define MENVCFGH_HADE BIT(29)
#define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31)
@@ -763,10 +765,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_HADE MENVCFG_HADE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */
+#define HENVCFGH_HADE MENVCFGH_HADE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b86c1aa6fa..be71c50f09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env,
int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
-(cfg->ext_sstc ? MENVCFG_STCE : 0);
+(cfg->ext_sstc ? MENVCFG_STCE : 0) |
+(cfg->ext_svadu ? MENVCFG_HADE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env,
int csrno,
{
RISCVCPUConfig *cfg = _archcpu(env)->cfg;
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
-(cfg->ext_sstc ? MENVCFG_STCE : 0);
+(cfg->ext_sstc ? MENVCFG_STCE : 0) |
+(cfg->ext_svadu ? MENVCFG_HADE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env,
int csrno,
/*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
+ * henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/
-*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
+*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+ env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env,
int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
-mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
return ret;
}
-*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
+*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
@@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
-uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
+HENVCFG_HADE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.39.2
[PULL 55/59] target/riscv/csr.c: simplify mctr()
From: Daniel Henrique Barboza
Use riscv_cpu_cfg() to retrieve pmu_num.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d047d8b45c..bf456fe87c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -165,8 +165,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+int pmu_num = riscv_cpu_cfg(env)->pmu_num;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -175,7 +174,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
-if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
+if (!pmu_num || ctr_index >= pmu_num) {
/* The PMU is not enabled or counter is out of range*/
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.39.2
[PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions
From: Weiwei Li
Zvfh supports vector float point instructions with SEW = 16
and supports conversions between 8-bit integers and binary16 values.
Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-12-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv.c.inc | 31 +++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9053759546..9b2c5c9ac0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s)
switch (s->sew) {
case MO_16:
+return s->cfg_ptr->ext_zvfh;
case MO_32:
return s->cfg_ptr->ext_zve32f;
case MO_64:
@@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s)
switch (s->sew) {
case MO_8:
+return s->cfg_ptr->ext_zvfh;
+case MO_16:
+return s->cfg_ptr->ext_zve32f;
+case MO_32:
+return s->cfg_ptr->ext_zve64d;
+default:
+return false;
+}
+}
+
+static bool require_scale_rvfmin(DisasContext *s)
+{
+if (s->mstatus_fs == 0) {
+return false;
+}
+
+switch (s->sew) {
+case MO_8:
+return s->cfg_ptr->ext_zvfhmin;
case MO_16:
return s->cfg_ptr->ext_zve32f;
case MO_32:
@@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
- require_scale_rvf(s) &&
+ require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
@@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr
*a)
}
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+return opfv_narrow_check(s, a) &&
+ require_scale_rvfmin(s) &&
+ (s->sew != MO_8);
+}
+
+static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
require_scale_rvf(s) &&
@@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check,
vfncvt_f_x_w,
GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
RISCV_FRM_DYN)
/* Reuse the helper function from vfncvt.f.f.w */
-GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
RISCV_FRM_ROD)
static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
--
2.39.2
[PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
From: Weiwei Li
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-10-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f7ecf1a68..9b2711b94b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
switch (s->sew) {
case MO_16:
case MO_32:
-return has_ext(s, RVF);
+return s->cfg_ptr->ext_zve32f;
case MO_64:
-return has_ext(s, RVD);
+return s->cfg_ptr->ext_zve64d;
default:
return false;
}
@@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
switch (s->sew) {
case MO_8:
case MO_16:
-return has_ext(s, RVF);
+return s->cfg_ptr->ext_zve32f;
case MO_32:
-return has_ext(s, RVD);
+return s->cfg_ptr->ext_zve64d;
default:
return false;
}
--
2.39.2
[PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
From: Daniel Henrique Barboza
This file has several uses of env_archcpu() that are used solely to read
cfg->vlen. Use the new riscv_cpu_cfg() inline instead.
Suggested-by: Weiwei Li
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Weiwei Li
Message-ID: <20230226170514.588071-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7e476ea8c3..2423affe37 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -272,7 +272,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env,
target_ulong vl,
uint32_t esz, uint32_t max_elems)
{
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
uint32_t vta = vext_vta(desc);
uint32_t registers_used;
int k;
@@ -671,7 +671,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState
*env, uint32_t desc,
{
uint32_t i, k, off, pos;
uint32_t nf = vext_nf(desc);
-uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
uint32_t max_elems = vlenb >> log2_esz;
k = env->vstart / max_elems;
@@ -1141,7 +1141,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vl = env->vl;\
uint32_t vm = vext_vm(desc); \
-uint32_t total_elems = env_archcpu(env)->cfg.vlen;\
+uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
@@ -1177,7 +1177,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc);\
-uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+uint32_t total_elems = riscv_cpu_cfg(env)->vlen;\
uint32_t vta_all_1s = vext_vta_all_1s(desc);\
uint32_t i; \
\
@@ -1376,7 +1376,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl;\
-uint32_t total_elems = env_archcpu(env)->cfg.vlen;\
+uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc);\
uint32_t i; \
@@ -1439,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
{ \
uint32_t vm = vext_vm(desc);\
uint32_t vl = env->vl; \
-uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+uint32_t total_elems = riscv_cpu_cfg(env)->vlen;\
uint32_t vta_all_1s = vext_vta_all_1s(desc);\
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -4152,7 +4152,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl;\
-uint32_t total_elems = env_archcpu(env)->cfg.vlen;\
+uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc);\
uint32_t i; \
@@ -4190,7 +4190,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc);\
uint32_t vl = env->vl; \
-uint32_t total_e
[PULL 00/59] Fifth RISC-V PR for QEMU 8.0
merged tag 'buildsys-qom-qdev-ui-20230227'
The following changes since commit 627634031092e1514f363fd8659a579398de0f0e:
Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu
into staging (2023-02-28 15:09:18 +)
are available in the Git repository at:
https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303
for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c:
Merge patch series "target/riscv: some vector_helper.c cleanups" (2023-03-01
18:09:48 -0800)
Fifth RISC-V PR for QEMU 8.0
* Experimantal support for writable misa.
* Support for Svadu extension.
* Support for the Zicond extension.
* Fixes to gdbstub, CSR accesses, dependencies between the various
floating-point exceptions, and XTheadMemPair.
* Many cleanups.
There's a lot of cleanups here, a handful of which ended up stepping on
each other and were necessary for various features. I tried to keep
each individual patch set intact, but that led to some merge conflicts
and a bit of a clunky history -- I'm not sure what the right answer is
there, happy to re-spin this to be more linear if that's problem for
folks.
Unfortunately the OpenSBI bump is still failing CI, it turns out I
missed the second stage. I was intending on having a sixth PR anyway as
I'd really like to get the ACPI patches in for 8.0 so we can start
testing everywhere else. There's also a patch set from Daniel that's
ready to go but depends on some recently merged TCG patches, so I
figured it'd be better to just send what's ready now rather than trying
to make the history more complicated.
This all passes my local tests ("make check" and a bunch of Linux
configs), but "push-ci-now" is still tripping up on OpenSBI as that's
due to some network resources changing. With any luck I'll have some
time to sort things out this weekend (though always happy to have some
help if anyone wants to throw in some time).
Bin Meng (20):
target/riscv: gdbstub: Check priv spec version before reporting CSR
target/riscv: Add some comments to clarify the priority policy of
riscv_csrrw_check()
target/riscv: Use g_assert() for the predicate() NULL check
target/riscv: gdbstub: Minor change for better readability
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
target/riscv: Coding style fixes in csr.c
target/riscv: Use 'bool' type for read_only
target/riscv: Simplify {read, write}_pmpcfg() a little bit
target/riscv: Simplify getting RISCVCPU pointer from env
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
target/riscv: gdbstub: Turn on debugger mode before calling CSR
predicate()
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
target/riscv: Allow debugger to access user timer and counter CSRs
target/riscv: Allow debugger to access seed CSR
target/riscv: Allow debugger to access {h, s}stateen CSRs
target/riscv: Allow debugger to access sstc CSRs
target/riscv: Drop priv level check in mseccfg predicate()
target/riscv: Group all predicate() routines together
hw/riscv: Skip re-generating DT nodes for a given DTB
hw/riscv: Move the dtb load bits outside of create_fdt()
Christoph Müllner (1):
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
Daniel Henrique Barboza (16):
target/riscv: introduce riscv_cpu_cfg()
target/riscv: do not mask unsupported QEMU extensions in write_misa()
target/riscv: allow MISA writes as experimental
target/riscv: remove RISCV_FEATURE_DEBUG
target/riscv/cpu.c: error out if EPMP is enabled without PMP
target/riscv: remove RISCV_FEATURE_EPMP
target/riscv: remove RISCV_FEATURE_PMP
hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
target/riscv: remove RISCV_FEATURE_MMU
target/riscv/cpu: remove CPUArchState::features and friends
target/riscv/csr.c: use env_archcpu() in ctr()
target/riscv/csr.c: simplify mctr()
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
target/riscv/vector_helper.c: avoid env_archcpu() when reading
RISCVCPUConfig
Palmer Dabbelt (6):
Merge patch series "make write_misa a no-op and FEATURE_* cleanups"
Merge patch series "target/riscv: Some updates to float point related
extensions"
Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"
Merge patch series "target/riscv: Add support for Svadu extension"
[PULL 30/59] target/riscv: Coding style fixes in csr.c
From: Bin Meng
Fix various places that violate QEMU coding style:
- correct multi-line comment format
- indent to opening parenthesis
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-7-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 62 --
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cfd7ffc5c2..6a82628749 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
}
static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
-target_ulong *val)
+ target_ulong *val)
{
*val = env->vstimecmp;
@@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env,
int csrno,
}
static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
-target_ulong *val)
+ target_ulong *val)
{
*val = env->vstimecmp >> 32;
@@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env,
int csrno,
}
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
-target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env,
int csrno,
}
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
-target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env,
int csrno,
}
static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
-target_ulong *val)
+ target_ulong *val)
{
if (riscv_cpu_virt_enabled(env)) {
*val = env->vstimecmp >> 32;
@@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env,
int csrno,
}
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
-target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env,
int csrno,
}
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
-target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
/* 'E' excludes all other extensions */
if (val & RVE) {
-/* when we support 'E' we can do "val = RVE;" however
+/*
+ * when we support 'E' we can do "val = RVE;" however
* for now we just drop writes if 'E' is present.
*/
return RISCV_EXCP_NONE;
@@ -1361,7 +1362,8 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
val &= ~RVD;
}
-/* Suppress 'C' if next instruction is not aligned
+/*
+ * Suppress 'C' if next instruction is not aligned
* TODO: this should check next_pc
*/
if ((val & RVC) && (GETPC() & ~3) != 0) {
@@ -1830,28 +1832,28 @@ static RISCVException write_mscratch(CPURISCVState
*env, int csrno,
}
static RISCVException read_mepc(CPURISCVState *env, int csrno,
- target_ulong *val)
+target_ulong *val)
{
*val = env->mepc;
return RISCV_EXCP_NONE;
}
static RISCVException write_mepc(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
env->mepc = val;
return RISCV_EXCP_NONE;
}
static RISCVException read_mcause(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->mcause;
return RISCV_EXCP_NONE;
}
static RISCVException write_mcause(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
env->mcause = val;
return RISCV_EXCP_NONE;
@@ -1873,14 +1875,14 @@ static RISCVException write_mtval(CPURISCVState *env,
int csrno,
/* Execution environment configuration setup */
static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
[PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D
From: Weiwei Li
Add dependence chain:
* V => Zve64d => Zve64f => Zve32f => F
* V => Zve64d => D
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-6-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dcd85f7f27..49912c9174 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
-if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
-error_setg(errp, "V extension requires D extension");
+/* The V vector extension depends on the Zve64d extension */
+if (cpu->cfg.ext_v) {
+cpu->cfg.ext_zve64d = true;
+}
+
+/* The Zve64d extension depends on the Zve64f extension */
+if (cpu->cfg.ext_zve64d) {
+cpu->cfg.ext_zve64f = true;
+}
+
+/* The Zve64f extension depends on the Zve32f extension */
+if (cpu->cfg.ext_zve64f) {
+cpu->cfg.ext_zve32f = true;
+}
+
+if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
+error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
-if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
--
2.39.2
[PULL 40/59] target/riscv: Allow debugger to access sstc CSRs
From: Bin Meng
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-17-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e70f5ba0..020c3f524f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+hmode_check = true;
+}
+
+RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+if (ret != RISCV_EXCP_NONE) {
+return ret;
+}
+
+if (env->debugger) {
+return RISCV_EXCP_NONE;
+}
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
-if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
-hmode_check = true;
-}
-
-return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
--
2.39.2
[PULL 31/59] target/riscv: Use 'bool' type for read_only
From: Bin Meng
The read_only variable is currently declared as an 'int', but it
should really be a 'bool'.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-8-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a82628749..9264db6110 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3775,7 +3775,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
RISCVCPU *cpu)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
-int read_only = get_field(csrno, 0xC00) == 3;
+bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */
--
2.39.2
[PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP
From: Daniel Henrique Barboza
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-7-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 10 +++---
target/riscv/cpu.h | 1 -
target/riscv/csr.c | 2 +-
target/riscv/pmp.c | 4 ++--
4 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aec7830c44..807a466f34 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_PMP);
}
-if (cpu->cfg.epmp) {
-riscv_set_feature(env, RISCV_FEATURE_EPMP);
-
+if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
-if (!cpu->cfg.pmp) {
-error_setg(errp, "Invalid configuration: EPMP requires PMP
support");
-return;
-}
+error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+return;
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dc62554e14..471e587729 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,7 +88,6 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
-RISCV_FEATURE_EPMP,
};
/* Privileged specification version */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e220c4a5fd..951327022d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
-if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 4bc4113531..aa4d1996e9 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t
pmp_index, uint8_t val)
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
-if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+if (riscv_cpu_cfg(env)->epmp) {
/* mseccfg.RLB is set */
if (MSECCFG_RLB_ISSET(env)) {
locked = false;
@@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env,
target_ulong addr,
{
bool ret;
-if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+if (riscv_cpu_cfg(env)->epmp) {
if (MSECCFG_MMWP_ISSET(env)) {
/*
* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
--
2.39.2
[PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env
From: Bin Meng
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-10-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 36
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a3e0e5755c..8e827362cc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env,
int index,
uint64_t bit)
{
bool virt = riscv_cpu_virt_enabled(env);
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
return RISCV_EXCP_NONE;
@@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (env->misa_ext & RVV ||
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
@@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
target_ulong ctr_mask;
int base_csrno = CSR_CYCLE;
@@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int
csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int
csrno,
static RISCVException sstc(CPURISCVState *env, int csrno)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
bool hmode_check = false;
if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
@@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env,
int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mvendorid;
return RISCV_EXCP_NONE;
@@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env,
int csrno,
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.marchid;
return RISCV_EXCP_NONE;
@@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env,
int csrno,
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mimpid;
return RISCV_EXCP_NONE;
--
2.39.2
[PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh
From: Weiwei Li
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-2-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..a717f5d995 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
-if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
+if (cpu->cfg.ext_zfh) {
+cpu->cfg.ext_zfhmin = true;
+}
+
+if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
}
--
2.39.2
[PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin
From: Weiwei Li
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-4-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 2ad5716312..85fc1aa822 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,15 +28,14 @@
} \
} while (0)
-#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
-if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
+#define REQUIRE_ZFHMIN(ctx) do { \
+if (!ctx->cfg_ptr->ext_zfhmin) { \
return false; \
} \
} while (0)
-#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
-if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \
- ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
+#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \
+if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
return false;\
}\
} while (0)
@@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
TCGv t0;
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN(ctx);
+REQUIRE_ZFHMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN(ctx);
+REQUIRE_ZFHMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h
*a)
static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
REQUIRE_ZDINX_OR_D(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h
*a)
static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s
*a)
static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
REQUIRE_ZDINX_OR_D(ctx);
TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx,
arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN(ctx);
+REQUIRE_ZFHMIN(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
-REQUIRE_ZFH_OR_ZFHMIN(ctx);
+REQUIRE_ZFHMIN(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
--
2.39.2
[PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
From: Bin Meng
The priority policy of riscv_csrrw_check() was once adjusted in
commit eacaf4401956 ("target/riscv: Fix priority of csr related check in
riscv_csrrw_check")
whose commit message says the CSR existence check should come before
the access control check, but the code changes did not agree with
the commit message, that the predicate() check actually came after
the read / write check.
In fact this was intentional. Add some comments there so that people
won't bother trying to change it without a solid reason.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-3-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 75a540bfcb..4cc2c6370f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3776,11 +3776,12 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
-/* ensure the CSR extension is enabled. */
+/* ensure the CSR extension is enabled */
if (!cpu->cfg.ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
}
+/* privileged spec version check */
if (env->priv_ver < csr_min_priv) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3790,10 +3791,18 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+/* read / write check */
if (write_mask && read_only) {
return RISCV_EXCP_ILLEGAL_INST;
}
+/*
+ * The predicate() not only does existence check but also does some
+ * access control check which triggers for example virtual instruction
+ * exception in some cases. When writing read-only CSRs in those cases
+ * illegal instruction exception should be triggered instead of virtual
+ * instruction exception. Hence this comes after the read / write check.
+ */
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.39.2
[PULL 28/59] target/riscv: gdbstub: Minor change for better readability
From: Bin Meng
Use a variable 'base_reg' to represent cs->gdb_num_regs so that
the call to ricsv_gen_dynamic_vector_xml() can be placed in one
single line for better readability.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-5-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index e57372db38..704f3d6922 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
32, "riscv-32bit-fpu.xml", 0);
}
if (env->misa_ext & RVV) {
+int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_xml(cs,
-
cs->gdb_num_regs),
+ ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
switch (env->misa_mxl_max) {
--
2.39.2
[PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions
From: Weiwei Li
Add check for Zvfh and Zvfhmin.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-7-liwei...@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 49912c9174..49ac368662 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
return;
}
+if (cpu->cfg.ext_zvfh) {
+cpu->cfg.ext_zvfhmin = true;
+}
+
+if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+return;
+}
+
+if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+return;
+}
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
cpu->cfg.ext_zhinxmin = true;
--
2.39.2
[PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
From: Daniel Henrique Barboza
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a env->vl versus an evl value being used in the
first loop, the code is being repeated 4 times.
Create a helper to avoid code repetition in all those functions.
Arguments that are used in the callers (nf, esz and max_elems) are
passed as arguments. All other values are being derived inside the
helper.
Reviewed-by: Weiwei Li
Reviewed-by: Frank Chang
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20230226170514.588071-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 86 +---
1 file changed, 30 insertions(+), 56 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3073c54871..7e476ea8c3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -267,6 +267,28 @@ GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
+static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
+ void *vd, uint32_t desc, uint32_t nf,
+ uint32_t esz, uint32_t max_elems)
+{
+uint32_t total_elems = vext_get_total_elems(env, desc, esz);
+uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+uint32_t vta = vext_vta(desc);
+uint32_t registers_used;
+int k;
+
+for (k = 0; k < nf; ++k) {
+vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
+ (k * max_elems + max_elems) * esz);
+}
+
+if (nf * max_elems % total_elems != 0) {
+registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
+vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
+ registers_used * vlenb);
+}
+}
+
/*
*** stride: access vector element from strided memory
*/
@@ -281,8 +303,6 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
-uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
for (i = env->vstart; i < env->vl; i++, env->vstart++) {
@@ -301,18 +321,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
}
env->vstart = 0;
-/* set tail elements to 1s */
-for (k = 0; k < nf; ++k) {
-vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz,
- (k * max_elems + max_elems) * esz);
-}
-if (nf * max_elems % total_elems != 0) {
-uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
-uint32_t registers_used =
-((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
-vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
-}
+
+vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\
@@ -359,8 +369,6 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
*env, uint32_t desc,
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
-uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-uint32_t vta = vext_vta(desc);
/* load bytes from guest memory */
for (i = env->vstart; i < evl; i++, env->vstart++) {
@@ -372,18 +380,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState
*env, uint32_t desc,
}
}
env->vstart = 0;
-/* set tail elements to 1s */
-for (k = 0; k < nf; ++k) {
-vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz,
- (k * max_elems + max_elems) * esz);
-}
-if (nf * max_elems % total_elems != 0) {
-uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
-uint32_t registers_used =
-((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
-vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
-}
+
+vext_set_tail_elems_1s(env, evl, vd, desc, nf, esz, max_elems);
}
/*
@@ -484,8 +482,6 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t vm = vext_vm(desc);
uint32_t max_elems = vext_max_elems(desc, log2_esz);
uint32_t esz = 1 << log2_esz;
-uint32_t total_elems = vext_get_total_elems(env, desc, esz);
-uint32_t vta = vext_vta(desc);
uint32_t vma = vext_vma(desc);
/* load bytes from guest memory */
@@ -505,18 +501,8 @@ vext_
[PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
From: Bin Meng
It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.
Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 &
rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-13-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 75 --
1 file changed, 75 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ef52f41460..6048541606 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -127,40 +127,6 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
return 0;
}
-/*
- * Convert register index number passed by GDB to the correspond
- * vector CSR number. Vector CSRs are defined after vector registers
- * in dynamic generated riscv-vector.xml, thus the starting register index
- * of vector CSRs is 32.
- * Return 0 if register index number is out of range.
- */
-static int riscv_gdb_vector_csrno(int num_regs)
-{
-/*
- * The order of vector CSRs in the switch case
- * should match with the order defined in csr_ops[].
- */
-switch (num_regs) {
-case 32:
-return CSR_VSTART;
-case 33:
-return CSR_VXSAT;
-case 34:
-return CSR_VXRM;
-case 35:
-return CSR_VCSR;
-case 36:
-return CSR_VL;
-case 37:
-return CSR_VTYPE;
-case 38:
-return CSR_VLENB;
-default:
-/* Unknown register. */
-return 0;
-}
-}
-
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
@@ -174,19 +140,6 @@ static int riscv_gdb_get_vector(CPURISCVState *env,
GByteArray *buf, int n)
return cnt;
}
-int csrno = riscv_gdb_vector_csrno(n);
-
-if (!csrno) {
-return 0;
-}
-
-target_ulong val = 0;
-int result = riscv_csrrw_debug(env, csrno, , 0, 0);
-
-if (result == RISCV_EXCP_NONE) {
-return gdb_get_regl(buf, val);
-}
-
return 0;
}
@@ -201,19 +154,6 @@ static int riscv_gdb_set_vector(CPURISCVState *env,
uint8_t *mem_buf, int n)
return vlenb;
}
-int csrno = riscv_gdb_vector_csrno(n);
-
-if (!csrno) {
-return 0;
-}
-
-target_ulong val = ldtul_p(mem_buf);
-int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
-
-if (result == RISCV_EXCP_NONE) {
-return sizeof(target_ulong);
-}
-
return 0;
}
@@ -361,21 +301,6 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int
base_reg)
num_regs++;
}
-/* Define vector CSRs */
-const char *vector_csrs[7] = {
-"vstart", "vxsat", "vxrm", "vcsr",
-"vl", "vtype", "vlenb"
-};
-
-for (i = 0; i < 7; i++) {
-g_string_append_printf(s,
- "",
- vector_csrs[i], TARGET_LONG_BITS, base_reg++);
-num_regs++;
-}
-
g_string_append_printf(s, "");
cpu->dyn_vreg_xml = g_string_free(s, false);
--
2.39.2
[PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
From: Bin Meng
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from
riscv-*-fpu.xml")
the 3 FPU CSRs are removed from the XML target decription. The
original intent of that commit was based on the assumption that
the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in
riscv-*-fpu.xml are redundant. But unforuantely that is not true.
As the FPU CSR predicate() has a run-time check on MSTATUS.FS,
at the time when CSR XML is generated MSTATUS.FS is unset, hence
no FPU CSRs will be reported.
The FPU CSR predicate() already considered such a case of being
accessed by a debugger. All we need to do is to turn on debugger
mode before calling predicate().
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-12-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 294f0ceb1c..ef52f41460 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -280,6 +280,10 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
base_reg)
int bitsize = 16 << env->misa_mxl_max;
int i;
+#if !defined(CONFIG_USER_ONLY)
+env->debugger = true;
+#endif
+
/* Until gdb knows about 128-bit registers */
if (bitsize > 64) {
bitsize = 64;
@@ -308,6 +312,11 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
base_reg)
g_string_append_printf(s, "");
cpu->dyn_csr_xml = g_string_free(s, false);
+
+#if !defined(CONFIG_USER_ONLY)
+env->debugger = false;
+#endif
+
return CSR_TABLE_SIZE;
}
--
2.39.2
[PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
From: Weiwei Li
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-3-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b20b00a9a7..b86c1aa6fa 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env,
int csrno,
return ret;
}
-*val = env->henvcfg;
+/*
+ * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
+ * henvcfg.stce is read_only 0 when menvcfg.stce = 0
+ */
+*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env,
int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
-mask |= HENVCFG_PBMTE | HENVCFG_STCE;
+mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
return ret;
}
-*val = env->henvcfg >> 32;
+*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
+env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
-uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
+uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.39.2
[PULL 14/59] target/riscv: Add cfg properties for Zv* extensions
From: Weiwei Li
Add properties for Zve64d,Zvfh,Zvfhmin extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-5-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..7f5264e165 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,7 +462,10 @@ struct RISCVCPUConfig {
bool ext_zhinxmin;
bool ext_zve32f;
bool ext_zve64f;
+bool ext_zve64d;
bool ext_zmmul;
+bool ext_zvfh;
+bool ext_zvfhmin;
bool ext_smaia;
bool ext_ssaia;
bool ext_sscofpmf;
--
2.39.2
[PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP
From: Daniel Henrique Barboza
Instead of silently ignoring the EPMP setting if there is no PMP
available, error out informing the user that EPMP depends on PMP
support:
$ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true
qemu-system-riscv64: Invalid configuration: EPMP requires PMP support
This will force users to pick saner options in the QEMU command line.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-6-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13e55ec5bd..aec7830c44 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.pmp) {
riscv_set_feature(env, RISCV_FEATURE_PMP);
+}
+
+if (cpu->cfg.epmp) {
+riscv_set_feature(env, RISCV_FEATURE_EPMP);
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
-if (cpu->cfg.epmp) {
-riscv_set_feature(env, RISCV_FEATURE_EPMP);
+if (!cpu->cfg.pmp) {
+error_setg(errp, "Invalid configuration: EPMP requires PMP
support");
+return;
}
}
--
2.39.2
[PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair
From: Christoph Müllner
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner
Reviewed-by: LIU Zhiwei
Message-ID: <20230220095612.1529031-1-christoph.muell...@vrull.eu>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_xthead.c.inc | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index be87c34f56..cf1731b08d 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -980,10 +980,6 @@ static bool trans_th_lwud(DisasContext *ctx, arg_th_pair
*a)
static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
-if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
-return false;
-}
-
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();
--
2.39.2
[PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr()
From: Daniel Henrique Barboza
We don't need to use env_cpu() and CPUState().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..d047d8b45c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -108,8 +108,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
-CPUState *cs = env_cpu(env);
-RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
target_ulong ctr_mask;
int base_csrno = CSR_CYCLE;
--
2.39.2
[PULL 42/59] target/riscv: Group all predicate() routines together
From: Bin Meng
Move sstc()/sstc32() to where all predicate() routines live, and
smstateen_acc_ok() to near {read,write}_xenvcfg().
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-19-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 177 ++---
1 file changed, 87 insertions(+), 90 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 785f6f4d45..3a7e0217e2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -40,42 +40,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
-/* Predicates */
-#if !defined(CONFIG_USER_ONLY)
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
- uint64_t bit)
-{
-bool virt = riscv_cpu_virt_enabled(env);
-RISCVCPU *cpu = env_archcpu(env);
-
-if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
-return RISCV_EXCP_NONE;
-}
-
-if (!(env->mstateen[index] & bit)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-if (virt) {
-if (!(env->hstateen[index] & bit)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-
-if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-}
-
-if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
-if (!(env->sstateen[index] & bit)) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-}
-
-return RISCV_EXCP_NONE;
-}
-#endif
-
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@@ -399,6 +363,60 @@ static RISCVException sstateen(CPURISCVState *env, int
csrno)
return RISCV_EXCP_NONE;
}
+static RISCVException sstc(CPURISCVState *env, int csrno)
+{
+RISCVCPU *cpu = env_archcpu(env);
+bool hmode_check = false;
+
+if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+hmode_check = true;
+}
+
+RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+if (ret != RISCV_EXCP_NONE) {
+return ret;
+}
+
+if (env->debugger) {
+return RISCV_EXCP_NONE;
+}
+
+if (env->priv == PRV_M) {
+return RISCV_EXCP_NONE;
+}
+
+/*
+ * No need of separate function for rv32 as menvcfg stores both menvcfg
+ * menvcfgh for RV32.
+ */
+if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
+ get_field(env->menvcfg, MENVCFG_STCE))) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+if (riscv_cpu_virt_enabled(env)) {
+if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
+ get_field(env->henvcfg, HENVCFG_STCE))) {
+return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+}
+}
+
+return RISCV_EXCP_NONE;
+}
+
+static RISCVException sstc_32(CPURISCVState *env, int csrno)
+{
+if (riscv_cpu_mxl(env) != MXL_RV32) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
+return sstc(env, csrno);
+}
+
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
@@ -943,60 +961,6 @@ static RISCVException read_timeh(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException sstc(CPURISCVState *env, int csrno)
-{
-RISCVCPU *cpu = env_archcpu(env);
-bool hmode_check = false;
-
-if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
-hmode_check = true;
-}
-
-RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
-if (ret != RISCV_EXCP_NONE) {
-return ret;
-}
-
-if (env->debugger) {
-return RISCV_EXCP_NONE;
-}
-
-if (env->priv == PRV_M) {
-return RISCV_EXCP_NONE;
-}
-
-/*
- * No need of separate function for rv32 as menvcfg stores both menvcfg
- * menvcfgh for RV32.
- */
-if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
- get_field(env->menvcfg, MENVCFG_STCE))) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-if (riscv_cpu_virt_enabled(env)) {
-if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
- get_field(env->henvcfg, HENVCFG_STCE))) {
-return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
-}
-}
-
-return RISCV_EXCP_NONE;
-}
-
-static RISCVException sstc_32(CPURISCVState *env, int csrno)
-{
-if (riscv_cpu_mxl(env) != MXL_RV32) {
-return RISCV_EXCP_ILLEGAL_INST;
-}
-
-return sstc(env, csrno);
-}
-
static RISCVException read_vstimecmp(CPUR
