[PATCH v2] hw/nvme: Add properties for PCI vendor/device IDs and IEEE-OUI ID
Add properties for user specified
- PCI vendor, device, subsystem vendor and subsystem IDs
- IEEE-OUI ID
e.g. PCI IDs to be specified as follows:
-device
nvme,id_vendor=0xABCD,id_device=0xA0B0,id_subsys_vendor=0xEF00,id_subsys=0xEF01
IEEE-OUI ID (Identify Controller bytes 75:73) is to be
specified in LE format.
(e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB).
Signed-off-by: Saif Abrar
---
v1 -> v2: Updated the commit message to mention 'properties' instead of 'CLI
options'.
hw/nvme/ctrl.c | 44
hw/nvme/nvme.h | 5 +
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 127c3d2383..35aeb48e0b 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8050,8 +8050,9 @@ out:
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
{
-uint16_t vf_dev_id = n->params.use_intel_id ?
- PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
+uint16_t vf_dev_id = n->params.id_device ? n->params.id_device :
+(n->params.use_intel_id ?
+ PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME);
NvmePriCtrlCap *cap = >pri_ctrl_cap;
uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm),
@@ -8098,7 +8099,13 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
-if (n->params.use_intel_id) {
+if (n->params.id_vendor) {
+pci_config_set_vendor_id(pci_conf, n->params.id_vendor);
+pci_config_set_device_id(pci_conf, n->params.id_device);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID,
+
n->params.id_subsys_vendor);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, n->params.id_subsys);
+} else if (n->params.use_intel_id) {
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME);
} else {
@@ -8206,7 +8213,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
id->rab = 6;
-if (n->params.use_intel_id) {
+if (n->params.ieee_oui) {
+id->ieee[0] = extract32(n->params.ieee_oui, 0, 8);
+id->ieee[1] = extract32(n->params.ieee_oui, 8, 8);
+id->ieee[2] = extract32(n->params.ieee_oui, 16, 8);
+} else if (n->params.use_intel_id) {
id->ieee[0] = 0xb3;
id->ieee[1] = 0x02;
id->ieee[2] = 0x00;
@@ -8419,6 +8430,24 @@ static void nvme_exit(PCIDevice *pci_dev)
memory_region_del_subregion(>bar0, >iomem);
}
+static void nvme_prop_ieee_set(Object *obj, Visitor *v, const char *name,
+void *opaque, Error **errp)
+{
+Property *prop = opaque;
+uint32_t *val = object_field_prop_ptr(obj, prop);
+if (!visit_type_uint32(v, name, val, errp)) {
+return;
+}
+}
+
+static const PropertyInfo nvme_prop_ieee = {
+.name = "uint32",
+.description = "IEEE OUI: Identify Controller bytes 75:73\
+ in LE format. (e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD,\
+ Byte[75]=0xAB)",
+.set = nvme_prop_ieee_set,
+};
+
static Property nvme_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,
@@ -8451,6 +8480,13 @@ static Property nvme_props[] = {
params.sriov_max_vq_per_vf, 0),
DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar,
false),
+DEFINE_PROP_UINT16("id_vendor", NvmeCtrl, params.id_vendor, 0),
+DEFINE_PROP_UINT16("id_device", NvmeCtrl, params.id_device, 0),
+DEFINE_PROP_UINT16("id_subsys_vendor", NvmeCtrl,
+params.id_subsys_vendor,
0),
+DEFINE_PROP_UINT16("id_subsys", NvmeCtrl, params.id_subsys, 0),
+DEFINE_PROP("ieee_oui", NvmeCtrl, params.ieee_oui, nvme_prop_ieee,
+
uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index bed8191bd5..6e19a479d1 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -537,6 +537,11 @@ typedef struct NvmeParams {
uint8_t sriov_max_vq_per_vf;
uint8_t sriov_max_vi_per_vf;
bool msix_exclusive_bar;
+uint16_t id_vendor;
+uint16_t id_device;
+uint16_t id_subsys_vendor;
+uint16_t id_subsys;
+uint32_t ieee_oui;
} NvmeParams;
typedef struct NvmeCtrl {
--
2.39.3
[PATCH] hw/nvme: Add CLI options for PCI vendor/device IDs and IEEE-OUI ID
Add CLI options for user specified
- PCI vendor, device, subsystem vendor and subsystem IDs
- IEEE-OUI ID
e.g. PCI IDs to be specified as follows:
-device
nvme,id_vendor=0xABCD,id_device=0xA0B0,id_subsys_vendor=0xEF00,id_subsys=0xEF01
IEEE-OUI ID (Identify Controller bytes 75:73) is to be
specified in LE format.
(e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB).
Signed-off-by: Saif Abrar
---
hw/nvme/nvme.h | 5 +
hw/nvme/ctrl.c | 44
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index bed8191bd5..6e19a479d1 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -537,6 +537,11 @@ typedef struct NvmeParams {
uint8_t sriov_max_vq_per_vf;
uint8_t sriov_max_vi_per_vf;
bool msix_exclusive_bar;
+uint16_t id_vendor;
+uint16_t id_device;
+uint16_t id_subsys_vendor;
+uint16_t id_subsys;
+uint32_t ieee_oui;
} NvmeParams;
typedef struct NvmeCtrl {
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 127c3d2383..35aeb48e0b 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8050,8 +8050,9 @@ out:
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
{
-uint16_t vf_dev_id = n->params.use_intel_id ?
- PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
+uint16_t vf_dev_id = n->params.id_device ? n->params.id_device :
+(n->params.use_intel_id ?
+ PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME);
NvmePriCtrlCap *cap = >pri_ctrl_cap;
uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm),
@@ -8098,7 +8099,13 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
-if (n->params.use_intel_id) {
+if (n->params.id_vendor) {
+pci_config_set_vendor_id(pci_conf, n->params.id_vendor);
+pci_config_set_device_id(pci_conf, n->params.id_device);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID,
+
n->params.id_subsys_vendor);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, n->params.id_subsys);
+} else if (n->params.use_intel_id) {
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME);
} else {
@@ -8206,7 +8213,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
id->rab = 6;
-if (n->params.use_intel_id) {
+if (n->params.ieee_oui) {
+id->ieee[0] = extract32(n->params.ieee_oui, 0, 8);
+id->ieee[1] = extract32(n->params.ieee_oui, 8, 8);
+id->ieee[2] = extract32(n->params.ieee_oui, 16, 8);
+} else if (n->params.use_intel_id) {
id->ieee[0] = 0xb3;
id->ieee[1] = 0x02;
id->ieee[2] = 0x00;
@@ -8419,6 +8430,24 @@ static void nvme_exit(PCIDevice *pci_dev)
memory_region_del_subregion(>bar0, >iomem);
}
+static void nvme_prop_ieee_set(Object *obj, Visitor *v, const char *name,
+void *opaque, Error **errp)
+{
+Property *prop = opaque;
+uint32_t *val = object_field_prop_ptr(obj, prop);
+if (!visit_type_uint32(v, name, val, errp)) {
+return;
+}
+}
+
+static const PropertyInfo nvme_prop_ieee = {
+.name = "uint32",
+.description = "IEEE OUI: Identify Controller bytes 75:73\
+ in LE format. (e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD,\
+ Byte[75]=0xAB)",
+.set = nvme_prop_ieee_set,
+};
+
static Property nvme_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,
@@ -8451,6 +8480,13 @@ static Property nvme_props[] = {
params.sriov_max_vq_per_vf, 0),
DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar,
false),
+DEFINE_PROP_UINT16("id_vendor", NvmeCtrl, params.id_vendor, 0),
+DEFINE_PROP_UINT16("id_device", NvmeCtrl, params.id_device, 0),
+DEFINE_PROP_UINT16("id_subsys_vendor", NvmeCtrl,
+params.id_subsys_vendor,
0),
+DEFINE_PROP_UINT16("id_subsys", NvmeCtrl, params.id_subsys, 0),
+DEFINE_PROP("ieee_oui", NvmeCtrl, params.ieee_oui, nvme_prop_ieee,
+
uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
--
2.39.3
Re: [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts
Hello Cedric,
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
What is fund_A ?
I used 'fund_A' as an abbreviation to "Fundamental Register Set A".
Please let know if you suggest another abbreviation to name this method.
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small
PHB.
Looks ok.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index f48750ee54..8fbaf6512e 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
lsi_base = GETFIELD(PHB_LSI_SRC_ID,
phb->regs[PHB_LSI_SOURCE_ID >> 3]);
lsi_base <<= 3;
+ lsi_base &= (xsrc->nr_irqs - 1);
/* TODO: handle reset values of PHB_LSI_SRC_ID */
if (!lsi_base) {
@@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
/* TODO: Add more RO-masks as regs are implemented in the model */
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
What is fund_A ?
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Thanks,
C.
+ pnv_phb4_update_xsrc(phb);
+}
+
static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
{
STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
@@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
pnv_phb4_cfg_core_reset(phb);
pnv_phb4_pbl_core_reset(phb);
+ pnv_phb4_fund_A_reset(phb);
pnv_phb4_err_reg_reset(phb);
pnv_phb4_pcie_stack_reg_reset(phb);
pnv_phb4_regb_err_reg_reset(phb);
@@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev,
Error **errp)
return;
}
- pnv_phb4_update_xsrc(phb);
-
phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc,
xsrc->nr_irqs);
pnv_phb4_xscom_realize(phb);
Re: [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts
Hello Cedric,
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
What is fund_A ?
I used 'fund_A' as an abbreviation to "Fundamental Register Set A".
Please let know if you suggest another abbreviation to name this method.
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small
PHB.
Looks ok.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index f48750ee54..8fbaf6512e 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
lsi_base = GETFIELD(PHB_LSI_SRC_ID,
phb->regs[PHB_LSI_SOURCE_ID >> 3]);
lsi_base <<= 3;
+ lsi_base &= (xsrc->nr_irqs - 1);
/* TODO: handle reset values of PHB_LSI_SRC_ID */
if (!lsi_base) {
@@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
/* TODO: Add more RO-masks as regs are implemented in the model */
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
What is fund_A ?
+{
+ phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Thanks,
C.
+ pnv_phb4_update_xsrc(phb);
+}
+
static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
{
STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
@@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
pnv_phb4_cfg_core_reset(phb);
pnv_phb4_pbl_core_reset(phb);
+ pnv_phb4_fund_A_reset(phb);
pnv_phb4_err_reg_reset(phb);
pnv_phb4_pcie_stack_reg_reset(phb);
pnv_phb4_regb_err_reg_reset(phb);
@@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev,
Error **errp)
return;
}
- pnv_phb4_update_xsrc(phb);
-
phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc,
xsrc->nr_irqs);
pnv_phb4_xscom_realize(phb);
[PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers
Config-read the link-status register in the PCI-E macro,
Depending on the link-active bit, set the link-active status
in the HOTPLUG_STATUS and LINK_MANAGEMENT registers
Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg
after config-reading the slot-status in the PCI-E macro.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 4e3a6b37f9..7b3d75bae6 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -516,6 +516,19 @@ static uint32_t get_exp_offset(PnvPHB4 *phb)
return rpc->exp_offset;
}
+/*
+ * Config-read the link-status register in the PCI-E macro,
+ * convert to LE and check the link-active bit.
+ */
+static uint32_t is_link_active(PnvPHB4 *phb)
+{
+uint32_t exp_offset = get_exp_offset(phb);
+
+return (bswap32(pnv_phb4_rc_config_read(phb,
+exp_offset + PCI_EXP_LNKSTA, 4))
+& PCI_EXP_LNKSTA_DLLLA);
+}
+
#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v)
/*
@@ -757,6 +770,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
val = 0;
break;
+case PHB_PCIE_HOTPLUG_STATUS:
+/* For normal operations, Simspeed diagnostic bit is always zero */
+val &= PHB_PCIE_HPSTAT_SIMDIAG;
+break;
+
/* Read only registers */
case PHB_CPU_LOADSTORE_STATUS:
case PHB_ETU_ERR_SUMMARY:
@@ -968,8 +986,40 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr
off, unsigned size)
val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
return val;
+/*
+ * Read PCI-E registers and set status for:
+ * - Card present (active low bit 10)
+ * - Link active (bit 12)
+ */
case PHB_PCIE_HOTPLUG_STATUS:
-/* Clear write-only bit */
+/*
+ * Presence-status bit hpi_present_n is active-low, with reset value 1.
+ * Start by setting this bit to 1, indicating the card is not present.
+ * Then check the PCI-E register and clear the bit if card is present.
+ */
+val |= PHB_PCIE_HPSTAT_PRESENCE;
+
+/* Get the PCI-E capability offset from the root-port */
+uint32_t exp_base = get_exp_offset(phb);
+
+/*
+ * Config-read the PCI-E macro register for slot-status.
+ * Method for config-read converts to BE value.
+ * To check actual bit in the PCI-E register,
+ * convert the value back to LE using bswap32().
+ * Clear the Presence-status active low bit.
+ */
+if (bswap32(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, 4))
+& PCI_EXP_SLTSTA_PDS) {
+val &= ~PHB_PCIE_HPSTAT_PRESENCE;
+}
+
+/* Check if link is active and set the bit */
+if (is_link_active(phb)) {
+val |= PHB_PCIE_HPSTAT_LINKACTIVE;
+}
+
+/* Clear write-only resample-bit */
val &= ~PHB_PCIE_HPSTAT_RESAMPLE;
return val;
@@ -977,6 +1027,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr
off, unsigned size)
case PHB_PCIE_LMR:
/* These write-only bits always read as 0 */
val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK);
+
+/* Check if link is active and set the bit */
+if (is_link_active(phb)) {
+val |= PHB_PCIE_LMR_LINKACTIVE;
+}
return val;
/* Silent simple reads */
--
2.39.3
[PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index f48750ee54..8fbaf6512e 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]);
lsi_base <<= 3;
+lsi_base &= (xsrc->nr_irqs - 1);
/* TODO: handle reset values of PHB_LSI_SRC_ID */
if (!lsi_base) {
@@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
/* TODO: Add more RO-masks as regs are implemented in the model */
}
+static void pnv_phb4_fund_A_reset(PnvPHB4 *phb)
+{
+phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12);
+pnv_phb4_update_xsrc(phb);
+}
+
static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)
{
STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));
@@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev)
pnv_phb4_cfg_core_reset(phb);
pnv_phb4_pbl_core_reset(phb);
+pnv_phb4_fund_A_reset(phb);
pnv_phb4_err_reg_reset(phb);
pnv_phb4_pcie_stack_reg_reset(phb);
pnv_phb4_regb_err_reg_reset(phb);
@@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error
**errp)
return;
}
-pnv_phb4_update_xsrc(phb);
-
phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
pnv_phb4_xscom_realize(phb);
--
2.39.3
[PATCH 03/10] pnv/phb4: Implement sticky reset logic in PHB4
Sticky bits retain their values on reset and are not overwritten with the reset
value.
Added sticky reset logic for all required registers,
i.e. CFG core, PBL core, PHB error registers, PCIE stack registers and REGB
error registers.
Tested by writing all 1's to the reg PHB_PBL_ERR_INJECT.
This will set the bits in the reg PHB_PBL_ERR_STATUS.
Reset the PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET.
Verify that the sticky bits in the PHB_PBL_ERR_STATUS reg are still set.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 156 ++--
include/hw/pci-host/pnv_phb4_regs.h | 20 +++-
tests/qtest/pnv-phb4-test.c | 30 +-
3 files changed, 196 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index d2e7403b37..b3a83837f8 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -516,14 +516,52 @@ static uint32_t get_exp_offset(PnvPHB4 *phb)
return rpc->exp_offset;
}
-#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v);
+#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v)
+
+/*
+ * Apply sticky-mask 's' to the reset-value 'v' and write to the address 'a'.
+ * RC-config space values and masks are LE.
+ * Method pnv_phb4_rc_config_read() returns BE, hence convert to LE.
+ * Compute new value in LE domain.
+ * New value computation using sticky-mask is in LE.
+ * Convert the computed value from LE to BE before writing back.
+ */
+#define RC_CONFIG_STICKY_RESET(a, v, s) \
+(RC_CONFIG_WRITE(a, bswap32( \
+ (bswap32(pnv_phb4_rc_config_read(phb, a, 4)) & s) \
+ | (v & ~s) \
+ )))
static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb)
{
-/* Zero all registers initially */
+/*
+ * Zero all registers initially,
+ * except those that have sticky reset.
+ */
int i;
for (i = PCI_COMMAND ; i < PHB_RC_CONFIG_SIZE ; i += 4) {
-RC_CONFIG_WRITE(i, 0)
+switch (i) {
+case PCI_EXP_LNKCTL2:
+case PHB_AER_UERR:
+case PHB_AER_UERR_MASK:
+case PHB_AER_CERR:
+case PHB_AER_CAPCTRL:
+case PHB_AER_HLOG_1:
+case PHB_AER_HLOG_2:
+case PHB_AER_HLOG_3:
+case PHB_AER_HLOG_4:
+case PHB_AER_RERR:
+case PHB_AER_ESID:
+case PHB_DLF_STAT:
+case P16_STAT:
+case P16_LDPM:
+case P16_FRDPM:
+case P16_SRDPM:
+case P32_CTL:
+break;
+default:
+RC_CONFIG_WRITE(i, 0);
+}
}
RC_CONFIG_WRITE(PCI_COMMAND, 0x100100);
@@ -563,15 +601,55 @@ static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb)
RC_CONFIG_WRITE(P16_ECAP, 0x22410026);
RC_CONFIG_WRITE(P32_ECAP, 0x1002A);
RC_CONFIG_WRITE(P32_CAP, 0x103);
+
+/* Sticky reset */
+RC_CONFIG_STICKY_RESET(exp_offset + PCI_EXP_LNKCTL2, 0x5, 0xFEFFBF);
+RC_CONFIG_STICKY_RESET(PHB_AER_UERR, 0,0x1FF030);
+RC_CONFIG_STICKY_RESET(PHB_AER_UERR_MASK, 0,0x1FF030);
+RC_CONFIG_STICKY_RESET(PHB_AER_CERR, 0,0x11C1);
+RC_CONFIG_STICKY_RESET(PHB_AER_CAPCTRL, 0xA0, 0x15F);
+RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_1,0,0x);
+RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_2,0,0x);
+RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_3,0,0x);
+RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_4,0,0x);
+RC_CONFIG_STICKY_RESET(PHB_AER_RERR, 0,0x7F);
+RC_CONFIG_STICKY_RESET(PHB_AER_ESID, 0,0x);
+RC_CONFIG_STICKY_RESET(PHB_DLF_STAT, 0,0x807F);
+RC_CONFIG_STICKY_RESET(P16_STAT, 0,0x1F);
+RC_CONFIG_STICKY_RESET(P16_LDPM, 0,0x);
+RC_CONFIG_STICKY_RESET(P16_FRDPM, 0,0x);
+RC_CONFIG_STICKY_RESET(P16_SRDPM, 0,0x);
+RC_CONFIG_STICKY_RESET(P32_CTL, 0,0x3);
}
+/* Apply sticky-mask to the reset-value and write to the reg-address */
+#define STICKY_RST(addr, rst_val, sticky_mask) (phb->regs[addr >> 3] = \
+((phb->regs[addr >> 3] & sticky_mask) | (rst_val & ~sticky_mask)))
+
static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb)
{
-/* Zero all registers initially */
+/*
+ * Zero all registers initially,
+ * with sticky reset of certain registers.
+ */
int i;
for (i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) {
-phb->regs[i >> 3] = 0x0;
+switch (i) {
+case PHB_PBL_ERR_STATUS:
+break;
+case PHB_PBL_ERR1_STATUS:
+case PHB_PBL_ERR_LOG_0:
+case PHB_PBL_ERR_LOG_1:
+case PHB_PBL_ERR_STATUS_MASK:
+case PHB_PBL_ERR1_STATUS_MASK:
+STICKY_RST(i, 0, PPC_BITMASK(0, 63));
+break;
+default:
+phb->regs[i >> 3] =
[PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register
PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
Signed-off-by: Saif Abrar
---
hw/pci/pcie.c | 6 ++
include/standard-headers/linux/pci_regs.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 4b2f0805c6..e3081f6b84 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -212,6 +212,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset,
pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
+pci_set_word(dev->wmask + pos + PCI_EXP_LNKCTL2,
+PCI_EXP_LNKCTL2_TLS | PCI_EXP_LNKCTL2_ENTER_COMP |
+PCI_EXP_LNKCTL2_TX_MARGIN | PCI_EXP_LNKCTL2_HASD |
+PCI_EXP_LNKCTL2_MOD_COMP | PCI_EXP_LNKCTL2_COMP_SOS |
+PCI_EXP_LNKCTL2_COMP_P_DE);
+
if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
/* read-only to behave like a 'NULL' Extended Capability Header */
pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
diff --git a/include/standard-headers/linux/pci_regs.h
b/include/standard-headers/linux/pci_regs.h
index a39193213f..f743defe91 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -694,6 +694,9 @@
#define PCI_EXP_LNKCTL2_ENTER_COMP0x0010 /* Enter Compliance */
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
+#define PCI_EXP_LNKCTL2_MOD_COMP 0x0400 /* Enter Modified Compliance */
+#define PCI_EXP_LNKCTL2_COMP_SOS 0x0800 /* Compliance SOS */
+#define PCI_EXP_LNKCTL2_COMP_P_DE 0xF000 /* Compliance Preset/De-emphasis
*/
#define PCI_EXP_LNKSTA20x32/* Link Status 2 */
#define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32/* end of v2 EPs w/ link */
--
2.39.3
[PATCH 05/10] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read
Implement write-1-to-clear and write-X-to-clear logic.
Update registers with silent simple read and write.
Return all 1's when an unimplemented/reserved register is read.
Test that reading address 0x0 returns all 1's (i.e. -1).
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 190 ++--
include/hw/pci-host/pnv_phb4_regs.h | 12 +-
tests/qtest/pnv-phb4-test.c | 9 ++
3 files changed, 170 insertions(+), 41 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index a81763f34c..4e3a6b37f9 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -683,8 +683,41 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
return;
}
-/* Handle masking */
+/* Handle RO, W1C, WxC and masking */
switch (off) {
+/* W1C: Write-1-to-Clear registers */
+case PHB_TXE_ERR_STATUS:
+case PHB_RXE_ARB_ERR_STATUS:
+case PHB_RXE_MRG_ERR_STATUS:
+case PHB_RXE_TCE_ERR_STATUS:
+case PHB_ERR_STATUS:
+case PHB_REGB_ERR_STATUS:
+case PHB_PCIE_DLP_ERRLOG1:
+case PHB_PCIE_DLP_ERRLOG2:
+case PHB_PCIE_DLP_ERR_STATUS:
+case PHB_PBL_ERR_STATUS:
+phb->regs[off >> 3] &= ~val;
+return;
+
+/* WxC: Clear register on any write */
+case PHB_PBL_ERR1_STATUS:
+case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR_LOG_1:
+case PHB_REGB_ERR1_STATUS:
+case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR_LOG_1:
+case PHB_TXE_ERR1_STATUS:
+case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR_LOG_1:
+case PHB_RXE_ARB_ERR1_STATUS:
+case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR_LOG_1:
+case PHB_RXE_MRG_ERR1_STATUS:
+case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR_LOG_1:
+case PHB_RXE_TCE_ERR1_STATUS:
+case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR_LOG_1:
+case PHB_ERR1_STATUS:
+case PHB_ERR_LOG_0 ... PHB_ERR_LOG_1:
+phb->regs[off >> 3] = 0;
+return;
+
+/* Write value updated by masks */
case PHB_LSI_SOURCE_ID:
val &= PHB_LSI_SRC_ID;
break;
@@ -723,7 +756,6 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
case PHB_LEM_WOF:
val = 0;
break;
-/* TODO: More regs ..., maybe create a table with masks... */
/* Read only registers */
case PHB_CPU_LOADSTORE_STATUS:
@@ -732,6 +764,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
case PHB_PHB4_TCE_CAP:
case PHB_PHB4_IRQ_CAP:
case PHB_PHB4_EEH_CAP:
+case PHB_VERSION:
+case PHB_DMA_CHAN_STATUS:
+case PHB_TCE_TAG_STATUS:
+case PHB_PBL_BUF_STATUS:
+case PHB_PCIE_BNR:
+case PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15:
return;
}
@@ -752,6 +790,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
pnv_phb4_update_all_msi_regions(phb);
}
break;
+
case PHB_M32_START_ADDR:
case PHB_M64_UPPER_BITS:
if (changed) {
@@ -797,27 +836,63 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
break;
/* Silent simple writes */
-case PHB_ASN_CMPM:
-case PHB_CONFIG_ADDRESS:
-case PHB_IODA_ADDR:
-case PHB_TCE_KILL:
-case PHB_TCE_SPEC_CTL:
-case PHB_PEST_BAR:
-case PHB_PELTV_BAR:
+/* PHB Fundamental register set A */
+case PHB_CONFIG_DATA ... PHB_LOCK1:
case PHB_RTT_BAR:
-case PHB_LEM_FIR_ACCUM:
-case PHB_LEM_ERROR_MASK:
-case PHB_LEM_ACTION0:
-case PHB_LEM_ACTION1:
-case PHB_TCE_TAG_ENABLE:
+case PHB_PELTV_BAR:
+case PHB_PEST_BAR:
+case PHB_CAPI_CMPM ... PHB_M64_AOMASK:
+case PHB_NXLATE_PREFIX ... PHB_DMA_SYNC:
+case PHB_TCE_KILL ... PHB_IODA_ADDR:
+case PHB_PAPR_ERR_INJ_CTL ... PHB_PAPR_ERR_INJ_MASK:
case PHB_INT_NOTIFY_ADDR:
case PHB_INT_NOTIFY_INDEX:
-case PHB_DMA_SYNC:
- break;
+/* Fundamental register set B */
+case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R:
+/* FIR & Error registers */
+case PHB_LEM_FIR_ACCUM:
+case PHB_LEM_ERROR_MASK:
+case PHB_LEM_ACTION0 ... PHB_LEM_WOF:
+case PHB_ERR_INJECT ... PHB_ERR_AIB_FENCE_ENABLE:
+case PHB_ERR_STATUS_MASK ... PHB_ERR1_STATUS_MASK:
+case PHB_TXE_ERR_INJECT ... PHB_TXE_ERR_AIB_FENCE_ENABLE:
+case PHB_TXE_ERR_STATUS_MASK ... PHB_TXE_ERR1_STATUS_MASK:
+case PHB_RXE_ARB_ERR_INJECT ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE:
+case PHB_RXE_ARB_ERR_STATUS_MASK ... PHB_RXE_ARB_ERR1_STATUS_MASK:
+case PHB_RXE_MRG_ERR_INJECT ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE:
+case PHB_RXE_MRG_ERR_STATUS_MASK ... PHB_RXE_MRG_ERR1_STATUS_MASK:
+case PHB_RXE_TCE_ERR_INJECT ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE:
+case PHB_RXE_TCE_ERR_STATUS_MASK ... PHB_RXE_TCE_ERR1_STATUS_MASK:
+/* Performance monitor & Debug registers */
+case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1:
+/* REGB Register
[PATCH 01/10] qtest/phb4: Add testbench for PHB4
New qtest TB added for PHB4.
TB reads PHB Version register and asserts that
bits[24:31] have value 0xA5.
Signed-off-by: Saif Abrar
---
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 74 +
2 files changed, 75 insertions(+)
create mode 100644 tests/qtest/pnv-phb4-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 36c5c13a7b..4795e51c17 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -168,6 +168,7 @@ qtests_ppc64 = \
(config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) +
\
(config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) +
\
(config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : [])
+ \
+ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) +
\
(config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) +
\
(slirp.found() ? ['pxe-test'] : []) + \
(config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : [])
+ \
diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c
new file mode 100644
index 00..e3b809e9c4
--- /dev/null
+++ b/tests/qtest/pnv-phb4-test.c
@@ -0,0 +1,74 @@
+/*
+ * QTest testcase for PowerNV PHB4
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "hw/pci-host/pnv_phb4_regs.h"
+
+#define P10_XSCOM_BASE 0x000603fcull
+#define PHB4_MMIO 0x000600c3c000ull
+#define PHB4_XSCOM 0x8010900ull
+
+#define PPC_BIT(bit)(0x8000ULL >> (bit))
+#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
+
+static uint64_t pnv_xscom_addr(uint32_t pcba)
+{
+return P10_XSCOM_BASE | ((uint64_t) pcba << 3);
+}
+
+static uint64_t pnv_phb4_xscom_addr(uint32_t reg)
+{
+return pnv_xscom_addr(PHB4_XSCOM + reg);
+}
+
+/*
+ * XSCOM read/write is indirect in PHB4:
+ * Write 'SCOM - HV Indirect Address Register'
+ * with register-offset to read/write.
+ - bit[0]: Valid Bit
+ - bit[51:61]: Indirect Address(00:10)
+ * Read/write 'SCOM - HV Indirect Data Register' to get/set the value.
+ */
+
+static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg)
+{
+qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR),
+PPC_BIT(0) | reg);
+return qtest_readq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA));
+}
+
+/* Assert that 'PHB - Version Register Offset 0x0800' bits-[24:31] are 0xA5 */
+static void phb4_version_test(QTestState *qts)
+{
+uint64_t ver = pnv_phb4_xscom_read(qts, PHB_VERSION);
+
+/* PHB Version register [24:31]: Major Revision ID 0xA5 */
+ver = ver >> (63 - 31);
+g_assert_cmpuint(ver, ==, 0xA5);
+}
+
+static void test_phb4(void)
+{
+QTestState *qts = NULL;
+
+qts = qtest_initf("-machine powernv10 -accel tcg -nographic -d unimp");
+
+/* Make sure test is running on PHB */
+phb4_version_test(qts);
+
+qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+g_test_init(, , NULL);
+qtest_add_func("phb4", test_phb4);
+return g_test_run();
+}
--
2.39.3
[PATCH 04/10] pnv/phb4: Implement read-only and write-only bits of registers
SW cannot write the read-only(RO) bits of a register
and write-only(WO) bits of a register return 0 when read.
Added ro_mask[] for each register that defines which
bits in that register are RO.
When writing to a register, the RO-bits are not updated.
When reading a register, clear the WO bits and return the updated value.
Tested the registers PHB_DMA_SYNC, PHB_PCIE_HOTPLUG_STATUS, PHB_PCIE_LMR,
PHB_PCIE_DLP_TRWCTL, PHB_LEM_ERROR_AND_MASK and PHB_LEM_ERROR_OR_MASK
by writing all 1's and reading back the value.
The WO bits in these registers should read back as 0.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 77 ++---
include/hw/pci-host/pnv_phb4.h | 7 +++
include/hw/pci-host/pnv_phb4_regs.h | 19 +--
tests/qtest/pnv-phb4-test.c | 60 +-
4 files changed, 150 insertions(+), 13 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index b3a83837f8..a81763f34c 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -735,6 +735,10 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
return;
}
+/* Update 'val' according to the register's RO-mask */
+val = (phb->regs[off >> 3] & phb->ro_mask[off >> 3]) |
+ (val & ~(phb->ro_mask[off >> 3]));
+
/* Record whether it changed */
changed = phb->regs[off >> 3] != val;
@@ -808,7 +812,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
case PHB_TCE_TAG_ENABLE:
case PHB_INT_NOTIFY_ADDR:
case PHB_INT_NOTIFY_INDEX:
-case PHB_DMARD_SYNC:
+case PHB_DMA_SYNC:
break;
/* Noise on anything else */
@@ -846,7 +850,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off,
unsigned size)
case PHB_VERSION:
return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;
-/* Read-only */
+/* Read-only */
case PHB_PHB4_GEN_CAP:
return 0xe4b8ull;
case PHB_PHB4_TCE_CAP:
@@ -856,18 +860,49 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr
off, unsigned size)
case PHB_PHB4_EEH_CAP:
return phb->big_phb ? 0x2000ull : 0x1000ull;
+/* Write-only, read will return zeros */
+case PHB_LEM_ERROR_AND_MASK:
+case PHB_LEM_ERROR_OR_MASK:
+return 0;
+case PHB_PCIE_DLP_TRWCTL:
+val &= ~PHB_PCIE_DLP_TRWCTL_WREN;
+return val;
/* IODA table accesses */
case PHB_IODA_DATA0:
return pnv_phb4_ioda_read(phb);
+/*
+ * DMA sync: make it look like it's complete,
+ * clear write-only read/write start sync bits.
+ */
+case PHB_DMA_SYNC:
+val = PHB_DMA_SYNC_RD_COMPLETE |
+~(PHB_DMA_SYNC_RD_START | PHB_DMA_SYNC_WR_START);
+return val;
+
+/*
+ * PCI-E Stack registers
+ */
+case PHB_PCIE_SCR:
+val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */
+break;
+
/* Link training always appears trained */
case PHB_PCIE_DLP_TRAIN_CTL:
/* TODO: Do something sensible with speed ? */
-return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
+val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
+return val;
+
+case PHB_PCIE_HOTPLUG_STATUS:
+/* Clear write-only bit */
+val &= ~PHB_PCIE_HPSTAT_RESAMPLE;
+return val;
-/* DMA read sync: make it look like it's complete */
-case PHB_DMARD_SYNC:
-return PHB_DMARD_SYNC_COMPLETE;
+/* Link Management Register */
+case PHB_PCIE_LMR:
+/* These write-only bits always read as 0 */
+val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK);
+return val;
/* Silent simple reads */
case PHB_LSI_SOURCE_ID:
@@ -1712,6 +1747,33 @@ static PCIIOMMUOps pnv_phb4_iommu_ops = {
.get_address_space = pnv_phb4_dma_iommu,
};
+static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)
+{
+/* Clear RO-mask to make all regs as R/W by default */
+memset(phb->ro_mask, 0x0, PNV_PHB4_NUM_REGS * sizeof(uint64_t));
+
+/*
+ * Set register specific RO-masks
+ */
+
+/* PBL - Error Injection Register (0x1910) */
+phb->ro_mask[PHB_PBL_ERR_INJECT >> 3] =
+PPC_BITMASK(0, 23) | PPC_BITMASK(28, 35) | PPC_BIT(38) | PPC_BIT(46) |
+PPC_BITMASK(49, 51) | PPC_BITMASK(55, 63);
+
+/* Reserved bits[60:63] */
+phb->ro_mask[PHB_TXE_ERR_LEM_ENABLE >> 3] =
+phb->ro_mask[PHB_TXE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(60, 63);
+/* Reserved bits[36:63] */
+phb->ro_mask[PHB_RXE_TCE_ERR_LEM_ENABLE >> 3] =
+phb->ro_mask[PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(36, 63);
+/* Reserved bits[40:63] */
+phb->ro_mask[PHB_ERR_LEM_ENABLE >> 3] =
+phb->ro_mask[PHB_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(40, 6
[PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5
Hello, This series updates the existing PHB4 model to the latest spec: "Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00". Updates include the following: - implemented sticky reset logic - implemented read-only, write-only, W1C and WxC logic - return all 1's on read to unimplemented registers - update PCIE registers for link status, speed and width - implement IODA PCT debug table without any functionality - set write-mask bits for PCIE Link-Control-2 register that is read/written by PHB4 - update LSI Source-ID register based on small/big PHB number of interrupts Also, a new testbench for PHB4 model is added that does XSCOM read/writes to various registers of interest and verifies the values. Regards. Saif Abrar (10): qtest/phb4: Add testbench for PHB4 pnv/phb4: Add reset logic to PHB4 pnv/phb4: Implement sticky reset logic in PHB4 pnv/phb4: Implement read-only and write-only bits of registers pnv/phb4: Implement write-clear and return 1's on unimplemented reg read pnv/phb4: Set link-active status in HPSTAT and LMR registers pnv/phb4: Set link speed and width in the DLP training control register pnv/phb4: Implement IODA PCT table hw/pci: Set write-mask bits for PCIE Link-Control-2 register pnv/phb4: Mask off LSI Source-ID based on number of interrupts hw/pci-host/pnv_phb4.c| 601 -- hw/pci/pcie.c | 6 + include/hw/pci-host/pnv_phb4.h| 9 + include/hw/pci-host/pnv_phb4_regs.h | 66 ++- include/standard-headers/linux/pci_regs.h | 3 + tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 177 +++ 7 files changed, 805 insertions(+), 58 deletions(-) create mode 100644 tests/qtest/pnv-phb4-test.c -- 2.39.3
[PATCH 02/10] pnv/phb4: Add reset logic to PHB4
Add a method to be invoked on QEMU reset.
Also add CFG and PBL core-blocks reset logic using
appropriate bits of PHB_PCIE_CRESET register.
Tested by reading the reset value of a register.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 104 +++-
include/hw/pci-host/pnv_phb4_regs.h | 16 -
tests/qtest/pnv-phb4-test.c | 10 +++
3 files changed, 127 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 075499d36d..d2e7403b37 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1,7 +1,7 @@
/*
- * QEMU PowerPC PowerNV (POWER9) PHB4 model
+ * QEMU PowerPC PowerNV (POWER10) PHB4 model
*
- * Copyright (c) 2018-2020, IBM Corporation.
+ * Copyright (c) 2018-2024, IBM Corporation.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
@@ -22,6 +22,7 @@
#include "hw/qdev-properties.h"
#include "qom/object.h"
#include "trace.h"
+#include "sysemu/reset.h"
#define phb_error(phb, fmt, ...)\
qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n",\
@@ -499,6 +500,86 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
}
}
+/*
+ * Get the PCI-E capability offset from the root-port
+ */
+static uint32_t get_exp_offset(PnvPHB4 *phb)
+{
+PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
+PCIDevice *pdev;
+pdev = pci_find_device(pci->bus, 0, 0);
+if (!pdev) {
+phb_error(phb, "PCI device not found");
+return ~0;
+}
+PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(pdev);
+return rpc->exp_offset;
+}
+
+#define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v);
+
+static void pnv_phb4_cfg_core_reset(PnvPHB4 *phb)
+{
+/* Zero all registers initially */
+int i;
+for (i = PCI_COMMAND ; i < PHB_RC_CONFIG_SIZE ; i += 4) {
+RC_CONFIG_WRITE(i, 0)
+}
+
+RC_CONFIG_WRITE(PCI_COMMAND, 0x100100);
+RC_CONFIG_WRITE(PCI_CLASS_REVISION, 0x604);
+RC_CONFIG_WRITE(PCI_CACHE_LINE_SIZE, 0x1);
+RC_CONFIG_WRITE(PCI_MEMORY_BASE, 0x10);
+RC_CONFIG_WRITE(PCI_PREF_MEMORY_BASE, 0x10011);
+RC_CONFIG_WRITE(PCI_CAPABILITY_LIST, 0x40);
+RC_CONFIG_WRITE(PCI_INTERRUPT_LINE, 0x2);
+/* PM Capabilities Register */
+RC_CONFIG_WRITE(PCI_BRIDGE_CONTROL + PCI_PM_PMC, 0xC8034801);
+
+uint32_t exp_offset = get_exp_offset(phb);
+RC_CONFIG_WRITE(exp_offset, 0x420010);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCAP, 0x8022);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCTL, 0x140);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCAP, 0x300105);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCTL, 0x2010008);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_SLTCTL, 0x2000);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCAP2, 0x1003F);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_DEVCTL2, 0x20);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCAP2, 0x80003E);
+RC_CONFIG_WRITE(exp_offset + PCI_EXP_LNKCTL2, 0x5);
+
+RC_CONFIG_WRITE(PHB_AER_ECAP,0x14810001);
+RC_CONFIG_WRITE(PHB_AER_CAPCTRL, 0xA0);
+RC_CONFIG_WRITE(PHB_SEC_ECAP,0x1A010019);
+
+RC_CONFIG_WRITE(PHB_LMR_ECAP, 0x1E810027);
+/* LMR - Margining Lane Control / Status Register # 2 to 16 */
+for (i = PHB_LMR_CTLSTA_2 ; i <= PHB_LMR_CTLSTA_16 ; i += 4) {
+RC_CONFIG_WRITE(i, 0x9C38);
+}
+
+RC_CONFIG_WRITE(PHB_DLF_ECAP, 0x1F410025);
+RC_CONFIG_WRITE(PHB_DLF_CAP, 0x8001);
+RC_CONFIG_WRITE(P16_ECAP, 0x22410026);
+RC_CONFIG_WRITE(P32_ECAP, 0x1002A);
+RC_CONFIG_WRITE(P32_CAP, 0x103);
+}
+
+static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb)
+{
+/* Zero all registers initially */
+int i;
+for (i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) {
+phb->regs[i >> 3] = 0x0;
+}
+
+/* Set specific register values */
+phb->regs[PHB_PBL_CONTROL >> 3] = 0xC009;
+phb->regs[PHB_PBL_TIMEOUT_CTRL >> 3] = 0x2020;
+phb->regs[PHB_PBL_NPTAG_ENABLE >> 3] = 0x;
+phb->regs[PHB_PBL_SYS_LINK_INIT >> 3] = 0x80088B4642473000;
+}
+
static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,
unsigned size)
{
@@ -612,6 +693,16 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off,
uint64_t val,
pnv_phb4_update_xsrc(phb);
break;
+/* Reset core blocks */
+case PHB_PCIE_CRESET:
+if (val & PHB_PCIE_CRESET_CFG_CORE) {
+pnv_phb4_cfg_core_reset(phb);
+}
+if (val & PHB_PCIE_CRESET_PBL) {
+pnv_phb4_pbl_core_reset(phb);
+}
+break;
+
/* Silent simple writes */
case PHB_ASN_CMPM:
[PATCH 07/10] pnv/phb4: Set link speed and width in the DLP training control register
Get the current link-status from PCIE macro. Extract link-speed and link-width from the link-status and set in the DLP training control (PCIE_DLP_TCR) register. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 7b3d75bae6..6823ffab54 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -980,10 +980,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */ break; -/* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: -/* TODO: Do something sensible with speed ? */ +/* Link training always appears trained */ val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + +/* Get the current link-status from PCIE */ +uint32_t exp_offset = get_exp_offset(phb); +uint32_t lnkstatus = bswap32(pnv_phb4_rc_config_read(phb, +exp_offset + PCI_EXP_LNKSTA, 4)); + +/* Extract link-speed from the link-status */ +uint32_t v = lnkstatus & PCI_EXP_LNKSTA_CLS; +/* Set the current link-speed at the LINK_SPEED position */ +val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); + +/* + * Extract link-width from the link-status, + * after shifting the required bitfields. + */ +v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; +/* Set the current link-width at the LINK_WIDTH position */ +val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); return val; /* -- 2.39.3
[PATCH 08/10] pnv/phb4: Implement IODA PCT table
IODA PCT table (#3) is implemented
without any functionality, being a debug table.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 6 ++
include/hw/pci-host/pnv_phb4.h | 2 ++
include/hw/pci-host/pnv_phb4_regs.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 6823ffab54..f48750ee54 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -263,6 +263,10 @@ static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb,
mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1);
mask -= 1;
break;
+case IODA3_TBL_PCT:
+tptr = phb->ioda_PCT;
+mask = 7;
+break;
case IODA3_TBL_RCAM:
mask = phb->big_phb ? 127 : 63;
break;
@@ -361,6 +365,8 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val)
/* Handle side effects */
switch (table) {
case IODA3_TBL_LIST:
+case IODA3_TBL_PCT:
+/* No action for debug tables */
break;
case IODA3_TBL_MIST: {
/* Special mask for MIST partial write */
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 91e81eee0e..6d83e5616f 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -64,6 +64,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
#define PNV_PHB4_MAX_LSIs 8
#define PNV_PHB4_MAX_INTs 4096
#define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2)
+#define PNV_PHB4_MAX_PCT 128
#define PNV_PHB4_MAX_MMIO_WINDOWS 32
#define PNV_PHB4_MIN_MMIO_WINDOWS 16
#define PNV_PHB4_NUM_REGS (0x3000 >> 3)
@@ -144,6 +145,7 @@ struct PnvPHB4 {
/* On-chip IODA tables */
uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
+uint64_t ioda_PCT[PNV_PHB4_MAX_PCT];
uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs];
uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs];
uint64_t ioda_MDT[PNV_PHB4_MAX_PEs];
diff --git a/include/hw/pci-host/pnv_phb4_regs.h
b/include/hw/pci-host/pnv_phb4_regs.h
index c1d5a83271..e30adff7b2 100644
--- a/include/hw/pci-host/pnv_phb4_regs.h
+++ b/include/hw/pci-host/pnv_phb4_regs.h
@@ -486,6 +486,7 @@
#define IODA3_TBL_LIST 1
#define IODA3_TBL_MIST 2
+#define IODA3_TBL_PCT 3
#define IODA3_TBL_RCAM 5
#define IODA3_TBL_MRT 6
#define IODA3_TBL_PESTA 7
--
2.39.3
[PATCH] tests/qemu-iotests: Bump timeout of iothreads-stream test
Current value of timeout=0.1 is sometimes too tight.
Bump timeout to 0.3 to avoid test failures.
Signed-off-by: Saif Abrar
---
tests/qemu-iotests/tests/iothreads-stream | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/tests/iothreads-stream
b/tests/qemu-iotests/tests/iothreads-stream
index 503f221f16..32e46e044e 100755
--- a/tests/qemu-iotests/tests/iothreads-stream
+++ b/tests/qemu-iotests/tests/iothreads-stream
@@ -63,7 +63,7 @@ with iotests.FilePath('disk1.img') as base1_path, \
finished = 0
while True:
try:
-ev = vm.event_wait('JOB_STATUS_CHANGE', timeout=0.1)
+ev = vm.event_wait('JOB_STATUS_CHANGE', timeout=0.3)
if ev is not None and ev['data']['status'] == 'null':
finished += 1
# The test is done once both jobs are gone
--
2.31.1
[PATCH v2] hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar
Reviewed-by: Cédric Le Goater
Reviewed-by: Harsh Prateek Bora
---
v2: Bit-masks specified using PPC_BITMASK macro.
hw/pci-host/pnv_phb4.c | 46 ++---
hw/pci-host/pnv_phb4_pec.c | 33 +
include/hw/pci-host/pnv_phb4.h | 2 +-
include/hw/pci-host/pnv_phb4_regs.h | 4 ++-
4 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 29cb11a5d9..2f935aabd4 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -855,7 +855,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque,
hwaddr addr,
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
return phb->nest_regs[reg];
}
@@ -1000,7 +1000,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
switch (reg) {
case PEC_NEST_STK_PCI_NEST_FIR:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val & PPC_BITMASK(0, 27);
break;
case PEC_NEST_STK_PCI_NEST_FIR_CLR:
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
@@ -1009,7 +1009,8 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSK:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val &
+PPC_BITMASK(0, 27);
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
@@ -1019,7 +1020,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
break;
case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
break;
case PEC_NEST_STK_PCI_NEST_FIR_WOF:
phb->nest_regs[reg] = 0;
@@ -1030,7 +1031,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
/* Flag error ? */
break;
case PEC_NEST_STK_PBCQ_MODE:
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
break;
case PEC_NEST_STK_MMIO_BAR0:
case PEC_NEST_STK_MMIO_BAR0_MASK:
@@ -1041,28 +1042,33 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
PEC_NEST_STK_BAR_EN_MMIO1)) {
phb_pec_error(pec, "Changing enabled BAR unsupported");
}
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 39);
break;
case PEC_NEST_STK_PHB_REGS_BAR:
if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
phb_pec_error(pec, "Changing enabled BAR unsupported");
}
-phb->nest_regs[reg] = val & 0xffc0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 41);
break;
case PEC_NEST_STK_INT_BAR:
if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
phb_pec_error(pec, "Changing enabled BAR unsupported");
}
-phb->nest_regs[reg] = val & 0xfff0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
break;
case PEC_NEST_STK_BAR_EN:
-phb->nest_regs[reg] = val & 0xf000ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 3);
pnv_pec_phb_update_map(phb);
break;
case PEC_NEST_STK_DATA_FRZ_TYPE:
-case PEC_NEST_STK_PBCQ_TUN_BAR:
/* Not used for now */
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
+break;
+case PEC_NEST_STK_PBCQ_SPARSE_PAGE:
+phb->nest_regs[reg] = val & PPC_BITMASK(3, 5);
+break;
+case PEC_NEST_STK_PBCQ_CACHE_INJ:
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
@@ -1086,7 +1092,7 @@ static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque,
hwaddr addr,
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
return phb->pci_regs[reg];
}
@@ -1095,10 +1101,9 @@ static voi
[PATCH] hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 29 +++--
hw/pci-host/pnv_phb4_pec.c | 33 -
include/hw/pci-host/pnv_phb4.h | 2 +-
include/hw/pci-host/pnv_phb4_regs.h | 4 +++-
4 files changed, 50 insertions(+), 18 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 29cb11a5d9..5661ed1472 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -855,7 +855,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque,
hwaddr addr,
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
return phb->nest_regs[reg];
}
@@ -1000,7 +1000,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
switch (reg) {
case PEC_NEST_STK_PCI_NEST_FIR:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val &
0xfff0ull;
break;
case PEC_NEST_STK_PCI_NEST_FIR_CLR:
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
@@ -1009,7 +1009,8 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSK:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val
+&
0xfff0ull;
break;
case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
@@ -1019,7 +1020,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
break;
case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & 0xfff0ull;
break;
case PEC_NEST_STK_PCI_NEST_FIR_WOF:
phb->nest_regs[reg] = 0;
@@ -1060,10 +1061,15 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque,
hwaddr addr,
pnv_pec_phb_update_map(phb);
break;
case PEC_NEST_STK_DATA_FRZ_TYPE:
-case PEC_NEST_STK_PBCQ_TUN_BAR:
/* Not used for now */
phb->nest_regs[reg] = val;
break;
+case PEC_NEST_STK_PBCQ_SPARSE_PAGE:
+phb->nest_regs[reg] = val & 0x1c00ull;
+break;
+case PEC_NEST_STK_PBCQ_CACHE_INJ:
+phb->nest_regs[reg] = val & 0xff00ull;
+break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
"=%"PRIx64"\n", addr, val);
@@ -1086,7 +1092,7 @@ static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque,
hwaddr addr,
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
return phb->pci_regs[reg];
}
@@ -1095,10 +1101,9 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque,
hwaddr addr,
{
PnvPHB4 *phb = PNV_PHB4(opaque);
uint32_t reg = addr >> 3;
-
switch (reg) {
case PEC_PCI_STK_PCI_FIR:
-phb->pci_regs[reg] = val;
+phb->pci_regs[reg] = val & 0xfc00ull;
break;
case PEC_PCI_STK_PCI_FIR_CLR:
phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
@@ -1107,7 +1112,7 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque,
hwaddr addr,
phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
break;
case PEC_PCI_STK_PCI_FIR_MSK:
-phb->pci_regs[reg] = val;
+phb->pci_regs[reg] = val & 0xfc00ull;
break;
case PEC_PCI_STK_PCI_FIR_MSKC:
phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
@@ -1117,7 +1122,7 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque,
hwaddr addr,
break;
case PEC_PCI_STK_PCI_FIR_ACT0:
case PEC_PCI_STK_PCI_FIR_ACT1:
-phb->pci_regs[reg] = val;
+phb->pci_regs[reg] = val & 0xfc00ull;
break;
case PEC_PCI_STK_PCI_FIR_WOF:
phb->pci_regs[reg] = 0;
@@ -1129,8 +1134,10 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque,
hwaddr addr,
case PEC_PCI_STK_PBAIB_ERR_REPORT:
break;
case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
+phb->pci_regs[reg] = val & 0xe03fe03fe07fe03full;
+break;
case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
-phb->pci_regs[reg] = val;
+phb->pci_regs[reg] = val & 0x600f;
break;
default:
qemu_log_mask(LOG_UNIMP, "phb4_pec
[PATCH] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar
---
target/ppc/gdbstub.c | 40 ++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 2ad11510bf..eb086c0168 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -412,7 +412,32 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArray
*buf, int n)
}
len = TARGET_LONG_SIZE;
-gdb_get_regl(buf, env->spr[reg]);
+
+/* Handle those SPRs that are not part of the env->spr[] array */
+target_ulong val;
+switch (reg) {
+#if defined(TARGET_PPC64)
+case SPR_CFAR:
+val = env->cfar;
+break;
+#endif
+case SPR_HDEC:
+val = cpu_ppc_load_hdecr(env);
+break;
+case SPR_TBL:
+val = cpu_ppc_load_tbl(env);
+break;
+case SPR_TBU:
+val = cpu_ppc_load_tbu(env);
+break;
+case SPR_DECR:
+val = cpu_ppc_load_decr(env);
+break;
+default:
+val = env->spr[reg];
+}
+gdb_get_regl(buf, val);
+
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
return len;
}
@@ -429,7 +454,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t
*mem_buf, int n)
len = TARGET_LONG_SIZE;
ppc_maybe_bswap_register(env, mem_buf, len);
-env->spr[reg] = ldn_p(mem_buf, len);
+
+/* Handle those SPRs that are not part of the env->spr[] array */
+target_ulong val = ldn_p(mem_buf, len);
+switch (reg) {
+#if defined(TARGET_PPC64)
+case SPR_CFAR:
+env->cfar = val;
+break;
+#endif
+default:
+env->spr[reg] = val;
+}
return len;
}
--
2.31.1
