Re: [Qemu-devel] [RISU PATCH] risu: Include on ppc64

[Sandipan Das]

On 07/06/19 6:55 PM, Peter Maydell wrote:
> To build the C parts of risu for ppc64le with recent glibc/kernel
> headers, we need to include sys/user.h to avoid a compile error,
> because sys/ucontext.h defines a struct which includes a pointer
> to 'struct pt_regs' but does not provide a definition of that struct.
> 
> Signed-off-by: Peter Maydell 

LGTM.

Reviewed-by: Sandipan Das 

> ---
> I need this to be able to do the ppc64le cross-build on my
> Ubuntu Bionic x86-64 system.
> 
>  risu_ppc64.c | 2 ++
>  risu_reginfo_ppc64.c | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/risu_ppc64.c b/risu_ppc64.c
> index 83f8d1f..a3028f7 100644
> --- a/risu_ppc64.c
> +++ b/risu_ppc64.c
> @@ -11,6 +11,8 @@
>   * based on Peter Maydell's risu_arm.c
>   
> */
> 
> +#include 
> +
>  #include "risu.h"
> 
>  void advance_pc(void *vuc)
> diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
> index f9d2f0d..071c951 100644
> --- a/risu_reginfo_ppc64.c
> +++ b/risu_reginfo_ppc64.c
> @@ -16,6 +16,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #include "risu.h"
>  #include "risu_reginfo_ppc64.h"
> 

[Qemu-devel] [PATCH risu] ppc64.risu: Fix pattern for darn

[Sandipan Das]

This fixes the pattern for the Deliver A Random Number (darn)
instruction to ensure that the value of the L field, which is
used to determine the type and length of the generated random
number, is never 3 which is currently reserved for future use.

Signed-off-by: Sandipan Das 
---
 ppc64.risu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ppc64.risu b/ppc64.risu
index 2018103..a27e4fd 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -277,7 +277,7 @@ DADDQd PPC64LE 11 frtp:5 frap:5 frbp:5 101
 
 # format:X book:I page:79 v3.0 darn Deliver A Random Number
 DARN PPC64LE 01 rt:5 000 l:2 01000110 \
-!constraints { $rt != 1 && $rt != 13; }
+!constraints { $rt != 1 && $rt != 13 && $l != 3; }
 
 # format:X book:I page:217 v2.06 dcffix DFP Convert From Fixed
 DCFFIX PPC64LE 111011 frt:5 0 frb:5 11001000100
-- 
2.14.4

[Qemu-devel] [PATCH] target-ppc: Extend HWCAP2 bits for ISA 3.0

[Sandipan Das]

This adds the HWCAP2 bit to detect if a linux user process is
running on an ISA 3.0 compliant cpu like POWER9. This can be
verified using a simple test program that prints the value in
the auxiliary vector for AT_HWCAP2 as shown below.

Before:
  $ qemu-ppc64le -cpu power8 test
  0x8c00

  $ qemu-ppc64le -cpu power9 test
  0x8c00

After:
  $ qemu-ppc64le -cpu power8 test
  0x8c00

  $ qemu-ppc64le -cpu power9 test
  0x8c80

Signed-off-by: Sandipan Das 
---
 linux-user/elfload.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 8638612aec..e97c4cde49 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -710,6 +710,7 @@ enum {
 QEMU_PPC_FEATURE2_HAS_EBB = 0x1000, /* Event Base Branching */
 QEMU_PPC_FEATURE2_HAS_ISEL = 0x0800, /* Integer Select */
 QEMU_PPC_FEATURE2_HAS_TAR = 0x0400, /* Target Address Register */
+QEMU_PPC_FEATURE2_ARCH_3_00 = 0x0080, /* ISA 3.00 */
 };
 
 #define ELF_HWCAP get_elf_hwcap()
@@ -764,6 +765,7 @@ static uint32_t get_elf_hwcap2(void)
 GET_FEATURE2(PPC2_BCTAR_ISA207, QEMU_PPC_FEATURE2_HAS_TAR);
 GET_FEATURE2((PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
   PPC2_ISA207S), QEMU_PPC_FEATURE2_ARCH_2_07);
+GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00);
 
 #undef GET_FEATURE
 #undef GET_FEATURE2
-- 
2.14.4

[Qemu-devel] [PATCH risu v2 3/3] risu_reginfo_ppc64.c: Fix register name prefix

[Sandipan Das]

Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 risu_reginfo_ppc64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..5f33648 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -122,7 +122,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
 fprintf(f, "\tdscr   : %16lx\n\n", ri->gregs[44]);
 
 for (i = 0; i < 16; i++) {
-fprintf(f, "\tf%2d: %.4f\tr%2d: %.4f\n", i, ri->fpregs[i],
+fprintf(f, "\tf%2d: %.4f\tf%2d: %.4f\n", i, ri->fpregs[i],
 i + 16, ri->fpregs[i + 16]);
 }
 fprintf(f, "\tfpscr: %f\n\n", ri->fpregs[32]);
@@ -167,7 +167,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo 
*a, FILE *f)
 }
 
 if (m->fpregs[i] != a->fpregs[i]) {
-fprintf(f, "Mismatch: Register r%d\n", i);
+fprintf(f, "Mismatch: Register f%d\n", i);
 fprintf(f, "m: [%f] != a: [%f]\n", m->fpregs[i], a->fpregs[i]);
 }
 }
-- 
2.14.3

[Qemu-devel] [PATCH risu v2 2/3] ppc64.risu: Fix pattern for load qword

[Sandipan Das]

The pattern for the Load Quadword (lq) instruction is fixed.

If rtp is 0 or 12, the instruction will overwrite r0, r1 or
r12, r13 respectively. However, r1 is the stack frame pointer
and r13 is the thread pointer. So, overwriting them can cause
a crash. This is avoided by putting a constraint to prevent
rtp from being 0 or 12.

For a given effective address (ea), this instruction loads
two dwords from ea and ea+8. However, if ea is the start
address of the current stack frame, then the value of the
back chain dword from the previous stack frame, which is at
ea+8, is loaded on to one of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 ppc64.risu | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 13b95ac..2018103 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1050,8 +1050,8 @@ LHZX PPC64LE 01 rt:5 ra:5 rb:5 01000101110 \
 
 # format:DQ book:I page:59 v2.03 lq Load Qword
 LQ PPC64LE 111000 rtp:5 ra:5 imm:12  \
-!constraints { $rtp % 2 == 0 && $ra != 1 && $ra != 13 && $ra != 0 && $ra != 
$rtp && $imm <= 2032; } \
-!memory { reg_plus_imm($ra, $imm << 4); }
+!constraints { $rtp % 2 == 0 && $rtp != 0 && $rtp != 12 && $ra != 1 && $ra != 
13 && $ra != 0 && $ra != $rtp && $imm <= 2032; } \
+!memory { reg_plus_imm($ra, ($imm << 4) + 8); }
 
 # format:X book:I page:65 v:P1 lswi Load String Word Immediate
 LSWI PPC64LE 01 rt:5 ra:5 rb:5 10010101010 \
-- 
2.14.3

[Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads

[Sandipan Das]

The patterns for the following instructions are added:
 * Load Byte and Zero (lbz)
 * Load Byte and Zero with Update (lbzu)
 * Load Byte and Zero Indexed (lbzx)
 * Load Byte and Zero with Update Indexed (lbzux)
 * Load Doubleword (ld)

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 ppc64.risu | 25 +
 1 file changed, 25 insertions(+)

diff --git a/ppc64.risu b/ppc64.risu
index e2fd4f6..13b95ac 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -887,6 +887,31 @@ FTSQRT PPC64LE 11 bf:3 000 frb:5 0010100
 ISEL PPC64LE 01 rt:5 ra:5 rb:5 bc:5 00 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13; }
 
+# format:D book:I page:48 v:P1 lbz Load Byte & Zero
+LBZ PPC64LE 100010 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:D book:I page:48 v:P1 lbzu Load Byte & Zero with Update
+LBZU PPC64LE 100011 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:X book:I page:49 v:P1 lbzux Load Byte & Zero with Update Indexed
+LBZUX PPC64LE 01 rt:5 ra:5 rb:5 00011101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:X book:I page:49 v:P1 lbzx Load Byte & Zero Indexed
+LBZX PPC64LE 01 rt:5 ra:5 rb:5 00010101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:DS book:I page:53 PPC ld Load Dword
+LD PPC64LE 111010 rt:5 ra:5 imm:14 00 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 8176; } \
+!memory { reg_plus_imm($ra, $imm << 2); }
+
 # format:X book:I page:62 v2.06 ldbrx Load Dword Byte-Reverse Indexed
 LDBRX PPC64LE 01 rt:5 ra:5 rb:5 1101000 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
-- 
2.14.3

[Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64

[Sandipan Das]

The first patch adds the patterns for the missing byte and
doubleword load instructions. The second patch fixes mismatches
encountered when using the load quadword instruction. The last
patch fixes a minor typo in the floating-point register prefix
shown when dumping the register values.

Changelog:
v2 -> Added a cover letter as requested by Peter.

Sandipan Das (3):
  ppc64.risu: Add missing byte and dword loads
  ppc64.risu: Fix pattern for load qword
  risu_reginfo_ppc64.c: Fix register name prefix

 ppc64.risu   | 29 +++--
 risu_reginfo_ppc64.c |  4 ++--
 2 files changed, 29 insertions(+), 4 deletions(-)

-- 
2.14.3

Re: [Qemu-devel] [PATCH risu 1/3] ppc64.risu: Add missing byte and dword loads

[Sandipan Das]

On 03/06/2018 05:09 PM, Peter Maydell wrote:
> On 6 March 2018 at 06:42, Sandipan Das <sandi...@linux.vnet.ibm.com> wrote:
>> The patterns for the following instructions are added:
>>  * Load Byte and Zero (lbz)
>>  * Load Byte and Zero with Update (lbzu)
>>  * Load Byte and Zero Indexed (lbzx)
>>  * Load Byte and Zero with Update Indexed (lbzux)
>>  * Load Doubleword (ld)
>>
>> Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
> 
> Hi -- this patchset doesn't seem to have a cover letter. Could
> you resend it with one, please? Our automated patch handling
> tools all expect a cover letter if there's more than one patch
> in a set.
> 
> thanks
> -- PMM
> 
> 

Sure

--
With Regards,
Sandipan

[Qemu-devel] [PATCH risu 3/3] risu_reginfo_ppc64.c: Fix register name prefix

[Sandipan Das]

Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 risu_reginfo_ppc64.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..5f33648 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -122,7 +122,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
 fprintf(f, "\tdscr   : %16lx\n\n", ri->gregs[44]);
 
 for (i = 0; i < 16; i++) {
-fprintf(f, "\tf%2d: %.4f\tr%2d: %.4f\n", i, ri->fpregs[i],
+fprintf(f, "\tf%2d: %.4f\tf%2d: %.4f\n", i, ri->fpregs[i],
 i + 16, ri->fpregs[i + 16]);
 }
 fprintf(f, "\tfpscr: %f\n\n", ri->fpregs[32]);
@@ -167,7 +167,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo 
*a, FILE *f)
 }
 
 if (m->fpregs[i] != a->fpregs[i]) {
-fprintf(f, "Mismatch: Register r%d\n", i);
+fprintf(f, "Mismatch: Register f%d\n", i);
 fprintf(f, "m: [%f] != a: [%f]\n", m->fpregs[i], a->fpregs[i]);
 }
 }
-- 
2.14.3

[Qemu-devel] [PATCH risu 2/3] ppc64.risu: Fix pattern for load qword

[Sandipan Das]

The pattern for the Load Quadword (lq) instruction is fixed.

If rtp is 0 or 12, the instruction will overwrite r0, r1 or
r12, r13 respectively. However, r1 is the stack frame pointer
and r13 is the thread pointer. So, overwriting them can cause
a crash. This is avoided by putting a constraint to prevent
rtp from being 0 or 12.

For a given effective address (ea), this instruction loads
two dwords from ea and ea+8. However, if ea is the start
address of the current stack frame, then the value of the
back chain dword from the previous stack frame, which is at
ea+8, is loaded on to one of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 ppc64.risu | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 13b95ac..2018103 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1050,8 +1050,8 @@ LHZX PPC64LE 01 rt:5 ra:5 rb:5 01000101110 \
 
 # format:DQ book:I page:59 v2.03 lq Load Qword
 LQ PPC64LE 111000 rtp:5 ra:5 imm:12  \
-!constraints { $rtp % 2 == 0 && $ra != 1 && $ra != 13 && $ra != 0 && $ra != 
$rtp && $imm <= 2032; } \
-!memory { reg_plus_imm($ra, $imm << 4); }
+!constraints { $rtp % 2 == 0 && $rtp != 0 && $rtp != 12 && $ra != 1 && $ra != 
13 && $ra != 0 && $ra != $rtp && $imm <= 2032; } \
+!memory { reg_plus_imm($ra, ($imm << 4) + 8); }
 
 # format:X book:I page:65 v:P1 lswi Load String Word Immediate
 LSWI PPC64LE 01 rt:5 ra:5 rb:5 10010101010 \
-- 
2.14.3

[Qemu-devel] [PATCH risu 1/3] ppc64.risu: Add missing byte and dword loads

[Sandipan Das]

The patterns for the following instructions are added:
 * Load Byte and Zero (lbz)
 * Load Byte and Zero with Update (lbzu)
 * Load Byte and Zero Indexed (lbzx)
 * Load Byte and Zero with Update Indexed (lbzux)
 * Load Doubleword (ld)

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
 ppc64.risu | 25 +
 1 file changed, 25 insertions(+)

diff --git a/ppc64.risu b/ppc64.risu
index e2fd4f6..13b95ac 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -887,6 +887,31 @@ FTSQRT PPC64LE 11 bf:3 000 frb:5 0010100
 ISEL PPC64LE 01 rt:5 ra:5 rb:5 bc:5 00 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13; }
 
+# format:D book:I page:48 v:P1 lbz Load Byte & Zero
+LBZ PPC64LE 100010 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:D book:I page:48 v:P1 lbzu Load Byte & Zero with Update
+LBZU PPC64LE 100011 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:X book:I page:49 v:P1 lbzux Load Byte & Zero with Update Indexed
+LBZUX PPC64LE 01 rt:5 ra:5 rb:5 00011101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:X book:I page:49 v:P1 lbzx Load Byte & Zero Indexed
+LBZX PPC64LE 01 rt:5 ra:5 rb:5 00010101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:DS book:I page:53 PPC ld Load Dword
+LD PPC64LE 111010 rt:5 ra:5 imm:14 00 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && 
$ra != $rt && $imm <= 8176; } \
+!memory { reg_plus_imm($ra, $imm << 2); }
+
 # format:X book:I page:62 v2.06 ldbrx Load Dword Byte-Reverse Indexed
 LDBRX PPC64LE 01 rt:5 ra:5 rb:5 1101000 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && 
$rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
-- 
2.14.3

[Qemu-devel] [PATCH v4] target/ppc: Fix carry flag setting for shift algebraic instructions

[Sandipan Das]

For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])
  * Shift Right Algebraic Doubleword (srad[.])
  * Shift Right Algebraic Doubleword Immediate (sradi[.])

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()

v3: Remove explicit checking for ISA v3.0 when setting CA32

v4: Set CA32 only when CA is being modified (as Richard suggested)
Set CA32 after checking for ISA300 in gen_* functions (as David suggested)
---
 target/ppc/int_helper.c | 16 
 target/ppc/translate.c  | 12 
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index da4e1a62c9..1c013a0ee3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -219,17 +219,17 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulong 
value,
 shift &= 0x1f;
 ret = (int32_t)value >> shift;
 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
-env->ca = 0;
+env->ca32 = env->ca = 0;
 } else {
-env->ca = 1;
+env->ca32 = env->ca = 1;
 }
 } else {
 ret = (int32_t)value;
-env->ca = 0;
+env->ca32 = env->ca = 0;
 }
 } else {
 ret = (int32_t)value >> 31;
-env->ca = (ret != 0);
+env->ca32 = env->ca = (ret != 0);
 }
 return (target_long)ret;
 }
@@ -245,17 +245,17 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong 
value,
 shift &= 0x3f;
 ret = (int64_t)value >> shift;
 if (likely(ret >= 0 || (value & ((1ULL << shift) - 1)) == 0)) {
-env->ca = 0;
+env->ca32 = env->ca = 0;
 } else {
-env->ca = 1;
+env->ca32 = env->ca = 1;
 }
 } else {
 ret = (int64_t)value;
-env->ca = 0;
+env->ca32 = env->ca = 0;
 }
 } else {
 ret = (int64_t)value >> 63;
-env->ca = (ret != 0);
+env->ca32 = env->ca = (ret != 0);
 }
 return ret;
 }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 606b605ba0..a81ff69d75 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2181,6 +2181,9 @@ static void gen_srawi(DisasContext *ctx)
 if (sh == 0) {
 tcg_gen_ext32s_tl(dst, src);
 tcg_gen_movi_tl(cpu_ca, 0);
+if (is_isa300(ctx)) {
+tcg_gen_movi_tl(cpu_ca32, 0);
+}
 } else {
 TCGv t0;
 tcg_gen_ext32s_tl(dst, src);
@@ -2190,6 +2193,9 @@ static void gen_srawi(DisasContext *ctx)
 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
 tcg_temp_free(t0);
 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+if (is_isa300(ctx)) {
+tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+}
 tcg_gen_sari_tl(dst, dst, sh);
 }
 if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -2259,6 +2265,9 @@ static inline void gen_sradi(DisasContext *ctx, int n)
 if (sh == 0) {
 tcg_gen_mov_tl(dst, src);
 tcg_gen_movi_tl(cpu_ca, 0);
+if (is_isa300(ctx)) {
+tcg_gen_movi_tl(cpu_ca32, 0);
+}
 } else {
 TCGv t0;
 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
@@ -2267,6 +2276,9 @@ static inline void gen_sradi(DisasContext *ctx, int n)
 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
 tcg_temp_free(t0);
 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
+if (is_isa300(ctx)) {
+tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+}
 tcg_gen_sari_tl(dst, src, sh);
 }
 if (unlikely(Rc(ctx->opcode) != 0)) {
-- 
2.13.6

[Qemu-devel] [PATCH v3] target/ppc: Fix carry flag setting for shift algebraic instructions

[Sandipan Das]

For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])
  * Shift Right Algebraic Doubleword (srad[.])
  * Shift Right Algebraic Doubleword Immediate (sradi[.])

Signed-off-by: Sandipan Das <sandi...@linux.vnet.ibm.com>
---
v2: Add tcg_temp_free() required in gen_sraw() and gen_srad()

v3: Remove explicit checking for ISA v3.0 when setting CA32
---
 target/ppc/int_helper.c | 8 
 target/ppc/translate.c  | 8 
 2 files changed, 16 insertions(+)

diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index da4e1a62c9..0bdd96aebe 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -231,6 +231,10 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulong 
value,
 ret = (int32_t)value >> 31;
 env->ca = (ret != 0);
 }
+
+/* update CA32 for ISA v3.0 */
+env->ca32 = env->ca;
+
 return (target_long)ret;
 }
 
@@ -257,6 +261,10 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong 
value,
 ret = (int64_t)value >> 63;
 env->ca = (ret != 0);
 }
+
+/* update CA32 for ISA v3.0 */
+env->ca32 = env->ca;
+
 return ret;
 }
 #endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 606b605ba0..c35a2027eb 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2192,6 +2192,10 @@ static void gen_srawi(DisasContext *ctx)
 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
 tcg_gen_sari_tl(dst, dst, sh);
 }
+
+/* update CA32 for ISA v3.0 */
+tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+
 if (unlikely(Rc(ctx->opcode) != 0)) {
 gen_set_Rc0(ctx, dst);
 }
@@ -2269,6 +2273,10 @@ static inline void gen_sradi(DisasContext *ctx, int n)
 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
 tcg_gen_sari_tl(dst, src, sh);
 }
+
+/* update CA32 for ISA v3.0 */
+tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+
 if (unlikely(Rc(ctx->opcode) != 0)) {
 gen_set_Rc0(ctx, dst);
 }
-- 
2.13.5

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

[Sandipan Das]

On Monday 22 May 2017 12:33 PM, Nikunj A Dadhania wrote:
> Sandipan Das <sandipandas1...@gmail.com> writes:
> 
>> The patterns for the following instructions are fixed:
>>  * Rotate Left Doubleword then Clear Right (rldcr[.])
>>  * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>>  * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>>
>> Signed-off-by: Sandipan Das <sandipandas1...@gmail.com>
>> ---
>>  ppc64.risu | 10 +-
>>  1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/ppc64.risu b/ppc64.risu
>> index 28df9da..0f29248 100644
>> --- a/ppc64.risu
>> +++ b/ppc64.risu
>> @@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
>> -RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
>> +RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
>>  RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
>> @@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 
>> 1 \
>>  !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
>>
>>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
>> then Clear Right
>> -RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
>> +RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \
> 
>RLDICR PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0
> 
> Also "rb:5" be changed as "sh:5"?

Yes, I missed that.

> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
>> then Clear Right
>> -RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
>> +RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \
> 
>RLDICRd PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0
> 
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
>> then Mask Insert
>> -RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
>> +RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \
> 
>RLDIMI PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 0
> 
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
>> then Mask Insert
>> -RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
>> +RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \
> 
>RLDIMId PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 1
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate 
>> then Mask Insert
>> -- 
>> 2.7.4
> 
> Regards,
> Nikunj
> 

With Regards,
Sandipan

[Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

[Sandipan Das]

The patterns for the following instructions are fixed:
 * Rotate Left Doubleword then Clear Right (rldcr[.])
 * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
 * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

Signed-off-by: Sandipan Das <sandipandas1...@gmail.com>
---
 ppc64.risu | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 28df9da..0f29248 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
-RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
+RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
 RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
@@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
 
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
+RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
+RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
+RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
+RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then 
Mask Insert
-- 
2.7.4

[Qemu-devel] [PATCH risu v2] ppc64: Fix patterns for rotate doubleword instructions

[Sandipan Das]

The patterns for the following instructions are fixed:
 * Rotate Left Doubleword then Clear Right (rldcr[.])
 * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
 * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

The first instruction has a typo. For the other two instructions,
the extended opcodes are incorrect and the shift field 'sha' is
absent. Also, the shift field 'sh' should be used in place of the
register field 'rb'.

Signed-off-by: Sandipan Das <sandipandas1...@gmail.com>
---
 ppc64.risu | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 28df9da..dd304e2 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
-RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
+RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
 RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
@@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
 
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
+RLDICR PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
+RLDICRd PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
+RLDIMI PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
+RLDIMId PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then 
Mask Insert
-- 
2.7.4