Re: [Qemu-devel] QEMU API for modelling of user's hardware
I've tried to collect some information from the QEMU sources (I've built my local LXR service with QEMU sources tom make it easier ;-) ), and from different web sources. As a result I've prepared a model of Bus Mastering PCI device which is a simple AES256 accelerator. Sources are available on alt.sources (subject:WZENC1 - Model of Bus Mastering PCI AES256 accelerator for QEM) or in Google archive: http://groups.google.com/group/alt.sources/browse_thread/thread/cc80f25d573813f5 I hope, that it will be useful as didactic aid for implementing of device drivers, but may also be a skeleton for model of real hardware... -- Regards, Wojtek
Re: [Qemu-devel] QEMU API for modelling of user's hardware
I've found the following source of information regarding writing of device models for QEMU: http://www.linux-kvm.org/wiki/images/f/fe/2010-forum-armbru-qdev.pdf http://www.google.com/url?sa=Dq=http://www.linux-kvm.org/wiki/images/f/fe/2010-forum-armbru-qdev.pdf Is there any better or more detailed description (except of sources themselves ;-) )? -- TIA Regards, Wojtek
[Qemu-devel] Model of simple Bus Mastering ADC for QEMU
Hi All, I'm interested in using of QEMU as a simple environment providing virtual hardware for my students, learning how to write device drivers for different devices. Unfortunately the QEMU's API seems to be not very strictly documented :-(. I've tried to implement a simple Analog to Digital Converter model, connected directly to the PC system bus (at 0x4100 physical address) and using the IRQ 5 line via standard ISA PIC. The ADC is able to take control over the system bus and write the data into the system RAM, after the physical address of allocated RAM is written by the driver to proper registers (one register per page). I'd appreciate any remarks regarding my implementation. The model is working, but I don't know if I have correctly used functionalities of QEMU. Next step should be to extend the model with the PCI interface... BTW. Is it possible to write similar models for devices connected via SPI interface to the embedded system? If you are interested, you can find my sources (model, Linux driver anmd sample program using it) in the alt.sources usenet group, as a message with subject: Model of Bus Mastering ADC implemented in QEMU or message slrniq9end.7tm.w...@wzab.nasz.dom or simply in the Google archive: http://groups.google.com/group/alt.sources/msg/4592a94e584b85a6 -- Best Regards, Wojtek Zabolotny
[Qemu-devel] QEMU API for modelling of user's hardware
Hi, I wanted to prepare QEMU models of new hardware for my students, to let them to write and debug device drivers before the real hardware is available (or even to optimize the design of this hardware before it is really made). I was able to establish the basic communication with memory mapped registers of my device, but when it comes to more advanced topics like DMA and interrupts, things start to be difficult. Is there any reference or manual for people trying to write device models for QEMU? I know that the hw subdirectory is full of examples, but I'd prefere something more formal, with info which solutions are optimal, which are deprecated... Thank you very much in advance, Wojciech Zabolotny
