Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
On Tue, Nov 15, 2022 at 9:56 AM Philippe Mathieu-Daudé
wrote:
>
> On 14/11/22 11:34, Frédéric Pétrot wrote:
> > Le 14/11/2022 à 09:40, Philippe Mathieu-Daudé a écrit :
> >> On 11/11/22 13:19, Frédéric Pétrot wrote:
>
>
> >> Eventually we could unify the style:
> >>
> >> -- >8 --
> >> @@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr,
> >> char *hart_config,
> >> CPUState *cpu = qemu_get_cpu(cpu_num);
> >>
> >> if (plic->addr_config[i].mode == PLICMode_M) {
> >> -qdev_connect_gpio_out(dev, num_harts - plic->hartid_base
> >> + cpu_num,
> >> +qdev_connect_gpio_out(dev, cpu_num - hartid_base +
> >> num_harts,
> >> qdev_get_gpio_in(DEVICE(cpu),
> >> IRQ_M_EXT));
> >> }
> >> if (plic->addr_config[i].mode == PLICMode_S) {
> >> -qdev_connect_gpio_out(dev, cpu_num,
> >> +qdev_connect_gpio_out(dev, cpu_num - hartid_base,hartid_base
> >> qdev_get_gpio_in(DEVICE(cpu),
> >> IRQ_S_EXT));
> >> }
> >> }
> >> ---
> >
> >IIUC hartid_base is used to set plic->hartid_base, so agreed, along
> > with the
> >style unification.
> >I'll send a v2, then.
> >Since Alistair already queued the patch, how shall I proceed?
>
> I didn't notice Alistair queued (he usually send a notification by
> responding "queued" to the patches). If it is queued, then too late
> (and not a big deal) -- you can still post the v2 and let him pick
> it :)
Yep! I'll drop it from my queue and take the v2
Alistair
>
Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
On Fri, Nov 11, 2022 at 10:20 PM Frédéric Pétrot
wrote:
>
> Commit 40244040 changed the way the S irqs are numbered. This breaks when
> using numa configuration, e.g.:
> ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
> -m 2G -smp cpus=16 \
> -object memory-backend-ram,id=mem0,size=512M \
> -object memory-backend-ram,id=mem1,size=512M \
> -object memory-backend-ram,id=mem2,size=512M \
> -object memory-backend-ram,id=mem3,size=512M \
> -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
> -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
> -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
> -numa node,cpus=12-15,memdev=mem3,nodeid=3
> leads to:
> Unexpected error in object_property_find_err() at ../qom/object.c:1304:
> qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
> found
>
> This patch makes the nubering of the S irqs identical to what it was before.
>
> Signed-off-by: Frédéric Pétrot
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/intc/sifive_plic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index c2dfacf028..89d2122742 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -480,7 +480,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char
> *hart_config,
>qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
> }
> if (plic->addr_config[i].mode == PLICMode_S) {
> -qdev_connect_gpio_out(dev, cpu_num,
> +qdev_connect_gpio_out(dev, cpu_num - plic->hartid_base,
>qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
> }
> }
> --
> 2.37.2
>
>
Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
On 11/11/22 13:19, Frédéric Pétrot wrote:
Commit 40244040 changed the way the S irqs are numbered. This breaks when
40244040a7 in case?
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=mem0,size=512M \
-object memory-backend-ram,id=mem1,size=512M \
-object memory-backend-ram,id=mem2,size=512M \
-object memory-backend-ram,id=mem3,size=512M \
-numa node,cpus=0-3,memdev=mem0,nodeid=0 \
-numa node,cpus=4-7,memdev=mem1,nodeid=1 \
-numa node,cpus=8-11,memdev=mem2,nodeid=2 \
-numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Signed-off-by: Frédéric Pétrot
---
hw/intc/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c2dfacf028..89d2122742 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -480,7 +480,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
-qdev_connect_gpio_out(dev, cpu_num,
+qdev_connect_gpio_out(dev, cpu_num - plic->hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
Oops.
Eventually we could unify the style:
-- >8 --
@@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
-qdev_connect_gpio_out(dev, num_harts - plic->hartid_base +
cpu_num,
+qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
qdev_get_gpio_in(DEVICE(cpu),
IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
-qdev_connect_gpio_out(dev, cpu_num,
+qdev_connect_gpio_out(dev, cpu_num - hartid_base,
qdev_get_gpio_in(DEVICE(cpu),
IRQ_S_EXT));
}
}
---
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
On 14/11/22 11:34, Frédéric Pétrot wrote:
Le 14/11/2022 à 09:40, Philippe Mathieu-Daudé a écrit :
On 11/11/22 13:19, Frédéric Pétrot wrote:
Eventually we could unify the style:
-- >8 --
@@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr,
char *hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
- qdev_connect_gpio_out(dev, num_harts - plic->hartid_base
+ cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base +
num_harts,
qdev_get_gpio_in(DEVICE(cpu),
IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
- qdev_connect_gpio_out(dev, cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base,hartid_base
qdev_get_gpio_in(DEVICE(cpu),
IRQ_S_EXT));
}
}
---
IIUC hartid_base is used to set plic->hartid_base, so agreed, along
with the
style unification.
I'll send a v2, then.
Since Alistair already queued the patch, how shall I proceed?
I didn't notice Alistair queued (he usually send a notification by
responding "queued" to the patches). If it is queued, then too late
(and not a big deal) -- you can still post the v2 and let him pick
it :)
Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
Le 14/11/2022 à 09:40, Philippe Mathieu-Daudé a écrit :
On 11/11/22 13:19, Frédéric Pétrot wrote:
Commit 40244040 changed the way the S irqs are numbered. This breaks when
40244040a7 in case?
Seems reasonnable, indeed, I'll even align with what git blame shows
(11 chars, so 40244040a7a).
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=mem0,size=512M \
-object memory-backend-ram,id=mem1,size=512M \
-object memory-backend-ram,id=mem2,size=512M \
-object memory-backend-ram,id=mem3,size=512M \
-numa node,cpus=0-3,memdev=mem0,nodeid=0 \
-numa node,cpus=4-7,memdev=mem1,nodeid=1 \
-numa node,cpus=8-11,memdev=mem2,nodeid=2 \
-numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Signed-off-by: Frédéric Pétrot
---
hw/intc/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c2dfacf028..89d2122742 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -480,7 +480,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
- qdev_connect_gpio_out(dev, cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - plic->hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
Oops. >
Eventually we could unify the style:
-- >8 --
@@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
- qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
- qdev_connect_gpio_out(dev, cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base,hartid_base
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
---
IIUC hartid_base is used to set plic->hartid_base, so agreed, along with the
style unification.
I'll send a v2, then.
Since Alistair already queued the patch, how shall I proceed?
Reviewed-by: Philippe Mathieu-Daudé
--
+---+
| Frédéric Pétrot,Pr. Grenoble INP-Ensimag/TIMA |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
+---+
Re: [PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
On Fri, Nov 11, 2022 at 10:20 PM Frédéric Pétrot
wrote:
>
> Commit 40244040 changed the way the S irqs are numbered. This breaks when
> using numa configuration, e.g.:
> ./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
> -m 2G -smp cpus=16 \
> -object memory-backend-ram,id=mem0,size=512M \
> -object memory-backend-ram,id=mem1,size=512M \
> -object memory-backend-ram,id=mem2,size=512M \
> -object memory-backend-ram,id=mem3,size=512M \
> -numa node,cpus=0-3,memdev=mem0,nodeid=0 \
> -numa node,cpus=4-7,memdev=mem1,nodeid=1 \
> -numa node,cpus=8-11,memdev=mem2,nodeid=2 \
> -numa node,cpus=12-15,memdev=mem3,nodeid=3
> leads to:
> Unexpected error in object_property_find_err() at ../qom/object.c:1304:
> qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
> found
>
> This patch makes the nubering of the S irqs identical to what it was before.
>
> Signed-off-by: Frédéric Pétrot
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/intc/sifive_plic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index c2dfacf028..89d2122742 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -480,7 +480,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char
> *hart_config,
>qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
> }
> if (plic->addr_config[i].mode == PLICMode_S) {
> -qdev_connect_gpio_out(dev, cpu_num,
> +qdev_connect_gpio_out(dev, cpu_num - plic->hartid_base,
>qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
> }
> }
> --
> 2.37.2
>
>
[PATCH] hw/intc: sifive_plic: Renumber the S irqs for numa support
Commit 40244040 changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=mem0,size=512M \
-object memory-backend-ram,id=mem1,size=512M \
-object memory-backend-ram,id=mem2,size=512M \
-object memory-backend-ram,id=mem3,size=512M \
-numa node,cpus=0-3,memdev=mem0,nodeid=0 \
-numa node,cpus=4-7,memdev=mem1,nodeid=1 \
-numa node,cpus=8-11,memdev=mem2,nodeid=2 \
-numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Signed-off-by: Frédéric Pétrot
---
hw/intc/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c2dfacf028..89d2122742 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -480,7 +480,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
-qdev_connect_gpio_out(dev, cpu_num,
+qdev_connect_gpio_out(dev, cpu_num - plic->hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
--
2.37.2
