Fix the exception classes for some SSE/AVX instructions to match what is
documented in the Intel manual.
Most of these changes have no functional effect on the behavior that
qemu implements (primarily >= 16-byte memory alignment checks). For
example, since qemu does not implement the AC flag, there is no
difference in behavior between Exception Classes 4 and 5 for
instructions where the SSE version only takes <16 byte memory operands.
There is one functional change:
Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class
4 (only requiring alignment for legacy SSE instructions). This changes
them to Exception Class 1 (always requiring memory alignment), as
documented in the Intel manual.
Signed-off-by: Ricky Zhou
---
target/i386/tcg/decode-new.c.inc | 79
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index d5fd8d965c..a9060c3268 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -237,7 +237,7 @@ static void decode_group14(DisasContext *s, CPUX86State
*env, X86OpEntry *entry,
static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F6F[4] = {
-X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
+X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa
*/
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu
*/
{},
@@ -274,9 +274,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
{
static const X86OpEntry opcodes_0F78[4] = {
{},
-X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)),
+X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /*
AMD extension */
{},
-X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w,cpuid(SSE4A)),
+X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w,cpuid(SSE4A)), /*
AMD extension */
};
*entry = *decode_by_prefix(s, opcodes_0F78);
}
@@ -284,9 +284,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
if (s->prefix & PREFIX_REPNZ) {
-entry->gen = gen_INSERTQ_r;
+entry->gen = gen_INSERTQ_r; /* AMD extension */
} else if (s->prefix & PREFIX_DATA) {
-entry->gen = gen_EXTRQ_r;
+entry->gen = gen_EXTRQ_r; /* AMD extension */
} else {
entry->gen = NULL;
};
@@ -306,7 +306,7 @@ static void decode_0F7E(DisasContext *s, CPUX86State *env,
X86OpEntry *entry, ui
static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F7F[4] = {
-X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx), /* movq */
+X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu
*/
{},
@@ -639,15 +639,15 @@ static void decode_0F10(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
static const X86OpEntry opcodes_0F10_reg[4] = {
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
-X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4),
-X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */
+X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5),
+X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */
};
static const X86OpEntry opcodes_0F10_mem[4] = {
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS
*/
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD
*/
-X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4),
-X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4),
+X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5),
+X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5),
};
if ((get_modrm(s, env) >> 6) == 3) {
@@ -660,17 +660,17 @@ static void decode_0F10(DisasContext *s, CPUX86State
*env, X86OpEntry *entry, ui
static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
uint8_t *b)
{
static const X86OpEntry opcodes_0F11_reg[4] = {
-X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
-X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
-X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4),
-X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */
+
