Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
On Fri, Jun 3, 2022 at 1:55 AM Frédéric Pétrot wrote: > > Add an MXL_RV128 case in two switches so that no error is triggered when > using the -cpu x-rv128 option. > > Signed-off-by: Frédéric Pétrot Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/debug.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index 2f2a51c732..fc6e13222f 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env, > tdata1 = RV32_TYPE(type); > break; > case MXL_RV64: > +case MXL_RV128: > tdata1 = RV64_TYPE(type); > break; > default: > @@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, > target_ulong val, > tdata1 = RV32_TYPE(t); > break; > case MXL_RV64: > +case MXL_RV128: > type = extract64(val, 60, 4); > dmode = extract64(val, 59, 1); > tdata1 = RV64_TYPE(t); > -- > 2.36.1 > >
Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
On Fri, Jun 3, 2022 at 1:55 AM Frédéric Pétrot wrote: > > Add an MXL_RV128 case in two switches so that no error is triggered when > using the -cpu x-rv128 option. > > Signed-off-by: Frédéric Pétrot Acked-by: Alistair Francis Alistair > --- > target/riscv/debug.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index 2f2a51c732..fc6e13222f 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env, > tdata1 = RV32_TYPE(type); > break; > case MXL_RV64: > +case MXL_RV128: > tdata1 = RV64_TYPE(type); > break; > default: > @@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, > target_ulong val, > tdata1 = RV32_TYPE(t); > break; > case MXL_RV64: > +case MXL_RV128: > type = extract64(val, 60, 4); > dmode = extract64(val, 59, 1); > tdata1 = RV64_TYPE(t); > -- > 2.36.1 > >
Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
On Thu, Jun 2, 2022 at 11:55 PM Frédéric Pétrot wrote: > > Add an MXL_RV128 case in two switches so that no error is triggered when > using the -cpu x-rv128 option. > > Signed-off-by: Frédéric Pétrot > --- > target/riscv/debug.c | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Bin Meng
[PATCH] target/riscv/debug.c: keep experimental rv128 support working
Add an MXL_RV128 case in two switches so that no error is triggered when using the -cpu x-rv128 option. Signed-off-by: Frédéric Pétrot --- target/riscv/debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 2f2a51c732..fc6e13222f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env, tdata1 = RV32_TYPE(type); break; case MXL_RV64: +case MXL_RV128: tdata1 = RV64_TYPE(type); break; default: @@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, tdata1 = RV32_TYPE(t); break; case MXL_RV64: +case MXL_RV128: type = extract64(val, 60, 4); dmode = extract64(val, 59, 1); tdata1 = RV64_TYPE(t); -- 2.36.1
