Re: [PATCH 03/12] target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec

2022-09-24 Thread Richard Henderson 

On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:

+static bool do_vx_vaddsubcuw(DisasContext *ctx, arg_VX *a, int add)
+{
+static const TCGOpcode vecop_list[] = {
+INDEX_op_cmp_vec, 0
+};
+
+static const GVecGen3 op[] = {
+{
+.fniv = gen_VSUBCUW,
+.fno = gen_helper_VSUBCUW,
+.opt_opc = vecop_list,
+.vece = MO_32
+},
+{
+.fniv = gen_VADDCUW,
+.fno = gen_helper_VADDCUW,
+.opt_opc = vecop_list,
+.vece = MO_32
+},


FWIW, you could implement the .fni4 hook and drop the helper, knowing that tcg won't 
choose to out-line 4x elements.



r~

Re: [PATCH 03/12] target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec

2022-09-24 Thread Richard Henderson 

On 9/23/22 21:47, Lucas Mateus Castro(alqotel) wrote:

+static void gen_VADDCUW(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+tcg_gen_not_vec(vece, a, a);
+tcg_gen_cmp_vec(TCG_COND_LTU, vece, t, a, b);
+tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(t, vece, 1));
+}


I wondered about negate instead of masking the low bit, but either works.

Reviewed-by: Richard Henderson 


r~

[PATCH 03/12] target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec

2022-09-23 Thread Lucas Mateus Castro(alqotel) 
From: "Lucas Mateus Castro (alqotel)" 

This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1

vaddcuw:
reptloopmaster patch
8   12500   0,01420600 0,00679200 (-52.2%)
25  40000,01781700 0,00524500 (-70.6%)
100 10000,02053300 0,00591800 (-71.2%)
500 200 0,02709800 0,01254600 (-53.7%)
250040  0,05537100 0,04347800 (-21.5%)
800012  0,13103100 0,12973600 (-1.0%)

vsubcuw:
reptloopmaster patch
8   12500   0,01426100 0,00685500 (-51.9%)
25  40000,01744600 0,00536000 (-69.3%)
100 10000,02029500 0,00597400 (-70.6%)
500 200 0,02654000 0,01263200 (-52.4%)
250040  0,05507200 0,04347100 (-21.1%)
800012  0,13072400 0,12872300 (-1.5%)

Overall there was a gain in performance, but the TCGop code was still
slightly bigger in the new version (it went from 4 to 5).

Signed-off-by: Lucas Mateus Castro (alqotel) 
---
 target/ppc/helper.h |  4 +--
 target/ppc/insn32.decode|  2 ++
 target/ppc/int_helper.c |  4 +--
 target/ppc/translate/vmx-impl.c.inc | 50 ++---
 target/ppc/translate/vmx-ops.c.inc  |  3 +-
 5 files changed, 53 insertions(+), 10 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f02a9497b7..edce059f2c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -193,11 +193,11 @@ DEF_HELPER_FLAGS_3(vslo, TCG_CALL_NO_RWG, void, avr, avr, 
avr)
 DEF_HELPER_FLAGS_3(vsro, TCG_CALL_NO_RWG, void, avr, avr, avr)
 DEF_HELPER_FLAGS_3(vsrv, TCG_CALL_NO_RWG, void, avr, avr, avr)
 DEF_HELPER_FLAGS_3(vslv, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vaddcuw, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VADDCUW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
 DEF_HELPER_FLAGS_2(vprtybw, TCG_CALL_NO_RWG, void, avr, avr)
 DEF_HELPER_FLAGS_2(vprtybd, TCG_CALL_NO_RWG, void, avr, avr)
 DEF_HELPER_FLAGS_2(vprtybq, TCG_CALL_NO_RWG, void, avr, avr)
-DEF_HELPER_FLAGS_3(vsubcuw, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VSUBCUW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
 DEF_HELPER_FLAGS_5(vaddsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
 DEF_HELPER_FLAGS_5(vaddshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
 DEF_HELPER_FLAGS_5(vaddsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9a509e84df..aebc7b73c8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -608,12 +608,14 @@ VRLQNM  000100 . . . 00101000101
@VX
 
 ## Vector Integer Arithmetic Instructions
 
+VADDCUW 000100 . . . 0011000@VX
 VADDCUQ 000100 . . . 0010100@VX
 VADDUQM 000100 . . . 001@VX
 
 VADDEUQM000100 . . . . 00   @VA
 VADDECUQ000100 . . . . 01   @VA
 
+VSUBCUW 000100 . . . 1011000@VX
 VSUBCUQ 000100 . . . 1010100@VX
 VSUBUQM 000100 . . . 101@VX
 
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ae1ba8084d..c48841819d 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -492,7 +492,7 @@ static inline void set_vscr_sat(CPUPPCState *env)
 env->vscr_sat.u32[0] = 1;
 }
 
-void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VADDCUW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t v)
 {
 int i;
 
@@ -1962,7 +1962,7 @@ void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 #endif
 }
 
-void helper_vsubcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VSUBCUW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t v)
 {
 int i;
 
diff --git a/target/ppc/translate/vmx-impl.c.inc 
b/target/ppc/translate/vmx-impl.c.inc
index 3acd585a2f..c5bfbfb3ce 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -803,8 +803,6 @@ GEN_VXFORM(vsrv, 2, 28);
 GEN_VXFORM(vslv, 2, 29);
 GEN_VXFORM(vslo, 6, 16);
 GEN_VXFORM(vsro, 6, 17);
-GEN_VXFORM(vaddcuw, 0, 6);
-GEN_VXFORM(vsubcuw, 0, 22);
 
 static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
void (*gen_gvec)(unsigned, uint32_t, uint32_t,
@@ -2847,8 +2845,6 @@ static void gen_xpnd04_2(DisasContext *ctx)
 }
 
 
-GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
-xpnd04_1, PPC_NONE, PPC2_ISA300)
 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
 xpnd04_2, PPC_NONE, PPC2_ISA300)
 
@@ -3110,6 +3106,52 @@ TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, 
gen_helper_VPMSUMD)