Re: [PATCH 03/17] target/ppc: Move 40x CPUs code to their own file

2022-03-02 Thread Fabiano Rosas 
BALATON Zoltan  writes:

> On Tue, 1 Mar 2022, Fabiano Rosas wrote:
>> Affects the 405 CPU.
>>
>> This moves init_proc, init_excp and register_*sprs functions that are
>> related to the 40x CPUs (currently only 405) into a separate file.
>>
>> Signed-off-by: Fabiano Rosas 
>> ---
>> target/ppc/cpu_40x.c   | 263 +
>> target/ppc/cpu_init.c  | 250 ---
>> target/ppc/meson.build |   1 +
>> 3 files changed, 264 insertions(+), 250 deletions(-)
>> create mode 100644 target/ppc/cpu_40x.c
>>
>> diff --git a/target/ppc/cpu_40x.c b/target/ppc/cpu_40x.c
>> new file mode 100644
>> index 00..4ed2cbc305
>> --- /dev/null
>> +++ b/target/ppc/cpu_40x.c
>> @@ -0,0 +1,263 @@
>> +/*
>> + * CPU initialization for PowerPC 40x CPUs
>> + *
>> + *  Copyright IBM Corp. 2022
>
> I think you can't replace the copyright when moving code. You have to 
> retain the original header and maybe you can add your own if you change or 
> rewrite it. You can only drop old copyright it you've completely replaced 
> the content.

Well spotted, thanks!

Re: [PATCH 03/17] target/ppc: Move 40x CPUs code to their own file

2022-03-01 Thread BALATON Zoltan 

On Tue, 1 Mar 2022, Fabiano Rosas wrote:

Affects the 405 CPU.

This moves init_proc, init_excp and register_*sprs functions that are
related to the 40x CPUs (currently only 405) into a separate file.

Signed-off-by: Fabiano Rosas 
---
target/ppc/cpu_40x.c   | 263 +
target/ppc/cpu_init.c  | 250 ---
target/ppc/meson.build |   1 +
3 files changed, 264 insertions(+), 250 deletions(-)
create mode 100644 target/ppc/cpu_40x.c

diff --git a/target/ppc/cpu_40x.c b/target/ppc/cpu_40x.c
new file mode 100644
index 00..4ed2cbc305
--- /dev/null
+++ b/target/ppc/cpu_40x.c
@@ -0,0 +1,263 @@
+/*
+ * CPU initialization for PowerPC 40x CPUs
+ *
+ *  Copyright IBM Corp. 2022


I think you can't replace the copyright when moving code. You have to 
retain the original header and maybe you can add your own if you change or 
rewrite it. You can only drop old copyright it you've completely replaced 
the content.


Regards,
BALATON Zoltan


+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ppc/ppc.h"
+#include "cpu.h"
+#include "spr_common.h"
+
+/* SPR shared between PowerPC 40x implementations */
+static void register_40x_sprs(CPUPPCState *env)
+{
+/* Cache */
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_40x_DCCR, "DCCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_40x_ICCR, "ICCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, SPR_NOACCESS,
+ 0x);
+/* Exception */
+spr_register(env, SPR_40x_DEAR, "DEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_ESR, "ESR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_EVPR, "EVPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_excp_prefix,
+ 0x);
+spr_register(env, SPR_40x_SRR2, "SRR2",
+ _read_generic, _write_generic,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_SRR3, "SRR3",
+ _read_generic, _write_generic,
+ _read_generic, _write_generic,
+ 0x);
+/* Timers */
+spr_register(env, SPR_40x_PIT, "PIT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_40x_pit, _write_40x_pit,
+ 0x);
+spr_register(env, SPR_40x_TCR, "TCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_tcr,
+ 0x);
+spr_register(env, SPR_40x_TSR, "TSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_tsr,
+ 0x);
+}
+
+/* SPR specific to PowerPC 405 implementation */
+static void register_405_sprs(CPUPPCState *env)
+{
+/* MMU */
+spr_register(env, SPR_40x_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_pid,
+ 0x);
+spr_register(env, SPR_4xx_CCR0, "CCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x0070);
+/* Debug interface */
+spr_register(env, SPR_40x_DBCR0, "DBCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_dbcr0,
+ 0x);
+
+spr_register(env, SPR_405_DBCR1, "DBCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_40x_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_clear,
+ /* Last reset was system reset */
+ 0x0300);
+
+spr_register(env, SPR_40x_DAC1, "DAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_DAC2, "DAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_405_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic,

[PATCH 03/17] target/ppc: Move 40x CPUs code to their own file

2022-03-01 Thread Fabiano Rosas 
Affects the 405 CPU.

This moves init_proc, init_excp and register_*sprs functions that are
related to the 40x CPUs (currently only 405) into a separate file.

Signed-off-by: Fabiano Rosas 
---
 target/ppc/cpu_40x.c   | 263 +
 target/ppc/cpu_init.c  | 250 ---
 target/ppc/meson.build |   1 +
 3 files changed, 264 insertions(+), 250 deletions(-)
 create mode 100644 target/ppc/cpu_40x.c

diff --git a/target/ppc/cpu_40x.c b/target/ppc/cpu_40x.c
new file mode 100644
index 00..4ed2cbc305
--- /dev/null
+++ b/target/ppc/cpu_40x.c
@@ -0,0 +1,263 @@
+/*
+ * CPU initialization for PowerPC 40x CPUs
+ *
+ *  Copyright IBM Corp. 2022
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ppc/ppc.h"
+#include "cpu.h"
+#include "spr_common.h"
+
+/* SPR shared between PowerPC 40x implementations */
+static void register_40x_sprs(CPUPPCState *env)
+{
+/* Cache */
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_40x_DCCR, "DCCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_40x_ICCR, "ICCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+/* not emulated, as QEMU do not emulate caches */
+spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, SPR_NOACCESS,
+ 0x);
+/* Exception */
+spr_register(env, SPR_40x_DEAR, "DEAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_ESR, "ESR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_EVPR, "EVPR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_excp_prefix,
+ 0x);
+spr_register(env, SPR_40x_SRR2, "SRR2",
+ _read_generic, _write_generic,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_SRR3, "SRR3",
+ _read_generic, _write_generic,
+ _read_generic, _write_generic,
+ 0x);
+/* Timers */
+spr_register(env, SPR_40x_PIT, "PIT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_40x_pit, _write_40x_pit,
+ 0x);
+spr_register(env, SPR_40x_TCR, "TCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_tcr,
+ 0x);
+spr_register(env, SPR_40x_TSR, "TSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_tsr,
+ 0x);
+}
+
+/* SPR specific to PowerPC 405 implementation */
+static void register_405_sprs(CPUPPCState *env)
+{
+/* MMU */
+spr_register(env, SPR_40x_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_pid,
+ 0x);
+spr_register(env, SPR_4xx_CCR0, "CCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x0070);
+/* Debug interface */
+spr_register(env, SPR_40x_DBCR0, "DBCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_40x_dbcr0,
+ 0x);
+
+spr_register(env, SPR_405_DBCR1, "DBCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_40x_DBSR, "DBSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_clear,
+ /* Last reset was system reset */
+ 0x0300);
+
+spr_register(env, SPR_40x_DAC1, "DAC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+spr_register(env, SPR_40x_DAC2, "DAC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_405_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_405_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ _read_generic, _write_generic,
+ 0x);
+
+spr_register(env, SPR_40x_IAC1, "IAC1",
+ SPR_NOACCESS,