Re: [PATCH 03/42] tcg: Split out tcg_out_ext8s

2023-04-21 Thread Philippe Mathieu-Daudé

On 8/4/23 04:42, Richard Henderson wrote:

We will need a backend interface for performing 8-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
  tcg/tcg.c| 21 -
  tcg/aarch64/tcg-target.c.inc | 11 +++
  tcg/arm/tcg-target.c.inc | 10 --
  tcg/i386/tcg-target.c.inc| 10 +-
  tcg/loongarch64/tcg-target.c.inc | 11 ---
  tcg/mips/tcg-target.c.inc| 12 
  tcg/ppc/tcg-target.c.inc | 10 --
  tcg/riscv/tcg-target.c.inc   |  9 +++--
  tcg/s390x/tcg-target.c.inc   | 10 +++---
  tcg/sparc64/tcg-target.c.inc |  7 +++
  tcg/tci/tcg-target.c.inc | 21 -
  11 files changed, 81 insertions(+), 51 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 




[PATCH 03/42] tcg: Split out tcg_out_ext8s

2023-04-07 Thread Richard Henderson
We will need a backend interface for performing 8-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
 tcg/tcg.c| 21 -
 tcg/aarch64/tcg-target.c.inc | 11 +++
 tcg/arm/tcg-target.c.inc | 10 --
 tcg/i386/tcg-target.c.inc| 10 +-
 tcg/loongarch64/tcg-target.c.inc | 11 ---
 tcg/mips/tcg-target.c.inc| 12 
 tcg/ppc/tcg-target.c.inc | 10 --
 tcg/riscv/tcg-target.c.inc   |  9 +++--
 tcg/s390x/tcg-target.c.inc   | 10 +++---
 tcg/sparc64/tcg-target.c.inc |  7 +++
 tcg/tci/tcg-target.c.inc | 21 -
 11 files changed, 81 insertions(+), 51 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index c3a8578951..76ba3e28cd 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -105,6 +105,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg 
ret, TCGReg arg1,
 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
 static void tcg_out_movi(TCGContext *s, TCGType type,
  TCGReg ret, tcg_target_long arg);
+static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
 static void tcg_out_goto_tb(TCGContext *s, int which);
@@ -4496,11 +4497,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
 }
 
 /* emit instruction */
-if (def->flags & TCG_OPF_VECTOR) {
-tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
-   new_args, const_args);
-} else {
-tcg_out_op(s, op->opc, new_args, const_args);
+switch (op->opc) {
+case INDEX_op_ext8s_i32:
+tcg_out_ext8s(s, TCG_TYPE_I32, new_args[0], new_args[1]);
+break;
+case INDEX_op_ext8s_i64:
+tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]);
+break;
+default:
+if (def->flags & TCG_OPF_VECTOR) {
+tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
+   new_args, const_args);
+} else {
+tcg_out_op(s, op->opc, new_args, const_args);
+}
+break;
 }
 
 /* move the outputs in the correct register if needed */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 1315cb92ab..4f4f814293 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1419,6 +1419,11 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType 
ext, MemOp s_bits,
 tcg_out_sbfm(s, ext, rd, rn, 0, bits);
 }
 
+static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn)
+{
+tcg_out_sxt(s, type, MO_8, rd, rn);
+}
+
 static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,
TCGReg rd, TCGReg rn)
 {
@@ -2230,10 +2235,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 }
 break;
 
-case INDEX_op_ext8s_i64:
-case INDEX_op_ext8s_i32:
-tcg_out_sxt(s, ext, MO_8, a0, a1);
-break;
 case INDEX_op_ext16s_i64:
 case INDEX_op_ext16s_i32:
 tcg_out_sxt(s, ext, MO_16, a0, a1);
@@ -2310,6 +2311,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 case INDEX_op_call: /* Always emitted via tcg_out_call.  */
 case INDEX_op_exit_tb:  /* Always emitted via tcg_out_exit_tb.  */
 case INDEX_op_goto_tb:  /* Always emitted via tcg_out_goto_tb.  */
+case INDEX_op_ext8s_i32:  /* Always emitted via tcg_reg_alloc_op.  */
+case INDEX_op_ext8s_i64:
 default:
 g_assert_not_reached();
 }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index b4daa97e7a..04a860897f 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -958,10 +958,10 @@ static void tcg_out_udiv(TCGContext *s, ARMCond cond,
 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
 }
 
-static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
+static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn)
 {
 /* sxtb */
-tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
+tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn);
 }
 
 static void __attribute__((unused))
@@ -1533,7 +1533,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, 
TCGLabelQemuLdst *lb)
 datahi = lb->datahi_reg;
 switch (opc & MO_SSIZE) {
 case MO_SB:
-tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0);
+tcg_out_ext8s(s, TCG_TYPE_I32, datalo, TCG_REG_R0);
 break;
 case MO_SW:
 tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0);
@@ -2244,9 +2244,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
 break;
 
-case INDEX_op_ext8s_i32:
-