From: "Lucas Mateus Castro (alqotel)"
Moved the instructions VNEGW and VNEGD to decodetree and used gvec to
decode it.
vnegw:
reptloopmaster patch
8 12500 0,01053200 0,00548400 (-47.9%)
25 40000,01030500 0,0039 (-62.2%)
100 10000,01096300 0,00395400 (-63.9%)
500 200 0,01472000 0,00712300 (-51.6%)
250040 0,03809000 0,02147700 (-43.6%)
800012 0,09957100 0,06202100 (-37.7%)
vnegd:
reptloopmaster patch
8 12500 0,00594600 0,00543800 (-8.5%)
25 40000,00575200 0,00396400 (-31.1%)
100 10000,00676100 0,00394800 (-41.6%)
500 200 0,01149300 0,00709400 (-38.3%)
250040 0,03441500 0,02169600 (-37.0%)
800012 0,09516900 0,06337000 (-33.4%)
Signed-off-by: Lucas Mateus Castro (alqotel)
---
target/ppc/helper.h | 2 --
target/ppc/insn32.decode| 3 +++
target/ppc/int_helper.c | 12
target/ppc/translate/vmx-impl.c.inc | 15 +--
target/ppc/translate/vmx-ops.c.inc | 2 --
5 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index edce059f2c..feccf30bcb 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -231,8 +231,6 @@ DEF_HELPER_FLAGS_2(VSTRIBL, TCG_CALL_NO_RWG, i32, avr, avr)
DEF_HELPER_FLAGS_2(VSTRIBR, TCG_CALL_NO_RWG, i32, avr, avr)
DEF_HELPER_FLAGS_2(VSTRIHL, TCG_CALL_NO_RWG, i32, avr, avr)
DEF_HELPER_FLAGS_2(VSTRIHR, TCG_CALL_NO_RWG, i32, avr, avr)
-DEF_HELPER_FLAGS_2(vnegw, TCG_CALL_NO_RWG, void, avr, avr)
-DEF_HELPER_FLAGS_2(vnegd, TCG_CALL_NO_RWG, void, avr, avr)
DEF_HELPER_FLAGS_2(vupkhpx, TCG_CALL_NO_RWG, void, avr, avr)
DEF_HELPER_FLAGS_2(vupklpx, TCG_CALL_NO_RWG, void, avr, avr)
DEF_HELPER_FLAGS_2(vupkhsb, TCG_CALL_NO_RWG, void, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index aebc7b73c8..2658dd3395 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -629,6 +629,9 @@ VEXTSH2D000100 . 11001 . 1100010
@VX_tb
VEXTSW2D000100 . 11010 . 1100010@VX_tb
VEXTSD2Q000100 . 11011 . 1100010@VX_tb
+VNEGD 000100 . 00111 . 1100010@VX_tb
+VNEGW 000100 . 00110 . 1100010@VX_tb
+
## Vector Mask Manipulation Instructions
MTVSRBM 000100 . 1 . 1100110@VX_tb
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index c48841819d..338ebced22 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1937,18 +1937,6 @@ XXBLEND(W, 32)
XXBLEND(D, 64)
#undef XXBLEND
-#define VNEG(name, element) \
-void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
-{ \
-int i; \
-for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
-r->element[i] = -b->element[i]; \
-} \
-}
-VNEG(vnegw, s32)
-VNEG(vnegd, s64)
-#undef VNEG
-
void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int sh = (b->VsrB(0xf) >> 3) & 0xf;
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index c5bfbfb3ce..3f614097ac 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2625,8 +2625,19 @@ GEN_VXFORM_NOA(vclzb, 1, 28)
GEN_VXFORM_NOA(vclzh, 1, 29)
GEN_VXFORM_TRANS(vclzw, 1, 30)
GEN_VXFORM_TRANS(vclzd, 1, 31)
-GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
-GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
+
+static bool do_vneg(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
+{
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_VECTOR(ctx);
+
+tcg_gen_gvec_neg(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
+ 16, 16);
+return true;
+}
+
+TRANS(VNEGW, do_vneg, MO_32)
+TRANS(VNEGD, do_vneg, MO_64)
static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
{
diff --git a/target/ppc/translate/vmx-ops.c.inc
b/target/ppc/translate/vmx-ops.c.inc
index ded0234123..27908533dd 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -181,8 +181,6 @@ GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x10),
GEN_VXFORM(vspltisb, 6, 12),
GEN_VXFORM(vspltish, 6, 13),
GEN_VXFORM(vspltisw, 6, 14),
-GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
-GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
--
2.31.1
