Re: [PATCH 05/42] tcg: Split out tcg_out_ext16s

2023-04-21 Thread Philippe Mathieu-Daudé

On 8/4/23 04:42, Richard Henderson wrote:

We will need a backend interface for performing 16-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
  tcg/tcg.c|  7 +++
  tcg/aarch64/tcg-target.c.inc | 13 -
  tcg/arm/tcg-target.c.inc | 10 --
  tcg/i386/tcg-target.c.inc| 16 
  tcg/loongarch64/tcg-target.c.inc | 13 +
  tcg/mips/tcg-target.c.inc| 11 ---
  tcg/ppc/tcg-target.c.inc | 12 +---
  tcg/riscv/tcg-target.c.inc   |  9 +++--
  tcg/s390x/tcg-target.c.inc   | 12 
  tcg/sparc64/tcg-target.c.inc |  7 +++
  tcg/tci/tcg-target.c.inc | 21 -
  11 files changed, 79 insertions(+), 52 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 




[PATCH 05/42] tcg: Split out tcg_out_ext16s

2023-04-07 Thread Richard Henderson
We will need a backend interface for performing 16-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
 tcg/tcg.c|  7 +++
 tcg/aarch64/tcg-target.c.inc | 13 -
 tcg/arm/tcg-target.c.inc | 10 --
 tcg/i386/tcg-target.c.inc| 16 
 tcg/loongarch64/tcg-target.c.inc | 13 +
 tcg/mips/tcg-target.c.inc| 11 ---
 tcg/ppc/tcg-target.c.inc | 12 +---
 tcg/riscv/tcg-target.c.inc   |  9 +++--
 tcg/s390x/tcg-target.c.inc   | 12 
 tcg/sparc64/tcg-target.c.inc |  7 +++
 tcg/tci/tcg-target.c.inc | 21 -
 11 files changed, 79 insertions(+), 52 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index b02ffc5679..739f92c2ee 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -106,6 +106,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg 
ret, TCGReg arg);
 static void tcg_out_movi(TCGContext *s, TCGType type,
  TCGReg ret, tcg_target_long arg);
 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
+static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg 
arg);
 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg);
 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
@@ -4509,6 +4510,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
 case INDEX_op_ext8u_i64:
 tcg_out_ext8u(s, new_args[0], new_args[1]);
 break;
+case INDEX_op_ext16s_i32:
+tcg_out_ext16s(s, TCG_TYPE_I32, new_args[0], new_args[1]);
+break;
+case INDEX_op_ext16s_i64:
+tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]);
+break;
 default:
 if (def->flags & TCG_OPF_VECTOR) {
 tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index cca91363ce..3527c14d04 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1424,6 +1424,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, 
TCGReg rd, TCGReg rn)
 tcg_out_sxt(s, type, MO_8, rd, rn);
 }
 
+static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn)
+{
+tcg_out_sxt(s, type, MO_16, rd, rn);
+}
+
 static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits,
TCGReg rd, TCGReg rn)
 {
@@ -2233,17 +2238,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1);
 if (a2 & TCG_BSWAP_OS) {
 /* Output must be sign-extended. */
-tcg_out_sxt(s, ext, MO_16, a0, a0);
+tcg_out_ext16s(s, ext, a0, a0);
 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
 /* Output must be zero-extended, but input isn't. */
 tcg_out_uxt(s, MO_16, a0, a0);
 }
 break;
 
-case INDEX_op_ext16s_i64:
-case INDEX_op_ext16s_i32:
-tcg_out_sxt(s, ext, MO_16, a0, a1);
-break;
 case INDEX_op_ext_i32_i64:
 case INDEX_op_ext32s_i64:
 tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);
@@ -2316,6 +2317,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 case INDEX_op_ext8s_i64:
 case INDEX_op_ext8u_i32:
 case INDEX_op_ext8u_i64:
+case INDEX_op_ext16s_i64:
+case INDEX_op_ext16s_i32:
 default:
 g_assert_not_reached();
 }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index b99f08a54b..cddf977a58 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -975,10 +975,10 @@ tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg 
rd, TCGReg rn)
 tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
 }
 
-static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
+static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn)
 {
 /* sxth */
-tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
+tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn);
 }
 
 static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
@@ -1541,7 +1541,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, 
TCGLabelQemuLdst *lb)
 tcg_out_ext8s(s, TCG_TYPE_I32, datalo, TCG_REG_R0);
 break;
 case MO_SW:
-tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0);
+tcg_out_ext16s(s, TCG_TYPE_I32, datalo, TCG_REG_R0);
 break;
 default:
 tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0);
@@ -2249,9 +2249,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
 break;
 
-case INDEX_op_ext16s_i32:
-tcg_out_ext16s(s, COND_AL, args[0], args[1]);
-break;
 case