Re: [PATCH 06/42] tcg: Split out tcg_out_ext16u

2023-04-21 Thread Philippe Mathieu-Daudé

On 8/4/23 04:42, Richard Henderson wrote:

We will need a backend interface for performing 16-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
  tcg/tcg.c|  5 +
  tcg/aarch64/tcg-target.c.inc | 13 -
  tcg/arm/tcg-target.c.inc | 17 ++---
  tcg/i386/tcg-target.c.inc|  8 +++-
  tcg/loongarch64/tcg-target.c.inc |  7 ++-
  tcg/mips/tcg-target.c.inc|  5 +
  tcg/ppc/tcg-target.c.inc |  4 +++-
  tcg/riscv/tcg-target.c.inc   |  7 ++-
  tcg/s390x/tcg-target.c.inc   | 17 ++---
  tcg/sparc64/tcg-target.c.inc | 11 +--
  tcg/tci/tcg-target.c.inc | 14 +-
  11 files changed, 66 insertions(+), 42 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 




[PATCH 06/42] tcg: Split out tcg_out_ext16u

2023-04-07 Thread Richard Henderson
We will need a backend interface for performing 16-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.

Signed-off-by: Richard Henderson 
---
 tcg/tcg.c|  5 +
 tcg/aarch64/tcg-target.c.inc | 13 -
 tcg/arm/tcg-target.c.inc | 17 ++---
 tcg/i386/tcg-target.c.inc|  8 +++-
 tcg/loongarch64/tcg-target.c.inc |  7 ++-
 tcg/mips/tcg-target.c.inc|  5 +
 tcg/ppc/tcg-target.c.inc |  4 +++-
 tcg/riscv/tcg-target.c.inc   |  7 ++-
 tcg/s390x/tcg-target.c.inc   | 17 ++---
 tcg/sparc64/tcg-target.c.inc | 11 +--
 tcg/tci/tcg-target.c.inc | 14 +-
 11 files changed, 66 insertions(+), 42 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index 739f92c2ee..5b0db747e8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -108,6 +108,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg 
arg);
 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg);
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg);
 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long);
 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
 static void tcg_out_goto_tb(TCGContext *s, int which);
@@ -4516,6 +4517,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
 case INDEX_op_ext16s_i64:
 tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]);
 break;
+case INDEX_op_ext16u_i32:
+case INDEX_op_ext16u_i64:
+tcg_out_ext16u(s, new_args[0], new_args[1]);
+break;
 default:
 if (def->flags & TCG_OPF_VECTOR) {
 tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3527c14d04..f55829e9ce 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1442,6 +1442,11 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, 
TCGReg rn)
 tcg_out_uxt(s, MO_8, rd, rn);
 }
 
+static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+tcg_out_uxt(s, MO_16, rd, rn);
+}
+
 static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
 TCGReg rn, int64_t aimm)
 {
@@ -2241,7 +2246,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 tcg_out_ext16s(s, ext, a0, a0);
 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
 /* Output must be zero-extended, but input isn't. */
-tcg_out_uxt(s, MO_16, a0, a0);
+tcg_out_ext16u(s, a0, a0);
 }
 break;
 
@@ -2249,10 +2254,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 case INDEX_op_ext32s_i64:
 tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1);
 break;
-case INDEX_op_ext16u_i64:
-case INDEX_op_ext16u_i32:
-tcg_out_uxt(s, MO_16, a0, a1);
-break;
 case INDEX_op_extu_i32_i64:
 case INDEX_op_ext32u_i64:
 tcg_out_movr(s, TCG_TYPE_I32, a0, a1);
@@ -2319,6 +2320,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 case INDEX_op_ext8u_i64:
 case INDEX_op_ext16s_i64:
 case INDEX_op_ext16s_i32:
+case INDEX_op_ext16u_i64:
+case INDEX_op_ext16u_i32:
 default:
 g_assert_not_reached();
 }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index cddf977a58..8fa0c6cbc0 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -981,12 +981,18 @@ static void tcg_out_ext16s(TCGContext *s, TCGType t, 
TCGReg rd, TCGReg rn)
 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn);
 }
 
-static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
+static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond,
+TCGReg rd, TCGReg rn)
 {
 /* uxth */
 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
 }
 
+static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn)
+{
+tcg_out_ext16u_cond(s, COND_AL, rd, rn);
+}
+
 static void tcg_out_bswap16(TCGContext *s, ARMCond cond,
 TCGReg rd, TCGReg rn, int flags)
 {
@@ -1372,8 +1378,8 @@ DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, 
tcg_out_movi32,
 (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond,
 (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
-DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u,
-(tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
+DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond,
+(tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP))
 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, )