Re: [PATCH 07/14] aspeed: Add PECI controller
> On Jun 27, 2022, at 11:47 PM, Cédric Le Goater wrote:
>
> On 6/27/22 21:54, Peter Delevoryas wrote:
>
> Could we have some short intro ? :)
Yes, definitely, I’ll resubmit with some more details.
>
>> Signed-off-by: Peter Delevoryas
>> ---
>> hw/arm/aspeed_ast10x0.c | 11 ++
>> hw/misc/aspeed_peci.c | 225 ++
>> hw/misc/meson.build | 3 +-
>> include/hw/arm/aspeed_soc.h | 3 +
>> include/hw/misc/aspeed_peci.h | 34 +
>> 5 files changed, 275 insertions(+), 1 deletion(-)
>> create mode 100644 hw/misc/aspeed_peci.c
>> create mode 100644 include/hw/misc/aspeed_peci.h
>> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
>> index 5df480a21f..780841ea84 100644
>> --- a/hw/arm/aspeed_ast10x0.c
>> +++ b/hw/arm/aspeed_ast10x0.c
>> @@ -47,6 +47,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
>> [ASPEED_DEV_UART13]= 0x7E790700,
>> [ASPEED_DEV_WDT] = 0x7E785000,
>> [ASPEED_DEV_LPC] = 0x7E789000,
>> +[ASPEED_DEV_PECI] = 0x7E78B000,
>> [ASPEED_DEV_I2C] = 0x7E7B,
>> };
>> @@ -75,6 +76,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {
>> [ASPEED_DEV_TIMER8]= 23,
>> [ASPEED_DEV_WDT] = 24,
>> [ASPEED_DEV_LPC] = 35,
>> +[ASPEED_DEV_PECI] = 38,
>> [ASPEED_DEV_FMC] = 39,
>> [ASPEED_DEV_PWM] = 44,
>> [ASPEED_DEV_ADC] = 46,
>> @@ -133,6 +135,8 @@ static void aspeed_soc_ast1030_init(Object *obj)
>>object_initialize_child(obj, "lpc", >lpc, TYPE_ASPEED_LPC);
>> +object_initialize_child(obj, "peci", >peci, TYPE_ASPEED_PECI);
>> +
>> object_initialize_child(obj, "sbc", >sbc, TYPE_ASPEED_SBC);
>>for (i = 0; i < sc->wdts_num; i++) {
>> @@ -238,6 +242,13 @@ static void aspeed_soc_ast1030_realize(DeviceState
>> *dev_soc, Error **errp)
>> /* UART */
>> aspeed_soc_uart_init(s);
>> +/* PECI */
>> +if (!sysbus_realize(SYS_BUS_DEVICE(>peci), errp)) {
>> +return;
>> +}
>> +sysbus_mmio_map(SYS_BUS_DEVICE(>peci), 0,
>> sc->memmap[ASPEED_DEV_PECI]);
>> +sysbus_connect_irq(SYS_BUS_DEVICE(>peci), 0, aspeed_soc_get_irq(s,
>> ASPEED_DEV_PECI));
>> +
>> /* Timer */
>> object_property_set_link(OBJECT(>timerctrl), "scu", OBJECT(>scu),
>> _abort);
>> diff --git a/hw/misc/aspeed_peci.c b/hw/misc/aspeed_peci.c
>> new file mode 100644
>> index 00..670e532fc0
>> --- /dev/null
>> +++ b/hw/misc/aspeed_peci.c
>> @@ -0,0 +1,225 @@
>> +/*
>> + * Aspeed PECI Controller
>> + *
>> + * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)
>> + *
>> + * This code is licensed under the GPL version 2 or later. See the COPYING
>> + * file in the top-level directory.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/log.h"
>> +#include "hw/irq.h"
>> +#include "hw/misc/aspeed_peci.h"
>> +
>> +#define U(x) (x##U)
>> +#define GENMASK(h, l) \
>> +(((~U(0)) - (U(1) << (l)) + 1) & \
>> + (~U(0) >> (32 - 1 - (h
>
> I beleive QEMU has similar macros to generate masks.
Ah yes good catch, I can probably fix that pretty easily.
>
>
>> +/* ASPEED PECI Registers */
>> +/* Control Register */
>> +#define ASPEED_PECI_CTRL (0x00 / 4)
>> +#define ASPEED_PECI_CTRL_SAMPLING_MASKGENMASK(19, 16)
>> +#define ASPEED_PECI_CTRL_RD_MODE_MASK GENMASK(13, 12)
>> +#define ASPEED_PECI_CTRL_RD_MODE_DBG BIT(13)
>> +#define ASPEED_PECI_CTRL_RD_MODE_COUNT BIT(12)
>> +#define ASPEED_PECI_CTRL_CLK_SRC_HCLK BIT(11)
>> +#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8)
>> +#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7)
>> +#define ASPEED_PECI_CTRL_INVERT_IN BIT(6)
>> +#define ASPEED_PECI_CTRL_BUS_CONTENTION_EN BIT(5)
>> +#define ASPEED_PECI_CTRL_PECI_EN BIT(4)
>> +#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0)
>> +
>> +/* Timing Negotiation Register */
>> +#define ASPEED_PECI_TIMING_NEGOTIATION (0x04 / 4)
>> +#define ASPEED_PECI_T_NEGO_MSG_MASK GENMASK(15, 8)
>> +#define ASPEED_PECI_T_NEGO_ADDR_MASK GENMASK(7, 0)
>> +
>> +/* Command Register */
>> +#define ASPEED_PECI_CMD (0x08 / 4)
>> +#define ASPEED_PECI_CMD_PIN_MONITORING BIT(31)
>> +#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24)
>> +#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3
>> +#define ASPEED_PECI_CMD_IDLE_MASK \
>> + (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MONITORING)
>> +#define ASPEED_PECI_CMD_FIRE BIT(0)
>> +
>> +/* Read/Write Length Register */
>> +#define ASPEED_PECI_RW_LENGTH (0x0c / 4)
>> +#define ASPEED_PECI_AW_FCS_EN BIT(31)
>> +#define ASPEED_PECI_RD_LEN_MASK GENMASK(23, 16)
>> +#define ASPEED_PECI_WR_LEN_MASK GENMASK(15, 8)
>> +#define ASPEED_PECI_TARGET_ADDR_MASK GENMASK(7, 0)
>> +
>> +/* Expected FCS Data Register */
>> +#define ASPEED_PECI_EXPECTED_FCS (0x10 / 4)
>> +#define ASPEED_PECI_EXPECTED_RD_FCS_MASK GENMASK(23, 16)
>> +#define
Re: [PATCH 07/14] aspeed: Add PECI controller
On 6/27/22 21:54, Peter Delevoryas wrote:
Could we have some short intro ? :)
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed_ast10x0.c | 11 ++
hw/misc/aspeed_peci.c | 225 ++
hw/misc/meson.build | 3 +-
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_peci.h | 34 +
5 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/misc/aspeed_peci.c
create mode 100644 include/hw/misc/aspeed_peci.h
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 5df480a21f..780841ea84 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -47,6 +47,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_UART13]= 0x7E790700,
[ASPEED_DEV_WDT] = 0x7E785000,
[ASPEED_DEV_LPC] = 0x7E789000,
+[ASPEED_DEV_PECI] = 0x7E78B000,
[ASPEED_DEV_I2C] = 0x7E7B,
};
@@ -75,6 +76,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {
[ASPEED_DEV_TIMER8]= 23,
[ASPEED_DEV_WDT] = 24,
[ASPEED_DEV_LPC] = 35,
+[ASPEED_DEV_PECI] = 38,
[ASPEED_DEV_FMC] = 39,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_ADC] = 46,
@@ -133,6 +135,8 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_initialize_child(obj, "lpc", >lpc, TYPE_ASPEED_LPC);
+object_initialize_child(obj, "peci", >peci, TYPE_ASPEED_PECI);
+
object_initialize_child(obj, "sbc", >sbc, TYPE_ASPEED_SBC);
for (i = 0; i < sc->wdts_num; i++) {
@@ -238,6 +242,13 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
/* UART */
aspeed_soc_uart_init(s);
+/* PECI */
+if (!sysbus_realize(SYS_BUS_DEVICE(>peci), errp)) {
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(>peci), 0, sc->memmap[ASPEED_DEV_PECI]);
+sysbus_connect_irq(SYS_BUS_DEVICE(>peci), 0, aspeed_soc_get_irq(s,
ASPEED_DEV_PECI));
+
/* Timer */
object_property_set_link(OBJECT(>timerctrl), "scu", OBJECT(>scu),
_abort);
diff --git a/hw/misc/aspeed_peci.c b/hw/misc/aspeed_peci.c
new file mode 100644
index 00..670e532fc0
--- /dev/null
+++ b/hw/misc/aspeed_peci.c
@@ -0,0 +1,225 @@
+/*
+ * Aspeed PECI Controller
+ *
+ * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)
+ *
+ * This code is licensed under the GPL version 2 or later. See the COPYING
+ * file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/misc/aspeed_peci.h"
+
+#define U(x) (x##U)
+#define GENMASK(h, l) \
+ (((~U(0)) - (U(1) << (l)) + 1) & \
+(~U(0) >> (32 - 1 - (h
I beleive QEMU has similar macros to generate masks.
+/* ASPEED PECI Registers */
+/* Control Register */
+#define ASPEED_PECI_CTRL (0x00 / 4)
+#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16)
+#define ASPEED_PECI_CTRL_RD_MODE_MASKGENMASK(13, 12)
+#define ASPEED_PECI_CTRL_RD_MODE_DBG BIT(13)
+#define ASPEED_PECI_CTRL_RD_MODE_COUNT BIT(12)
+#define ASPEED_PECI_CTRL_CLK_SRC_HCLK BIT(11)
+#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8)
+#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7)
+#define ASPEED_PECI_CTRL_INVERT_IN BIT(6)
+#define ASPEED_PECI_CTRL_BUS_CONTENTION_EN BIT(5)
+#define ASPEED_PECI_CTRL_PECI_EN BIT(4)
+#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0)
+
+/* Timing Negotiation Register */
+#define ASPEED_PECI_TIMING_NEGOTIATION (0x04 / 4)
+#define ASPEED_PECI_T_NEGO_MSG_MASK GENMASK(15, 8)
+#define ASPEED_PECI_T_NEGO_ADDR_MASK GENMASK(7, 0)
+
+/* Command Register */
+#define ASPEED_PECI_CMD (0x08 / 4)
+#define ASPEED_PECI_CMD_PIN_MONITORING BIT(31)
+#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24)
+#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3
+#define ASPEED_PECI_CMD_IDLE_MASK \
+ (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MONITORING)
+#define ASPEED_PECI_CMD_FIRE BIT(0)
+
+/* Read/Write Length Register */
+#define ASPEED_PECI_RW_LENGTH (0x0c / 4)
+#define ASPEED_PECI_AW_FCS_EN BIT(31)
+#define ASPEED_PECI_RD_LEN_MASK GENMASK(23, 16)
+#define ASPEED_PECI_WR_LEN_MASK GENMASK(15, 8)
+#define ASPEED_PECI_TARGET_ADDR_MASK GENMASK(7, 0)
+
+/* Expected FCS Data Register */
+#define ASPEED_PECI_EXPECTED_FCS (0x10 / 4)
+#define ASPEED_PECI_EXPECTED_RD_FCS_MASK GENMASK(23, 16)
+#define ASPEED_PECI_EXPECTED_AW_FCS_AUTO_MASK GENMASK(15, 8)
+#define ASPEED_PECI_EXPECTED_WR_FCS_MASK GENMASK(7, 0)
+
+/* Captured FCS Data Register */
+#define ASPEED_PECI_CAPTURED_FCS (0x14 / 4)
+#define ASPEED_PECI_CAPTURED_RD_FCS_MASK GENMASK(23, 16)
+#define ASPEED_PECI_CAPTURED_WR_FCS_MASK GENMASK(7, 0)
+
+/* Interrupt Register */
+#define ASPEED_PECI_INT_CTRL (0x18 / 4)
+#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30)
+#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0
+#define
[PATCH 07/14] aspeed: Add PECI controller
Signed-off-by: Peter Delevoryas
---
hw/arm/aspeed_ast10x0.c | 11 ++
hw/misc/aspeed_peci.c | 225 ++
hw/misc/meson.build | 3 +-
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_peci.h | 34 +
5 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/misc/aspeed_peci.c
create mode 100644 include/hw/misc/aspeed_peci.h
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 5df480a21f..780841ea84 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -47,6 +47,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_UART13]= 0x7E790700,
[ASPEED_DEV_WDT] = 0x7E785000,
[ASPEED_DEV_LPC] = 0x7E789000,
+[ASPEED_DEV_PECI] = 0x7E78B000,
[ASPEED_DEV_I2C] = 0x7E7B,
};
@@ -75,6 +76,7 @@ static const int aspeed_soc_ast1030_irqmap[] = {
[ASPEED_DEV_TIMER8]= 23,
[ASPEED_DEV_WDT] = 24,
[ASPEED_DEV_LPC] = 35,
+[ASPEED_DEV_PECI] = 38,
[ASPEED_DEV_FMC] = 39,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_ADC] = 46,
@@ -133,6 +135,8 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_initialize_child(obj, "lpc", >lpc, TYPE_ASPEED_LPC);
+object_initialize_child(obj, "peci", >peci, TYPE_ASPEED_PECI);
+
object_initialize_child(obj, "sbc", >sbc, TYPE_ASPEED_SBC);
for (i = 0; i < sc->wdts_num; i++) {
@@ -238,6 +242,13 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
/* UART */
aspeed_soc_uart_init(s);
+/* PECI */
+if (!sysbus_realize(SYS_BUS_DEVICE(>peci), errp)) {
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(>peci), 0, sc->memmap[ASPEED_DEV_PECI]);
+sysbus_connect_irq(SYS_BUS_DEVICE(>peci), 0, aspeed_soc_get_irq(s,
ASPEED_DEV_PECI));
+
/* Timer */
object_property_set_link(OBJECT(>timerctrl), "scu", OBJECT(>scu),
_abort);
diff --git a/hw/misc/aspeed_peci.c b/hw/misc/aspeed_peci.c
new file mode 100644
index 00..670e532fc0
--- /dev/null
+++ b/hw/misc/aspeed_peci.c
@@ -0,0 +1,225 @@
+/*
+ * Aspeed PECI Controller
+ *
+ * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)
+ *
+ * This code is licensed under the GPL version 2 or later. See the COPYING
+ * file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/misc/aspeed_peci.h"
+
+#define U(x) (x##U)
+#define GENMASK(h, l) \
+ (((~U(0)) - (U(1) << (l)) + 1) & \
+(~U(0) >> (32 - 1 - (h
+
+/* ASPEED PECI Registers */
+/* Control Register */
+#define ASPEED_PECI_CTRL (0x00 / 4)
+#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16)
+#define ASPEED_PECI_CTRL_RD_MODE_MASKGENMASK(13, 12)
+#define ASPEED_PECI_CTRL_RD_MODE_DBG BIT(13)
+#define ASPEED_PECI_CTRL_RD_MODE_COUNT BIT(12)
+#define ASPEED_PECI_CTRL_CLK_SRC_HCLK BIT(11)
+#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8)
+#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7)
+#define ASPEED_PECI_CTRL_INVERT_IN BIT(6)
+#define ASPEED_PECI_CTRL_BUS_CONTENTION_EN BIT(5)
+#define ASPEED_PECI_CTRL_PECI_EN BIT(4)
+#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0)
+
+/* Timing Negotiation Register */
+#define ASPEED_PECI_TIMING_NEGOTIATION (0x04 / 4)
+#define ASPEED_PECI_T_NEGO_MSG_MASK GENMASK(15, 8)
+#define ASPEED_PECI_T_NEGO_ADDR_MASK GENMASK(7, 0)
+
+/* Command Register */
+#define ASPEED_PECI_CMD (0x08 / 4)
+#define ASPEED_PECI_CMD_PIN_MONITORING BIT(31)
+#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24)
+#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3
+#define ASPEED_PECI_CMD_IDLE_MASK \
+ (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MONITORING)
+#define ASPEED_PECI_CMD_FIRE BIT(0)
+
+/* Read/Write Length Register */
+#define ASPEED_PECI_RW_LENGTH (0x0c / 4)
+#define ASPEED_PECI_AW_FCS_EN BIT(31)
+#define ASPEED_PECI_RD_LEN_MASK GENMASK(23, 16)
+#define ASPEED_PECI_WR_LEN_MASK GENMASK(15, 8)
+#define ASPEED_PECI_TARGET_ADDR_MASK GENMASK(7, 0)
+
+/* Expected FCS Data Register */
+#define ASPEED_PECI_EXPECTED_FCS (0x10 / 4)
+#define ASPEED_PECI_EXPECTED_RD_FCS_MASK GENMASK(23, 16)
+#define ASPEED_PECI_EXPECTED_AW_FCS_AUTO_MASK GENMASK(15, 8)
+#define ASPEED_PECI_EXPECTED_WR_FCS_MASK GENMASK(7, 0)
+
+/* Captured FCS Data Register */
+#define ASPEED_PECI_CAPTURED_FCS (0x14 / 4)
+#define ASPEED_PECI_CAPTURED_RD_FCS_MASK GENMASK(23, 16)
+#define ASPEED_PECI_CAPTURED_WR_FCS_MASK GENMASK(7, 0)
+
+/* Interrupt Register */
+#define ASPEED_PECI_INT_CTRL (0x18 / 4)
+#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30)
+#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0
+#define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO 1
+#define ASPEED_PECI_MESSAGE_NEGO 2
+#define ASPEED_PECI_INT_MASK GENMASK(4, 0)
+#define ASPEED_PECI_INT_BUS_TIMEOUT BIT(4)
+#define
