Re: [PATCH 1/1] linux-headers: update to v6.5-rc1
For the vfio-ap bus driver IRQ index mapping:
Reviewed-by: Tony Krowiak
On 7/9/23 5:23 PM, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
include/standard-headers/drm/drm_fourcc.h | 43 ++
include/standard-headers/linux/const.h| 2 +-
include/standard-headers/linux/pci_regs.h | 1 +
include/standard-headers/linux/vhost_types.h | 16 +++
include/standard-headers/linux/virtio_blk.h | 18 +--
.../standard-headers/linux/virtio_config.h| 6 +
include/standard-headers/linux/virtio_net.h | 1 +
linux-headers/asm-arm64/bitsperlong.h | 23 ---
linux-headers/asm-arm64/kvm.h | 33 +
linux-headers/asm-generic/bitsperlong.h | 13 +-
linux-headers/asm-generic/unistd.h| 134 +-
linux-headers/asm-mips/unistd_n32.h | 1 +
linux-headers/asm-mips/unistd_n64.h | 1 +
linux-headers/asm-mips/unistd_o32.h | 1 +
linux-headers/asm-powerpc/unistd_32.h | 1 +
linux-headers/asm-powerpc/unistd_64.h | 1 +
linux-headers/asm-riscv/bitsperlong.h | 13 --
linux-headers/asm-riscv/kvm.h | 134 +-
linux-headers/asm-riscv/unistd.h | 9 ++
linux-headers/asm-s390/unistd_32.h| 2 +
linux-headers/asm-s390/unistd_64.h| 2 +
linux-headers/asm-x86/kvm.h | 3 +
linux-headers/asm-x86/unistd_32.h | 1 +
linux-headers/asm-x86/unistd_64.h | 1 +
linux-headers/asm-x86/unistd_x32.h| 1 +
linux-headers/linux/const.h | 2 +-
linux-headers/linux/kvm.h | 18 ++-
linux-headers/linux/mman.h| 14 ++
linux-headers/linux/psp-sev.h | 7 +
linux-headers/linux/userfaultfd.h | 17 ++-
linux-headers/linux/vfio.h| 27
linux-headers/linux/vhost.h | 31
32 files changed, 423 insertions(+), 154 deletions(-)
diff --git a/include/standard-headers/drm/drm_fourcc.h
b/include/standard-headers/drm/drm_fourcc.h
index dc3e6112c11c..72279f4d25d4 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -656,6 +656,49 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
+
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for display ver. 14
render
+ * compression.
+ *
+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
diff --git a/include/standard-headers/linux/const.h
b/include/standard-headers/linux/const.h
index 5e4898725168..1eb84b5087f8 100644
--- a/include/standard-headers/linux/const.h
+++ b/include/standard-headers/linux/const.h
@@ -28,7 +28,7
Re: [PATCH 1/1] linux-headers: update to v6.5-rc1
On Sun, Jul 09 2023, Cédric Le Goater wrote: > Signed-off-by: Cédric Le Goater > --- > include/standard-headers/drm/drm_fourcc.h | 43 ++ > include/standard-headers/linux/const.h| 2 +- > include/standard-headers/linux/pci_regs.h | 1 + > include/standard-headers/linux/vhost_types.h | 16 +++ > include/standard-headers/linux/virtio_blk.h | 18 +-- > .../standard-headers/linux/virtio_config.h| 6 + > include/standard-headers/linux/virtio_net.h | 1 + > linux-headers/asm-arm64/bitsperlong.h | 23 --- > linux-headers/asm-arm64/kvm.h | 33 + > linux-headers/asm-generic/bitsperlong.h | 13 +- > linux-headers/asm-generic/unistd.h| 134 +- > linux-headers/asm-mips/unistd_n32.h | 1 + > linux-headers/asm-mips/unistd_n64.h | 1 + > linux-headers/asm-mips/unistd_o32.h | 1 + > linux-headers/asm-powerpc/unistd_32.h | 1 + > linux-headers/asm-powerpc/unistd_64.h | 1 + > linux-headers/asm-riscv/bitsperlong.h | 13 -- > linux-headers/asm-riscv/kvm.h | 134 +- > linux-headers/asm-riscv/unistd.h | 9 ++ > linux-headers/asm-s390/unistd_32.h| 2 + > linux-headers/asm-s390/unistd_64.h| 2 + > linux-headers/asm-x86/kvm.h | 3 + > linux-headers/asm-x86/unistd_32.h | 1 + > linux-headers/asm-x86/unistd_64.h | 1 + > linux-headers/asm-x86/unistd_x32.h| 1 + > linux-headers/linux/const.h | 2 +- > linux-headers/linux/kvm.h | 18 ++- > linux-headers/linux/mman.h| 14 ++ > linux-headers/linux/psp-sev.h | 7 + > linux-headers/linux/userfaultfd.h | 17 ++- > linux-headers/linux/vfio.h| 27 > linux-headers/linux/vhost.h | 31 > 32 files changed, 423 insertions(+), 154 deletions(-) Acked-by: Cornelia Huck
Re: [PATCH 1/1] linux-headers: update to v6.5-rc1
On 09/07/2023 23.23, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater --- Looks fine to me (I quickly double-checked that this is the correct update to v6.5-rc1). Reviewed-by: Thomas Huth
[PATCH 1/1] linux-headers: update to v6.5-rc1
Signed-off-by: Cédric Le Goater
---
include/standard-headers/drm/drm_fourcc.h | 43 ++
include/standard-headers/linux/const.h| 2 +-
include/standard-headers/linux/pci_regs.h | 1 +
include/standard-headers/linux/vhost_types.h | 16 +++
include/standard-headers/linux/virtio_blk.h | 18 +--
.../standard-headers/linux/virtio_config.h| 6 +
include/standard-headers/linux/virtio_net.h | 1 +
linux-headers/asm-arm64/bitsperlong.h | 23 ---
linux-headers/asm-arm64/kvm.h | 33 +
linux-headers/asm-generic/bitsperlong.h | 13 +-
linux-headers/asm-generic/unistd.h| 134 +-
linux-headers/asm-mips/unistd_n32.h | 1 +
linux-headers/asm-mips/unistd_n64.h | 1 +
linux-headers/asm-mips/unistd_o32.h | 1 +
linux-headers/asm-powerpc/unistd_32.h | 1 +
linux-headers/asm-powerpc/unistd_64.h | 1 +
linux-headers/asm-riscv/bitsperlong.h | 13 --
linux-headers/asm-riscv/kvm.h | 134 +-
linux-headers/asm-riscv/unistd.h | 9 ++
linux-headers/asm-s390/unistd_32.h| 2 +
linux-headers/asm-s390/unistd_64.h| 2 +
linux-headers/asm-x86/kvm.h | 3 +
linux-headers/asm-x86/unistd_32.h | 1 +
linux-headers/asm-x86/unistd_64.h | 1 +
linux-headers/asm-x86/unistd_x32.h| 1 +
linux-headers/linux/const.h | 2 +-
linux-headers/linux/kvm.h | 18 ++-
linux-headers/linux/mman.h| 14 ++
linux-headers/linux/psp-sev.h | 7 +
linux-headers/linux/userfaultfd.h | 17 ++-
linux-headers/linux/vfio.h| 27
linux-headers/linux/vhost.h | 31
32 files changed, 423 insertions(+), 154 deletions(-)
diff --git a/include/standard-headers/drm/drm_fourcc.h
b/include/standard-headers/drm/drm_fourcc.h
index dc3e6112c11c..72279f4d25d4 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -656,6 +656,49 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
+
+/*
+ * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
+ *
+ * The main surface is tile4 and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
+ * planes 2 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
+
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for display ver. 14
render
+ * compression.
+ *
+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
diff --git a/include/standard-headers/linux/const.h
b/include/standard-headers/linux/const.h
index 5e4898725168..1eb84b5087f8 100644
--- a/include/standard-headers/linux/const.h
+++ b/include/standard-headers/linux/const.h
@@ -28,7 +28,7 @@
#define _BITUL(x) (_UL(1) << (x))
#define _BITULL(x) (_ULL(1) << (x))
-#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x,
