Re: [PATCH 2/6] hw/misc: Allwinner A10 DRAM Controller Emulation

2022-12-07 Thread Niek Linnenbank 
Hi Strahinja,

On Sun, Dec 4, 2022 at 12:19 AM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:

> During SPL boot several DRAM Controller registers are used. Most
> important registers are those related to DRAM initialization and
> calibration, where SPL initiates process and waits until certain bit is
> set/cleared.
>
> This patch adds these registers, initializes reset values from user's
> guide and updates state of registers as SPL expects it.
>
> Signed-off-by: Strahinja Jankovic 
> ---
>  hw/arm/Kconfig|   1 +
>  hw/arm/allwinner-a10.c|   7 +
>  hw/misc/Kconfig   |   3 +
>  hw/misc/allwinner-a10-dramc.c | 179 ++
>  hw/misc/meson.build   |   1 +
>  include/hw/arm/allwinner-a10.h|   2 +
>  include/hw/misc/allwinner-a10-dramc.h |  68 ++
>  7 files changed, 261 insertions(+)
>  create mode 100644 hw/misc/allwinner-a10-dramc.c
>  create mode 100644 include/hw/misc/allwinner-a10-dramc.h
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 14f52b41af..140f142ae5 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -320,6 +320,7 @@ config ALLWINNER_A10
>  select ALLWINNER_A10_PIT
>  select ALLWINNER_A10_PIC
>  select ALLWINNER_A10_CCM
> +select ALLWINNER_A10_DRAMC
>  select ALLWINNER_EMAC
>  select SERIAL
>  select UNIMP
> diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
> index 86baeeeca2..a5f7a36ac9 100644
> --- a/hw/arm/allwinner-a10.c
> +++ b/hw/arm/allwinner-a10.c
> @@ -25,6 +25,7 @@
>  #include "hw/boards.h"
>  #include "hw/usb/hcd-ohci.h"
>
> +#define AW_A10_DRAMC_BASE   0x01c01000
>  #define AW_A10_MMC0_BASE0x01c0f000
>  #define AW_A10_CCM_BASE 0x01c2
>  #define AW_A10_PIC_REG_BASE 0x01c20400
> @@ -49,6 +50,8 @@ static void aw_a10_init(Object *obj)
>
>  object_initialize_child(obj, "ccm", >ccm, TYPE_AW_A10_CCM);
>
> +object_initialize_child(obj, "dramc", >dramc, TYPE_AW_A10_DRAMC);
> +
>  object_initialize_child(obj, "emac", >emac, TYPE_AW_EMAC);
>
>  object_initialize_child(obj, "sata", >sata, TYPE_ALLWINNER_AHCI);
> @@ -110,6 +113,10 @@ static void aw_a10_realize(DeviceState *dev, Error
> **errp)
>  sysbus_realize(SYS_BUS_DEVICE(>ccm), _fatal);
>  sysbus_mmio_map(SYS_BUS_DEVICE(>ccm), 0, AW_A10_CCM_BASE);
>
> +/* DRAM Control Module */
> +sysbus_realize(SYS_BUS_DEVICE(>dramc), _fatal);
> +sysbus_mmio_map(SYS_BUS_DEVICE(>dramc), 0, AW_A10_DRAMC_BASE);
> +
>  /* FIXME use qdev NIC properties instead of nd_table[] */
>  if (nd_table[0].used) {
>  qemu_check_nic_model(_table[0], TYPE_AW_EMAC);
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index ed07bf4133..052fb54310 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -177,4 +177,7 @@ config LASI
>  config ALLWINNER_A10_CCM
>  bool
>
> +config ALLWINNER_A10_DRAMC
> +bool
> +
>  source macio/Kconfig
> diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
> new file mode 100644
> index 00..e118b0c2fd
> --- /dev/null
> +++ b/hw/misc/allwinner-a10-dramc.c
> @@ -0,0 +1,179 @@
> +/*
> + * Allwinner A10 DRAM Controller emulation
> + *
> + * Copyright (C) 2022 Strahinja Jankovic 
> + *
> + *  This file is derived from Allwinner H3 DRAMC,
> + *  by Niek Linnenbank.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "hw/sysbus.h"
> +#include "migration/vmstate.h"
> +#include "qemu/log.h"
> +#include "qemu/module.h"
> +#include "hw/misc/allwinner-a10-dramc.h"
> +
> +/* DRAMC register offsets */
> +enum {
> +REG_SDR_CCR = 0x,
> +REG_SDR_ZQCR0 = 0x00a8,
> +REG_SDR_ZQSR = 0x00b0
> +};
>

This matches indeed with what is currently implemented in u-boot in the
file arch/arm/include/asm/arch-sunxi/dram_sun4i.h.
And since the datasheets don't document the DRAM controllers, probably the
best we can do is match with u-boot.

Reviewed-by: Niek Linnenbank 

Regards,
Niek


> +
> +#define REG_INDEX(offset)(offset / sizeof(uint32_t))
> +
> +/* DRAMC register flags */
> +enum {
> +REG_SDR_CCR_DATA_TRAINING = (1 << 30),
> +REG_SDR_CCR_DRAM_INIT = (1 << 31),
> +};
> +enum {
> +REG_SDR_ZQSR_ZCAL = (1 << 31),
> +};
> +
> +/* DRAMC

[PATCH 2/6] hw/misc: Allwinner A10 DRAM Controller Emulation

2022-12-03 Thread Strahinja Jankovic 
During SPL boot several DRAM Controller registers are used. Most
important registers are those related to DRAM initialization and
calibration, where SPL initiates process and waits until certain bit is
set/cleared.

This patch adds these registers, initializes reset values from user's
guide and updates state of registers as SPL expects it.

Signed-off-by: Strahinja Jankovic 
---
 hw/arm/Kconfig|   1 +
 hw/arm/allwinner-a10.c|   7 +
 hw/misc/Kconfig   |   3 +
 hw/misc/allwinner-a10-dramc.c | 179 ++
 hw/misc/meson.build   |   1 +
 include/hw/arm/allwinner-a10.h|   2 +
 include/hw/misc/allwinner-a10-dramc.h |  68 ++
 7 files changed, 261 insertions(+)
 create mode 100644 hw/misc/allwinner-a10-dramc.c
 create mode 100644 include/hw/misc/allwinner-a10-dramc.h

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 14f52b41af..140f142ae5 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -320,6 +320,7 @@ config ALLWINNER_A10
 select ALLWINNER_A10_PIT
 select ALLWINNER_A10_PIC
 select ALLWINNER_A10_CCM
+select ALLWINNER_A10_DRAMC
 select ALLWINNER_EMAC
 select SERIAL
 select UNIMP
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 86baeeeca2..a5f7a36ac9 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -25,6 +25,7 @@
 #include "hw/boards.h"
 #include "hw/usb/hcd-ohci.h"
 
+#define AW_A10_DRAMC_BASE   0x01c01000
 #define AW_A10_MMC0_BASE0x01c0f000
 #define AW_A10_CCM_BASE 0x01c2
 #define AW_A10_PIC_REG_BASE 0x01c20400
@@ -49,6 +50,8 @@ static void aw_a10_init(Object *obj)
 
 object_initialize_child(obj, "ccm", >ccm, TYPE_AW_A10_CCM);
 
+object_initialize_child(obj, "dramc", >dramc, TYPE_AW_A10_DRAMC);
+
 object_initialize_child(obj, "emac", >emac, TYPE_AW_EMAC);
 
 object_initialize_child(obj, "sata", >sata, TYPE_ALLWINNER_AHCI);
@@ -110,6 +113,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
 sysbus_realize(SYS_BUS_DEVICE(>ccm), _fatal);
 sysbus_mmio_map(SYS_BUS_DEVICE(>ccm), 0, AW_A10_CCM_BASE);
 
+/* DRAM Control Module */
+sysbus_realize(SYS_BUS_DEVICE(>dramc), _fatal);
+sysbus_mmio_map(SYS_BUS_DEVICE(>dramc), 0, AW_A10_DRAMC_BASE);
+
 /* FIXME use qdev NIC properties instead of nd_table[] */
 if (nd_table[0].used) {
 qemu_check_nic_model(_table[0], TYPE_AW_EMAC);
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index ed07bf4133..052fb54310 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -177,4 +177,7 @@ config LASI
 config ALLWINNER_A10_CCM
 bool
 
+config ALLWINNER_A10_DRAMC
+bool
+
 source macio/Kconfig
diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
new file mode 100644
index 00..e118b0c2fd
--- /dev/null
+++ b/hw/misc/allwinner-a10-dramc.c
@@ -0,0 +1,179 @@
+/*
+ * Allwinner A10 DRAM Controller emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic 
+ *
+ *  This file is derived from Allwinner H3 DRAMC,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-a10-dramc.h"
+
+/* DRAMC register offsets */
+enum {
+REG_SDR_CCR = 0x,
+REG_SDR_ZQCR0 = 0x00a8,
+REG_SDR_ZQSR = 0x00b0
+};
+
+#define REG_INDEX(offset)(offset / sizeof(uint32_t))
+
+/* DRAMC register flags */
+enum {
+REG_SDR_CCR_DATA_TRAINING = (1 << 30),
+REG_SDR_CCR_DRAM_INIT = (1 << 31),
+};
+enum {
+REG_SDR_ZQSR_ZCAL = (1 << 31),
+};
+
+/* DRAMC register reset values */
+enum {
+REG_SDR_CCR_RESET   = 0x8002,
+REG_SDR_ZQCR0_RESET = 0x07b0,
+REG_SDR_ZQSR_RESET  = 0x8000
+};
+
+static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
+   unsigned size)
+{
+const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
+const uint32_t idx = REG_INDEX(offset);
+
+switch (offset) {
+case REG_SDR_CCR:
+case REG_SDR_ZQCR0:
+case REG_SDR_ZQSR:
+break;
+case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+