Re: [PATCH 4/6] target/ppc: 4xx optimise tlbwe_lo TLB flushing

[Cédric Le Goater]

On 1/17/24 16:12, Nicholas Piggin wrote:

Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.

Signed-off-by: Nicholas Piggin 




Acked-by: Cédric Le Goater 

Thanks,

C.


---
  target/ppc/mmu_helper.c | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 68632bf54e..923779d052 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -813,12 +813,20 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong 
entry,
  void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
   target_ulong val)
  {
+CPUState *cs = env_cpu(env);
  ppcemb_tlb_t *tlb;
  
  qemu_log_mask(CPU_LOG_MMU, "%s entry %i val " TARGET_FMT_lx "\n",

__func__, (int)entry, val);
  entry &= PPC4XX_TLB_ENTRY_MASK;
  tlb = &env->tlb.tlbe[entry];
+/* Invalidate previous TLB (if it's valid) */
+if (tlb->prot & PAGE_VALID) {
+qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start "
+  TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
+  (int)entry, tlb->EPN, tlb->EPN + tlb->size);
+ppcemb_tlb_flush(cs, tlb);
+}
  tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;
  tlb->RPN = val & PPC4XX_TLBLO_RPN_MASK;
  tlb->prot = PAGE_READ;
@@ -836,8 +844,6 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong 
entry,
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
-
-env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
  }
  
  target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)

[PATCH 4/6] target/ppc: 4xx optimise tlbwe_lo TLB flushing

[Nicholas Piggin]

Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.

Signed-off-by: Nicholas Piggin 
---
 target/ppc/mmu_helper.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 68632bf54e..923779d052 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -813,12 +813,20 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong 
entry,
 void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
  target_ulong val)
 {
+CPUState *cs = env_cpu(env);
 ppcemb_tlb_t *tlb;
 
 qemu_log_mask(CPU_LOG_MMU, "%s entry %i val " TARGET_FMT_lx "\n",
   __func__, (int)entry, val);
 entry &= PPC4XX_TLB_ENTRY_MASK;
 tlb = &env->tlb.tlbe[entry];
+/* Invalidate previous TLB (if it's valid) */
+if (tlb->prot & PAGE_VALID) {
+qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start "
+  TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
+  (int)entry, tlb->EPN, tlb->EPN + tlb->size);
+ppcemb_tlb_flush(cs, tlb);
+}
 tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;
 tlb->RPN = val & PPC4XX_TLBLO_RPN_MASK;
 tlb->prot = PAGE_READ;
@@ -836,8 +844,6 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong 
entry,
   tlb->prot & PAGE_WRITE ? 'w' : '-',
   tlb->prot & PAGE_EXEC ? 'x' : '-',
   tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
-
-env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
 }
 
 target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
-- 
2.42.0