Re: [PATCH 4/7] hw/hppa: Inform SeaBIOS about fw_cfg port address

2020-09-02 Thread Helge Deller
On 02.09.20 18:46, Richard Henderson wrote:
> On 9/2/20 4:24 AM, Helge Deller wrote:
>> On 01.09.20 23:39, Richard Henderson wrote:
>>> On 9/1/20 11:34 AM, Helge Deller wrote:
 -/* QEMU fw_cfg interface port */
 -#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
 +#define FW_CFG_IO_BASE  0xfffa
>>>
>>> Why is this value changing?
>>
>> Devices on hppa occupy at least 4k starting at the HPA,
>> so MEMORY_HPA+4k is blocked (by Linux) for the memory module.
>> I noticed this when testing the new Linux kernel patch to
>> let the fw_cfg entries show up in Linux under /proc:
>> https://patchwork.kernel.org/patch/11715133/
>> The Linux kernel driver could not allocate the region for fw_cfg.
>> This new base address seems to not conflict.
>
> Then that information should be in a patch description, and the change should
> be a completely separate patch.

Ok, I've splitted that patch up and added the description in
the last v3 version I just sent.

Helge



Re: [PATCH 4/7] hw/hppa: Inform SeaBIOS about fw_cfg port address

2020-09-02 Thread Richard Henderson
On 9/2/20 4:24 AM, Helge Deller wrote:
> On 01.09.20 23:39, Richard Henderson wrote:
>> On 9/1/20 11:34 AM, Helge Deller wrote:
>>> -/* QEMU fw_cfg interface port */
>>> -#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
>>> +#define FW_CFG_IO_BASE  0xfffa
>>
>> Why is this value changing?
> 
> Devices on hppa occupy at least 4k starting at the HPA,
> so MEMORY_HPA+4k is blocked (by Linux) for the memory module.
> I noticed this when testing the new Linux kernel patch to
> let the fw_cfg entries show up in Linux under /proc:
> https://patchwork.kernel.org/patch/11715133/
> The Linux kernel driver could not allocate the region for fw_cfg.
> This new base address seems to not conflict.

Then that information should be in a patch description, and the change should
be a completely separate patch.


r~



Re: [PATCH 4/7] hw/hppa: Inform SeaBIOS about fw_cfg port address

2020-09-02 Thread Helge Deller
On 01.09.20 23:39, Richard Henderson wrote:
> On 9/1/20 11:34 AM, Helge Deller wrote:
>> -/* QEMU fw_cfg interface port */
>> -#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
>> +#define FW_CFG_IO_BASE  0xfffa
>
> Why is this value changing?

Devices on hppa occupy at least 4k starting at the HPA,
so MEMORY_HPA+4k is blocked (by Linux) for the memory module.
I noticed this when testing the new Linux kernel patch to
let the fw_cfg entries show up in Linux under /proc:
https://patchwork.kernel.org/patch/11715133/
The Linux kernel driver could not allocate the region for fw_cfg.
This new base address seems to not conflict.

Helge



Re: [PATCH 4/7] hw/hppa: Inform SeaBIOS about fw_cfg port address

2020-09-01 Thread Richard Henderson
On 9/1/20 11:34 AM, Helge Deller wrote:
> -/* QEMU fw_cfg interface port */
> -#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
> +#define FW_CFG_IO_BASE  0xfffa

Why is this value changing?


r~



[PATCH 4/7] hw/hppa: Inform SeaBIOS about fw_cfg port address

2020-09-01 Thread Helge Deller
Signed-off-by: Helge Deller 
---
 hw/hppa/hppa_hardware.h | 3 +--
 hw/hppa/machine.c   | 7 ++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h
index cdb7fa6240..bc258895c9 100644
--- a/hw/hppa/hppa_hardware.h
+++ b/hw/hppa/hppa_hardware.h
@@ -38,8 +38,7 @@
 #define PORT_PCI_CMD(PCI_HPA + DINO_PCI_ADDR)
 #define PORT_PCI_DATA   (PCI_HPA + DINO_CONFIG_DATA)

-/* QEMU fw_cfg interface port */
-#define QEMU_FW_CFG_IO_BASE (MEMORY_HPA + 0x80)
+#define FW_CFG_IO_BASE  0xfffa

 #define PORT_SERIAL1(DINO_UART_HPA + 0x800)
 #define PORT_SERIAL2(LASI_UART_HPA + 0x800)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 4b35afc9d5..2bed49807b 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -69,7 +69,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
 FWCfgState *fw_cfg;
 uint64_t val;

-fw_cfg = fw_cfg_init_mem(QEMU_FW_CFG_IO_BASE, QEMU_FW_CFG_IO_BASE + 4);
+fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4);
 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ram_size);
@@ -290,6 +290,9 @@ static void machine_hppa_init(MachineState *machine)

 /* tell firmware how many SMP CPUs to present in inventory table */
 cpu[0]->env.gr[21] = smp_cpus;
+
+/* tell firmware fw_cfg port */
+cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
 }

 static void hppa_machine_reset(MachineState *ms)
@@ -317,6 +320,8 @@ static void hppa_machine_reset(MachineState *ms)
 cpu[0]->env.gr[24] = 'c';
 /* gr22/gr23 unused, no initrd while reboot. */
 cpu[0]->env.gr[21] = smp_cpus;
+/* tell firmware fw_cfg port */
+cpu[0]->env.gr[19] = FW_CFG_IO_BASE;
 }


--
2.21.3