Fabiano Rosas writes:
> We currently clear MSR_LE when copying bits from env->msr to
> new_msr. However, for CPUs that do not have LPCR_ILE we always set
> new_msr[LE] according to env->msr[LE]. And for CPUs that do have ILE
> support we need to check LPCR/HID0 anyway, so there's no need to clear
> the bit when copying.
>
> Signed-off-by: Fabiano Rosas
> ---
> target/ppc/excp_helper.c | 14 +-
> 1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 5d31940426..e56ddbe5d5 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -348,10 +348,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp)
> }
>
> /*
> - * new interrupt handler msr preserves existing HV and ME unless
> - * explicitly overriden
> + * new interrupt handler msr preserves existing HV, ME and LE
> + * unless explicitly overriden.
> */
> -new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> +new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB | MSR_LE);
>
> /* target registers */
> srr0 = SPR_SRR0;
> @@ -763,13 +763,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp)
> if (excp_model >= POWERPC_EXCP_970) {
> if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> new_msr |= (target_ulong)1 << MSR_LE;
> +} else {
> +new_msr &= ~((target_ulong)1 << MSR_LE);
> }
> -} else if (msr_ile) {
> -new_msr |= (target_ulong)1 << MSR_LE;
> -}
> -#else
> -if (msr_ile) {
> -new_msr |= (target_ulong)1 << MSR_LE;
> }
> #endif
This patch is incorrect, don't bother with it. I misread the msr_ile
macro as msr_le. I'll think of an alternative.
