Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2023-01-16 Thread Laurent Vivier

Le 05/11/2022 à 12:53, Michael Tokarev a écrit :

Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
Signed-off-by: Michael Tokarev 
---
  hw/ssi/sifive_spi.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
index 03540cf5ca..1b4a401ca1 100644
--- a/hw/ssi/sifive_spi.c
+++ b/hw/ssi/sifive_spi.c
@@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr,
  case R_RXDATA:
  case R_IP:
  qemu_log_mask(LOG_GUEST_ERROR,
-  "%s: invalid write to read-only reigster 0x%"
+  "%s: invalid write to read-only register 0x%"
HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value);
  break;
  


Applied to my trivial-patches branch.

Thanks,
Laurent




Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2022-11-08 Thread Philippe Mathieu-Daudé

On 8/11/22 23:11, Palmer Dabbelt wrote:

On Sat, 05 Nov 2022 04:53:29 PDT (-0700), m...@tls.msk.ru wrote:

Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0


Not sure if I missed something in QEMU land, but those are usually 
listed more like


Fixes: 0694dabe97 ("hw/ssi: Add SiFive SPI controller support")


MST suggested once to try to restrict the 'Fixes:' tag to bug /
regressions, as it might help downstream distributions to filter
commits to cherry-pick.

Since it might be useful to have the offending commit sha1 in the
description, when it is simply an omission or improvement I use
the an inline form instead of a tag:

  Fixes the typo introduced in commit 0694dabe97 ("hw/ssi: Add SiFive
  SPI controller support").

Although in this particular use-case it is not really useful ;)

Another example:

  When adding  in commit ")>, we forgot
  to fill the API prototype description. Do it now.

Regards,

Phil.



Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2022-11-08 Thread Palmer Dabbelt

On Sat, 05 Nov 2022 04:53:29 PDT (-0700), m...@tls.msk.ru wrote:

Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0


Not sure if I missed something in QEMU land, but those are usually 
listed more like


Fixes: 0694dabe97 ("hw/ssi: Add SiFive SPI controller support")

Checkpatch isn't failing, though.  Either way

Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

Thanks!


Signed-off-by: Michael Tokarev 
---
 hw/ssi/sifive_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
index 03540cf5ca..1b4a401ca1 100644
--- a/hw/ssi/sifive_spi.c
+++ b/hw/ssi/sifive_spi.c
@@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr,
 case R_RXDATA:
 case R_IP:
 qemu_log_mask(LOG_GUEST_ERROR,
-  "%s: invalid write to read-only reigster 0x%"
+  "%s: invalid write to read-only register 0x%"
   HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value);
 break;




Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2022-11-05 Thread Alistair Francis
On Sat, Nov 5, 2022 at 9:54 PM Michael Tokarev  wrote:
>
> Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
> Signed-off-by: Michael Tokarev 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  hw/ssi/sifive_spi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
> index 03540cf5ca..1b4a401ca1 100644
> --- a/hw/ssi/sifive_spi.c
> +++ b/hw/ssi/sifive_spi.c
> @@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr,
>  case R_RXDATA:
>  case R_IP:
>  qemu_log_mask(LOG_GUEST_ERROR,
> -  "%s: invalid write to read-only reigster 0x%"
> +  "%s: invalid write to read-only register 0x%"
>HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, 
> value);
>  break;
>
> --
> 2.30.2
>
>



Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2022-11-05 Thread Stefan Weil via

Am 05.11.22 um 12:53 schrieb Michael Tokarev:

Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
Signed-off-by: Michael Tokarev 
---
  hw/ssi/sifive_spi.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
index 03540cf5ca..1b4a401ca1 100644
--- a/hw/ssi/sifive_spi.c
+++ b/hw/ssi/sifive_spi.c
@@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr,
  case R_RXDATA:
  case R_IP:
  qemu_log_mask(LOG_GUEST_ERROR,
-  "%s: invalid write to read-only reigster 0x%"
+  "%s: invalid write to read-only register 0x%"
HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value);
  break;
  


Reviewed-by: Stefan Weil 


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[PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster

2022-11-05 Thread Michael Tokarev
Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
Signed-off-by: Michael Tokarev 
---
 hw/ssi/sifive_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
index 03540cf5ca..1b4a401ca1 100644
--- a/hw/ssi/sifive_spi.c
+++ b/hw/ssi/sifive_spi.c
@@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr,
 case R_RXDATA:
 case R_IP:
 qemu_log_mask(LOG_GUEST_ERROR,
-  "%s: invalid write to read-only reigster 0x%"
+  "%s: invalid write to read-only register 0x%"
   HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value);
 break;
 
-- 
2.30.2