RE: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

2021-12-10 Thread Jiangyifei via 


> -Original Message-
> From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of
> Anup Patel
> Sent: Friday, December 3, 2021 2:20 PM
> To: Jiangyifei 
> Cc: QEMU Developers ; open list:RISC-V
> ; kvm-ri...@lists.infradead.org; KVM General
> ; libvir-l...@redhat.com; Anup Patel
> ; Palmer Dabbelt ; Alistair
> Francis ; Bin Meng ;
> Fanliang (EulerOS) ; Wubin (H)
> ; Wanghaibin (D) ;
> wanbo (G) ; limingwang (A)
> 
> Subject: Re: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers
> 
> On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang  wrote:
> >
> > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
> >
> > Signed-off-by: Yifei Jiang 
> > Signed-off-by: Mingwang Li 
> > Reviewed-by: Alistair Francis 
> > ---
> >  target/riscv/kvm.c | 150
> > -
> >  1 file changed, 149 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index
> > 9f9692fb9e..b49c24be0a 100644
> > --- a/target/riscv/kvm.c
> > +++ b/target/riscv/kvm.c
> > @@ -55,13 +55,161 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState
> *env, uint64_t type, uint64_t idx
> >  return id;
> >  }
> >
> > +#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env,
> KVM_REG_RISCV_CORE, \
> > + KVM_REG_RISCV_CORE_REG(name))
> > +
> > +#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env,
> KVM_REG_RISCV_CSR, \
> > + KVM_REG_RISCV_CSR_REG(name))
> > +
> > +#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env,
> > +KVM_REG_RISCV_FP_F, idx)
> > +
> > +#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env,
> > +KVM_REG_RISCV_FP_D, idx)
> > +
> > +static int kvm_riscv_get_regs_core(CPUState *cs) {
> > +int ret = 0;
> > +int i;
> > +target_ulong reg;
> > +CPURISCVState *env = _CPU(cs)->env;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->pc = reg;
> > +
> > +for (i = 1; i < 32; i++) {
> > +uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> > +ret = kvm_get_one_reg(cs, id, );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->gpr[i] = reg;
> > +}
> > +
> > +return ret;
> > +}
> > +
> > +static int kvm_riscv_get_regs_csr(CPUState *cs) {
> > +int ret = 0;
> > +target_ulong reg;
> > +CPURISCVState *env = _CPU(cs)->env;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->mstatus = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->mie = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->stvec = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->sscratch = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->sepc = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->scause = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->stval = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->mip = reg;
> > +
> > +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), );
> > +if (ret) {
> > +return ret;
> > +}
> > +env->satp = reg;
> 
> There is a common pattern in above kvm_get_one_reg() calls so I suggest
> creating a macro for repeating code patterns. This can help us to have one 
> line
> for each CSR and in future it is easy to add more CSRs.
> 
> Regards,
> Anup
> 

Thanks, it will be modified in the next series.

Yifei

> > +
>

Re: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

2021-12-02 Thread Anup Patel 
On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang  wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang 
> Signed-off-by: Mingwang Li 
> Reviewed-by: Alistair Francis 
> ---
>  target/riscv/kvm.c | 150 -
>  1 file changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 9f9692fb9e..b49c24be0a 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -55,13 +55,161 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, 
> uint64_t type, uint64_t idx
>  return id;
>  }
>
> +#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, 
> \
> + KVM_REG_RISCV_CORE_REG(name))
> +
> +#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name))
> +
> +#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, 
> idx)
> +
> +#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, 
> idx)
> +
> +static int kvm_riscv_get_regs_core(CPUState *cs)
> +{
> +int ret = 0;
> +int i;
> +target_ulong reg;
> +CPURISCVState *env = _CPU(cs)->env;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), );
> +if (ret) {
> +return ret;
> +}
> +env->pc = reg;
> +
> +for (i = 1; i < 32; i++) {
> +uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> +ret = kvm_get_one_reg(cs, id, );
> +if (ret) {
> +return ret;
> +}
> +env->gpr[i] = reg;
> +}
> +
> +return ret;
> +}
> +
> +static int kvm_riscv_get_regs_csr(CPUState *cs)
> +{
> +int ret = 0;
> +target_ulong reg;
> +CPURISCVState *env = _CPU(cs)->env;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), );
> +if (ret) {
> +return ret;
> +}
> +env->mstatus = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), );
> +if (ret) {
> +return ret;
> +}
> +env->mie = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), );
> +if (ret) {
> +return ret;
> +}
> +env->stvec = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), );
> +if (ret) {
> +return ret;
> +}
> +env->sscratch = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), );
> +if (ret) {
> +return ret;
> +}
> +env->sepc = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), );
> +if (ret) {
> +return ret;
> +}
> +env->scause = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), );
> +if (ret) {
> +return ret;
> +}
> +env->stval = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), );
> +if (ret) {
> +return ret;
> +}
> +env->mip = reg;
> +
> +ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), );
> +if (ret) {
> +return ret;
> +}
> +env->satp = reg;

There is a common pattern in above kvm_get_one_reg() calls so I suggest
creating a macro for repeating code patterns. This can help us to have one
line for each CSR and in future it is easy to add more CSRs.

Regards,
Anup

> +
> +return ret;
> +}
> +
> +static int kvm_riscv_get_regs_fp(CPUState *cs)
> +{
> +int ret = 0;
> +int i;
> +CPURISCVState *env = _CPU(cs)->env;
> +
> +if (riscv_has_ext(env, RVD)) {
> +uint64_t reg;
> +for (i = 0; i < 32; i++) {
> +ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), );
> +if (ret) {
> +return ret;
> +}
> +env->fpr[i] = reg;
> +}
> +return ret;
> +}
> +
> +if (riscv_has_ext(env, RVF)) {
> +uint32_t reg;
> +for (i = 0; i < 32; i++) {
> +ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), );
> +if (ret) {
> +return ret;
> +}
> +env->fpr[i] = reg;
> +}
> +return ret;
> +}
> +
> +return ret;
> +}
> +
>  const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
>  KVM_CAP_LAST_INFO
>  };
>
>  int kvm_arch_get_registers(CPUState *cs)
>  {
> -return 0;
> +int ret = 0;
> +
> +ret = kvm_riscv_get_regs_core(cs);
> +if (ret) {
> +return ret;
> +}
> +
> +ret = kvm_riscv_get_regs_csr(cs);
> +if (ret) {
> +return ret;
> +}
> +
> +ret = kvm_riscv_get_regs_fp(cs);
> +if (ret) {
> +return ret;
> +}
> +
> +return ret;
>  }
>
>  int kvm_arch_put_registers(CPUState *cs, int level)
> --
> 2.19.1
>
>
> --
> kvm-riscv mailing list
> kvm-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv

[PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

2021-11-19 Thread Yifei Jiang 
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.

Signed-off-by: Yifei Jiang 
Signed-off-by: Mingwang Li 
Reviewed-by: Alistair Francis 
---
 target/riscv/kvm.c | 150 -
 1 file changed, 149 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 9f9692fb9e..b49c24be0a 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -55,13 +55,161 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, 
uint64_t type, uint64_t idx
 return id;
 }
 
+#define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, 
idx)
+
+#define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, 
idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+int ret = 0;
+int i;
+target_ulong reg;
+CPURISCVState *env = _CPU(cs)->env;
+
+ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), );
+if (ret) {
+return ret;
+}
+env->pc = reg;
+
+for (i = 1; i < 32; i++) {
+uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+ret = kvm_get_one_reg(cs, id, );
+if (ret) {
+return ret;
+}
+env->gpr[i] = reg;
+}
+
+return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+int ret = 0;
+target_ulong reg;
+CPURISCVState *env = _CPU(cs)->env;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), );
+if (ret) {
+return ret;
+}
+env->mstatus = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), );
+if (ret) {
+return ret;
+}
+env->mie = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), );
+if (ret) {
+return ret;
+}
+env->stvec = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), );
+if (ret) {
+return ret;
+}
+env->sscratch = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), );
+if (ret) {
+return ret;
+}
+env->sepc = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), );
+if (ret) {
+return ret;
+}
+env->scause = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), );
+if (ret) {
+return ret;
+}
+env->stval = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), );
+if (ret) {
+return ret;
+}
+env->mip = reg;
+
+ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), );
+if (ret) {
+return ret;
+}
+env->satp = reg;
+
+return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+int ret = 0;
+int i;
+CPURISCVState *env = _CPU(cs)->env;
+
+if (riscv_has_ext(env, RVD)) {
+uint64_t reg;
+for (i = 0; i < 32; i++) {
+ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), );
+if (ret) {
+return ret;
+}
+env->fpr[i] = reg;
+}
+return ret;
+}
+
+if (riscv_has_ext(env, RVF)) {
+uint32_t reg;
+for (i = 0; i < 32; i++) {
+ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), );
+if (ret) {
+return ret;
+}
+env->fpr[i] = reg;
+}
+return ret;
+}
+
+return ret;
+}
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 KVM_CAP_LAST_INFO
 };
 
 int kvm_arch_get_registers(CPUState *cs)
 {
-return 0;
+int ret = 0;
+
+ret = kvm_riscv_get_regs_core(cs);
+if (ret) {
+return ret;
+}
+
+ret = kvm_riscv_get_regs_csr(cs);
+if (ret) {
+return ret;
+}
+
+ret = kvm_riscv_get_regs_fp(cs);
+if (ret) {
+return ret;
+}
+
+return ret;
 }
 
 int kvm_arch_put_registers(CPUState *cs, int level)
-- 
2.19.1