subject:"\[PATCH v2\] hw\/pci\-host\: Update PHB5 XSCOM registers"

Re: [PATCH v2] hw/pci-host: Update PHB5 XSCOM registers

2023-11-07 Thread Daniel Henrique Barboza


Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 10/16/23 14:59, Saif Abrar wrote:

Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Bit-masks specified using PPC_BITMASK macro.

Signed-off-by: Saif Abrar 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Harsh Prateek Bora 
---
v2: Bit-masks specified using PPC_BITMASK macro.

  hw/pci-host/pnv_phb4.c  | 46 ++---
  hw/pci-host/pnv_phb4_pec.c  | 33 +
  include/hw/pci-host/pnv_phb4.h  |  2 +-
  include/hw/pci-host/pnv_phb4_regs.h |  4 ++-
  4 files changed, 60 insertions(+), 25 deletions(-)

diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 29cb11a5d9..2f935aabd4 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -855,7 +855,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, 
hwaddr addr,
  PnvPHB4 *phb = PNV_PHB4(opaque);
  uint32_t reg = addr >> 3;
  
-/* TODO: add list of allowed registers and error out if not */

+/* All registers are read-able */
  return phb->nest_regs[reg];
  }
  
@@ -1000,7 +1000,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
  
  switch (reg) {

  case PEC_NEST_STK_PCI_NEST_FIR:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val & PPC_BITMASK(0, 27);
  break;
  case PEC_NEST_STK_PCI_NEST_FIR_CLR:
  phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
@@ -1009,7 +1009,8 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
  phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
  break;
  case PEC_NEST_STK_PCI_NEST_FIR_MSK:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val &
+PPC_BITMASK(0, 27);
  break;
  case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
  phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
@@ -1019,7 +1020,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
  break;
  case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
  case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
  break;
  case PEC_NEST_STK_PCI_NEST_FIR_WOF:
  phb->nest_regs[reg] = 0;
@@ -1030,7 +1031,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
  /* Flag error ? */
  break;
  case PEC_NEST_STK_PBCQ_MODE:
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
  break;
  case PEC_NEST_STK_MMIO_BAR0:
  case PEC_NEST_STK_MMIO_BAR0_MASK:
@@ -1041,28 +1042,33 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
   PEC_NEST_STK_BAR_EN_MMIO1)) {
  phb_pec_error(pec, "Changing enabled BAR unsupported");
  }
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 39);
  break;
  case PEC_NEST_STK_PHB_REGS_BAR:
  if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
  phb_pec_error(pec, "Changing enabled BAR unsupported");
  }
-phb->nest_regs[reg] = val & 0xffc0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 41);
  break;
  case PEC_NEST_STK_INT_BAR:
  if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
  phb_pec_error(pec, "Changing enabled BAR unsupported");
  }
-phb->nest_regs[reg] = val & 0xfff0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
  break;
  case PEC_NEST_STK_BAR_EN:
-phb->nest_regs[reg] = val & 0xf000ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 3);
  pnv_pec_phb_update_map(phb);
  break;
  case PEC_NEST_STK_DATA_FRZ_TYPE:
-case PEC_NEST_STK_PBCQ_TUN_BAR:
  /* Not used for now */
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
+break;
+case PEC_NEST_STK_PBCQ_SPARSE_PAGE:
+phb->nest_regs[reg] = val & PPC_BITMASK(3, 5);
+break;
+case PEC_NEST_STK_PBCQ_CACHE_INJ:
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
  break;
  default:
  qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
@@ -1086,7 +1092,7 @@ static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, 
hwaddr addr,
  PnvPHB4 *phb = PNV_PHB4(opaque);
  uint32_t reg = addr >> 3;
  
-/* TODO: add list of allowed registers and error out if not */

+/* All registers are read-able */
  return phb->pci_regs[reg];
  }
  
@@ -1095,10 +1101,9 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque,

[PATCH v2] hw/pci-host: Update PHB5 XSCOM registers

2023-10-16 Thread Saif Abrar

Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Bit-masks specified using PPC_BITMASK macro.

Signed-off-by: Saif Abrar 
Reviewed-by: Cédric Le Goater 
Reviewed-by: Harsh Prateek Bora 
---
v2: Bit-masks specified using PPC_BITMASK macro.

 hw/pci-host/pnv_phb4.c  | 46 ++---
 hw/pci-host/pnv_phb4_pec.c  | 33 +
 include/hw/pci-host/pnv_phb4.h  |  2 +-
 include/hw/pci-host/pnv_phb4_regs.h |  4 ++-
 4 files changed, 60 insertions(+), 25 deletions(-)

diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 29cb11a5d9..2f935aabd4 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -855,7 +855,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, 
hwaddr addr,
 PnvPHB4 *phb = PNV_PHB4(opaque);
 uint32_t reg = addr >> 3;
 
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
 return phb->nest_regs[reg];
 }
 
@@ -1000,7 +1000,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
 
 switch (reg) {
 case PEC_NEST_STK_PCI_NEST_FIR:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val & PPC_BITMASK(0, 27);
 break;
 case PEC_NEST_STK_PCI_NEST_FIR_CLR:
 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
@@ -1009,7 +1009,8 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
 break;
 case PEC_NEST_STK_PCI_NEST_FIR_MSK:
-phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
+phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val &
+PPC_BITMASK(0, 27);
 break;
 case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
@@ -1019,7 +1020,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
 break;
 case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
 case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
 break;
 case PEC_NEST_STK_PCI_NEST_FIR_WOF:
 phb->nest_regs[reg] = 0;
@@ -1030,7 +1031,7 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
 /* Flag error ? */
 break;
 case PEC_NEST_STK_PBCQ_MODE:
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
 break;
 case PEC_NEST_STK_MMIO_BAR0:
 case PEC_NEST_STK_MMIO_BAR0_MASK:
@@ -1041,28 +1042,33 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, 
hwaddr addr,
  PEC_NEST_STK_BAR_EN_MMIO1)) {
 phb_pec_error(pec, "Changing enabled BAR unsupported");
 }
-phb->nest_regs[reg] = val & 0xff00ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 39);
 break;
 case PEC_NEST_STK_PHB_REGS_BAR:
 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
 phb_pec_error(pec, "Changing enabled BAR unsupported");
 }
-phb->nest_regs[reg] = val & 0xffc0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 41);
 break;
 case PEC_NEST_STK_INT_BAR:
 if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
 phb_pec_error(pec, "Changing enabled BAR unsupported");
 }
-phb->nest_regs[reg] = val & 0xfff0ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
 break;
 case PEC_NEST_STK_BAR_EN:
-phb->nest_regs[reg] = val & 0xf000ull;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 3);
 pnv_pec_phb_update_map(phb);
 break;
 case PEC_NEST_STK_DATA_FRZ_TYPE:
-case PEC_NEST_STK_PBCQ_TUN_BAR:
 /* Not used for now */
-phb->nest_regs[reg] = val;
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 27);
+break;
+case PEC_NEST_STK_PBCQ_SPARSE_PAGE:
+phb->nest_regs[reg] = val & PPC_BITMASK(3, 5);
+break;
+case PEC_NEST_STK_PBCQ_CACHE_INJ:
+phb->nest_regs[reg] = val & PPC_BITMASK(0, 7);
 break;
 default:
 qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
@@ -1086,7 +1092,7 @@ static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, 
hwaddr addr,
 PnvPHB4 *phb = PNV_PHB4(opaque);
 uint32_t reg = addr >> 3;
 
-/* TODO: add list of allowed registers and error out if not */
+/* All registers are read-able */
 return phb->pci_regs[reg];
 }
 
@@ -1095,10 +1101,9 @@ static void pnv_pec_stk_pci_xscom_write(void *opaque, 
hwaddr addr,
 {
 PnvPHB4 *phb = PNV_PHB4(opaque);
 uint32_t reg = addr >> 3;
-
 switch (reg) {
 case PEC_PCI_STK_PCI_FIR:
-phb->pci_regs[reg] = val;
+

Re: [PATCH v2] hw/pci-host: Update PHB5 XSCOM registers

[PATCH v2] hw/pci-host: Update PHB5 XSCOM registers

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