Re: [PATCH v2] tests/tcg/s390x: Cleanup of mie3 tests.

[Richard Henderson]

On 3/1/22 10:22, David Miller wrote:

However the constraint must be wrong there.
Sorry about split message.

On Tue, Mar 1, 2022 at 3:21 PM David Miller > wrote:


I used


#define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
{   \
 uint64_t res= 0; \
asm volatile (  \
 "ltgr %[c], %[c]\n" \
 ASM \
 "stg %[c], %[res] " \
 : [res]"=" (res) \
 : [a]"r" (a), \
   [b]"r" (b), \
   [c]"r" (c)   \
); \
 return res; \
}




The final stg is wrong and unnecessary.


r~

Re: [PATCH v2] tests/tcg/s390x: Cleanup of mie3 tests.

[David Miller]

However the constraint must be wrong there.
Sorry about split message.

On Tue, Mar 1, 2022 at 3:21 PM David Miller  wrote:

> I used
>
>
> #define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
> {   \
> uint64_t res = 0;   \
> asm volatile (  \
> "ltgr %[c], %[c]\n" \
> ASM \
> "stg %[c], %[res] " \
> : [res] "=" (res) \
> : [a] "r" (a),  \
>   [b] "r" (b),  \
>   [c] "r" (c)   \
> );  \
> return res; \
> }
>
>
>

Re: [PATCH v2] tests/tcg/s390x: Cleanup of mie3 tests.

[David Miller]

I used


#define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
{   \
uint64_t res = 0;   \
asm volatile (  \
"ltgr %[c], %[c]\n" \
ASM \
"stg %[c], %[res] " \
: [res] "=" (res) \
: [a] "r" (a),  \
  [b] "r" (b),  \
  [c] "r" (c)   \
);  \
return res; \
}

Re: [PATCH v2] tests/tcg/s390x: Cleanup of mie3 tests.

[Richard Henderson]

On 3/1/22 09:59, David Miller wrote:

+{   \
+uint64_t res = 0;   \
+asm volatile (  \
+"lg %%r0, %[c]\n"   \
+"ltgr %%r0, %%r0\n" \
+ASM \
+"stg %%r0, %[res] " \
+: [res] "=m" (res)  \
+: [a] "r" (a),  \
+  [b] "r" (b),  \
+  [c] "m" (c)   \
+: "r0", "memory"\
+);  \


I don't understand why you're still going through memory.

r~

[PATCH v2] tests/tcg/s390x: Cleanup of mie3 tests.

[David Miller]

Adds clobbers and merges remaining separate asm statements.

v1 -> v2:
* Corrected side in rebase conflict, removing older code.


Signed-off-by: David Miller 
---
 tests/tcg/s390x/mie3-compl.c | 18 +++-
 tests/tcg/s390x/mie3-mvcrl.c | 12 +++
 tests/tcg/s390x/mie3-sel.c   | 41 ++--
 3 files changed, 41 insertions(+), 30 deletions(-)

diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
index 35649f3b02..938938df9e 100644
--- a/tests/tcg/s390x/mie3-compl.c
+++ b/tests/tcg/s390x/mie3-compl.c
@@ -1,13 +1,20 @@
 #include 
 
+
 #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
-{ \
-uint64_t res = 0; \
-asm ("llihf %[res],801\n" ASM \
- : [res]"="(res) : [a]"r"(a), [b]"r"(b) : "cc"); \
-return res; \
+{   \
+uint64_t res = 0;   \
+asm volatile (  \
+"llihf %[res],801\n"\
+ASM \
+: [res] "=" (res)  \
+: [a] "r" (a)   \
+, [b] "r" (b)   \
+);  \
+return res; \
 }
 
+
 /* AND WITH COMPLEMENT */
 FbinOp(_ncrk,  ".insn rrf, 0xB9F5, %[res], %[b], %[a], 0\n")
 FbinOp(_ncgrk, ".insn rrf, 0xB9E5, %[res], %[b], %[a], 0\n")
@@ -28,6 +35,7 @@ FbinOp(_nogrk, ".insn rrf, 0xB966, %[res], %[b], %[a], 
0\n")
 FbinOp(_ocrk,  ".insn rrf, 0xB975, %[res], %[b], %[a], 0\n")
 FbinOp(_ocgrk, ".insn rrf, 0xB965, %[res], %[b], %[a], 0\n")
 
+
 int main(int argc, char *argv[])
 {
 if (_ncrk(0xFF88, 0xAA11)  != 0x03210011ull ||
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
index 57b08e48d0..f749dad9c2 100644
--- a/tests/tcg/s390x/mie3-mvcrl.c
+++ b/tests/tcg/s390x/mie3-mvcrl.c
@@ -1,15 +1,17 @@
 #include 
 #include 
 
+
 static inline void mvcrl_8(const char *dst, const char *src)
 {
 asm volatile (
-"llill %%r0, 8\n"
-".insn sse, 0xE50A, 0(%[dst]), 0(%[src])"
-: : [dst] "d" (dst), [src] "d" (src)
-: "memory");
+"llill %%r0, 8\n"
+".insn sse, 0xE50A, 0(%[dst]), 0(%[src])"
+: : [dst] "d" (dst), [src] "d" (src)
+: "r0", "memory");
 }
 
+
 int main(int argc, char *argv[])
 {
 const char *alpha = "abcdefghijklmnop";
@@ -25,3 +27,5 @@ int main(int argc, char *argv[])
 
 return strncmp(alpha, tstr, 16ul);
 }
+
+
diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
index b0c5c9857d..ca6043251b 100644
--- a/tests/tcg/s390x/mie3-sel.c
+++ b/tests/tcg/s390x/mie3-sel.c
@@ -1,28 +1,26 @@
 #include 
 
 #define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
-{\
-uint64_t res = 0;\
-asm (\
- "lg %%r2, %[a]\n"   \
- "lg %%r3, %[b]\n"   \
- "lg %%r0, %[c]\n"   \
- "ltgr %%r0, %%r0\n" \
- ASM \
- "stg %%r0, %[res] " \
- : [res] "=m" (res)  \
- : [a] "m" (a),  \
-   [b] "m" (b),  \
-   [c] "m" (c)   \
- : "r0", "r2",   \
-   "r3", "r4"\
-);   \
-return res;  \
+{   \
+uint64_t res = 0;   \
+asm volatile (  \
+"lg %%r0, %[c]\n"   \
+"ltgr %%r0, %%r0\n" \
+ASM \
+"stg %%r0, %[res] " \
+: [res] "=m" (res)  \
+: [a] "r" (a),  \
+  [b] "r" (b),  \
+  [c] "m" (c)   \
+: "r0", "memory"\
+);  \
+return res; \
 }
 
-Fi3 (_selre, ".insn rrf, 0xB9F0, %%r0, %%r3, %%r2, 8\n")
-Fi3 (_selgrz,".insn rrf, 0xB9E3, %%r0, %%r3, %%r2, 8\n")
-Fi3 (_selfhrnz,  ".insn rrf, 0xB9C0, %%r0, %%r3, %%r2, 7\n")
+Fi3 (_selre, ".insn rrf, 0xB9F0, %%r0, %[b], %[a], 8\n")
+Fi3 (_selgrz,".insn rrf, 0xB9E3, %%r0, %[b], %[a], 8\n")
+Fi3 (_selfhrnz,  ".insn rrf, 0xB9C0, %%r0, %[b], %[a], 7\n")
+
 
 int main(int argc, char *argv[])
 {
@@ -34,5 +32,6 @@ int main(int argc, char *argv[])
 return (int) (
 (0x0066ull != a) ||
 (0xF00D0005ull != b) ||
-(0x0654ull != c));
+(0x0654ull != c) );
 }
+
-- 
2.34.1