Re: [PATCH v2 00/21] target/ppc: Remove hidden usages of *env
On 5/2/22 16:39, Víctor Colombo wrote: By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'` we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't take *env as a parameter. Richard Henderson said [1] that these macros hiding the usage of *env "are evil". This patch series remove them and substitute with an explicit usage of *env by using registerfields API. Patch 20 (target/ppc: Add unused msr bits FIELDs) declares unused FIELDs, the same that were removed in patch 02 (target/ppc: Remove unused msr_* macros). I did that to keep the changes consistent with what was already present before. Patch 21 (target/ppc: Change MSR_* to follow POWER ISA numbering convention) changes the MSR_* bit number to match POWER ISA by adding a new macro to 'invert' the ordering. (added in v2) [1]: https://lists.gnu.org/archive/html/qemu-ppc/2021-11/msg00280.html Patches requiring review: Patch 3 and after Hello everyone, thanks for your kind reviews in v1, What do you think of this new approach I did for v2? It looks real good. I hope we can queue it for the next PR. Thanks, C. v2: - Abandon the ideia to add an M_MSR_* macro - Instead, use registerfields API as suggested by Richard - Add patch 21 to invert MSR_* values to match ISA ordering Víctor Colombo (21): target/ppc: Remove fpscr_* macros from cpu.h target/ppc: Remove unused msr_* macros target/ppc: Remove msr_pr macro target/ppc: Remove msr_le macro target/ppc: Remove msr_ds macro target/ppc: Remove msr_ile macro target/ppc: Remove msr_ee macro target/ppc: Remove msr_ce macro target/ppc: Remove msr_pow macro target/ppc: Remove msr_me macro target/ppc: Remove msr_gs macro target/ppc: Remove msr_fp macro target/ppc: Remove msr_me macro target/ppc: Remove msr_ir macro target/ppc: Remove msr_dr macro target/ppc: Remove msr_ep macro target/ppc: Remove msr_fe0 and msr_fe1 macros target/ppc: Remove msr_ts macro target/ppc: Remove msr_hv macro target/ppc: Add unused msr bits FIELDs target/ppc: Change MSR_* to follow POWER ISA numbering convention hw/ppc/pegasos2.c| 2 +- hw/ppc/spapr.c | 2 +- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 214 ++- target/ppc/cpu_init.c| 23 +++-- target/ppc/excp_helper.c | 66 +++- target/ppc/fpu_helper.c | 28 ++--- target/ppc/gdbstub.c | 2 +- target/ppc/helper_regs.c | 12 +-- target/ppc/kvm.c | 7 +- target/ppc/machine.c | 2 +- target/ppc/mem_helper.c | 23 +++-- target/ppc/misc_helper.c | 2 +- target/ppc/mmu-radix64.c | 11 +- target/ppc/mmu_common.c | 40 target/ppc/mmu_helper.c | 6 +- 16 files changed, 225 insertions(+), 217 deletions(-)
[PATCH v2 00/21] target/ppc: Remove hidden usages of *env
By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'` we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't take *env as a parameter. Richard Henderson said [1] that these macros hiding the usage of *env "are evil". This patch series remove them and substitute with an explicit usage of *env by using registerfields API. Patch 20 (target/ppc: Add unused msr bits FIELDs) declares unused FIELDs, the same that were removed in patch 02 (target/ppc: Remove unused msr_* macros). I did that to keep the changes consistent with what was already present before. Patch 21 (target/ppc: Change MSR_* to follow POWER ISA numbering convention) changes the MSR_* bit number to match POWER ISA by adding a new macro to 'invert' the ordering. (added in v2) [1]: https://lists.gnu.org/archive/html/qemu-ppc/2021-11/msg00280.html Patches requiring review: Patch 3 and after Hello everyone, thanks for your kind reviews in v1, What do you think of this new approach I did for v2? v2: - Abandon the ideia to add an M_MSR_* macro - Instead, use registerfields API as suggested by Richard - Add patch 21 to invert MSR_* values to match ISA ordering Víctor Colombo (21): target/ppc: Remove fpscr_* macros from cpu.h target/ppc: Remove unused msr_* macros target/ppc: Remove msr_pr macro target/ppc: Remove msr_le macro target/ppc: Remove msr_ds macro target/ppc: Remove msr_ile macro target/ppc: Remove msr_ee macro target/ppc: Remove msr_ce macro target/ppc: Remove msr_pow macro target/ppc: Remove msr_me macro target/ppc: Remove msr_gs macro target/ppc: Remove msr_fp macro target/ppc: Remove msr_me macro target/ppc: Remove msr_ir macro target/ppc: Remove msr_dr macro target/ppc: Remove msr_ep macro target/ppc: Remove msr_fe0 and msr_fe1 macros target/ppc: Remove msr_ts macro target/ppc: Remove msr_hv macro target/ppc: Add unused msr bits FIELDs target/ppc: Change MSR_* to follow POWER ISA numbering convention hw/ppc/pegasos2.c| 2 +- hw/ppc/spapr.c | 2 +- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 214 ++- target/ppc/cpu_init.c| 23 +++-- target/ppc/excp_helper.c | 66 +++- target/ppc/fpu_helper.c | 28 ++--- target/ppc/gdbstub.c | 2 +- target/ppc/helper_regs.c | 12 +-- target/ppc/kvm.c | 7 +- target/ppc/machine.c | 2 +- target/ppc/mem_helper.c | 23 +++-- target/ppc/misc_helper.c | 2 +- target/ppc/mmu-radix64.c | 11 +- target/ppc/mmu_common.c | 40 target/ppc/mmu_helper.c | 6 +- 16 files changed, 225 insertions(+), 217 deletions(-) -- 2.25.1