Re: [PATCH v2 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
On 6/12/20 12:30 AM, Havard Skinnemoen wrote:
> The Nuvoton NPCM7xx SoC family are used to implement Baseboard
> Management Controllers in servers. While the family includes four SoCs,
> this patch implements limited support for two of them: NPCM730 (targeted
> for Data Center applications) and NPCM750 (targeted for Enterprise
> applications).
>
> This patch includes little more than the bare minimum needed to boot a
> Linux kernel built with NPCM7xx support in direct-kernel mode:
>
> - Two Cortex-A9 CPU cores with built-in periperhals.
> - Global Configuration Registers.
> - Clock Management.
> - 3 Timer Modules with 5 timers each.
> - 4 serial ports.
>
> The chips themselves have a lot more features, some of which will be
> added to the model at a later stage.
>
> Reviewed-by: Tyrone Ting
> Reviewed-by: Joel Stanley
> Signed-off-by: Havard Skinnemoen
> ---
> MAINTAINERS | 2 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/npcm7xx.c | 330 +++
> include/hw/arm/npcm7xx.h | 80 ++
> 4 files changed, 413 insertions(+)
> create mode 100644 hw/arm/npcm7xx.c
> create mode 100644 include/hw/arm/npcm7xx.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 97d24b1443..077c86643c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -726,8 +726,10 @@ M: Havard Skinnemoen
> M: Tyrone Ting
> L: qemu-...@nongnu.org
> S: Supported
> +F: hw/arm/npcm7xx*
> F: hw/misc/npcm7xx*
> F: hw/timer/npcm7xx*
> +F: include/hw/arm/npcm7xx*
> F: include/hw/misc/npcm7xx*
> F: include/hw/timer/npcm7xx*
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 534a6a119e..13d163a599 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -41,6 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
> obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
> obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
> obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
> +obj-$(CONFIG_NPCM7XX) += npcm7xx.o
> obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
> diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
> new file mode 100644
> index 00..a5dbf08c00
> --- /dev/null
> +++ b/hw/arm/npcm7xx.c
> @@ -0,0 +1,330 @@
> +/*
> + * Nuvoton NPCM7xx SoC family.
> + *
> + * Copyright 2020 Google LLC
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "exec/address-spaces.h"
> +#include "hw/arm/npcm7xx.h"
> +#include "hw/char/serial.h"
> +#include "hw/loader.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/qdev-properties.h"
> +#include "qapi/error.h"
> +#include "qemu/units.h"
> +#include "sysemu/sysemu.h"
> +
> +/* The first half of the address space is reserved for DDR4 DRAM. */
> +#define NPCM7XX_DRAM_BA (0x)
> +#define NPCM7XX_DRAM_SZ (2 * GiB)
> +
> +/*
> + * This covers the whole MMIO space. We'll use this to catch any MMIO
> accesses
> + * that aren't handled by any device.
> + */
> +#define NPCM7XX_MMIO_BA (0x8000)
> +#define NPCM7XX_MMIO_SZ (0x7FFD)
> +
> +/* Core system modules. */
> +#define NPCM7XX_L2C_BA (0xF03FC000)
> +#define NPCM7XX_CPUP_BA (0xF03FE000)
> +#define NPCM7XX_GCR_BA (0xF080)
> +#define NPCM7XX_CLK_BA (0xF0801000)
> +
> +/* Memory blocks at the end of the address space */
> +#define NPCM7XX_RAM2_BA (0xFFFD)
> +#define NPCM7XX_RAM2_SZ (128 * KiB)
> +#define NPCM7XX_ROM_BA (0x)
> +#define NPCM7XX_ROM_SZ (64 * KiB)
> +
> +/*
> + * Interrupt lines going into the GIC. This does not include internal
> Cortex-A9
> + * interrupts.
> + */
> +enum NPCM7xxInterrupt {
> +NPCM7XX_UART0_IRQ = 2,
> +NPCM7XX_UART1_IRQ,
> +NPCM7XX_UART2_IRQ,
> +NPCM7XX_UART3_IRQ,
> +NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
> +NPCM7XX_TIMER1_IRQ,
> +NPCM7XX_TIMER2_IRQ,
> +NPCM7XX_TIMER3_IRQ,
> +NPCM7XX_TIMER4_IRQ,
> +NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
> +NPCM7XX_TIMER6_IRQ,
> +NPCM7XX_TIMER7_IRQ,
> +NPCM7XX_TIMER8_IRQ,
> +NPCM7XX_TIMER9_IRQ,
> +NPCM7XX_TIMER10_IRQ,/* Timer Module 2 */
> +NPCM7XX_TIMER11_IRQ,
> +NPCM7XX_TIMER12_IRQ,
> +NPCM7XX_TIMER13_IRQ,
> +NPCM7XX_TIMER14_IRQ,
> +};
> +
> +/* Total number of GIC interrupts, including internal Cortex-A9 interrupts.
> */
> +#define NPCM7XX_NUM_IRQ
[PATCH v2 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models
The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).
This patch includes little more than the bare minimum needed to boot a
Linux kernel built with NPCM7xx support in direct-kernel mode:
- Two Cortex-A9 CPU cores with built-in periperhals.
- Global Configuration Registers.
- Clock Management.
- 3 Timer Modules with 5 timers each.
- 4 serial ports.
The chips themselves have a lot more features, some of which will be
added to the model at a later stage.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Signed-off-by: Havard Skinnemoen
---
MAINTAINERS | 2 +
hw/arm/Makefile.objs | 1 +
hw/arm/npcm7xx.c | 330 +++
include/hw/arm/npcm7xx.h | 80 ++
4 files changed, 413 insertions(+)
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 include/hw/arm/npcm7xx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 97d24b1443..077c86643c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -726,8 +726,10 @@ M: Havard Skinnemoen
M: Tyrone Ting
L: qemu-...@nongnu.org
S: Supported
+F: hw/arm/npcm7xx*
F: hw/misc/npcm7xx*
F: hw/timer/npcm7xx*
+F: include/hw/arm/npcm7xx*
F: include/hw/misc/npcm7xx*
F: include/hw/timer/npcm7xx*
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 534a6a119e..13d163a599 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -41,6 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
+obj-$(CONFIG_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
new file mode 100644
index 00..a5dbf08c00
--- /dev/null
+++ b/hw/arm/npcm7xx.c
@@ -0,0 +1,330 @@
+/*
+ * Nuvoton NPCM7xx SoC family.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "exec/address-spaces.h"
+#include "hw/arm/npcm7xx.h"
+#include "hw/char/serial.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+#include "sysemu/sysemu.h"
+
+/* The first half of the address space is reserved for DDR4 DRAM. */
+#define NPCM7XX_DRAM_BA (0x)
+#define NPCM7XX_DRAM_SZ (2 * GiB)
+
+/*
+ * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
+ * that aren't handled by any device.
+ */
+#define NPCM7XX_MMIO_BA (0x8000)
+#define NPCM7XX_MMIO_SZ (0x7FFD)
+
+/* Core system modules. */
+#define NPCM7XX_L2C_BA (0xF03FC000)
+#define NPCM7XX_CPUP_BA (0xF03FE000)
+#define NPCM7XX_GCR_BA (0xF080)
+#define NPCM7XX_CLK_BA (0xF0801000)
+
+/* Memory blocks at the end of the address space */
+#define NPCM7XX_RAM2_BA (0xFFFD)
+#define NPCM7XX_RAM2_SZ (128 * KiB)
+#define NPCM7XX_ROM_BA (0x)
+#define NPCM7XX_ROM_SZ (64 * KiB)
+
+/*
+ * Interrupt lines going into the GIC. This does not include internal Cortex-A9
+ * interrupts.
+ */
+enum NPCM7xxInterrupt {
+NPCM7XX_UART0_IRQ = 2,
+NPCM7XX_UART1_IRQ,
+NPCM7XX_UART2_IRQ,
+NPCM7XX_UART3_IRQ,
+NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
+NPCM7XX_TIMER1_IRQ,
+NPCM7XX_TIMER2_IRQ,
+NPCM7XX_TIMER3_IRQ,
+NPCM7XX_TIMER4_IRQ,
+NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
+NPCM7XX_TIMER6_IRQ,
+NPCM7XX_TIMER7_IRQ,
+NPCM7XX_TIMER8_IRQ,
+NPCM7XX_TIMER9_IRQ,
+NPCM7XX_TIMER10_IRQ,/* Timer Module 2 */
+NPCM7XX_TIMER11_IRQ,
+NPCM7XX_TIMER12_IRQ,
+NPCM7XX_TIMER13_IRQ,
+NPCM7XX_TIMER14_IRQ,
+};
+
+/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
+#define NPCM7XX_NUM_IRQ (160)
+
+/* Register base address for each Timer Module */
+static const hwaddr npcm7xx_tim_addr[] = {
+0xF0008000,
+0xF0009000,
+0xF000A000,
+};
+
+/* Register base address for each 16550 UART */
+static const hwaddr npcm7xx_uart_addr[] = {
+0xF0001000,
+0xF0002000,
+0xF0003000,
+0xF0004000,
+};
+
+void
