Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation
On 4/16/24 19:02, Chalapathi V wrote:
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55 +
include/hw/ppc/pnv_spi_controller_regs.h | 114 ++
These two files should be under hw/ssi/ and include/hw/ssi/. Please
remove '_controller'.
Sure. Thank You.
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c | 278 +++
hw/ppc/Kconfig | 1 +
hw/ppc/meson.build | 1 +
6 files changed, 452 insertions(+)
create mode 100644 include/hw/ppc/pnv_spi_controller.h
create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h
create mode 100644 hw/ppc/pnv_spi_controller.c
diff --git a/include/hw/ppc/pnv_spi_controller.h
b/include/hw/ppc/pnv_spi_controller.h
new file mode 100644
index 00..5ec50fb14c
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This model Supports a connection to a single SPI responder.
+ * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
+ * and an ADC controller.
+ */
+#include "hw/ssi/ssi.h"
+
+#ifndef PPC_PNV_SPI_CONTROLLER_H
+#define PPC_PNV_SPI_CONTROLLER_H
+
+#define TYPE_PNV_SPI_CONTROLLER "pnv-spi-controller"
+#define PNV_SPICONTROLLER(obj) \
+ OBJECT_CHECK(PnvSpiController, (obj), TYPE_PNV_SPI_CONTROLLER)
You could use OBJECT_DECLARE_SIMPLE_TYPE ? Anyhow, I would prefer
naming the macro PNV_SPI_CONTROLLER.
+#define SPI_CONTROLLER_REG_SIZE 8
+
+typedef struct SSIBus SSIBus;
why ?
I might have got compile time errors. I will recheck and update. Thank You.
+
+#define TYPE_PNV_SPI_BUS "pnv-spi-bus"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvSPIBus, PNV_SPI_BUS)
+
+typedef struct PnvSPIBus {
I don't think this extra PnvSPIBus model is useful.
+ SysBusDevice parent_obj;
+
+ SSIBus *ssi_bus;
+ qemu_irq *cs_line;
These two attributes could live under PnvSpiController.
This is added to have a SysBusDevice parent so that I can use the busname in
command line for TPM. I will add these in PnvSpiController with SysBusDevice
parent and test.
You could still compute the bus name from pnv_spi_controller_realize()
and move all PnvSPIBus attributes under PnvSpiController. The PnvSPIBus
is not required.
+ uint32_t id;
and this one would become useless.
+} PnvSPIBus;
+typedef struct PnvSpiController {
+ DeviceState parent;
+
+ PnvSPIBus bus;
+ MemoryRegion xscom_spic_regs;
+ /* SPI controller object number */
+ uint32_t spic_num;
+
+ /* SPI Controller registers */
+ uint64_t error_reg;
+ uint64_t counter_config_reg;
+ uint64_t config_reg1;
+ uint64_t clock_config_reset_control;
+ uint64_t memory_mapping_reg;
+ uint64_t transmit_data_reg;
+ uint64_t receive_data_reg;
+ uint8_t sequencer_operation_reg[SPI_CONTROLLER_REG_SIZE];
+ uint64_t status_reg;
You could use an array of uint64_t also.
Sure. I will try and check.
That's not a must have. Both approach work but since the memops use
the MMIO offest to address the register, it is sometime simpler to
use an array of uint64_t.
+} PnvSpiController;
+#endif /* PPC_PNV_SPI_CONTROLLER_H */
diff --git a/include/hw/ppc/pnv_spi_controller_regs.h
b/include/hw/ppc/pnv_spi_controller_regs.h
new file mode 100644
index 00..6f613aca5e
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller_regs.h
@@ -0,0 +1,114 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef SPI_CONTROLLER_REGS_H
+#define SPI_CONTROLLER_REGS_H
+
+/* Error Register */
+#define ERROR_REG 0x00
+
+/* counter_config_reg */
+#define COUNTER_CONFIG_REG 0x01
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0, 7)
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N2 PPC_BITMASK(8, 15)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE1 PPC_BITMASK(24, 31)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE2 PPC_BITMASK(32, 39)
+#define COUNTER_CONFIG_REG_N1_COUNT_CONTROL
Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and an ADC
controller.
All SPI function control is mapped into the SPI register space to
enable full
control by firmware. In this commit SPI configuration component is
modelled
which contains all SPI configuration and status registers as well as
the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55 +
include/hw/ppc/pnv_spi_controller_regs.h | 114 ++
These two files should be under hw/ssi/ and include/hw/ssi/. Please
remove '_controller'.
Sure. Thank You.
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c | 278 +++
hw/ppc/Kconfig | 1 +
hw/ppc/meson.build | 1 +
6 files changed, 452 insertions(+)
create mode 100644 include/hw/ppc/pnv_spi_controller.h
create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h
create mode 100644 hw/ppc/pnv_spi_controller.c
diff --git a/include/hw/ppc/pnv_spi_controller.h
b/include/hw/ppc/pnv_spi_controller.h
new file mode 100644
index 00..5ec50fb14c
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This model Supports a connection to a single SPI responder.
+ * Introduced for P10 to provide access to SPI seeproms, TPM, flash
device
+ * and an ADC controller.
+ */
+#include "hw/ssi/ssi.h"
+
+#ifndef PPC_PNV_SPI_CONTROLLER_H
+#define PPC_PNV_SPI_CONTROLLER_H
+
+#define TYPE_PNV_SPI_CONTROLLER "pnv-spi-controller"
+#define PNV_SPICONTROLLER(obj) \
+ OBJECT_CHECK(PnvSpiController, (obj), TYPE_PNV_SPI_CONTROLLER)
You could use OBJECT_DECLARE_SIMPLE_TYPE ? Anyhow, I would prefer
naming the macro PNV_SPI_CONTROLLER.
+#define SPI_CONTROLLER_REG_SIZE 8
+
+typedef struct SSIBus SSIBus;
why ?
I might have got compile time errors. I will recheck and update. Thank You.
+
+#define TYPE_PNV_SPI_BUS "pnv-spi-bus"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvSPIBus, PNV_SPI_BUS)
+
+typedef struct PnvSPIBus {
I don't think this extra PnvSPIBus model is useful.
+ SysBusDevice parent_obj;
+
+ SSIBus *ssi_bus;
+ qemu_irq *cs_line;
These two attributes could live under PnvSpiController.
This is added to have a SysBusDevice parent so that I can use the
busname in command line for TPM. I will add these in PnvSpiController
with SysBusDevice parent and test.
+ uint32_t id;
and this one would become useless.
+} PnvSPIBus;
+typedef struct PnvSpiController {
+ DeviceState parent;
+
+ PnvSPIBus bus;
+ MemoryRegion xscom_spic_regs;
+ /* SPI controller object number */
+ uint32_t spic_num;
+
+ /* SPI Controller registers */
+ uint64_t error_reg;
+ uint64_t counter_config_reg;
+ uint64_t config_reg1;
+ uint64_t clock_config_reset_control;
+ uint64_t memory_mapping_reg;
+ uint64_t transmit_data_reg;
+ uint64_t receive_data_reg;
+ uint8_t sequencer_operation_reg[SPI_CONTROLLER_REG_SIZE];
+ uint64_t status_reg;
You could use an array of uint64_t also.
Sure. I will try and check.
+} PnvSpiController;
+#endif /* PPC_PNV_SPI_CONTROLLER_H */
diff --git a/include/hw/ppc/pnv_spi_controller_regs.h
b/include/hw/ppc/pnv_spi_controller_regs.h
new file mode 100644
index 00..6f613aca5e
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller_regs.h
@@ -0,0 +1,114 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef SPI_CONTROLLER_REGS_H
+#define SPI_CONTROLLER_REGS_H
+
+/* Error Register */
+#define ERROR_REG 0x00
+
+/* counter_config_reg */
+#define COUNTER_CONFIG_REG 0x01
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0, 7)
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N2 PPC_BITMASK(8, 15)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE1 PPC_BITMASK(24, 31)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE2 PPC_BITMASK(32, 39)
+#define COUNTER_CONFIG_REG_N1_COUNT_CONTROL PPC_BITMASK(48, 51)
+#define COUNTER_CONFIG_REG_N2_COUNT_CONTROL PPC_BITMASK(52, 55)
+
+/* config_reg */
+#define CONFIG_REG1 0x02
+
+/* clock_config_reset_control_ecc_enable_reg */
+#define CLOCK_CONFIG_REG 0x03
+#define CLOCK_CONFIG_RESET_CONTROL_HARD_RESET 0x0084;
+#define
Re: [PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55 +
include/hw/ppc/pnv_spi_controller_regs.h | 114 ++
These two files should be under hw/ssi/ and include/hw/ssi/. Please
remove '_controller'.
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c | 278 +++
hw/ppc/Kconfig | 1 +
hw/ppc/meson.build | 1 +
6 files changed, 452 insertions(+)
create mode 100644 include/hw/ppc/pnv_spi_controller.h
create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h
create mode 100644 hw/ppc/pnv_spi_controller.c
diff --git a/include/hw/ppc/pnv_spi_controller.h
b/include/hw/ppc/pnv_spi_controller.h
new file mode 100644
index 00..5ec50fb14c
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This model Supports a connection to a single SPI responder.
+ * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
+ * and an ADC controller.
+ */
+#include "hw/ssi/ssi.h"
+
+#ifndef PPC_PNV_SPI_CONTROLLER_H
+#define PPC_PNV_SPI_CONTROLLER_H
+
+#define TYPE_PNV_SPI_CONTROLLER "pnv-spi-controller"
+#define PNV_SPICONTROLLER(obj) \
+OBJECT_CHECK(PnvSpiController, (obj), TYPE_PNV_SPI_CONTROLLER)
You could use OBJECT_DECLARE_SIMPLE_TYPE ? Anyhow, I would prefer
naming the macro PNV_SPI_CONTROLLER.
+#define SPI_CONTROLLER_REG_SIZE 8
+
+typedef struct SSIBus SSIBus;
why ?
+
+#define TYPE_PNV_SPI_BUS "pnv-spi-bus"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvSPIBus, PNV_SPI_BUS)
+
+typedef struct PnvSPIBus {
I don't think this extra PnvSPIBus model is useful.
+SysBusDevice parent_obj;
+
+SSIBus *ssi_bus;
+qemu_irq *cs_line;
These two attributes could live under PnvSpiController.
+uint32_t id;
and this one would become useless.
+} PnvSPIBus;
+typedef struct PnvSpiController {
+DeviceState parent;
+
+PnvSPIBus bus;
+MemoryRegionxscom_spic_regs;
+/* SPI controller object number */
+uint32_tspic_num;
+
+/* SPI Controller registers */
+uint64_terror_reg;
+uint64_tcounter_config_reg;
+uint64_tconfig_reg1;
+uint64_tclock_config_reset_control;
+uint64_tmemory_mapping_reg;
+uint64_ttransmit_data_reg;
+uint64_treceive_data_reg;
+uint8_t sequencer_operation_reg[SPI_CONTROLLER_REG_SIZE];
+uint64_tstatus_reg;
You could use an array of uint64_t also.
+} PnvSpiController;
+#endif /* PPC_PNV_SPI_CONTROLLER_H */
diff --git a/include/hw/ppc/pnv_spi_controller_regs.h
b/include/hw/ppc/pnv_spi_controller_regs.h
new file mode 100644
index 00..6f613aca5e
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller_regs.h
@@ -0,0 +1,114 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef SPI_CONTROLLER_REGS_H
+#define SPI_CONTROLLER_REGS_H
+
+/* Error Register */
+#define ERROR_REG 0x00
+
+/* counter_config_reg */
+#define COUNTER_CONFIG_REG 0x01
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0, 7)
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N2 PPC_BITMASK(8, 15)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE1 PPC_BITMASK(24, 31)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE2 PPC_BITMASK(32, 39)
+#define COUNTER_CONFIG_REG_N1_COUNT_CONTROL PPC_BITMASK(48, 51)
+#define COUNTER_CONFIG_REG_N2_COUNT_CONTROL PPC_BITMASK(52, 55)
+
+/* config_reg */
+#define CONFIG_REG1 0x02
+
+/* clock_config_reset_control_ecc_enable_reg */
+#define CLOCK_CONFIG_REG0x03
+#define CLOCK_CONFIG_RESET_CONTROL_HARD_RESET 0x0084;
+#define CLOCK_CONFIG_REG_RESET_CONTROL PPC_BITMASK(24, 27)
+#define CLOCK_CONFIG_REG_ECC_CONTROLPPC_BITMASK(28, 30)
+
+/* memory_mapping_reg */
+#define MEMORY_MAPPING_REG 0x04
+#define MEMORY_MAPPING_REG_MMSPISM_BASE_ADDRPPC_BITMASK(0, 15)
+#define MEMORY_MAPPING_REG_MMSPISM_ADDR_MASKPPC_BITMASK(16, 31)
[PATCH v2 2/6] hw/ppc: SPI controller model - registers implementation
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55 +
include/hw/ppc/pnv_spi_controller_regs.h | 114 ++
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c | 278 +++
hw/ppc/Kconfig | 1 +
hw/ppc/meson.build | 1 +
6 files changed, 452 insertions(+)
create mode 100644 include/hw/ppc/pnv_spi_controller.h
create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h
create mode 100644 hw/ppc/pnv_spi_controller.c
diff --git a/include/hw/ppc/pnv_spi_controller.h
b/include/hw/ppc/pnv_spi_controller.h
new file mode 100644
index 00..5ec50fb14c
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This model Supports a connection to a single SPI responder.
+ * Introduced for P10 to provide access to SPI seeproms, TPM, flash device
+ * and an ADC controller.
+ */
+#include "hw/ssi/ssi.h"
+
+#ifndef PPC_PNV_SPI_CONTROLLER_H
+#define PPC_PNV_SPI_CONTROLLER_H
+
+#define TYPE_PNV_SPI_CONTROLLER "pnv-spi-controller"
+#define PNV_SPICONTROLLER(obj) \
+OBJECT_CHECK(PnvSpiController, (obj), TYPE_PNV_SPI_CONTROLLER)
+
+#define SPI_CONTROLLER_REG_SIZE 8
+
+typedef struct SSIBus SSIBus;
+
+#define TYPE_PNV_SPI_BUS "pnv-spi-bus"
+OBJECT_DECLARE_SIMPLE_TYPE(PnvSPIBus, PNV_SPI_BUS)
+
+typedef struct PnvSPIBus {
+SysBusDevice parent_obj;
+
+SSIBus *ssi_bus;
+qemu_irq *cs_line;
+uint32_t id;
+} PnvSPIBus;
+
+typedef struct PnvSpiController {
+DeviceState parent;
+
+PnvSPIBus bus;
+MemoryRegionxscom_spic_regs;
+/* SPI controller object number */
+uint32_tspic_num;
+
+/* SPI Controller registers */
+uint64_terror_reg;
+uint64_tcounter_config_reg;
+uint64_tconfig_reg1;
+uint64_tclock_config_reset_control;
+uint64_tmemory_mapping_reg;
+uint64_ttransmit_data_reg;
+uint64_treceive_data_reg;
+uint8_t sequencer_operation_reg[SPI_CONTROLLER_REG_SIZE];
+uint64_tstatus_reg;
+} PnvSpiController;
+#endif /* PPC_PNV_SPI_CONTROLLER_H */
diff --git a/include/hw/ppc/pnv_spi_controller_regs.h
b/include/hw/ppc/pnv_spi_controller_regs.h
new file mode 100644
index 00..6f613aca5e
--- /dev/null
+++ b/include/hw/ppc/pnv_spi_controller_regs.h
@@ -0,0 +1,114 @@
+/*
+ * QEMU PowerPC SPI Controller model
+ *
+ * Copyright (c) 2023, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef SPI_CONTROLLER_REGS_H
+#define SPI_CONTROLLER_REGS_H
+
+/* Error Register */
+#define ERROR_REG 0x00
+
+/* counter_config_reg */
+#define COUNTER_CONFIG_REG 0x01
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0, 7)
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N2 PPC_BITMASK(8, 15)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE1 PPC_BITMASK(24, 31)
+#define COUNTER_CONFIG_REG_COUNT_COMPARE2 PPC_BITMASK(32, 39)
+#define COUNTER_CONFIG_REG_N1_COUNT_CONTROL PPC_BITMASK(48, 51)
+#define COUNTER_CONFIG_REG_N2_COUNT_CONTROL PPC_BITMASK(52, 55)
+
+/* config_reg */
+#define CONFIG_REG1 0x02
+
+/* clock_config_reset_control_ecc_enable_reg */
+#define CLOCK_CONFIG_REG0x03
+#define CLOCK_CONFIG_RESET_CONTROL_HARD_RESET 0x0084;
+#define CLOCK_CONFIG_REG_RESET_CONTROL PPC_BITMASK(24, 27)
+#define CLOCK_CONFIG_REG_ECC_CONTROLPPC_BITMASK(28, 30)
+
+/* memory_mapping_reg */
+#define MEMORY_MAPPING_REG 0x04
+#define MEMORY_MAPPING_REG_MMSPISM_BASE_ADDRPPC_BITMASK(0, 15)
+#define MEMORY_MAPPING_REG_MMSPISM_ADDR_MASKPPC_BITMASK(16, 31)
+#define MEMORY_MAPPING_REG_RDR_MATCH_VALPPC_BITMASK(32, 47)
+#define MEMORY_MAPPING_REG_RDR_MATCH_MASK PPC_BITMASK(48, 63)
+
+/* transmit_data_reg */
+#define TRANSMIT_DATA_REG 0x05
+
+/* receive_data_reg */
+#define RECEIVE_DATA_REG0x06
+
+/* sequencer_operation_reg */
+#define SEQUENCER_OPERATION_REG 0x07
+
+/* status_reg */
+#define STATUS_REG 0x08
+#define STATUS_REG_RDR_FULL PPC_BIT(0)
+#define
