RE: [PATCH v3 3/9] igb: add ICR_RXDW
> -Original Message-
> From: Akihiko Odaki
> Sent: Wednesday, 1 February 2023 05:36
> To: Sriram Yagnaraman
> Cc: qemu-devel@nongnu.org; Jason Wang ; Dmitry
> Fleytman ; Michael S . Tsirkin
> ; Marcel Apfelbaum
> Subject: Re: [PATCH v3 3/9] igb: add ICR_RXDW
>
> On 2023/01/31 18:42, Sriram Yagnaraman wrote:
> > IGB uses RXDW ICR bit to indicate that rx descriptor has been written
> > back. This is the same as RXT0 bit in older HW.
> >
> > Signed-off-by: Sriram Yagnaraman
> > ---
> > hw/net/e1000x_regs.h | 4
> > hw/net/igb_core.c| 46 +---
> > 2 files changed, 22 insertions(+), 28 deletions(-)
> >
> > diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index
> > fb5b861135..f509db73a7 100644
> > --- a/hw/net/e1000x_regs.h
> > +++ b/hw/net/e1000x_regs.h
> > @@ -335,6 +335,7 @@
> > #define E1000_ICR_RXDMT00x0010 /* rx desc min. threshold (0)
> */
> > #define E1000_ICR_RXO 0x0040 /* rx overrun */
> > #define E1000_ICR_RXT0 0x0080 /* rx timer intr (ring 0) */
> > +#define E1000_ICR_RXDW 0x0080 /* rx desc written back */
> > #define E1000_ICR_MDAC 0x0200 /* MDIO access complete */
> > #define E1000_ICR_RXCFG 0x0400 /* RX /c/ ordered set */
> > #define E1000_ICR_GPI_EN0 0x0800 /* GP Int 0 */
> > @@ -378,6 +379,7 @@
> > #define E1000_ICS_RXDMT0E1000_ICR_RXDMT0/* rx desc min.
> threshold */
> > #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
> > #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
> > +#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back
> */
> > #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access
> complete */
> > #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
> > #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
> > @@ -407,6 +409,7 @@
> > #define E1000_IMS_RXDMT0E1000_ICR_RXDMT0/* rx desc min.
> threshold */
> > #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
> > #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
> > +#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back
> */
> > #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access
> complete */
> > #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
> > #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
> > @@ -441,6 +444,7 @@
> > #define E1000_IMC_RXDMT0E1000_ICR_RXDMT0/* rx desc min.
> threshold */
> > #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
> > #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
> > +#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back
> */
> > #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access
> complete */
> > #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
> > #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
> > diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index
> > 9c32ad5e36..e78bc3611a 100644
> > --- a/hw/net/igb_core.c
> > +++ b/hw/net/igb_core.c
> > @@ -1488,7 +1488,7 @@ igb_receive_internal(IGBCore *core, const struct
> iovec *iov, int iovcnt,
> > static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
> >
> > uint16_t queues = 0;
> > -uint32_t n;
> > +uint32_t icr_bits = 0;
> > uint8_t min_buf[ETH_ZLEN];
> > struct iovec min_iov;
> > struct eth_header *ehdr;
> > @@ -1561,6 +1561,7 @@ igb_receive_internal(IGBCore *core, const struct
> iovec *iov, int iovcnt,
> > e1000x_fcs_len(core->mac);
> >
> > retval = orig_size;
> > +igb_rx_fix_l4_csum(core, core->rx_pkt);
> >
> > for (i = 0; i < IGB_NUM_QUEUES; i++) {
> > if (!(queues & BIT(i))) {
> > @@ -1569,43 +1570,32 @@ igb_receive_internal(IGBCore *core, const
> > struct iovec *iov, int iovcnt,
> >
> > igb_rx_ring_init(core, , i);
> >
> > -trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
> > -
> > if (!igb_has_rxbufs(core, rxr.i, total_size)) {
> > -retval = 0;
> > +icr_bits |= E1000_ICS_RXO;
> > +continue;
> > }
> > -}
> >
> > -if (retval) {
> > -n = E1000_ICR_RXT0;
> > -
> > -
Re: [PATCH v3 3/9] igb: add ICR_RXDW
On 2023/01/31 18:42, Sriram Yagnaraman wrote:
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000x_regs.h | 4
hw/net/igb_core.c| 46 +---
2 files changed, 22 insertions(+), 28 deletions(-)
diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h
index fb5b861135..f509db73a7 100644
--- a/hw/net/e1000x_regs.h
+++ b/hw/net/e1000x_regs.h
@@ -335,6 +335,7 @@
#define E1000_ICR_RXDMT00x0010 /* rx desc min. threshold (0) */
#define E1000_ICR_RXO 0x0040 /* rx overrun */
#define E1000_ICR_RXT0 0x0080 /* rx timer intr (ring 0) */
+#define E1000_ICR_RXDW 0x0080 /* rx desc written back */
#define E1000_ICR_MDAC 0x0200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x0400 /* RX /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x0800 /* GP Int 0 */
@@ -378,6 +379,7 @@
#define E1000_ICS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -407,6 +409,7 @@
#define E1000_IMS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -441,6 +444,7 @@
#define E1000_IMC_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 9c32ad5e36..e78bc3611a 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1488,7 +1488,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
uint16_t queues = 0;
-uint32_t n;
+uint32_t icr_bits = 0;
uint8_t min_buf[ETH_ZLEN];
struct iovec min_iov;
struct eth_header *ehdr;
@@ -1561,6 +1561,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
e1000x_fcs_len(core->mac);
retval = orig_size;
+igb_rx_fix_l4_csum(core, core->rx_pkt);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
if (!(queues & BIT(i))) {
@@ -1569,43 +1570,32 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
igb_rx_ring_init(core, , i);
-trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
-
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
-retval = 0;
+icr_bits |= E1000_ICS_RXO;
+continue;
}
-}
-if (retval) {
-n = E1000_ICR_RXT0;
-
-igb_rx_fix_l4_csum(core, core->rx_pkt);
-
-for (i = 0; i < IGB_NUM_QUEUES; i++) {
-if (!(queues & BIT(i))) {
-continue;
-}
-
-igb_rx_ring_init(core, , i);
+trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
+igb_write_packet_to_guest(core, core->rx_pkt, , _info);
-igb_write_packet_to_guest(core, core->rx_pkt, , _info);
+/* Check if receive descriptor minimum threshold hit */
+if (igb_rx_descr_threshold_hit(core, rxr.i)) {
+icr_bits |= E1000_ICS_RXDMT0;
+}
-/* Check if receive descriptor minimum threshold hit */
-if (igb_rx_descr_threshold_hit(core, rxr.i)) {
-n |= E1000_ICS_RXDMT0;
-}
+core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-}
+icr_bits |= E1000_ICR_RXDW;
+}
-trace_e1000e_rx_written_to_guest(n);
+if (icr_bits & E1000_ICR_RXDW) {
+trace_e1000e_rx_written_to_guest(icr_bits);
} else {
-n = E1000_ICS_RXO;
-trace_e1000e_rx_not_written_to_guest(n);
+
[PATCH v3 3/9] igb: add ICR_RXDW
IGB uses RXDW ICR bit to indicate that rx descriptor has been written
back. This is the same as RXT0 bit in older HW.
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000x_regs.h | 4
hw/net/igb_core.c| 46 +---
2 files changed, 22 insertions(+), 28 deletions(-)
diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h
index fb5b861135..f509db73a7 100644
--- a/hw/net/e1000x_regs.h
+++ b/hw/net/e1000x_regs.h
@@ -335,6 +335,7 @@
#define E1000_ICR_RXDMT00x0010 /* rx desc min. threshold (0) */
#define E1000_ICR_RXO 0x0040 /* rx overrun */
#define E1000_ICR_RXT0 0x0080 /* rx timer intr (ring 0) */
+#define E1000_ICR_RXDW 0x0080 /* rx desc written back */
#define E1000_ICR_MDAC 0x0200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x0400 /* RX /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x0800 /* GP Int 0 */
@@ -378,6 +379,7 @@
#define E1000_ICS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -407,6 +409,7 @@
#define E1000_IMS_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
@@ -441,6 +444,7 @@
#define E1000_IMC_RXDMT0E1000_ICR_RXDMT0/* rx desc min. threshold */
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
+#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 9c32ad5e36..e78bc3611a 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1488,7 +1488,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
uint16_t queues = 0;
-uint32_t n;
+uint32_t icr_bits = 0;
uint8_t min_buf[ETH_ZLEN];
struct iovec min_iov;
struct eth_header *ehdr;
@@ -1561,6 +1561,7 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
e1000x_fcs_len(core->mac);
retval = orig_size;
+igb_rx_fix_l4_csum(core, core->rx_pkt);
for (i = 0; i < IGB_NUM_QUEUES; i++) {
if (!(queues & BIT(i))) {
@@ -1569,43 +1570,32 @@ igb_receive_internal(IGBCore *core, const struct iovec
*iov, int iovcnt,
igb_rx_ring_init(core, , i);
-trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
-
if (!igb_has_rxbufs(core, rxr.i, total_size)) {
-retval = 0;
+icr_bits |= E1000_ICS_RXO;
+continue;
}
-}
-if (retval) {
-n = E1000_ICR_RXT0;
-
-igb_rx_fix_l4_csum(core, core->rx_pkt);
-
-for (i = 0; i < IGB_NUM_QUEUES; i++) {
-if (!(queues & BIT(i))) {
-continue;
-}
-
-igb_rx_ring_init(core, , i);
+trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
+igb_write_packet_to_guest(core, core->rx_pkt, , _info);
-igb_write_packet_to_guest(core, core->rx_pkt, , _info);
+/* Check if receive descriptor minimum threshold hit */
+if (igb_rx_descr_threshold_hit(core, rxr.i)) {
+icr_bits |= E1000_ICS_RXDMT0;
+}
-/* Check if receive descriptor minimum threshold hit */
-if (igb_rx_descr_threshold_hit(core, rxr.i)) {
-n |= E1000_ICS_RXDMT0;
-}
+core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
-}
+icr_bits |= E1000_ICR_RXDW;
+}
-trace_e1000e_rx_written_to_guest(n);
+if (icr_bits & E1000_ICR_RXDW) {
+trace_e1000e_rx_written_to_guest(icr_bits);
} else {
-n = E1000_ICS_RXO;
-trace_e1000e_rx_not_written_to_guest(n);
+trace_e1000e_rx_not_written_to_guest(icr_bits);
}
-trace_e1000e_rx_interrupt_set(n);
-
