Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
On Friday, October 11, 2019, Alex Bennée wrote: > > Aleksandar Markovic writes: > > > On Friday, October 11, 2019, Philippe Mathieu-Daudé > > wrote: > > > >> Hi Michael, > >> > >> On 9/2/19 4:01 PM, Michael Rolnik wrote: > >> > >>> This series of patches adds 8bit AVR cores to QEMU. > >>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > >>> tested yet. > >>> However I was able to execute simple code with functions. e.g fibonacci > >>> calculation. > >>> This series of patches include a non real, sample board. > >>> No fuses support yet. PC is set to 0 at reset. > >>> > >>> the patches include the following > >>> 1. just a basic 8bit AVR CPU, without instruction decoding or > translation > >>> 2. CPU features which allow define the following 8bit AVR cores > >>> avr1 > >>> avr2 avr25 > >>> avr3 avr31 avr35 > >>> avr4 > >>> avr5 avr51 > >>> avr6 > >>> xmega2 xmega4 xmega5 xmega6 xmega7 > >>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows > >>> to execute simple code > >>> 4. encoding for all AVR instructions > >>> 5. interrupt handling > >>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions > >>> 7. a decoder which given an opcode decides what istruction it is > >>> 8. translation of AVR instruction into TCG > >>> 9. all features together > >>> > >>> [..] > >> > >>> Michael Rolnik (7): > >>>target/avr: Add outward facing interfaces and core CPU logic > >>>target/avr: Add instruction helpers > >>>target/avr: Add instruction decoding > >>>target/avr: Add instruction translation > >>>target/avr: Add example board configuration > >>>target/avr: Register AVR support with the rest of QEMU, the build > >>> system, and the MAINTAINERS file > >>>target/avr: Add tests > >>> > >>> Sarah Harris (1): > >>>target/avr: Add limited support for USART and 16 bit timer > peripherals > >>> > >> > >> Overall architecture patches look good, but I'd like some more time to > >> review the hardware patches. Unfortunately I won't have time until > November. > >> There was a chat on IRC about your series, > >> > > I don't see the reason why do you initiate IRC communication on this > topic, > > if we have the mailing list for discussing such important issues as > > introducing a new target (that should be definitely visible to all > > participants). > > IRC is often a good way of quickly discussing something when someone is > about (often as a tangent from another discussion). I don't think there > is anything wrong with that as long as it's followed up on the mailing > list. > > OK, at least the series got some attention, be it on IRC or on the list. I still find it odd that suddenly, after months and months of this series practically sitting on the list, any suggestion couldn't first be discussed here, so that we collectively find the best outcome. But, yes, I probably produced much ado about nothing. I hope that this would soon result in helping Michael complete the integration. Micheal, whatever I said regarding patch 4, is only a suggestion - if others are fine with it, I am fine too. Best luck to all involved! :) Aleksandar > > > >> I suggested Richard we could merge patches 1-4 and 7. They are almost > >> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS > >> ones). > > Which is was ;-) > > -- > Alex Bennée > >
Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
Aleksandar Markovic writes: > On Friday, October 11, 2019, Philippe Mathieu-Daudé > wrote: > >> Hi Michael, >> >> On 9/2/19 4:01 PM, Michael Rolnik wrote: >> >>> This series of patches adds 8bit AVR cores to QEMU. >>> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully >>> tested yet. >>> However I was able to execute simple code with functions. e.g fibonacci >>> calculation. >>> This series of patches include a non real, sample board. >>> No fuses support yet. PC is set to 0 at reset. >>> >>> the patches include the following >>> 1. just a basic 8bit AVR CPU, without instruction decoding or translation >>> 2. CPU features which allow define the following 8bit AVR cores >>> avr1 >>> avr2 avr25 >>> avr3 avr31 avr35 >>> avr4 >>> avr5 avr51 >>> avr6 >>> xmega2 xmega4 xmega5 xmega6 xmega7 >>> 3. a definition of sample machine with SRAM, FLASH and CPU which allows >>> to execute simple code >>> 4. encoding for all AVR instructions >>> 5. interrupt handling >>> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions >>> 7. a decoder which given an opcode decides what istruction it is >>> 8. translation of AVR instruction into TCG >>> 9. all features together >>> >>> [..] >> >>> Michael Rolnik (7): >>>target/avr: Add outward facing interfaces and core CPU logic >>>target/avr: Add instruction helpers >>>target/avr: Add instruction decoding >>>target/avr: Add instruction translation >>>target/avr: Add example board configuration >>>target/avr: Register AVR support with the rest of QEMU, the build >>> system, and the MAINTAINERS file >>>target/avr: Add tests >>> >>> Sarah Harris (1): >>>target/avr: Add limited support for USART and 16 bit timer peripherals >>> >> >> Overall architecture patches look good, but I'd like some more time to >> review the hardware patches. Unfortunately I won't have time until November. >> There was a chat on IRC about your series, >> > I don't see the reason why do you initiate IRC communication on this topic, > if we have the mailing list for discussing such important issues as > introducing a new target (that should be definitely visible to all > participants). IRC is often a good way of quickly discussing something when someone is about (often as a tangent from another discussion). I don't think there is anything wrong with that as long as it's followed up on the mailing list. > >> I suggested Richard we could merge patches 1-4 and 7. They are almost >> sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS >> ones). Which is was ;-) -- Alex Bennée
Re: [Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
On Friday, October 11, 2019, Philippe Mathieu-Daudé wrote: > Hi Michael, > > On 9/2/19 4:01 PM, Michael Rolnik wrote: > >> This series of patches adds 8bit AVR cores to QEMU. >> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully >> tested yet. >> However I was able to execute simple code with functions. e.g fibonacci >> calculation. >> This series of patches include a non real, sample board. >> No fuses support yet. PC is set to 0 at reset. >> >> the patches include the following >> 1. just a basic 8bit AVR CPU, without instruction decoding or translation >> 2. CPU features which allow define the following 8bit AVR cores >> avr1 >> avr2 avr25 >> avr3 avr31 avr35 >> avr4 >> avr5 avr51 >> avr6 >> xmega2 xmega4 xmega5 xmega6 xmega7 >> 3. a definition of sample machine with SRAM, FLASH and CPU which allows >> to execute simple code >> 4. encoding for all AVR instructions >> 5. interrupt handling >> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions >> 7. a decoder which given an opcode decides what istruction it is >> 8. translation of AVR instruction into TCG >> 9. all features together >> >> [..] > >> Michael Rolnik (7): >>target/avr: Add outward facing interfaces and core CPU logic >>target/avr: Add instruction helpers >>target/avr: Add instruction decoding >>target/avr: Add instruction translation >>target/avr: Add example board configuration >>target/avr: Register AVR support with the rest of QEMU, the build >> system, and the MAINTAINERS file >>target/avr: Add tests >> >> Sarah Harris (1): >>target/avr: Add limited support for USART and 16 bit timer peripherals >> > > Overall architecture patches look good, but I'd like some more time to > review the hardware patches. Unfortunately I won't have time until November. > There was a chat on IRC about your series, > > I don't see the reason why do you initiate IRC communication on this topic, if we have the mailing list for discussing such important issues as introducing a new target (that should be definitely visible to all participants). Thanks, Aleksandar > > > > I suggested Richard we could merge patches 1-4 and 7. They are almost > sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS > ones). > > Regards, > > Phil. > >
Re: [PATCH v30 0/8] QEMU AVR 8 bit cores
On 9/2/19 4:01 PM, Michael Rolnik wrote: Michael Rolnik (7): target/avr: Add outward facing interfaces and core CPU logic target/avr: Add instruction helpers target/avr: Add instruction decoding target/avr: Add instruction translation [...]> target/avr/Makefile.objs | 33 + target/avr/cpu-param.h | 37 + target/avr/cpu-qom.h | 54 + target/avr/cpu.c | 576 ++ target/avr/cpu.h | 254 +++ target/avr/gdbstub.c | 85 + target/avr/helper.c | 354 target/avr/helper.h | 29 + target/avr/insn.decode | 175 ++ target/avr/machine.c | 121 ++ target/avr/translate.c | 2888 ++ Hmmm I'm wondering, since the 32-bit arch is different, shouldn't we add this under target/avr8/ ?
Re: [PATCH v30 0/8] QEMU AVR 8 bit cores
Hi Michael, On 9/2/19 4:01 PM, Michael Rolnik wrote: This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support yet. PC is set to 0 at reset. the patches include the following 1. just a basic 8bit AVR CPU, without instruction decoding or translation 2. CPU features which allow define the following 8bit AVR cores avr1 avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 xmega2 xmega4 xmega5 xmega6 xmega7 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code 4. encoding for all AVR instructions 5. interrupt handling 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions 7. a decoder which given an opcode decides what istruction it is 8. translation of AVR instruction into TCG 9. all features together [..] Michael Rolnik (7): target/avr: Add outward facing interfaces and core CPU logic target/avr: Add instruction helpers target/avr: Add instruction decoding target/avr: Add instruction translation target/avr: Add example board configuration target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file target/avr: Add tests Sarah Harris (1): target/avr: Add limited support for USART and 16 bit timer peripherals Overall architecture patches look good, but I'd like some more time to review the hardware patches. Unfortunately I won't have time until November. There was a chat on IRC about your series, I suggested Richard we could merge patches 1-4 and 7. They are almost sufficient to run the qemu-avr-tests gdbstub tests (but not the FreeRTOS ones). Regards, Phil.
[Qemu-devel] [PATCH v30 0/8] QEMU AVR 8 bit cores
This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support yet. PC is set to 0 at reset. the patches include the following 1. just a basic 8bit AVR CPU, without instruction decoding or translation 2. CPU features which allow define the following 8bit AVR cores avr1 avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 xmega2 xmega4 xmega5 xmega6 xmega7 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code 4. encoding for all AVR instructions 5. interrupt handling 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions 7. a decoder which given an opcode decides what istruction it is 8. translation of AVR instruction into TCG 9. all features together changes since v3 1. rampD/X/Y/Z registers are encoded as 0x00ff (instead of 0x00ff) for faster address manipulaton 2. ffs changed to ctz32 3. duplicate code removed at avr_cpu_do_interrupt 4. using andc instead of not + and 5. fixing V flag calculation in varios instructions 6. freeing local variables in PUSH 7. tcg_const_local_i32 -> tcg_const_i32 8. using sextract32 instead of my implementation 9. fixing BLD instruction 10.xor(r) instead of 0xff - r at COM 11.fixing MULS/MULSU not to modify inputs' content 12.using SUB for NEG 13.fixing tcg_gen_qemu_ld/st call in XCH changes since v4 1. target is now defined as big endian in order to optimize push_ret/pop_ret 2. all style warnings are fixed 3. adding cpu_set/get_sreg functions 4. simplifying gen_goto_tb as there is no real paging 5. env->pc -> env->pc_w 6. making flag dump more compact 7. more spacing 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX 9. removing avr_set_feature 10. SPL/SPH set bug fix 11. switching stb_phys to cpu_stb_data 12. cleaning up avr_decode 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm) 14. saving CPU features (savevm) changes since v5 1. BLD bug fix 2. decoder generator is added chages since v6 1. using cpu_get_sreg/cpu_set_sreg in avr_cpu_gdb_read_register/avr_cpu_gdb_write_register 2. configure the target as little endian because otherwise GDB does not work 3. fixing and testing gen_push_ret/gen_pop_ret changes since v7 1. folding back v6 2. logging at helper_outb and helper_inb are done for non supported yet registers only 3. MAINTAINERS updated changes since v8 1. removing hw/avr from hw/Makefile.obj as it should not be built for all 2. making linux compilable 3. testing on a. Mac, Apple LLVM version 7.0.0 b. Ubuntu 12.04, gcc 4.9.2 c. Fedora 23, gcc 5.3.1 4. folding back some patches 5. translation bug fixes for ORI, CPI, XOR instructions 6. propper handling of cpu register writes though memory changes since v9 1. removing forward declarations of static functions 2. disabling debug prints 3. switching to case range instead of if else if ... 4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any device 5. commenst about sample board and sample IO device added 6. sample board description is more descriptive now 7. memory_region_allocate_system_memory is used to create RAM 8. now there are helper_fullrd & helper_fullwr when LD/ST try to access registers changes since v10 1. movig back fullwr & fullrd into the commit where outb and inb were introduced 2. changing tlb_fill function signature 3. adding empty line between functions 4. adding newline on the last line of the file 5. using tb->flags to generae full access ST/LD instructions 6. fixing SBRC bug 7. folding back 10th commit 8. whenever a new file is introduced it's added to Makefile.objs changes since v11 1. updating to v2.7.0-rc 2. removing assignment to env->fullacc from gen_intermediate_code changes since v12 1. fixing spacing 2. fixing get/put_segment functions 3. removing target-avr/machine.h file 4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE 5. comment spelling 6. removing hw/avr/sample_io.c 7. char const* -> const char* 8. proper ram allocation 9. fixing breakpoint functionality. 10.env1 -> env 11.fixing avr_cpu_gdb_write_register & avr_cpu_gdb_read_register functions 12.any cpu is removed 12.feature bits are not saved into vm state changes since v13 1. rebasing to v2.7.0-rc1 changes since v14 1. I made self review with git gui tool. (I did not know such a thing exists) 2. removing all double/tripple spaces 3. removing comment reference to SampleIO 4. folding back some changes, so there is not deleted lines in my code 5. moving avr configuration, within configure file, before chris changes since v15 1. removing IO registers cache from CPU 2. implementing CBI/SBI as read(helper_inb), modify, write(helper_outb) 3. implementing CBIC/SBIC as read(helper_inb), check, branch 4. adding missing tcg_temp_free_i32 for tcg_const_i32 changes since v16 1.
