Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Monday, December 2, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> +
> +/* update status register */
> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
> +gen_ZNSf(R);
> +tcg_gen_mov_tl(Rd, R);
> +
>
My email client drives me crazy, all lines from the above segment should be
consecutive, without any empty lines in between. If you see empty lines,
that is because of my email client.
> The idea is to distinguish visually better the portions for updating
> status register from the central part of the operation (usually marked by
> "/* op */" comment. The code also gets more compact, which looks like a
> good thing too.
>
> Aleksandar
>
>
>> Regards,
>> Michael Rolnik
>>
>> On Sun, Dec 1, 2019 at 1:11 AM Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>> On Saturday, November 30, 2019, Michael Rolnik
>>> wrote:
>>>
Hi Aleksandar.
thanks for pointing that out I was not aware of that.
I can fix it.
>>> Hey, Michael,
>>>
>>> Please take alook at this:
>>>
>>> https://en.m.wikipedia.org/wiki/ATtiny_microcontroller_comparison_chart
>>>
>>> It looks that all cases of AVR 16-gpr-registers cores belong to the
>>> group "avrtiny10", that actually you may want to add to your solution.
>>> Just a hint.
>>>
>>> Best regards,
>>> Aleksandar
>>>
>>>
>>>
>>> Regards,
Michael Rolnik
On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Saturday, November 30, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Wednesday, November 27, 2019, Michael Rolnik
>> wrote:
>>
>> +
>>> +
>>> +/*
>>> + * Performs the logical AND between the contents of register Rd
>>> and register
>>> + * Rr and places the result in the destination register Rd.
>>> + */
>>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>>> +{
>>> +TCGv Rd = cpu_r[a->rd];
>>> +TCGv Rr = cpu_r[a->rr];
>>> +TCGv R = tcg_temp_new_i32();
>>> +
>>> +/* op */
>>> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>>> +
>>> +/* Vf */
>>> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>>> +
>>> +/* Zf */
>>> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0
>>> */
>>> +
>>> +gen_ZNSf(R);
>>> +
>>> +/* R */
>>> +tcg_gen_mov_tl(Rd, R);
>>> +
>>> +tcg_temp_free_i32(R);
>>> +
>>> +return true;
>>> +}
>>> +
>>> +
>>>
>>
>> According to specs:
>>
>> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-
>> 8-bit-avr-microcontrollers-attiny102-attiny104_datasheet.pdf
>>
>> ... the chips in question have cores with 16 GPRs (that correspond to
>> GPRs R16-R31 of more common AVR cores with 32 GPRs).
>>
>>
> There are more examples;
>
> http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-
> avr-8-bit-microcontroller-attiny4-attiny5-attiny9-
> attiny10_datasheet.pdf
>
> Also ATtiny20, ATtiny40.
>
> How do you handle such cores?
>>
>> I don't see here anything preventing usage of all 32 GPRs, resulting,
>> of course, in an inaccurate emulation.
>>
>> Thanks,
>> Aleksandar
>>
>
--
Best Regards,
Michael Rolnik
>>>
>>
>> --
>> Best Regards,
>> Michael Rolnik
>>
>
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Monday, December 2, 2019, Michael Rolnik wrote:
> Aleksandar.
>
> I could not find what happens if an instruction with unsupported registers
> is executed. So, I am leaving this tiny core for later.
>
>
No problem with me. You already have instruction support for a rich variety
of cores. These can certainly added it in future.
May I suggest, then, a following cosmetic change: In order for a reader to
get a brtter "first glance" feeling for emulations of ALL instructions that
involve updating status register, I suggest that the code blocks like this
one:
+
+/* Vf */
+tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+
+/* Zf */
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+
+gen_ZNSf(R);
+
+/* R */
+tcg_gen_mov_tl(Rd, R);
+
be replaced with this one:
+
+/* update status register */
+tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+gen_ZNSf(R);
+tcg_gen_mov_tl(Rd, R);
+
The idea is to distinguish visually better the portions for updating status
register from the central part of the operation (usually marked by "/* op
*/" comment. The code also gets more compact, which looks like a good thing
too.
Aleksandar
> Regards,
> Michael Rolnik
>
> On Sun, Dec 1, 2019 at 1:11 AM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Saturday, November 30, 2019, Michael Rolnik wrote:
>>
>>> Hi Aleksandar.
>>>
>>> thanks for pointing that out I was not aware of that.
>>> I can fix it.
>>>
>>>
>> Hey, Michael,
>>
>> Please take alook at this:
>>
>> https://en.m.wikipedia.org/wiki/ATtiny_microcontroller_comparison_chart
>>
>> It looks that all cases of AVR 16-gpr-registers cores belong to the group
>> "avrtiny10", that actually you may want to add to your solution. Just a
>> hint.
>>
>> Best regards,
>> Aleksandar
>>
>>
>>
>> Regards,
>>> Michael Rolnik
>>>
>>> On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
>>> aleksandar.m.m...@gmail.com> wrote:
>>>
On Saturday, November 30, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Wednesday, November 27, 2019, Michael Rolnik
> wrote:
>
> +
>> +
>> +/*
>> + * Performs the logical AND between the contents of register Rd and
>> register
>> + * Rr and places the result in the destination register Rd.
>> + */
>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>> +{
>> +TCGv Rd = cpu_r[a->rd];
>> +TCGv Rr = cpu_r[a->rr];
>> +TCGv R = tcg_temp_new_i32();
>> +
>> +/* op */
>> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>> +
>> +/* Vf */
>> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>> +
>> +/* Zf */
>> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0
>> */
>> +
>> +gen_ZNSf(R);
>> +
>> +/* R */
>> +tcg_gen_mov_tl(Rd, R);
>> +
>> +tcg_temp_free_i32(R);
>> +
>> +return true;
>> +}
>> +
>> +
>>
>
> According to specs:
>
> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-
> microcontrollers-attiny102-attiny104_datasheet.pdf
>
> ... the chips in question have cores with 16 GPRs (that correspond to
> GPRs R16-R31 of more common AVR cores with 32 GPRs).
>
>
There are more examples;
http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-
microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
Also ATtiny20, ATtiny40.
How do you handle such cores?
>
> I don't see here anything preventing usage of all 32 GPRs, resulting,
> of course, in an inaccurate emulation.
>
> Thanks,
> Aleksandar
>
>>>
>>> --
>>> Best Regards,
>>> Michael Rolnik
>>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
Aleksandar.
I could not find what happens if an instruction with unsupported registers
is executed. So, I am leaving this tiny core for later.
Regards,
Michael Rolnik
On Sun, Dec 1, 2019 at 1:11 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Saturday, November 30, 2019, Michael Rolnik wrote:
>
>> Hi Aleksandar.
>>
>> thanks for pointing that out I was not aware of that.
>> I can fix it.
>>
>>
> Hey, Michael,
>
> Please take alook at this:
>
> https://en.m.wikipedia.org/wiki/ATtiny_microcontroller_comparison_chart
>
> It looks that all cases of AVR 16-gpr-registers cores belong to the group
> "avrtiny10",
> that actually you may want to add to your solution. Just a hint.
>
> Best regards,
> Aleksandar
>
>
>
> Regards,
>> Michael Rolnik
>>
>> On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>> On Saturday, November 30, 2019, Aleksandar Markovic <
>>> aleksandar.m.m...@gmail.com> wrote:
>>>
On Wednesday, November 27, 2019, Michael Rolnik
wrote:
+
> +
> +/*
> + * Performs the logical AND between the contents of register Rd and
> register
> + * Rr and places the result in the destination register Rd.
> + */
> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
> +{
> +TCGv Rd = cpu_r[a->rd];
> +TCGv Rr = cpu_r[a->rr];
> +TCGv R = tcg_temp_new_i32();
> +
> +/* op */
> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
> +
> +/* Vf */
> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
> +
> +/* Zf */
> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
> +
> +gen_ZNSf(R);
> +
> +/* R */
> +tcg_gen_mov_tl(Rd, R);
> +
> +tcg_temp_free_i32(R);
> +
> +return true;
> +}
> +
> +
>
According to specs:
http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-microcontrollers-attiny102-attiny104_datasheet.pdf
... the chips in question have cores with 16 GPRs (that correspond to
GPRs R16-R31 of more common AVR cores with 32 GPRs).
>>> There are more examples;
>>>
>>>
>>> http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
>>>
>>> Also ATtiny20, ATtiny40.
>>>
>>> How do you handle such cores?
I don't see here anything preventing usage of all 32 GPRs, resulting,
of course, in an inaccurate emulation.
Thanks,
Aleksandar
>>>
>>
>> --
>> Best Regards,
>> Michael Rolnik
>>
>
--
Best Regards,
Michael Rolnik
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Saturday, November 30, 2019, Michael Rolnik wrote:
> Hi Aleksandar.
>
> thanks for pointing that out I was not aware of that.
> I can fix it.
>
>
Hey, Michael,
Please take alook at this:
https://en.m.wikipedia.org/wiki/ATtiny_microcontroller_comparison_chart
It looks that all cases of AVR 16-gpr-registers cores belong to the
group "avrtiny10",
that actually you may want to add to your solution. Just a hint.
Best regards,
Aleksandar
Regards,
> Michael Rolnik
>
> On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Saturday, November 30, 2019, Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>> On Wednesday, November 27, 2019, Michael Rolnik
>>> wrote:
>>>
>>> +
+
+/*
+ * Performs the logical AND between the contents of register Rd and
register
+ * Rr and places the result in the destination register Rd.
+ */
+static bool trans_AND(DisasContext *ctx, arg_AND *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+/* op */
+tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
+
+/* Vf */
+tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+
+/* Zf */
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+
+gen_ZNSf(R);
+
+/* R */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+
>>>
>>> According to specs:
>>>
>>> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-
>>> microcontrollers-attiny102-attiny104_datasheet.pdf
>>>
>>> ... the chips in question have cores with 16 GPRs (that correspond to
>>> GPRs R16-R31 of more common AVR cores with 32 GPRs).
>>>
>>>
>> There are more examples;
>>
>> http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-
>> microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
>>
>> Also ATtiny20, ATtiny40.
>>
>> How do you handle such cores?
>>>
>>> I don't see here anything preventing usage of all 32 GPRs, resulting, of
>>> course, in an inaccurate emulation.
>>>
>>> Thanks,
>>> Aleksandar
>>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
Hi Aleksandar.
thanks for pointing that out I was not aware of that.
I can fix it.
Regards,
Michael Rolnik
On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Saturday, November 30, 2019, Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Wednesday, November 27, 2019, Michael Rolnik
>> wrote:
>>
>> +
>>> +
>>> +/*
>>> + * Performs the logical AND between the contents of register Rd and
>>> register
>>> + * Rr and places the result in the destination register Rd.
>>> + */
>>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>>> +{
>>> +TCGv Rd = cpu_r[a->rd];
>>> +TCGv Rr = cpu_r[a->rr];
>>> +TCGv R = tcg_temp_new_i32();
>>> +
>>> +/* op */
>>> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>>> +
>>> +/* Vf */
>>> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>>> +
>>> +/* Zf */
>>> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
>>> +
>>> +gen_ZNSf(R);
>>> +
>>> +/* R */
>>> +tcg_gen_mov_tl(Rd, R);
>>> +
>>> +tcg_temp_free_i32(R);
>>> +
>>> +return true;
>>> +}
>>> +
>>> +
>>>
>>
>> According to specs:
>>
>>
>> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-microcontrollers-attiny102-attiny104_datasheet.pdf
>>
>> ... the chips in question have cores with 16 GPRs (that correspond to
>> GPRs R16-R31 of more common AVR cores with 32 GPRs).
>>
>>
> There are more examples;
>
>
> http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
>
> Also ATtiny20, ATtiny40.
>
> How do you handle such cores?
>>
>> I don't see here anything preventing usage of all 32 GPRs, resulting, of
>> course, in an inaccurate emulation.
>>
>> Thanks,
>> Aleksandar
>>
>
--
Best Regards,
Michael Rolnik
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Saturday, November 30, 2019, Michael Rolnik wrote:
> Hi Aleksandar.
>
> thanks for pointing that out I was not aware of that.
> I can fix it.
>
That'd be great!
Thanks,
Aleksandar
>
> Regards,
> Michael Rolnik
>
> On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Saturday, November 30, 2019, Aleksandar Markovic <
>> aleksandar.m.m...@gmail.com> wrote:
>>
>>>
>>>
>>> On Wednesday, November 27, 2019, Michael Rolnik
>>> wrote:
>>>
>>> +
+
+/*
+ * Performs the logical AND between the contents of register Rd and
register
+ * Rr and places the result in the destination register Rd.
+ */
+static bool trans_AND(DisasContext *ctx, arg_AND *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+/* op */
+tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
+
+/* Vf */
+tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
+
+/* Zf */
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+
+gen_ZNSf(R);
+
+/* R */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+
>>>
>>> According to specs:
>>>
>>> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-
>>> microcontrollers-attiny102-attiny104_datasheet.pdf
>>>
>>> ... the chips in question have cores with 16 GPRs (that correspond to
>>> GPRs R16-R31 of more common AVR cores with 32 GPRs).
>>>
>>>
>> There are more examples;
>>
>> http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-
>> microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
>>
>> Also ATtiny20, ATtiny40.
>>
>> How do you handle such cores?
>>>
>>> I don't see here anything preventing usage of all 32 GPRs, resulting, of
>>> course, in an inaccurate emulation.
>>>
>>> Thanks,
>>> Aleksandar
>>>
>>
>
> --
> Best Regards,
> Michael Rolnik
>
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Saturday, November 30, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Wednesday, November 27, 2019, Michael Rolnik wrote:
>
> +
>> +
>> +/*
>> + * Performs the logical AND between the contents of register Rd and
>> register
>> + * Rr and places the result in the destination register Rd.
>> + */
>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>> +{
>> +TCGv Rd = cpu_r[a->rd];
>> +TCGv Rr = cpu_r[a->rr];
>> +TCGv R = tcg_temp_new_i32();
>> +
>> +/* op */
>> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>> +
>> +/* Vf */
>> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>> +
>> +/* Zf */
>> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
>> +
>> +gen_ZNSf(R);
>> +
>> +/* R */
>> +tcg_gen_mov_tl(Rd, R);
>> +
>> +tcg_temp_free_i32(R);
>> +
>> +return true;
>> +}
>> +
>> +
>>
>
> According to specs:
>
> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-
> microcontrollers-attiny102-attiny104_datasheet.pdf
>
> ... the chips in question have cores with 16 GPRs (that correspond to GPRs
> R16-R31 of more common AVR cores with 32 GPRs).
>
>
There are more examples;
http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
Also ATtiny20, ATtiny40.
How do you handle such cores?
>
> I don't see here anything preventing usage of all 32 GPRs, resulting, of
> course, in an inaccurate emulation.
>
> Thanks,
> Aleksandar
>
Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
On Wednesday, November 27, 2019, Michael Rolnik wrote:
+
> +
> +/*
> + * Performs the logical AND between the contents of register Rd and
> register
> + * Rr and places the result in the destination register Rd.
> + */
> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
> +{
> +TCGv Rd = cpu_r[a->rd];
> +TCGv Rr = cpu_r[a->rr];
> +TCGv R = tcg_temp_new_i32();
> +
> +/* op */
> +tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
> +
> +/* Vf */
> +tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
> +
> +/* Zf */
> +tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
> +
> +gen_ZNSf(R);
> +
> +/* R */
> +tcg_gen_mov_tl(Rd, R);
> +
> +tcg_temp_free_i32(R);
> +
> +return true;
> +}
> +
> +
>
According to specs:
http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-microcontrollers-attiny102-attiny104_datasheet.pdf
... the chips in question have cores with 16 GPRs (that correspond to GPRs
R16-R31 of more common AVR cores with 32 GPRs).
How do you handle such cores?
I don't see here anything preventing usage of all 32 GPRs, resulting, of
course, in an inaccurate emulation.
Thanks,
Aleksandar
[PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 822 +
1 file changed, 822 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index fad074b88a..76bfa651b6 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -143,3 +143,825 @@ static bool avr_have_feature(DisasContext *ctx, int
feature)
static bool decode_insn(DisasContext *ctx, uint16_t insn);
#include "decode_insn.inc.c"
+
+static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+TCGv t3 = tcg_temp_new_i32();
+
+tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */
+tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */
+tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */
+tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */
+tcg_gen_or_tl(t1, t1, t3);
+
+tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */
+tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+
+/* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R = (Rd ^ R) & ~(Rd ^ Rr) */
+tcg_gen_xor_tl(t1, Rd, R);
+tcg_gen_xor_tl(t2, Rd, Rr);
+tcg_gen_andc_tl(t1, t1, t2);
+
+tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+TCGv t3 = tcg_temp_new_i32();
+
+/* Cf & Hf */
+tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */
+tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */
+tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */
+tcg_gen_and_tl(t3, t3, R);
+tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
+tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */
+tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */
+tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1);
+
+tcg_temp_free_i32(t3);
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr)
+{
+TCGv t1 = tcg_temp_new_i32();
+TCGv t2 = tcg_temp_new_i32();
+
+/* Vf */
+/* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R = (Rd ^ R) & (Rd ^ R) */
+tcg_gen_xor_tl(t1, Rd, R);
+tcg_gen_xor_tl(t2, Rd, Rr);
+tcg_gen_and_tl(t1, t1, t2);
+tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */
+
+tcg_temp_free_i32(t2);
+tcg_temp_free_i32(t1);
+}
+
+
+static void gen_NSf(TCGv R)
+{
+tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+
+static void gen_ZNSf(TCGv R)
+{
+tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
+tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */
+tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */
+}
+
+
+/*
+ * Adds two registers without the C Flag and places the result in the
+ * destination register Rd.
+ */
+static bool trans_ADD(DisasContext *ctx, arg_ADD *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+/* op */
+tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */
+tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+gen_add_CHf(R, Rd, Rr);
+gen_add_Vf(R, Rd, Rr);
+gen_ZNSf(R);
+
+/* R */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+
+/*
+ * Adds two registers and the contents of the C Flag and places the result in
+ * the destination register Rd.
+ */
+static bool trans_ADC(DisasContext *ctx, arg_ADC *a)
+{
+TCGv Rd = cpu_r[a->rd];
+TCGv Rr = cpu_r[a->rr];
+TCGv R = tcg_temp_new_i32();
+
+/* op */
+tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */
+tcg_gen_add_tl(R, R, cpu_Cf);
+tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */
+
+gen_add_CHf(R, Rd, Rr);
+gen_add_Vf(R, Rd, Rr);
+gen_ZNSf(R);
+
+/* R */
+tcg_gen_mov_tl(Rd, R);
+
+tcg_temp_free_i32(R);
+
+return true;
+}
+
+
+/*
+ * Subtracts an immediate value (0-63) from a register pair and places the
+ * result in the register pair. This instruction operates on the upper four
+ * register pairs, and is well suited for operations on the Pointer Registers.
+ * This instruction is not available in all devices. Refer to the device
+ * specific instruction set summary.
+ */
+static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a)
+{
+if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) {
+return true;
+}
+
+TCGv RdL = cpu_r[a->rd];
+TCGv RdH = cpu_r[a->rd + 1];
+int Imm = (a->imm);
+TCGv R =
